Commit | Line | Data |
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8187a2b7 ZN |
1 | #ifndef _INTEL_RINGBUFFER_H_ |
2 | #define _INTEL_RINGBUFFER_H_ | |
3 | ||
44e895a8 BV |
4 | #include <linux/hashtable.h> |
5 | ||
6 | #define I915_CMD_HASH_ORDER 9 | |
7 | ||
633cf8f5 VS |
8 | /* |
9 | * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use" | |
10 | * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use" | |
11 | * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use" | |
12 | * | |
13 | * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same | |
14 | * cacheline, the Head Pointer must not be greater than the Tail | |
15 | * Pointer." | |
16 | */ | |
17 | #define I915_RING_FREE_SPACE 64 | |
18 | ||
8187a2b7 | 19 | struct intel_hw_status_page { |
4225d0f2 | 20 | u32 *page_addr; |
8187a2b7 | 21 | unsigned int gfx_addr; |
05394f39 | 22 | struct drm_i915_gem_object *obj; |
8187a2b7 ZN |
23 | }; |
24 | ||
b7287d80 BW |
25 | #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base)) |
26 | #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val) | |
cae5852d | 27 | |
b7287d80 BW |
28 | #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base)) |
29 | #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val) | |
cae5852d | 30 | |
b7287d80 BW |
31 | #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base)) |
32 | #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val) | |
cae5852d | 33 | |
b7287d80 BW |
34 | #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base)) |
35 | #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val) | |
cae5852d | 36 | |
b7287d80 BW |
37 | #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base)) |
38 | #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val) | |
870e86dd | 39 | |
e9fea574 | 40 | #define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base)) |
9991ae78 | 41 | #define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val) |
e9fea574 | 42 | |
f2f4d82f | 43 | enum intel_ring_hangcheck_action { |
da661464 | 44 | HANGCHECK_IDLE = 0, |
f2f4d82f JN |
45 | HANGCHECK_WAIT, |
46 | HANGCHECK_ACTIVE, | |
47 | HANGCHECK_KICK, | |
48 | HANGCHECK_HUNG, | |
49 | }; | |
ad8beaea | 50 | |
b6b0fac0 MK |
51 | #define HANGCHECK_SCORE_RING_HUNG 31 |
52 | ||
92cab734 | 53 | struct intel_ring_hangcheck { |
50877445 | 54 | u64 acthd; |
92cab734 | 55 | u32 seqno; |
05407ff8 | 56 | int score; |
ad8beaea | 57 | enum intel_ring_hangcheck_action action; |
50877445 | 58 | bool deadlock; |
92cab734 MK |
59 | }; |
60 | ||
8ee14975 OM |
61 | struct intel_ringbuffer { |
62 | struct drm_i915_gem_object *obj; | |
63 | void __iomem *virtual_start; | |
64 | ||
65 | u32 head; | |
66 | u32 tail; | |
67 | int space; | |
68 | int size; | |
69 | int effective_size; | |
70 | ||
71 | /** We track the position of the requests in the ring buffer, and | |
72 | * when each is retired we increment last_retired_head as the GPU | |
73 | * must have finished processing the request and so we know we | |
74 | * can advance the ringbuffer up to that position. | |
75 | * | |
76 | * last_retired_head is set to -1 after the value is consumed so | |
77 | * we can detect new retirements. | |
78 | */ | |
79 | u32 last_retired_head; | |
80 | }; | |
81 | ||
a4872ba6 | 82 | struct intel_engine_cs { |
8187a2b7 | 83 | const char *name; |
9220434a | 84 | enum intel_ring_id { |
96154f2f DV |
85 | RCS = 0x0, |
86 | VCS, | |
87 | BCS, | |
4a3dd19d | 88 | VECS, |
845f74a7 | 89 | VCS2 |
9220434a | 90 | } id; |
845f74a7 | 91 | #define I915_NUM_RINGS 5 |
b1a93306 | 92 | #define LAST_USER_RING (VECS + 1) |
333e9fe9 | 93 | u32 mmio_base; |
8187a2b7 | 94 | struct drm_device *dev; |
8ee14975 | 95 | struct intel_ringbuffer *buffer; |
8187a2b7 | 96 | |
8187a2b7 ZN |
97 | struct intel_hw_status_page status_page; |
98 | ||
c7113cc3 | 99 | unsigned irq_refcount; /* protected by dev_priv->irq_lock */ |
6a848ccb | 100 | u32 irq_enable_mask; /* bitmask to enable ring interrupt */ |
db53a302 | 101 | u32 trace_irq_seqno; |
a4872ba6 OM |
102 | bool __must_check (*irq_get)(struct intel_engine_cs *ring); |
103 | void (*irq_put)(struct intel_engine_cs *ring); | |
8187a2b7 | 104 | |
a4872ba6 | 105 | int (*init)(struct intel_engine_cs *ring); |
8187a2b7 | 106 | |
a4872ba6 | 107 | void (*write_tail)(struct intel_engine_cs *ring, |
297b0c5b | 108 | u32 value); |
a4872ba6 | 109 | int __must_check (*flush)(struct intel_engine_cs *ring, |
b72f3acb CW |
110 | u32 invalidate_domains, |
111 | u32 flush_domains); | |
a4872ba6 | 112 | int (*add_request)(struct intel_engine_cs *ring); |
b2eadbc8 CW |
113 | /* Some chipsets are not quite as coherent as advertised and need |
114 | * an expensive kick to force a true read of the up-to-date seqno. | |
115 | * However, the up-to-date seqno is not always required and the last | |
116 | * seen value is good enough. Note that the seqno will always be | |
117 | * monotonic, even if not coherent. | |
118 | */ | |
a4872ba6 | 119 | u32 (*get_seqno)(struct intel_engine_cs *ring, |
b2eadbc8 | 120 | bool lazy_coherency); |
a4872ba6 | 121 | void (*set_seqno)(struct intel_engine_cs *ring, |
b70ec5bf | 122 | u32 seqno); |
a4872ba6 | 123 | int (*dispatch_execbuffer)(struct intel_engine_cs *ring, |
9bcb144c | 124 | u64 offset, u32 length, |
d7d4eedd CW |
125 | unsigned flags); |
126 | #define I915_DISPATCH_SECURE 0x1 | |
b45305fc | 127 | #define I915_DISPATCH_PINNED 0x2 |
a4872ba6 | 128 | void (*cleanup)(struct intel_engine_cs *ring); |
ebc348b2 BW |
129 | |
130 | struct { | |
131 | u32 sync_seqno[I915_NUM_RINGS-1]; | |
78325f2d | 132 | |
ebc348b2 BW |
133 | struct { |
134 | /* our mbox written by others */ | |
135 | u32 wait[I915_NUM_RINGS]; | |
136 | /* mboxes this ring signals to */ | |
137 | u32 signal[I915_NUM_RINGS]; | |
138 | } mbox; | |
78325f2d BW |
139 | |
140 | /* AKA wait() */ | |
a4872ba6 OM |
141 | int (*sync_to)(struct intel_engine_cs *ring, |
142 | struct intel_engine_cs *to, | |
78325f2d | 143 | u32 seqno); |
a4872ba6 | 144 | int (*signal)(struct intel_engine_cs *signaller, |
024a43e1 BW |
145 | /* num_dwords needed by caller */ |
146 | unsigned int num_dwords); | |
ebc348b2 | 147 | } semaphore; |
ad776f8b | 148 | |
8187a2b7 ZN |
149 | /** |
150 | * List of objects currently involved in rendering from the | |
151 | * ringbuffer. | |
152 | * | |
153 | * Includes buffers having the contents of their GPU caches | |
154 | * flushed, not necessarily primitives. last_rendering_seqno | |
155 | * represents when the rendering involved will be completed. | |
156 | * | |
157 | * A reference is held on the buffer while on this list. | |
158 | */ | |
159 | struct list_head active_list; | |
160 | ||
161 | /** | |
162 | * List of breadcrumbs associated with GPU requests currently | |
163 | * outstanding. | |
164 | */ | |
165 | struct list_head request_list; | |
166 | ||
a56ba56c CW |
167 | /** |
168 | * Do we have some not yet emitted requests outstanding? | |
169 | */ | |
3c0e234c | 170 | struct drm_i915_gem_request *preallocated_lazy_request; |
1823521d | 171 | u32 outstanding_lazy_seqno; |
cc889e0f | 172 | bool gpu_caches_dirty; |
c65355bb | 173 | bool fbc_dirty; |
a56ba56c | 174 | |
8187a2b7 | 175 | wait_queue_head_t irq_queue; |
8d19215b | 176 | |
273497e5 OM |
177 | struct intel_context *default_context; |
178 | struct intel_context *last_context; | |
40521054 | 179 | |
92cab734 MK |
180 | struct intel_ring_hangcheck hangcheck; |
181 | ||
0d1aacac CW |
182 | struct { |
183 | struct drm_i915_gem_object *obj; | |
184 | u32 gtt_offset; | |
185 | volatile u32 *cpu_page; | |
186 | } scratch; | |
351e3db2 | 187 | |
44e895a8 BV |
188 | bool needs_cmd_parser; |
189 | ||
351e3db2 | 190 | /* |
44e895a8 | 191 | * Table of commands the command parser needs to know about |
351e3db2 BV |
192 | * for this ring. |
193 | */ | |
44e895a8 | 194 | DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER); |
351e3db2 BV |
195 | |
196 | /* | |
197 | * Table of registers allowed in commands that read/write registers. | |
198 | */ | |
199 | const u32 *reg_table; | |
200 | int reg_count; | |
201 | ||
202 | /* | |
203 | * Table of registers allowed in commands that read/write registers, but | |
204 | * only from the DRM master. | |
205 | */ | |
206 | const u32 *master_reg_table; | |
207 | int master_reg_count; | |
208 | ||
209 | /* | |
210 | * Returns the bitmask for the length field of the specified command. | |
211 | * Return 0 for an unrecognized/invalid command. | |
212 | * | |
213 | * If the command parser finds an entry for a command in the ring's | |
214 | * cmd_tables, it gets the command's length based on the table entry. | |
215 | * If not, it calls this function to determine the per-ring length field | |
216 | * encoding for the command (i.e. certain opcode ranges use certain bits | |
217 | * to encode the command length in the header). | |
218 | */ | |
219 | u32 (*get_cmd_length_mask)(u32 cmd_header); | |
8187a2b7 ZN |
220 | }; |
221 | ||
b4519513 | 222 | static inline bool |
a4872ba6 | 223 | intel_ring_initialized(struct intel_engine_cs *ring) |
b4519513 | 224 | { |
ee1b1e5e | 225 | return ring->buffer && ring->buffer->obj; |
b4519513 CW |
226 | } |
227 | ||
96154f2f | 228 | static inline unsigned |
a4872ba6 | 229 | intel_ring_flag(struct intel_engine_cs *ring) |
96154f2f DV |
230 | { |
231 | return 1 << ring->id; | |
232 | } | |
233 | ||
1ec14ad3 | 234 | static inline u32 |
a4872ba6 OM |
235 | intel_ring_sync_index(struct intel_engine_cs *ring, |
236 | struct intel_engine_cs *other) | |
1ec14ad3 CW |
237 | { |
238 | int idx; | |
239 | ||
240 | /* | |
241 | * cs -> 0 = vcs, 1 = bcs | |
242 | * vcs -> 0 = bcs, 1 = cs, | |
243 | * bcs -> 0 = cs, 1 = vcs. | |
244 | */ | |
245 | ||
246 | idx = (other - ring) - 1; | |
247 | if (idx < 0) | |
248 | idx += I915_NUM_RINGS; | |
249 | ||
250 | return idx; | |
251 | } | |
252 | ||
8187a2b7 | 253 | static inline u32 |
a4872ba6 | 254 | intel_read_status_page(struct intel_engine_cs *ring, |
78501eac | 255 | int reg) |
8187a2b7 | 256 | { |
4225d0f2 DV |
257 | /* Ensure that the compiler doesn't optimize away the load. */ |
258 | barrier(); | |
259 | return ring->status_page.page_addr[reg]; | |
8187a2b7 ZN |
260 | } |
261 | ||
b70ec5bf | 262 | static inline void |
a4872ba6 | 263 | intel_write_status_page(struct intel_engine_cs *ring, |
b70ec5bf MK |
264 | int reg, u32 value) |
265 | { | |
266 | ring->status_page.page_addr[reg] = value; | |
267 | } | |
268 | ||
311bd68e CW |
269 | /** |
270 | * Reads a dword out of the status page, which is written to from the command | |
271 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or | |
272 | * MI_STORE_DATA_IMM. | |
273 | * | |
274 | * The following dwords have a reserved meaning: | |
275 | * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. | |
276 | * 0x04: ring 0 head pointer | |
277 | * 0x05: ring 1 head pointer (915-class) | |
278 | * 0x06: ring 2 head pointer (915-class) | |
279 | * 0x10-0x1b: Context status DWords (GM45) | |
280 | * 0x1f: Last written status offset. (GM45) | |
281 | * | |
282 | * The area from dword 0x20 to 0x3ff is available for driver usage. | |
283 | */ | |
311bd68e | 284 | #define I915_GEM_HWS_INDEX 0x20 |
9a289771 JB |
285 | #define I915_GEM_HWS_SCRATCH_INDEX 0x30 |
286 | #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT) | |
311bd68e | 287 | |
a4872ba6 OM |
288 | void intel_stop_ring_buffer(struct intel_engine_cs *ring); |
289 | void intel_cleanup_ring_buffer(struct intel_engine_cs *ring); | |
96f298aa | 290 | |
a4872ba6 OM |
291 | int __must_check intel_ring_begin(struct intel_engine_cs *ring, int n); |
292 | int __must_check intel_ring_cacheline_align(struct intel_engine_cs *ring); | |
293 | static inline void intel_ring_emit(struct intel_engine_cs *ring, | |
78501eac | 294 | u32 data) |
e898cd22 | 295 | { |
93b0a4e0 OM |
296 | struct intel_ringbuffer *ringbuf = ring->buffer; |
297 | iowrite32(data, ringbuf->virtual_start + ringbuf->tail); | |
298 | ringbuf->tail += 4; | |
e898cd22 | 299 | } |
a4872ba6 | 300 | static inline void intel_ring_advance(struct intel_engine_cs *ring) |
09246732 | 301 | { |
93b0a4e0 OM |
302 | struct intel_ringbuffer *ringbuf = ring->buffer; |
303 | ringbuf->tail &= ringbuf->size - 1; | |
09246732 | 304 | } |
a4872ba6 | 305 | void __intel_ring_advance(struct intel_engine_cs *ring); |
09246732 | 306 | |
a4872ba6 OM |
307 | int __must_check intel_ring_idle(struct intel_engine_cs *ring); |
308 | void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno); | |
309 | int intel_ring_flush_all_caches(struct intel_engine_cs *ring); | |
310 | int intel_ring_invalidate_all_caches(struct intel_engine_cs *ring); | |
8187a2b7 | 311 | |
5c1143bb XH |
312 | int intel_init_render_ring_buffer(struct drm_device *dev); |
313 | int intel_init_bsd_ring_buffer(struct drm_device *dev); | |
845f74a7 | 314 | int intel_init_bsd2_ring_buffer(struct drm_device *dev); |
549f7365 | 315 | int intel_init_blt_ring_buffer(struct drm_device *dev); |
9a8a2213 | 316 | int intel_init_vebox_ring_buffer(struct drm_device *dev); |
8187a2b7 | 317 | |
a4872ba6 OM |
318 | u64 intel_ring_get_active_head(struct intel_engine_cs *ring); |
319 | void intel_ring_setup_status_page(struct intel_engine_cs *ring); | |
79f321b7 | 320 | |
a4872ba6 | 321 | static inline u32 intel_ring_get_tail(struct intel_engine_cs *ring) |
a71d8d94 | 322 | { |
ee1b1e5e | 323 | return ring->buffer->tail; |
a71d8d94 CW |
324 | } |
325 | ||
a4872ba6 | 326 | static inline u32 intel_ring_get_seqno(struct intel_engine_cs *ring) |
9d773091 | 327 | { |
1823521d CW |
328 | BUG_ON(ring->outstanding_lazy_seqno == 0); |
329 | return ring->outstanding_lazy_seqno; | |
9d773091 CW |
330 | } |
331 | ||
a4872ba6 | 332 | static inline void i915_trace_irq_get(struct intel_engine_cs *ring, u32 seqno) |
db53a302 CW |
333 | { |
334 | if (ring->trace_irq_seqno == 0 && ring->irq_get(ring)) | |
335 | ring->trace_irq_seqno = seqno; | |
336 | } | |
337 | ||
e8616b6c CW |
338 | /* DRI warts */ |
339 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size); | |
340 | ||
8187a2b7 | 341 | #endif /* _INTEL_RINGBUFFER_H_ */ |