Commit | Line | Data |
---|---|---|
8187a2b7 ZN |
1 | #ifndef _INTEL_RINGBUFFER_H_ |
2 | #define _INTEL_RINGBUFFER_H_ | |
3 | ||
44e895a8 | 4 | #include <linux/hashtable.h> |
06fbca71 | 5 | #include "i915_gem_batch_pool.h" |
dcff85c8 | 6 | #include "i915_gem_request.h" |
44e895a8 BV |
7 | |
8 | #define I915_CMD_HASH_ORDER 9 | |
9 | ||
4712274c OM |
10 | /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill, |
11 | * but keeps the logic simple. Indeed, the whole purpose of this macro is just | |
12 | * to give some inclination as to some of the magic values used in the various | |
13 | * workarounds! | |
14 | */ | |
15 | #define CACHELINE_BYTES 64 | |
17ee950d | 16 | #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t)) |
4712274c | 17 | |
633cf8f5 VS |
18 | /* |
19 | * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use" | |
20 | * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use" | |
21 | * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use" | |
22 | * | |
23 | * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same | |
24 | * cacheline, the Head Pointer must not be greater than the Tail | |
25 | * Pointer." | |
26 | */ | |
27 | #define I915_RING_FREE_SPACE 64 | |
28 | ||
57e88531 CW |
29 | struct intel_hw_status_page { |
30 | struct i915_vma *vma; | |
31 | u32 *page_addr; | |
32 | u32 ggtt_offset; | |
8187a2b7 ZN |
33 | }; |
34 | ||
bbdc070a DG |
35 | #define I915_READ_TAIL(engine) I915_READ(RING_TAIL((engine)->mmio_base)) |
36 | #define I915_WRITE_TAIL(engine, val) I915_WRITE(RING_TAIL((engine)->mmio_base), val) | |
cae5852d | 37 | |
bbdc070a DG |
38 | #define I915_READ_START(engine) I915_READ(RING_START((engine)->mmio_base)) |
39 | #define I915_WRITE_START(engine, val) I915_WRITE(RING_START((engine)->mmio_base), val) | |
cae5852d | 40 | |
bbdc070a DG |
41 | #define I915_READ_HEAD(engine) I915_READ(RING_HEAD((engine)->mmio_base)) |
42 | #define I915_WRITE_HEAD(engine, val) I915_WRITE(RING_HEAD((engine)->mmio_base), val) | |
cae5852d | 43 | |
bbdc070a DG |
44 | #define I915_READ_CTL(engine) I915_READ(RING_CTL((engine)->mmio_base)) |
45 | #define I915_WRITE_CTL(engine, val) I915_WRITE(RING_CTL((engine)->mmio_base), val) | |
cae5852d | 46 | |
bbdc070a DG |
47 | #define I915_READ_IMR(engine) I915_READ(RING_IMR((engine)->mmio_base)) |
48 | #define I915_WRITE_IMR(engine, val) I915_WRITE(RING_IMR((engine)->mmio_base), val) | |
870e86dd | 49 | |
bbdc070a DG |
50 | #define I915_READ_MODE(engine) I915_READ(RING_MI_MODE((engine)->mmio_base)) |
51 | #define I915_WRITE_MODE(engine, val) I915_WRITE(RING_MI_MODE((engine)->mmio_base), val) | |
e9fea574 | 52 | |
3e78998a BW |
53 | /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to |
54 | * do the writes, and that must have qw aligned offsets, simply pretend it's 8b. | |
55 | */ | |
8c12672e CW |
56 | #define gen8_semaphore_seqno_size sizeof(uint64_t) |
57 | #define GEN8_SEMAPHORE_OFFSET(__from, __to) \ | |
58 | (((__from) * I915_NUM_ENGINES + (__to)) * gen8_semaphore_seqno_size) | |
3e78998a BW |
59 | #define GEN8_SIGNAL_OFFSET(__ring, to) \ |
60 | (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \ | |
8c12672e | 61 | GEN8_SEMAPHORE_OFFSET((__ring)->id, (to))) |
3e78998a BW |
62 | #define GEN8_WAIT_OFFSET(__ring, from) \ |
63 | (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \ | |
8c12672e | 64 | GEN8_SEMAPHORE_OFFSET(from, (__ring)->id)) |
3e78998a | 65 | |
7e37f889 | 66 | enum intel_engine_hangcheck_action { |
da661464 | 67 | HANGCHECK_IDLE = 0, |
f2f4d82f JN |
68 | HANGCHECK_WAIT, |
69 | HANGCHECK_ACTIVE, | |
70 | HANGCHECK_KICK, | |
71 | HANGCHECK_HUNG, | |
72 | }; | |
ad8beaea | 73 | |
b6b0fac0 MK |
74 | #define HANGCHECK_SCORE_RING_HUNG 31 |
75 | ||
7e37f889 | 76 | struct intel_engine_hangcheck { |
50877445 | 77 | u64 acthd; |
92cab734 | 78 | u32 seqno; |
05407ff8 | 79 | int score; |
7e37f889 | 80 | enum intel_engine_hangcheck_action action; |
4be17381 | 81 | int deadlock; |
61642ff0 | 82 | u32 instdone[I915_NUM_INSTDONE_REG]; |
92cab734 MK |
83 | }; |
84 | ||
7e37f889 | 85 | struct intel_ring { |
0eb973d3 | 86 | struct i915_vma *vma; |
57e88531 | 87 | void *vaddr; |
8ee14975 | 88 | |
4a570db5 | 89 | struct intel_engine_cs *engine; |
608c1a52 | 90 | struct list_head link; |
0c7dd53b | 91 | |
675d9ad7 CW |
92 | struct list_head request_list; |
93 | ||
8ee14975 OM |
94 | u32 head; |
95 | u32 tail; | |
96 | int space; | |
97 | int size; | |
98 | int effective_size; | |
57e88531 | 99 | bool needs_iomap; |
8ee14975 OM |
100 | |
101 | /** We track the position of the requests in the ring buffer, and | |
102 | * when each is retired we increment last_retired_head as the GPU | |
103 | * must have finished processing the request and so we know we | |
104 | * can advance the ringbuffer up to that position. | |
105 | * | |
106 | * last_retired_head is set to -1 after the value is consumed so | |
107 | * we can detect new retirements. | |
108 | */ | |
109 | u32 last_retired_head; | |
110 | }; | |
111 | ||
e2efd130 | 112 | struct i915_gem_context; |
361b027b | 113 | struct drm_i915_reg_table; |
21076372 | 114 | |
17ee950d AS |
115 | /* |
116 | * we use a single page to load ctx workarounds so all of these | |
117 | * values are referred in terms of dwords | |
118 | * | |
119 | * struct i915_wa_ctx_bb: | |
120 | * offset: specifies batch starting position, also helpful in case | |
121 | * if we want to have multiple batches at different offsets based on | |
122 | * some criteria. It is not a requirement at the moment but provides | |
123 | * an option for future use. | |
124 | * size: size of the batch in DWORDS | |
125 | */ | |
126 | struct i915_ctx_workarounds { | |
127 | struct i915_wa_ctx_bb { | |
128 | u32 offset; | |
129 | u32 size; | |
130 | } indirect_ctx, per_ctx; | |
131 | struct drm_i915_gem_object *obj; | |
132 | }; | |
133 | ||
c81d4613 CW |
134 | struct drm_i915_gem_request; |
135 | ||
c033666a CW |
136 | struct intel_engine_cs { |
137 | struct drm_i915_private *i915; | |
8187a2b7 | 138 | const char *name; |
117897f4 | 139 | enum intel_engine_id { |
de1add36 | 140 | RCS = 0, |
96154f2f | 141 | BCS, |
de1add36 TU |
142 | VCS, |
143 | VCS2, /* Keep instances of the same type engine together. */ | |
144 | VECS | |
9220434a | 145 | } id; |
666796da | 146 | #define I915_NUM_ENGINES 5 |
de1add36 | 147 | #define _VCS(n) (VCS + (n)) |
426960be | 148 | unsigned int exec_id; |
215a7e32 CW |
149 | unsigned int hw_id; |
150 | unsigned int guc_id; /* XXX same as hw_id? */ | |
04769652 | 151 | u64 fence_context; |
333e9fe9 | 152 | u32 mmio_base; |
c2c7f240 | 153 | unsigned int irq_shift; |
7e37f889 | 154 | struct intel_ring *buffer; |
608c1a52 | 155 | struct list_head buffers; |
8187a2b7 | 156 | |
688e6c72 CW |
157 | /* Rather than have every client wait upon all user interrupts, |
158 | * with the herd waking after every interrupt and each doing the | |
159 | * heavyweight seqno dance, we delegate the task (of being the | |
160 | * bottom-half of the user interrupt) to the first client. After | |
161 | * every interrupt, we wake up one client, who does the heavyweight | |
162 | * coherent seqno read and either goes back to sleep (if incomplete), | |
163 | * or wakes up all the completed clients in parallel, before then | |
164 | * transferring the bottom-half status to the next client in the queue. | |
165 | * | |
166 | * Compared to walking the entire list of waiters in a single dedicated | |
167 | * bottom-half, we reduce the latency of the first waiter by avoiding | |
168 | * a context switch, but incur additional coherent seqno reads when | |
169 | * following the chain of request breadcrumbs. Since it is most likely | |
170 | * that we have a single client waiting on each seqno, then reducing | |
171 | * the overhead of waking that client is much preferred. | |
172 | */ | |
173 | struct intel_breadcrumbs { | |
dbd6ef29 | 174 | struct task_struct __rcu *irq_seqno_bh; /* bh for interrupts */ |
aca34b6e CW |
175 | bool irq_posted; |
176 | ||
688e6c72 CW |
177 | spinlock_t lock; /* protects the lists of requests */ |
178 | struct rb_root waiters; /* sorted by retirement, priority */ | |
c81d4613 | 179 | struct rb_root signals; /* sorted by retirement */ |
688e6c72 | 180 | struct intel_wait *first_wait; /* oldest waiter by retirement */ |
c81d4613 | 181 | struct task_struct *signaler; /* used for fence signalling */ |
b3850855 | 182 | struct drm_i915_gem_request *first_signal; |
688e6c72 | 183 | struct timer_list fake_irq; /* used after a missed interrupt */ |
83348ba8 CW |
184 | struct timer_list hangcheck; /* detect missed interrupts */ |
185 | ||
186 | unsigned long timeout; | |
aca34b6e CW |
187 | |
188 | bool irq_enabled : 1; | |
189 | bool rpm_wakelock : 1; | |
688e6c72 CW |
190 | } breadcrumbs; |
191 | ||
06fbca71 CW |
192 | /* |
193 | * A pool of objects to use as shadow copies of client batch buffers | |
194 | * when the command parser is enabled. Prevents the client from | |
195 | * modifying the batch contents after software parsing. | |
196 | */ | |
197 | struct i915_gem_batch_pool batch_pool; | |
198 | ||
8187a2b7 | 199 | struct intel_hw_status_page status_page; |
17ee950d | 200 | struct i915_ctx_workarounds wa_ctx; |
8187a2b7 | 201 | |
61ff75ac CW |
202 | u32 irq_keep_mask; /* always keep these interrupts */ |
203 | u32 irq_enable_mask; /* bitmask to enable ring interrupt */ | |
38a0f2db DG |
204 | void (*irq_enable)(struct intel_engine_cs *engine); |
205 | void (*irq_disable)(struct intel_engine_cs *engine); | |
8187a2b7 | 206 | |
38a0f2db | 207 | int (*init_hw)(struct intel_engine_cs *engine); |
8187a2b7 | 208 | |
8753181e | 209 | int (*init_context)(struct drm_i915_gem_request *req); |
86d7f238 | 210 | |
ddd66c51 CW |
211 | int (*emit_flush)(struct drm_i915_gem_request *request, |
212 | u32 mode); | |
213 | #define EMIT_INVALIDATE BIT(0) | |
214 | #define EMIT_FLUSH BIT(1) | |
215 | #define EMIT_BARRIER (EMIT_INVALIDATE | EMIT_FLUSH) | |
216 | int (*emit_bb_start)(struct drm_i915_gem_request *req, | |
217 | u64 offset, u32 length, | |
218 | unsigned int dispatch_flags); | |
219 | #define I915_DISPATCH_SECURE BIT(0) | |
220 | #define I915_DISPATCH_PINNED BIT(1) | |
221 | #define I915_DISPATCH_RS BIT(2) | |
222 | int (*emit_request)(struct drm_i915_gem_request *req); | |
223 | void (*submit_request)(struct drm_i915_gem_request *req); | |
b2eadbc8 CW |
224 | /* Some chipsets are not quite as coherent as advertised and need |
225 | * an expensive kick to force a true read of the up-to-date seqno. | |
226 | * However, the up-to-date seqno is not always required and the last | |
227 | * seen value is good enough. Note that the seqno will always be | |
228 | * monotonic, even if not coherent. | |
229 | */ | |
38a0f2db | 230 | void (*irq_seqno_barrier)(struct intel_engine_cs *engine); |
38a0f2db | 231 | void (*cleanup)(struct intel_engine_cs *engine); |
ebc348b2 | 232 | |
3e78998a BW |
233 | /* GEN8 signal/wait table - never trust comments! |
234 | * signal to signal to signal to signal to signal to | |
235 | * RCS VCS BCS VECS VCS2 | |
236 | * -------------------------------------------------------------------- | |
237 | * RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) | | |
238 | * |------------------------------------------------------------------- | |
239 | * VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) | | |
240 | * |------------------------------------------------------------------- | |
241 | * BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) | | |
242 | * |------------------------------------------------------------------- | |
243 | * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) | NOP (0x90) | VCS2 (0x98) | | |
244 | * |------------------------------------------------------------------- | |
245 | * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP (0xc0) | | |
246 | * |------------------------------------------------------------------- | |
247 | * | |
248 | * Generalization: | |
249 | * f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id) | |
250 | * ie. transpose of g(x, y) | |
251 | * | |
252 | * sync from sync from sync from sync from sync from | |
253 | * RCS VCS BCS VECS VCS2 | |
254 | * -------------------------------------------------------------------- | |
255 | * RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) | | |
256 | * |------------------------------------------------------------------- | |
257 | * VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) | | |
258 | * |------------------------------------------------------------------- | |
259 | * BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) | | |
260 | * |------------------------------------------------------------------- | |
261 | * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) | NOP (0x90) | VCS2 (0xb8) | | |
262 | * |------------------------------------------------------------------- | |
263 | * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) | NOP (0xc0) | | |
264 | * |------------------------------------------------------------------- | |
265 | * | |
266 | * Generalization: | |
267 | * g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id) | |
268 | * ie. transpose of f(x, y) | |
269 | */ | |
ebc348b2 | 270 | struct { |
666796da | 271 | u32 sync_seqno[I915_NUM_ENGINES-1]; |
78325f2d | 272 | |
3e78998a BW |
273 | union { |
274 | struct { | |
275 | /* our mbox written by others */ | |
666796da | 276 | u32 wait[I915_NUM_ENGINES]; |
3e78998a | 277 | /* mboxes this ring signals to */ |
666796da | 278 | i915_reg_t signal[I915_NUM_ENGINES]; |
3e78998a | 279 | } mbox; |
666796da | 280 | u64 signal_ggtt[I915_NUM_ENGINES]; |
3e78998a | 281 | }; |
78325f2d BW |
282 | |
283 | /* AKA wait() */ | |
ad7bdb2b CW |
284 | int (*sync_to)(struct drm_i915_gem_request *req, |
285 | struct drm_i915_gem_request *signal); | |
286 | int (*signal)(struct drm_i915_gem_request *req); | |
ebc348b2 | 287 | } semaphore; |
ad776f8b | 288 | |
4da46e1e | 289 | /* Execlists */ |
27af5eea TU |
290 | struct tasklet_struct irq_tasklet; |
291 | spinlock_t execlist_lock; /* used inside tasklet, use spin_lock_bh */ | |
acdd884a | 292 | struct list_head execlist_queue; |
3756685a | 293 | unsigned int fw_domains; |
c6a2ac71 TU |
294 | unsigned int next_context_status_buffer; |
295 | unsigned int idle_lite_restore_wa; | |
ca82580c TU |
296 | bool disable_lite_restore_wa; |
297 | u32 ctx_desc_template; | |
4da46e1e | 298 | |
8187a2b7 ZN |
299 | /** |
300 | * List of breadcrumbs associated with GPU requests currently | |
301 | * outstanding. | |
302 | */ | |
303 | struct list_head request_list; | |
304 | ||
94f7bbe1 TE |
305 | /** |
306 | * Seqno of request most recently submitted to request_list. | |
307 | * Used exclusively by hang checker to avoid grabbing lock while | |
308 | * inspecting request list. | |
309 | */ | |
310 | u32 last_submitted_seqno; | |
311 | ||
dcff85c8 CW |
312 | /* An RCU guarded pointer to the last request. No reference is |
313 | * held to the request, users must carefully acquire a reference to | |
1426f715 | 314 | * the request using i915_gem_active_get_rcu(), or hold the |
dcff85c8 CW |
315 | * struct_mutex. |
316 | */ | |
317 | struct i915_gem_active last_request; | |
318 | ||
e2efd130 | 319 | struct i915_gem_context *last_context; |
40521054 | 320 | |
7e37f889 | 321 | struct intel_engine_hangcheck hangcheck; |
92cab734 | 322 | |
0d1aacac CW |
323 | struct { |
324 | struct drm_i915_gem_object *obj; | |
325 | u32 gtt_offset; | |
0d1aacac | 326 | } scratch; |
351e3db2 | 327 | |
44e895a8 BV |
328 | bool needs_cmd_parser; |
329 | ||
351e3db2 | 330 | /* |
44e895a8 | 331 | * Table of commands the command parser needs to know about |
33a051a5 | 332 | * for this engine. |
351e3db2 | 333 | */ |
44e895a8 | 334 | DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER); |
351e3db2 BV |
335 | |
336 | /* | |
337 | * Table of registers allowed in commands that read/write registers. | |
338 | */ | |
361b027b JJ |
339 | const struct drm_i915_reg_table *reg_tables; |
340 | int reg_table_count; | |
351e3db2 BV |
341 | |
342 | /* | |
343 | * Returns the bitmask for the length field of the specified command. | |
344 | * Return 0 for an unrecognized/invalid command. | |
345 | * | |
33a051a5 | 346 | * If the command parser finds an entry for a command in the engine's |
351e3db2 | 347 | * cmd_tables, it gets the command's length based on the table entry. |
33a051a5 CW |
348 | * If not, it calls this function to determine the per-engine length |
349 | * field encoding for the command (i.e. different opcode ranges use | |
350 | * certain bits to encode the command length in the header). | |
351e3db2 BV |
351 | */ |
352 | u32 (*get_cmd_length_mask)(u32 cmd_header); | |
8187a2b7 ZN |
353 | }; |
354 | ||
b0366a54 | 355 | static inline bool |
67d97da3 | 356 | intel_engine_initialized(const struct intel_engine_cs *engine) |
b0366a54 | 357 | { |
c033666a | 358 | return engine->i915 != NULL; |
b0366a54 | 359 | } |
b4519513 | 360 | |
96154f2f | 361 | static inline unsigned |
67d97da3 | 362 | intel_engine_flag(const struct intel_engine_cs *engine) |
96154f2f | 363 | { |
0bc40be8 | 364 | return 1 << engine->id; |
96154f2f DV |
365 | } |
366 | ||
1ec14ad3 | 367 | static inline u32 |
7e37f889 CW |
368 | intel_engine_sync_index(struct intel_engine_cs *engine, |
369 | struct intel_engine_cs *other) | |
1ec14ad3 CW |
370 | { |
371 | int idx; | |
372 | ||
373 | /* | |
ddd4dbc6 RV |
374 | * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2; |
375 | * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs; | |
376 | * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs; | |
377 | * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs; | |
378 | * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs; | |
1ec14ad3 CW |
379 | */ |
380 | ||
0bc40be8 | 381 | idx = (other - engine) - 1; |
1ec14ad3 | 382 | if (idx < 0) |
666796da | 383 | idx += I915_NUM_ENGINES; |
1ec14ad3 CW |
384 | |
385 | return idx; | |
386 | } | |
387 | ||
319404df | 388 | static inline void |
0bc40be8 | 389 | intel_flush_status_page(struct intel_engine_cs *engine, int reg) |
319404df | 390 | { |
0d317ce9 CW |
391 | mb(); |
392 | clflush(&engine->status_page.page_addr[reg]); | |
393 | mb(); | |
319404df ID |
394 | } |
395 | ||
8187a2b7 | 396 | static inline u32 |
5dd8e50c | 397 | intel_read_status_page(struct intel_engine_cs *engine, int reg) |
8187a2b7 | 398 | { |
4225d0f2 | 399 | /* Ensure that the compiler doesn't optimize away the load. */ |
5dd8e50c | 400 | return READ_ONCE(engine->status_page.page_addr[reg]); |
8187a2b7 ZN |
401 | } |
402 | ||
b70ec5bf | 403 | static inline void |
0bc40be8 | 404 | intel_write_status_page(struct intel_engine_cs *engine, |
b70ec5bf MK |
405 | int reg, u32 value) |
406 | { | |
0bc40be8 | 407 | engine->status_page.page_addr[reg] = value; |
b70ec5bf MK |
408 | } |
409 | ||
e2828914 | 410 | /* |
311bd68e CW |
411 | * Reads a dword out of the status page, which is written to from the command |
412 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or | |
413 | * MI_STORE_DATA_IMM. | |
414 | * | |
415 | * The following dwords have a reserved meaning: | |
416 | * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. | |
417 | * 0x04: ring 0 head pointer | |
418 | * 0x05: ring 1 head pointer (915-class) | |
419 | * 0x06: ring 2 head pointer (915-class) | |
420 | * 0x10-0x1b: Context status DWords (GM45) | |
421 | * 0x1f: Last written status offset. (GM45) | |
b07da53c | 422 | * 0x20-0x2f: Reserved (Gen6+) |
311bd68e | 423 | * |
b07da53c | 424 | * The area from dword 0x30 to 0x3ff is available for driver usage. |
311bd68e | 425 | */ |
b07da53c | 426 | #define I915_GEM_HWS_INDEX 0x30 |
7c17d377 | 427 | #define I915_GEM_HWS_INDEX_ADDR (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT) |
b07da53c | 428 | #define I915_GEM_HWS_SCRATCH_INDEX 0x40 |
9a289771 | 429 | #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT) |
311bd68e | 430 | |
7e37f889 CW |
431 | struct intel_ring * |
432 | intel_engine_create_ring(struct intel_engine_cs *engine, int size); | |
aad29fbb CW |
433 | int intel_ring_pin(struct intel_ring *ring); |
434 | void intel_ring_unpin(struct intel_ring *ring); | |
7e37f889 | 435 | void intel_ring_free(struct intel_ring *ring); |
84c2377f | 436 | |
7e37f889 CW |
437 | void intel_engine_stop(struct intel_engine_cs *engine); |
438 | void intel_engine_cleanup(struct intel_engine_cs *engine); | |
96f298aa | 439 | |
6689cb2b JH |
440 | int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request); |
441 | ||
5fb9de1a | 442 | int __must_check intel_ring_begin(struct drm_i915_gem_request *req, int n); |
bba09b12 | 443 | int __must_check intel_ring_cacheline_align(struct drm_i915_gem_request *req); |
406ea8d2 | 444 | |
7e37f889 | 445 | static inline void intel_ring_emit(struct intel_ring *ring, u32 data) |
406ea8d2 | 446 | { |
b5321f30 CW |
447 | *(uint32_t *)(ring->vaddr + ring->tail) = data; |
448 | ring->tail += 4; | |
406ea8d2 CW |
449 | } |
450 | ||
7e37f889 | 451 | static inline void intel_ring_emit_reg(struct intel_ring *ring, i915_reg_t reg) |
f92a9162 | 452 | { |
b5321f30 | 453 | intel_ring_emit(ring, i915_mmio_reg_offset(reg)); |
f92a9162 | 454 | } |
406ea8d2 | 455 | |
7e37f889 | 456 | static inline void intel_ring_advance(struct intel_ring *ring) |
09246732 | 457 | { |
8f942018 CW |
458 | /* Dummy function. |
459 | * | |
460 | * This serves as a placeholder in the code so that the reader | |
461 | * can compare against the preceding intel_ring_begin() and | |
462 | * check that the number of dwords emitted matches the space | |
463 | * reserved for the command packet (i.e. the value passed to | |
464 | * intel_ring_begin()). | |
c5efa1ad | 465 | */ |
8f942018 CW |
466 | } |
467 | ||
468 | static inline u32 intel_ring_offset(struct intel_ring *ring, u32 value) | |
469 | { | |
470 | /* Don't write ring->size (equivalent to 0) as that hangs some GPUs. */ | |
471 | return value & (ring->size - 1); | |
09246732 | 472 | } |
406ea8d2 | 473 | |
82e104cc | 474 | int __intel_ring_space(int head, int tail, int size); |
32c04f16 | 475 | void intel_ring_update_space(struct intel_ring *ring); |
09246732 | 476 | |
7e37f889 | 477 | void intel_engine_init_seqno(struct intel_engine_cs *engine, u32 seqno); |
8187a2b7 | 478 | |
7d5ea807 | 479 | int intel_init_pipe_control(struct intel_engine_cs *engine, int size); |
0bc40be8 | 480 | void intel_fini_pipe_control(struct intel_engine_cs *engine); |
9b1136d5 | 481 | |
019bf277 TU |
482 | void intel_engine_setup_common(struct intel_engine_cs *engine); |
483 | int intel_engine_init_common(struct intel_engine_cs *engine); | |
96a945aa | 484 | void intel_engine_cleanup_common(struct intel_engine_cs *engine); |
019bf277 | 485 | |
dcff85c8 CW |
486 | static inline int intel_engine_idle(struct intel_engine_cs *engine, |
487 | bool interruptible) | |
488 | { | |
489 | /* Wait upon the last request to be completed */ | |
490 | return i915_gem_active_wait_unlocked(&engine->last_request, | |
491 | interruptible, NULL, NULL); | |
492 | } | |
493 | ||
8b3e2d36 TU |
494 | int intel_init_render_ring_buffer(struct intel_engine_cs *engine); |
495 | int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine); | |
496 | int intel_init_bsd2_ring_buffer(struct intel_engine_cs *engine); | |
497 | int intel_init_blt_ring_buffer(struct intel_engine_cs *engine); | |
498 | int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine); | |
8187a2b7 | 499 | |
7e37f889 | 500 | u64 intel_engine_get_active_head(struct intel_engine_cs *engine); |
1b7744e7 CW |
501 | static inline u32 intel_engine_get_seqno(struct intel_engine_cs *engine) |
502 | { | |
503 | return intel_read_status_page(engine, I915_GEM_HWS_INDEX); | |
504 | } | |
79f321b7 | 505 | |
0bc40be8 | 506 | int init_workarounds_ring(struct intel_engine_cs *engine); |
771b9a53 | 507 | |
29b1b415 JH |
508 | /* |
509 | * Arbitrary size for largest possible 'add request' sequence. The code paths | |
510 | * are complex and variable. Empirical measurement shows that the worst case | |
596e5efc CW |
511 | * is BDW at 192 bytes (6 + 6 + 36 dwords), then ILK at 136 bytes. However, |
512 | * we need to allocate double the largest single packet within that emission | |
513 | * to account for tail wraparound (so 6 + 6 + 72 dwords for BDW). | |
29b1b415 | 514 | */ |
596e5efc | 515 | #define MIN_SPACE_FOR_ADD_REQUEST 336 |
29b1b415 | 516 | |
a58c01aa CW |
517 | static inline u32 intel_hws_seqno_address(struct intel_engine_cs *engine) |
518 | { | |
57e88531 | 519 | return engine->status_page.ggtt_offset + I915_GEM_HWS_INDEX_ADDR; |
a58c01aa CW |
520 | } |
521 | ||
688e6c72 | 522 | /* intel_breadcrumbs.c -- user interrupt bottom-half for waiters */ |
688e6c72 CW |
523 | int intel_engine_init_breadcrumbs(struct intel_engine_cs *engine); |
524 | ||
525 | static inline void intel_wait_init(struct intel_wait *wait, u32 seqno) | |
526 | { | |
527 | wait->tsk = current; | |
528 | wait->seqno = seqno; | |
529 | } | |
530 | ||
531 | static inline bool intel_wait_complete(const struct intel_wait *wait) | |
532 | { | |
533 | return RB_EMPTY_NODE(&wait->node); | |
534 | } | |
535 | ||
536 | bool intel_engine_add_wait(struct intel_engine_cs *engine, | |
537 | struct intel_wait *wait); | |
538 | void intel_engine_remove_wait(struct intel_engine_cs *engine, | |
539 | struct intel_wait *wait); | |
b3850855 | 540 | void intel_engine_enable_signaling(struct drm_i915_gem_request *request); |
688e6c72 | 541 | |
dbd6ef29 | 542 | static inline bool intel_engine_has_waiter(const struct intel_engine_cs *engine) |
688e6c72 | 543 | { |
dbd6ef29 | 544 | return rcu_access_pointer(engine->breadcrumbs.irq_seqno_bh); |
688e6c72 CW |
545 | } |
546 | ||
dbd6ef29 | 547 | static inline bool intel_engine_wakeup(const struct intel_engine_cs *engine) |
688e6c72 CW |
548 | { |
549 | bool wakeup = false; | |
dbd6ef29 | 550 | |
688e6c72 | 551 | /* Note that for this not to dangerously chase a dangling pointer, |
dbd6ef29 | 552 | * we must hold the rcu_read_lock here. |
688e6c72 CW |
553 | * |
554 | * Also note that tsk is likely to be in !TASK_RUNNING state so an | |
555 | * early test for tsk->state != TASK_RUNNING before wake_up_process() | |
556 | * is unlikely to be beneficial. | |
557 | */ | |
dbd6ef29 CW |
558 | if (intel_engine_has_waiter(engine)) { |
559 | struct task_struct *tsk; | |
560 | ||
561 | rcu_read_lock(); | |
562 | tsk = rcu_dereference(engine->breadcrumbs.irq_seqno_bh); | |
563 | if (tsk) | |
564 | wakeup = wake_up_process(tsk); | |
565 | rcu_read_unlock(); | |
566 | } | |
567 | ||
688e6c72 CW |
568 | return wakeup; |
569 | } | |
570 | ||
688e6c72 CW |
571 | void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine); |
572 | unsigned int intel_kick_waiters(struct drm_i915_private *i915); | |
c81d4613 | 573 | unsigned int intel_kick_signalers(struct drm_i915_private *i915); |
688e6c72 | 574 | |
dcff85c8 CW |
575 | static inline bool intel_engine_is_active(struct intel_engine_cs *engine) |
576 | { | |
577 | return i915_gem_active_isset(&engine->last_request); | |
578 | } | |
579 | ||
8187a2b7 | 580 | #endif /* _INTEL_RINGBUFFER_H_ */ |