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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
a4d8a0fe | 30 | #include <linux/log2.h> |
7c2fa7fa | 31 | |
760285e7 | 32 | #include <drm/drmP.h> |
760285e7 | 33 | #include <drm/i915_drm.h> |
7c2fa7fa CW |
34 | |
35 | #include "i915_drv.h" | |
36 | #include "i915_gem_render_state.h" | |
62fdfeaf | 37 | #include "i915_trace.h" |
881f47b6 | 38 | #include "intel_drv.h" |
62fdfeaf | 39 | |
a0442461 CW |
40 | /* Rough estimate of the typical request size, performing a flush, |
41 | * set-context and then emitting the batch. | |
42 | */ | |
43 | #define LEGACY_REQUEST_SIZE 200 | |
44 | ||
605d5b32 CW |
45 | static unsigned int __intel_ring_space(unsigned int head, |
46 | unsigned int tail, | |
47 | unsigned int size) | |
c7dca47b | 48 | { |
605d5b32 CW |
49 | /* |
50 | * "If the Ring Buffer Head Pointer and the Tail Pointer are on the | |
51 | * same cacheline, the Head Pointer must not be greater than the Tail | |
52 | * Pointer." | |
53 | */ | |
54 | GEM_BUG_ON(!is_power_of_2(size)); | |
55 | return (head - tail - CACHELINE_BYTES) & (size - 1); | |
c7dca47b CW |
56 | } |
57 | ||
95aebcb2 | 58 | unsigned int intel_ring_update_space(struct intel_ring *ring) |
ebd0fd4b | 59 | { |
95aebcb2 CW |
60 | unsigned int space; |
61 | ||
62 | space = __intel_ring_space(ring->head, ring->emit, ring->size); | |
63 | ||
64 | ring->space = space; | |
65 | return space; | |
ebd0fd4b DG |
66 | } |
67 | ||
b72f3acb | 68 | static int |
7c9cf4e3 | 69 | gen2_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
46f0f8d1 | 70 | { |
73dec95e | 71 | u32 cmd, *cs; |
46f0f8d1 CW |
72 | |
73 | cmd = MI_FLUSH; | |
46f0f8d1 | 74 | |
7c9cf4e3 | 75 | if (mode & EMIT_INVALIDATE) |
46f0f8d1 CW |
76 | cmd |= MI_READ_FLUSH; |
77 | ||
73dec95e TU |
78 | cs = intel_ring_begin(req, 2); |
79 | if (IS_ERR(cs)) | |
80 | return PTR_ERR(cs); | |
46f0f8d1 | 81 | |
73dec95e TU |
82 | *cs++ = cmd; |
83 | *cs++ = MI_NOOP; | |
84 | intel_ring_advance(req, cs); | |
46f0f8d1 CW |
85 | |
86 | return 0; | |
87 | } | |
88 | ||
89 | static int | |
7c9cf4e3 | 90 | gen4_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
62fdfeaf | 91 | { |
73dec95e | 92 | u32 cmd, *cs; |
6f392d54 | 93 | |
36d527de CW |
94 | /* |
95 | * read/write caches: | |
96 | * | |
97 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
98 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
99 | * also flushed at 2d versus 3d pipeline switches. | |
100 | * | |
101 | * read-only caches: | |
102 | * | |
103 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
104 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
105 | * | |
106 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
107 | * | |
108 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
109 | * invalidated when MI_EXE_FLUSH is set. | |
110 | * | |
111 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
112 | * invalidated with every MI_FLUSH. | |
113 | * | |
114 | * TLBs: | |
115 | * | |
116 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
117 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
118 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
119 | * are flushed at any MI_FLUSH. | |
120 | */ | |
121 | ||
b5321f30 | 122 | cmd = MI_FLUSH; |
7c9cf4e3 | 123 | if (mode & EMIT_INVALIDATE) { |
36d527de | 124 | cmd |= MI_EXE_FLUSH; |
b5321f30 CW |
125 | if (IS_G4X(req->i915) || IS_GEN5(req->i915)) |
126 | cmd |= MI_INVALIDATE_ISP; | |
127 | } | |
70eac33e | 128 | |
73dec95e TU |
129 | cs = intel_ring_begin(req, 2); |
130 | if (IS_ERR(cs)) | |
131 | return PTR_ERR(cs); | |
b72f3acb | 132 | |
73dec95e TU |
133 | *cs++ = cmd; |
134 | *cs++ = MI_NOOP; | |
135 | intel_ring_advance(req, cs); | |
b72f3acb CW |
136 | |
137 | return 0; | |
8187a2b7 ZN |
138 | } |
139 | ||
8d315287 JB |
140 | /** |
141 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
142 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
143 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
144 | * | |
145 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
146 | * produced by non-pipelined state commands), software needs to first | |
147 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
148 | * 0. | |
149 | * | |
150 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
151 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
152 | * | |
153 | * And the workaround for these two requires this workaround first: | |
154 | * | |
155 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
156 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
157 | * flushes. | |
158 | * | |
159 | * And this last workaround is tricky because of the requirements on | |
160 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
161 | * volume 2 part 1: | |
162 | * | |
163 | * "1 of the following must also be set: | |
164 | * - Render Target Cache Flush Enable ([12] of DW1) | |
165 | * - Depth Cache Flush Enable ([0] of DW1) | |
166 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
167 | * - Depth Stall ([13] of DW1) | |
168 | * - Post-Sync Operation ([13] of DW1) | |
169 | * - Notify Enable ([8] of DW1)" | |
170 | * | |
171 | * The cache flushes require the workaround flush that triggered this | |
172 | * one, so we can't use it. Depth stall would trigger the same. | |
173 | * Post-sync nonzero is what triggered this second workaround, so we | |
174 | * can't use that one either. Notify enable is IRQs, which aren't | |
175 | * really our business. That leaves only stall at scoreboard. | |
176 | */ | |
177 | static int | |
f2cf1fcc | 178 | intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req) |
8d315287 | 179 | { |
b5321f30 | 180 | u32 scratch_addr = |
bde13ebd | 181 | i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; |
73dec95e TU |
182 | u32 *cs; |
183 | ||
184 | cs = intel_ring_begin(req, 6); | |
185 | if (IS_ERR(cs)) | |
186 | return PTR_ERR(cs); | |
187 | ||
188 | *cs++ = GFX_OP_PIPE_CONTROL(5); | |
189 | *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; | |
190 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
191 | *cs++ = 0; /* low dword */ | |
192 | *cs++ = 0; /* high dword */ | |
193 | *cs++ = MI_NOOP; | |
194 | intel_ring_advance(req, cs); | |
195 | ||
196 | cs = intel_ring_begin(req, 6); | |
197 | if (IS_ERR(cs)) | |
198 | return PTR_ERR(cs); | |
199 | ||
200 | *cs++ = GFX_OP_PIPE_CONTROL(5); | |
201 | *cs++ = PIPE_CONTROL_QW_WRITE; | |
202 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
203 | *cs++ = 0; | |
204 | *cs++ = 0; | |
205 | *cs++ = MI_NOOP; | |
206 | intel_ring_advance(req, cs); | |
8d315287 JB |
207 | |
208 | return 0; | |
209 | } | |
210 | ||
211 | static int | |
7c9cf4e3 | 212 | gen6_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
8d315287 | 213 | { |
b5321f30 | 214 | u32 scratch_addr = |
bde13ebd | 215 | i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; |
73dec95e | 216 | u32 *cs, flags = 0; |
8d315287 JB |
217 | int ret; |
218 | ||
b3111509 | 219 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
f2cf1fcc | 220 | ret = intel_emit_post_sync_nonzero_flush(req); |
b3111509 PZ |
221 | if (ret) |
222 | return ret; | |
223 | ||
8d315287 JB |
224 | /* Just flush everything. Experiments have shown that reducing the |
225 | * number of bits based on the write domains has little performance | |
226 | * impact. | |
227 | */ | |
7c9cf4e3 | 228 | if (mode & EMIT_FLUSH) { |
7d54a904 CW |
229 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
230 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
231 | /* | |
232 | * Ensure that any following seqno writes only happen | |
233 | * when the render cache is indeed flushed. | |
234 | */ | |
97f209bc | 235 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 | 236 | } |
7c9cf4e3 | 237 | if (mode & EMIT_INVALIDATE) { |
7d54a904 CW |
238 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
239 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
240 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
241 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
242 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
243 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
244 | /* | |
245 | * TLB invalidate requires a post-sync write. | |
246 | */ | |
3ac78313 | 247 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 248 | } |
8d315287 | 249 | |
73dec95e TU |
250 | cs = intel_ring_begin(req, 4); |
251 | if (IS_ERR(cs)) | |
252 | return PTR_ERR(cs); | |
8d315287 | 253 | |
73dec95e TU |
254 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
255 | *cs++ = flags; | |
256 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
257 | *cs++ = 0; | |
258 | intel_ring_advance(req, cs); | |
8d315287 JB |
259 | |
260 | return 0; | |
261 | } | |
262 | ||
f3987631 | 263 | static int |
f2cf1fcc | 264 | gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req) |
f3987631 | 265 | { |
73dec95e | 266 | u32 *cs; |
f3987631 | 267 | |
73dec95e TU |
268 | cs = intel_ring_begin(req, 4); |
269 | if (IS_ERR(cs)) | |
270 | return PTR_ERR(cs); | |
f3987631 | 271 | |
73dec95e TU |
272 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
273 | *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; | |
274 | *cs++ = 0; | |
275 | *cs++ = 0; | |
276 | intel_ring_advance(req, cs); | |
f3987631 PZ |
277 | |
278 | return 0; | |
279 | } | |
280 | ||
4772eaeb | 281 | static int |
7c9cf4e3 | 282 | gen7_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
4772eaeb | 283 | { |
b5321f30 | 284 | u32 scratch_addr = |
bde13ebd | 285 | i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; |
73dec95e | 286 | u32 *cs, flags = 0; |
4772eaeb | 287 | |
f3987631 PZ |
288 | /* |
289 | * Ensure that any following seqno writes only happen when the render | |
290 | * cache is indeed flushed. | |
291 | * | |
292 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
293 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
294 | * don't try to be clever and just set it unconditionally. | |
295 | */ | |
296 | flags |= PIPE_CONTROL_CS_STALL; | |
297 | ||
4772eaeb PZ |
298 | /* Just flush everything. Experiments have shown that reducing the |
299 | * number of bits based on the write domains has little performance | |
300 | * impact. | |
301 | */ | |
7c9cf4e3 | 302 | if (mode & EMIT_FLUSH) { |
4772eaeb PZ |
303 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
304 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 305 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 306 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4772eaeb | 307 | } |
7c9cf4e3 | 308 | if (mode & EMIT_INVALIDATE) { |
4772eaeb PZ |
309 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
310 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
311 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
312 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
313 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
314 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
148b83d0 | 315 | flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; |
4772eaeb PZ |
316 | /* |
317 | * TLB invalidate requires a post-sync write. | |
318 | */ | |
319 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 320 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 | 321 | |
add284a3 CW |
322 | flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; |
323 | ||
f3987631 PZ |
324 | /* Workaround: we must issue a pipe_control with CS-stall bit |
325 | * set before a pipe_control command that has the state cache | |
326 | * invalidate bit set. */ | |
f2cf1fcc | 327 | gen7_render_ring_cs_stall_wa(req); |
4772eaeb PZ |
328 | } |
329 | ||
73dec95e TU |
330 | cs = intel_ring_begin(req, 4); |
331 | if (IS_ERR(cs)) | |
332 | return PTR_ERR(cs); | |
4772eaeb | 333 | |
73dec95e TU |
334 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
335 | *cs++ = flags; | |
336 | *cs++ = scratch_addr; | |
337 | *cs++ = 0; | |
338 | intel_ring_advance(req, cs); | |
4772eaeb PZ |
339 | |
340 | return 0; | |
341 | } | |
342 | ||
884ceace | 343 | static int |
9f235dfa | 344 | gen8_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
884ceace | 345 | { |
9f235dfa | 346 | u32 flags; |
73dec95e | 347 | u32 *cs; |
884ceace | 348 | |
9f235dfa | 349 | cs = intel_ring_begin(req, mode & EMIT_INVALIDATE ? 12 : 6); |
73dec95e TU |
350 | if (IS_ERR(cs)) |
351 | return PTR_ERR(cs); | |
884ceace | 352 | |
9f235dfa | 353 | flags = PIPE_CONTROL_CS_STALL; |
a5f3d68e | 354 | |
7c9cf4e3 | 355 | if (mode & EMIT_FLUSH) { |
a5f3d68e BW |
356 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
357 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 358 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 359 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
a5f3d68e | 360 | } |
7c9cf4e3 | 361 | if (mode & EMIT_INVALIDATE) { |
a5f3d68e BW |
362 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
363 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
364 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
365 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
366 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
367 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
368 | flags |= PIPE_CONTROL_QW_WRITE; | |
369 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
02c9f7e3 KG |
370 | |
371 | /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ | |
9f235dfa TU |
372 | cs = gen8_emit_pipe_control(cs, |
373 | PIPE_CONTROL_CS_STALL | | |
374 | PIPE_CONTROL_STALL_AT_SCOREBOARD, | |
375 | 0); | |
a5f3d68e BW |
376 | } |
377 | ||
9f235dfa TU |
378 | cs = gen8_emit_pipe_control(cs, flags, |
379 | i915_ggtt_offset(req->engine->scratch) + | |
380 | 2 * CACHELINE_BYTES); | |
381 | ||
382 | intel_ring_advance(req, cs); | |
383 | ||
384 | return 0; | |
a5f3d68e BW |
385 | } |
386 | ||
0bc40be8 | 387 | static void ring_setup_phys_status_page(struct intel_engine_cs *engine) |
035dc1e0 | 388 | { |
c033666a | 389 | struct drm_i915_private *dev_priv = engine->i915; |
035dc1e0 DV |
390 | u32 addr; |
391 | ||
392 | addr = dev_priv->status_page_dmah->busaddr; | |
c033666a | 393 | if (INTEL_GEN(dev_priv) >= 4) |
035dc1e0 DV |
394 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
395 | I915_WRITE(HWS_PGA, addr); | |
396 | } | |
397 | ||
0bc40be8 | 398 | static void intel_ring_setup_status_page(struct intel_engine_cs *engine) |
af75f269 | 399 | { |
c033666a | 400 | struct drm_i915_private *dev_priv = engine->i915; |
f0f59a00 | 401 | i915_reg_t mmio; |
af75f269 DL |
402 | |
403 | /* The ring status page addresses are no longer next to the rest of | |
404 | * the ring registers as of gen7. | |
405 | */ | |
c033666a | 406 | if (IS_GEN7(dev_priv)) { |
0bc40be8 | 407 | switch (engine->id) { |
a2d3d265 MT |
408 | /* |
409 | * No more rings exist on Gen7. Default case is only to shut up | |
410 | * gcc switch check warning. | |
411 | */ | |
412 | default: | |
413 | GEM_BUG_ON(engine->id); | |
af75f269 DL |
414 | case RCS: |
415 | mmio = RENDER_HWS_PGA_GEN7; | |
416 | break; | |
417 | case BCS: | |
418 | mmio = BLT_HWS_PGA_GEN7; | |
419 | break; | |
af75f269 DL |
420 | case VCS: |
421 | mmio = BSD_HWS_PGA_GEN7; | |
422 | break; | |
423 | case VECS: | |
424 | mmio = VEBOX_HWS_PGA_GEN7; | |
425 | break; | |
426 | } | |
c033666a | 427 | } else if (IS_GEN6(dev_priv)) { |
0bc40be8 | 428 | mmio = RING_HWS_PGA_GEN6(engine->mmio_base); |
af75f269 DL |
429 | } else { |
430 | /* XXX: gen8 returns to sanity */ | |
0bc40be8 | 431 | mmio = RING_HWS_PGA(engine->mmio_base); |
af75f269 DL |
432 | } |
433 | ||
c5498089 VS |
434 | if (INTEL_GEN(dev_priv) >= 6) |
435 | I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff); | |
436 | ||
57e88531 | 437 | I915_WRITE(mmio, engine->status_page.ggtt_offset); |
af75f269 DL |
438 | POSTING_READ(mmio); |
439 | ||
440 | /* | |
441 | * Flush the TLB for this page | |
442 | * | |
443 | * FIXME: These two bits have disappeared on gen8, so a question | |
444 | * arises: do we still need this and if so how should we go about | |
445 | * invalidating the TLB? | |
446 | */ | |
ac657f64 | 447 | if (IS_GEN(dev_priv, 6, 7)) { |
0bc40be8 | 448 | i915_reg_t reg = RING_INSTPM(engine->mmio_base); |
af75f269 DL |
449 | |
450 | /* ring should be idle before issuing a sync flush*/ | |
0bc40be8 | 451 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
af75f269 DL |
452 | |
453 | I915_WRITE(reg, | |
454 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
455 | INSTPM_SYNC_FLUSH)); | |
25ab57f4 CW |
456 | if (intel_wait_for_register(dev_priv, |
457 | reg, INSTPM_SYNC_FLUSH, 0, | |
458 | 1000)) | |
af75f269 | 459 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", |
0bc40be8 | 460 | engine->name); |
af75f269 DL |
461 | } |
462 | } | |
463 | ||
0bc40be8 | 464 | static bool stop_ring(struct intel_engine_cs *engine) |
8187a2b7 | 465 | { |
c033666a | 466 | struct drm_i915_private *dev_priv = engine->i915; |
8187a2b7 | 467 | |
21a2c58a | 468 | if (INTEL_GEN(dev_priv) > 2) { |
0bc40be8 | 469 | I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); |
3d808eb1 CW |
470 | if (intel_wait_for_register(dev_priv, |
471 | RING_MI_MODE(engine->mmio_base), | |
472 | MODE_IDLE, | |
473 | MODE_IDLE, | |
474 | 1000)) { | |
0bc40be8 TU |
475 | DRM_ERROR("%s : timed out trying to stop ring\n", |
476 | engine->name); | |
9bec9b13 CW |
477 | /* Sometimes we observe that the idle flag is not |
478 | * set even though the ring is empty. So double | |
479 | * check before giving up. | |
480 | */ | |
0bc40be8 | 481 | if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine)) |
9bec9b13 | 482 | return false; |
9991ae78 CW |
483 | } |
484 | } | |
b7884eb4 | 485 | |
11caf551 CW |
486 | I915_WRITE_HEAD(engine, I915_READ_TAIL(engine)); |
487 | ||
0bc40be8 | 488 | I915_WRITE_HEAD(engine, 0); |
c5efa1ad | 489 | I915_WRITE_TAIL(engine, 0); |
8187a2b7 | 490 | |
11caf551 CW |
491 | /* The ring must be empty before it is disabled */ |
492 | I915_WRITE_CTL(engine, 0); | |
493 | ||
0bc40be8 | 494 | return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0; |
9991ae78 | 495 | } |
8187a2b7 | 496 | |
0bc40be8 | 497 | static int init_ring_common(struct intel_engine_cs *engine) |
9991ae78 | 498 | { |
c033666a | 499 | struct drm_i915_private *dev_priv = engine->i915; |
7e37f889 | 500 | struct intel_ring *ring = engine->buffer; |
9991ae78 CW |
501 | int ret = 0; |
502 | ||
59bad947 | 503 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
9991ae78 | 504 | |
0bc40be8 | 505 | if (!stop_ring(engine)) { |
9991ae78 | 506 | /* G45 ring initialization often fails to reset head to zero */ |
6fd0d56e CW |
507 | DRM_DEBUG_KMS("%s head not reset to zero " |
508 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
509 | engine->name, |
510 | I915_READ_CTL(engine), | |
511 | I915_READ_HEAD(engine), | |
512 | I915_READ_TAIL(engine), | |
513 | I915_READ_START(engine)); | |
8187a2b7 | 514 | |
0bc40be8 | 515 | if (!stop_ring(engine)) { |
6fd0d56e CW |
516 | DRM_ERROR("failed to set %s head to zero " |
517 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
518 | engine->name, |
519 | I915_READ_CTL(engine), | |
520 | I915_READ_HEAD(engine), | |
521 | I915_READ_TAIL(engine), | |
522 | I915_READ_START(engine)); | |
9991ae78 CW |
523 | ret = -EIO; |
524 | goto out; | |
6fd0d56e | 525 | } |
8187a2b7 ZN |
526 | } |
527 | ||
3177659a | 528 | if (HWS_NEEDS_PHYSICAL(dev_priv)) |
0bc40be8 | 529 | ring_setup_phys_status_page(engine); |
3177659a CS |
530 | else |
531 | intel_ring_setup_status_page(engine); | |
9991ae78 | 532 | |
ad07dfcd | 533 | intel_engine_reset_breadcrumbs(engine); |
821ed7df | 534 | |
ece4a17d | 535 | /* Enforce ordering by reading HEAD register back */ |
0bc40be8 | 536 | I915_READ_HEAD(engine); |
ece4a17d | 537 | |
0d8957c8 DV |
538 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
539 | * registers with the above sequence (the readback of the HEAD registers | |
540 | * also enforces ordering), otherwise the hw might lose the new ring | |
541 | * register values. */ | |
bde13ebd | 542 | I915_WRITE_START(engine, i915_ggtt_offset(ring->vma)); |
95468892 CW |
543 | |
544 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ | |
0bc40be8 | 545 | if (I915_READ_HEAD(engine)) |
95468892 | 546 | DRM_DEBUG("%s initialization failed [head=%08x], fudging\n", |
0bc40be8 | 547 | engine->name, I915_READ_HEAD(engine)); |
821ed7df CW |
548 | |
549 | intel_ring_update_space(ring); | |
550 | I915_WRITE_HEAD(engine, ring->head); | |
551 | I915_WRITE_TAIL(engine, ring->tail); | |
552 | (void)I915_READ_TAIL(engine); | |
95468892 | 553 | |
62ae14b1 | 554 | I915_WRITE_CTL(engine, RING_CTL_SIZE(ring->size) | RING_VALID); |
8187a2b7 | 555 | |
8187a2b7 | 556 | /* If the head is still not zero, the ring is dead */ |
f42bb651 CW |
557 | if (intel_wait_for_register(dev_priv, RING_CTL(engine->mmio_base), |
558 | RING_VALID, RING_VALID, | |
559 | 50)) { | |
e74cfed5 | 560 | DRM_ERROR("%s initialization failed " |
821ed7df | 561 | "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n", |
0bc40be8 TU |
562 | engine->name, |
563 | I915_READ_CTL(engine), | |
564 | I915_READ_CTL(engine) & RING_VALID, | |
821ed7df CW |
565 | I915_READ_HEAD(engine), ring->head, |
566 | I915_READ_TAIL(engine), ring->tail, | |
0bc40be8 | 567 | I915_READ_START(engine), |
bde13ebd | 568 | i915_ggtt_offset(ring->vma)); |
b7884eb4 DV |
569 | ret = -EIO; |
570 | goto out; | |
8187a2b7 ZN |
571 | } |
572 | ||
fc0768ce | 573 | intel_engine_init_hangcheck(engine); |
50f018df | 574 | |
7836cd02 CW |
575 | if (INTEL_GEN(dev_priv) > 2) |
576 | I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); | |
577 | ||
b7884eb4 | 578 | out: |
59bad947 | 579 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
580 | |
581 | return ret; | |
8187a2b7 ZN |
582 | } |
583 | ||
821ed7df CW |
584 | static void reset_ring_common(struct intel_engine_cs *engine, |
585 | struct drm_i915_gem_request *request) | |
586 | { | |
67e64564 CW |
587 | /* |
588 | * RC6 must be prevented until the reset is complete and the engine | |
589 | * reinitialised. If it occurs in the middle of this sequence, the | |
590 | * state written to/loaded from the power context is ill-defined (e.g. | |
591 | * the PP_BASE_DIR may be lost). | |
592 | */ | |
593 | assert_forcewakes_active(engine->i915, FORCEWAKE_ALL); | |
594 | ||
595 | /* | |
596 | * Try to restore the logical GPU state to match the continuation | |
c0dcb203 CW |
597 | * of the request queue. If we skip the context/PD restore, then |
598 | * the next request may try to execute assuming that its context | |
599 | * is valid and loaded on the GPU and so may try to access invalid | |
600 | * memory, prompting repeated GPU hangs. | |
601 | * | |
602 | * If the request was guilty, we still restore the logical state | |
603 | * in case the next request requires it (e.g. the aliasing ppgtt), | |
604 | * but skip over the hung batch. | |
605 | * | |
606 | * If the request was innocent, we try to replay the request with | |
607 | * the restored context. | |
608 | */ | |
609 | if (request) { | |
610 | struct drm_i915_private *dev_priv = request->i915; | |
611 | struct intel_context *ce = &request->ctx->engine[engine->id]; | |
612 | struct i915_hw_ppgtt *ppgtt; | |
613 | ||
614 | /* FIXME consider gen8 reset */ | |
615 | ||
616 | if (ce->state) { | |
617 | I915_WRITE(CCID, | |
618 | i915_ggtt_offset(ce->state) | | |
619 | BIT(8) /* must be set! */ | | |
620 | CCID_EXTENDED_STATE_SAVE | | |
621 | CCID_EXTENDED_STATE_RESTORE | | |
622 | CCID_EN); | |
623 | } | |
624 | ||
625 | ppgtt = request->ctx->ppgtt ?: engine->i915->mm.aliasing_ppgtt; | |
626 | if (ppgtt) { | |
627 | u32 pd_offset = ppgtt->pd.base.ggtt_offset << 10; | |
628 | ||
629 | I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G); | |
630 | I915_WRITE(RING_PP_DIR_BASE(engine), pd_offset); | |
631 | ||
632 | /* Wait for the PD reload to complete */ | |
633 | if (intel_wait_for_register(dev_priv, | |
634 | RING_PP_DIR_BASE(engine), | |
635 | BIT(0), 0, | |
636 | 10)) | |
637 | DRM_ERROR("Wait for reload of ppgtt page-directory timed out\n"); | |
821ed7df | 638 | |
c0dcb203 CW |
639 | ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); |
640 | } | |
641 | ||
642 | /* If the rq hung, jump to its breadcrumb and skip the batch */ | |
fe085f13 CW |
643 | if (request->fence.error == -EIO) |
644 | request->ring->head = request->postfix; | |
c0dcb203 CW |
645 | } else { |
646 | engine->legacy_active_context = NULL; | |
647 | } | |
821ed7df CW |
648 | } |
649 | ||
8753181e | 650 | static int intel_rcs_ctx_init(struct drm_i915_gem_request *req) |
8f0e2b9d DV |
651 | { |
652 | int ret; | |
653 | ||
e2be4faf | 654 | ret = intel_ring_workarounds_emit(req); |
8f0e2b9d DV |
655 | if (ret != 0) |
656 | return ret; | |
657 | ||
4e50f082 | 658 | ret = i915_gem_render_state_emit(req); |
8f0e2b9d | 659 | if (ret) |
e26e1b97 | 660 | return ret; |
8f0e2b9d | 661 | |
e26e1b97 | 662 | return 0; |
8f0e2b9d DV |
663 | } |
664 | ||
0bc40be8 | 665 | static int init_render_ring(struct intel_engine_cs *engine) |
8187a2b7 | 666 | { |
c033666a | 667 | struct drm_i915_private *dev_priv = engine->i915; |
0bc40be8 | 668 | int ret = init_ring_common(engine); |
9c33baa6 KZ |
669 | if (ret) |
670 | return ret; | |
a69ffdbf | 671 | |
61a563a2 | 672 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
ac657f64 | 673 | if (IS_GEN(dev_priv, 4, 6)) |
6b26c86d | 674 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
675 | |
676 | /* We need to disable the AsyncFlip performance optimisations in order | |
677 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
678 | * programmed to '1' on all products. | |
8693a824 | 679 | * |
2441f877 | 680 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv |
1c8c38c5 | 681 | */ |
ac657f64 | 682 | if (IS_GEN(dev_priv, 6, 7)) |
1c8c38c5 CW |
683 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
684 | ||
f05bb0c7 | 685 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 686 | /* WaEnableFlushTlbInvalidationMode:snb */ |
c033666a | 687 | if (IS_GEN6(dev_priv)) |
f05bb0c7 | 688 | I915_WRITE(GFX_MODE, |
aa83e30d | 689 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 690 | |
01fa0302 | 691 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
c033666a | 692 | if (IS_GEN7(dev_priv)) |
1c8c38c5 | 693 | I915_WRITE(GFX_MODE_GEN7, |
01fa0302 | 694 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 695 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 696 | |
c033666a | 697 | if (IS_GEN6(dev_priv)) { |
3a69ddd6 KG |
698 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
699 | * "If this bit is set, STCunit will have LRA as replacement | |
700 | * policy. [...] This bit must be reset. LRA replacement | |
701 | * policy is not supported." | |
702 | */ | |
703 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 704 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
705 | } |
706 | ||
ac657f64 | 707 | if (IS_GEN(dev_priv, 6, 7)) |
6b26c86d | 708 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
84f9f938 | 709 | |
035ea405 VS |
710 | if (INTEL_INFO(dev_priv)->gen >= 6) |
711 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); | |
15b9f80e | 712 | |
0bc40be8 | 713 | return init_workarounds_ring(engine); |
8187a2b7 ZN |
714 | } |
715 | ||
0bc40be8 | 716 | static void render_ring_cleanup(struct intel_engine_cs *engine) |
c6df541c | 717 | { |
c033666a | 718 | struct drm_i915_private *dev_priv = engine->i915; |
3e78998a | 719 | |
19880c4a | 720 | i915_vma_unpin_and_release(&dev_priv->semaphore); |
c6df541c CW |
721 | } |
722 | ||
73dec95e | 723 | static u32 *gen8_rcs_signal(struct drm_i915_gem_request *req, u32 *cs) |
3e78998a | 724 | { |
ad7bdb2b | 725 | struct drm_i915_private *dev_priv = req->i915; |
3e78998a | 726 | struct intel_engine_cs *waiter; |
c3232b18 | 727 | enum intel_engine_id id; |
3e78998a | 728 | |
3b3f1650 | 729 | for_each_engine(waiter, dev_priv, id) { |
ad7bdb2b | 730 | u64 gtt_offset = req->engine->semaphore.signal_ggtt[id]; |
3e78998a BW |
731 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
732 | continue; | |
733 | ||
73dec95e TU |
734 | *cs++ = GFX_OP_PIPE_CONTROL(6); |
735 | *cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_QW_WRITE | | |
736 | PIPE_CONTROL_CS_STALL; | |
737 | *cs++ = lower_32_bits(gtt_offset); | |
738 | *cs++ = upper_32_bits(gtt_offset); | |
739 | *cs++ = req->global_seqno; | |
740 | *cs++ = 0; | |
741 | *cs++ = MI_SEMAPHORE_SIGNAL | | |
742 | MI_SEMAPHORE_TARGET(waiter->hw_id); | |
743 | *cs++ = 0; | |
3e78998a BW |
744 | } |
745 | ||
73dec95e | 746 | return cs; |
3e78998a BW |
747 | } |
748 | ||
73dec95e | 749 | static u32 *gen8_xcs_signal(struct drm_i915_gem_request *req, u32 *cs) |
3e78998a | 750 | { |
ad7bdb2b | 751 | struct drm_i915_private *dev_priv = req->i915; |
3e78998a | 752 | struct intel_engine_cs *waiter; |
c3232b18 | 753 | enum intel_engine_id id; |
3e78998a | 754 | |
3b3f1650 | 755 | for_each_engine(waiter, dev_priv, id) { |
ad7bdb2b | 756 | u64 gtt_offset = req->engine->semaphore.signal_ggtt[id]; |
3e78998a BW |
757 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
758 | continue; | |
759 | ||
73dec95e TU |
760 | *cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW; |
761 | *cs++ = lower_32_bits(gtt_offset) | MI_FLUSH_DW_USE_GTT; | |
762 | *cs++ = upper_32_bits(gtt_offset); | |
763 | *cs++ = req->global_seqno; | |
764 | *cs++ = MI_SEMAPHORE_SIGNAL | | |
765 | MI_SEMAPHORE_TARGET(waiter->hw_id); | |
766 | *cs++ = 0; | |
3e78998a BW |
767 | } |
768 | ||
73dec95e | 769 | return cs; |
3e78998a BW |
770 | } |
771 | ||
73dec95e | 772 | static u32 *gen6_signal(struct drm_i915_gem_request *req, u32 *cs) |
1ec14ad3 | 773 | { |
ad7bdb2b | 774 | struct drm_i915_private *dev_priv = req->i915; |
318f89ca | 775 | struct intel_engine_cs *engine; |
3b3f1650 | 776 | enum intel_engine_id id; |
caddfe71 | 777 | int num_rings = 0; |
024a43e1 | 778 | |
3b3f1650 | 779 | for_each_engine(engine, dev_priv, id) { |
318f89ca TU |
780 | i915_reg_t mbox_reg; |
781 | ||
782 | if (!(BIT(engine->hw_id) & GEN6_SEMAPHORES_MASK)) | |
783 | continue; | |
f0f59a00 | 784 | |
318f89ca | 785 | mbox_reg = req->engine->semaphore.mbox.signal[engine->hw_id]; |
f0f59a00 | 786 | if (i915_mmio_reg_valid(mbox_reg)) { |
73dec95e TU |
787 | *cs++ = MI_LOAD_REGISTER_IMM(1); |
788 | *cs++ = i915_mmio_reg_offset(mbox_reg); | |
789 | *cs++ = req->global_seqno; | |
caddfe71 | 790 | num_rings++; |
78325f2d BW |
791 | } |
792 | } | |
caddfe71 | 793 | if (num_rings & 1) |
73dec95e | 794 | *cs++ = MI_NOOP; |
024a43e1 | 795 | |
73dec95e | 796 | return cs; |
1ec14ad3 CW |
797 | } |
798 | ||
27a5f61b CW |
799 | static void cancel_requests(struct intel_engine_cs *engine) |
800 | { | |
801 | struct drm_i915_gem_request *request; | |
802 | unsigned long flags; | |
803 | ||
804 | spin_lock_irqsave(&engine->timeline->lock, flags); | |
805 | ||
806 | /* Mark all submitted requests as skipped. */ | |
807 | list_for_each_entry(request, &engine->timeline->requests, link) { | |
808 | GEM_BUG_ON(!request->global_seqno); | |
809 | if (!i915_gem_request_completed(request)) | |
810 | dma_fence_set_error(&request->fence, -EIO); | |
811 | } | |
812 | /* Remaining _unready_ requests will be nop'ed when submitted */ | |
813 | ||
814 | spin_unlock_irqrestore(&engine->timeline->lock, flags); | |
815 | } | |
816 | ||
b0411e7d CW |
817 | static void i9xx_submit_request(struct drm_i915_gem_request *request) |
818 | { | |
819 | struct drm_i915_private *dev_priv = request->i915; | |
820 | ||
d55ac5bf CW |
821 | i915_gem_request_submit(request); |
822 | ||
e6ba9992 CW |
823 | I915_WRITE_TAIL(request->engine, |
824 | intel_ring_set_tail(request->ring, request->tail)); | |
b0411e7d CW |
825 | } |
826 | ||
73dec95e | 827 | static void i9xx_emit_breadcrumb(struct drm_i915_gem_request *req, u32 *cs) |
1ec14ad3 | 828 | { |
73dec95e TU |
829 | *cs++ = MI_STORE_DWORD_INDEX; |
830 | *cs++ = I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT; | |
831 | *cs++ = req->global_seqno; | |
832 | *cs++ = MI_USER_INTERRUPT; | |
1ec14ad3 | 833 | |
73dec95e | 834 | req->tail = intel_ring_offset(req, cs); |
ed1501d4 | 835 | assert_ring_tail_valid(req->ring, req->tail); |
1ec14ad3 CW |
836 | } |
837 | ||
98f29e8d CW |
838 | static const int i9xx_emit_breadcrumb_sz = 4; |
839 | ||
b0411e7d | 840 | /** |
9b81d556 | 841 | * gen6_sema_emit_breadcrumb - Update the semaphore mailbox registers |
b0411e7d CW |
842 | * |
843 | * @request - request to write to the ring | |
844 | * | |
845 | * Update the mailbox registers in the *other* rings with the current seqno. | |
846 | * This acts like a signal in the canonical semaphore. | |
847 | */ | |
73dec95e | 848 | static void gen6_sema_emit_breadcrumb(struct drm_i915_gem_request *req, u32 *cs) |
b0411e7d | 849 | { |
caddfe71 | 850 | return i9xx_emit_breadcrumb(req, |
73dec95e | 851 | req->engine->semaphore.signal(req, cs)); |
b0411e7d CW |
852 | } |
853 | ||
caddfe71 | 854 | static void gen8_render_emit_breadcrumb(struct drm_i915_gem_request *req, |
73dec95e | 855 | u32 *cs) |
a58c01aa CW |
856 | { |
857 | struct intel_engine_cs *engine = req->engine; | |
9242f974 | 858 | |
caddfe71 | 859 | if (engine->semaphore.signal) |
73dec95e TU |
860 | cs = engine->semaphore.signal(req, cs); |
861 | ||
862 | *cs++ = GFX_OP_PIPE_CONTROL(6); | |
863 | *cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_CS_STALL | | |
864 | PIPE_CONTROL_QW_WRITE; | |
865 | *cs++ = intel_hws_seqno_address(engine); | |
866 | *cs++ = 0; | |
867 | *cs++ = req->global_seqno; | |
a58c01aa | 868 | /* We're thrashing one dword of HWS. */ |
73dec95e TU |
869 | *cs++ = 0; |
870 | *cs++ = MI_USER_INTERRUPT; | |
871 | *cs++ = MI_NOOP; | |
a58c01aa | 872 | |
73dec95e | 873 | req->tail = intel_ring_offset(req, cs); |
ed1501d4 | 874 | assert_ring_tail_valid(req->ring, req->tail); |
a58c01aa CW |
875 | } |
876 | ||
98f29e8d CW |
877 | static const int gen8_render_emit_breadcrumb_sz = 8; |
878 | ||
c8c99b0f BW |
879 | /** |
880 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
881 | * | |
882 | * @waiter - ring that is waiting | |
883 | * @signaller - ring which has, or will signal | |
884 | * @seqno - seqno which the waiter will block on | |
885 | */ | |
5ee426ca BW |
886 | |
887 | static int | |
ad7bdb2b CW |
888 | gen8_ring_sync_to(struct drm_i915_gem_request *req, |
889 | struct drm_i915_gem_request *signal) | |
5ee426ca | 890 | { |
ad7bdb2b CW |
891 | struct drm_i915_private *dev_priv = req->i915; |
892 | u64 offset = GEN8_WAIT_OFFSET(req->engine, signal->engine->id); | |
6ef48d7f | 893 | struct i915_hw_ppgtt *ppgtt; |
73dec95e | 894 | u32 *cs; |
5ee426ca | 895 | |
73dec95e TU |
896 | cs = intel_ring_begin(req, 4); |
897 | if (IS_ERR(cs)) | |
898 | return PTR_ERR(cs); | |
5ee426ca | 899 | |
73dec95e TU |
900 | *cs++ = MI_SEMAPHORE_WAIT | MI_SEMAPHORE_GLOBAL_GTT | |
901 | MI_SEMAPHORE_SAD_GTE_SDD; | |
902 | *cs++ = signal->global_seqno; | |
903 | *cs++ = lower_32_bits(offset); | |
904 | *cs++ = upper_32_bits(offset); | |
905 | intel_ring_advance(req, cs); | |
6ef48d7f CW |
906 | |
907 | /* When the !RCS engines idle waiting upon a semaphore, they lose their | |
908 | * pagetables and we must reload them before executing the batch. | |
909 | * We do this on the i915_switch_context() following the wait and | |
910 | * before the dispatch. | |
911 | */ | |
ad7bdb2b CW |
912 | ppgtt = req->ctx->ppgtt; |
913 | if (ppgtt && req->engine->id != RCS) | |
914 | ppgtt->pd_dirty_rings |= intel_engine_flag(req->engine); | |
5ee426ca BW |
915 | return 0; |
916 | } | |
917 | ||
c8c99b0f | 918 | static int |
ad7bdb2b CW |
919 | gen6_ring_sync_to(struct drm_i915_gem_request *req, |
920 | struct drm_i915_gem_request *signal) | |
1ec14ad3 | 921 | { |
c8c99b0f BW |
922 | u32 dw1 = MI_SEMAPHORE_MBOX | |
923 | MI_SEMAPHORE_COMPARE | | |
924 | MI_SEMAPHORE_REGISTER; | |
318f89ca | 925 | u32 wait_mbox = signal->engine->semaphore.mbox.wait[req->engine->hw_id]; |
73dec95e | 926 | u32 *cs; |
1ec14ad3 | 927 | |
ebc348b2 | 928 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
686cb5f9 | 929 | |
73dec95e TU |
930 | cs = intel_ring_begin(req, 4); |
931 | if (IS_ERR(cs)) | |
932 | return PTR_ERR(cs); | |
1ec14ad3 | 933 | |
73dec95e | 934 | *cs++ = dw1 | wait_mbox; |
ddf07be7 CW |
935 | /* Throughout all of the GEM code, seqno passed implies our current |
936 | * seqno is >= the last seqno executed. However for hardware the | |
937 | * comparison is strictly greater than. | |
938 | */ | |
73dec95e TU |
939 | *cs++ = signal->global_seqno - 1; |
940 | *cs++ = 0; | |
941 | *cs++ = MI_NOOP; | |
942 | intel_ring_advance(req, cs); | |
1ec14ad3 CW |
943 | |
944 | return 0; | |
945 | } | |
946 | ||
f8973c21 | 947 | static void |
38a0f2db | 948 | gen5_seqno_barrier(struct intel_engine_cs *engine) |
c6df541c | 949 | { |
f8973c21 CW |
950 | /* MI_STORE are internally buffered by the GPU and not flushed |
951 | * either by MI_FLUSH or SyncFlush or any other combination of | |
952 | * MI commands. | |
c6df541c | 953 | * |
f8973c21 CW |
954 | * "Only the submission of the store operation is guaranteed. |
955 | * The write result will be complete (coherent) some time later | |
956 | * (this is practically a finite period but there is no guaranteed | |
957 | * latency)." | |
958 | * | |
959 | * Empirically, we observe that we need a delay of at least 75us to | |
960 | * be sure that the seqno write is visible by the CPU. | |
c6df541c | 961 | */ |
f8973c21 | 962 | usleep_range(125, 250); |
c6df541c CW |
963 | } |
964 | ||
c04e0f3b CW |
965 | static void |
966 | gen6_seqno_barrier(struct intel_engine_cs *engine) | |
4cd53c0c | 967 | { |
c033666a | 968 | struct drm_i915_private *dev_priv = engine->i915; |
bcbdb6d0 | 969 | |
4cd53c0c DV |
970 | /* Workaround to force correct ordering between irq and seqno writes on |
971 | * ivb (and maybe also on snb) by reading from a CS register (like | |
9b9ed309 CW |
972 | * ACTHD) before reading the status page. |
973 | * | |
974 | * Note that this effectively stalls the read by the time it takes to | |
975 | * do a memory transaction, which more or less ensures that the write | |
976 | * from the GPU has sufficient time to invalidate the CPU cacheline. | |
977 | * Alternatively we could delay the interrupt from the CS ring to give | |
978 | * the write time to land, but that would incur a delay after every | |
979 | * batch i.e. much more frequent than a delay when waiting for the | |
980 | * interrupt (with the same net latency). | |
bcbdb6d0 CW |
981 | * |
982 | * Also note that to prevent whole machine hangs on gen7, we have to | |
983 | * take the spinlock to guard against concurrent cacheline access. | |
9b9ed309 | 984 | */ |
bcbdb6d0 | 985 | spin_lock_irq(&dev_priv->uncore.lock); |
c04e0f3b | 986 | POSTING_READ_FW(RING_ACTHD(engine->mmio_base)); |
bcbdb6d0 | 987 | spin_unlock_irq(&dev_priv->uncore.lock); |
4cd53c0c DV |
988 | } |
989 | ||
31bb59cc CW |
990 | static void |
991 | gen5_irq_enable(struct intel_engine_cs *engine) | |
e48d8634 | 992 | { |
31bb59cc | 993 | gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
994 | } |
995 | ||
996 | static void | |
31bb59cc | 997 | gen5_irq_disable(struct intel_engine_cs *engine) |
e48d8634 | 998 | { |
31bb59cc | 999 | gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
1000 | } |
1001 | ||
31bb59cc CW |
1002 | static void |
1003 | i9xx_irq_enable(struct intel_engine_cs *engine) | |
62fdfeaf | 1004 | { |
c033666a | 1005 | struct drm_i915_private *dev_priv = engine->i915; |
b13c2b96 | 1006 | |
31bb59cc CW |
1007 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
1008 | I915_WRITE(IMR, dev_priv->irq_mask); | |
1009 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
62fdfeaf EA |
1010 | } |
1011 | ||
8187a2b7 | 1012 | static void |
31bb59cc | 1013 | i9xx_irq_disable(struct intel_engine_cs *engine) |
62fdfeaf | 1014 | { |
c033666a | 1015 | struct drm_i915_private *dev_priv = engine->i915; |
62fdfeaf | 1016 | |
31bb59cc CW |
1017 | dev_priv->irq_mask |= engine->irq_enable_mask; |
1018 | I915_WRITE(IMR, dev_priv->irq_mask); | |
62fdfeaf EA |
1019 | } |
1020 | ||
31bb59cc CW |
1021 | static void |
1022 | i8xx_irq_enable(struct intel_engine_cs *engine) | |
c2798b19 | 1023 | { |
c033666a | 1024 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 1025 | |
31bb59cc CW |
1026 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
1027 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
1028 | POSTING_READ16(RING_IMR(engine->mmio_base)); | |
c2798b19 CW |
1029 | } |
1030 | ||
1031 | static void | |
31bb59cc | 1032 | i8xx_irq_disable(struct intel_engine_cs *engine) |
c2798b19 | 1033 | { |
c033666a | 1034 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 1035 | |
31bb59cc CW |
1036 | dev_priv->irq_mask |= engine->irq_enable_mask; |
1037 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
c2798b19 CW |
1038 | } |
1039 | ||
b72f3acb | 1040 | static int |
7c9cf4e3 | 1041 | bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
d1b851fc | 1042 | { |
73dec95e | 1043 | u32 *cs; |
b72f3acb | 1044 | |
73dec95e TU |
1045 | cs = intel_ring_begin(req, 2); |
1046 | if (IS_ERR(cs)) | |
1047 | return PTR_ERR(cs); | |
b72f3acb | 1048 | |
73dec95e TU |
1049 | *cs++ = MI_FLUSH; |
1050 | *cs++ = MI_NOOP; | |
1051 | intel_ring_advance(req, cs); | |
b72f3acb | 1052 | return 0; |
d1b851fc ZN |
1053 | } |
1054 | ||
31bb59cc CW |
1055 | static void |
1056 | gen6_irq_enable(struct intel_engine_cs *engine) | |
0f46832f | 1057 | { |
c033666a | 1058 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 1059 | |
61ff75ac CW |
1060 | I915_WRITE_IMR(engine, |
1061 | ~(engine->irq_enable_mask | | |
1062 | engine->irq_keep_mask)); | |
31bb59cc | 1063 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); |
0f46832f CW |
1064 | } |
1065 | ||
1066 | static void | |
31bb59cc | 1067 | gen6_irq_disable(struct intel_engine_cs *engine) |
0f46832f | 1068 | { |
c033666a | 1069 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 1070 | |
61ff75ac | 1071 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
31bb59cc | 1072 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); |
d1b851fc ZN |
1073 | } |
1074 | ||
31bb59cc CW |
1075 | static void |
1076 | hsw_vebox_irq_enable(struct intel_engine_cs *engine) | |
a19d2933 | 1077 | { |
c033666a | 1078 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 1079 | |
31bb59cc | 1080 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
f4e9af4f | 1081 | gen6_unmask_pm_irq(dev_priv, engine->irq_enable_mask); |
a19d2933 BW |
1082 | } |
1083 | ||
1084 | static void | |
31bb59cc | 1085 | hsw_vebox_irq_disable(struct intel_engine_cs *engine) |
a19d2933 | 1086 | { |
c033666a | 1087 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 1088 | |
31bb59cc | 1089 | I915_WRITE_IMR(engine, ~0); |
f4e9af4f | 1090 | gen6_mask_pm_irq(dev_priv, engine->irq_enable_mask); |
a19d2933 BW |
1091 | } |
1092 | ||
31bb59cc CW |
1093 | static void |
1094 | gen8_irq_enable(struct intel_engine_cs *engine) | |
abd58f01 | 1095 | { |
c033666a | 1096 | struct drm_i915_private *dev_priv = engine->i915; |
abd58f01 | 1097 | |
61ff75ac CW |
1098 | I915_WRITE_IMR(engine, |
1099 | ~(engine->irq_enable_mask | | |
1100 | engine->irq_keep_mask)); | |
31bb59cc | 1101 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); |
abd58f01 BW |
1102 | } |
1103 | ||
1104 | static void | |
31bb59cc | 1105 | gen8_irq_disable(struct intel_engine_cs *engine) |
abd58f01 | 1106 | { |
c033666a | 1107 | struct drm_i915_private *dev_priv = engine->i915; |
abd58f01 | 1108 | |
61ff75ac | 1109 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
abd58f01 BW |
1110 | } |
1111 | ||
d1b851fc | 1112 | static int |
803688ba CW |
1113 | i965_emit_bb_start(struct drm_i915_gem_request *req, |
1114 | u64 offset, u32 length, | |
1115 | unsigned int dispatch_flags) | |
d1b851fc | 1116 | { |
73dec95e | 1117 | u32 *cs; |
78501eac | 1118 | |
73dec95e TU |
1119 | cs = intel_ring_begin(req, 2); |
1120 | if (IS_ERR(cs)) | |
1121 | return PTR_ERR(cs); | |
e1f99ce6 | 1122 | |
73dec95e TU |
1123 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | (dispatch_flags & |
1124 | I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965); | |
1125 | *cs++ = offset; | |
1126 | intel_ring_advance(req, cs); | |
78501eac | 1127 | |
d1b851fc ZN |
1128 | return 0; |
1129 | } | |
1130 | ||
b45305fc DV |
1131 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1132 | #define I830_BATCH_LIMIT (256*1024) | |
c4d69da1 CW |
1133 | #define I830_TLB_ENTRIES (2) |
1134 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) | |
8187a2b7 | 1135 | static int |
803688ba CW |
1136 | i830_emit_bb_start(struct drm_i915_gem_request *req, |
1137 | u64 offset, u32 len, | |
1138 | unsigned int dispatch_flags) | |
62fdfeaf | 1139 | { |
73dec95e | 1140 | u32 *cs, cs_offset = i915_ggtt_offset(req->engine->scratch); |
62fdfeaf | 1141 | |
73dec95e TU |
1142 | cs = intel_ring_begin(req, 6); |
1143 | if (IS_ERR(cs)) | |
1144 | return PTR_ERR(cs); | |
62fdfeaf | 1145 | |
c4d69da1 | 1146 | /* Evict the invalid PTE TLBs */ |
73dec95e TU |
1147 | *cs++ = COLOR_BLT_CMD | BLT_WRITE_RGBA; |
1148 | *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096; | |
1149 | *cs++ = I830_TLB_ENTRIES << 16 | 4; /* load each page */ | |
1150 | *cs++ = cs_offset; | |
1151 | *cs++ = 0xdeadbeef; | |
1152 | *cs++ = MI_NOOP; | |
1153 | intel_ring_advance(req, cs); | |
b45305fc | 1154 | |
8e004efc | 1155 | if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { |
b45305fc DV |
1156 | if (len > I830_BATCH_LIMIT) |
1157 | return -ENOSPC; | |
1158 | ||
73dec95e TU |
1159 | cs = intel_ring_begin(req, 6 + 2); |
1160 | if (IS_ERR(cs)) | |
1161 | return PTR_ERR(cs); | |
c4d69da1 CW |
1162 | |
1163 | /* Blit the batch (which has now all relocs applied) to the | |
1164 | * stable batch scratch bo area (so that the CS never | |
1165 | * stumbles over its tlb invalidation bug) ... | |
1166 | */ | |
73dec95e TU |
1167 | *cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA; |
1168 | *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096; | |
1169 | *cs++ = DIV_ROUND_UP(len, 4096) << 16 | 4096; | |
1170 | *cs++ = cs_offset; | |
1171 | *cs++ = 4096; | |
1172 | *cs++ = offset; | |
1173 | ||
1174 | *cs++ = MI_FLUSH; | |
1175 | *cs++ = MI_NOOP; | |
1176 | intel_ring_advance(req, cs); | |
b45305fc DV |
1177 | |
1178 | /* ... and execute it. */ | |
c4d69da1 | 1179 | offset = cs_offset; |
b45305fc | 1180 | } |
e1f99ce6 | 1181 | |
73dec95e TU |
1182 | cs = intel_ring_begin(req, 2); |
1183 | if (IS_ERR(cs)) | |
1184 | return PTR_ERR(cs); | |
c4d69da1 | 1185 | |
73dec95e TU |
1186 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; |
1187 | *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 : | |
1188 | MI_BATCH_NON_SECURE); | |
1189 | intel_ring_advance(req, cs); | |
c4d69da1 | 1190 | |
fb3256da DV |
1191 | return 0; |
1192 | } | |
1193 | ||
1194 | static int | |
803688ba CW |
1195 | i915_emit_bb_start(struct drm_i915_gem_request *req, |
1196 | u64 offset, u32 len, | |
1197 | unsigned int dispatch_flags) | |
fb3256da | 1198 | { |
73dec95e | 1199 | u32 *cs; |
fb3256da | 1200 | |
73dec95e TU |
1201 | cs = intel_ring_begin(req, 2); |
1202 | if (IS_ERR(cs)) | |
1203 | return PTR_ERR(cs); | |
fb3256da | 1204 | |
73dec95e TU |
1205 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; |
1206 | *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 : | |
1207 | MI_BATCH_NON_SECURE); | |
1208 | intel_ring_advance(req, cs); | |
62fdfeaf | 1209 | |
62fdfeaf EA |
1210 | return 0; |
1211 | } | |
1212 | ||
62fdfeaf | 1213 | |
6b8294a4 | 1214 | |
d822bb18 CW |
1215 | int intel_ring_pin(struct intel_ring *ring, |
1216 | struct drm_i915_private *i915, | |
1217 | unsigned int offset_bias) | |
7ba717cf | 1218 | { |
d822bb18 | 1219 | enum i915_map_type map = HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC; |
57e88531 | 1220 | struct i915_vma *vma = ring->vma; |
d822bb18 | 1221 | unsigned int flags; |
8305216f | 1222 | void *addr; |
7ba717cf TD |
1223 | int ret; |
1224 | ||
57e88531 | 1225 | GEM_BUG_ON(ring->vaddr); |
7ba717cf | 1226 | |
9d80841e | 1227 | |
d3ef1af6 DCS |
1228 | flags = PIN_GLOBAL; |
1229 | if (offset_bias) | |
1230 | flags |= PIN_OFFSET_BIAS | offset_bias; | |
9d80841e | 1231 | if (vma->obj->stolen) |
57e88531 | 1232 | flags |= PIN_MAPPABLE; |
def0c5f6 | 1233 | |
57e88531 | 1234 | if (!(vma->flags & I915_VMA_GLOBAL_BIND)) { |
9d80841e | 1235 | if (flags & PIN_MAPPABLE || map == I915_MAP_WC) |
57e88531 CW |
1236 | ret = i915_gem_object_set_to_gtt_domain(vma->obj, true); |
1237 | else | |
1238 | ret = i915_gem_object_set_to_cpu_domain(vma->obj, true); | |
1239 | if (unlikely(ret)) | |
def0c5f6 | 1240 | return ret; |
57e88531 | 1241 | } |
7ba717cf | 1242 | |
57e88531 CW |
1243 | ret = i915_vma_pin(vma, 0, PAGE_SIZE, flags); |
1244 | if (unlikely(ret)) | |
1245 | return ret; | |
def0c5f6 | 1246 | |
9d80841e | 1247 | if (i915_vma_is_map_and_fenceable(vma)) |
57e88531 CW |
1248 | addr = (void __force *)i915_vma_pin_iomap(vma); |
1249 | else | |
9d80841e | 1250 | addr = i915_gem_object_pin_map(vma->obj, map); |
57e88531 CW |
1251 | if (IS_ERR(addr)) |
1252 | goto err; | |
7ba717cf | 1253 | |
3d574a6b CW |
1254 | vma->obj->pin_global++; |
1255 | ||
32c04f16 | 1256 | ring->vaddr = addr; |
7ba717cf | 1257 | return 0; |
d2cad535 | 1258 | |
57e88531 CW |
1259 | err: |
1260 | i915_vma_unpin(vma); | |
1261 | return PTR_ERR(addr); | |
7ba717cf TD |
1262 | } |
1263 | ||
e6ba9992 CW |
1264 | void intel_ring_reset(struct intel_ring *ring, u32 tail) |
1265 | { | |
1266 | GEM_BUG_ON(!list_empty(&ring->request_list)); | |
1267 | ring->tail = tail; | |
1268 | ring->head = tail; | |
1269 | ring->emit = tail; | |
1270 | intel_ring_update_space(ring); | |
1271 | } | |
1272 | ||
aad29fbb CW |
1273 | void intel_ring_unpin(struct intel_ring *ring) |
1274 | { | |
1275 | GEM_BUG_ON(!ring->vma); | |
1276 | GEM_BUG_ON(!ring->vaddr); | |
1277 | ||
e6ba9992 CW |
1278 | /* Discard any unused bytes beyond that submitted to hw. */ |
1279 | intel_ring_reset(ring, ring->tail); | |
1280 | ||
9d80841e | 1281 | if (i915_vma_is_map_and_fenceable(ring->vma)) |
aad29fbb | 1282 | i915_vma_unpin_iomap(ring->vma); |
57e88531 CW |
1283 | else |
1284 | i915_gem_object_unpin_map(ring->vma->obj); | |
aad29fbb CW |
1285 | ring->vaddr = NULL; |
1286 | ||
3d574a6b | 1287 | ring->vma->obj->pin_global--; |
57e88531 | 1288 | i915_vma_unpin(ring->vma); |
2919d291 OM |
1289 | } |
1290 | ||
57e88531 CW |
1291 | static struct i915_vma * |
1292 | intel_ring_create_vma(struct drm_i915_private *dev_priv, int size) | |
62fdfeaf | 1293 | { |
05394f39 | 1294 | struct drm_i915_gem_object *obj; |
57e88531 | 1295 | struct i915_vma *vma; |
62fdfeaf | 1296 | |
187685cb | 1297 | obj = i915_gem_object_create_stolen(dev_priv, size); |
c58b735f | 1298 | if (!obj) |
2d6c4c84 | 1299 | obj = i915_gem_object_create_internal(dev_priv, size); |
57e88531 CW |
1300 | if (IS_ERR(obj)) |
1301 | return ERR_CAST(obj); | |
8187a2b7 | 1302 | |
24f3a8cf AG |
1303 | /* mark ring buffers as read-only from GPU side by default */ |
1304 | obj->gt_ro = 1; | |
1305 | ||
a01cb37a | 1306 | vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL); |
57e88531 CW |
1307 | if (IS_ERR(vma)) |
1308 | goto err; | |
1309 | ||
1310 | return vma; | |
e3efda49 | 1311 | |
57e88531 CW |
1312 | err: |
1313 | i915_gem_object_put(obj); | |
1314 | return vma; | |
e3efda49 CW |
1315 | } |
1316 | ||
7e37f889 CW |
1317 | struct intel_ring * |
1318 | intel_engine_create_ring(struct intel_engine_cs *engine, int size) | |
01101fa7 | 1319 | { |
7e37f889 | 1320 | struct intel_ring *ring; |
57e88531 | 1321 | struct i915_vma *vma; |
01101fa7 | 1322 | |
8f942018 | 1323 | GEM_BUG_ON(!is_power_of_2(size)); |
62ae14b1 | 1324 | GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES); |
8f942018 | 1325 | |
01101fa7 | 1326 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
57e88531 | 1327 | if (!ring) |
01101fa7 CW |
1328 | return ERR_PTR(-ENOMEM); |
1329 | ||
675d9ad7 CW |
1330 | INIT_LIST_HEAD(&ring->request_list); |
1331 | ||
01101fa7 CW |
1332 | ring->size = size; |
1333 | /* Workaround an erratum on the i830 which causes a hang if | |
1334 | * the TAIL pointer points to within the last 2 cachelines | |
1335 | * of the buffer. | |
1336 | */ | |
1337 | ring->effective_size = size; | |
2a307c2e | 1338 | if (IS_I830(engine->i915) || IS_I845G(engine->i915)) |
01101fa7 CW |
1339 | ring->effective_size -= 2 * CACHELINE_BYTES; |
1340 | ||
01101fa7 CW |
1341 | intel_ring_update_space(ring); |
1342 | ||
57e88531 CW |
1343 | vma = intel_ring_create_vma(engine->i915, size); |
1344 | if (IS_ERR(vma)) { | |
01101fa7 | 1345 | kfree(ring); |
57e88531 | 1346 | return ERR_CAST(vma); |
01101fa7 | 1347 | } |
57e88531 | 1348 | ring->vma = vma; |
01101fa7 CW |
1349 | |
1350 | return ring; | |
1351 | } | |
1352 | ||
1353 | void | |
7e37f889 | 1354 | intel_ring_free(struct intel_ring *ring) |
01101fa7 | 1355 | { |
f8a7fde4 CW |
1356 | struct drm_i915_gem_object *obj = ring->vma->obj; |
1357 | ||
1358 | i915_vma_close(ring->vma); | |
1359 | __i915_gem_object_release_unless_active(obj); | |
1360 | ||
01101fa7 CW |
1361 | kfree(ring); |
1362 | } | |
1363 | ||
72b72ae4 | 1364 | static int context_pin(struct i915_gem_context *ctx) |
e8a9c58f CW |
1365 | { |
1366 | struct i915_vma *vma = ctx->engine[RCS].state; | |
1367 | int ret; | |
1368 | ||
f4e15af7 CW |
1369 | /* |
1370 | * Clear this page out of any CPU caches for coherent swap-in/out. | |
e8a9c58f CW |
1371 | * We only want to do this on the first bind so that we do not stall |
1372 | * on an active context (which by nature is already on the GPU). | |
1373 | */ | |
1374 | if (!(vma->flags & I915_VMA_GLOBAL_BIND)) { | |
f4e15af7 | 1375 | ret = i915_gem_object_set_to_gtt_domain(vma->obj, true); |
e8a9c58f CW |
1376 | if (ret) |
1377 | return ret; | |
1378 | } | |
1379 | ||
afeddf50 CW |
1380 | return i915_vma_pin(vma, 0, I915_GTT_MIN_ALIGNMENT, |
1381 | PIN_GLOBAL | PIN_HIGH); | |
e8a9c58f CW |
1382 | } |
1383 | ||
3204c343 CW |
1384 | static struct i915_vma * |
1385 | alloc_context_vma(struct intel_engine_cs *engine) | |
1386 | { | |
1387 | struct drm_i915_private *i915 = engine->i915; | |
1388 | struct drm_i915_gem_object *obj; | |
1389 | struct i915_vma *vma; | |
d2b4b979 | 1390 | int err; |
3204c343 | 1391 | |
63ffbcda | 1392 | obj = i915_gem_object_create(i915, engine->context_size); |
3204c343 CW |
1393 | if (IS_ERR(obj)) |
1394 | return ERR_CAST(obj); | |
1395 | ||
d2b4b979 CW |
1396 | if (engine->default_state) { |
1397 | void *defaults, *vaddr; | |
1398 | ||
1399 | vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); | |
1400 | if (IS_ERR(vaddr)) { | |
1401 | err = PTR_ERR(vaddr); | |
1402 | goto err_obj; | |
1403 | } | |
1404 | ||
1405 | defaults = i915_gem_object_pin_map(engine->default_state, | |
1406 | I915_MAP_WB); | |
1407 | if (IS_ERR(defaults)) { | |
1408 | err = PTR_ERR(defaults); | |
1409 | goto err_map; | |
1410 | } | |
1411 | ||
1412 | memcpy(vaddr, defaults, engine->context_size); | |
1413 | ||
1414 | i915_gem_object_unpin_map(engine->default_state); | |
1415 | i915_gem_object_unpin_map(obj); | |
1416 | } | |
1417 | ||
3204c343 CW |
1418 | /* |
1419 | * Try to make the context utilize L3 as well as LLC. | |
1420 | * | |
1421 | * On VLV we don't have L3 controls in the PTEs so we | |
1422 | * shouldn't touch the cache level, especially as that | |
1423 | * would make the object snooped which might have a | |
1424 | * negative performance impact. | |
1425 | * | |
1426 | * Snooping is required on non-llc platforms in execlist | |
1427 | * mode, but since all GGTT accesses use PAT entry 0 we | |
1428 | * get snooping anyway regardless of cache_level. | |
1429 | * | |
1430 | * This is only applicable for Ivy Bridge devices since | |
1431 | * later platforms don't have L3 control bits in the PTE. | |
1432 | */ | |
1433 | if (IS_IVYBRIDGE(i915)) { | |
1434 | /* Ignore any error, regard it as a simple optimisation */ | |
1435 | i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC); | |
1436 | } | |
1437 | ||
1438 | vma = i915_vma_instance(obj, &i915->ggtt.base, NULL); | |
d2b4b979 CW |
1439 | if (IS_ERR(vma)) { |
1440 | err = PTR_ERR(vma); | |
1441 | goto err_obj; | |
1442 | } | |
3204c343 CW |
1443 | |
1444 | return vma; | |
d2b4b979 CW |
1445 | |
1446 | err_map: | |
1447 | i915_gem_object_unpin_map(obj); | |
1448 | err_obj: | |
1449 | i915_gem_object_put(obj); | |
1450 | return ERR_PTR(err); | |
3204c343 CW |
1451 | } |
1452 | ||
266a240b CW |
1453 | static struct intel_ring * |
1454 | intel_ring_context_pin(struct intel_engine_cs *engine, | |
1455 | struct i915_gem_context *ctx) | |
0cb26a8e CW |
1456 | { |
1457 | struct intel_context *ce = &ctx->engine[engine->id]; | |
1458 | int ret; | |
1459 | ||
91c8a326 | 1460 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
0cb26a8e | 1461 | |
266a240b CW |
1462 | if (likely(ce->pin_count++)) |
1463 | goto out; | |
a533b4ba | 1464 | GEM_BUG_ON(!ce->pin_count); /* no overflow please! */ |
0cb26a8e | 1465 | |
63ffbcda | 1466 | if (!ce->state && engine->context_size) { |
3204c343 CW |
1467 | struct i915_vma *vma; |
1468 | ||
1469 | vma = alloc_context_vma(engine); | |
1470 | if (IS_ERR(vma)) { | |
1471 | ret = PTR_ERR(vma); | |
266a240b | 1472 | goto err; |
3204c343 CW |
1473 | } |
1474 | ||
1475 | ce->state = vma; | |
1476 | } | |
1477 | ||
0cb26a8e | 1478 | if (ce->state) { |
72b72ae4 | 1479 | ret = context_pin(ctx); |
e8a9c58f | 1480 | if (ret) |
266a240b | 1481 | goto err; |
5d4bac55 | 1482 | |
3d574a6b | 1483 | ce->state->obj->pin_global++; |
0cb26a8e CW |
1484 | } |
1485 | ||
9a6feaf0 | 1486 | i915_gem_context_get(ctx); |
0cb26a8e | 1487 | |
266a240b CW |
1488 | out: |
1489 | /* One ringbuffer to rule them all */ | |
1490 | return engine->buffer; | |
1491 | ||
1492 | err: | |
0cb26a8e | 1493 | ce->pin_count = 0; |
266a240b | 1494 | return ERR_PTR(ret); |
0cb26a8e CW |
1495 | } |
1496 | ||
e8a9c58f CW |
1497 | static void intel_ring_context_unpin(struct intel_engine_cs *engine, |
1498 | struct i915_gem_context *ctx) | |
0cb26a8e CW |
1499 | { |
1500 | struct intel_context *ce = &ctx->engine[engine->id]; | |
1501 | ||
91c8a326 | 1502 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
e8a9c58f | 1503 | GEM_BUG_ON(ce->pin_count == 0); |
0cb26a8e CW |
1504 | |
1505 | if (--ce->pin_count) | |
1506 | return; | |
1507 | ||
3d574a6b CW |
1508 | if (ce->state) { |
1509 | ce->state->obj->pin_global--; | |
bf3783e5 | 1510 | i915_vma_unpin(ce->state); |
3d574a6b | 1511 | } |
0cb26a8e | 1512 | |
9a6feaf0 | 1513 | i915_gem_context_put(ctx); |
0cb26a8e CW |
1514 | } |
1515 | ||
acd27845 | 1516 | static int intel_init_ring_buffer(struct intel_engine_cs *engine) |
e3efda49 | 1517 | { |
32c04f16 | 1518 | struct intel_ring *ring; |
1a5788bf | 1519 | int err; |
bfc882b4 | 1520 | |
019bf277 TU |
1521 | intel_engine_setup_common(engine); |
1522 | ||
1a5788bf CW |
1523 | err = intel_engine_init_common(engine); |
1524 | if (err) | |
1525 | goto err; | |
e3efda49 | 1526 | |
d822bb18 CW |
1527 | ring = intel_engine_create_ring(engine, 32 * PAGE_SIZE); |
1528 | if (IS_ERR(ring)) { | |
1a5788bf | 1529 | err = PTR_ERR(ring); |
486e93f7 | 1530 | goto err; |
d822bb18 CW |
1531 | } |
1532 | ||
d3ef1af6 | 1533 | /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ |
1a5788bf CW |
1534 | err = intel_ring_pin(ring, engine->i915, I915_GTT_PAGE_SIZE); |
1535 | if (err) | |
1536 | goto err_ring; | |
1537 | ||
1538 | GEM_BUG_ON(engine->buffer); | |
57e88531 | 1539 | engine->buffer = ring; |
62fdfeaf | 1540 | |
8ee14975 | 1541 | return 0; |
351e3db2 | 1542 | |
1a5788bf CW |
1543 | err_ring: |
1544 | intel_ring_free(ring); | |
1a5788bf CW |
1545 | err: |
1546 | intel_engine_cleanup_common(engine); | |
1547 | return err; | |
62fdfeaf EA |
1548 | } |
1549 | ||
7e37f889 | 1550 | void intel_engine_cleanup(struct intel_engine_cs *engine) |
62fdfeaf | 1551 | { |
1a5788bf | 1552 | struct drm_i915_private *dev_priv = engine->i915; |
6402c330 | 1553 | |
1a5788bf CW |
1554 | WARN_ON(INTEL_GEN(dev_priv) > 2 && |
1555 | (I915_READ_MODE(engine) & MODE_IDLE) == 0); | |
33626e6a | 1556 | |
1a5788bf CW |
1557 | intel_ring_unpin(engine->buffer); |
1558 | intel_ring_free(engine->buffer); | |
78501eac | 1559 | |
0bc40be8 TU |
1560 | if (engine->cleanup) |
1561 | engine->cleanup(engine); | |
8d19215b | 1562 | |
96a945aa | 1563 | intel_engine_cleanup_common(engine); |
0cb26a8e | 1564 | |
3b3f1650 AG |
1565 | dev_priv->engine[engine->id] = NULL; |
1566 | kfree(engine); | |
62fdfeaf EA |
1567 | } |
1568 | ||
821ed7df CW |
1569 | void intel_legacy_submission_resume(struct drm_i915_private *dev_priv) |
1570 | { | |
1571 | struct intel_engine_cs *engine; | |
3b3f1650 | 1572 | enum intel_engine_id id; |
821ed7df | 1573 | |
e6ba9992 | 1574 | /* Restart from the beginning of the rings for convenience */ |
fe085f13 | 1575 | for_each_engine(engine, dev_priv, id) |
e6ba9992 | 1576 | intel_ring_reset(engine->buffer, 0); |
821ed7df CW |
1577 | } |
1578 | ||
f73e7399 | 1579 | static int ring_request_alloc(struct drm_i915_gem_request *request) |
9d773091 | 1580 | { |
fd138212 | 1581 | int ret; |
6310346e | 1582 | |
e8a9c58f CW |
1583 | GEM_BUG_ON(!request->ctx->engine[request->engine->id].pin_count); |
1584 | ||
6310346e CW |
1585 | /* Flush enough space to reduce the likelihood of waiting after |
1586 | * we start building the request - in which case we will just | |
1587 | * have to repeat work. | |
1588 | */ | |
a0442461 | 1589 | request->reserved_space += LEGACY_REQUEST_SIZE; |
6310346e | 1590 | |
fd138212 CW |
1591 | ret = intel_ring_wait_for_space(request->ring, request->reserved_space); |
1592 | if (ret) | |
1593 | return ret; | |
6310346e | 1594 | |
a0442461 | 1595 | request->reserved_space -= LEGACY_REQUEST_SIZE; |
6310346e | 1596 | return 0; |
9d773091 CW |
1597 | } |
1598 | ||
fd138212 | 1599 | static noinline int wait_for_space(struct intel_ring *ring, unsigned int bytes) |
987046ad | 1600 | { |
987046ad | 1601 | struct drm_i915_gem_request *target; |
e95433c7 CW |
1602 | long timeout; |
1603 | ||
fd138212 | 1604 | lockdep_assert_held(&ring->vma->vm->i915->drm.struct_mutex); |
987046ad | 1605 | |
95aebcb2 | 1606 | if (intel_ring_update_space(ring) >= bytes) |
987046ad CW |
1607 | return 0; |
1608 | ||
675d9ad7 | 1609 | list_for_each_entry(target, &ring->request_list, ring_link) { |
987046ad | 1610 | /* Would completion of this request free enough space? */ |
605d5b32 CW |
1611 | if (bytes <= __intel_ring_space(target->postfix, |
1612 | ring->emit, ring->size)) | |
987046ad | 1613 | break; |
79bbcc29 | 1614 | } |
29b1b415 | 1615 | |
675d9ad7 | 1616 | if (WARN_ON(&target->ring_link == &ring->request_list)) |
987046ad CW |
1617 | return -ENOSPC; |
1618 | ||
e95433c7 CW |
1619 | timeout = i915_wait_request(target, |
1620 | I915_WAIT_INTERRUPTIBLE | I915_WAIT_LOCKED, | |
1621 | MAX_SCHEDULE_TIMEOUT); | |
1622 | if (timeout < 0) | |
1623 | return timeout; | |
7da844c5 | 1624 | |
7da844c5 CW |
1625 | i915_gem_request_retire_upto(target); |
1626 | ||
1627 | intel_ring_update_space(ring); | |
1628 | GEM_BUG_ON(ring->space < bytes); | |
1629 | return 0; | |
29b1b415 JH |
1630 | } |
1631 | ||
fd138212 CW |
1632 | int intel_ring_wait_for_space(struct intel_ring *ring, unsigned int bytes) |
1633 | { | |
1634 | GEM_BUG_ON(bytes > ring->effective_size); | |
1635 | if (unlikely(bytes > ring->effective_size - ring->emit)) | |
1636 | bytes += ring->size - ring->emit; | |
1637 | ||
1638 | if (unlikely(bytes > ring->space)) { | |
1639 | int ret = wait_for_space(ring, bytes); | |
1640 | if (unlikely(ret)) | |
1641 | return ret; | |
1642 | } | |
1643 | ||
1644 | GEM_BUG_ON(ring->space < bytes); | |
1645 | return 0; | |
1646 | } | |
1647 | ||
5e5655c3 CW |
1648 | u32 *intel_ring_begin(struct drm_i915_gem_request *req, |
1649 | unsigned int num_dwords) | |
cbcc80df | 1650 | { |
7e37f889 | 1651 | struct intel_ring *ring = req->ring; |
5e5655c3 CW |
1652 | const unsigned int remain_usable = ring->effective_size - ring->emit; |
1653 | const unsigned int bytes = num_dwords * sizeof(u32); | |
1654 | unsigned int need_wrap = 0; | |
1655 | unsigned int total_bytes; | |
73dec95e | 1656 | u32 *cs; |
29b1b415 | 1657 | |
6492ca79 CW |
1658 | /* Packets must be qword aligned. */ |
1659 | GEM_BUG_ON(num_dwords & 1); | |
1660 | ||
0251a963 | 1661 | total_bytes = bytes + req->reserved_space; |
5e5655c3 | 1662 | GEM_BUG_ON(total_bytes > ring->effective_size); |
29b1b415 | 1663 | |
5e5655c3 CW |
1664 | if (unlikely(total_bytes > remain_usable)) { |
1665 | const int remain_actual = ring->size - ring->emit; | |
1666 | ||
1667 | if (bytes > remain_usable) { | |
1668 | /* | |
1669 | * Not enough space for the basic request. So need to | |
1670 | * flush out the remainder and then wait for | |
1671 | * base + reserved. | |
1672 | */ | |
1673 | total_bytes += remain_actual; | |
1674 | need_wrap = remain_actual | 1; | |
1675 | } else { | |
1676 | /* | |
1677 | * The base request will fit but the reserved space | |
1678 | * falls off the end. So we don't need an immediate | |
1679 | * wrap and only need to effectively wait for the | |
1680 | * reserved size from the start of ringbuffer. | |
1681 | */ | |
1682 | total_bytes = req->reserved_space + remain_actual; | |
1683 | } | |
cbcc80df MK |
1684 | } |
1685 | ||
5e5655c3 | 1686 | if (unlikely(total_bytes > ring->space)) { |
fd138212 CW |
1687 | int ret; |
1688 | ||
1689 | /* | |
1690 | * Space is reserved in the ringbuffer for finalising the | |
1691 | * request, as that cannot be allowed to fail. During request | |
1692 | * finalisation, reserved_space is set to 0 to stop the | |
1693 | * overallocation and the assumption is that then we never need | |
1694 | * to wait (which has the risk of failing with EINTR). | |
1695 | * | |
1696 | * See also i915_gem_request_alloc() and i915_add_request(). | |
1697 | */ | |
1698 | GEM_BUG_ON(!req->reserved_space); | |
1699 | ||
1700 | ret = wait_for_space(ring, total_bytes); | |
cbcc80df | 1701 | if (unlikely(ret)) |
73dec95e | 1702 | return ERR_PTR(ret); |
cbcc80df MK |
1703 | } |
1704 | ||
987046ad | 1705 | if (unlikely(need_wrap)) { |
5e5655c3 CW |
1706 | need_wrap &= ~1; |
1707 | GEM_BUG_ON(need_wrap > ring->space); | |
1708 | GEM_BUG_ON(ring->emit + need_wrap > ring->size); | |
78501eac | 1709 | |
987046ad | 1710 | /* Fill the tail with MI_NOOP */ |
5e5655c3 | 1711 | memset(ring->vaddr + ring->emit, 0, need_wrap); |
e6ba9992 | 1712 | ring->emit = 0; |
5e5655c3 | 1713 | ring->space -= need_wrap; |
987046ad | 1714 | } |
304d695c | 1715 | |
e6ba9992 | 1716 | GEM_BUG_ON(ring->emit > ring->size - bytes); |
605d5b32 | 1717 | GEM_BUG_ON(ring->space < bytes); |
e6ba9992 | 1718 | cs = ring->vaddr + ring->emit; |
01001863 | 1719 | GEM_DEBUG_EXEC(memset(cs, POISON_INUSE, bytes)); |
e6ba9992 | 1720 | ring->emit += bytes; |
1dae2dfb | 1721 | ring->space -= bytes; |
73dec95e TU |
1722 | |
1723 | return cs; | |
8187a2b7 | 1724 | } |
78501eac | 1725 | |
753b1ad4 | 1726 | /* Align the ring tail to a cacheline boundary */ |
bba09b12 | 1727 | int intel_ring_cacheline_align(struct drm_i915_gem_request *req) |
753b1ad4 | 1728 | { |
b5321f30 | 1729 | int num_dwords = |
e6ba9992 | 1730 | (req->ring->emit & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); |
73dec95e | 1731 | u32 *cs; |
753b1ad4 VS |
1732 | |
1733 | if (num_dwords == 0) | |
1734 | return 0; | |
1735 | ||
18393f63 | 1736 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
73dec95e TU |
1737 | cs = intel_ring_begin(req, num_dwords); |
1738 | if (IS_ERR(cs)) | |
1739 | return PTR_ERR(cs); | |
753b1ad4 VS |
1740 | |
1741 | while (num_dwords--) | |
73dec95e | 1742 | *cs++ = MI_NOOP; |
753b1ad4 | 1743 | |
73dec95e | 1744 | intel_ring_advance(req, cs); |
753b1ad4 VS |
1745 | |
1746 | return 0; | |
1747 | } | |
1748 | ||
c5efa1ad | 1749 | static void gen6_bsd_submit_request(struct drm_i915_gem_request *request) |
881f47b6 | 1750 | { |
c5efa1ad | 1751 | struct drm_i915_private *dev_priv = request->i915; |
881f47b6 | 1752 | |
76f8421f CW |
1753 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
1754 | ||
881f47b6 | 1755 | /* Every tail move must follow the sequence below */ |
12f55818 CW |
1756 | |
1757 | /* Disable notification that the ring is IDLE. The GT | |
1758 | * will then assume that it is busy and bring it out of rc6. | |
1759 | */ | |
76f8421f CW |
1760 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
1761 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
12f55818 CW |
1762 | |
1763 | /* Clear the context id. Here be magic! */ | |
76f8421f | 1764 | I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0); |
0206e353 | 1765 | |
12f55818 | 1766 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
02b312d0 CW |
1767 | if (__intel_wait_for_register_fw(dev_priv, |
1768 | GEN6_BSD_SLEEP_PSMI_CONTROL, | |
1769 | GEN6_BSD_SLEEP_INDICATOR, | |
1770 | 0, | |
1771 | 1000, 0, NULL)) | |
12f55818 | 1772 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
0206e353 | 1773 | |
12f55818 | 1774 | /* Now that the ring is fully powered up, update the tail */ |
b0411e7d | 1775 | i9xx_submit_request(request); |
12f55818 CW |
1776 | |
1777 | /* Let the ring send IDLE messages to the GT again, | |
1778 | * and so let it sleep to conserve power when idle. | |
1779 | */ | |
76f8421f CW |
1780 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
1781 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
1782 | ||
1783 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
881f47b6 XH |
1784 | } |
1785 | ||
7c9cf4e3 | 1786 | static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
881f47b6 | 1787 | { |
73dec95e | 1788 | u32 cmd, *cs; |
b72f3acb | 1789 | |
73dec95e TU |
1790 | cs = intel_ring_begin(req, 4); |
1791 | if (IS_ERR(cs)) | |
1792 | return PTR_ERR(cs); | |
b72f3acb | 1793 | |
71a77e07 | 1794 | cmd = MI_FLUSH_DW; |
c033666a | 1795 | if (INTEL_GEN(req->i915) >= 8) |
075b3bba | 1796 | cmd += 1; |
f0a1fb10 CW |
1797 | |
1798 | /* We always require a command barrier so that subsequent | |
1799 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1800 | * wrt the contents of the write cache being flushed to memory | |
1801 | * (and thus being coherent from the CPU). | |
1802 | */ | |
1803 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1804 | ||
9a289771 JB |
1805 | /* |
1806 | * Bspec vol 1c.5 - video engine command streamer: | |
1807 | * "If ENABLED, all TLBs will be invalidated once the flush | |
1808 | * operation is complete. This bit is only valid when the | |
1809 | * Post-Sync Operation field is a value of 1h or 3h." | |
1810 | */ | |
7c9cf4e3 | 1811 | if (mode & EMIT_INVALIDATE) |
f0a1fb10 CW |
1812 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
1813 | ||
73dec95e TU |
1814 | *cs++ = cmd; |
1815 | *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; | |
c033666a | 1816 | if (INTEL_GEN(req->i915) >= 8) { |
73dec95e TU |
1817 | *cs++ = 0; /* upper addr */ |
1818 | *cs++ = 0; /* value */ | |
075b3bba | 1819 | } else { |
73dec95e TU |
1820 | *cs++ = 0; |
1821 | *cs++ = MI_NOOP; | |
075b3bba | 1822 | } |
73dec95e | 1823 | intel_ring_advance(req, cs); |
b72f3acb | 1824 | return 0; |
881f47b6 XH |
1825 | } |
1826 | ||
1c7a0623 | 1827 | static int |
803688ba CW |
1828 | gen8_emit_bb_start(struct drm_i915_gem_request *req, |
1829 | u64 offset, u32 len, | |
1830 | unsigned int dispatch_flags) | |
1c7a0623 | 1831 | { |
b5321f30 | 1832 | bool ppgtt = USES_PPGTT(req->i915) && |
8e004efc | 1833 | !(dispatch_flags & I915_DISPATCH_SECURE); |
73dec95e | 1834 | u32 *cs; |
1c7a0623 | 1835 | |
73dec95e TU |
1836 | cs = intel_ring_begin(req, 4); |
1837 | if (IS_ERR(cs)) | |
1838 | return PTR_ERR(cs); | |
1c7a0623 BW |
1839 | |
1840 | /* FIXME(BDW): Address space and security selectors. */ | |
73dec95e TU |
1841 | *cs++ = MI_BATCH_BUFFER_START_GEN8 | (ppgtt << 8) | (dispatch_flags & |
1842 | I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0); | |
1843 | *cs++ = lower_32_bits(offset); | |
1844 | *cs++ = upper_32_bits(offset); | |
1845 | *cs++ = MI_NOOP; | |
1846 | intel_ring_advance(req, cs); | |
1c7a0623 BW |
1847 | |
1848 | return 0; | |
1849 | } | |
1850 | ||
d7d4eedd | 1851 | static int |
803688ba CW |
1852 | hsw_emit_bb_start(struct drm_i915_gem_request *req, |
1853 | u64 offset, u32 len, | |
1854 | unsigned int dispatch_flags) | |
d7d4eedd | 1855 | { |
73dec95e | 1856 | u32 *cs; |
d7d4eedd | 1857 | |
73dec95e TU |
1858 | cs = intel_ring_begin(req, 2); |
1859 | if (IS_ERR(cs)) | |
1860 | return PTR_ERR(cs); | |
d7d4eedd | 1861 | |
73dec95e TU |
1862 | *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ? |
1863 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) | | |
1864 | (dispatch_flags & I915_DISPATCH_RS ? | |
1865 | MI_BATCH_RESOURCE_STREAMER : 0); | |
d7d4eedd | 1866 | /* bit0-7 is the length on GEN6+ */ |
73dec95e TU |
1867 | *cs++ = offset; |
1868 | intel_ring_advance(req, cs); | |
d7d4eedd CW |
1869 | |
1870 | return 0; | |
1871 | } | |
1872 | ||
881f47b6 | 1873 | static int |
803688ba CW |
1874 | gen6_emit_bb_start(struct drm_i915_gem_request *req, |
1875 | u64 offset, u32 len, | |
1876 | unsigned int dispatch_flags) | |
881f47b6 | 1877 | { |
73dec95e | 1878 | u32 *cs; |
ab6f8e32 | 1879 | |
73dec95e TU |
1880 | cs = intel_ring_begin(req, 2); |
1881 | if (IS_ERR(cs)) | |
1882 | return PTR_ERR(cs); | |
e1f99ce6 | 1883 | |
73dec95e TU |
1884 | *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ? |
1885 | 0 : MI_BATCH_NON_SECURE_I965); | |
0206e353 | 1886 | /* bit0-7 is the length on GEN6+ */ |
73dec95e TU |
1887 | *cs++ = offset; |
1888 | intel_ring_advance(req, cs); | |
ab6f8e32 | 1889 | |
0206e353 | 1890 | return 0; |
881f47b6 XH |
1891 | } |
1892 | ||
549f7365 CW |
1893 | /* Blitter support (SandyBridge+) */ |
1894 | ||
7c9cf4e3 | 1895 | static int gen6_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
8d19215b | 1896 | { |
73dec95e | 1897 | u32 cmd, *cs; |
b72f3acb | 1898 | |
73dec95e TU |
1899 | cs = intel_ring_begin(req, 4); |
1900 | if (IS_ERR(cs)) | |
1901 | return PTR_ERR(cs); | |
b72f3acb | 1902 | |
71a77e07 | 1903 | cmd = MI_FLUSH_DW; |
c033666a | 1904 | if (INTEL_GEN(req->i915) >= 8) |
075b3bba | 1905 | cmd += 1; |
f0a1fb10 CW |
1906 | |
1907 | /* We always require a command barrier so that subsequent | |
1908 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1909 | * wrt the contents of the write cache being flushed to memory | |
1910 | * (and thus being coherent from the CPU). | |
1911 | */ | |
1912 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1913 | ||
9a289771 JB |
1914 | /* |
1915 | * Bspec vol 1c.3 - blitter engine command streamer: | |
1916 | * "If ENABLED, all TLBs will be invalidated once the flush | |
1917 | * operation is complete. This bit is only valid when the | |
1918 | * Post-Sync Operation field is a value of 1h or 3h." | |
1919 | */ | |
7c9cf4e3 | 1920 | if (mode & EMIT_INVALIDATE) |
f0a1fb10 | 1921 | cmd |= MI_INVALIDATE_TLB; |
73dec95e TU |
1922 | *cs++ = cmd; |
1923 | *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; | |
c033666a | 1924 | if (INTEL_GEN(req->i915) >= 8) { |
73dec95e TU |
1925 | *cs++ = 0; /* upper addr */ |
1926 | *cs++ = 0; /* value */ | |
075b3bba | 1927 | } else { |
73dec95e TU |
1928 | *cs++ = 0; |
1929 | *cs++ = MI_NOOP; | |
075b3bba | 1930 | } |
73dec95e | 1931 | intel_ring_advance(req, cs); |
fd3da6c9 | 1932 | |
b72f3acb | 1933 | return 0; |
8d19215b ZN |
1934 | } |
1935 | ||
d9a64610 TU |
1936 | static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv, |
1937 | struct intel_engine_cs *engine) | |
1938 | { | |
db3d4019 | 1939 | struct drm_i915_gem_object *obj; |
1b9e6650 | 1940 | int ret, i; |
db3d4019 | 1941 | |
4f044a88 | 1942 | if (!i915_modparams.semaphores) |
db3d4019 TU |
1943 | return; |
1944 | ||
51d545d0 CW |
1945 | if (INTEL_GEN(dev_priv) >= 8 && !dev_priv->semaphore) { |
1946 | struct i915_vma *vma; | |
1947 | ||
f51455d4 | 1948 | obj = i915_gem_object_create(dev_priv, PAGE_SIZE); |
51d545d0 CW |
1949 | if (IS_ERR(obj)) |
1950 | goto err; | |
db3d4019 | 1951 | |
a01cb37a | 1952 | vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL); |
51d545d0 CW |
1953 | if (IS_ERR(vma)) |
1954 | goto err_obj; | |
1955 | ||
1956 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
1957 | if (ret) | |
1958 | goto err_obj; | |
1959 | ||
1960 | ret = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH); | |
1961 | if (ret) | |
1962 | goto err_obj; | |
1963 | ||
1964 | dev_priv->semaphore = vma; | |
1965 | } | |
d9a64610 TU |
1966 | |
1967 | if (INTEL_GEN(dev_priv) >= 8) { | |
bde13ebd | 1968 | u32 offset = i915_ggtt_offset(dev_priv->semaphore); |
1b9e6650 | 1969 | |
ad7bdb2b | 1970 | engine->semaphore.sync_to = gen8_ring_sync_to; |
d9a64610 | 1971 | engine->semaphore.signal = gen8_xcs_signal; |
1b9e6650 TU |
1972 | |
1973 | for (i = 0; i < I915_NUM_ENGINES; i++) { | |
bde13ebd | 1974 | u32 ring_offset; |
1b9e6650 TU |
1975 | |
1976 | if (i != engine->id) | |
1977 | ring_offset = offset + GEN8_SEMAPHORE_OFFSET(engine->id, i); | |
1978 | else | |
1979 | ring_offset = MI_SEMAPHORE_SYNC_INVALID; | |
1980 | ||
1981 | engine->semaphore.signal_ggtt[i] = ring_offset; | |
1982 | } | |
d9a64610 | 1983 | } else if (INTEL_GEN(dev_priv) >= 6) { |
ad7bdb2b | 1984 | engine->semaphore.sync_to = gen6_ring_sync_to; |
d9a64610 | 1985 | engine->semaphore.signal = gen6_signal; |
4b8e38a9 TU |
1986 | |
1987 | /* | |
1988 | * The current semaphore is only applied on pre-gen8 | |
1989 | * platform. And there is no VCS2 ring on the pre-gen8 | |
1990 | * platform. So the semaphore between RCS and VCS2 is | |
1991 | * initialized as INVALID. Gen8 will initialize the | |
1992 | * sema between VCS2 and RCS later. | |
1993 | */ | |
318f89ca | 1994 | for (i = 0; i < GEN6_NUM_SEMAPHORES; i++) { |
4b8e38a9 TU |
1995 | static const struct { |
1996 | u32 wait_mbox; | |
1997 | i915_reg_t mbox_reg; | |
318f89ca TU |
1998 | } sem_data[GEN6_NUM_SEMAPHORES][GEN6_NUM_SEMAPHORES] = { |
1999 | [RCS_HW] = { | |
2000 | [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RV, .mbox_reg = GEN6_VRSYNC }, | |
2001 | [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RB, .mbox_reg = GEN6_BRSYNC }, | |
2002 | [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC }, | |
4b8e38a9 | 2003 | }, |
318f89ca TU |
2004 | [VCS_HW] = { |
2005 | [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VR, .mbox_reg = GEN6_RVSYNC }, | |
2006 | [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VB, .mbox_reg = GEN6_BVSYNC }, | |
2007 | [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC }, | |
4b8e38a9 | 2008 | }, |
318f89ca TU |
2009 | [BCS_HW] = { |
2010 | [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BR, .mbox_reg = GEN6_RBSYNC }, | |
2011 | [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BV, .mbox_reg = GEN6_VBSYNC }, | |
2012 | [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC }, | |
4b8e38a9 | 2013 | }, |
318f89ca TU |
2014 | [VECS_HW] = { |
2015 | [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC }, | |
2016 | [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC }, | |
2017 | [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC }, | |
4b8e38a9 TU |
2018 | }, |
2019 | }; | |
2020 | u32 wait_mbox; | |
2021 | i915_reg_t mbox_reg; | |
2022 | ||
318f89ca | 2023 | if (i == engine->hw_id) { |
4b8e38a9 TU |
2024 | wait_mbox = MI_SEMAPHORE_SYNC_INVALID; |
2025 | mbox_reg = GEN6_NOSYNC; | |
2026 | } else { | |
318f89ca TU |
2027 | wait_mbox = sem_data[engine->hw_id][i].wait_mbox; |
2028 | mbox_reg = sem_data[engine->hw_id][i].mbox_reg; | |
4b8e38a9 TU |
2029 | } |
2030 | ||
2031 | engine->semaphore.mbox.wait[i] = wait_mbox; | |
2032 | engine->semaphore.mbox.signal[i] = mbox_reg; | |
2033 | } | |
d9a64610 | 2034 | } |
51d545d0 CW |
2035 | |
2036 | return; | |
2037 | ||
2038 | err_obj: | |
2039 | i915_gem_object_put(obj); | |
2040 | err: | |
2041 | DRM_DEBUG_DRIVER("Failed to allocate space for semaphores, disabling\n"); | |
4f044a88 | 2042 | i915_modparams.semaphores = 0; |
d9a64610 TU |
2043 | } |
2044 | ||
ed003078 CW |
2045 | static void intel_ring_init_irq(struct drm_i915_private *dev_priv, |
2046 | struct intel_engine_cs *engine) | |
2047 | { | |
c78d6061 TU |
2048 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << engine->irq_shift; |
2049 | ||
ed003078 | 2050 | if (INTEL_GEN(dev_priv) >= 8) { |
31bb59cc CW |
2051 | engine->irq_enable = gen8_irq_enable; |
2052 | engine->irq_disable = gen8_irq_disable; | |
ed003078 CW |
2053 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2054 | } else if (INTEL_GEN(dev_priv) >= 6) { | |
31bb59cc CW |
2055 | engine->irq_enable = gen6_irq_enable; |
2056 | engine->irq_disable = gen6_irq_disable; | |
ed003078 CW |
2057 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2058 | } else if (INTEL_GEN(dev_priv) >= 5) { | |
31bb59cc CW |
2059 | engine->irq_enable = gen5_irq_enable; |
2060 | engine->irq_disable = gen5_irq_disable; | |
f8973c21 | 2061 | engine->irq_seqno_barrier = gen5_seqno_barrier; |
ed003078 | 2062 | } else if (INTEL_GEN(dev_priv) >= 3) { |
31bb59cc CW |
2063 | engine->irq_enable = i9xx_irq_enable; |
2064 | engine->irq_disable = i9xx_irq_disable; | |
ed003078 | 2065 | } else { |
31bb59cc CW |
2066 | engine->irq_enable = i8xx_irq_enable; |
2067 | engine->irq_disable = i8xx_irq_disable; | |
ed003078 CW |
2068 | } |
2069 | } | |
2070 | ||
ff44ad51 CW |
2071 | static void i9xx_set_default_submission(struct intel_engine_cs *engine) |
2072 | { | |
2073 | engine->submit_request = i9xx_submit_request; | |
27a5f61b | 2074 | engine->cancel_requests = cancel_requests; |
aba5e278 CW |
2075 | |
2076 | engine->park = NULL; | |
2077 | engine->unpark = NULL; | |
ff44ad51 CW |
2078 | } |
2079 | ||
2080 | static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine) | |
2081 | { | |
aba5e278 | 2082 | i9xx_set_default_submission(engine); |
ff44ad51 CW |
2083 | engine->submit_request = gen6_bsd_submit_request; |
2084 | } | |
2085 | ||
06a2fe22 TU |
2086 | static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv, |
2087 | struct intel_engine_cs *engine) | |
2088 | { | |
618e4ca7 CW |
2089 | intel_ring_init_irq(dev_priv, engine); |
2090 | intel_ring_init_semaphores(dev_priv, engine); | |
2091 | ||
1d8a1337 | 2092 | engine->init_hw = init_ring_common; |
821ed7df | 2093 | engine->reset_hw = reset_ring_common; |
7445a2a4 | 2094 | |
e8a9c58f CW |
2095 | engine->context_pin = intel_ring_context_pin; |
2096 | engine->context_unpin = intel_ring_context_unpin; | |
2097 | ||
f73e7399 CW |
2098 | engine->request_alloc = ring_request_alloc; |
2099 | ||
9b81d556 | 2100 | engine->emit_breadcrumb = i9xx_emit_breadcrumb; |
98f29e8d | 2101 | engine->emit_breadcrumb_sz = i9xx_emit_breadcrumb_sz; |
4f044a88 | 2102 | if (i915_modparams.semaphores) { |
98f29e8d CW |
2103 | int num_rings; |
2104 | ||
9b81d556 | 2105 | engine->emit_breadcrumb = gen6_sema_emit_breadcrumb; |
98f29e8d | 2106 | |
c58949f4 | 2107 | num_rings = INTEL_INFO(dev_priv)->num_rings - 1; |
98f29e8d CW |
2108 | if (INTEL_GEN(dev_priv) >= 8) { |
2109 | engine->emit_breadcrumb_sz += num_rings * 6; | |
2110 | } else { | |
2111 | engine->emit_breadcrumb_sz += num_rings * 3; | |
2112 | if (num_rings & 1) | |
2113 | engine->emit_breadcrumb_sz++; | |
2114 | } | |
2115 | } | |
ff44ad51 CW |
2116 | |
2117 | engine->set_default_submission = i9xx_set_default_submission; | |
6f7bef75 CW |
2118 | |
2119 | if (INTEL_GEN(dev_priv) >= 8) | |
803688ba | 2120 | engine->emit_bb_start = gen8_emit_bb_start; |
6f7bef75 | 2121 | else if (INTEL_GEN(dev_priv) >= 6) |
803688ba | 2122 | engine->emit_bb_start = gen6_emit_bb_start; |
6f7bef75 | 2123 | else if (INTEL_GEN(dev_priv) >= 4) |
803688ba | 2124 | engine->emit_bb_start = i965_emit_bb_start; |
2a307c2e | 2125 | else if (IS_I830(dev_priv) || IS_I845G(dev_priv)) |
803688ba | 2126 | engine->emit_bb_start = i830_emit_bb_start; |
6f7bef75 | 2127 | else |
803688ba | 2128 | engine->emit_bb_start = i915_emit_bb_start; |
06a2fe22 TU |
2129 | } |
2130 | ||
8b3e2d36 | 2131 | int intel_init_render_ring_buffer(struct intel_engine_cs *engine) |
5c1143bb | 2132 | { |
8b3e2d36 | 2133 | struct drm_i915_private *dev_priv = engine->i915; |
3e78998a | 2134 | int ret; |
5c1143bb | 2135 | |
06a2fe22 TU |
2136 | intel_ring_default_vfuncs(dev_priv, engine); |
2137 | ||
61ff75ac CW |
2138 | if (HAS_L3_DPF(dev_priv)) |
2139 | engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
f8973c21 | 2140 | |
c033666a | 2141 | if (INTEL_GEN(dev_priv) >= 8) { |
e2f80391 | 2142 | engine->init_context = intel_rcs_ctx_init; |
9b81d556 | 2143 | engine->emit_breadcrumb = gen8_render_emit_breadcrumb; |
98f29e8d | 2144 | engine->emit_breadcrumb_sz = gen8_render_emit_breadcrumb_sz; |
c7fe7d25 | 2145 | engine->emit_flush = gen8_render_ring_flush; |
4f044a88 | 2146 | if (i915_modparams.semaphores) { |
98f29e8d CW |
2147 | int num_rings; |
2148 | ||
e2f80391 | 2149 | engine->semaphore.signal = gen8_rcs_signal; |
98f29e8d | 2150 | |
c58949f4 | 2151 | num_rings = INTEL_INFO(dev_priv)->num_rings - 1; |
6f9b850b | 2152 | engine->emit_breadcrumb_sz += num_rings * 8; |
98f29e8d | 2153 | } |
c033666a | 2154 | } else if (INTEL_GEN(dev_priv) >= 6) { |
e2f80391 | 2155 | engine->init_context = intel_rcs_ctx_init; |
c7fe7d25 | 2156 | engine->emit_flush = gen7_render_ring_flush; |
c033666a | 2157 | if (IS_GEN6(dev_priv)) |
c7fe7d25 | 2158 | engine->emit_flush = gen6_render_ring_flush; |
c033666a | 2159 | } else if (IS_GEN5(dev_priv)) { |
c7fe7d25 | 2160 | engine->emit_flush = gen4_render_ring_flush; |
59465b5f | 2161 | } else { |
c033666a | 2162 | if (INTEL_GEN(dev_priv) < 4) |
c7fe7d25 | 2163 | engine->emit_flush = gen2_render_ring_flush; |
46f0f8d1 | 2164 | else |
c7fe7d25 | 2165 | engine->emit_flush = gen4_render_ring_flush; |
e2f80391 | 2166 | engine->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2167 | } |
707d9cf9 | 2168 | |
c033666a | 2169 | if (IS_HASWELL(dev_priv)) |
803688ba | 2170 | engine->emit_bb_start = hsw_emit_bb_start; |
6f7bef75 | 2171 | |
e2f80391 TU |
2172 | engine->init_hw = init_render_ring; |
2173 | engine->cleanup = render_ring_cleanup; | |
59465b5f | 2174 | |
acd27845 | 2175 | ret = intel_init_ring_buffer(engine); |
99be1dfe DV |
2176 | if (ret) |
2177 | return ret; | |
2178 | ||
f8973c21 | 2179 | if (INTEL_GEN(dev_priv) >= 6) { |
f51455d4 | 2180 | ret = intel_engine_create_scratch(engine, PAGE_SIZE); |
7d5ea807 CW |
2181 | if (ret) |
2182 | return ret; | |
2183 | } else if (HAS_BROKEN_CS_TLB(dev_priv)) { | |
56c0f1a7 | 2184 | ret = intel_engine_create_scratch(engine, I830_WA_SIZE); |
99be1dfe DV |
2185 | if (ret) |
2186 | return ret; | |
2187 | } | |
2188 | ||
2189 | return 0; | |
5c1143bb XH |
2190 | } |
2191 | ||
8b3e2d36 | 2192 | int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine) |
5c1143bb | 2193 | { |
8b3e2d36 | 2194 | struct drm_i915_private *dev_priv = engine->i915; |
58fa3835 | 2195 | |
06a2fe22 TU |
2196 | intel_ring_default_vfuncs(dev_priv, engine); |
2197 | ||
c033666a | 2198 | if (INTEL_GEN(dev_priv) >= 6) { |
0fd2c201 | 2199 | /* gen6 bsd needs a special wa for tail updates */ |
c033666a | 2200 | if (IS_GEN6(dev_priv)) |
ff44ad51 | 2201 | engine->set_default_submission = gen6_bsd_set_default_submission; |
c7fe7d25 | 2202 | engine->emit_flush = gen6_bsd_ring_flush; |
c78d6061 | 2203 | if (INTEL_GEN(dev_priv) < 8) |
e2f80391 | 2204 | engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
58fa3835 | 2205 | } else { |
e2f80391 | 2206 | engine->mmio_base = BSD_RING_BASE; |
c7fe7d25 | 2207 | engine->emit_flush = bsd_ring_flush; |
8d228911 | 2208 | if (IS_GEN5(dev_priv)) |
e2f80391 | 2209 | engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
8d228911 | 2210 | else |
e2f80391 | 2211 | engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
58fa3835 | 2212 | } |
58fa3835 | 2213 | |
acd27845 | 2214 | return intel_init_ring_buffer(engine); |
5c1143bb | 2215 | } |
549f7365 | 2216 | |
8b3e2d36 | 2217 | int intel_init_blt_ring_buffer(struct intel_engine_cs *engine) |
549f7365 | 2218 | { |
8b3e2d36 | 2219 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 TU |
2220 | |
2221 | intel_ring_default_vfuncs(dev_priv, engine); | |
2222 | ||
c7fe7d25 | 2223 | engine->emit_flush = gen6_ring_flush; |
c78d6061 | 2224 | if (INTEL_GEN(dev_priv) < 8) |
e2f80391 | 2225 | engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
549f7365 | 2226 | |
acd27845 | 2227 | return intel_init_ring_buffer(engine); |
549f7365 | 2228 | } |
a7b9761d | 2229 | |
8b3e2d36 | 2230 | int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine) |
9a8a2213 | 2231 | { |
8b3e2d36 | 2232 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 TU |
2233 | |
2234 | intel_ring_default_vfuncs(dev_priv, engine); | |
2235 | ||
c7fe7d25 | 2236 | engine->emit_flush = gen6_ring_flush; |
abd58f01 | 2237 | |
c78d6061 | 2238 | if (INTEL_GEN(dev_priv) < 8) { |
e2f80391 | 2239 | engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
31bb59cc CW |
2240 | engine->irq_enable = hsw_vebox_irq_enable; |
2241 | engine->irq_disable = hsw_vebox_irq_disable; | |
abd58f01 | 2242 | } |
9a8a2213 | 2243 | |
acd27845 | 2244 | return intel_init_ring_buffer(engine); |
9a8a2213 | 2245 | } |