projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: Fix kerneldoc for i915_gem_shrink_all
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
CommitLineData
62fdfeaf
EA		 1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
760285e7 30#include <drm/drmP.h>
62fdfeaf 31#include "i915_drv.h"
760285e7 32#include <drm/i915_drm.h>
62fdfeaf 33#include "i915_trace.h"
881f47b6 34#include "intel_drv.h"
62fdfeaf 35
48d82387
OM		 36bool
37intel_ring_initialized(struct intel_engine_cs *ring)
38{
39 struct drm_device *dev = ring->dev;
40
41 if (!dev)
42 return false;
43
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
47
48 return ringbuf->obj;
49 } else
50 return ring->buffer && ring->buffer->obj;
51}
18393f63 52
82e104cc 53int __intel_ring_space(int head, int tail, int size)
c7dca47b 54{
4f54741e
DG		 55 int space = head - tail;
56 if (space <= 0)
1cf0ba14 57 space += size;
4f54741e 58 return space - I915_RING_FREE_SPACE;
c7dca47b
CW		 59}
60
ebd0fd4b
DG		 61void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
62{
63 if (ringbuf->last_retired_head != -1) {
64 ringbuf->head = ringbuf->last_retired_head;
65 ringbuf->last_retired_head = -1;
66 }
67
68 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
69 ringbuf->tail, ringbuf->size);
70}
71
82e104cc 72int intel_ring_space(struct intel_ringbuffer *ringbuf)
1cf0ba14 73{
ebd0fd4b
DG		 74 intel_ring_update_space(ringbuf);
75 return ringbuf->space;
1cf0ba14
CW		 76}
77
82e104cc 78bool intel_ring_stopped(struct intel_engine_cs *ring)
09246732
CW		 79{
80 struct drm_i915_private *dev_priv = ring->dev->dev_private;
88b4aa87
MK		 81 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
82}
09246732 83
6258fbe2 84static void __intel_ring_advance(struct intel_engine_cs *ring)
88b4aa87 85{
93b0a4e0
OM		 86 struct intel_ringbuffer *ringbuf = ring->buffer;
87 ringbuf->tail &= ringbuf->size - 1;
88b4aa87 88 if (intel_ring_stopped(ring))
09246732 89 return;
93b0a4e0 90 ring->write_tail(ring, ringbuf->tail);
09246732
CW		 91}
92
b72f3acb 93static int
a84c3ae1 94gen2_render_ring_flush(struct drm_i915_gem_request *req,
46f0f8d1
CW		 95 u32 invalidate_domains,
96 u32 flush_domains)
97{
a84c3ae1 98 struct intel_engine_cs *ring = req->ring;
46f0f8d1
CW		 99 u32 cmd;
100 int ret;
101
102 cmd = MI_FLUSH;
31b14c9f 103 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
46f0f8d1
CW		 104 cmd |= MI_NO_WRITE_FLUSH;
105
106 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
107 cmd |= MI_READ_FLUSH;
108
5fb9de1a 109 ret = intel_ring_begin(req, 2);
46f0f8d1
CW		 110 if (ret)
111 return ret;
112
113 intel_ring_emit(ring, cmd);
114 intel_ring_emit(ring, MI_NOOP);
115 intel_ring_advance(ring);
116
117 return 0;
118}
119
120static int
a84c3ae1 121gen4_render_ring_flush(struct drm_i915_gem_request *req,
46f0f8d1
CW		 122 u32 invalidate_domains,
123 u32 flush_domains)
62fdfeaf 124{
a84c3ae1 125 struct intel_engine_cs *ring = req->ring;
78501eac 126 struct drm_device *dev = ring->dev;
6f392d54 127 u32 cmd;
b72f3acb 128 int ret;
6f392d54 129
36d527de
CW		 130 /*
131 * read/write caches:
132 *
133 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
134 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
135 * also flushed at 2d versus 3d pipeline switches.
136 *
137 * read-only caches:
138 *
139 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
140 * MI_READ_FLUSH is set, and is always flushed on 965.
141 *
142 * I915_GEM_DOMAIN_COMMAND may not exist?
143 *
144 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
145 * invalidated when MI_EXE_FLUSH is set.
146 *
147 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
148 * invalidated with every MI_FLUSH.
149 *
150 * TLBs:
151 *
152 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
153 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
154 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
155 * are flushed at any MI_FLUSH.
156 */
157
158 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
46f0f8d1 159 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
36d527de 160 cmd &= ~MI_NO_WRITE_FLUSH;
36d527de
CW		 161 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
162 cmd |= MI_EXE_FLUSH;
62fdfeaf 163
36d527de
CW		 164 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
165 (IS_G4X(dev) || IS_GEN5(dev)))
166 cmd |= MI_INVALIDATE_ISP;
70eac33e 167
5fb9de1a 168 ret = intel_ring_begin(req, 2);
36d527de
CW		 169 if (ret)
170 return ret;
b72f3acb 171
36d527de
CW		 172 intel_ring_emit(ring, cmd);
173 intel_ring_emit(ring, MI_NOOP);
174 intel_ring_advance(ring);
b72f3acb
CW		 175
176 return 0;
8187a2b7
ZN		 177}
178
8d315287
JB		 179/**
180 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
181 * implementing two workarounds on gen6. From section 1.4.7.1
182 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
183 *
184 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
185 * produced by non-pipelined state commands), software needs to first
186 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
187 * 0.
188 *
189 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
190 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
191 *
192 * And the workaround for these two requires this workaround first:
193 *
194 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
195 * BEFORE the pipe-control with a post-sync op and no write-cache
196 * flushes.
197 *
198 * And this last workaround is tricky because of the requirements on
199 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
200 * volume 2 part 1:
201 *
202 * "1 of the following must also be set:
203 * - Render Target Cache Flush Enable ([12] of DW1)
204 * - Depth Cache Flush Enable ([0] of DW1)
205 * - Stall at Pixel Scoreboard ([1] of DW1)
206 * - Depth Stall ([13] of DW1)
207 * - Post-Sync Operation ([13] of DW1)
208 * - Notify Enable ([8] of DW1)"
209 *
210 * The cache flushes require the workaround flush that triggered this
211 * one, so we can't use it. Depth stall would trigger the same.
212 * Post-sync nonzero is what triggered this second workaround, so we
213 * can't use that one either. Notify enable is IRQs, which aren't
214 * really our business. That leaves only stall at scoreboard.
215 */
216static int
f2cf1fcc 217intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
8d315287 218{
f2cf1fcc 219 struct intel_engine_cs *ring = req->ring;
18393f63 220 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 221 int ret;
222
5fb9de1a 223 ret = intel_ring_begin(req, 6);
8d315287
JB		 224 if (ret)
225 return ret;
226
227 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
228 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
229 PIPE_CONTROL_STALL_AT_SCOREBOARD);
230 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
231 intel_ring_emit(ring, 0); /* low dword */
232 intel_ring_emit(ring, 0); /* high dword */
233 intel_ring_emit(ring, MI_NOOP);
234 intel_ring_advance(ring);
235
5fb9de1a 236 ret = intel_ring_begin(req, 6);
8d315287
JB		 237 if (ret)
238 return ret;
239
240 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
241 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
242 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
243 intel_ring_emit(ring, 0);
244 intel_ring_emit(ring, 0);
245 intel_ring_emit(ring, MI_NOOP);
246 intel_ring_advance(ring);
247
248 return 0;
249}
250
251static int
a84c3ae1
JH		 252gen6_render_ring_flush(struct drm_i915_gem_request *req,
253 u32 invalidate_domains, u32 flush_domains)
8d315287 254{
a84c3ae1 255 struct intel_engine_cs *ring = req->ring;
8d315287 256 u32 flags = 0;
18393f63 257 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 258 int ret;
259
b3111509 260 /* Force SNB workarounds for PIPE_CONTROL flushes */
f2cf1fcc 261 ret = intel_emit_post_sync_nonzero_flush(req);
b3111509
PZ		 262 if (ret)
263 return ret;
264
8d315287
JB		 265 /* Just flush everything. Experiments have shown that reducing the
266 * number of bits based on the write domains has little performance
267 * impact.
268 */
7d54a904
CW		 269 if (flush_domains) {
270 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
271 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
272 /*
273 * Ensure that any following seqno writes only happen
274 * when the render cache is indeed flushed.
275 */
97f209bc 276 flags |= PIPE_CONTROL_CS_STALL;
7d54a904
CW		 277 }
278 if (invalidate_domains) {
279 flags |= PIPE_CONTROL_TLB_INVALIDATE;
280 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
281 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
282 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
283 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
284 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
285 /*
286 * TLB invalidate requires a post-sync write.
287 */
3ac78313 288 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
7d54a904 289 }
8d315287 290
5fb9de1a 291 ret = intel_ring_begin(req, 4);
8d315287
JB		 292 if (ret)
293 return ret;
294
6c6cf5aa 295 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
8d315287
JB		 296 intel_ring_emit(ring, flags);
297 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
6c6cf5aa 298 intel_ring_emit(ring, 0);
8d315287
JB		 299 intel_ring_advance(ring);
300
301 return 0;
302}
303
f3987631 304static int
f2cf1fcc 305gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
f3987631 306{
f2cf1fcc 307 struct intel_engine_cs *ring = req->ring;
f3987631
PZ		 308 int ret;
309
5fb9de1a 310 ret = intel_ring_begin(req, 4);
f3987631
PZ		 311 if (ret)
312 return ret;
313
314 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
315 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
316 PIPE_CONTROL_STALL_AT_SCOREBOARD);
317 intel_ring_emit(ring, 0);
318 intel_ring_emit(ring, 0);
319 intel_ring_advance(ring);
320
321 return 0;
322}
323
4772eaeb 324static int
a84c3ae1 325gen7_render_ring_flush(struct drm_i915_gem_request *req,
4772eaeb
PZ		 326 u32 invalidate_domains, u32 flush_domains)
327{
a84c3ae1 328 struct intel_engine_cs *ring = req->ring;
4772eaeb 329 u32 flags = 0;
18393f63 330 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
4772eaeb
PZ		 331 int ret;
332
f3987631
PZ		 333 /*
334 * Ensure that any following seqno writes only happen when the render
335 * cache is indeed flushed.
336 *
337 * Workaround: 4th PIPE_CONTROL command (except the ones with only
338 * read-cache invalidate bits set) must have the CS_STALL bit set. We
339 * don't try to be clever and just set it unconditionally.
340 */
341 flags |= PIPE_CONTROL_CS_STALL;
342
4772eaeb
PZ		 343 /* Just flush everything. Experiments have shown that reducing the
344 * number of bits based on the write domains has little performance
345 * impact.
346 */
347 if (flush_domains) {
348 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
349 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
4772eaeb
PZ		 350 }
351 if (invalidate_domains) {
352 flags |= PIPE_CONTROL_TLB_INVALIDATE;
353 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
354 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
355 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
356 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
357 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
148b83d0 358 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
4772eaeb
PZ		 359 /*
360 * TLB invalidate requires a post-sync write.
361 */
362 flags |= PIPE_CONTROL_QW_WRITE;
b9e1faa7 363 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
f3987631 364
add284a3
CW		 365 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
366
f3987631
PZ		 367 /* Workaround: we must issue a pipe_control with CS-stall bit
368 * set before a pipe_control command that has the state cache
369 * invalidate bit set. */
f2cf1fcc 370 gen7_render_ring_cs_stall_wa(req);
4772eaeb
PZ		 371 }
372
5fb9de1a 373 ret = intel_ring_begin(req, 4);
4772eaeb
PZ		 374 if (ret)
375 return ret;
376
377 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
378 intel_ring_emit(ring, flags);
b9e1faa7 379 intel_ring_emit(ring, scratch_addr);
4772eaeb
PZ		 380 intel_ring_emit(ring, 0);
381 intel_ring_advance(ring);
382
383 return 0;
384}
385
884ceace 386static int
f2cf1fcc 387gen8_emit_pipe_control(struct drm_i915_gem_request *req,
884ceace
KG		 388 u32 flags, u32 scratch_addr)
389{
f2cf1fcc 390 struct intel_engine_cs *ring = req->ring;
884ceace
KG		 391 int ret;
392
5fb9de1a 393 ret = intel_ring_begin(req, 6);
884ceace
KG		 394 if (ret)
395 return ret;
396
397 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
398 intel_ring_emit(ring, flags);
399 intel_ring_emit(ring, scratch_addr);
400 intel_ring_emit(ring, 0);
401 intel_ring_emit(ring, 0);
402 intel_ring_emit(ring, 0);
403 intel_ring_advance(ring);
404
405 return 0;
406}
407
a5f3d68e 408static int
a84c3ae1 409gen8_render_ring_flush(struct drm_i915_gem_request *req,
a5f3d68e
BW		 410 u32 invalidate_domains, u32 flush_domains)
411{
412 u32 flags = 0;
f2cf1fcc 413 u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
02c9f7e3 414 int ret;
a5f3d68e
BW		 415
416 flags |= PIPE_CONTROL_CS_STALL;
417
418 if (flush_domains) {
419 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
420 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
421 }
422 if (invalidate_domains) {
423 flags |= PIPE_CONTROL_TLB_INVALIDATE;
424 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
425 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
426 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
427 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
428 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
429 flags |= PIPE_CONTROL_QW_WRITE;
430 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
02c9f7e3
KG		 431
432 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
f2cf1fcc 433 ret = gen8_emit_pipe_control(req,
02c9f7e3
KG		 434 PIPE_CONTROL_CS_STALL |
435 PIPE_CONTROL_STALL_AT_SCOREBOARD,
436 0);
437 if (ret)
438 return ret;
a5f3d68e
BW		 439 }
440
f2cf1fcc 441 return gen8_emit_pipe_control(req, flags, scratch_addr);
a5f3d68e
BW		 442}
443
a4872ba6 444static void ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 445 u32 value)
d46eefa2 446{
4640c4ff 447 struct drm_i915_private *dev_priv = ring->dev->dev_private;
297b0c5b 448 I915_WRITE_TAIL(ring, value);
d46eefa2
XH		 449}
450
a4872ba6 451u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
8187a2b7 452{
4640c4ff 453 struct drm_i915_private *dev_priv = ring->dev->dev_private;
50877445 454 u64 acthd;
8187a2b7 455
50877445
CW		 456 if (INTEL_INFO(ring->dev)->gen >= 8)
457 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
458 RING_ACTHD_UDW(ring->mmio_base));
459 else if (INTEL_INFO(ring->dev)->gen >= 4)
460 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
461 else
462 acthd = I915_READ(ACTHD);
463
464 return acthd;
8187a2b7
ZN		 465}
466
a4872ba6 467static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
035dc1e0
DV		 468{
469 struct drm_i915_private *dev_priv = ring->dev->dev_private;
470 u32 addr;
471
472 addr = dev_priv->status_page_dmah->busaddr;
473 if (INTEL_INFO(ring->dev)->gen >= 4)
474 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
475 I915_WRITE(HWS_PGA, addr);
476}
477
af75f269
DL		 478static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
479{
480 struct drm_device *dev = ring->dev;
481 struct drm_i915_private *dev_priv = ring->dev->dev_private;
482 u32 mmio = 0;
483
484 /* The ring status page addresses are no longer next to the rest of
485 * the ring registers as of gen7.
486 */
487 if (IS_GEN7(dev)) {
488 switch (ring->id) {
489 case RCS:
490 mmio = RENDER_HWS_PGA_GEN7;
491 break;
492 case BCS:
493 mmio = BLT_HWS_PGA_GEN7;
494 break;
495 /*
496 * VCS2 actually doesn't exist on Gen7. Only shut up
497 * gcc switch check warning
498 */
499 case VCS2:
500 case VCS:
501 mmio = BSD_HWS_PGA_GEN7;
502 break;
503 case VECS:
504 mmio = VEBOX_HWS_PGA_GEN7;
505 break;
506 }
507 } else if (IS_GEN6(ring->dev)) {
508 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
509 } else {
510 /* XXX: gen8 returns to sanity */
511 mmio = RING_HWS_PGA(ring->mmio_base);
512 }
513
514 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
515 POSTING_READ(mmio);
516
517 /*
518 * Flush the TLB for this page
519 *
520 * FIXME: These two bits have disappeared on gen8, so a question
521 * arises: do we still need this and if so how should we go about
522 * invalidating the TLB?
523 */
524 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
525 u32 reg = RING_INSTPM(ring->mmio_base);
526
527 /* ring should be idle before issuing a sync flush*/
528 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
529
530 I915_WRITE(reg,
531 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
532 INSTPM_SYNC_FLUSH));
533 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
534 1000))
535 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
536 ring->name);
537 }
538}
539
a4872ba6 540static bool stop_ring(struct intel_engine_cs *ring)
8187a2b7 541{
9991ae78 542 struct drm_i915_private *dev_priv = to_i915(ring->dev);
8187a2b7 543
9991ae78
CW		 544 if (!IS_GEN2(ring->dev)) {
545 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
403bdd10
DV		 546 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
547 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
9bec9b13
CW		 548 /* Sometimes we observe that the idle flag is not
549 * set even though the ring is empty. So double
550 * check before giving up.
551 */
552 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
553 return false;
9991ae78
CW		 554 }
555 }
b7884eb4 556
7f2ab699 557 I915_WRITE_CTL(ring, 0);
570ef608 558 I915_WRITE_HEAD(ring, 0);
78501eac 559 ring->write_tail(ring, 0);
8187a2b7 560
9991ae78
CW		 561 if (!IS_GEN2(ring->dev)) {
562 (void)I915_READ_CTL(ring);
563 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
564 }
a51435a3 565
9991ae78
CW		 566 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
567}
8187a2b7 568
a4872ba6 569static int init_ring_common(struct intel_engine_cs *ring)
9991ae78
CW		 570{
571 struct drm_device *dev = ring->dev;
572 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0
OM		 573 struct intel_ringbuffer *ringbuf = ring->buffer;
574 struct drm_i915_gem_object *obj = ringbuf->obj;
9991ae78
CW		 575 int ret = 0;
576
59bad947 577 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9991ae78
CW		 578
579 if (!stop_ring(ring)) {
580 /* G45 ring initialization often fails to reset head to zero */
6fd0d56e
CW		 581 DRM_DEBUG_KMS("%s head not reset to zero "
582 "ctl %08x head %08x tail %08x start %08x\n",
583 ring->name,
584 I915_READ_CTL(ring),
585 I915_READ_HEAD(ring),
586 I915_READ_TAIL(ring),
587 I915_READ_START(ring));
8187a2b7 588
9991ae78 589 if (!stop_ring(ring)) {
6fd0d56e
CW		 590 DRM_ERROR("failed to set %s head to zero "
591 "ctl %08x head %08x tail %08x start %08x\n",
592 ring->name,
593 I915_READ_CTL(ring),
594 I915_READ_HEAD(ring),
595 I915_READ_TAIL(ring),
596 I915_READ_START(ring));
9991ae78
CW		 597 ret = -EIO;
598 goto out;
6fd0d56e 599 }
8187a2b7
ZN		 600 }
601
9991ae78
CW		 602 if (I915_NEED_GFX_HWS(dev))
603 intel_ring_setup_status_page(ring);
604 else
605 ring_setup_phys_status_page(ring);
606
ece4a17d
JK		 607 /* Enforce ordering by reading HEAD register back */
608 I915_READ_HEAD(ring);
609
0d8957c8
DV		 610 /* Initialize the ring. This must happen _after_ we've cleared the ring
611 * registers with the above sequence (the readback of the HEAD registers
612 * also enforces ordering), otherwise the hw might lose the new ring
613 * register values. */
f343c5f6 614 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
95468892
CW		 615
616 /* WaClearRingBufHeadRegAtInit:ctg,elk */
617 if (I915_READ_HEAD(ring))
618 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
619 ring->name, I915_READ_HEAD(ring));
620 I915_WRITE_HEAD(ring, 0);
621 (void)I915_READ_HEAD(ring);
622
7f2ab699 623 I915_WRITE_CTL(ring,
93b0a4e0 624 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
5d031e5b 625 | RING_VALID);
8187a2b7 626
8187a2b7 627 /* If the head is still not zero, the ring is dead */
f01db988 628 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
f343c5f6 629 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
f01db988 630 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
e74cfed5 631 DRM_ERROR("%s initialization failed "
48e48a0b
CW		 632 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
633 ring->name,
634 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
635 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
636 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
b7884eb4
DV		 637 ret = -EIO;
638 goto out;
8187a2b7
ZN		 639 }
640
ebd0fd4b 641 ringbuf->last_retired_head = -1;
5c6c6003
CW		 642 ringbuf->head = I915_READ_HEAD(ring);
643 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
ebd0fd4b 644 intel_ring_update_space(ringbuf);
1ec14ad3 645
50f018df
CW		 646 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
647
b7884eb4 648out:
59bad947 649 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b7884eb4
DV		 650
651 return ret;
8187a2b7
ZN		 652}
653
9b1136d5
OM		 654void
655intel_fini_pipe_control(struct intel_engine_cs *ring)
656{
657 struct drm_device *dev = ring->dev;
658
659 if (ring->scratch.obj == NULL)
660 return;
661
662 if (INTEL_INFO(dev)->gen >= 5) {
663 kunmap(sg_page(ring->scratch.obj->pages->sgl));
664 i915_gem_object_ggtt_unpin(ring->scratch.obj);
665 }
666
667 drm_gem_object_unreference(&ring->scratch.obj->base);
668 ring->scratch.obj = NULL;
669}
670
671int
672intel_init_pipe_control(struct intel_engine_cs *ring)
c6df541c 673{
c6df541c
CW		 674 int ret;
675
bfc882b4 676 WARN_ON(ring->scratch.obj);
c6df541c 677
0d1aacac
CW		 678 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
679 if (ring->scratch.obj == NULL) {
c6df541c
CW		 680 DRM_ERROR("Failed to allocate seqno page\n");
681 ret = -ENOMEM;
682 goto err;
683 }
e4ffd173 684
a9cc726c
DV		 685 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
686 if (ret)
687 goto err_unref;
c6df541c 688
1ec9e26d 689 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
c6df541c
CW		 690 if (ret)
691 goto err_unref;
692
0d1aacac
CW		 693 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
694 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
695 if (ring->scratch.cpu_page == NULL) {
56b085a0 696 ret = -ENOMEM;
c6df541c 697 goto err_unpin;
56b085a0 698 }
c6df541c 699
2b1086cc 700 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
0d1aacac 701 ring->name, ring->scratch.gtt_offset);
c6df541c
CW		 702 return 0;
703
704err_unpin:
d7f46fc4 705 i915_gem_object_ggtt_unpin(ring->scratch.obj);
c6df541c 706err_unref:
0d1aacac 707 drm_gem_object_unreference(&ring->scratch.obj->base);
c6df541c 708err:
c6df541c
CW		 709 return ret;
710}
711
e2be4faf 712static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
86d7f238 713{
7225342a 714 int ret, i;
e2be4faf 715 struct intel_engine_cs *ring = req->ring;
888b5995
AS		 716 struct drm_device *dev = ring->dev;
717 struct drm_i915_private *dev_priv = dev->dev_private;
7225342a 718 struct i915_workarounds *w = &dev_priv->workarounds;
888b5995 719
e6c1abb7 720 if (WARN_ON_ONCE(w->count == 0))
7225342a 721 return 0;
888b5995 722
7225342a 723 ring->gpu_caches_dirty = true;
4866d729 724 ret = intel_ring_flush_all_caches(req);
7225342a
MK		 725 if (ret)
726 return ret;
888b5995 727
5fb9de1a 728 ret = intel_ring_begin(req, (w->count * 2 + 2));
7225342a
MK		 729 if (ret)
730 return ret;
731
22a916aa 732 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
7225342a 733 for (i = 0; i < w->count; i++) {
7225342a
MK		 734 intel_ring_emit(ring, w->reg[i].addr);
735 intel_ring_emit(ring, w->reg[i].value);
736 }
22a916aa 737 intel_ring_emit(ring, MI_NOOP);
7225342a
MK		 738
739 intel_ring_advance(ring);
740
741 ring->gpu_caches_dirty = true;
4866d729 742 ret = intel_ring_flush_all_caches(req);
7225342a
MK		 743 if (ret)
744 return ret;
888b5995 745
7225342a 746 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
888b5995 747
7225342a 748 return 0;
86d7f238
AS		 749}
750
8753181e 751static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
8f0e2b9d
DV		 752{
753 int ret;
754
e2be4faf 755 ret = intel_ring_workarounds_emit(req);
8f0e2b9d
DV		 756 if (ret != 0)
757 return ret;
758
be01363f 759 ret = i915_gem_render_state_init(req);
8f0e2b9d
DV		 760 if (ret)
761 DRM_ERROR("init render state: %d\n", ret);
762
763 return ret;
764}
765
7225342a 766static int wa_add(struct drm_i915_private *dev_priv,
cf4b0de6 767 const u32 addr, const u32 mask, const u32 val)
7225342a
MK		 768{
769 const u32 idx = dev_priv->workarounds.count;
770
771 if (WARN_ON(idx >= I915_MAX_WA_REGS))
772 return -ENOSPC;
773
774 dev_priv->workarounds.reg[idx].addr = addr;
775 dev_priv->workarounds.reg[idx].value = val;
776 dev_priv->workarounds.reg[idx].mask = mask;
777
778 dev_priv->workarounds.count++;
779
780 return 0;
86d7f238
AS		 781}
782
ca5a0fbd 783#define WA_REG(addr, mask, val) do { \
cf4b0de6 784 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
7225342a
MK		 785 if (r) \
786 return r; \
ca5a0fbd 787 } while (0)
7225342a
MK		 788
789#define WA_SET_BIT_MASKED(addr, mask) \
26459343 790 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
7225342a
MK		 791
792#define WA_CLR_BIT_MASKED(addr, mask) \
26459343 793 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
7225342a 794
98533251 795#define WA_SET_FIELD_MASKED(addr, mask, value) \
cf4b0de6 796 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
7225342a 797
cf4b0de6
DL		 798#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
799#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
7225342a 800
cf4b0de6 801#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
7225342a 802
00e1e623 803static int bdw_init_workarounds(struct intel_engine_cs *ring)
86d7f238 804{
888b5995
AS		 805 struct drm_device *dev = ring->dev;
806 struct drm_i915_private *dev_priv = dev->dev_private;
86d7f238 807
9cc83020
VS		 808 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
809
2441f877
VS		 810 /* WaDisableAsyncFlipPerfMode:bdw */
811 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
812
86d7f238 813 /* WaDisablePartialInstShootdown:bdw */
101b376d 814 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
7225342a
MK		 815 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
816 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
817 STALL_DOP_GATING_DISABLE);
86d7f238 818
101b376d 819 /* WaDisableDopClockGating:bdw */
7225342a
MK		 820 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
821 DOP_CLOCK_GATING_DISABLE);
86d7f238 822
7225342a
MK		 823 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
824 GEN8_SAMPLER_POWER_BYPASS_DIS);
86d7f238
AS		 825
826 /* Use Force Non-Coherent whenever executing a 3D context. This is a
827 * workaround for for a possible hang in the unlikely event a TLB
828 * invalidation occurs during a PSD flush.
829 */
7225342a 830 WA_SET_BIT_MASKED(HDC_CHICKEN0,
35cb6f3b 831 /* WaForceEnableNonCoherent:bdw */
7225342a 832 HDC_FORCE_NON_COHERENT |
35cb6f3b
DL		 833 /* WaForceContextSaveRestoreNonCoherent:bdw */
834 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
835 /* WaHdcDisableFetchWhenMasked:bdw */
f3f32360 836 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
35cb6f3b 837 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
7225342a 838 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
86d7f238 839
2701fc43
KG		 840 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
841 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
842 * polygons in the same 8x4 pixel/sample area to be processed without
843 * stalling waiting for the earlier ones to write to Hierarchical Z
844 * buffer."
845 *
846 * This optimization is off by default for Broadwell; turn it on.
847 */
848 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
849
86d7f238 850 /* Wa4x4STCOptimizationDisable:bdw */
7225342a
MK		 851 WA_SET_BIT_MASKED(CACHE_MODE_1,
852 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
86d7f238
AS		 853
854 /*
855 * BSpec recommends 8x4 when MSAA is used,
856 * however in practice 16x4 seems fastest.
857 *
858 * Note that PS/WM thread counts depend on the WIZ hashing
859 * disable bit, which we don't touch here, but it's good
860 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
861 */
98533251
DL		 862 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
863 GEN6_WIZ_HASHING_MASK,
864 GEN6_WIZ_HASHING_16x4);
888b5995 865
86d7f238
AS		 866 return 0;
867}
868
00e1e623
VS		 869static int chv_init_workarounds(struct intel_engine_cs *ring)
870{
00e1e623
VS		 871 struct drm_device *dev = ring->dev;
872 struct drm_i915_private *dev_priv = dev->dev_private;
873
9cc83020
VS		 874 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
875
2441f877
VS		 876 /* WaDisableAsyncFlipPerfMode:chv */
877 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
878
00e1e623 879 /* WaDisablePartialInstShootdown:chv */
00e1e623 880 /* WaDisableThreadStallDopClockGating:chv */
7225342a 881 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
605f1433
AS		 882 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
883 STALL_DOP_GATING_DISABLE);
00e1e623 884
95289009
AS		 885 /* Use Force Non-Coherent whenever executing a 3D context. This is a
886 * workaround for a possible hang in the unlikely event a TLB
887 * invalidation occurs during a PSD flush.
888 */
889 /* WaForceEnableNonCoherent:chv */
890 /* WaHdcDisableFetchWhenMasked:chv */
891 WA_SET_BIT_MASKED(HDC_CHICKEN0,
892 HDC_FORCE_NON_COHERENT |
893 HDC_DONOT_FETCH_MEM_WHEN_MASKED);
894
973a5b06
KG		 895 /* According to the CACHE_MODE_0 default value documentation, some
896 * CHV platforms disable this optimization by default. Turn it on.
897 */
898 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
899
14bc16e3
VS		 900 /* Wa4x4STCOptimizationDisable:chv */
901 WA_SET_BIT_MASKED(CACHE_MODE_1,
902 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
903
d60de81d
KG		 904 /* Improve HiZ throughput on CHV. */
905 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
906
e7fc2436
VS		 907 /*
908 * BSpec recommends 8x4 when MSAA is used,
909 * however in practice 16x4 seems fastest.
910 *
911 * Note that PS/WM thread counts depend on the WIZ hashing
912 * disable bit, which we don't touch here, but it's good
913 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
914 */
915 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
916 GEN6_WIZ_HASHING_MASK,
917 GEN6_WIZ_HASHING_16x4);
918
7225342a
MK		 919 return 0;
920}
921
3b106531
HN		 922static int gen9_init_workarounds(struct intel_engine_cs *ring)
923{
ab0dfafe
HN		 924 struct drm_device *dev = ring->dev;
925 struct drm_i915_private *dev_priv = dev->dev_private;
8ea6f892 926 uint32_t tmp;
ab0dfafe 927
b0e6f6d4 928 /* WaDisablePartialInstShootdown:skl,bxt */
ab0dfafe
HN		 929 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
930 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
931
a119a6e6 932 /* Syncing dependencies between camera and graphics:skl,bxt */
8424171e
NH		 933 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
934 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
935
d2a31dbd
NH		 936 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 ||
937 INTEL_REVID(dev) == SKL_REVID_B0)) ||
938 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
939 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
a86eb582
DL		 940 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
941 GEN9_DG_MIRROR_FIX_ENABLE);
1de4582f
NH		 942 }
943
a13d215f
NH		 944 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
945 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
946 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
183c6dac
DL		 947 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
948 GEN9_RHWO_OPTIMIZATION_DISABLE);
9b01435d
AS		 949 /*
950 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
951 * but we do that in per ctx batchbuffer as there is an issue
952 * with this register not getting restored on ctx restore
953 */
183c6dac
DL		 954 }
955
27a1b688
NH		 956 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
957 IS_BROXTON(dev)) {
958 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
cac23df4
NH		 959 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
960 GEN9_ENABLE_YV12_BUGFIX);
961 }
962
5068368c 963 /* Wa4x4STCOptimizationDisable:skl,bxt */
1840481f
HN		 964 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
965
27160c96 966 /* WaDisablePartialResolveInVc:skl,bxt */
9370cd98
DL		 967 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
968
16be17af 969 /* WaCcsTlbPrefetchDisable:skl,bxt */
e2db7071
DL		 970 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
971 GEN9_CCS_TLB_PREFETCH_ENABLE);
972
5a2ae95e
ID		 973 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
974 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) ||
975 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0))
38a39a7b
BW		 976 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
977 PIXEL_MASK_CAMMING_DISABLE);
978
8ea6f892
ID		 979 /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
980 tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
981 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) ||
982 (IS_BROXTON(dev) && INTEL_REVID(dev) >= BXT_REVID_B0))
983 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
984 WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
985
3b106531
HN		 986 return 0;
987}
988
b7668791
DL		 989static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
990{
991 struct drm_device *dev = ring->dev;
992 struct drm_i915_private *dev_priv = dev->dev_private;
993 u8 vals[3] = { 0, 0, 0 };
994 unsigned int i;
995
996 for (i = 0; i < 3; i++) {
997 u8 ss;
998
999 /*
1000 * Only consider slices where one, and only one, subslice has 7
1001 * EUs
1002 */
1003 if (hweight8(dev_priv->info.subslice_7eu[i]) != 1)
1004 continue;
1005
1006 /*
1007 * subslice_7eu[i] != 0 (because of the check above) and
1008 * ss_max == 4 (maximum number of subslices possible per slice)
1009 *
1010 * -> 0 <= ss <= 3;
1011 */
1012 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1013 vals[i] = 3 - ss;
1014 }
1015
1016 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1017 return 0;
1018
1019 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1020 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1021 GEN9_IZ_HASHING_MASK(2) |
1022 GEN9_IZ_HASHING_MASK(1) |
1023 GEN9_IZ_HASHING_MASK(0),
1024 GEN9_IZ_HASHING(2, vals[2]) |
1025 GEN9_IZ_HASHING(1, vals[1]) |
1026 GEN9_IZ_HASHING(0, vals[0]));
1027
1028 return 0;
1029}
1030
1031
8d205494
DL		 1032static int skl_init_workarounds(struct intel_engine_cs *ring)
1033{
d0bbbc4f
DL		 1034 struct drm_device *dev = ring->dev;
1035 struct drm_i915_private *dev_priv = dev->dev_private;
1036
8d205494
DL		 1037 gen9_init_workarounds(ring);
1038
d0bbbc4f
DL		 1039 /* WaDisablePowerCompilerClockGating:skl */
1040 if (INTEL_REVID(dev) == SKL_REVID_B0)
1041 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1042 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1043
b62adbd1
NH		 1044 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
1045 /*
1046 *Use Force Non-Coherent whenever executing a 3D context. This
1047 * is a workaround for a possible hang in the unlikely event
1048 * a TLB invalidation occurs during a PSD flush.
1049 */
1050 /* WaForceEnableNonCoherent:skl */
1051 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1052 HDC_FORCE_NON_COHERENT);
1053 }
1054
5b6fd12a
VS		 1055 if (INTEL_REVID(dev) == SKL_REVID_C0 ||
1056 INTEL_REVID(dev) == SKL_REVID_D0)
1057 /* WaBarrierPerformanceFixDisable:skl */
1058 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1059 HDC_FENCE_DEST_SLM_DISABLE |
1060 HDC_BARRIER_PERFORMANCE_DISABLE);
1061
9bd9dfb4
MK		 1062 /* WaDisableSbeCacheDispatchPortSharing:skl */
1063 if (INTEL_REVID(dev) <= SKL_REVID_F0) {
1064 WA_SET_BIT_MASKED(
1065 GEN7_HALF_SLICE_CHICKEN1,
1066 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1067 }
1068
b7668791 1069 return skl_tune_iz_hashing(ring);
7225342a
MK		 1070}
1071
cae0437f
NH		 1072static int bxt_init_workarounds(struct intel_engine_cs *ring)
1073{
dfb601e6
NH		 1074 struct drm_device *dev = ring->dev;
1075 struct drm_i915_private *dev_priv = dev->dev_private;
1076
cae0437f
NH		 1077 gen9_init_workarounds(ring);
1078
dfb601e6
NH		 1079 /* WaDisableThreadStallDopClockGating:bxt */
1080 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1081 STALL_DOP_GATING_DISABLE);
1082
983b4b9d
NH		 1083 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1084 if (INTEL_REVID(dev) <= BXT_REVID_B0) {
1085 WA_SET_BIT_MASKED(
1086 GEN7_HALF_SLICE_CHICKEN1,
1087 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1088 }
1089
cae0437f
NH		 1090 return 0;
1091}
1092
771b9a53 1093int init_workarounds_ring(struct intel_engine_cs *ring)
7225342a
MK		 1094{
1095 struct drm_device *dev = ring->dev;
1096 struct drm_i915_private *dev_priv = dev->dev_private;
1097
1098 WARN_ON(ring->id != RCS);
1099
1100 dev_priv->workarounds.count = 0;
1101
1102 if (IS_BROADWELL(dev))
1103 return bdw_init_workarounds(ring);
1104
1105 if (IS_CHERRYVIEW(dev))
1106 return chv_init_workarounds(ring);
00e1e623 1107
8d205494
DL		 1108 if (IS_SKYLAKE(dev))
1109 return skl_init_workarounds(ring);
cae0437f
NH		 1110
1111 if (IS_BROXTON(dev))
1112 return bxt_init_workarounds(ring);
3b106531 1113
00e1e623
VS		 1114 return 0;
1115}
1116
a4872ba6 1117static int init_render_ring(struct intel_engine_cs *ring)
8187a2b7 1118{
78501eac 1119 struct drm_device *dev = ring->dev;
1ec14ad3 1120 struct drm_i915_private *dev_priv = dev->dev_private;
78501eac 1121 int ret = init_ring_common(ring);
9c33baa6
KZ		 1122 if (ret)
1123 return ret;
a69ffdbf 1124
61a563a2
AG		 1125 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1126 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
6b26c86d 1127 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1c8c38c5
CW		 1128
1129 /* We need to disable the AsyncFlip performance optimisations in order
1130 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1131 * programmed to '1' on all products.
8693a824 1132 *
2441f877 1133 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1c8c38c5 1134 */
2441f877 1135 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1c8c38c5
CW		 1136 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1137
f05bb0c7 1138 /* Required for the hardware to program scanline values for waiting */
01fa0302 1139 /* WaEnableFlushTlbInvalidationMode:snb */
f05bb0c7
CW		 1140 if (INTEL_INFO(dev)->gen == 6)
1141 I915_WRITE(GFX_MODE,
aa83e30d 1142 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
f05bb0c7 1143
01fa0302 1144 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1c8c38c5
CW		 1145 if (IS_GEN7(dev))
1146 I915_WRITE(GFX_MODE_GEN7,
01fa0302 1147 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1c8c38c5 1148 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
78501eac 1149
5e13a0c5 1150 if (IS_GEN6(dev)) {
3a69ddd6
KG		 1151 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1152 * "If this bit is set, STCunit will have LRA as replacement
1153 * policy. [...] This bit must be reset. LRA replacement
1154 * policy is not supported."
1155 */
1156 I915_WRITE(CACHE_MODE_0,
5e13a0c5 1157 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
84f9f938
BW		 1158 }
1159
9cc83020 1160 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
6b26c86d 1161 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
84f9f938 1162
040d2baa 1163 if (HAS_L3_DPF(dev))
35a85ac6 1164 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e 1165
7225342a 1166 return init_workarounds_ring(ring);
8187a2b7
ZN		 1167}
1168
a4872ba6 1169static void render_ring_cleanup(struct intel_engine_cs *ring)
c6df541c 1170{
b45305fc 1171 struct drm_device *dev = ring->dev;
3e78998a
BW		 1172 struct drm_i915_private *dev_priv = dev->dev_private;
1173
1174 if (dev_priv->semaphore_obj) {
1175 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1176 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1177 dev_priv->semaphore_obj = NULL;
1178 }
b45305fc 1179
9b1136d5 1180 intel_fini_pipe_control(ring);
c6df541c
CW		 1181}
1182
f7169687 1183static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
3e78998a
BW		 1184 unsigned int num_dwords)
1185{
1186#define MBOX_UPDATE_DWORDS 8
f7169687 1187 struct intel_engine_cs *signaller = signaller_req->ring;
3e78998a
BW		 1188 struct drm_device *dev = signaller->dev;
1189 struct drm_i915_private *dev_priv = dev->dev_private;
1190 struct intel_engine_cs *waiter;
1191 int i, ret, num_rings;
1192
1193 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1194 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1195#undef MBOX_UPDATE_DWORDS
1196
5fb9de1a 1197 ret = intel_ring_begin(signaller_req, num_dwords);
3e78998a
BW		 1198 if (ret)
1199 return ret;
1200
1201 for_each_ring(waiter, dev_priv, i) {
6259cead 1202 u32 seqno;
3e78998a
BW		 1203 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1204 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1205 continue;
1206
f7169687 1207 seqno = i915_gem_request_get_seqno(signaller_req);
3e78998a
BW		 1208 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1209 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1210 PIPE_CONTROL_QW_WRITE |
1211 PIPE_CONTROL_FLUSH_ENABLE);
1212 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1213 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1214 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1215 intel_ring_emit(signaller, 0);
1216 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1217 MI_SEMAPHORE_TARGET(waiter->id));
1218 intel_ring_emit(signaller, 0);
1219 }
1220
1221 return 0;
1222}
1223
f7169687 1224static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
3e78998a
BW		 1225 unsigned int num_dwords)
1226{
1227#define MBOX_UPDATE_DWORDS 6
f7169687 1228 struct intel_engine_cs *signaller = signaller_req->ring;
3e78998a
BW		 1229 struct drm_device *dev = signaller->dev;
1230 struct drm_i915_private *dev_priv = dev->dev_private;
1231 struct intel_engine_cs *waiter;
1232 int i, ret, num_rings;
1233
1234 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1235 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1236#undef MBOX_UPDATE_DWORDS
1237
5fb9de1a 1238 ret = intel_ring_begin(signaller_req, num_dwords);
3e78998a
BW		 1239 if (ret)
1240 return ret;
1241
1242 for_each_ring(waiter, dev_priv, i) {
6259cead 1243 u32 seqno;
3e78998a
BW		 1244 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1245 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1246 continue;
1247
f7169687 1248 seqno = i915_gem_request_get_seqno(signaller_req);
3e78998a
BW		 1249 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1250 MI_FLUSH_DW_OP_STOREDW);
1251 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1252 MI_FLUSH_DW_USE_GTT);
1253 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1254 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1255 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1256 MI_SEMAPHORE_TARGET(waiter->id));
1257 intel_ring_emit(signaller, 0);
1258 }
1259
1260 return 0;
1261}
1262
f7169687 1263static int gen6_signal(struct drm_i915_gem_request *signaller_req,
024a43e1 1264 unsigned int num_dwords)
1ec14ad3 1265{
f7169687 1266 struct intel_engine_cs *signaller = signaller_req->ring;
024a43e1
BW		 1267 struct drm_device *dev = signaller->dev;
1268 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1269 struct intel_engine_cs *useless;
a1444b79 1270 int i, ret, num_rings;
78325f2d 1271
a1444b79
BW		 1272#define MBOX_UPDATE_DWORDS 3
1273 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1274 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1275#undef MBOX_UPDATE_DWORDS
024a43e1 1276
5fb9de1a 1277 ret = intel_ring_begin(signaller_req, num_dwords);
024a43e1
BW		 1278 if (ret)
1279 return ret;
024a43e1 1280
78325f2d
BW		 1281 for_each_ring(useless, dev_priv, i) {
1282 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1283 if (mbox_reg != GEN6_NOSYNC) {
f7169687 1284 u32 seqno = i915_gem_request_get_seqno(signaller_req);
78325f2d
BW		 1285 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1286 intel_ring_emit(signaller, mbox_reg);
6259cead 1287 intel_ring_emit(signaller, seqno);
78325f2d
BW		 1288 }
1289 }
024a43e1 1290
a1444b79
BW		 1291 /* If num_dwords was rounded, make sure the tail pointer is correct */
1292 if (num_rings % 2 == 0)
1293 intel_ring_emit(signaller, MI_NOOP);
1294
024a43e1 1295 return 0;
1ec14ad3
CW		 1296}
1297
c8c99b0f
BW		 1298/**
1299 * gen6_add_request - Update the semaphore mailbox registers
ee044a88
JH		 1300 *
1301 * @request - request to write to the ring
c8c99b0f
BW		 1302 *
1303 * Update the mailbox registers in the *other* rings with the current seqno.
1304 * This acts like a signal in the canonical semaphore.
1305 */
1ec14ad3 1306static int
ee044a88 1307gen6_add_request(struct drm_i915_gem_request *req)
1ec14ad3 1308{
ee044a88 1309 struct intel_engine_cs *ring = req->ring;
024a43e1 1310 int ret;
52ed2325 1311
707d9cf9 1312 if (ring->semaphore.signal)
f7169687 1313 ret = ring->semaphore.signal(req, 4);
707d9cf9 1314 else
5fb9de1a 1315 ret = intel_ring_begin(req, 4);
707d9cf9 1316
1ec14ad3
CW		 1317 if (ret)
1318 return ret;
1319
1ec14ad3
CW		 1320 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1321 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
ee044a88 1322 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1ec14ad3 1323 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1324 __intel_ring_advance(ring);
1ec14ad3 1325
1ec14ad3
CW		 1326 return 0;
1327}
1328
f72b3435
MK		 1329static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1330 u32 seqno)
1331{
1332 struct drm_i915_private *dev_priv = dev->dev_private;
1333 return dev_priv->last_seqno < seqno;
1334}
1335
c8c99b0f
BW		 1336/**
1337 * intel_ring_sync - sync the waiter to the signaller on seqno
1338 *
1339 * @waiter - ring that is waiting
1340 * @signaller - ring which has, or will signal
1341 * @seqno - seqno which the waiter will block on
1342 */
5ee426ca
BW		 1343
1344static int
599d924c 1345gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
5ee426ca
BW		 1346 struct intel_engine_cs *signaller,
1347 u32 seqno)
1348{
599d924c 1349 struct intel_engine_cs *waiter = waiter_req->ring;
5ee426ca
BW		 1350 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1351 int ret;
1352
5fb9de1a 1353 ret = intel_ring_begin(waiter_req, 4);
5ee426ca
BW		 1354 if (ret)
1355 return ret;
1356
1357 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1358 MI_SEMAPHORE_GLOBAL_GTT |
bae4fcd2 1359 MI_SEMAPHORE_POLL |
5ee426ca
BW		 1360 MI_SEMAPHORE_SAD_GTE_SDD);
1361 intel_ring_emit(waiter, seqno);
1362 intel_ring_emit(waiter,
1363 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1364 intel_ring_emit(waiter,
1365 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1366 intel_ring_advance(waiter);
1367 return 0;
1368}
1369
c8c99b0f 1370static int
599d924c 1371gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
a4872ba6 1372 struct intel_engine_cs *signaller,
686cb5f9 1373 u32 seqno)
1ec14ad3 1374{
599d924c 1375 struct intel_engine_cs *waiter = waiter_req->ring;
c8c99b0f
BW		 1376 u32 dw1 = MI_SEMAPHORE_MBOX |
1377 MI_SEMAPHORE_COMPARE |
1378 MI_SEMAPHORE_REGISTER;
ebc348b2
BW		 1379 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1380 int ret;
1ec14ad3 1381
1500f7ea
BW		 1382 /* Throughout all of the GEM code, seqno passed implies our current
1383 * seqno is >= the last seqno executed. However for hardware the
1384 * comparison is strictly greater than.
1385 */
1386 seqno -= 1;
1387
ebc348b2 1388 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
686cb5f9 1389
5fb9de1a 1390 ret = intel_ring_begin(waiter_req, 4);
1ec14ad3
CW		 1391 if (ret)
1392 return ret;
1393
f72b3435
MK		 1394 /* If seqno wrap happened, omit the wait with no-ops */
1395 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
ebc348b2 1396 intel_ring_emit(waiter, dw1 | wait_mbox);
f72b3435
MK		 1397 intel_ring_emit(waiter, seqno);
1398 intel_ring_emit(waiter, 0);
1399 intel_ring_emit(waiter, MI_NOOP);
1400 } else {
1401 intel_ring_emit(waiter, MI_NOOP);
1402 intel_ring_emit(waiter, MI_NOOP);
1403 intel_ring_emit(waiter, MI_NOOP);
1404 intel_ring_emit(waiter, MI_NOOP);
1405 }
c8c99b0f 1406 intel_ring_advance(waiter);
1ec14ad3
CW		 1407
1408 return 0;
1409}
1410
c6df541c
CW		 1411#define PIPE_CONTROL_FLUSH(ring__, addr__) \
1412do { \
fcbc34e4
KG		 1413 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1414 PIPE_CONTROL_DEPTH_STALL); \
c6df541c
CW		 1415 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1416 intel_ring_emit(ring__, 0); \
1417 intel_ring_emit(ring__, 0); \
1418} while (0)
1419
1420static int
ee044a88 1421pc_render_add_request(struct drm_i915_gem_request *req)
c6df541c 1422{
ee044a88 1423 struct intel_engine_cs *ring = req->ring;
18393f63 1424 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
c6df541c
CW		 1425 int ret;
1426
1427 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1428 * incoherent with writes to memory, i.e. completely fubar,
1429 * so we need to use PIPE_NOTIFY instead.
1430 *
1431 * However, we also need to workaround the qword write
1432 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1433 * memory before requesting an interrupt.
1434 */
5fb9de1a 1435 ret = intel_ring_begin(req, 32);
c6df541c
CW		 1436 if (ret)
1437 return ret;
1438
fcbc34e4 1439 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1440 PIPE_CONTROL_WRITE_FLUSH |
1441 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
0d1aacac 1442 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
ee044a88 1443 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
c6df541c
CW		 1444 intel_ring_emit(ring, 0);
1445 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1446 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
c6df541c 1447 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1448 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1449 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1450 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1451 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1452 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1453 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1454 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1455 PIPE_CONTROL_FLUSH(ring, scratch_addr);
a71d8d94 1456
fcbc34e4 1457 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1458 PIPE_CONTROL_WRITE_FLUSH |
1459 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
c6df541c 1460 PIPE_CONTROL_NOTIFY);
0d1aacac 1461 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
ee044a88 1462 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
c6df541c 1463 intel_ring_emit(ring, 0);
09246732 1464 __intel_ring_advance(ring);
c6df541c 1465
c6df541c
CW		 1466 return 0;
1467}
1468
4cd53c0c 1469static u32
a4872ba6 1470gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
4cd53c0c 1471{
4cd53c0c
DV		 1472 /* Workaround to force correct ordering between irq and seqno writes on
1473 * ivb (and maybe also on snb) by reading from a CS register (like
1474 * ACTHD) before reading the status page. */
50877445
CW		 1475 if (!lazy_coherency) {
1476 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1477 POSTING_READ(RING_ACTHD(ring->mmio_base));
1478 }
1479
4cd53c0c
DV		 1480 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1481}
1482
8187a2b7 1483static u32
a4872ba6 1484ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
8187a2b7 1485{
1ec14ad3
CW		 1486 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1487}
1488
b70ec5bf 1489static void
a4872ba6 1490ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf
MK		 1491{
1492 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1493}
1494
c6df541c 1495static u32
a4872ba6 1496pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
c6df541c 1497{
0d1aacac 1498 return ring->scratch.cpu_page[0];
c6df541c
CW		 1499}
1500
b70ec5bf 1501static void
a4872ba6 1502pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf 1503{
0d1aacac 1504 ring->scratch.cpu_page[0] = seqno;
b70ec5bf
MK		 1505}
1506
e48d8634 1507static bool
a4872ba6 1508gen5_ring_get_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1509{
1510 struct drm_device *dev = ring->dev;
4640c4ff 1511 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1512 unsigned long flags;
e48d8634 1513
7cd512f1 1514 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
e48d8634
DV		 1515 return false;
1516
7338aefa 1517 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1518 if (ring->irq_refcount++ == 0)
480c8033 1519 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1520 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1521
1522 return true;
1523}
1524
1525static void
a4872ba6 1526gen5_ring_put_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1527{
1528 struct drm_device *dev = ring->dev;
4640c4ff 1529 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1530 unsigned long flags;
e48d8634 1531
7338aefa 1532 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1533 if (--ring->irq_refcount == 0)
480c8033 1534 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1535 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1536}
1537
b13c2b96 1538static bool
a4872ba6 1539i9xx_ring_get_irq(struct intel_engine_cs *ring)
62fdfeaf 1540{
78501eac 1541 struct drm_device *dev = ring->dev;
4640c4ff 1542 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1543 unsigned long flags;
62fdfeaf 1544
7cd512f1 1545 if (!intel_irqs_enabled(dev_priv))
b13c2b96
CW		 1546 return false;
1547
7338aefa 1548 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1549 if (ring->irq_refcount++ == 0) {
f637fde4
DV		 1550 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1551 I915_WRITE(IMR, dev_priv->irq_mask);
1552 POSTING_READ(IMR);
1553 }
7338aefa 1554 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
b13c2b96
CW		 1555
1556 return true;
62fdfeaf
EA		 1557}
1558
8187a2b7 1559static void
a4872ba6 1560i9xx_ring_put_irq(struct intel_engine_cs *ring)
62fdfeaf 1561{
78501eac 1562 struct drm_device *dev = ring->dev;
4640c4ff 1563 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1564 unsigned long flags;
62fdfeaf 1565
7338aefa 1566 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1567 if (--ring->irq_refcount == 0) {
f637fde4
DV		 1568 dev_priv->irq_mask |= ring->irq_enable_mask;
1569 I915_WRITE(IMR, dev_priv->irq_mask);
1570 POSTING_READ(IMR);
1571 }
7338aefa 1572 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
62fdfeaf
EA		 1573}
1574
c2798b19 1575static bool
a4872ba6 1576i8xx_ring_get_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1577{
1578 struct drm_device *dev = ring->dev;
4640c4ff 1579 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1580 unsigned long flags;
c2798b19 1581
7cd512f1 1582 if (!intel_irqs_enabled(dev_priv))
c2798b19
CW		 1583 return false;
1584
7338aefa 1585 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1586 if (ring->irq_refcount++ == 0) {
c2798b19
CW		 1587 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1588 I915_WRITE16(IMR, dev_priv->irq_mask);
1589 POSTING_READ16(IMR);
1590 }
7338aefa 1591 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1592
1593 return true;
1594}
1595
1596static void
a4872ba6 1597i8xx_ring_put_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1598{
1599 struct drm_device *dev = ring->dev;
4640c4ff 1600 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1601 unsigned long flags;
c2798b19 1602
7338aefa 1603 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1604 if (--ring->irq_refcount == 0) {
c2798b19
CW		 1605 dev_priv->irq_mask |= ring->irq_enable_mask;
1606 I915_WRITE16(IMR, dev_priv->irq_mask);
1607 POSTING_READ16(IMR);
1608 }
7338aefa 1609 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1610}
1611
b72f3acb 1612static int
a84c3ae1 1613bsd_ring_flush(struct drm_i915_gem_request *req,
78501eac
CW		 1614 u32 invalidate_domains,
1615 u32 flush_domains)
d1b851fc 1616{
a84c3ae1 1617 struct intel_engine_cs *ring = req->ring;
b72f3acb
CW		 1618 int ret;
1619
5fb9de1a 1620 ret = intel_ring_begin(req, 2);
b72f3acb
CW		 1621 if (ret)
1622 return ret;
1623
1624 intel_ring_emit(ring, MI_FLUSH);
1625 intel_ring_emit(ring, MI_NOOP);
1626 intel_ring_advance(ring);
1627 return 0;
d1b851fc
ZN		 1628}
1629
3cce469c 1630static int
ee044a88 1631i9xx_add_request(struct drm_i915_gem_request *req)
d1b851fc 1632{
ee044a88 1633 struct intel_engine_cs *ring = req->ring;
3cce469c
CW		 1634 int ret;
1635
5fb9de1a 1636 ret = intel_ring_begin(req, 4);
3cce469c
CW		 1637 if (ret)
1638 return ret;
6f392d54 1639
3cce469c
CW		 1640 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1641 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
ee044a88 1642 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
3cce469c 1643 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1644 __intel_ring_advance(ring);
d1b851fc 1645
3cce469c 1646 return 0;
d1b851fc
ZN		 1647}
1648
0f46832f 1649static bool
a4872ba6 1650gen6_ring_get_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1651{
1652 struct drm_device *dev = ring->dev;
4640c4ff 1653 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1654 unsigned long flags;
0f46832f 1655
7cd512f1
DV		 1656 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1657 return false;
0f46832f 1658
7338aefa 1659 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1660 if (ring->irq_refcount++ == 0) {
040d2baa 1661 if (HAS_L3_DPF(dev) && ring->id == RCS)
cc609d5d
BW		 1662 I915_WRITE_IMR(ring,
1663 ~(ring->irq_enable_mask |
35a85ac6 1664 GT_PARITY_ERROR(dev)));
15b9f80e
BW		 1665 else
1666 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1667 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
0f46832f 1668 }
7338aefa 1669 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
0f46832f
CW		 1670
1671 return true;
1672}
1673
1674static void
a4872ba6 1675gen6_ring_put_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1676{
1677 struct drm_device *dev = ring->dev;
4640c4ff 1678 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1679 unsigned long flags;
0f46832f 1680
7338aefa 1681 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1682 if (--ring->irq_refcount == 0) {
040d2baa 1683 if (HAS_L3_DPF(dev) && ring->id == RCS)
35a85ac6 1684 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e
BW		 1685 else
1686 I915_WRITE_IMR(ring, ~0);
480c8033 1687 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1ec14ad3 1688 }
7338aefa 1689 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
d1b851fc
ZN		 1690}
1691
a19d2933 1692static bool
a4872ba6 1693hsw_vebox_get_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1694{
1695 struct drm_device *dev = ring->dev;
1696 struct drm_i915_private *dev_priv = dev->dev_private;
1697 unsigned long flags;
1698
7cd512f1 1699 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
a19d2933
BW		 1700 return false;
1701
59cdb63d 1702 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1703 if (ring->irq_refcount++ == 0) {
a19d2933 1704 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1705 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1706 }
59cdb63d 1707 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1708
1709 return true;
1710}
1711
1712static void
a4872ba6 1713hsw_vebox_put_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1714{
1715 struct drm_device *dev = ring->dev;
1716 struct drm_i915_private *dev_priv = dev->dev_private;
1717 unsigned long flags;
1718
59cdb63d 1719 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1720 if (--ring->irq_refcount == 0) {
a19d2933 1721 I915_WRITE_IMR(ring, ~0);
480c8033 1722 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1723 }
59cdb63d 1724 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1725}
1726
abd58f01 1727static bool
a4872ba6 1728gen8_ring_get_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1729{
1730 struct drm_device *dev = ring->dev;
1731 struct drm_i915_private *dev_priv = dev->dev_private;
1732 unsigned long flags;
1733
7cd512f1 1734 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
abd58f01
BW		 1735 return false;
1736
1737 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1738 if (ring->irq_refcount++ == 0) {
1739 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1740 I915_WRITE_IMR(ring,
1741 ~(ring->irq_enable_mask |
1742 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1743 } else {
1744 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1745 }
1746 POSTING_READ(RING_IMR(ring->mmio_base));
1747 }
1748 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1749
1750 return true;
1751}
1752
1753static void
a4872ba6 1754gen8_ring_put_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1755{
1756 struct drm_device *dev = ring->dev;
1757 struct drm_i915_private *dev_priv = dev->dev_private;
1758 unsigned long flags;
1759
1760 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1761 if (--ring->irq_refcount == 0) {
1762 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1763 I915_WRITE_IMR(ring,
1764 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1765 } else {
1766 I915_WRITE_IMR(ring, ~0);
1767 }
1768 POSTING_READ(RING_IMR(ring->mmio_base));
1769 }
1770 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1771}
1772
d1b851fc 1773static int
53fddaf7 1774i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 1775 u64 offset, u32 length,
8e004efc 1776 unsigned dispatch_flags)
d1b851fc 1777{
53fddaf7 1778 struct intel_engine_cs *ring = req->ring;
e1f99ce6 1779 int ret;
78501eac 1780
5fb9de1a 1781 ret = intel_ring_begin(req, 2);
e1f99ce6
CW		 1782 if (ret)
1783 return ret;
1784
78501eac 1785 intel_ring_emit(ring,
65f56876
CW		 1786 MI_BATCH_BUFFER_START |
1787 MI_BATCH_GTT |
8e004efc
JH		 1788 (dispatch_flags & I915_DISPATCH_SECURE ?
1789 0 : MI_BATCH_NON_SECURE_I965));
c4e7a414 1790 intel_ring_emit(ring, offset);
78501eac
CW		 1791 intel_ring_advance(ring);
1792
d1b851fc
ZN		 1793 return 0;
1794}
1795
b45305fc
DV		 1796/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1797#define I830_BATCH_LIMIT (256*1024)
c4d69da1
CW		 1798#define I830_TLB_ENTRIES (2)
1799#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
8187a2b7 1800static int
53fddaf7 1801i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
8e004efc
JH		 1802 u64 offset, u32 len,
1803 unsigned dispatch_flags)
62fdfeaf 1804{
53fddaf7 1805 struct intel_engine_cs *ring = req->ring;
c4d69da1 1806 u32 cs_offset = ring->scratch.gtt_offset;
c4e7a414 1807 int ret;
62fdfeaf 1808
5fb9de1a 1809 ret = intel_ring_begin(req, 6);
c4d69da1
CW		 1810 if (ret)
1811 return ret;
62fdfeaf 1812
c4d69da1
CW		 1813 /* Evict the invalid PTE TLBs */
1814 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1815 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1816 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1817 intel_ring_emit(ring, cs_offset);
1818 intel_ring_emit(ring, 0xdeadbeef);
1819 intel_ring_emit(ring, MI_NOOP);
1820 intel_ring_advance(ring);
b45305fc 1821
8e004efc 1822 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
b45305fc
DV		 1823 if (len > I830_BATCH_LIMIT)
1824 return -ENOSPC;
1825
5fb9de1a 1826 ret = intel_ring_begin(req, 6 + 2);
b45305fc
DV		 1827 if (ret)
1828 return ret;
c4d69da1
CW		 1829
1830 /* Blit the batch (which has now all relocs applied) to the
1831 * stable batch scratch bo area (so that the CS never
1832 * stumbles over its tlb invalidation bug) ...
1833 */
1834 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1835 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
611a7a4f 1836 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
b45305fc 1837 intel_ring_emit(ring, cs_offset);
b45305fc
DV		 1838 intel_ring_emit(ring, 4096);
1839 intel_ring_emit(ring, offset);
c4d69da1 1840
b45305fc 1841 intel_ring_emit(ring, MI_FLUSH);
c4d69da1
CW		 1842 intel_ring_emit(ring, MI_NOOP);
1843 intel_ring_advance(ring);
b45305fc
DV		 1844
1845 /* ... and execute it. */
c4d69da1 1846 offset = cs_offset;
b45305fc 1847 }
e1f99ce6 1848
5fb9de1a 1849 ret = intel_ring_begin(req, 4);
c4d69da1
CW		 1850 if (ret)
1851 return ret;
1852
1853 intel_ring_emit(ring, MI_BATCH_BUFFER);
8e004efc
JH		 1854 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1855 0 : MI_BATCH_NON_SECURE));
c4d69da1
CW		 1856 intel_ring_emit(ring, offset + len - 8);
1857 intel_ring_emit(ring, MI_NOOP);
1858 intel_ring_advance(ring);
1859
fb3256da
DV		 1860 return 0;
1861}
1862
1863static int
53fddaf7 1864i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 1865 u64 offset, u32 len,
8e004efc 1866 unsigned dispatch_flags)
fb3256da 1867{
53fddaf7 1868 struct intel_engine_cs *ring = req->ring;
fb3256da
DV		 1869 int ret;
1870
5fb9de1a 1871 ret = intel_ring_begin(req, 2);
fb3256da
DV		 1872 if (ret)
1873 return ret;
1874
65f56876 1875 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
8e004efc
JH		 1876 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1877 0 : MI_BATCH_NON_SECURE));
c4e7a414 1878 intel_ring_advance(ring);
62fdfeaf 1879
62fdfeaf
EA		 1880 return 0;
1881}
1882
a4872ba6 1883static void cleanup_status_page(struct intel_engine_cs *ring)
62fdfeaf 1884{
05394f39 1885 struct drm_i915_gem_object *obj;
62fdfeaf 1886
8187a2b7
ZN		 1887 obj = ring->status_page.obj;
1888 if (obj == NULL)
62fdfeaf 1889 return;
62fdfeaf 1890
9da3da66 1891 kunmap(sg_page(obj->pages->sgl));
d7f46fc4 1892 i915_gem_object_ggtt_unpin(obj);
05394f39 1893 drm_gem_object_unreference(&obj->base);
8187a2b7 1894 ring->status_page.obj = NULL;
62fdfeaf
EA		 1895}
1896
a4872ba6 1897static int init_status_page(struct intel_engine_cs *ring)
62fdfeaf 1898{
05394f39 1899 struct drm_i915_gem_object *obj;
62fdfeaf 1900
e3efda49 1901 if ((obj = ring->status_page.obj) == NULL) {
1f767e02 1902 unsigned flags;
e3efda49 1903 int ret;
e4ffd173 1904
e3efda49
CW		 1905 obj = i915_gem_alloc_object(ring->dev, 4096);
1906 if (obj == NULL) {
1907 DRM_ERROR("Failed to allocate status page\n");
1908 return -ENOMEM;
1909 }
62fdfeaf 1910
e3efda49
CW		 1911 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1912 if (ret)
1913 goto err_unref;
1914
1f767e02
CW		 1915 flags = 0;
1916 if (!HAS_LLC(ring->dev))
1917 /* On g33, we cannot place HWS above 256MiB, so
1918 * restrict its pinning to the low mappable arena.
1919 * Though this restriction is not documented for
1920 * gen4, gen5, or byt, they also behave similarly
1921 * and hang if the HWS is placed at the top of the
1922 * GTT. To generalise, it appears that all !llc
1923 * platforms have issues with us placing the HWS
1924 * above the mappable region (even though we never
1925 * actualy map it).
1926 */
1927 flags |= PIN_MAPPABLE;
1928 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
e3efda49
CW		 1929 if (ret) {
1930err_unref:
1931 drm_gem_object_unreference(&obj->base);
1932 return ret;
1933 }
1934
1935 ring->status_page.obj = obj;
1936 }
62fdfeaf 1937
f343c5f6 1938 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
9da3da66 1939 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
8187a2b7 1940 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
62fdfeaf 1941
8187a2b7
ZN		 1942 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1943 ring->name, ring->status_page.gfx_addr);
62fdfeaf
EA		 1944
1945 return 0;
62fdfeaf
EA		 1946}
1947
a4872ba6 1948static int init_phys_status_page(struct intel_engine_cs *ring)
6b8294a4
CW		 1949{
1950 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6b8294a4
CW		 1951
1952 if (!dev_priv->status_page_dmah) {
1953 dev_priv->status_page_dmah =
1954 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1955 if (!dev_priv->status_page_dmah)
1956 return -ENOMEM;
1957 }
1958
6b8294a4
CW		 1959 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1960 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1961
1962 return 0;
1963}
1964
7ba717cf 1965void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2919d291 1966{
2919d291 1967 iounmap(ringbuf->virtual_start);
7ba717cf 1968 ringbuf->virtual_start = NULL;
2919d291 1969 i915_gem_object_ggtt_unpin(ringbuf->obj);
7ba717cf
TD		 1970}
1971
1972int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1973 struct intel_ringbuffer *ringbuf)
1974{
1975 struct drm_i915_private *dev_priv = to_i915(dev);
1976 struct drm_i915_gem_object *obj = ringbuf->obj;
1977 int ret;
1978
1979 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1980 if (ret)
1981 return ret;
1982
1983 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1984 if (ret) {
1985 i915_gem_object_ggtt_unpin(obj);
1986 return ret;
1987 }
1988
1989 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1990 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1991 if (ringbuf->virtual_start == NULL) {
1992 i915_gem_object_ggtt_unpin(obj);
1993 return -EINVAL;
1994 }
1995
1996 return 0;
1997}
1998
1999void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2000{
2919d291
OM		 2001 drm_gem_object_unreference(&ringbuf->obj->base);
2002 ringbuf->obj = NULL;
2003}
2004
84c2377f
OM		 2005int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2006 struct intel_ringbuffer *ringbuf)
62fdfeaf 2007{
05394f39 2008 struct drm_i915_gem_object *obj;
62fdfeaf 2009
ebc052e0
CW		 2010 obj = NULL;
2011 if (!HAS_LLC(dev))
93b0a4e0 2012 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
ebc052e0 2013 if (obj == NULL)
93b0a4e0 2014 obj = i915_gem_alloc_object(dev, ringbuf->size);
e3efda49
CW		 2015 if (obj == NULL)
2016 return -ENOMEM;
8187a2b7 2017
24f3a8cf
AG		 2018 /* mark ring buffers as read-only from GPU side by default */
2019 obj->gt_ro = 1;
2020
93b0a4e0 2021 ringbuf->obj = obj;
e3efda49 2022
7ba717cf 2023 return 0;
e3efda49
CW		 2024}
2025
2026static int intel_init_ring_buffer(struct drm_device *dev,
a4872ba6 2027 struct intel_engine_cs *ring)
e3efda49 2028{
bfc882b4 2029 struct intel_ringbuffer *ringbuf;
e3efda49
CW		 2030 int ret;
2031
bfc882b4
DV		 2032 WARN_ON(ring->buffer);
2033
2034 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
2035 if (!ringbuf)
2036 return -ENOMEM;
2037 ring->buffer = ringbuf;
8ee14975 2038
e3efda49
CW		 2039 ring->dev = dev;
2040 INIT_LIST_HEAD(&ring->active_list);
2041 INIT_LIST_HEAD(&ring->request_list);
cc9130be 2042 INIT_LIST_HEAD(&ring->execlist_queue);
06fbca71 2043 i915_gem_batch_pool_init(dev, &ring->batch_pool);
93b0a4e0 2044 ringbuf->size = 32 * PAGE_SIZE;
0c7dd53b 2045 ringbuf->ring = ring;
ebc348b2 2046 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
e3efda49
CW		 2047
2048 init_waitqueue_head(&ring->irq_queue);
2049
2050 if (I915_NEED_GFX_HWS(dev)) {
2051 ret = init_status_page(ring);
2052 if (ret)
8ee14975 2053 goto error;
e3efda49
CW		 2054 } else {
2055 BUG_ON(ring->id != RCS);
2056 ret = init_phys_status_page(ring);
2057 if (ret)
8ee14975 2058 goto error;
e3efda49
CW		 2059 }
2060
bfc882b4 2061 WARN_ON(ringbuf->obj);
7ba717cf 2062
bfc882b4
DV		 2063 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
2064 if (ret) {
2065 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
2066 ring->name, ret);
2067 goto error;
2068 }
2069
2070 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2071 if (ret) {
2072 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2073 ring->name, ret);
2074 intel_destroy_ringbuffer_obj(ringbuf);
2075 goto error;
e3efda49 2076 }
62fdfeaf 2077
55249baa
CW		 2078 /* Workaround an erratum on the i830 which causes a hang if
2079 * the TAIL pointer points to within the last 2 cachelines
2080 * of the buffer.
2081 */
93b0a4e0 2082 ringbuf->effective_size = ringbuf->size;
e3efda49 2083 if (IS_I830(dev) || IS_845G(dev))
93b0a4e0 2084 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
55249baa 2085
44e895a8
BV		 2086 ret = i915_cmd_parser_init_ring(ring);
2087 if (ret)
8ee14975
OM		 2088 goto error;
2089
8ee14975 2090 return 0;
351e3db2 2091
8ee14975
OM		 2092error:
2093 kfree(ringbuf);
2094 ring->buffer = NULL;
2095 return ret;
62fdfeaf
EA		 2096}
2097
a4872ba6 2098void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
62fdfeaf 2099{
6402c330
JH		 2100 struct drm_i915_private *dev_priv;
2101 struct intel_ringbuffer *ringbuf;
33626e6a 2102
93b0a4e0 2103 if (!intel_ring_initialized(ring))
62fdfeaf
EA		 2104 return;
2105
6402c330
JH		 2106 dev_priv = to_i915(ring->dev);
2107 ringbuf = ring->buffer;
2108
e3efda49 2109 intel_stop_ring_buffer(ring);
de8f0a50 2110 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
33626e6a 2111
7ba717cf 2112 intel_unpin_ringbuffer_obj(ringbuf);
2919d291 2113 intel_destroy_ringbuffer_obj(ringbuf);
78501eac 2114
8d19215b
ZN		 2115 if (ring->cleanup)
2116 ring->cleanup(ring);
2117
78501eac 2118 cleanup_status_page(ring);
44e895a8
BV		 2119
2120 i915_cmd_parser_fini_ring(ring);
06fbca71 2121 i915_gem_batch_pool_fini(&ring->batch_pool);
8ee14975 2122
93b0a4e0 2123 kfree(ringbuf);
8ee14975 2124 ring->buffer = NULL;
62fdfeaf
EA		 2125}
2126
595e1eeb 2127static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
a71d8d94 2128{
93b0a4e0 2129 struct intel_ringbuffer *ringbuf = ring->buffer;
a71d8d94 2130 struct drm_i915_gem_request *request;
b4716185
CW		 2131 unsigned space;
2132 int ret;
a71d8d94 2133
ebd0fd4b
DG		 2134 if (intel_ring_space(ringbuf) >= n)
2135 return 0;
a71d8d94 2136
79bbcc29
JH		 2137 /* The whole point of reserving space is to not wait! */
2138 WARN_ON(ringbuf->reserved_in_use);
2139
a71d8d94 2140 list_for_each_entry(request, &ring->request_list, list) {
b4716185
CW		 2141 space = __intel_ring_space(request->postfix, ringbuf->tail,
2142 ringbuf->size);
2143 if (space >= n)
a71d8d94 2144 break;
a71d8d94
CW		 2145 }
2146
595e1eeb 2147 if (WARN_ON(&request->list == &ring->request_list))
a71d8d94
CW		 2148 return -ENOSPC;
2149
a4b3a571 2150 ret = i915_wait_request(request);
a71d8d94
CW		 2151 if (ret)
2152 return ret;
2153
b4716185 2154 ringbuf->space = space;
a71d8d94
CW		 2155 return 0;
2156}
2157
79bbcc29 2158static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
3e960501
CW		 2159{
2160 uint32_t __iomem *virt;
93b0a4e0 2161 int rem = ringbuf->size - ringbuf->tail;
3e960501 2162
93b0a4e0 2163 virt = ringbuf->virtual_start + ringbuf->tail;
3e960501
CW		 2164 rem /= 4;
2165 while (rem--)
2166 iowrite32(MI_NOOP, virt++);
2167
93b0a4e0 2168 ringbuf->tail = 0;
ebd0fd4b 2169 intel_ring_update_space(ringbuf);
3e960501
CW		 2170}
2171
a4872ba6 2172int intel_ring_idle(struct intel_engine_cs *ring)
3e960501 2173{
a4b3a571 2174 struct drm_i915_gem_request *req;
3e960501 2175
3e960501
CW		 2176 /* Wait upon the last request to be completed */
2177 if (list_empty(&ring->request_list))
2178 return 0;
2179
a4b3a571 2180 req = list_entry(ring->request_list.prev,
b4716185
CW		 2181 struct drm_i915_gem_request,
2182 list);
2183
2184 /* Make sure we do not trigger any retires */
2185 return __i915_wait_request(req,
2186 atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter),
2187 to_i915(ring->dev)->mm.interruptible,
2188 NULL, NULL);
3e960501
CW		 2189}
2190
6689cb2b 2191int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
9d773091 2192{
6689cb2b 2193 request->ringbuf = request->ring->buffer;
9eba5d4a 2194 return 0;
9d773091
CW		 2195}
2196
ccd98fe4
JH		 2197int intel_ring_reserve_space(struct drm_i915_gem_request *request)
2198{
2199 /*
2200 * The first call merely notes the reserve request and is common for
2201 * all back ends. The subsequent localised _begin() call actually
2202 * ensures that the reservation is available. Without the begin, if
2203 * the request creator immediately submitted the request without
2204 * adding any commands to it then there might not actually be
2205 * sufficient room for the submission commands.
2206 */
2207 intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
2208
2209 return intel_ring_begin(request, 0);
2210}
2211
29b1b415
JH		 2212void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2213{
ccd98fe4 2214 WARN_ON(ringbuf->reserved_size);
29b1b415
JH		 2215 WARN_ON(ringbuf->reserved_in_use);
2216
2217 ringbuf->reserved_size = size;
29b1b415
JH		 2218}
2219
2220void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2221{
2222 WARN_ON(ringbuf->reserved_in_use);
2223
2224 ringbuf->reserved_size = 0;
2225 ringbuf->reserved_in_use = false;
2226}
2227
2228void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2229{
2230 WARN_ON(ringbuf->reserved_in_use);
2231
2232 ringbuf->reserved_in_use = true;
2233 ringbuf->reserved_tail = ringbuf->tail;
2234}
2235
2236void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2237{
2238 WARN_ON(!ringbuf->reserved_in_use);
79bbcc29
JH		 2239 if (ringbuf->tail > ringbuf->reserved_tail) {
2240 WARN(ringbuf->tail > ringbuf->reserved_tail + ringbuf->reserved_size,
2241 "request reserved size too small: %d vs %d!\n",
2242 ringbuf->tail - ringbuf->reserved_tail, ringbuf->reserved_size);
2243 } else {
2244 /*
2245 * The ring was wrapped while the reserved space was in use.
2246 * That means that some unknown amount of the ring tail was
2247 * no-op filled and skipped. Thus simply adding the ring size
2248 * to the tail and doing the above space check will not work.
2249 * Rather than attempt to track how much tail was skipped,
2250 * it is much simpler to say that also skipping the sanity
2251 * check every once in a while is not a big issue.
2252 */
2253 }
29b1b415
JH		 2254
2255 ringbuf->reserved_size = 0;
2256 ringbuf->reserved_in_use = false;
2257}
2258
2259static int __intel_ring_prepare(struct intel_engine_cs *ring, int bytes)
cbcc80df 2260{
93b0a4e0 2261 struct intel_ringbuffer *ringbuf = ring->buffer;
79bbcc29
JH		 2262 int remain_usable = ringbuf->effective_size - ringbuf->tail;
2263 int remain_actual = ringbuf->size - ringbuf->tail;
2264 int ret, total_bytes, wait_bytes = 0;
2265 bool need_wrap = false;
29b1b415 2266
79bbcc29
JH		 2267 if (ringbuf->reserved_in_use)
2268 total_bytes = bytes;
2269 else
2270 total_bytes = bytes + ringbuf->reserved_size;
29b1b415 2271
79bbcc29
JH		 2272 if (unlikely(bytes > remain_usable)) {
2273 /*
2274 * Not enough space for the basic request. So need to flush
2275 * out the remainder and then wait for base + reserved.
2276 */
2277 wait_bytes = remain_actual + total_bytes;
2278 need_wrap = true;
2279 } else {
2280 if (unlikely(total_bytes > remain_usable)) {
2281 /*
2282 * The base request will fit but the reserved space
2283 * falls off the end. So only need to to wait for the
2284 * reserved size after flushing out the remainder.
2285 */
2286 wait_bytes = remain_actual + ringbuf->reserved_size;
2287 need_wrap = true;
2288 } else if (total_bytes > ringbuf->space) {
2289 /* No wrapping required, just waiting. */
2290 wait_bytes = total_bytes;
29b1b415 2291 }
cbcc80df
MK		 2292 }
2293
79bbcc29
JH		 2294 if (wait_bytes) {
2295 ret = ring_wait_for_space(ring, wait_bytes);
cbcc80df
MK		 2296 if (unlikely(ret))
2297 return ret;
79bbcc29
JH		 2298
2299 if (need_wrap)
2300 __wrap_ring_buffer(ringbuf);
cbcc80df
MK		 2301 }
2302
cbcc80df
MK		 2303 return 0;
2304}
2305
5fb9de1a 2306int intel_ring_begin(struct drm_i915_gem_request *req,
e1f99ce6 2307 int num_dwords)
8187a2b7 2308{
5fb9de1a
JH		 2309 struct intel_engine_cs *ring;
2310 struct drm_i915_private *dev_priv;
e1f99ce6 2311 int ret;
78501eac 2312
5fb9de1a
JH		 2313 WARN_ON(req == NULL);
2314 ring = req->ring;
2315 dev_priv = ring->dev->dev_private;
2316
33196ded
DV		 2317 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2318 dev_priv->mm.interruptible);
de2b9985
DV		 2319 if (ret)
2320 return ret;
21dd3734 2321
304d695c
CW		 2322 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2323 if (ret)
2324 return ret;
2325
ee1b1e5e 2326 ring->buffer->space -= num_dwords * sizeof(uint32_t);
304d695c 2327 return 0;
8187a2b7 2328}
78501eac 2329
753b1ad4 2330/* Align the ring tail to a cacheline boundary */
bba09b12 2331int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
753b1ad4 2332{
bba09b12 2333 struct intel_engine_cs *ring = req->ring;
ee1b1e5e 2334 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
753b1ad4
VS		 2335 int ret;
2336
2337 if (num_dwords == 0)
2338 return 0;
2339
18393f63 2340 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
5fb9de1a 2341 ret = intel_ring_begin(req, num_dwords);
753b1ad4
VS		 2342 if (ret)
2343 return ret;
2344
2345 while (num_dwords--)
2346 intel_ring_emit(ring, MI_NOOP);
2347
2348 intel_ring_advance(ring);
2349
2350 return 0;
2351}
2352
a4872ba6 2353void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
498d2ac1 2354{
3b2cc8ab
OM		 2355 struct drm_device *dev = ring->dev;
2356 struct drm_i915_private *dev_priv = dev->dev_private;
498d2ac1 2357
3b2cc8ab 2358 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
f7e98ad4
MK		 2359 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2360 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
3b2cc8ab 2361 if (HAS_VEBOX(dev))
5020150b 2362 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
e1f99ce6 2363 }
d97ed339 2364
f7e98ad4 2365 ring->set_seqno(ring, seqno);
92cab734 2366 ring->hangcheck.seqno = seqno;
8187a2b7 2367}
62fdfeaf 2368
a4872ba6 2369static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 2370 u32 value)
881f47b6 2371{
4640c4ff 2372 struct drm_i915_private *dev_priv = ring->dev->dev_private;
881f47b6
XH		 2373
2374 /* Every tail move must follow the sequence below */
12f55818
CW		 2375
2376 /* Disable notification that the ring is IDLE. The GT
2377 * will then assume that it is busy and bring it out of rc6.
2378 */
0206e353 2379 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818
CW		 2380 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2381
2382 /* Clear the context id. Here be magic! */
2383 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
0206e353 2384
12f55818 2385 /* Wait for the ring not to be idle, i.e. for it to wake up. */
0206e353 2386 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
12f55818
CW		 2387 GEN6_BSD_SLEEP_INDICATOR) == 0,
2388 50))
2389 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
0206e353 2390
12f55818 2391 /* Now that the ring is fully powered up, update the tail */
0206e353 2392 I915_WRITE_TAIL(ring, value);
12f55818
CW		 2393 POSTING_READ(RING_TAIL(ring->mmio_base));
2394
2395 /* Let the ring send IDLE messages to the GT again,
2396 * and so let it sleep to conserve power when idle.
2397 */
0206e353 2398 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818 2399 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
881f47b6
XH		 2400}
2401
a84c3ae1 2402static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
ea251324 2403 u32 invalidate, u32 flush)
881f47b6 2404{
a84c3ae1 2405 struct intel_engine_cs *ring = req->ring;
71a77e07 2406 uint32_t cmd;
b72f3acb
CW		 2407 int ret;
2408
5fb9de1a 2409 ret = intel_ring_begin(req, 4);
b72f3acb
CW		 2410 if (ret)
2411 return ret;
2412
71a77e07 2413 cmd = MI_FLUSH_DW;
075b3bba
BW		 2414 if (INTEL_INFO(ring->dev)->gen >= 8)
2415 cmd += 1;
f0a1fb10
CW		 2416
2417 /* We always require a command barrier so that subsequent
2418 * commands, such as breadcrumb interrupts, are strictly ordered
2419 * wrt the contents of the write cache being flushed to memory
2420 * (and thus being coherent from the CPU).
2421 */
2422 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2423
9a289771
JB		 2424 /*
2425 * Bspec vol 1c.5 - video engine command streamer:
2426 * "If ENABLED, all TLBs will be invalidated once the flush
2427 * operation is complete. This bit is only valid when the
2428 * Post-Sync Operation field is a value of 1h or 3h."
2429 */
71a77e07 2430 if (invalidate & I915_GEM_GPU_DOMAINS)
f0a1fb10
CW		 2431 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2432
71a77e07 2433 intel_ring_emit(ring, cmd);
9a289771 2434 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
075b3bba
BW		 2435 if (INTEL_INFO(ring->dev)->gen >= 8) {
2436 intel_ring_emit(ring, 0); /* upper addr */
2437 intel_ring_emit(ring, 0); /* value */
2438 } else {
2439 intel_ring_emit(ring, 0);
2440 intel_ring_emit(ring, MI_NOOP);
2441 }
b72f3acb
CW		 2442 intel_ring_advance(ring);
2443 return 0;
881f47b6
XH		 2444}
2445
1c7a0623 2446static int
53fddaf7 2447gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 2448 u64 offset, u32 len,
8e004efc 2449 unsigned dispatch_flags)
1c7a0623 2450{
53fddaf7 2451 struct intel_engine_cs *ring = req->ring;
8e004efc
JH		 2452 bool ppgtt = USES_PPGTT(ring->dev) &&
2453 !(dispatch_flags & I915_DISPATCH_SECURE);
1c7a0623
BW		 2454 int ret;
2455
5fb9de1a 2456 ret = intel_ring_begin(req, 4);
1c7a0623
BW		 2457 if (ret)
2458 return ret;
2459
2460 /* FIXME(BDW): Address space and security selectors. */
919032ec
AJ		 2461 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2462 (dispatch_flags & I915_DISPATCH_RS ?
2463 MI_BATCH_RESOURCE_STREAMER : 0));
9bcb144c
BW		 2464 intel_ring_emit(ring, lower_32_bits(offset));
2465 intel_ring_emit(ring, upper_32_bits(offset));
1c7a0623
BW		 2466 intel_ring_emit(ring, MI_NOOP);
2467 intel_ring_advance(ring);
2468
2469 return 0;
2470}
2471
d7d4eedd 2472static int
53fddaf7 2473hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
8e004efc
JH		 2474 u64 offset, u32 len,
2475 unsigned dispatch_flags)
d7d4eedd 2476{
53fddaf7 2477 struct intel_engine_cs *ring = req->ring;
d7d4eedd
CW		 2478 int ret;
2479
5fb9de1a 2480 ret = intel_ring_begin(req, 2);
d7d4eedd
CW		 2481 if (ret)
2482 return ret;
2483
2484 intel_ring_emit(ring,
77072258 2485 MI_BATCH_BUFFER_START |
8e004efc 2486 (dispatch_flags & I915_DISPATCH_SECURE ?
919032ec
AJ		 2487 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2488 (dispatch_flags & I915_DISPATCH_RS ?
2489 MI_BATCH_RESOURCE_STREAMER : 0));
d7d4eedd
CW		 2490 /* bit0-7 is the length on GEN6+ */
2491 intel_ring_emit(ring, offset);
2492 intel_ring_advance(ring);
2493
2494 return 0;
2495}
2496
881f47b6 2497static int
53fddaf7 2498gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 2499 u64 offset, u32 len,
8e004efc 2500 unsigned dispatch_flags)
881f47b6 2501{
53fddaf7 2502 struct intel_engine_cs *ring = req->ring;
0206e353 2503 int ret;
ab6f8e32 2504
5fb9de1a 2505 ret = intel_ring_begin(req, 2);
0206e353
AJ		 2506 if (ret)
2507 return ret;
e1f99ce6 2508
d7d4eedd
CW		 2509 intel_ring_emit(ring,
2510 MI_BATCH_BUFFER_START |
8e004efc
JH		 2511 (dispatch_flags & I915_DISPATCH_SECURE ?
2512 0 : MI_BATCH_NON_SECURE_I965));
0206e353
AJ		 2513 /* bit0-7 is the length on GEN6+ */
2514 intel_ring_emit(ring, offset);
2515 intel_ring_advance(ring);
ab6f8e32 2516
0206e353 2517 return 0;
881f47b6
XH		 2518}
2519
549f7365
CW		 2520/* Blitter support (SandyBridge+) */
2521
a84c3ae1 2522static int gen6_ring_flush(struct drm_i915_gem_request *req,
ea251324 2523 u32 invalidate, u32 flush)
8d19215b 2524{
a84c3ae1 2525 struct intel_engine_cs *ring = req->ring;
fd3da6c9 2526 struct drm_device *dev = ring->dev;
71a77e07 2527 uint32_t cmd;
b72f3acb
CW		 2528 int ret;
2529
5fb9de1a 2530 ret = intel_ring_begin(req, 4);
b72f3acb
CW		 2531 if (ret)
2532 return ret;
2533
71a77e07 2534 cmd = MI_FLUSH_DW;
dbef0f15 2535 if (INTEL_INFO(dev)->gen >= 8)
075b3bba 2536 cmd += 1;
f0a1fb10
CW		 2537
2538 /* We always require a command barrier so that subsequent
2539 * commands, such as breadcrumb interrupts, are strictly ordered
2540 * wrt the contents of the write cache being flushed to memory
2541 * (and thus being coherent from the CPU).
2542 */
2543 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2544
9a289771
JB		 2545 /*
2546 * Bspec vol 1c.3 - blitter engine command streamer:
2547 * "If ENABLED, all TLBs will be invalidated once the flush
2548 * operation is complete. This bit is only valid when the
2549 * Post-Sync Operation field is a value of 1h or 3h."
2550 */
71a77e07 2551 if (invalidate & I915_GEM_DOMAIN_RENDER)
f0a1fb10 2552 cmd |= MI_INVALIDATE_TLB;
71a77e07 2553 intel_ring_emit(ring, cmd);
9a289771 2554 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
dbef0f15 2555 if (INTEL_INFO(dev)->gen >= 8) {
075b3bba
BW		 2556 intel_ring_emit(ring, 0); /* upper addr */
2557 intel_ring_emit(ring, 0); /* value */
2558 } else {
2559 intel_ring_emit(ring, 0);
2560 intel_ring_emit(ring, MI_NOOP);
2561 }
b72f3acb 2562 intel_ring_advance(ring);
fd3da6c9 2563
b72f3acb 2564 return 0;
8d19215b
ZN		 2565}
2566
5c1143bb
XH		 2567int intel_init_render_ring_buffer(struct drm_device *dev)
2568{
4640c4ff 2569 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2570 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3e78998a
BW		 2571 struct drm_i915_gem_object *obj;
2572 int ret;
5c1143bb 2573
59465b5f
DV		 2574 ring->name = "render ring";
2575 ring->id = RCS;
2576 ring->mmio_base = RENDER_RING_BASE;
2577
707d9cf9 2578 if (INTEL_INFO(dev)->gen >= 8) {
3e78998a
BW		 2579 if (i915_semaphore_is_enabled(dev)) {
2580 obj = i915_gem_alloc_object(dev, 4096);
2581 if (obj == NULL) {
2582 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2583 i915.semaphores = 0;
2584 } else {
2585 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2586 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2587 if (ret != 0) {
2588 drm_gem_object_unreference(&obj->base);
2589 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2590 i915.semaphores = 0;
2591 } else
2592 dev_priv->semaphore_obj = obj;
2593 }
2594 }
7225342a 2595
8f0e2b9d 2596 ring->init_context = intel_rcs_ctx_init;
707d9cf9
BW		 2597 ring->add_request = gen6_add_request;
2598 ring->flush = gen8_render_ring_flush;
2599 ring->irq_get = gen8_ring_get_irq;
2600 ring->irq_put = gen8_ring_put_irq;
2601 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2602 ring->get_seqno = gen6_ring_get_seqno;
2603 ring->set_seqno = ring_set_seqno;
2604 if (i915_semaphore_is_enabled(dev)) {
3e78998a 2605 WARN_ON(!dev_priv->semaphore_obj);
5ee426ca 2606 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2607 ring->semaphore.signal = gen8_rcs_signal;
2608 GEN8_RING_SEMAPHORE_INIT;
707d9cf9
BW		 2609 }
2610 } else if (INTEL_INFO(dev)->gen >= 6) {
1ec14ad3 2611 ring->add_request = gen6_add_request;
4772eaeb 2612 ring->flush = gen7_render_ring_flush;
6c6cf5aa 2613 if (INTEL_INFO(dev)->gen == 6)
b3111509 2614 ring->flush = gen6_render_ring_flush;
707d9cf9
BW		 2615 ring->irq_get = gen6_ring_get_irq;
2616 ring->irq_put = gen6_ring_put_irq;
cc609d5d 2617 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
4cd53c0c 2618 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2619 ring->set_seqno = ring_set_seqno;
707d9cf9
BW		 2620 if (i915_semaphore_is_enabled(dev)) {
2621 ring->semaphore.sync_to = gen6_ring_sync;
2622 ring->semaphore.signal = gen6_signal;
2623 /*
2624 * The current semaphore is only applied on pre-gen8
2625 * platform. And there is no VCS2 ring on the pre-gen8
2626 * platform. So the semaphore between RCS and VCS2 is
2627 * initialized as INVALID. Gen8 will initialize the
2628 * sema between VCS2 and RCS later.
2629 */
2630 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2631 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2632 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2633 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2634 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2635 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2636 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2637 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2638 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2639 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2640 }
c6df541c
CW		 2641 } else if (IS_GEN5(dev)) {
2642 ring->add_request = pc_render_add_request;
46f0f8d1 2643 ring->flush = gen4_render_ring_flush;
c6df541c 2644 ring->get_seqno = pc_render_get_seqno;
b70ec5bf 2645 ring->set_seqno = pc_render_set_seqno;
e48d8634
DV		 2646 ring->irq_get = gen5_ring_get_irq;
2647 ring->irq_put = gen5_ring_put_irq;
cc609d5d
BW		 2648 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2649 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
59465b5f 2650 } else {
8620a3a9 2651 ring->add_request = i9xx_add_request;
46f0f8d1
CW		 2652 if (INTEL_INFO(dev)->gen < 4)
2653 ring->flush = gen2_render_ring_flush;
2654 else
2655 ring->flush = gen4_render_ring_flush;
59465b5f 2656 ring->get_seqno = ring_get_seqno;
b70ec5bf 2657 ring->set_seqno = ring_set_seqno;
c2798b19
CW		 2658 if (IS_GEN2(dev)) {
2659 ring->irq_get = i8xx_ring_get_irq;
2660 ring->irq_put = i8xx_ring_put_irq;
2661 } else {
2662 ring->irq_get = i9xx_ring_get_irq;
2663 ring->irq_put = i9xx_ring_put_irq;
2664 }
e3670319 2665 ring->irq_enable_mask = I915_USER_INTERRUPT;
1ec14ad3 2666 }
59465b5f 2667 ring->write_tail = ring_write_tail;
707d9cf9 2668
d7d4eedd
CW		 2669 if (IS_HASWELL(dev))
2670 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1c7a0623
BW		 2671 else if (IS_GEN8(dev))
2672 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
d7d4eedd 2673 else if (INTEL_INFO(dev)->gen >= 6)
fb3256da
DV		 2674 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2675 else if (INTEL_INFO(dev)->gen >= 4)
2676 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2677 else if (IS_I830(dev) || IS_845G(dev))
2678 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2679 else
2680 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
ecfe00d8 2681 ring->init_hw = init_render_ring;
59465b5f
DV		 2682 ring->cleanup = render_ring_cleanup;
2683
b45305fc
DV		 2684 /* Workaround batchbuffer to combat CS tlb bug. */
2685 if (HAS_BROKEN_CS_TLB(dev)) {
c4d69da1 2686 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
b45305fc
DV		 2687 if (obj == NULL) {
2688 DRM_ERROR("Failed to allocate batch bo\n");
2689 return -ENOMEM;
2690 }
2691
be1fa129 2692 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
b45305fc
DV		 2693 if (ret != 0) {
2694 drm_gem_object_unreference(&obj->base);
2695 DRM_ERROR("Failed to ping batch bo\n");
2696 return ret;
2697 }
2698
0d1aacac
CW		 2699 ring->scratch.obj = obj;
2700 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
b45305fc
DV		 2701 }
2702
99be1dfe
DV		 2703 ret = intel_init_ring_buffer(dev, ring);
2704 if (ret)
2705 return ret;
2706
2707 if (INTEL_INFO(dev)->gen >= 5) {
2708 ret = intel_init_pipe_control(ring);
2709 if (ret)
2710 return ret;
2711 }
2712
2713 return 0;
5c1143bb
XH		 2714}
2715
2716int intel_init_bsd_ring_buffer(struct drm_device *dev)
2717{
4640c4ff 2718 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2719 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
5c1143bb 2720
58fa3835
DV		 2721 ring->name = "bsd ring";
2722 ring->id = VCS;
2723
0fd2c201 2724 ring->write_tail = ring_write_tail;
780f18c8 2725 if (INTEL_INFO(dev)->gen >= 6) {
58fa3835 2726 ring->mmio_base = GEN6_BSD_RING_BASE;
0fd2c201
DV		 2727 /* gen6 bsd needs a special wa for tail updates */
2728 if (IS_GEN6(dev))
2729 ring->write_tail = gen6_bsd_ring_write_tail;
ea251324 2730 ring->flush = gen6_bsd_ring_flush;
58fa3835
DV		 2731 ring->add_request = gen6_add_request;
2732 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2733 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2734 if (INTEL_INFO(dev)->gen >= 8) {
2735 ring->irq_enable_mask =
2736 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2737 ring->irq_get = gen8_ring_get_irq;
2738 ring->irq_put = gen8_ring_put_irq;
1c7a0623
BW		 2739 ring->dispatch_execbuffer =
2740 gen8_ring_dispatch_execbuffer;
707d9cf9 2741 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2742 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2743 ring->semaphore.signal = gen8_xcs_signal;
2744 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2745 }
abd58f01
BW		 2746 } else {
2747 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2748 ring->irq_get = gen6_ring_get_irq;
2749 ring->irq_put = gen6_ring_put_irq;
1c7a0623
BW		 2750 ring->dispatch_execbuffer =
2751 gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2752 if (i915_semaphore_is_enabled(dev)) {
2753 ring->semaphore.sync_to = gen6_ring_sync;
2754 ring->semaphore.signal = gen6_signal;
2755 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2756 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2757 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2758 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2759 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2760 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2761 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2762 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2763 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2764 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2765 }
abd58f01 2766 }
58fa3835
DV		 2767 } else {
2768 ring->mmio_base = BSD_RING_BASE;
58fa3835 2769 ring->flush = bsd_ring_flush;
8620a3a9 2770 ring->add_request = i9xx_add_request;
58fa3835 2771 ring->get_seqno = ring_get_seqno;
b70ec5bf 2772 ring->set_seqno = ring_set_seqno;
e48d8634 2773 if (IS_GEN5(dev)) {
cc609d5d 2774 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
e48d8634
DV		 2775 ring->irq_get = gen5_ring_get_irq;
2776 ring->irq_put = gen5_ring_put_irq;
2777 } else {
e3670319 2778 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
e48d8634
DV		 2779 ring->irq_get = i9xx_ring_get_irq;
2780 ring->irq_put = i9xx_ring_put_irq;
2781 }
fb3256da 2782 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
58fa3835 2783 }
ecfe00d8 2784 ring->init_hw = init_ring_common;
58fa3835 2785
1ec14ad3 2786 return intel_init_ring_buffer(dev, ring);
5c1143bb 2787}
549f7365 2788
845f74a7 2789/**
62659920 2790 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
845f74a7
ZY		 2791 */
2792int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2793{
2794 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2795 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
845f74a7 2796
f7b64236 2797 ring->name = "bsd2 ring";
845f74a7
ZY		 2798 ring->id = VCS2;
2799
2800 ring->write_tail = ring_write_tail;
2801 ring->mmio_base = GEN8_BSD2_RING_BASE;
2802 ring->flush = gen6_bsd_ring_flush;
2803 ring->add_request = gen6_add_request;
2804 ring->get_seqno = gen6_ring_get_seqno;
2805 ring->set_seqno = ring_set_seqno;
2806 ring->irq_enable_mask =
2807 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2808 ring->irq_get = gen8_ring_get_irq;
2809 ring->irq_put = gen8_ring_put_irq;
2810 ring->dispatch_execbuffer =
2811 gen8_ring_dispatch_execbuffer;
3e78998a 2812 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2813 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2814 ring->semaphore.signal = gen8_xcs_signal;
2815 GEN8_RING_SEMAPHORE_INIT;
2816 }
ecfe00d8 2817 ring->init_hw = init_ring_common;
845f74a7
ZY		 2818
2819 return intel_init_ring_buffer(dev, ring);
2820}
2821
549f7365
CW		 2822int intel_init_blt_ring_buffer(struct drm_device *dev)
2823{
4640c4ff 2824 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2825 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
549f7365 2826
3535d9dd
DV		 2827 ring->name = "blitter ring";
2828 ring->id = BCS;
2829
2830 ring->mmio_base = BLT_RING_BASE;
2831 ring->write_tail = ring_write_tail;
ea251324 2832 ring->flush = gen6_ring_flush;
3535d9dd
DV		 2833 ring->add_request = gen6_add_request;
2834 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2835 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2836 if (INTEL_INFO(dev)->gen >= 8) {
2837 ring->irq_enable_mask =
2838 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2839 ring->irq_get = gen8_ring_get_irq;
2840 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2841 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2842 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2843 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2844 ring->semaphore.signal = gen8_xcs_signal;
2845 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2846 }
abd58f01
BW		 2847 } else {
2848 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2849 ring->irq_get = gen6_ring_get_irq;
2850 ring->irq_put = gen6_ring_put_irq;
1c7a0623 2851 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2852 if (i915_semaphore_is_enabled(dev)) {
2853 ring->semaphore.signal = gen6_signal;
2854 ring->semaphore.sync_to = gen6_ring_sync;
2855 /*
2856 * The current semaphore is only applied on pre-gen8
2857 * platform. And there is no VCS2 ring on the pre-gen8
2858 * platform. So the semaphore between BCS and VCS2 is
2859 * initialized as INVALID. Gen8 will initialize the
2860 * sema between BCS and VCS2 later.
2861 */
2862 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2863 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2864 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2865 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2866 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2867 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2868 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2869 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2870 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2871 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2872 }
abd58f01 2873 }
ecfe00d8 2874 ring->init_hw = init_ring_common;
549f7365 2875
1ec14ad3 2876 return intel_init_ring_buffer(dev, ring);
549f7365 2877}
a7b9761d 2878
9a8a2213
BW		 2879int intel_init_vebox_ring_buffer(struct drm_device *dev)
2880{
4640c4ff 2881 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2882 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
9a8a2213
BW		 2883
2884 ring->name = "video enhancement ring";
2885 ring->id = VECS;
2886
2887 ring->mmio_base = VEBOX_RING_BASE;
2888 ring->write_tail = ring_write_tail;
2889 ring->flush = gen6_ring_flush;
2890 ring->add_request = gen6_add_request;
2891 ring->get_seqno = gen6_ring_get_seqno;
2892 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2893
2894 if (INTEL_INFO(dev)->gen >= 8) {
2895 ring->irq_enable_mask =
40c499f9 2896 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
abd58f01
BW		 2897 ring->irq_get = gen8_ring_get_irq;
2898 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2899 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2900 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2901 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2902 ring->semaphore.signal = gen8_xcs_signal;
2903 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2904 }
abd58f01
BW		 2905 } else {
2906 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2907 ring->irq_get = hsw_vebox_get_irq;
2908 ring->irq_put = hsw_vebox_put_irq;
1c7a0623 2909 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2910 if (i915_semaphore_is_enabled(dev)) {
2911 ring->semaphore.sync_to = gen6_ring_sync;
2912 ring->semaphore.signal = gen6_signal;
2913 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2914 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2915 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2916 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2917 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2918 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2919 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2920 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2921 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2922 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2923 }
abd58f01 2924 }
ecfe00d8 2925 ring->init_hw = init_ring_common;
9a8a2213
BW		 2926
2927 return intel_init_ring_buffer(dev, ring);
2928}
2929
a7b9761d 2930int
4866d729 2931intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
a7b9761d 2932{
4866d729 2933 struct intel_engine_cs *ring = req->ring;
a7b9761d
CW		 2934 int ret;
2935
2936 if (!ring->gpu_caches_dirty)
2937 return 0;
2938
a84c3ae1 2939 ret = ring->flush(req, 0, I915_GEM_GPU_DOMAINS);
a7b9761d
CW		 2940 if (ret)
2941 return ret;
2942
a84c3ae1 2943 trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
a7b9761d
CW		 2944
2945 ring->gpu_caches_dirty = false;
2946 return 0;
2947}
2948
2949int
2f20055d 2950intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
a7b9761d 2951{
2f20055d 2952 struct intel_engine_cs *ring = req->ring;
a7b9761d
CW		 2953 uint32_t flush_domains;
2954 int ret;
2955
2956 flush_domains = 0;
2957 if (ring->gpu_caches_dirty)
2958 flush_domains = I915_GEM_GPU_DOMAINS;
2959
a84c3ae1 2960 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
a7b9761d
CW		 2961 if (ret)
2962 return ret;
2963
a84c3ae1 2964 trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
a7b9761d
CW		 2965
2966 ring->gpu_caches_dirty = false;
2967 return 0;
2968}
e3efda49
CW		 2969
2970void
a4872ba6 2971intel_stop_ring_buffer(struct intel_engine_cs *ring)
e3efda49
CW		 2972{
2973 int ret;
2974
2975 if (!intel_ring_initialized(ring))
2976 return;
2977
2978 ret = intel_ring_idle(ring);
2979 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2980 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2981 ring->name, ret);
2982
2983 stop_ring(ring);
2984}
Linux 6.x block layer and io_uring tree(s)