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Merge remote-tracking branch 'asoc/topic/w-codec' into asoc-next
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
CommitLineData
62fdfeaf
EA		 1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
760285e7 30#include <drm/drmP.h>
62fdfeaf 31#include "i915_drv.h"
760285e7 32#include <drm/i915_drm.h>
62fdfeaf 33#include "i915_trace.h"
881f47b6 34#include "intel_drv.h"
62fdfeaf 35
48d82387
OM		 36bool
37intel_ring_initialized(struct intel_engine_cs *ring)
38{
39 struct drm_device *dev = ring->dev;
40
41 if (!dev)
42 return false;
43
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
47
48 return ringbuf->obj;
49 } else
50 return ring->buffer && ring->buffer->obj;
51}
18393f63 52
82e104cc 53int __intel_ring_space(int head, int tail, int size)
c7dca47b 54{
1cf0ba14 55 int space = head - (tail + I915_RING_FREE_SPACE);
c7dca47b 56 if (space < 0)
1cf0ba14 57 space += size;
c7dca47b
CW		 58 return space;
59}
60
82e104cc 61int intel_ring_space(struct intel_ringbuffer *ringbuf)
1cf0ba14 62{
82e104cc
OM		 63 return __intel_ring_space(ringbuf->head & HEAD_ADDR,
64 ringbuf->tail, ringbuf->size);
1cf0ba14
CW		 65}
66
82e104cc 67bool intel_ring_stopped(struct intel_engine_cs *ring)
09246732
CW		 68{
69 struct drm_i915_private *dev_priv = ring->dev->dev_private;
88b4aa87
MK		 70 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
71}
09246732 72
a4872ba6 73void __intel_ring_advance(struct intel_engine_cs *ring)
88b4aa87 74{
93b0a4e0
OM		 75 struct intel_ringbuffer *ringbuf = ring->buffer;
76 ringbuf->tail &= ringbuf->size - 1;
88b4aa87 77 if (intel_ring_stopped(ring))
09246732 78 return;
93b0a4e0 79 ring->write_tail(ring, ringbuf->tail);
09246732
CW		 80}
81
b72f3acb 82static int
a4872ba6 83gen2_render_ring_flush(struct intel_engine_cs *ring,
46f0f8d1
CW		 84 u32 invalidate_domains,
85 u32 flush_domains)
86{
87 u32 cmd;
88 int ret;
89
90 cmd = MI_FLUSH;
31b14c9f 91 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
46f0f8d1
CW		 92 cmd |= MI_NO_WRITE_FLUSH;
93
94 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
95 cmd |= MI_READ_FLUSH;
96
97 ret = intel_ring_begin(ring, 2);
98 if (ret)
99 return ret;
100
101 intel_ring_emit(ring, cmd);
102 intel_ring_emit(ring, MI_NOOP);
103 intel_ring_advance(ring);
104
105 return 0;
106}
107
108static int
a4872ba6 109gen4_render_ring_flush(struct intel_engine_cs *ring,
46f0f8d1
CW		 110 u32 invalidate_domains,
111 u32 flush_domains)
62fdfeaf 112{
78501eac 113 struct drm_device *dev = ring->dev;
6f392d54 114 u32 cmd;
b72f3acb 115 int ret;
6f392d54 116
36d527de
CW		 117 /*
118 * read/write caches:
119 *
120 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
121 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
122 * also flushed at 2d versus 3d pipeline switches.
123 *
124 * read-only caches:
125 *
126 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
127 * MI_READ_FLUSH is set, and is always flushed on 965.
128 *
129 * I915_GEM_DOMAIN_COMMAND may not exist?
130 *
131 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
132 * invalidated when MI_EXE_FLUSH is set.
133 *
134 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
135 * invalidated with every MI_FLUSH.
136 *
137 * TLBs:
138 *
139 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
140 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
141 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
142 * are flushed at any MI_FLUSH.
143 */
144
145 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
46f0f8d1 146 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
36d527de 147 cmd &= ~MI_NO_WRITE_FLUSH;
36d527de
CW		 148 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
149 cmd |= MI_EXE_FLUSH;
62fdfeaf 150
36d527de
CW		 151 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
152 (IS_G4X(dev) || IS_GEN5(dev)))
153 cmd |= MI_INVALIDATE_ISP;
70eac33e 154
36d527de
CW		 155 ret = intel_ring_begin(ring, 2);
156 if (ret)
157 return ret;
b72f3acb 158
36d527de
CW		 159 intel_ring_emit(ring, cmd);
160 intel_ring_emit(ring, MI_NOOP);
161 intel_ring_advance(ring);
b72f3acb
CW		 162
163 return 0;
8187a2b7
ZN		 164}
165
8d315287
JB		 166/**
167 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
168 * implementing two workarounds on gen6. From section 1.4.7.1
169 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
170 *
171 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
172 * produced by non-pipelined state commands), software needs to first
173 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
174 * 0.
175 *
176 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
177 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
178 *
179 * And the workaround for these two requires this workaround first:
180 *
181 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
182 * BEFORE the pipe-control with a post-sync op and no write-cache
183 * flushes.
184 *
185 * And this last workaround is tricky because of the requirements on
186 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
187 * volume 2 part 1:
188 *
189 * "1 of the following must also be set:
190 * - Render Target Cache Flush Enable ([12] of DW1)
191 * - Depth Cache Flush Enable ([0] of DW1)
192 * - Stall at Pixel Scoreboard ([1] of DW1)
193 * - Depth Stall ([13] of DW1)
194 * - Post-Sync Operation ([13] of DW1)
195 * - Notify Enable ([8] of DW1)"
196 *
197 * The cache flushes require the workaround flush that triggered this
198 * one, so we can't use it. Depth stall would trigger the same.
199 * Post-sync nonzero is what triggered this second workaround, so we
200 * can't use that one either. Notify enable is IRQs, which aren't
201 * really our business. That leaves only stall at scoreboard.
202 */
203static int
a4872ba6 204intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
8d315287 205{
18393f63 206 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 207 int ret;
208
209
210 ret = intel_ring_begin(ring, 6);
211 if (ret)
212 return ret;
213
214 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
215 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
216 PIPE_CONTROL_STALL_AT_SCOREBOARD);
217 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
218 intel_ring_emit(ring, 0); /* low dword */
219 intel_ring_emit(ring, 0); /* high dword */
220 intel_ring_emit(ring, MI_NOOP);
221 intel_ring_advance(ring);
222
223 ret = intel_ring_begin(ring, 6);
224 if (ret)
225 return ret;
226
227 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
228 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
229 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
230 intel_ring_emit(ring, 0);
231 intel_ring_emit(ring, 0);
232 intel_ring_emit(ring, MI_NOOP);
233 intel_ring_advance(ring);
234
235 return 0;
236}
237
238static int
a4872ba6 239gen6_render_ring_flush(struct intel_engine_cs *ring,
8d315287
JB		 240 u32 invalidate_domains, u32 flush_domains)
241{
242 u32 flags = 0;
18393f63 243 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 244 int ret;
245
b3111509
PZ		 246 /* Force SNB workarounds for PIPE_CONTROL flushes */
247 ret = intel_emit_post_sync_nonzero_flush(ring);
248 if (ret)
249 return ret;
250
8d315287
JB		 251 /* Just flush everything. Experiments have shown that reducing the
252 * number of bits based on the write domains has little performance
253 * impact.
254 */
7d54a904
CW		 255 if (flush_domains) {
256 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
257 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
258 /*
259 * Ensure that any following seqno writes only happen
260 * when the render cache is indeed flushed.
261 */
97f209bc 262 flags |= PIPE_CONTROL_CS_STALL;
7d54a904
CW		 263 }
264 if (invalidate_domains) {
265 flags |= PIPE_CONTROL_TLB_INVALIDATE;
266 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
267 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
268 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
269 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
270 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
271 /*
272 * TLB invalidate requires a post-sync write.
273 */
3ac78313 274 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
7d54a904 275 }
8d315287 276
6c6cf5aa 277 ret = intel_ring_begin(ring, 4);
8d315287
JB		 278 if (ret)
279 return ret;
280
6c6cf5aa 281 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
8d315287
JB		 282 intel_ring_emit(ring, flags);
283 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
6c6cf5aa 284 intel_ring_emit(ring, 0);
8d315287
JB		 285 intel_ring_advance(ring);
286
287 return 0;
288}
289
f3987631 290static int
a4872ba6 291gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
f3987631
PZ		 292{
293 int ret;
294
295 ret = intel_ring_begin(ring, 4);
296 if (ret)
297 return ret;
298
299 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
300 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
301 PIPE_CONTROL_STALL_AT_SCOREBOARD);
302 intel_ring_emit(ring, 0);
303 intel_ring_emit(ring, 0);
304 intel_ring_advance(ring);
305
306 return 0;
307}
308
a4872ba6 309static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value)
fd3da6c9
RV		 310{
311 int ret;
312
313 if (!ring->fbc_dirty)
314 return 0;
315
37c1d94f 316 ret = intel_ring_begin(ring, 6);
fd3da6c9
RV		 317 if (ret)
318 return ret;
fd3da6c9
RV		 319 /* WaFbcNukeOn3DBlt:ivb/hsw */
320 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
321 intel_ring_emit(ring, MSG_FBC_REND_STATE);
322 intel_ring_emit(ring, value);
37c1d94f
VS		 323 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
324 intel_ring_emit(ring, MSG_FBC_REND_STATE);
325 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
fd3da6c9
RV		 326 intel_ring_advance(ring);
327
328 ring->fbc_dirty = false;
329 return 0;
330}
331
4772eaeb 332static int
a4872ba6 333gen7_render_ring_flush(struct intel_engine_cs *ring,
4772eaeb
PZ		 334 u32 invalidate_domains, u32 flush_domains)
335{
336 u32 flags = 0;
18393f63 337 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
4772eaeb
PZ		 338 int ret;
339
f3987631
PZ		 340 /*
341 * Ensure that any following seqno writes only happen when the render
342 * cache is indeed flushed.
343 *
344 * Workaround: 4th PIPE_CONTROL command (except the ones with only
345 * read-cache invalidate bits set) must have the CS_STALL bit set. We
346 * don't try to be clever and just set it unconditionally.
347 */
348 flags |= PIPE_CONTROL_CS_STALL;
349
4772eaeb
PZ		 350 /* Just flush everything. Experiments have shown that reducing the
351 * number of bits based on the write domains has little performance
352 * impact.
353 */
354 if (flush_domains) {
355 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
356 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
4772eaeb
PZ		 357 }
358 if (invalidate_domains) {
359 flags |= PIPE_CONTROL_TLB_INVALIDATE;
360 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
361 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
362 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
363 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
364 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
148b83d0 365 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
4772eaeb
PZ		 366 /*
367 * TLB invalidate requires a post-sync write.
368 */
369 flags |= PIPE_CONTROL_QW_WRITE;
b9e1faa7 370 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
f3987631 371
add284a3
CW		 372 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
373
f3987631
PZ		 374 /* Workaround: we must issue a pipe_control with CS-stall bit
375 * set before a pipe_control command that has the state cache
376 * invalidate bit set. */
377 gen7_render_ring_cs_stall_wa(ring);
4772eaeb
PZ		 378 }
379
380 ret = intel_ring_begin(ring, 4);
381 if (ret)
382 return ret;
383
384 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
385 intel_ring_emit(ring, flags);
b9e1faa7 386 intel_ring_emit(ring, scratch_addr);
4772eaeb
PZ		 387 intel_ring_emit(ring, 0);
388 intel_ring_advance(ring);
389
9688ecad 390 if (!invalidate_domains && flush_domains)
fd3da6c9
RV		 391 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
392
4772eaeb
PZ		 393 return 0;
394}
395
884ceace
KG		 396static int
397gen8_emit_pipe_control(struct intel_engine_cs *ring,
398 u32 flags, u32 scratch_addr)
399{
400 int ret;
401
402 ret = intel_ring_begin(ring, 6);
403 if (ret)
404 return ret;
405
406 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
407 intel_ring_emit(ring, flags);
408 intel_ring_emit(ring, scratch_addr);
409 intel_ring_emit(ring, 0);
410 intel_ring_emit(ring, 0);
411 intel_ring_emit(ring, 0);
412 intel_ring_advance(ring);
413
414 return 0;
415}
416
a5f3d68e 417static int
a4872ba6 418gen8_render_ring_flush(struct intel_engine_cs *ring,
a5f3d68e
BW		 419 u32 invalidate_domains, u32 flush_domains)
420{
421 u32 flags = 0;
18393f63 422 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
02c9f7e3 423 int ret;
a5f3d68e
BW		 424
425 flags |= PIPE_CONTROL_CS_STALL;
426
427 if (flush_domains) {
428 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
429 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
430 }
431 if (invalidate_domains) {
432 flags |= PIPE_CONTROL_TLB_INVALIDATE;
433 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
434 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
435 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
436 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
437 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
438 flags |= PIPE_CONTROL_QW_WRITE;
439 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
02c9f7e3
KG		 440
441 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
442 ret = gen8_emit_pipe_control(ring,
443 PIPE_CONTROL_CS_STALL |
444 PIPE_CONTROL_STALL_AT_SCOREBOARD,
445 0);
446 if (ret)
447 return ret;
a5f3d68e
BW		 448 }
449
c5ad011d
RV		 450 ret = gen8_emit_pipe_control(ring, flags, scratch_addr);
451 if (ret)
452 return ret;
453
454 if (!invalidate_domains && flush_domains)
455 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
456
457 return 0;
a5f3d68e
BW		 458}
459
a4872ba6 460static void ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 461 u32 value)
d46eefa2 462{
4640c4ff 463 struct drm_i915_private *dev_priv = ring->dev->dev_private;
297b0c5b 464 I915_WRITE_TAIL(ring, value);
d46eefa2
XH		 465}
466
a4872ba6 467u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
8187a2b7 468{
4640c4ff 469 struct drm_i915_private *dev_priv = ring->dev->dev_private;
50877445 470 u64 acthd;
8187a2b7 471
50877445
CW		 472 if (INTEL_INFO(ring->dev)->gen >= 8)
473 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
474 RING_ACTHD_UDW(ring->mmio_base));
475 else if (INTEL_INFO(ring->dev)->gen >= 4)
476 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
477 else
478 acthd = I915_READ(ACTHD);
479
480 return acthd;
8187a2b7
ZN		 481}
482
a4872ba6 483static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
035dc1e0
DV		 484{
485 struct drm_i915_private *dev_priv = ring->dev->dev_private;
486 u32 addr;
487
488 addr = dev_priv->status_page_dmah->busaddr;
489 if (INTEL_INFO(ring->dev)->gen >= 4)
490 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
491 I915_WRITE(HWS_PGA, addr);
492}
493
a4872ba6 494static bool stop_ring(struct intel_engine_cs *ring)
8187a2b7 495{
9991ae78 496 struct drm_i915_private *dev_priv = to_i915(ring->dev);
8187a2b7 497
9991ae78
CW		 498 if (!IS_GEN2(ring->dev)) {
499 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
403bdd10
DV		 500 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
501 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
9bec9b13
CW		 502 /* Sometimes we observe that the idle flag is not
503 * set even though the ring is empty. So double
504 * check before giving up.
505 */
506 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
507 return false;
9991ae78
CW		 508 }
509 }
b7884eb4 510
7f2ab699 511 I915_WRITE_CTL(ring, 0);
570ef608 512 I915_WRITE_HEAD(ring, 0);
78501eac 513 ring->write_tail(ring, 0);
8187a2b7 514
9991ae78
CW		 515 if (!IS_GEN2(ring->dev)) {
516 (void)I915_READ_CTL(ring);
517 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
518 }
a51435a3 519
9991ae78
CW		 520 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
521}
8187a2b7 522
a4872ba6 523static int init_ring_common(struct intel_engine_cs *ring)
9991ae78
CW		 524{
525 struct drm_device *dev = ring->dev;
526 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0
OM		 527 struct intel_ringbuffer *ringbuf = ring->buffer;
528 struct drm_i915_gem_object *obj = ringbuf->obj;
9991ae78
CW		 529 int ret = 0;
530
531 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
532
533 if (!stop_ring(ring)) {
534 /* G45 ring initialization often fails to reset head to zero */
6fd0d56e
CW		 535 DRM_DEBUG_KMS("%s head not reset to zero "
536 "ctl %08x head %08x tail %08x start %08x\n",
537 ring->name,
538 I915_READ_CTL(ring),
539 I915_READ_HEAD(ring),
540 I915_READ_TAIL(ring),
541 I915_READ_START(ring));
8187a2b7 542
9991ae78 543 if (!stop_ring(ring)) {
6fd0d56e
CW		 544 DRM_ERROR("failed to set %s head to zero "
545 "ctl %08x head %08x tail %08x start %08x\n",
546 ring->name,
547 I915_READ_CTL(ring),
548 I915_READ_HEAD(ring),
549 I915_READ_TAIL(ring),
550 I915_READ_START(ring));
9991ae78
CW		 551 ret = -EIO;
552 goto out;
6fd0d56e 553 }
8187a2b7
ZN		 554 }
555
9991ae78
CW		 556 if (I915_NEED_GFX_HWS(dev))
557 intel_ring_setup_status_page(ring);
558 else
559 ring_setup_phys_status_page(ring);
560
ece4a17d
JK		 561 /* Enforce ordering by reading HEAD register back */
562 I915_READ_HEAD(ring);
563
0d8957c8
DV		 564 /* Initialize the ring. This must happen _after_ we've cleared the ring
565 * registers with the above sequence (the readback of the HEAD registers
566 * also enforces ordering), otherwise the hw might lose the new ring
567 * register values. */
f343c5f6 568 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
95468892
CW		 569
570 /* WaClearRingBufHeadRegAtInit:ctg,elk */
571 if (I915_READ_HEAD(ring))
572 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
573 ring->name, I915_READ_HEAD(ring));
574 I915_WRITE_HEAD(ring, 0);
575 (void)I915_READ_HEAD(ring);
576
7f2ab699 577 I915_WRITE_CTL(ring,
93b0a4e0 578 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
5d031e5b 579 | RING_VALID);
8187a2b7 580
8187a2b7 581 /* If the head is still not zero, the ring is dead */
f01db988 582 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
f343c5f6 583 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
f01db988 584 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
e74cfed5 585 DRM_ERROR("%s initialization failed "
48e48a0b
CW		 586 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
587 ring->name,
588 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
589 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
590 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
b7884eb4
DV		 591 ret = -EIO;
592 goto out;
8187a2b7
ZN		 593 }
594
5c6c6003
CW		 595 ringbuf->head = I915_READ_HEAD(ring);
596 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
597 ringbuf->space = intel_ring_space(ringbuf);
598 ringbuf->last_retired_head = -1;
1ec14ad3 599
50f018df
CW		 600 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
601
b7884eb4 602out:
c8d9a590 603 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
b7884eb4
DV		 604
605 return ret;
8187a2b7
ZN		 606}
607
9b1136d5
OM		 608void
609intel_fini_pipe_control(struct intel_engine_cs *ring)
610{
611 struct drm_device *dev = ring->dev;
612
613 if (ring->scratch.obj == NULL)
614 return;
615
616 if (INTEL_INFO(dev)->gen >= 5) {
617 kunmap(sg_page(ring->scratch.obj->pages->sgl));
618 i915_gem_object_ggtt_unpin(ring->scratch.obj);
619 }
620
621 drm_gem_object_unreference(&ring->scratch.obj->base);
622 ring->scratch.obj = NULL;
623}
624
625int
626intel_init_pipe_control(struct intel_engine_cs *ring)
c6df541c 627{
c6df541c
CW		 628 int ret;
629
0d1aacac 630 if (ring->scratch.obj)
c6df541c
CW		 631 return 0;
632
0d1aacac
CW		 633 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
634 if (ring->scratch.obj == NULL) {
c6df541c
CW		 635 DRM_ERROR("Failed to allocate seqno page\n");
636 ret = -ENOMEM;
637 goto err;
638 }
e4ffd173 639
a9cc726c
DV		 640 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
641 if (ret)
642 goto err_unref;
c6df541c 643
1ec9e26d 644 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
c6df541c
CW		 645 if (ret)
646 goto err_unref;
647
0d1aacac
CW		 648 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
649 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
650 if (ring->scratch.cpu_page == NULL) {
56b085a0 651 ret = -ENOMEM;
c6df541c 652 goto err_unpin;
56b085a0 653 }
c6df541c 654
2b1086cc 655 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
0d1aacac 656 ring->name, ring->scratch.gtt_offset);
c6df541c
CW		 657 return 0;
658
659err_unpin:
d7f46fc4 660 i915_gem_object_ggtt_unpin(ring->scratch.obj);
c6df541c 661err_unref:
0d1aacac 662 drm_gem_object_unreference(&ring->scratch.obj->base);
c6df541c 663err:
c6df541c
CW		 664 return ret;
665}
666
771b9a53
MT		 667static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
668 struct intel_context *ctx)
86d7f238 669{
7225342a 670 int ret, i;
888b5995
AS		 671 struct drm_device *dev = ring->dev;
672 struct drm_i915_private *dev_priv = dev->dev_private;
7225342a 673 struct i915_workarounds *w = &dev_priv->workarounds;
888b5995 674
7225342a
MK		 675 if (WARN_ON(w->count == 0))
676 return 0;
888b5995 677
7225342a
MK		 678 ring->gpu_caches_dirty = true;
679 ret = intel_ring_flush_all_caches(ring);
680 if (ret)
681 return ret;
888b5995 682
22a916aa 683 ret = intel_ring_begin(ring, (w->count * 2 + 2));
7225342a
MK		 684 if (ret)
685 return ret;
686
22a916aa 687 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
7225342a 688 for (i = 0; i < w->count; i++) {
7225342a
MK		 689 intel_ring_emit(ring, w->reg[i].addr);
690 intel_ring_emit(ring, w->reg[i].value);
691 }
22a916aa 692 intel_ring_emit(ring, MI_NOOP);
7225342a
MK		 693
694 intel_ring_advance(ring);
695
696 ring->gpu_caches_dirty = true;
697 ret = intel_ring_flush_all_caches(ring);
698 if (ret)
699 return ret;
888b5995 700
7225342a 701 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
888b5995 702
7225342a 703 return 0;
86d7f238
AS		 704}
705
7225342a 706static int wa_add(struct drm_i915_private *dev_priv,
cf4b0de6 707 const u32 addr, const u32 mask, const u32 val)
7225342a
MK		 708{
709 const u32 idx = dev_priv->workarounds.count;
710
711 if (WARN_ON(idx >= I915_MAX_WA_REGS))
712 return -ENOSPC;
713
714 dev_priv->workarounds.reg[idx].addr = addr;
715 dev_priv->workarounds.reg[idx].value = val;
716 dev_priv->workarounds.reg[idx].mask = mask;
717
718 dev_priv->workarounds.count++;
719
720 return 0;
86d7f238
AS		 721}
722
cf4b0de6
DL		 723#define WA_REG(addr, mask, val) { \
724 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
7225342a
MK		 725 if (r) \
726 return r; \
727 }
728
729#define WA_SET_BIT_MASKED(addr, mask) \
26459343 730 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
7225342a
MK		 731
732#define WA_CLR_BIT_MASKED(addr, mask) \
26459343 733 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
7225342a 734
98533251 735#define WA_SET_FIELD_MASKED(addr, mask, value) \
cf4b0de6 736 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
98533251 737
cf4b0de6
DL		 738#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
739#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
7225342a 740
cf4b0de6 741#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
7225342a 742
00e1e623 743static int bdw_init_workarounds(struct intel_engine_cs *ring)
86d7f238 744{
888b5995
AS		 745 struct drm_device *dev = ring->dev;
746 struct drm_i915_private *dev_priv = dev->dev_private;
86d7f238 747
86d7f238 748 /* WaDisablePartialInstShootdown:bdw */
101b376d 749 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
7225342a
MK		 750 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
751 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
752 STALL_DOP_GATING_DISABLE);
86d7f238 753
101b376d 754 /* WaDisableDopClockGating:bdw */
7225342a
MK		 755 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
756 DOP_CLOCK_GATING_DISABLE);
86d7f238 757
7225342a
MK		 758 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
759 GEN8_SAMPLER_POWER_BYPASS_DIS);
86d7f238
AS		 760
761 /* Use Force Non-Coherent whenever executing a 3D context. This is a
762 * workaround for for a possible hang in the unlikely event a TLB
763 * invalidation occurs during a PSD flush.
764 */
da09654d 765 /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
7225342a
MK		 766 WA_SET_BIT_MASKED(HDC_CHICKEN0,
767 HDC_FORCE_NON_COHERENT |
768 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
86d7f238
AS		 769
770 /* Wa4x4STCOptimizationDisable:bdw */
7225342a
MK		 771 WA_SET_BIT_MASKED(CACHE_MODE_1,
772 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
86d7f238
AS		 773
774 /*
775 * BSpec recommends 8x4 when MSAA is used,
776 * however in practice 16x4 seems fastest.
777 *
778 * Note that PS/WM thread counts depend on the WIZ hashing
779 * disable bit, which we don't touch here, but it's good
780 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
781 */
98533251
DL		 782 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
783 GEN6_WIZ_HASHING_MASK,
784 GEN6_WIZ_HASHING_16x4);
888b5995 785
86d7f238
AS		 786 return 0;
787}
788
00e1e623
VS		 789static int chv_init_workarounds(struct intel_engine_cs *ring)
790{
00e1e623
VS		 791 struct drm_device *dev = ring->dev;
792 struct drm_i915_private *dev_priv = dev->dev_private;
793
00e1e623 794 /* WaDisablePartialInstShootdown:chv */
00e1e623 795 /* WaDisableThreadStallDopClockGating:chv */
7225342a 796 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
605f1433
AS		 797 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
798 STALL_DOP_GATING_DISABLE);
00e1e623 799
95289009
AS		 800 /* Use Force Non-Coherent whenever executing a 3D context. This is a
801 * workaround for a possible hang in the unlikely event a TLB
802 * invalidation occurs during a PSD flush.
803 */
804 /* WaForceEnableNonCoherent:chv */
805 /* WaHdcDisableFetchWhenMasked:chv */
806 WA_SET_BIT_MASKED(HDC_CHICKEN0,
807 HDC_FORCE_NON_COHERENT |
808 HDC_DONOT_FETCH_MEM_WHEN_MASKED);
809
7225342a
MK		 810 return 0;
811}
812
771b9a53 813int init_workarounds_ring(struct intel_engine_cs *ring)
7225342a
MK		 814{
815 struct drm_device *dev = ring->dev;
816 struct drm_i915_private *dev_priv = dev->dev_private;
817
818 WARN_ON(ring->id != RCS);
819
820 dev_priv->workarounds.count = 0;
821
822 if (IS_BROADWELL(dev))
823 return bdw_init_workarounds(ring);
824
825 if (IS_CHERRYVIEW(dev))
826 return chv_init_workarounds(ring);
00e1e623
VS		 827
828 return 0;
829}
830
a4872ba6 831static int init_render_ring(struct intel_engine_cs *ring)
8187a2b7 832{
78501eac 833 struct drm_device *dev = ring->dev;
1ec14ad3 834 struct drm_i915_private *dev_priv = dev->dev_private;
78501eac 835 int ret = init_ring_common(ring);
9c33baa6
KZ		 836 if (ret)
837 return ret;
a69ffdbf 838
61a563a2
AG		 839 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
840 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
6b26c86d 841 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1c8c38c5
CW		 842
843 /* We need to disable the AsyncFlip performance optimisations in order
844 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
845 * programmed to '1' on all products.
8693a824 846 *
b3f797ac 847 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1c8c38c5 848 */
fbdcb068 849 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
1c8c38c5
CW		 850 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
851
f05bb0c7 852 /* Required for the hardware to program scanline values for waiting */
01fa0302 853 /* WaEnableFlushTlbInvalidationMode:snb */
f05bb0c7
CW		 854 if (INTEL_INFO(dev)->gen == 6)
855 I915_WRITE(GFX_MODE,
aa83e30d 856 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
f05bb0c7 857
01fa0302 858 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1c8c38c5
CW		 859 if (IS_GEN7(dev))
860 I915_WRITE(GFX_MODE_GEN7,
01fa0302 861 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1c8c38c5 862 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
78501eac 863
8d315287 864 if (INTEL_INFO(dev)->gen >= 5) {
9b1136d5 865 ret = intel_init_pipe_control(ring);
c6df541c
CW		 866 if (ret)
867 return ret;
868 }
869
5e13a0c5 870 if (IS_GEN6(dev)) {
3a69ddd6
KG		 871 /* From the Sandybridge PRM, volume 1 part 3, page 24:
872 * "If this bit is set, STCunit will have LRA as replacement
873 * policy. [...] This bit must be reset. LRA replacement
874 * policy is not supported."
875 */
876 I915_WRITE(CACHE_MODE_0,
5e13a0c5 877 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
84f9f938
BW		 878 }
879
6b26c86d
DV		 880 if (INTEL_INFO(dev)->gen >= 6)
881 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
84f9f938 882
040d2baa 883 if (HAS_L3_DPF(dev))
35a85ac6 884 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e 885
7225342a 886 return init_workarounds_ring(ring);
8187a2b7
ZN		 887}
888
a4872ba6 889static void render_ring_cleanup(struct intel_engine_cs *ring)
c6df541c 890{
b45305fc 891 struct drm_device *dev = ring->dev;
3e78998a
BW		 892 struct drm_i915_private *dev_priv = dev->dev_private;
893
894 if (dev_priv->semaphore_obj) {
895 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
896 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
897 dev_priv->semaphore_obj = NULL;
898 }
b45305fc 899
9b1136d5 900 intel_fini_pipe_control(ring);
c6df541c
CW		 901}
902
3e78998a
BW		 903static int gen8_rcs_signal(struct intel_engine_cs *signaller,
904 unsigned int num_dwords)
905{
906#define MBOX_UPDATE_DWORDS 8
907 struct drm_device *dev = signaller->dev;
908 struct drm_i915_private *dev_priv = dev->dev_private;
909 struct intel_engine_cs *waiter;
910 int i, ret, num_rings;
911
912 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
913 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
914#undef MBOX_UPDATE_DWORDS
915
916 ret = intel_ring_begin(signaller, num_dwords);
917 if (ret)
918 return ret;
919
920 for_each_ring(waiter, dev_priv, i) {
921 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
922 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
923 continue;
924
925 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
926 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
927 PIPE_CONTROL_QW_WRITE |
928 PIPE_CONTROL_FLUSH_ENABLE);
929 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
930 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
931 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
932 intel_ring_emit(signaller, 0);
933 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
934 MI_SEMAPHORE_TARGET(waiter->id));
935 intel_ring_emit(signaller, 0);
936 }
937
938 return 0;
939}
940
941static int gen8_xcs_signal(struct intel_engine_cs *signaller,
942 unsigned int num_dwords)
943{
944#define MBOX_UPDATE_DWORDS 6
945 struct drm_device *dev = signaller->dev;
946 struct drm_i915_private *dev_priv = dev->dev_private;
947 struct intel_engine_cs *waiter;
948 int i, ret, num_rings;
949
950 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
951 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
952#undef MBOX_UPDATE_DWORDS
953
954 ret = intel_ring_begin(signaller, num_dwords);
955 if (ret)
956 return ret;
957
958 for_each_ring(waiter, dev_priv, i) {
959 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
960 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
961 continue;
962
963 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
964 MI_FLUSH_DW_OP_STOREDW);
965 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
966 MI_FLUSH_DW_USE_GTT);
967 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
968 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
969 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
970 MI_SEMAPHORE_TARGET(waiter->id));
971 intel_ring_emit(signaller, 0);
972 }
973
974 return 0;
975}
976
a4872ba6 977static int gen6_signal(struct intel_engine_cs *signaller,
024a43e1 978 unsigned int num_dwords)
1ec14ad3 979{
024a43e1
BW		 980 struct drm_device *dev = signaller->dev;
981 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 982 struct intel_engine_cs *useless;
a1444b79 983 int i, ret, num_rings;
78325f2d 984
a1444b79
BW		 985#define MBOX_UPDATE_DWORDS 3
986 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
987 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
988#undef MBOX_UPDATE_DWORDS
024a43e1
BW		 989
990 ret = intel_ring_begin(signaller, num_dwords);
991 if (ret)
992 return ret;
024a43e1 993
78325f2d
BW		 994 for_each_ring(useless, dev_priv, i) {
995 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
996 if (mbox_reg != GEN6_NOSYNC) {
997 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
998 intel_ring_emit(signaller, mbox_reg);
999 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
78325f2d
BW		 1000 }
1001 }
024a43e1 1002
a1444b79
BW		 1003 /* If num_dwords was rounded, make sure the tail pointer is correct */
1004 if (num_rings % 2 == 0)
1005 intel_ring_emit(signaller, MI_NOOP);
1006
024a43e1 1007 return 0;
1ec14ad3
CW		 1008}
1009
c8c99b0f
BW		 1010/**
1011 * gen6_add_request - Update the semaphore mailbox registers
1012 *
1013 * @ring - ring that is adding a request
1014 * @seqno - return seqno stuck into the ring
1015 *
1016 * Update the mailbox registers in the *other* rings with the current seqno.
1017 * This acts like a signal in the canonical semaphore.
1018 */
1ec14ad3 1019static int
a4872ba6 1020gen6_add_request(struct intel_engine_cs *ring)
1ec14ad3 1021{
024a43e1 1022 int ret;
52ed2325 1023
707d9cf9
BW		 1024 if (ring->semaphore.signal)
1025 ret = ring->semaphore.signal(ring, 4);
1026 else
1027 ret = intel_ring_begin(ring, 4);
1028
1ec14ad3
CW		 1029 if (ret)
1030 return ret;
1031
1ec14ad3
CW		 1032 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1033 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1823521d 1034 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1ec14ad3 1035 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1036 __intel_ring_advance(ring);
1ec14ad3 1037
1ec14ad3
CW		 1038 return 0;
1039}
1040
f72b3435
MK		 1041static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1042 u32 seqno)
1043{
1044 struct drm_i915_private *dev_priv = dev->dev_private;
1045 return dev_priv->last_seqno < seqno;
1046}
1047
c8c99b0f
BW		 1048/**
1049 * intel_ring_sync - sync the waiter to the signaller on seqno
1050 *
1051 * @waiter - ring that is waiting
1052 * @signaller - ring which has, or will signal
1053 * @seqno - seqno which the waiter will block on
1054 */
5ee426ca
BW		 1055
1056static int
1057gen8_ring_sync(struct intel_engine_cs *waiter,
1058 struct intel_engine_cs *signaller,
1059 u32 seqno)
1060{
1061 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1062 int ret;
1063
1064 ret = intel_ring_begin(waiter, 4);
1065 if (ret)
1066 return ret;
1067
1068 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1069 MI_SEMAPHORE_GLOBAL_GTT |
bae4fcd2 1070 MI_SEMAPHORE_POLL |
5ee426ca
BW		 1071 MI_SEMAPHORE_SAD_GTE_SDD);
1072 intel_ring_emit(waiter, seqno);
1073 intel_ring_emit(waiter,
1074 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1075 intel_ring_emit(waiter,
1076 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1077 intel_ring_advance(waiter);
1078 return 0;
1079}
1080
c8c99b0f 1081static int
a4872ba6
OM		 1082gen6_ring_sync(struct intel_engine_cs *waiter,
1083 struct intel_engine_cs *signaller,
686cb5f9 1084 u32 seqno)
1ec14ad3 1085{
c8c99b0f
BW		 1086 u32 dw1 = MI_SEMAPHORE_MBOX |
1087 MI_SEMAPHORE_COMPARE |
1088 MI_SEMAPHORE_REGISTER;
ebc348b2
BW		 1089 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1090 int ret;
1ec14ad3 1091
1500f7ea
BW		 1092 /* Throughout all of the GEM code, seqno passed implies our current
1093 * seqno is >= the last seqno executed. However for hardware the
1094 * comparison is strictly greater than.
1095 */
1096 seqno -= 1;
1097
ebc348b2 1098 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
686cb5f9 1099
c8c99b0f 1100 ret = intel_ring_begin(waiter, 4);
1ec14ad3
CW		 1101 if (ret)
1102 return ret;
1103
f72b3435
MK		 1104 /* If seqno wrap happened, omit the wait with no-ops */
1105 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
ebc348b2 1106 intel_ring_emit(waiter, dw1 | wait_mbox);
f72b3435
MK		 1107 intel_ring_emit(waiter, seqno);
1108 intel_ring_emit(waiter, 0);
1109 intel_ring_emit(waiter, MI_NOOP);
1110 } else {
1111 intel_ring_emit(waiter, MI_NOOP);
1112 intel_ring_emit(waiter, MI_NOOP);
1113 intel_ring_emit(waiter, MI_NOOP);
1114 intel_ring_emit(waiter, MI_NOOP);
1115 }
c8c99b0f 1116 intel_ring_advance(waiter);
1ec14ad3
CW		 1117
1118 return 0;
1119}
1120
c6df541c
CW		 1121#define PIPE_CONTROL_FLUSH(ring__, addr__) \
1122do { \
fcbc34e4
KG		 1123 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1124 PIPE_CONTROL_DEPTH_STALL); \
c6df541c
CW		 1125 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1126 intel_ring_emit(ring__, 0); \
1127 intel_ring_emit(ring__, 0); \
1128} while (0)
1129
1130static int
a4872ba6 1131pc_render_add_request(struct intel_engine_cs *ring)
c6df541c 1132{
18393f63 1133 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
c6df541c
CW		 1134 int ret;
1135
1136 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1137 * incoherent with writes to memory, i.e. completely fubar,
1138 * so we need to use PIPE_NOTIFY instead.
1139 *
1140 * However, we also need to workaround the qword write
1141 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1142 * memory before requesting an interrupt.
1143 */
1144 ret = intel_ring_begin(ring, 32);
1145 if (ret)
1146 return ret;
1147
fcbc34e4 1148 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1149 PIPE_CONTROL_WRITE_FLUSH |
1150 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
0d1aacac 1151 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1823521d 1152 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
c6df541c
CW		 1153 intel_ring_emit(ring, 0);
1154 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1155 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
c6df541c 1156 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1157 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1158 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1159 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1160 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1161 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1162 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1163 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1164 PIPE_CONTROL_FLUSH(ring, scratch_addr);
a71d8d94 1165
fcbc34e4 1166 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1167 PIPE_CONTROL_WRITE_FLUSH |
1168 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
c6df541c 1169 PIPE_CONTROL_NOTIFY);
0d1aacac 1170 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1823521d 1171 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
c6df541c 1172 intel_ring_emit(ring, 0);
09246732 1173 __intel_ring_advance(ring);
c6df541c 1174
c6df541c
CW		 1175 return 0;
1176}
1177
4cd53c0c 1178static u32
a4872ba6 1179gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
4cd53c0c 1180{
4cd53c0c
DV		 1181 /* Workaround to force correct ordering between irq and seqno writes on
1182 * ivb (and maybe also on snb) by reading from a CS register (like
1183 * ACTHD) before reading the status page. */
50877445
CW		 1184 if (!lazy_coherency) {
1185 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1186 POSTING_READ(RING_ACTHD(ring->mmio_base));
1187 }
1188
4cd53c0c
DV		 1189 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1190}
1191
8187a2b7 1192static u32
a4872ba6 1193ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
8187a2b7 1194{
1ec14ad3
CW		 1195 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1196}
1197
b70ec5bf 1198static void
a4872ba6 1199ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf
MK		 1200{
1201 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1202}
1203
c6df541c 1204static u32
a4872ba6 1205pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
c6df541c 1206{
0d1aacac 1207 return ring->scratch.cpu_page[0];
c6df541c
CW		 1208}
1209
b70ec5bf 1210static void
a4872ba6 1211pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf 1212{
0d1aacac 1213 ring->scratch.cpu_page[0] = seqno;
b70ec5bf
MK		 1214}
1215
e48d8634 1216static bool
a4872ba6 1217gen5_ring_get_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1218{
1219 struct drm_device *dev = ring->dev;
4640c4ff 1220 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1221 unsigned long flags;
e48d8634 1222
7cd512f1 1223 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
e48d8634
DV		 1224 return false;
1225
7338aefa 1226 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1227 if (ring->irq_refcount++ == 0)
480c8033 1228 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1229 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1230
1231 return true;
1232}
1233
1234static void
a4872ba6 1235gen5_ring_put_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1236{
1237 struct drm_device *dev = ring->dev;
4640c4ff 1238 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1239 unsigned long flags;
e48d8634 1240
7338aefa 1241 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1242 if (--ring->irq_refcount == 0)
480c8033 1243 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1244 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1245}
1246
b13c2b96 1247static bool
a4872ba6 1248i9xx_ring_get_irq(struct intel_engine_cs *ring)
62fdfeaf 1249{
78501eac 1250 struct drm_device *dev = ring->dev;
4640c4ff 1251 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1252 unsigned long flags;
62fdfeaf 1253
7cd512f1 1254 if (!intel_irqs_enabled(dev_priv))
b13c2b96
CW		 1255 return false;
1256
7338aefa 1257 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1258 if (ring->irq_refcount++ == 0) {
f637fde4
DV		 1259 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1260 I915_WRITE(IMR, dev_priv->irq_mask);
1261 POSTING_READ(IMR);
1262 }
7338aefa 1263 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
b13c2b96
CW		 1264
1265 return true;
62fdfeaf
EA		 1266}
1267
8187a2b7 1268static void
a4872ba6 1269i9xx_ring_put_irq(struct intel_engine_cs *ring)
62fdfeaf 1270{
78501eac 1271 struct drm_device *dev = ring->dev;
4640c4ff 1272 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1273 unsigned long flags;
62fdfeaf 1274
7338aefa 1275 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1276 if (--ring->irq_refcount == 0) {
f637fde4
DV		 1277 dev_priv->irq_mask |= ring->irq_enable_mask;
1278 I915_WRITE(IMR, dev_priv->irq_mask);
1279 POSTING_READ(IMR);
1280 }
7338aefa 1281 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
62fdfeaf
EA		 1282}
1283
c2798b19 1284static bool
a4872ba6 1285i8xx_ring_get_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1286{
1287 struct drm_device *dev = ring->dev;
4640c4ff 1288 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1289 unsigned long flags;
c2798b19 1290
7cd512f1 1291 if (!intel_irqs_enabled(dev_priv))
c2798b19
CW		 1292 return false;
1293
7338aefa 1294 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1295 if (ring->irq_refcount++ == 0) {
c2798b19
CW		 1296 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1297 I915_WRITE16(IMR, dev_priv->irq_mask);
1298 POSTING_READ16(IMR);
1299 }
7338aefa 1300 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1301
1302 return true;
1303}
1304
1305static void
a4872ba6 1306i8xx_ring_put_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1307{
1308 struct drm_device *dev = ring->dev;
4640c4ff 1309 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1310 unsigned long flags;
c2798b19 1311
7338aefa 1312 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1313 if (--ring->irq_refcount == 0) {
c2798b19
CW		 1314 dev_priv->irq_mask |= ring->irq_enable_mask;
1315 I915_WRITE16(IMR, dev_priv->irq_mask);
1316 POSTING_READ16(IMR);
1317 }
7338aefa 1318 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1319}
1320
a4872ba6 1321void intel_ring_setup_status_page(struct intel_engine_cs *ring)
8187a2b7 1322{
4593010b 1323 struct drm_device *dev = ring->dev;
4640c4ff 1324 struct drm_i915_private *dev_priv = ring->dev->dev_private;
4593010b
EA		 1325 u32 mmio = 0;
1326
1327 /* The ring status page addresses are no longer next to the rest of
1328 * the ring registers as of gen7.
1329 */
1330 if (IS_GEN7(dev)) {
1331 switch (ring->id) {
96154f2f 1332 case RCS:
4593010b
EA		 1333 mmio = RENDER_HWS_PGA_GEN7;
1334 break;
96154f2f 1335 case BCS:
4593010b
EA		 1336 mmio = BLT_HWS_PGA_GEN7;
1337 break;
77fe2ff3
ZY		 1338 /*
1339 * VCS2 actually doesn't exist on Gen7. Only shut up
1340 * gcc switch check warning
1341 */
1342 case VCS2:
96154f2f 1343 case VCS:
4593010b
EA		 1344 mmio = BSD_HWS_PGA_GEN7;
1345 break;
4a3dd19d 1346 case VECS:
9a8a2213
BW		 1347 mmio = VEBOX_HWS_PGA_GEN7;
1348 break;
4593010b
EA		 1349 }
1350 } else if (IS_GEN6(ring->dev)) {
1351 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
1352 } else {
eb0d4b75 1353 /* XXX: gen8 returns to sanity */
4593010b
EA		 1354 mmio = RING_HWS_PGA(ring->mmio_base);
1355 }
1356
78501eac
CW		 1357 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
1358 POSTING_READ(mmio);
884020bf 1359
dc616b89
DL		 1360 /*
1361 * Flush the TLB for this page
1362 *
1363 * FIXME: These two bits have disappeared on gen8, so a question
1364 * arises: do we still need this and if so how should we go about
1365 * invalidating the TLB?
1366 */
1367 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
884020bf 1368 u32 reg = RING_INSTPM(ring->mmio_base);
02f6a1e7
NKK		 1369
1370 /* ring should be idle before issuing a sync flush*/
1371 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1372
884020bf
CW		 1373 I915_WRITE(reg,
1374 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
1375 INSTPM_SYNC_FLUSH));
1376 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
1377 1000))
1378 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1379 ring->name);
1380 }
8187a2b7
ZN		 1381}
1382
b72f3acb 1383static int
a4872ba6 1384bsd_ring_flush(struct intel_engine_cs *ring,
78501eac
CW		 1385 u32 invalidate_domains,
1386 u32 flush_domains)
d1b851fc 1387{
b72f3acb
CW		 1388 int ret;
1389
b72f3acb
CW		 1390 ret = intel_ring_begin(ring, 2);
1391 if (ret)
1392 return ret;
1393
1394 intel_ring_emit(ring, MI_FLUSH);
1395 intel_ring_emit(ring, MI_NOOP);
1396 intel_ring_advance(ring);
1397 return 0;
d1b851fc
ZN		 1398}
1399
3cce469c 1400static int
a4872ba6 1401i9xx_add_request(struct intel_engine_cs *ring)
d1b851fc 1402{
3cce469c
CW		 1403 int ret;
1404
1405 ret = intel_ring_begin(ring, 4);
1406 if (ret)
1407 return ret;
6f392d54 1408
3cce469c
CW		 1409 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1410 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1823521d 1411 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
3cce469c 1412 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1413 __intel_ring_advance(ring);
d1b851fc 1414
3cce469c 1415 return 0;
d1b851fc
ZN		 1416}
1417
0f46832f 1418static bool
a4872ba6 1419gen6_ring_get_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1420{
1421 struct drm_device *dev = ring->dev;
4640c4ff 1422 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1423 unsigned long flags;
0f46832f 1424
7cd512f1
DV		 1425 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1426 return false;
0f46832f 1427
7338aefa 1428 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1429 if (ring->irq_refcount++ == 0) {
040d2baa 1430 if (HAS_L3_DPF(dev) && ring->id == RCS)
cc609d5d
BW		 1431 I915_WRITE_IMR(ring,
1432 ~(ring->irq_enable_mask |
35a85ac6 1433 GT_PARITY_ERROR(dev)));
15b9f80e
BW		 1434 else
1435 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1436 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
0f46832f 1437 }
7338aefa 1438 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
0f46832f
CW		 1439
1440 return true;
1441}
1442
1443static void
a4872ba6 1444gen6_ring_put_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1445{
1446 struct drm_device *dev = ring->dev;
4640c4ff 1447 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1448 unsigned long flags;
0f46832f 1449
7338aefa 1450 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1451 if (--ring->irq_refcount == 0) {
040d2baa 1452 if (HAS_L3_DPF(dev) && ring->id == RCS)
35a85ac6 1453 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e
BW		 1454 else
1455 I915_WRITE_IMR(ring, ~0);
480c8033 1456 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1ec14ad3 1457 }
7338aefa 1458 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
d1b851fc
ZN		 1459}
1460
a19d2933 1461static bool
a4872ba6 1462hsw_vebox_get_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1463{
1464 struct drm_device *dev = ring->dev;
1465 struct drm_i915_private *dev_priv = dev->dev_private;
1466 unsigned long flags;
1467
7cd512f1 1468 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
a19d2933
BW		 1469 return false;
1470
59cdb63d 1471 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1472 if (ring->irq_refcount++ == 0) {
a19d2933 1473 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1474 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1475 }
59cdb63d 1476 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1477
1478 return true;
1479}
1480
1481static void
a4872ba6 1482hsw_vebox_put_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1483{
1484 struct drm_device *dev = ring->dev;
1485 struct drm_i915_private *dev_priv = dev->dev_private;
1486 unsigned long flags;
1487
59cdb63d 1488 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1489 if (--ring->irq_refcount == 0) {
a19d2933 1490 I915_WRITE_IMR(ring, ~0);
480c8033 1491 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1492 }
59cdb63d 1493 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1494}
1495
abd58f01 1496static bool
a4872ba6 1497gen8_ring_get_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1498{
1499 struct drm_device *dev = ring->dev;
1500 struct drm_i915_private *dev_priv = dev->dev_private;
1501 unsigned long flags;
1502
7cd512f1 1503 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
abd58f01
BW		 1504 return false;
1505
1506 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1507 if (ring->irq_refcount++ == 0) {
1508 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1509 I915_WRITE_IMR(ring,
1510 ~(ring->irq_enable_mask |
1511 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1512 } else {
1513 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1514 }
1515 POSTING_READ(RING_IMR(ring->mmio_base));
1516 }
1517 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1518
1519 return true;
1520}
1521
1522static void
a4872ba6 1523gen8_ring_put_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1524{
1525 struct drm_device *dev = ring->dev;
1526 struct drm_i915_private *dev_priv = dev->dev_private;
1527 unsigned long flags;
1528
1529 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1530 if (--ring->irq_refcount == 0) {
1531 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1532 I915_WRITE_IMR(ring,
1533 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1534 } else {
1535 I915_WRITE_IMR(ring, ~0);
1536 }
1537 POSTING_READ(RING_IMR(ring->mmio_base));
1538 }
1539 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1540}
1541
d1b851fc 1542static int
a4872ba6 1543i965_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1544 u64 offset, u32 length,
d7d4eedd 1545 unsigned flags)
d1b851fc 1546{
e1f99ce6 1547 int ret;
78501eac 1548
e1f99ce6
CW		 1549 ret = intel_ring_begin(ring, 2);
1550 if (ret)
1551 return ret;
1552
78501eac 1553 intel_ring_emit(ring,
65f56876
CW		 1554 MI_BATCH_BUFFER_START |
1555 MI_BATCH_GTT |
d7d4eedd 1556 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
c4e7a414 1557 intel_ring_emit(ring, offset);
78501eac
CW		 1558 intel_ring_advance(ring);
1559
d1b851fc
ZN		 1560 return 0;
1561}
1562
b45305fc
DV		 1563/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1564#define I830_BATCH_LIMIT (256*1024)
c4d69da1
CW		 1565#define I830_TLB_ENTRIES (2)
1566#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
8187a2b7 1567static int
a4872ba6 1568i830_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1569 u64 offset, u32 len,
d7d4eedd 1570 unsigned flags)
62fdfeaf 1571{
c4d69da1 1572 u32 cs_offset = ring->scratch.gtt_offset;
c4e7a414 1573 int ret;
62fdfeaf 1574
c4d69da1
CW		 1575 ret = intel_ring_begin(ring, 6);
1576 if (ret)
1577 return ret;
62fdfeaf 1578
c4d69da1
CW		 1579 /* Evict the invalid PTE TLBs */
1580 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1581 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1582 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1583 intel_ring_emit(ring, cs_offset);
1584 intel_ring_emit(ring, 0xdeadbeef);
1585 intel_ring_emit(ring, MI_NOOP);
1586 intel_ring_advance(ring);
b45305fc 1587
c4d69da1 1588 if ((flags & I915_DISPATCH_PINNED) == 0) {
b45305fc
DV		 1589 if (len > I830_BATCH_LIMIT)
1590 return -ENOSPC;
1591
c4d69da1 1592 ret = intel_ring_begin(ring, 6 + 2);
b45305fc
DV		 1593 if (ret)
1594 return ret;
c4d69da1
CW		 1595
1596 /* Blit the batch (which has now all relocs applied) to the
1597 * stable batch scratch bo area (so that the CS never
1598 * stumbles over its tlb invalidation bug) ...
1599 */
1600 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1601 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
611a7a4f 1602 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
b45305fc 1603 intel_ring_emit(ring, cs_offset);
b45305fc
DV		 1604 intel_ring_emit(ring, 4096);
1605 intel_ring_emit(ring, offset);
c4d69da1 1606
b45305fc 1607 intel_ring_emit(ring, MI_FLUSH);
c4d69da1
CW		 1608 intel_ring_emit(ring, MI_NOOP);
1609 intel_ring_advance(ring);
b45305fc
DV		 1610
1611 /* ... and execute it. */
c4d69da1 1612 offset = cs_offset;
b45305fc 1613 }
e1f99ce6 1614
c4d69da1
CW		 1615 ret = intel_ring_begin(ring, 4);
1616 if (ret)
1617 return ret;
1618
1619 intel_ring_emit(ring, MI_BATCH_BUFFER);
1620 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1621 intel_ring_emit(ring, offset + len - 8);
1622 intel_ring_emit(ring, MI_NOOP);
1623 intel_ring_advance(ring);
1624
fb3256da
DV		 1625 return 0;
1626}
1627
1628static int
a4872ba6 1629i915_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1630 u64 offset, u32 len,
d7d4eedd 1631 unsigned flags)
fb3256da
DV		 1632{
1633 int ret;
1634
1635 ret = intel_ring_begin(ring, 2);
1636 if (ret)
1637 return ret;
1638
65f56876 1639 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
d7d4eedd 1640 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
c4e7a414 1641 intel_ring_advance(ring);
62fdfeaf 1642
62fdfeaf
EA		 1643 return 0;
1644}
1645
a4872ba6 1646static void cleanup_status_page(struct intel_engine_cs *ring)
62fdfeaf 1647{
05394f39 1648 struct drm_i915_gem_object *obj;
62fdfeaf 1649
8187a2b7
ZN		 1650 obj = ring->status_page.obj;
1651 if (obj == NULL)
62fdfeaf 1652 return;
62fdfeaf 1653
9da3da66 1654 kunmap(sg_page(obj->pages->sgl));
d7f46fc4 1655 i915_gem_object_ggtt_unpin(obj);
05394f39 1656 drm_gem_object_unreference(&obj->base);
8187a2b7 1657 ring->status_page.obj = NULL;
62fdfeaf
EA		 1658}
1659
a4872ba6 1660static int init_status_page(struct intel_engine_cs *ring)
62fdfeaf 1661{
05394f39 1662 struct drm_i915_gem_object *obj;
62fdfeaf 1663
e3efda49 1664 if ((obj = ring->status_page.obj) == NULL) {
1f767e02 1665 unsigned flags;
e3efda49 1666 int ret;
e4ffd173 1667
e3efda49
CW		 1668 obj = i915_gem_alloc_object(ring->dev, 4096);
1669 if (obj == NULL) {
1670 DRM_ERROR("Failed to allocate status page\n");
1671 return -ENOMEM;
1672 }
62fdfeaf 1673
e3efda49
CW		 1674 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1675 if (ret)
1676 goto err_unref;
1677
1f767e02
CW		 1678 flags = 0;
1679 if (!HAS_LLC(ring->dev))
1680 /* On g33, we cannot place HWS above 256MiB, so
1681 * restrict its pinning to the low mappable arena.
1682 * Though this restriction is not documented for
1683 * gen4, gen5, or byt, they also behave similarly
1684 * and hang if the HWS is placed at the top of the
1685 * GTT. To generalise, it appears that all !llc
1686 * platforms have issues with us placing the HWS
1687 * above the mappable region (even though we never
1688 * actualy map it).
1689 */
1690 flags |= PIN_MAPPABLE;
1691 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
e3efda49
CW		 1692 if (ret) {
1693err_unref:
1694 drm_gem_object_unreference(&obj->base);
1695 return ret;
1696 }
1697
1698 ring->status_page.obj = obj;
1699 }
62fdfeaf 1700
f343c5f6 1701 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
9da3da66 1702 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
8187a2b7 1703 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
62fdfeaf 1704
8187a2b7
ZN		 1705 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1706 ring->name, ring->status_page.gfx_addr);
62fdfeaf
EA		 1707
1708 return 0;
62fdfeaf
EA		 1709}
1710
a4872ba6 1711static int init_phys_status_page(struct intel_engine_cs *ring)
6b8294a4
CW		 1712{
1713 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6b8294a4
CW		 1714
1715 if (!dev_priv->status_page_dmah) {
1716 dev_priv->status_page_dmah =
1717 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1718 if (!dev_priv->status_page_dmah)
1719 return -ENOMEM;
1720 }
1721
6b8294a4
CW		 1722 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1723 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1724
1725 return 0;
1726}
1727
7ba717cf 1728void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2919d291 1729{
2919d291 1730 iounmap(ringbuf->virtual_start);
7ba717cf 1731 ringbuf->virtual_start = NULL;
2919d291 1732 i915_gem_object_ggtt_unpin(ringbuf->obj);
7ba717cf
TD		 1733}
1734
1735int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1736 struct intel_ringbuffer *ringbuf)
1737{
1738 struct drm_i915_private *dev_priv = to_i915(dev);
1739 struct drm_i915_gem_object *obj = ringbuf->obj;
1740 int ret;
1741
1742 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1743 if (ret)
1744 return ret;
1745
1746 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1747 if (ret) {
1748 i915_gem_object_ggtt_unpin(obj);
1749 return ret;
1750 }
1751
1752 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1753 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1754 if (ringbuf->virtual_start == NULL) {
1755 i915_gem_object_ggtt_unpin(obj);
1756 return -EINVAL;
1757 }
1758
1759 return 0;
1760}
1761
1762void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1763{
2919d291
OM		 1764 drm_gem_object_unreference(&ringbuf->obj->base);
1765 ringbuf->obj = NULL;
1766}
1767
84c2377f
OM		 1768int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1769 struct intel_ringbuffer *ringbuf)
62fdfeaf 1770{
05394f39 1771 struct drm_i915_gem_object *obj;
62fdfeaf 1772
ebc052e0
CW		 1773 obj = NULL;
1774 if (!HAS_LLC(dev))
93b0a4e0 1775 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
ebc052e0 1776 if (obj == NULL)
93b0a4e0 1777 obj = i915_gem_alloc_object(dev, ringbuf->size);
e3efda49
CW		 1778 if (obj == NULL)
1779 return -ENOMEM;
8187a2b7 1780
24f3a8cf
AG		 1781 /* mark ring buffers as read-only from GPU side by default */
1782 obj->gt_ro = 1;
1783
93b0a4e0 1784 ringbuf->obj = obj;
e3efda49 1785
7ba717cf 1786 return 0;
e3efda49
CW		 1787}
1788
1789static int intel_init_ring_buffer(struct drm_device *dev,
a4872ba6 1790 struct intel_engine_cs *ring)
e3efda49 1791{
8ee14975 1792 struct intel_ringbuffer *ringbuf = ring->buffer;
e3efda49
CW		 1793 int ret;
1794
8ee14975
OM		 1795 if (ringbuf == NULL) {
1796 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1797 if (!ringbuf)
1798 return -ENOMEM;
1799 ring->buffer = ringbuf;
1800 }
1801
e3efda49
CW		 1802 ring->dev = dev;
1803 INIT_LIST_HEAD(&ring->active_list);
1804 INIT_LIST_HEAD(&ring->request_list);
cc9130be 1805 INIT_LIST_HEAD(&ring->execlist_queue);
93b0a4e0 1806 ringbuf->size = 32 * PAGE_SIZE;
0c7dd53b 1807 ringbuf->ring = ring;
ebc348b2 1808 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
e3efda49
CW		 1809
1810 init_waitqueue_head(&ring->irq_queue);
1811
1812 if (I915_NEED_GFX_HWS(dev)) {
1813 ret = init_status_page(ring);
1814 if (ret)
8ee14975 1815 goto error;
e3efda49
CW		 1816 } else {
1817 BUG_ON(ring->id != RCS);
1818 ret = init_phys_status_page(ring);
1819 if (ret)
8ee14975 1820 goto error;
e3efda49
CW		 1821 }
1822
7ba717cf
TD		 1823 if (ringbuf->obj == NULL) {
1824 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1825 if (ret) {
1826 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
1827 ring->name, ret);
1828 goto error;
1829 }
1830
1831 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
1832 if (ret) {
1833 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
1834 ring->name, ret);
1835 intel_destroy_ringbuffer_obj(ringbuf);
1836 goto error;
1837 }
e3efda49 1838 }
62fdfeaf 1839
55249baa
CW		 1840 /* Workaround an erratum on the i830 which causes a hang if
1841 * the TAIL pointer points to within the last 2 cachelines
1842 * of the buffer.
1843 */
93b0a4e0 1844 ringbuf->effective_size = ringbuf->size;
e3efda49 1845 if (IS_I830(dev) || IS_845G(dev))
93b0a4e0 1846 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
55249baa 1847
44e895a8
BV		 1848 ret = i915_cmd_parser_init_ring(ring);
1849 if (ret)
8ee14975
OM		 1850 goto error;
1851
1852 ret = ring->init(ring);
1853 if (ret)
1854 goto error;
1855
1856 return 0;
351e3db2 1857
8ee14975
OM		 1858error:
1859 kfree(ringbuf);
1860 ring->buffer = NULL;
1861 return ret;
62fdfeaf
EA		 1862}
1863
a4872ba6 1864void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
62fdfeaf 1865{
6402c330
JH		 1866 struct drm_i915_private *dev_priv;
1867 struct intel_ringbuffer *ringbuf;
33626e6a 1868
93b0a4e0 1869 if (!intel_ring_initialized(ring))
62fdfeaf
EA		 1870 return;
1871
6402c330
JH		 1872 dev_priv = to_i915(ring->dev);
1873 ringbuf = ring->buffer;
1874
e3efda49 1875 intel_stop_ring_buffer(ring);
de8f0a50 1876 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
33626e6a 1877
7ba717cf 1878 intel_unpin_ringbuffer_obj(ringbuf);
2919d291 1879 intel_destroy_ringbuffer_obj(ringbuf);
3d57e5bd
BW		 1880 ring->preallocated_lazy_request = NULL;
1881 ring->outstanding_lazy_seqno = 0;
78501eac 1882
8d19215b
ZN		 1883 if (ring->cleanup)
1884 ring->cleanup(ring);
1885
78501eac 1886 cleanup_status_page(ring);
44e895a8
BV		 1887
1888 i915_cmd_parser_fini_ring(ring);
8ee14975 1889
93b0a4e0 1890 kfree(ringbuf);
8ee14975 1891 ring->buffer = NULL;
62fdfeaf
EA		 1892}
1893
a4872ba6 1894static int intel_ring_wait_request(struct intel_engine_cs *ring, int n)
a71d8d94 1895{
93b0a4e0 1896 struct intel_ringbuffer *ringbuf = ring->buffer;
a71d8d94 1897 struct drm_i915_gem_request *request;
1cf0ba14 1898 u32 seqno = 0;
a71d8d94
CW		 1899 int ret;
1900
93b0a4e0
OM		 1901 if (ringbuf->last_retired_head != -1) {
1902 ringbuf->head = ringbuf->last_retired_head;
1903 ringbuf->last_retired_head = -1;
1f70999f 1904
82e104cc 1905 ringbuf->space = intel_ring_space(ringbuf);
93b0a4e0 1906 if (ringbuf->space >= n)
a71d8d94
CW		 1907 return 0;
1908 }
1909
1910 list_for_each_entry(request, &ring->request_list, list) {
82e104cc
OM		 1911 if (__intel_ring_space(request->tail, ringbuf->tail,
1912 ringbuf->size) >= n) {
a71d8d94
CW		 1913 seqno = request->seqno;
1914 break;
1915 }
a71d8d94
CW		 1916 }
1917
1918 if (seqno == 0)
1919 return -ENOSPC;
1920
1f70999f 1921 ret = i915_wait_seqno(ring, seqno);
a71d8d94
CW		 1922 if (ret)
1923 return ret;
1924
1cf0ba14 1925 i915_gem_retire_requests_ring(ring);
93b0a4e0
OM		 1926 ringbuf->head = ringbuf->last_retired_head;
1927 ringbuf->last_retired_head = -1;
a71d8d94 1928
82e104cc 1929 ringbuf->space = intel_ring_space(ringbuf);
a71d8d94
CW		 1930 return 0;
1931}
1932
a4872ba6 1933static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
62fdfeaf 1934{
78501eac 1935 struct drm_device *dev = ring->dev;
cae5852d 1936 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0 1937 struct intel_ringbuffer *ringbuf = ring->buffer;
78501eac 1938 unsigned long end;
a71d8d94 1939 int ret;
c7dca47b 1940
a71d8d94
CW		 1941 ret = intel_ring_wait_request(ring, n);
1942 if (ret != -ENOSPC)
1943 return ret;
1944
09246732
CW		 1945 /* force the tail write in case we have been skipping them */
1946 __intel_ring_advance(ring);
1947
63ed2cb2
DV		 1948 /* With GEM the hangcheck timer should kick us out of the loop,
1949 * leaving it early runs the risk of corrupting GEM state (due
1950 * to running on almost untested codepaths). But on resume
1951 * timers don't work yet, so prevent a complete hang in that
1952 * case by choosing an insanely large timeout. */
1953 end = jiffies + 60 * HZ;
e6bfaf85 1954
dcfe0506 1955 trace_i915_ring_wait_begin(ring);
8187a2b7 1956 do {
93b0a4e0 1957 ringbuf->head = I915_READ_HEAD(ring);
82e104cc 1958 ringbuf->space = intel_ring_space(ringbuf);
93b0a4e0 1959 if (ringbuf->space >= n) {
dcfe0506
CW		 1960 ret = 0;
1961 break;
62fdfeaf
EA		 1962 }
1963
e60a0b10 1964 msleep(1);
d6b2c790 1965
dcfe0506
CW		 1966 if (dev_priv->mm.interruptible && signal_pending(current)) {
1967 ret = -ERESTARTSYS;
1968 break;
1969 }
1970
33196ded
DV		 1971 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1972 dev_priv->mm.interruptible);
d6b2c790 1973 if (ret)
dcfe0506
CW		 1974 break;
1975
1976 if (time_after(jiffies, end)) {
1977 ret = -EBUSY;
1978 break;
1979 }
1980 } while (1);
db53a302 1981 trace_i915_ring_wait_end(ring);
dcfe0506 1982 return ret;
8187a2b7 1983}
62fdfeaf 1984
a4872ba6 1985static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
3e960501
CW		 1986{
1987 uint32_t __iomem *virt;
93b0a4e0
OM		 1988 struct intel_ringbuffer *ringbuf = ring->buffer;
1989 int rem = ringbuf->size - ringbuf->tail;
3e960501 1990
93b0a4e0 1991 if (ringbuf->space < rem) {
3e960501
CW		 1992 int ret = ring_wait_for_space(ring, rem);
1993 if (ret)
1994 return ret;
1995 }
1996
93b0a4e0 1997 virt = ringbuf->virtual_start + ringbuf->tail;
3e960501
CW		 1998 rem /= 4;
1999 while (rem--)
2000 iowrite32(MI_NOOP, virt++);
2001
93b0a4e0 2002 ringbuf->tail = 0;
82e104cc 2003 ringbuf->space = intel_ring_space(ringbuf);
3e960501
CW		 2004
2005 return 0;
2006}
2007
a4872ba6 2008int intel_ring_idle(struct intel_engine_cs *ring)
3e960501
CW		 2009{
2010 u32 seqno;
2011 int ret;
2012
2013 /* We need to add any requests required to flush the objects and ring */
1823521d 2014 if (ring->outstanding_lazy_seqno) {
0025c077 2015 ret = i915_add_request(ring, NULL);
3e960501
CW		 2016 if (ret)
2017 return ret;
2018 }
2019
2020 /* Wait upon the last request to be completed */
2021 if (list_empty(&ring->request_list))
2022 return 0;
2023
2024 seqno = list_entry(ring->request_list.prev,
2025 struct drm_i915_gem_request,
2026 list)->seqno;
2027
2028 return i915_wait_seqno(ring, seqno);
2029}
2030
9d773091 2031static int
a4872ba6 2032intel_ring_alloc_seqno(struct intel_engine_cs *ring)
9d773091 2033{
1823521d 2034 if (ring->outstanding_lazy_seqno)
9d773091
CW		 2035 return 0;
2036
3c0e234c
CW		 2037 if (ring->preallocated_lazy_request == NULL) {
2038 struct drm_i915_gem_request *request;
2039
2040 request = kmalloc(sizeof(*request), GFP_KERNEL);
2041 if (request == NULL)
2042 return -ENOMEM;
2043
2044 ring->preallocated_lazy_request = request;
2045 }
2046
1823521d 2047 return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
9d773091
CW		 2048}
2049
a4872ba6 2050static int __intel_ring_prepare(struct intel_engine_cs *ring,
304d695c 2051 int bytes)
cbcc80df 2052{
93b0a4e0 2053 struct intel_ringbuffer *ringbuf = ring->buffer;
cbcc80df
MK		 2054 int ret;
2055
93b0a4e0 2056 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
cbcc80df
MK		 2057 ret = intel_wrap_ring_buffer(ring);
2058 if (unlikely(ret))
2059 return ret;
2060 }
2061
93b0a4e0 2062 if (unlikely(ringbuf->space < bytes)) {
cbcc80df
MK		 2063 ret = ring_wait_for_space(ring, bytes);
2064 if (unlikely(ret))
2065 return ret;
2066 }
2067
cbcc80df
MK		 2068 return 0;
2069}
2070
a4872ba6 2071int intel_ring_begin(struct intel_engine_cs *ring,
e1f99ce6 2072 int num_dwords)
8187a2b7 2073{
4640c4ff 2074 struct drm_i915_private *dev_priv = ring->dev->dev_private;
e1f99ce6 2075 int ret;
78501eac 2076
33196ded
DV		 2077 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2078 dev_priv->mm.interruptible);
de2b9985
DV		 2079 if (ret)
2080 return ret;
21dd3734 2081
304d695c
CW		 2082 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2083 if (ret)
2084 return ret;
2085
9d773091
CW		 2086 /* Preallocate the olr before touching the ring */
2087 ret = intel_ring_alloc_seqno(ring);
2088 if (ret)
2089 return ret;
2090
ee1b1e5e 2091 ring->buffer->space -= num_dwords * sizeof(uint32_t);
304d695c 2092 return 0;
8187a2b7 2093}
78501eac 2094
753b1ad4 2095/* Align the ring tail to a cacheline boundary */
a4872ba6 2096int intel_ring_cacheline_align(struct intel_engine_cs *ring)
753b1ad4 2097{
ee1b1e5e 2098 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
753b1ad4
VS		 2099 int ret;
2100
2101 if (num_dwords == 0)
2102 return 0;
2103
18393f63 2104 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
753b1ad4
VS		 2105 ret = intel_ring_begin(ring, num_dwords);
2106 if (ret)
2107 return ret;
2108
2109 while (num_dwords--)
2110 intel_ring_emit(ring, MI_NOOP);
2111
2112 intel_ring_advance(ring);
2113
2114 return 0;
2115}
2116
a4872ba6 2117void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
498d2ac1 2118{
3b2cc8ab
OM		 2119 struct drm_device *dev = ring->dev;
2120 struct drm_i915_private *dev_priv = dev->dev_private;
498d2ac1 2121
1823521d 2122 BUG_ON(ring->outstanding_lazy_seqno);
498d2ac1 2123
3b2cc8ab 2124 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
f7e98ad4
MK		 2125 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2126 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
3b2cc8ab 2127 if (HAS_VEBOX(dev))
5020150b 2128 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
e1f99ce6 2129 }
d97ed339 2130
f7e98ad4 2131 ring->set_seqno(ring, seqno);
92cab734 2132 ring->hangcheck.seqno = seqno;
8187a2b7 2133}
62fdfeaf 2134
a4872ba6 2135static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 2136 u32 value)
881f47b6 2137{
4640c4ff 2138 struct drm_i915_private *dev_priv = ring->dev->dev_private;
881f47b6
XH		 2139
2140 /* Every tail move must follow the sequence below */
12f55818
CW		 2141
2142 /* Disable notification that the ring is IDLE. The GT
2143 * will then assume that it is busy and bring it out of rc6.
2144 */
0206e353 2145 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818
CW		 2146 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2147
2148 /* Clear the context id. Here be magic! */
2149 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
0206e353 2150
12f55818 2151 /* Wait for the ring not to be idle, i.e. for it to wake up. */
0206e353 2152 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
12f55818
CW		 2153 GEN6_BSD_SLEEP_INDICATOR) == 0,
2154 50))
2155 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
0206e353 2156
12f55818 2157 /* Now that the ring is fully powered up, update the tail */
0206e353 2158 I915_WRITE_TAIL(ring, value);
12f55818
CW		 2159 POSTING_READ(RING_TAIL(ring->mmio_base));
2160
2161 /* Let the ring send IDLE messages to the GT again,
2162 * and so let it sleep to conserve power when idle.
2163 */
0206e353 2164 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818 2165 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
881f47b6
XH		 2166}
2167
a4872ba6 2168static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
ea251324 2169 u32 invalidate, u32 flush)
881f47b6 2170{
71a77e07 2171 uint32_t cmd;
b72f3acb
CW		 2172 int ret;
2173
b72f3acb
CW		 2174 ret = intel_ring_begin(ring, 4);
2175 if (ret)
2176 return ret;
2177
71a77e07 2178 cmd = MI_FLUSH_DW;
075b3bba
BW		 2179 if (INTEL_INFO(ring->dev)->gen >= 8)
2180 cmd += 1;
9a289771
JB		 2181 /*
2182 * Bspec vol 1c.5 - video engine command streamer:
2183 * "If ENABLED, all TLBs will be invalidated once the flush
2184 * operation is complete. This bit is only valid when the
2185 * Post-Sync Operation field is a value of 1h or 3h."
2186 */
71a77e07 2187 if (invalidate & I915_GEM_GPU_DOMAINS)
9a289771
JB		 2188 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
2189 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
71a77e07 2190 intel_ring_emit(ring, cmd);
9a289771 2191 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
075b3bba
BW		 2192 if (INTEL_INFO(ring->dev)->gen >= 8) {
2193 intel_ring_emit(ring, 0); /* upper addr */
2194 intel_ring_emit(ring, 0); /* value */
2195 } else {
2196 intel_ring_emit(ring, 0);
2197 intel_ring_emit(ring, MI_NOOP);
2198 }
b72f3acb
CW		 2199 intel_ring_advance(ring);
2200 return 0;
881f47b6
XH		 2201}
2202
1c7a0623 2203static int
a4872ba6 2204gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2205 u64 offset, u32 len,
1c7a0623
BW		 2206 unsigned flags)
2207{
896ab1a5 2208 bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE);
1c7a0623
BW		 2209 int ret;
2210
2211 ret = intel_ring_begin(ring, 4);
2212 if (ret)
2213 return ret;
2214
2215 /* FIXME(BDW): Address space and security selectors. */
28cf5415 2216 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
9bcb144c
BW		 2217 intel_ring_emit(ring, lower_32_bits(offset));
2218 intel_ring_emit(ring, upper_32_bits(offset));
1c7a0623
BW		 2219 intel_ring_emit(ring, MI_NOOP);
2220 intel_ring_advance(ring);
2221
2222 return 0;
2223}
2224
d7d4eedd 2225static int
a4872ba6 2226hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2227 u64 offset, u32 len,
d7d4eedd
CW		 2228 unsigned flags)
2229{
2230 int ret;
2231
2232 ret = intel_ring_begin(ring, 2);
2233 if (ret)
2234 return ret;
2235
2236 intel_ring_emit(ring,
77072258
CW		 2237 MI_BATCH_BUFFER_START |
2238 (flags & I915_DISPATCH_SECURE ?
2239 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
d7d4eedd
CW		 2240 /* bit0-7 is the length on GEN6+ */
2241 intel_ring_emit(ring, offset);
2242 intel_ring_advance(ring);
2243
2244 return 0;
2245}
2246
881f47b6 2247static int
a4872ba6 2248gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2249 u64 offset, u32 len,
d7d4eedd 2250 unsigned flags)
881f47b6 2251{
0206e353 2252 int ret;
ab6f8e32 2253
0206e353
AJ		 2254 ret = intel_ring_begin(ring, 2);
2255 if (ret)
2256 return ret;
e1f99ce6 2257
d7d4eedd
CW		 2258 intel_ring_emit(ring,
2259 MI_BATCH_BUFFER_START |
2260 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
0206e353
AJ		 2261 /* bit0-7 is the length on GEN6+ */
2262 intel_ring_emit(ring, offset);
2263 intel_ring_advance(ring);
ab6f8e32 2264
0206e353 2265 return 0;
881f47b6
XH		 2266}
2267
549f7365
CW		 2268/* Blitter support (SandyBridge+) */
2269
a4872ba6 2270static int gen6_ring_flush(struct intel_engine_cs *ring,
ea251324 2271 u32 invalidate, u32 flush)
8d19215b 2272{
fd3da6c9 2273 struct drm_device *dev = ring->dev;
1d73c2a8 2274 struct drm_i915_private *dev_priv = dev->dev_private;
71a77e07 2275 uint32_t cmd;
b72f3acb
CW		 2276 int ret;
2277
6a233c78 2278 ret = intel_ring_begin(ring, 4);
b72f3acb
CW		 2279 if (ret)
2280 return ret;
2281
71a77e07 2282 cmd = MI_FLUSH_DW;
075b3bba
BW		 2283 if (INTEL_INFO(ring->dev)->gen >= 8)
2284 cmd += 1;
9a289771
JB		 2285 /*
2286 * Bspec vol 1c.3 - blitter engine command streamer:
2287 * "If ENABLED, all TLBs will be invalidated once the flush
2288 * operation is complete. This bit is only valid when the
2289 * Post-Sync Operation field is a value of 1h or 3h."
2290 */
71a77e07 2291 if (invalidate & I915_GEM_DOMAIN_RENDER)
9a289771 2292 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
b3fcabb1 2293 MI_FLUSH_DW_OP_STOREDW;
71a77e07 2294 intel_ring_emit(ring, cmd);
9a289771 2295 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
075b3bba
BW		 2296 if (INTEL_INFO(ring->dev)->gen >= 8) {
2297 intel_ring_emit(ring, 0); /* upper addr */
2298 intel_ring_emit(ring, 0); /* value */
2299 } else {
2300 intel_ring_emit(ring, 0);
2301 intel_ring_emit(ring, MI_NOOP);
2302 }
b72f3acb 2303 intel_ring_advance(ring);
fd3da6c9 2304
1d73c2a8
RV		 2305 if (!invalidate && flush) {
2306 if (IS_GEN7(dev))
2307 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
2308 else if (IS_BROADWELL(dev))
2309 dev_priv->fbc.need_sw_cache_clean = true;
2310 }
fd3da6c9 2311
b72f3acb 2312 return 0;
8d19215b
ZN		 2313}
2314
5c1143bb
XH		 2315int intel_init_render_ring_buffer(struct drm_device *dev)
2316{
4640c4ff 2317 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2318 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3e78998a
BW		 2319 struct drm_i915_gem_object *obj;
2320 int ret;
5c1143bb 2321
59465b5f
DV		 2322 ring->name = "render ring";
2323 ring->id = RCS;
2324 ring->mmio_base = RENDER_RING_BASE;
2325
707d9cf9 2326 if (INTEL_INFO(dev)->gen >= 8) {
3e78998a
BW		 2327 if (i915_semaphore_is_enabled(dev)) {
2328 obj = i915_gem_alloc_object(dev, 4096);
2329 if (obj == NULL) {
2330 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2331 i915.semaphores = 0;
2332 } else {
2333 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2334 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2335 if (ret != 0) {
2336 drm_gem_object_unreference(&obj->base);
2337 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2338 i915.semaphores = 0;
2339 } else
2340 dev_priv->semaphore_obj = obj;
2341 }
2342 }
7225342a
MK		 2343
2344 ring->init_context = intel_ring_workarounds_emit;
707d9cf9
BW		 2345 ring->add_request = gen6_add_request;
2346 ring->flush = gen8_render_ring_flush;
2347 ring->irq_get = gen8_ring_get_irq;
2348 ring->irq_put = gen8_ring_put_irq;
2349 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2350 ring->get_seqno = gen6_ring_get_seqno;
2351 ring->set_seqno = ring_set_seqno;
2352 if (i915_semaphore_is_enabled(dev)) {
3e78998a 2353 WARN_ON(!dev_priv->semaphore_obj);
5ee426ca 2354 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2355 ring->semaphore.signal = gen8_rcs_signal;
2356 GEN8_RING_SEMAPHORE_INIT;
707d9cf9
BW		 2357 }
2358 } else if (INTEL_INFO(dev)->gen >= 6) {
1ec14ad3 2359 ring->add_request = gen6_add_request;
4772eaeb 2360 ring->flush = gen7_render_ring_flush;
6c6cf5aa 2361 if (INTEL_INFO(dev)->gen == 6)
b3111509 2362 ring->flush = gen6_render_ring_flush;
707d9cf9
BW		 2363 ring->irq_get = gen6_ring_get_irq;
2364 ring->irq_put = gen6_ring_put_irq;
cc609d5d 2365 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
4cd53c0c 2366 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2367 ring->set_seqno = ring_set_seqno;
707d9cf9
BW		 2368 if (i915_semaphore_is_enabled(dev)) {
2369 ring->semaphore.sync_to = gen6_ring_sync;
2370 ring->semaphore.signal = gen6_signal;
2371 /*
2372 * The current semaphore is only applied on pre-gen8
2373 * platform. And there is no VCS2 ring on the pre-gen8
2374 * platform. So the semaphore between RCS and VCS2 is
2375 * initialized as INVALID. Gen8 will initialize the
2376 * sema between VCS2 and RCS later.
2377 */
2378 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2379 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2380 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2381 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2382 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2383 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2384 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2385 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2386 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2387 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2388 }
c6df541c
CW		 2389 } else if (IS_GEN5(dev)) {
2390 ring->add_request = pc_render_add_request;
46f0f8d1 2391 ring->flush = gen4_render_ring_flush;
c6df541c 2392 ring->get_seqno = pc_render_get_seqno;
b70ec5bf 2393 ring->set_seqno = pc_render_set_seqno;
e48d8634
DV		 2394 ring->irq_get = gen5_ring_get_irq;
2395 ring->irq_put = gen5_ring_put_irq;
cc609d5d
BW		 2396 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2397 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
59465b5f 2398 } else {
8620a3a9 2399 ring->add_request = i9xx_add_request;
46f0f8d1
CW		 2400 if (INTEL_INFO(dev)->gen < 4)
2401 ring->flush = gen2_render_ring_flush;
2402 else
2403 ring->flush = gen4_render_ring_flush;
59465b5f 2404 ring->get_seqno = ring_get_seqno;
b70ec5bf 2405 ring->set_seqno = ring_set_seqno;
c2798b19
CW		 2406 if (IS_GEN2(dev)) {
2407 ring->irq_get = i8xx_ring_get_irq;
2408 ring->irq_put = i8xx_ring_put_irq;
2409 } else {
2410 ring->irq_get = i9xx_ring_get_irq;
2411 ring->irq_put = i9xx_ring_put_irq;
2412 }
e3670319 2413 ring->irq_enable_mask = I915_USER_INTERRUPT;
1ec14ad3 2414 }
59465b5f 2415 ring->write_tail = ring_write_tail;
707d9cf9 2416
d7d4eedd
CW		 2417 if (IS_HASWELL(dev))
2418 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1c7a0623
BW		 2419 else if (IS_GEN8(dev))
2420 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
d7d4eedd 2421 else if (INTEL_INFO(dev)->gen >= 6)
fb3256da
DV		 2422 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2423 else if (INTEL_INFO(dev)->gen >= 4)
2424 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2425 else if (IS_I830(dev) || IS_845G(dev))
2426 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2427 else
2428 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
59465b5f
DV		 2429 ring->init = init_render_ring;
2430 ring->cleanup = render_ring_cleanup;
2431
b45305fc
DV		 2432 /* Workaround batchbuffer to combat CS tlb bug. */
2433 if (HAS_BROKEN_CS_TLB(dev)) {
c4d69da1 2434 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
b45305fc
DV		 2435 if (obj == NULL) {
2436 DRM_ERROR("Failed to allocate batch bo\n");
2437 return -ENOMEM;
2438 }
2439
be1fa129 2440 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
b45305fc
DV		 2441 if (ret != 0) {
2442 drm_gem_object_unreference(&obj->base);
2443 DRM_ERROR("Failed to ping batch bo\n");
2444 return ret;
2445 }
2446
0d1aacac
CW		 2447 ring->scratch.obj = obj;
2448 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
b45305fc
DV		 2449 }
2450
1ec14ad3 2451 return intel_init_ring_buffer(dev, ring);
5c1143bb
XH		 2452}
2453
2454int intel_init_bsd_ring_buffer(struct drm_device *dev)
2455{
4640c4ff 2456 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2457 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
5c1143bb 2458
58fa3835
DV		 2459 ring->name = "bsd ring";
2460 ring->id = VCS;
2461
0fd2c201 2462 ring->write_tail = ring_write_tail;
780f18c8 2463 if (INTEL_INFO(dev)->gen >= 6) {
58fa3835 2464 ring->mmio_base = GEN6_BSD_RING_BASE;
0fd2c201
DV		 2465 /* gen6 bsd needs a special wa for tail updates */
2466 if (IS_GEN6(dev))
2467 ring->write_tail = gen6_bsd_ring_write_tail;
ea251324 2468 ring->flush = gen6_bsd_ring_flush;
58fa3835
DV		 2469 ring->add_request = gen6_add_request;
2470 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2471 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2472 if (INTEL_INFO(dev)->gen >= 8) {
2473 ring->irq_enable_mask =
2474 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2475 ring->irq_get = gen8_ring_get_irq;
2476 ring->irq_put = gen8_ring_put_irq;
1c7a0623
BW		 2477 ring->dispatch_execbuffer =
2478 gen8_ring_dispatch_execbuffer;
707d9cf9 2479 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2480 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2481 ring->semaphore.signal = gen8_xcs_signal;
2482 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2483 }
abd58f01
BW		 2484 } else {
2485 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2486 ring->irq_get = gen6_ring_get_irq;
2487 ring->irq_put = gen6_ring_put_irq;
1c7a0623
BW		 2488 ring->dispatch_execbuffer =
2489 gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2490 if (i915_semaphore_is_enabled(dev)) {
2491 ring->semaphore.sync_to = gen6_ring_sync;
2492 ring->semaphore.signal = gen6_signal;
2493 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2494 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2495 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2496 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2497 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2498 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2499 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2500 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2501 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2502 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2503 }
abd58f01 2504 }
58fa3835
DV		 2505 } else {
2506 ring->mmio_base = BSD_RING_BASE;
58fa3835 2507 ring->flush = bsd_ring_flush;
8620a3a9 2508 ring->add_request = i9xx_add_request;
58fa3835 2509 ring->get_seqno = ring_get_seqno;
b70ec5bf 2510 ring->set_seqno = ring_set_seqno;
e48d8634 2511 if (IS_GEN5(dev)) {
cc609d5d 2512 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
e48d8634
DV		 2513 ring->irq_get = gen5_ring_get_irq;
2514 ring->irq_put = gen5_ring_put_irq;
2515 } else {
e3670319 2516 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
e48d8634
DV		 2517 ring->irq_get = i9xx_ring_get_irq;
2518 ring->irq_put = i9xx_ring_put_irq;
2519 }
fb3256da 2520 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
58fa3835
DV		 2521 }
2522 ring->init = init_ring_common;
2523
1ec14ad3 2524 return intel_init_ring_buffer(dev, ring);
5c1143bb 2525}
549f7365 2526
845f74a7
ZY		 2527/**
2528 * Initialize the second BSD ring for Broadwell GT3.
2529 * It is noted that this only exists on Broadwell GT3.
2530 */
2531int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2532{
2533 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2534 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
845f74a7
ZY		 2535
2536 if ((INTEL_INFO(dev)->gen != 8)) {
2537 DRM_ERROR("No dual-BSD ring on non-BDW machine\n");
2538 return -EINVAL;
2539 }
2540
f7b64236 2541 ring->name = "bsd2 ring";
845f74a7
ZY		 2542 ring->id = VCS2;
2543
2544 ring->write_tail = ring_write_tail;
2545 ring->mmio_base = GEN8_BSD2_RING_BASE;
2546 ring->flush = gen6_bsd_ring_flush;
2547 ring->add_request = gen6_add_request;
2548 ring->get_seqno = gen6_ring_get_seqno;
2549 ring->set_seqno = ring_set_seqno;
2550 ring->irq_enable_mask =
2551 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2552 ring->irq_get = gen8_ring_get_irq;
2553 ring->irq_put = gen8_ring_put_irq;
2554 ring->dispatch_execbuffer =
2555 gen8_ring_dispatch_execbuffer;
3e78998a 2556 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2557 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2558 ring->semaphore.signal = gen8_xcs_signal;
2559 GEN8_RING_SEMAPHORE_INIT;
2560 }
845f74a7
ZY		 2561 ring->init = init_ring_common;
2562
2563 return intel_init_ring_buffer(dev, ring);
2564}
2565
549f7365
CW		 2566int intel_init_blt_ring_buffer(struct drm_device *dev)
2567{
4640c4ff 2568 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2569 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
549f7365 2570
3535d9dd
DV		 2571 ring->name = "blitter ring";
2572 ring->id = BCS;
2573
2574 ring->mmio_base = BLT_RING_BASE;
2575 ring->write_tail = ring_write_tail;
ea251324 2576 ring->flush = gen6_ring_flush;
3535d9dd
DV		 2577 ring->add_request = gen6_add_request;
2578 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2579 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2580 if (INTEL_INFO(dev)->gen >= 8) {
2581 ring->irq_enable_mask =
2582 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2583 ring->irq_get = gen8_ring_get_irq;
2584 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2585 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2586 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2587 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2588 ring->semaphore.signal = gen8_xcs_signal;
2589 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2590 }
abd58f01
BW		 2591 } else {
2592 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2593 ring->irq_get = gen6_ring_get_irq;
2594 ring->irq_put = gen6_ring_put_irq;
1c7a0623 2595 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2596 if (i915_semaphore_is_enabled(dev)) {
2597 ring->semaphore.signal = gen6_signal;
2598 ring->semaphore.sync_to = gen6_ring_sync;
2599 /*
2600 * The current semaphore is only applied on pre-gen8
2601 * platform. And there is no VCS2 ring on the pre-gen8
2602 * platform. So the semaphore between BCS and VCS2 is
2603 * initialized as INVALID. Gen8 will initialize the
2604 * sema between BCS and VCS2 later.
2605 */
2606 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2607 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2608 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2609 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2610 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2611 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2612 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2613 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2614 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2615 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2616 }
abd58f01 2617 }
3535d9dd 2618 ring->init = init_ring_common;
549f7365 2619
1ec14ad3 2620 return intel_init_ring_buffer(dev, ring);
549f7365 2621}
a7b9761d 2622
9a8a2213
BW		 2623int intel_init_vebox_ring_buffer(struct drm_device *dev)
2624{
4640c4ff 2625 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2626 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
9a8a2213
BW		 2627
2628 ring->name = "video enhancement ring";
2629 ring->id = VECS;
2630
2631 ring->mmio_base = VEBOX_RING_BASE;
2632 ring->write_tail = ring_write_tail;
2633 ring->flush = gen6_ring_flush;
2634 ring->add_request = gen6_add_request;
2635 ring->get_seqno = gen6_ring_get_seqno;
2636 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2637
2638 if (INTEL_INFO(dev)->gen >= 8) {
2639 ring->irq_enable_mask =
40c499f9 2640 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
abd58f01
BW		 2641 ring->irq_get = gen8_ring_get_irq;
2642 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2643 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2644 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2645 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2646 ring->semaphore.signal = gen8_xcs_signal;
2647 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2648 }
abd58f01
BW		 2649 } else {
2650 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2651 ring->irq_get = hsw_vebox_get_irq;
2652 ring->irq_put = hsw_vebox_put_irq;
1c7a0623 2653 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2654 if (i915_semaphore_is_enabled(dev)) {
2655 ring->semaphore.sync_to = gen6_ring_sync;
2656 ring->semaphore.signal = gen6_signal;
2657 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2658 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2659 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2660 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2661 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2662 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2663 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2664 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2665 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2666 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2667 }
abd58f01 2668 }
9a8a2213
BW		 2669 ring->init = init_ring_common;
2670
2671 return intel_init_ring_buffer(dev, ring);
2672}
2673
a7b9761d 2674int
a4872ba6 2675intel_ring_flush_all_caches(struct intel_engine_cs *ring)
a7b9761d
CW		 2676{
2677 int ret;
2678
2679 if (!ring->gpu_caches_dirty)
2680 return 0;
2681
2682 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2683 if (ret)
2684 return ret;
2685
2686 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2687
2688 ring->gpu_caches_dirty = false;
2689 return 0;
2690}
2691
2692int
a4872ba6 2693intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
a7b9761d
CW		 2694{
2695 uint32_t flush_domains;
2696 int ret;
2697
2698 flush_domains = 0;
2699 if (ring->gpu_caches_dirty)
2700 flush_domains = I915_GEM_GPU_DOMAINS;
2701
2702 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2703 if (ret)
2704 return ret;
2705
2706 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2707
2708 ring->gpu_caches_dirty = false;
2709 return 0;
2710}
e3efda49
CW		 2711
2712void
a4872ba6 2713intel_stop_ring_buffer(struct intel_engine_cs *ring)
e3efda49
CW		 2714{
2715 int ret;
2716
2717 if (!intel_ring_initialized(ring))
2718 return;
2719
2720 ret = intel_ring_idle(ring);
2721 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2722 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2723 ring->name, ret);
2724
2725 stop_ring(ring);
2726}
Linux 6.x block layer and io_uring tree(s)