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drm/i915: Prevent a machine hang by checking crtc->active before loading lut
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
CommitLineData
62fdfeaf
EA		 1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30#include "drmP.h"
31#include "drm.h"
62fdfeaf 32#include "i915_drv.h"
8187a2b7 33#include "i915_drm.h"
62fdfeaf 34#include "i915_trace.h"
881f47b6 35#include "intel_drv.h"
62fdfeaf 36
8d315287
JB		 37/*
38 * 965+ support PIPE_CONTROL commands, which provide finer grained control
39 * over cache flushing.
40 */
41struct pipe_control {
42 struct drm_i915_gem_object *obj;
43 volatile u32 *cpu_page;
44 u32 gtt_offset;
45};
46
c7dca47b
CW		 47static inline int ring_space(struct intel_ring_buffer *ring)
48{
49 int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
50 if (space < 0)
51 space += ring->size;
52 return space;
53}
54
6f392d54
CW		 55static u32 i915_gem_get_seqno(struct drm_device *dev)
56{
57 drm_i915_private_t *dev_priv = dev->dev_private;
58 u32 seqno;
59
60 seqno = dev_priv->next_seqno;
61
62 /* reserve 0 for non-seqno */
63 if (++dev_priv->next_seqno == 0)
64 dev_priv->next_seqno = 1;
65
66 return seqno;
67}
68
b72f3acb 69static int
78501eac 70render_ring_flush(struct intel_ring_buffer *ring,
ab6f8e32
CW		 71 u32 invalidate_domains,
72 u32 flush_domains)
62fdfeaf 73{
78501eac 74 struct drm_device *dev = ring->dev;
6f392d54 75 u32 cmd;
b72f3acb 76 int ret;
6f392d54 77
36d527de
CW		 78 /*
79 * read/write caches:
80 *
81 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
82 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
83 * also flushed at 2d versus 3d pipeline switches.
84 *
85 * read-only caches:
86 *
87 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
88 * MI_READ_FLUSH is set, and is always flushed on 965.
89 *
90 * I915_GEM_DOMAIN_COMMAND may not exist?
91 *
92 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
93 * invalidated when MI_EXE_FLUSH is set.
94 *
95 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
96 * invalidated with every MI_FLUSH.
97 *
98 * TLBs:
99 *
100 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
101 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
102 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
103 * are flushed at any MI_FLUSH.
104 */
105
106 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
107 if ((invalidate_domains|flush_domains) &
108 I915_GEM_DOMAIN_RENDER)
109 cmd &= ~MI_NO_WRITE_FLUSH;
110 if (INTEL_INFO(dev)->gen < 4) {
62fdfeaf 111 /*
36d527de
CW		 112 * On the 965, the sampler cache always gets flushed
113 * and this bit is reserved.
62fdfeaf 114 */
36d527de
CW		 115 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
116 cmd |= MI_READ_FLUSH;
117 }
118 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
119 cmd |= MI_EXE_FLUSH;
62fdfeaf 120
36d527de
CW		 121 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
122 (IS_G4X(dev) || IS_GEN5(dev)))
123 cmd |= MI_INVALIDATE_ISP;
70eac33e 124
36d527de
CW		 125 ret = intel_ring_begin(ring, 2);
126 if (ret)
127 return ret;
b72f3acb 128
36d527de
CW		 129 intel_ring_emit(ring, cmd);
130 intel_ring_emit(ring, MI_NOOP);
131 intel_ring_advance(ring);
b72f3acb
CW		 132
133 return 0;
8187a2b7
ZN		 134}
135
8d315287
JB		 136/**
137 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
138 * implementing two workarounds on gen6. From section 1.4.7.1
139 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
140 *
141 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
142 * produced by non-pipelined state commands), software needs to first
143 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
144 * 0.
145 *
146 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
147 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
148 *
149 * And the workaround for these two requires this workaround first:
150 *
151 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
152 * BEFORE the pipe-control with a post-sync op and no write-cache
153 * flushes.
154 *
155 * And this last workaround is tricky because of the requirements on
156 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
157 * volume 2 part 1:
158 *
159 * "1 of the following must also be set:
160 * - Render Target Cache Flush Enable ([12] of DW1)
161 * - Depth Cache Flush Enable ([0] of DW1)
162 * - Stall at Pixel Scoreboard ([1] of DW1)
163 * - Depth Stall ([13] of DW1)
164 * - Post-Sync Operation ([13] of DW1)
165 * - Notify Enable ([8] of DW1)"
166 *
167 * The cache flushes require the workaround flush that triggered this
168 * one, so we can't use it. Depth stall would trigger the same.
169 * Post-sync nonzero is what triggered this second workaround, so we
170 * can't use that one either. Notify enable is IRQs, which aren't
171 * really our business. That leaves only stall at scoreboard.
172 */
173static int
174intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
175{
176 struct pipe_control *pc = ring->private;
177 u32 scratch_addr = pc->gtt_offset + 128;
178 int ret;
179
180
181 ret = intel_ring_begin(ring, 6);
182 if (ret)
183 return ret;
184
185 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
186 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
187 PIPE_CONTROL_STALL_AT_SCOREBOARD);
188 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
189 intel_ring_emit(ring, 0); /* low dword */
190 intel_ring_emit(ring, 0); /* high dword */
191 intel_ring_emit(ring, MI_NOOP);
192 intel_ring_advance(ring);
193
194 ret = intel_ring_begin(ring, 6);
195 if (ret)
196 return ret;
197
198 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
199 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
200 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
201 intel_ring_emit(ring, 0);
202 intel_ring_emit(ring, 0);
203 intel_ring_emit(ring, MI_NOOP);
204 intel_ring_advance(ring);
205
206 return 0;
207}
208
209static int
210gen6_render_ring_flush(struct intel_ring_buffer *ring,
211 u32 invalidate_domains, u32 flush_domains)
212{
213 u32 flags = 0;
214 struct pipe_control *pc = ring->private;
215 u32 scratch_addr = pc->gtt_offset + 128;
216 int ret;
217
218 /* Force SNB workarounds for PIPE_CONTROL flushes */
219 intel_emit_post_sync_nonzero_flush(ring);
220
221 /* Just flush everything. Experiments have shown that reducing the
222 * number of bits based on the write domains has little performance
223 * impact.
224 */
225 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
226 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
227 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
228 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
229 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
230 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
231 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
232
233 ret = intel_ring_begin(ring, 6);
234 if (ret)
235 return ret;
236
237 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
238 intel_ring_emit(ring, flags);
239 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
240 intel_ring_emit(ring, 0); /* lower dword */
241 intel_ring_emit(ring, 0); /* uppwer dword */
242 intel_ring_emit(ring, MI_NOOP);
243 intel_ring_advance(ring);
244
245 return 0;
246}
247
78501eac 248static void ring_write_tail(struct intel_ring_buffer *ring,
297b0c5b 249 u32 value)
d46eefa2 250{
78501eac 251 drm_i915_private_t *dev_priv = ring->dev->dev_private;
297b0c5b 252 I915_WRITE_TAIL(ring, value);
d46eefa2
XH		 253}
254
78501eac 255u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
8187a2b7 256{
78501eac
CW		 257 drm_i915_private_t *dev_priv = ring->dev->dev_private;
258 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
3d281d8c 259 RING_ACTHD(ring->mmio_base) : ACTHD;
8187a2b7
ZN		 260
261 return I915_READ(acthd_reg);
262}
263
78501eac 264static int init_ring_common(struct intel_ring_buffer *ring)
8187a2b7 265{
78501eac 266 drm_i915_private_t *dev_priv = ring->dev->dev_private;
05394f39 267 struct drm_i915_gem_object *obj = ring->obj;
8187a2b7 268 u32 head;
8187a2b7
ZN		 269
270 /* Stop the ring if it's running. */
7f2ab699 271 I915_WRITE_CTL(ring, 0);
570ef608 272 I915_WRITE_HEAD(ring, 0);
78501eac 273 ring->write_tail(ring, 0);
8187a2b7
ZN		 274
275 /* Initialize the ring. */
05394f39 276 I915_WRITE_START(ring, obj->gtt_offset);
570ef608 277 head = I915_READ_HEAD(ring) & HEAD_ADDR;
8187a2b7
ZN		 278
279 /* G45 ring initialization fails to reset head to zero */
280 if (head != 0) {
6fd0d56e
CW		 281 DRM_DEBUG_KMS("%s head not reset to zero "
282 "ctl %08x head %08x tail %08x start %08x\n",
283 ring->name,
284 I915_READ_CTL(ring),
285 I915_READ_HEAD(ring),
286 I915_READ_TAIL(ring),
287 I915_READ_START(ring));
8187a2b7 288
570ef608 289 I915_WRITE_HEAD(ring, 0);
8187a2b7 290
6fd0d56e
CW		 291 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
292 DRM_ERROR("failed to set %s head to zero "
293 "ctl %08x head %08x tail %08x start %08x\n",
294 ring->name,
295 I915_READ_CTL(ring),
296 I915_READ_HEAD(ring),
297 I915_READ_TAIL(ring),
298 I915_READ_START(ring));
299 }
8187a2b7
ZN		 300 }
301
7f2ab699 302 I915_WRITE_CTL(ring,
ae69b42a 303 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
6aa56062 304 | RING_REPORT_64K | RING_VALID);
8187a2b7 305
8187a2b7 306 /* If the head is still not zero, the ring is dead */
176f28eb 307 if ((I915_READ_CTL(ring) & RING_VALID) == 0 ||
05394f39 308 I915_READ_START(ring) != obj->gtt_offset ||
176f28eb 309 (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {
e74cfed5
CW		 310 DRM_ERROR("%s initialization failed "
311 "ctl %08x head %08x tail %08x start %08x\n",
312 ring->name,
313 I915_READ_CTL(ring),
314 I915_READ_HEAD(ring),
315 I915_READ_TAIL(ring),
316 I915_READ_START(ring));
317 return -EIO;
8187a2b7
ZN		 318 }
319
78501eac
CW		 320 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
321 i915_kernel_lost_context(ring->dev);
8187a2b7 322 else {
c7dca47b 323 ring->head = I915_READ_HEAD(ring);
870e86dd 324 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
c7dca47b 325 ring->space = ring_space(ring);
8187a2b7 326 }
1ec14ad3 327
8187a2b7
ZN		 328 return 0;
329}
330
c6df541c
CW		 331static int
332init_pipe_control(struct intel_ring_buffer *ring)
333{
334 struct pipe_control *pc;
335 struct drm_i915_gem_object *obj;
336 int ret;
337
338 if (ring->private)
339 return 0;
340
341 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
342 if (!pc)
343 return -ENOMEM;
344
345 obj = i915_gem_alloc_object(ring->dev, 4096);
346 if (obj == NULL) {
347 DRM_ERROR("Failed to allocate seqno page\n");
348 ret = -ENOMEM;
349 goto err;
350 }
e4ffd173
CW		 351
352 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
c6df541c
CW		 353
354 ret = i915_gem_object_pin(obj, 4096, true);
355 if (ret)
356 goto err_unref;
357
358 pc->gtt_offset = obj->gtt_offset;
359 pc->cpu_page = kmap(obj->pages[0]);
360 if (pc->cpu_page == NULL)
361 goto err_unpin;
362
363 pc->obj = obj;
364 ring->private = pc;
365 return 0;
366
367err_unpin:
368 i915_gem_object_unpin(obj);
369err_unref:
370 drm_gem_object_unreference(&obj->base);
371err:
372 kfree(pc);
373 return ret;
374}
375
376static void
377cleanup_pipe_control(struct intel_ring_buffer *ring)
378{
379 struct pipe_control *pc = ring->private;
380 struct drm_i915_gem_object *obj;
381
382 if (!ring->private)
383 return;
384
385 obj = pc->obj;
386 kunmap(obj->pages[0]);
387 i915_gem_object_unpin(obj);
388 drm_gem_object_unreference(&obj->base);
389
390 kfree(pc);
391 ring->private = NULL;
392}
393
78501eac 394static int init_render_ring(struct intel_ring_buffer *ring)
8187a2b7 395{
78501eac 396 struct drm_device *dev = ring->dev;
1ec14ad3 397 struct drm_i915_private *dev_priv = dev->dev_private;
78501eac 398 int ret = init_ring_common(ring);
a69ffdbf 399
a6c45cf0 400 if (INTEL_INFO(dev)->gen > 3) {
78501eac 401 int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
65d3eb1e 402 if (IS_GEN6(dev) || IS_GEN7(dev))
a69ffdbf
ZW		 403 mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
404 I915_WRITE(MI_MODE, mode);
b095cd0a
JB		 405 if (IS_GEN7(dev))
406 I915_WRITE(GFX_MODE_GEN7,
407 GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
408 GFX_MODE_ENABLE(GFX_REPLAY_MODE));
8187a2b7 409 }
78501eac 410
8d315287 411 if (INTEL_INFO(dev)->gen >= 5) {
c6df541c
CW		 412 ret = init_pipe_control(ring);
413 if (ret)
414 return ret;
415 }
416
84f9f938
BW		 417 if (INTEL_INFO(dev)->gen >= 6) {
418 I915_WRITE(INSTPM,
419 INSTPM_FORCE_ORDERING << 16 | INSTPM_FORCE_ORDERING);
420 }
421
8187a2b7
ZN		 422 return ret;
423}
424
c6df541c
CW		 425static void render_ring_cleanup(struct intel_ring_buffer *ring)
426{
427 if (!ring->private)
428 return;
429
430 cleanup_pipe_control(ring);
431}
432
1ec14ad3 433static void
c8c99b0f
BW		 434update_mboxes(struct intel_ring_buffer *ring,
435 u32 seqno,
436 u32 mmio_offset)
1ec14ad3 437{
c8c99b0f
BW		 438 intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
439 MI_SEMAPHORE_GLOBAL_GTT |
440 MI_SEMAPHORE_REGISTER |
441 MI_SEMAPHORE_UPDATE);
1ec14ad3 442 intel_ring_emit(ring, seqno);
c8c99b0f 443 intel_ring_emit(ring, mmio_offset);
1ec14ad3
CW		 444}
445
c8c99b0f
BW		 446/**
447 * gen6_add_request - Update the semaphore mailbox registers
448 *
449 * @ring - ring that is adding a request
450 * @seqno - return seqno stuck into the ring
451 *
452 * Update the mailbox registers in the *other* rings with the current seqno.
453 * This acts like a signal in the canonical semaphore.
454 */
1ec14ad3
CW		 455static int
456gen6_add_request(struct intel_ring_buffer *ring,
c8c99b0f 457 u32 *seqno)
1ec14ad3 458{
c8c99b0f
BW		 459 u32 mbox1_reg;
460 u32 mbox2_reg;
1ec14ad3
CW		 461 int ret;
462
463 ret = intel_ring_begin(ring, 10);
464 if (ret)
465 return ret;
466
c8c99b0f
BW		 467 mbox1_reg = ring->signal_mbox[0];
468 mbox2_reg = ring->signal_mbox[1];
1ec14ad3 469
c8c99b0f
BW		 470 *seqno = i915_gem_get_seqno(ring->dev);
471
472 update_mboxes(ring, *seqno, mbox1_reg);
473 update_mboxes(ring, *seqno, mbox2_reg);
1ec14ad3
CW		 474 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
475 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
c8c99b0f 476 intel_ring_emit(ring, *seqno);
1ec14ad3
CW		 477 intel_ring_emit(ring, MI_USER_INTERRUPT);
478 intel_ring_advance(ring);
479
1ec14ad3
CW		 480 return 0;
481}
482
c8c99b0f
BW		 483/**
484 * intel_ring_sync - sync the waiter to the signaller on seqno
485 *
486 * @waiter - ring that is waiting
487 * @signaller - ring which has, or will signal
488 * @seqno - seqno which the waiter will block on
489 */
490static int
491intel_ring_sync(struct intel_ring_buffer *waiter,
492 struct intel_ring_buffer *signaller,
493 int ring,
1ec14ad3
CW		 494 u32 seqno)
495{
496 int ret;
c8c99b0f
BW		 497 u32 dw1 = MI_SEMAPHORE_MBOX |
498 MI_SEMAPHORE_COMPARE |
499 MI_SEMAPHORE_REGISTER;
1ec14ad3 500
c8c99b0f 501 ret = intel_ring_begin(waiter, 4);
1ec14ad3
CW		 502 if (ret)
503 return ret;
504
c8c99b0f
BW		 505 intel_ring_emit(waiter, dw1 | signaller->semaphore_register[ring]);
506 intel_ring_emit(waiter, seqno);
507 intel_ring_emit(waiter, 0);
508 intel_ring_emit(waiter, MI_NOOP);
509 intel_ring_advance(waiter);
1ec14ad3
CW		 510
511 return 0;
512}
513
c8c99b0f
BW		 514/* VCS->RCS (RVSYNC) or BCS->RCS (RBSYNC) */
515int
516render_ring_sync_to(struct intel_ring_buffer *waiter,
517 struct intel_ring_buffer *signaller,
518 u32 seqno)
519{
520 WARN_ON(signaller->semaphore_register[RCS] == MI_SEMAPHORE_SYNC_INVALID);
521 return intel_ring_sync(waiter,
522 signaller,
523 RCS,
524 seqno);
525}
526
527/* RCS->VCS (VRSYNC) or BCS->VCS (VBSYNC) */
528int
529gen6_bsd_ring_sync_to(struct intel_ring_buffer *waiter,
530 struct intel_ring_buffer *signaller,
531 u32 seqno)
532{
533 WARN_ON(signaller->semaphore_register[VCS] == MI_SEMAPHORE_SYNC_INVALID);
534 return intel_ring_sync(waiter,
535 signaller,
536 VCS,
537 seqno);
538}
539
540/* RCS->BCS (BRSYNC) or VCS->BCS (BVSYNC) */
541int
542gen6_blt_ring_sync_to(struct intel_ring_buffer *waiter,
543 struct intel_ring_buffer *signaller,
544 u32 seqno)
545{
546 WARN_ON(signaller->semaphore_register[BCS] == MI_SEMAPHORE_SYNC_INVALID);
547 return intel_ring_sync(waiter,
548 signaller,
549 BCS,
550 seqno);
551}
552
553
554
c6df541c
CW		 555#define PIPE_CONTROL_FLUSH(ring__, addr__) \
556do { \
fcbc34e4
KG		 557 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
558 PIPE_CONTROL_DEPTH_STALL); \
c6df541c
CW		 559 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
560 intel_ring_emit(ring__, 0); \
561 intel_ring_emit(ring__, 0); \
562} while (0)
563
564static int
565pc_render_add_request(struct intel_ring_buffer *ring,
566 u32 *result)
567{
568 struct drm_device *dev = ring->dev;
569 u32 seqno = i915_gem_get_seqno(dev);
570 struct pipe_control *pc = ring->private;
571 u32 scratch_addr = pc->gtt_offset + 128;
572 int ret;
573
574 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
575 * incoherent with writes to memory, i.e. completely fubar,
576 * so we need to use PIPE_NOTIFY instead.
577 *
578 * However, we also need to workaround the qword write
579 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
580 * memory before requesting an interrupt.
581 */
582 ret = intel_ring_begin(ring, 32);
583 if (ret)
584 return ret;
585
fcbc34e4 586 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 587 PIPE_CONTROL_WRITE_FLUSH |
588 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
c6df541c
CW		 589 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
590 intel_ring_emit(ring, seqno);
591 intel_ring_emit(ring, 0);
592 PIPE_CONTROL_FLUSH(ring, scratch_addr);
593 scratch_addr += 128; /* write to separate cachelines */
594 PIPE_CONTROL_FLUSH(ring, scratch_addr);
595 scratch_addr += 128;
596 PIPE_CONTROL_FLUSH(ring, scratch_addr);
597 scratch_addr += 128;
598 PIPE_CONTROL_FLUSH(ring, scratch_addr);
599 scratch_addr += 128;
600 PIPE_CONTROL_FLUSH(ring, scratch_addr);
601 scratch_addr += 128;
602 PIPE_CONTROL_FLUSH(ring, scratch_addr);
fcbc34e4 603 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 604 PIPE_CONTROL_WRITE_FLUSH |
605 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
c6df541c
CW		 606 PIPE_CONTROL_NOTIFY);
607 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
608 intel_ring_emit(ring, seqno);
609 intel_ring_emit(ring, 0);
610 intel_ring_advance(ring);
611
612 *result = seqno;
613 return 0;
614}
615
1ec14ad3
CW		 616static int
617render_ring_add_request(struct intel_ring_buffer *ring,
618 u32 *result)
619{
620 struct drm_device *dev = ring->dev;
621 u32 seqno = i915_gem_get_seqno(dev);
622 int ret;
3cce469c 623
1ec14ad3
CW		 624 ret = intel_ring_begin(ring, 4);
625 if (ret)
626 return ret;
3cce469c 627
1ec14ad3
CW		 628 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
629 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
630 intel_ring_emit(ring, seqno);
631 intel_ring_emit(ring, MI_USER_INTERRUPT);
3cce469c 632 intel_ring_advance(ring);
1ec14ad3 633
3cce469c
CW		 634 *result = seqno;
635 return 0;
62fdfeaf
EA		 636}
637
4cd53c0c
DV		 638static u32
639gen6_ring_get_seqno(struct intel_ring_buffer *ring)
640{
641 struct drm_device *dev = ring->dev;
642
643 /* Workaround to force correct ordering between irq and seqno writes on
644 * ivb (and maybe also on snb) by reading from a CS register (like
645 * ACTHD) before reading the status page. */
646 if (IS_GEN7(dev))
647 intel_ring_get_active_head(ring);
648 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
649}
650
8187a2b7 651static u32
1ec14ad3 652ring_get_seqno(struct intel_ring_buffer *ring)
8187a2b7 653{
1ec14ad3
CW		 654 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
655}
656
c6df541c
CW		 657static u32
658pc_render_get_seqno(struct intel_ring_buffer *ring)
659{
660 struct pipe_control *pc = ring->private;
661 return pc->cpu_page[0];
662}
663
0f46832f
CW		 664static void
665ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
666{
667 dev_priv->gt_irq_mask &= ~mask;
668 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
669 POSTING_READ(GTIMR);
670}
671
672static void
673ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
674{
675 dev_priv->gt_irq_mask |= mask;
676 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
677 POSTING_READ(GTIMR);
678}
679
680static void
681i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
682{
683 dev_priv->irq_mask &= ~mask;
684 I915_WRITE(IMR, dev_priv->irq_mask);
685 POSTING_READ(IMR);
686}
687
688static void
689i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
690{
691 dev_priv->irq_mask |= mask;
692 I915_WRITE(IMR, dev_priv->irq_mask);
693 POSTING_READ(IMR);
694}
695
b13c2b96 696static bool
1ec14ad3 697render_ring_get_irq(struct intel_ring_buffer *ring)
62fdfeaf 698{
78501eac 699 struct drm_device *dev = ring->dev;
01a03331 700 drm_i915_private_t *dev_priv = dev->dev_private;
62fdfeaf 701
b13c2b96
CW		 702 if (!dev->irq_enabled)
703 return false;
704
0dc79fb2 705 spin_lock(&ring->irq_lock);
01a03331 706 if (ring->irq_refcount++ == 0) {
62fdfeaf 707 if (HAS_PCH_SPLIT(dev))
0f46832f
CW		 708 ironlake_enable_irq(dev_priv,
709 GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
62fdfeaf
EA		 710 else
711 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
712 }
0dc79fb2 713 spin_unlock(&ring->irq_lock);
b13c2b96
CW		 714
715 return true;
62fdfeaf
EA		 716}
717
8187a2b7 718static void
1ec14ad3 719render_ring_put_irq(struct intel_ring_buffer *ring)
62fdfeaf 720{
78501eac 721 struct drm_device *dev = ring->dev;
01a03331 722 drm_i915_private_t *dev_priv = dev->dev_private;
62fdfeaf 723
0dc79fb2 724 spin_lock(&ring->irq_lock);
01a03331 725 if (--ring->irq_refcount == 0) {
62fdfeaf 726 if (HAS_PCH_SPLIT(dev))
0f46832f
CW		 727 ironlake_disable_irq(dev_priv,
728 GT_USER_INTERRUPT |
729 GT_PIPE_NOTIFY);
62fdfeaf
EA		 730 else
731 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
732 }
0dc79fb2 733 spin_unlock(&ring->irq_lock);
62fdfeaf
EA		 734}
735
78501eac 736void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
8187a2b7 737{
4593010b 738 struct drm_device *dev = ring->dev;
78501eac 739 drm_i915_private_t *dev_priv = ring->dev->dev_private;
4593010b
EA		 740 u32 mmio = 0;
741
742 /* The ring status page addresses are no longer next to the rest of
743 * the ring registers as of gen7.
744 */
745 if (IS_GEN7(dev)) {
746 switch (ring->id) {
747 case RING_RENDER:
748 mmio = RENDER_HWS_PGA_GEN7;
749 break;
750 case RING_BLT:
751 mmio = BLT_HWS_PGA_GEN7;
752 break;
753 case RING_BSD:
754 mmio = BSD_HWS_PGA_GEN7;
755 break;
756 }
757 } else if (IS_GEN6(ring->dev)) {
758 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
759 } else {
760 mmio = RING_HWS_PGA(ring->mmio_base);
761 }
762
78501eac
CW		 763 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
764 POSTING_READ(mmio);
8187a2b7
ZN		 765}
766
b72f3acb 767static int
78501eac
CW		 768bsd_ring_flush(struct intel_ring_buffer *ring,
769 u32 invalidate_domains,
770 u32 flush_domains)
d1b851fc 771{
b72f3acb
CW		 772 int ret;
773
b72f3acb
CW		 774 ret = intel_ring_begin(ring, 2);
775 if (ret)
776 return ret;
777
778 intel_ring_emit(ring, MI_FLUSH);
779 intel_ring_emit(ring, MI_NOOP);
780 intel_ring_advance(ring);
781 return 0;
d1b851fc
ZN		 782}
783
3cce469c 784static int
78501eac 785ring_add_request(struct intel_ring_buffer *ring,
3cce469c 786 u32 *result)
d1b851fc
ZN		 787{
788 u32 seqno;
3cce469c
CW		 789 int ret;
790
791 ret = intel_ring_begin(ring, 4);
792 if (ret)
793 return ret;
6f392d54 794
78501eac 795 seqno = i915_gem_get_seqno(ring->dev);
6f392d54 796
3cce469c
CW		 797 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
798 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
799 intel_ring_emit(ring, seqno);
800 intel_ring_emit(ring, MI_USER_INTERRUPT);
801 intel_ring_advance(ring);
d1b851fc 802
3cce469c
CW		 803 *result = seqno;
804 return 0;
d1b851fc
ZN		 805}
806
0f46832f
CW		 807static bool
808gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
809{
810 struct drm_device *dev = ring->dev;
01a03331 811 drm_i915_private_t *dev_priv = dev->dev_private;
0f46832f
CW		 812
813 if (!dev->irq_enabled)
814 return false;
815
4cd53c0c
DV		 816 /* It looks like we need to prevent the gt from suspending while waiting
817 * for an notifiy irq, otherwise irqs seem to get lost on at least the
818 * blt/bsd rings on ivb. */
819 if (IS_GEN7(dev))
820 gen6_gt_force_wake_get(dev_priv);
821
0dc79fb2 822 spin_lock(&ring->irq_lock);
01a03331 823 if (ring->irq_refcount++ == 0) {
0f46832f
CW		 824 ring->irq_mask &= ~rflag;
825 I915_WRITE_IMR(ring, ring->irq_mask);
826 ironlake_enable_irq(dev_priv, gflag);
0f46832f 827 }
0dc79fb2 828 spin_unlock(&ring->irq_lock);
0f46832f
CW		 829
830 return true;
831}
832
833static void
834gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
835{
836 struct drm_device *dev = ring->dev;
01a03331 837 drm_i915_private_t *dev_priv = dev->dev_private;
0f46832f 838
0dc79fb2 839 spin_lock(&ring->irq_lock);
01a03331 840 if (--ring->irq_refcount == 0) {
0f46832f
CW		 841 ring->irq_mask |= rflag;
842 I915_WRITE_IMR(ring, ring->irq_mask);
843 ironlake_disable_irq(dev_priv, gflag);
1ec14ad3 844 }
0dc79fb2 845 spin_unlock(&ring->irq_lock);
4cd53c0c
DV		 846
847 if (IS_GEN7(dev))
848 gen6_gt_force_wake_put(dev_priv);
d1b851fc
ZN		 849}
850
b13c2b96 851static bool
1ec14ad3 852bsd_ring_get_irq(struct intel_ring_buffer *ring)
d1b851fc 853{
5bfa1063
FB		 854 struct drm_device *dev = ring->dev;
855 drm_i915_private_t *dev_priv = dev->dev_private;
856
857 if (!dev->irq_enabled)
858 return false;
859
860 spin_lock(&ring->irq_lock);
861 if (ring->irq_refcount++ == 0) {
862 if (IS_G4X(dev))
863 i915_enable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
864 else
865 ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
866 }
867 spin_unlock(&ring->irq_lock);
868
869 return true;
1ec14ad3
CW		 870}
871static void
872bsd_ring_put_irq(struct intel_ring_buffer *ring)
873{
5bfa1063
FB		 874 struct drm_device *dev = ring->dev;
875 drm_i915_private_t *dev_priv = dev->dev_private;
876
877 spin_lock(&ring->irq_lock);
878 if (--ring->irq_refcount == 0) {
879 if (IS_G4X(dev))
880 i915_disable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
881 else
882 ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
883 }
884 spin_unlock(&ring->irq_lock);
d1b851fc
ZN		 885}
886
887static int
c4e7a414 888ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
d1b851fc 889{
e1f99ce6 890 int ret;
78501eac 891
e1f99ce6
CW		 892 ret = intel_ring_begin(ring, 2);
893 if (ret)
894 return ret;
895
78501eac 896 intel_ring_emit(ring,
c4e7a414 897 MI_BATCH_BUFFER_START | (2 << 6) |
78501eac 898 MI_BATCH_NON_SECURE_I965);
c4e7a414 899 intel_ring_emit(ring, offset);
78501eac
CW		 900 intel_ring_advance(ring);
901
d1b851fc
ZN		 902 return 0;
903}
904
8187a2b7 905static int
78501eac 906render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
c4e7a414 907 u32 offset, u32 len)
62fdfeaf 908{
78501eac 909 struct drm_device *dev = ring->dev;
c4e7a414 910 int ret;
62fdfeaf 911
c4e7a414
CW		 912 if (IS_I830(dev) || IS_845G(dev)) {
913 ret = intel_ring_begin(ring, 4);
914 if (ret)
915 return ret;
62fdfeaf 916
c4e7a414
CW		 917 intel_ring_emit(ring, MI_BATCH_BUFFER);
918 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
919 intel_ring_emit(ring, offset + len - 8);
920 intel_ring_emit(ring, 0);
921 } else {
922 ret = intel_ring_begin(ring, 2);
923 if (ret)
924 return ret;
e1f99ce6 925
c4e7a414
CW		 926 if (INTEL_INFO(dev)->gen >= 4) {
927 intel_ring_emit(ring,
928 MI_BATCH_BUFFER_START | (2 << 6) |
929 MI_BATCH_NON_SECURE_I965);
930 intel_ring_emit(ring, offset);
62fdfeaf 931 } else {
c4e7a414
CW		 932 intel_ring_emit(ring,
933 MI_BATCH_BUFFER_START | (2 << 6));
934 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
62fdfeaf
EA		 935 }
936 }
c4e7a414 937 intel_ring_advance(ring);
62fdfeaf 938
62fdfeaf
EA		 939 return 0;
940}
941
78501eac 942static void cleanup_status_page(struct intel_ring_buffer *ring)
62fdfeaf 943{
78501eac 944 drm_i915_private_t *dev_priv = ring->dev->dev_private;
05394f39 945 struct drm_i915_gem_object *obj;
62fdfeaf 946
8187a2b7
ZN		 947 obj = ring->status_page.obj;
948 if (obj == NULL)
62fdfeaf 949 return;
62fdfeaf 950
05394f39 951 kunmap(obj->pages[0]);
62fdfeaf 952 i915_gem_object_unpin(obj);
05394f39 953 drm_gem_object_unreference(&obj->base);
8187a2b7 954 ring->status_page.obj = NULL;
62fdfeaf
EA		 955
956 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
62fdfeaf
EA		 957}
958
78501eac 959static int init_status_page(struct intel_ring_buffer *ring)
62fdfeaf 960{
78501eac 961 struct drm_device *dev = ring->dev;
62fdfeaf 962 drm_i915_private_t *dev_priv = dev->dev_private;
05394f39 963 struct drm_i915_gem_object *obj;
62fdfeaf
EA		 964 int ret;
965
62fdfeaf
EA		 966 obj = i915_gem_alloc_object(dev, 4096);
967 if (obj == NULL) {
968 DRM_ERROR("Failed to allocate status page\n");
969 ret = -ENOMEM;
970 goto err;
971 }
e4ffd173
CW		 972
973 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
62fdfeaf 974
75e9e915 975 ret = i915_gem_object_pin(obj, 4096, true);
62fdfeaf 976 if (ret != 0) {
62fdfeaf
EA		 977 goto err_unref;
978 }
979
05394f39
CW		 980 ring->status_page.gfx_addr = obj->gtt_offset;
981 ring->status_page.page_addr = kmap(obj->pages[0]);
8187a2b7 982 if (ring->status_page.page_addr == NULL) {
62fdfeaf 983 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
62fdfeaf
EA		 984 goto err_unpin;
985 }
8187a2b7
ZN		 986 ring->status_page.obj = obj;
987 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
62fdfeaf 988
78501eac 989 intel_ring_setup_status_page(ring);
8187a2b7
ZN		 990 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
991 ring->name, ring->status_page.gfx_addr);
62fdfeaf
EA		 992
993 return 0;
994
995err_unpin:
996 i915_gem_object_unpin(obj);
997err_unref:
05394f39 998 drm_gem_object_unreference(&obj->base);
62fdfeaf 999err:
8187a2b7 1000 return ret;
62fdfeaf
EA		 1001}
1002
8187a2b7 1003int intel_init_ring_buffer(struct drm_device *dev,
ab6f8e32 1004 struct intel_ring_buffer *ring)
62fdfeaf 1005{
05394f39 1006 struct drm_i915_gem_object *obj;
dd785e35
CW		 1007 int ret;
1008
8187a2b7 1009 ring->dev = dev;
23bc5982
CW		 1010 INIT_LIST_HEAD(&ring->active_list);
1011 INIT_LIST_HEAD(&ring->request_list);
64193406 1012 INIT_LIST_HEAD(&ring->gpu_write_list);
0dc79fb2 1013
b259f673 1014 init_waitqueue_head(&ring->irq_queue);
0dc79fb2 1015 spin_lock_init(&ring->irq_lock);
0f46832f 1016 ring->irq_mask = ~0;
62fdfeaf 1017
8187a2b7 1018 if (I915_NEED_GFX_HWS(dev)) {
78501eac 1019 ret = init_status_page(ring);
8187a2b7
ZN		 1020 if (ret)
1021 return ret;
1022 }
62fdfeaf 1023
8187a2b7 1024 obj = i915_gem_alloc_object(dev, ring->size);
62fdfeaf
EA		 1025 if (obj == NULL) {
1026 DRM_ERROR("Failed to allocate ringbuffer\n");
8187a2b7 1027 ret = -ENOMEM;
dd785e35 1028 goto err_hws;
62fdfeaf 1029 }
62fdfeaf 1030
05394f39 1031 ring->obj = obj;
8187a2b7 1032
75e9e915 1033 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
dd785e35
CW		 1034 if (ret)
1035 goto err_unref;
62fdfeaf 1036
8187a2b7 1037 ring->map.size = ring->size;
05394f39 1038 ring->map.offset = dev->agp->base + obj->gtt_offset;
62fdfeaf
EA		 1039 ring->map.type = 0;
1040 ring->map.flags = 0;
1041 ring->map.mtrr = 0;
1042
1043 drm_core_ioremap_wc(&ring->map, dev);
1044 if (ring->map.handle == NULL) {
1045 DRM_ERROR("Failed to map ringbuffer.\n");
8187a2b7 1046 ret = -EINVAL;
dd785e35 1047 goto err_unpin;
62fdfeaf
EA		 1048 }
1049
8187a2b7 1050 ring->virtual_start = ring->map.handle;
78501eac 1051 ret = ring->init(ring);
dd785e35
CW		 1052 if (ret)
1053 goto err_unmap;
62fdfeaf 1054
55249baa
CW		 1055 /* Workaround an erratum on the i830 which causes a hang if
1056 * the TAIL pointer points to within the last 2 cachelines
1057 * of the buffer.
1058 */
1059 ring->effective_size = ring->size;
1060 if (IS_I830(ring->dev))
1061 ring->effective_size -= 128;
1062
c584fe47 1063 return 0;
dd785e35
CW		 1064
1065err_unmap:
1066 drm_core_ioremapfree(&ring->map, dev);
1067err_unpin:
1068 i915_gem_object_unpin(obj);
1069err_unref:
05394f39
CW		 1070 drm_gem_object_unreference(&obj->base);
1071 ring->obj = NULL;
dd785e35 1072err_hws:
78501eac 1073 cleanup_status_page(ring);
8187a2b7 1074 return ret;
62fdfeaf
EA		 1075}
1076
78501eac 1077void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
62fdfeaf 1078{
33626e6a
CW		 1079 struct drm_i915_private *dev_priv;
1080 int ret;
1081
05394f39 1082 if (ring->obj == NULL)
62fdfeaf
EA		 1083 return;
1084
33626e6a
CW		 1085 /* Disable the ring buffer. The ring must be idle at this point */
1086 dev_priv = ring->dev->dev_private;
96f298aa 1087 ret = intel_wait_ring_idle(ring);
29ee3991
CW		 1088 if (ret)
1089 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1090 ring->name, ret);
1091
33626e6a
CW		 1092 I915_WRITE_CTL(ring, 0);
1093
78501eac 1094 drm_core_ioremapfree(&ring->map, ring->dev);
62fdfeaf 1095
05394f39
CW		 1096 i915_gem_object_unpin(ring->obj);
1097 drm_gem_object_unreference(&ring->obj->base);
1098 ring->obj = NULL;
78501eac 1099
8d19215b
ZN		 1100 if (ring->cleanup)
1101 ring->cleanup(ring);
1102
78501eac 1103 cleanup_status_page(ring);
62fdfeaf
EA		 1104}
1105
78501eac 1106static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
62fdfeaf 1107{
8187a2b7 1108 unsigned int *virt;
55249baa 1109 int rem = ring->size - ring->tail;
62fdfeaf 1110
8187a2b7 1111 if (ring->space < rem) {
78501eac 1112 int ret = intel_wait_ring_buffer(ring, rem);
62fdfeaf
EA		 1113 if (ret)
1114 return ret;
1115 }
62fdfeaf 1116
8187a2b7 1117 virt = (unsigned int *)(ring->virtual_start + ring->tail);
1741dd4a
CW		 1118 rem /= 8;
1119 while (rem--) {
62fdfeaf 1120 *virt++ = MI_NOOP;
1741dd4a
CW		 1121 *virt++ = MI_NOOP;
1122 }
62fdfeaf 1123
8187a2b7 1124 ring->tail = 0;
c7dca47b 1125 ring->space = ring_space(ring);
62fdfeaf
EA		 1126
1127 return 0;
1128}
1129
78501eac 1130int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
62fdfeaf 1131{
78501eac 1132 struct drm_device *dev = ring->dev;
cae5852d 1133 struct drm_i915_private *dev_priv = dev->dev_private;
78501eac 1134 unsigned long end;
6aa56062
CW		 1135 u32 head;
1136
c7dca47b
CW		 1137 /* If the reported head position has wrapped or hasn't advanced,
1138 * fallback to the slow and accurate path.
1139 */
1140 head = intel_read_status_page(ring, 4);
1141 if (head > ring->head) {
1142 ring->head = head;
1143 ring->space = ring_space(ring);
1144 if (ring->space >= n)
1145 return 0;
1146 }
1147
db53a302 1148 trace_i915_ring_wait_begin(ring);
e6bfaf85
DV		 1149 if (drm_core_check_feature(dev, DRIVER_GEM))
1150 /* With GEM the hangcheck timer should kick us out of the loop,
1151 * leaving it early runs the risk of corrupting GEM state (due
1152 * to running on almost untested codepaths). But on resume
1153 * timers don't work yet, so prevent a complete hang in that
1154 * case by choosing an insanely large timeout. */
1155 end = jiffies + 60 * HZ;
1156 else
1157 end = jiffies + 3 * HZ;
1158
8187a2b7 1159 do {
c7dca47b
CW		 1160 ring->head = I915_READ_HEAD(ring);
1161 ring->space = ring_space(ring);
62fdfeaf 1162 if (ring->space >= n) {
db53a302 1163 trace_i915_ring_wait_end(ring);
62fdfeaf
EA		 1164 return 0;
1165 }
1166
1167 if (dev->primary->master) {
1168 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1169 if (master_priv->sarea_priv)
1170 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1171 }
d1b851fc 1172
e60a0b10 1173 msleep(1);
f4e0b29b
CW		 1174 if (atomic_read(&dev_priv->mm.wedged))
1175 return -EAGAIN;
8187a2b7 1176 } while (!time_after(jiffies, end));
db53a302 1177 trace_i915_ring_wait_end(ring);
8187a2b7
ZN		 1178 return -EBUSY;
1179}
62fdfeaf 1180
e1f99ce6
CW		 1181int intel_ring_begin(struct intel_ring_buffer *ring,
1182 int num_dwords)
8187a2b7 1183{
21dd3734 1184 struct drm_i915_private *dev_priv = ring->dev->dev_private;
be26a10b 1185 int n = 4*num_dwords;
e1f99ce6 1186 int ret;
78501eac 1187
21dd3734
CW		 1188 if (unlikely(atomic_read(&dev_priv->mm.wedged)))
1189 return -EIO;
1190
55249baa 1191 if (unlikely(ring->tail + n > ring->effective_size)) {
e1f99ce6
CW		 1192 ret = intel_wrap_ring_buffer(ring);
1193 if (unlikely(ret))
1194 return ret;
1195 }
78501eac 1196
e1f99ce6
CW		 1197 if (unlikely(ring->space < n)) {
1198 ret = intel_wait_ring_buffer(ring, n);
1199 if (unlikely(ret))
1200 return ret;
1201 }
d97ed339
CW		 1202
1203 ring->space -= n;
e1f99ce6 1204 return 0;
8187a2b7 1205}
62fdfeaf 1206
78501eac 1207void intel_ring_advance(struct intel_ring_buffer *ring)
8187a2b7 1208{
d97ed339 1209 ring->tail &= ring->size - 1;
78501eac 1210 ring->write_tail(ring, ring->tail);
8187a2b7 1211}
62fdfeaf 1212
e070868e 1213static const struct intel_ring_buffer render_ring = {
8187a2b7 1214 .name = "render ring",
9220434a 1215 .id = RING_RENDER,
333e9fe9 1216 .mmio_base = RENDER_RING_BASE,
8187a2b7 1217 .size = 32 * PAGE_SIZE,
8187a2b7 1218 .init = init_render_ring,
297b0c5b 1219 .write_tail = ring_write_tail,
8187a2b7
ZN		 1220 .flush = render_ring_flush,
1221 .add_request = render_ring_add_request,
1ec14ad3
CW		 1222 .get_seqno = ring_get_seqno,
1223 .irq_get = render_ring_get_irq,
1224 .irq_put = render_ring_put_irq,
78501eac 1225 .dispatch_execbuffer = render_ring_dispatch_execbuffer,
0206e353 1226 .cleanup = render_ring_cleanup,
c8c99b0f
BW		 1227 .sync_to = render_ring_sync_to,
1228 .semaphore_register = {MI_SEMAPHORE_SYNC_INVALID,
1229 MI_SEMAPHORE_SYNC_RV,
1230 MI_SEMAPHORE_SYNC_RB},
1231 .signal_mbox = {GEN6_VRSYNC, GEN6_BRSYNC},
8187a2b7 1232};
d1b851fc
ZN		 1233
1234/* ring buffer for bit-stream decoder */
1235
e070868e 1236static const struct intel_ring_buffer bsd_ring = {
d1b851fc 1237 .name = "bsd ring",
9220434a 1238 .id = RING_BSD,
333e9fe9 1239 .mmio_base = BSD_RING_BASE,
d1b851fc 1240 .size = 32 * PAGE_SIZE,
78501eac 1241 .init = init_ring_common,
297b0c5b 1242 .write_tail = ring_write_tail,
d1b851fc 1243 .flush = bsd_ring_flush,
549f7365 1244 .add_request = ring_add_request,
1ec14ad3
CW		 1245 .get_seqno = ring_get_seqno,
1246 .irq_get = bsd_ring_get_irq,
1247 .irq_put = bsd_ring_put_irq,
78501eac 1248 .dispatch_execbuffer = ring_dispatch_execbuffer,
d1b851fc 1249};
5c1143bb 1250
881f47b6 1251
78501eac 1252static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
297b0c5b 1253 u32 value)
881f47b6 1254{
0206e353 1255 drm_i915_private_t *dev_priv = ring->dev->dev_private;
881f47b6
XH		 1256
1257 /* Every tail move must follow the sequence below */
0206e353
AJ		 1258 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1259 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1260 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
1261 I915_WRITE(GEN6_BSD_RNCID, 0x0);
1262
1263 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1264 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
1265 50))
1266 DRM_ERROR("timed out waiting for IDLE Indicator\n");
1267
1268 I915_WRITE_TAIL(ring, value);
1269 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1270 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1271 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
881f47b6
XH		 1272}
1273
b72f3acb 1274static int gen6_ring_flush(struct intel_ring_buffer *ring,
71a77e07 1275 u32 invalidate, u32 flush)
881f47b6 1276{
71a77e07 1277 uint32_t cmd;
b72f3acb
CW		 1278 int ret;
1279
b72f3acb
CW		 1280 ret = intel_ring_begin(ring, 4);
1281 if (ret)
1282 return ret;
1283
71a77e07
CW		 1284 cmd = MI_FLUSH_DW;
1285 if (invalidate & I915_GEM_GPU_DOMAINS)
1286 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1287 intel_ring_emit(ring, cmd);
b72f3acb
CW		 1288 intel_ring_emit(ring, 0);
1289 intel_ring_emit(ring, 0);
71a77e07 1290 intel_ring_emit(ring, MI_NOOP);
b72f3acb
CW		 1291 intel_ring_advance(ring);
1292 return 0;
881f47b6
XH		 1293}
1294
1295static int
78501eac 1296gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
c4e7a414 1297 u32 offset, u32 len)
881f47b6 1298{
0206e353 1299 int ret;
ab6f8e32 1300
0206e353
AJ		 1301 ret = intel_ring_begin(ring, 2);
1302 if (ret)
1303 return ret;
e1f99ce6 1304
0206e353
AJ		 1305 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1306 /* bit0-7 is the length on GEN6+ */
1307 intel_ring_emit(ring, offset);
1308 intel_ring_advance(ring);
ab6f8e32 1309
0206e353 1310 return 0;
881f47b6
XH		 1311}
1312
0f46832f
CW		 1313static bool
1314gen6_render_ring_get_irq(struct intel_ring_buffer *ring)
1315{
1316 return gen6_ring_get_irq(ring,
1317 GT_USER_INTERRUPT,
1318 GEN6_RENDER_USER_INTERRUPT);
1319}
1320
1321static void
1322gen6_render_ring_put_irq(struct intel_ring_buffer *ring)
1323{
1324 return gen6_ring_put_irq(ring,
1325 GT_USER_INTERRUPT,
1326 GEN6_RENDER_USER_INTERRUPT);
1327}
1328
b13c2b96 1329static bool
1ec14ad3
CW		 1330gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
1331{
0f46832f
CW		 1332 return gen6_ring_get_irq(ring,
1333 GT_GEN6_BSD_USER_INTERRUPT,
1334 GEN6_BSD_USER_INTERRUPT);
1ec14ad3
CW		 1335}
1336
1337static void
1338gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
1339{
0f46832f
CW		 1340 return gen6_ring_put_irq(ring,
1341 GT_GEN6_BSD_USER_INTERRUPT,
1342 GEN6_BSD_USER_INTERRUPT);
1ec14ad3
CW		 1343}
1344
881f47b6 1345/* ring buffer for Video Codec for Gen6+ */
e070868e 1346static const struct intel_ring_buffer gen6_bsd_ring = {
1ec14ad3
CW		 1347 .name = "gen6 bsd ring",
1348 .id = RING_BSD,
1349 .mmio_base = GEN6_BSD_RING_BASE,
1350 .size = 32 * PAGE_SIZE,
1351 .init = init_ring_common,
1352 .write_tail = gen6_bsd_ring_write_tail,
1353 .flush = gen6_ring_flush,
1354 .add_request = gen6_add_request,
4cd53c0c 1355 .get_seqno = gen6_ring_get_seqno,
1ec14ad3
CW		 1356 .irq_get = gen6_bsd_ring_get_irq,
1357 .irq_put = gen6_bsd_ring_put_irq,
1358 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
c8c99b0f
BW		 1359 .sync_to = gen6_bsd_ring_sync_to,
1360 .semaphore_register = {MI_SEMAPHORE_SYNC_VR,
1361 MI_SEMAPHORE_SYNC_INVALID,
1362 MI_SEMAPHORE_SYNC_VB},
1363 .signal_mbox = {GEN6_RVSYNC, GEN6_BVSYNC},
549f7365
CW		 1364};
1365
1366/* Blitter support (SandyBridge+) */
1367
b13c2b96 1368static bool
1ec14ad3 1369blt_ring_get_irq(struct intel_ring_buffer *ring)
549f7365 1370{
0f46832f
CW		 1371 return gen6_ring_get_irq(ring,
1372 GT_BLT_USER_INTERRUPT,
1373 GEN6_BLITTER_USER_INTERRUPT);
549f7365 1374}
1ec14ad3 1375
549f7365 1376static void
1ec14ad3 1377blt_ring_put_irq(struct intel_ring_buffer *ring)
549f7365 1378{
0f46832f
CW		 1379 gen6_ring_put_irq(ring,
1380 GT_BLT_USER_INTERRUPT,
1381 GEN6_BLITTER_USER_INTERRUPT);
549f7365
CW		 1382}
1383
8d19215b
ZN		 1384
1385/* Workaround for some stepping of SNB,
1386 * each time when BLT engine ring tail moved,
1387 * the first command in the ring to be parsed
1388 * should be MI_BATCH_BUFFER_START
1389 */
1390#define NEED_BLT_WORKAROUND(dev) \
1391 (IS_GEN6(dev) && (dev->pdev->revision < 8))
1392
1393static inline struct drm_i915_gem_object *
1394to_blt_workaround(struct intel_ring_buffer *ring)
1395{
1396 return ring->private;
1397}
1398
1399static int blt_ring_init(struct intel_ring_buffer *ring)
1400{
1401 if (NEED_BLT_WORKAROUND(ring->dev)) {
1402 struct drm_i915_gem_object *obj;
27153f72 1403 u32 *ptr;
8d19215b
ZN		 1404 int ret;
1405
05394f39 1406 obj = i915_gem_alloc_object(ring->dev, 4096);
8d19215b
ZN		 1407 if (obj == NULL)
1408 return -ENOMEM;
1409
05394f39 1410 ret = i915_gem_object_pin(obj, 4096, true);
8d19215b
ZN		 1411 if (ret) {
1412 drm_gem_object_unreference(&obj->base);
1413 return ret;
1414 }
1415
1416 ptr = kmap(obj->pages[0]);
27153f72
CW		 1417 *ptr++ = MI_BATCH_BUFFER_END;
1418 *ptr++ = MI_NOOP;
8d19215b
ZN		 1419 kunmap(obj->pages[0]);
1420
05394f39 1421 ret = i915_gem_object_set_to_gtt_domain(obj, false);
8d19215b 1422 if (ret) {
05394f39 1423 i915_gem_object_unpin(obj);
8d19215b
ZN		 1424 drm_gem_object_unreference(&obj->base);
1425 return ret;
1426 }
1427
1428 ring->private = obj;
1429 }
1430
1431 return init_ring_common(ring);
1432}
1433
1434static int blt_ring_begin(struct intel_ring_buffer *ring,
1435 int num_dwords)
1436{
1437 if (ring->private) {
1438 int ret = intel_ring_begin(ring, num_dwords+2);
1439 if (ret)
1440 return ret;
1441
1442 intel_ring_emit(ring, MI_BATCH_BUFFER_START);
1443 intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset);
1444
1445 return 0;
1446 } else
1447 return intel_ring_begin(ring, 4);
1448}
1449
b72f3acb 1450static int blt_ring_flush(struct intel_ring_buffer *ring,
71a77e07 1451 u32 invalidate, u32 flush)
8d19215b 1452{
71a77e07 1453 uint32_t cmd;
b72f3acb
CW		 1454 int ret;
1455
b72f3acb
CW		 1456 ret = blt_ring_begin(ring, 4);
1457 if (ret)
1458 return ret;
1459
71a77e07
CW		 1460 cmd = MI_FLUSH_DW;
1461 if (invalidate & I915_GEM_DOMAIN_RENDER)
1462 cmd |= MI_INVALIDATE_TLB;
1463 intel_ring_emit(ring, cmd);
b72f3acb
CW		 1464 intel_ring_emit(ring, 0);
1465 intel_ring_emit(ring, 0);
71a77e07 1466 intel_ring_emit(ring, MI_NOOP);
b72f3acb
CW		 1467 intel_ring_advance(ring);
1468 return 0;
8d19215b
ZN		 1469}
1470
8d19215b
ZN		 1471static void blt_ring_cleanup(struct intel_ring_buffer *ring)
1472{
1473 if (!ring->private)
1474 return;
1475
1476 i915_gem_object_unpin(ring->private);
1477 drm_gem_object_unreference(ring->private);
1478 ring->private = NULL;
1479}
1480
549f7365 1481static const struct intel_ring_buffer gen6_blt_ring = {
0206e353
AJ		 1482 .name = "blt ring",
1483 .id = RING_BLT,
1484 .mmio_base = BLT_RING_BASE,
1485 .size = 32 * PAGE_SIZE,
1486 .init = blt_ring_init,
1487 .write_tail = ring_write_tail,
1488 .flush = blt_ring_flush,
1489 .add_request = gen6_add_request,
4cd53c0c 1490 .get_seqno = gen6_ring_get_seqno,
c8c99b0f
BW		 1491 .irq_get = blt_ring_get_irq,
1492 .irq_put = blt_ring_put_irq,
0206e353 1493 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
c8c99b0f
BW		 1494 .cleanup = blt_ring_cleanup,
1495 .sync_to = gen6_blt_ring_sync_to,
1496 .semaphore_register = {MI_SEMAPHORE_SYNC_BR,
1497 MI_SEMAPHORE_SYNC_BV,
1498 MI_SEMAPHORE_SYNC_INVALID},
1499 .signal_mbox = {GEN6_RBSYNC, GEN6_VBSYNC},
881f47b6
XH		 1500};
1501
5c1143bb
XH		 1502int intel_init_render_ring_buffer(struct drm_device *dev)
1503{
1504 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3 1505 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5c1143bb 1506
1ec14ad3
CW		 1507 *ring = render_ring;
1508 if (INTEL_INFO(dev)->gen >= 6) {
1509 ring->add_request = gen6_add_request;
8d315287 1510 ring->flush = gen6_render_ring_flush;
0f46832f
CW		 1511 ring->irq_get = gen6_render_ring_get_irq;
1512 ring->irq_put = gen6_render_ring_put_irq;
4cd53c0c 1513 ring->get_seqno = gen6_ring_get_seqno;
c6df541c
CW		 1514 } else if (IS_GEN5(dev)) {
1515 ring->add_request = pc_render_add_request;
1516 ring->get_seqno = pc_render_get_seqno;
1ec14ad3 1517 }
5c1143bb
XH		 1518
1519 if (!I915_NEED_GFX_HWS(dev)) {
1ec14ad3
CW		 1520 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1521 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
5c1143bb
XH		 1522 }
1523
1ec14ad3 1524 return intel_init_ring_buffer(dev, ring);
5c1143bb
XH		 1525}
1526
e8616b6c
CW		 1527int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1528{
1529 drm_i915_private_t *dev_priv = dev->dev_private;
1530 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1531
1532 *ring = render_ring;
1533 if (INTEL_INFO(dev)->gen >= 6) {
1534 ring->add_request = gen6_add_request;
1535 ring->irq_get = gen6_render_ring_get_irq;
1536 ring->irq_put = gen6_render_ring_put_irq;
1537 } else if (IS_GEN5(dev)) {
1538 ring->add_request = pc_render_add_request;
1539 ring->get_seqno = pc_render_get_seqno;
1540 }
1541
f3234706
KP		 1542 if (!I915_NEED_GFX_HWS(dev))
1543 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1544
e8616b6c
CW		 1545 ring->dev = dev;
1546 INIT_LIST_HEAD(&ring->active_list);
1547 INIT_LIST_HEAD(&ring->request_list);
1548 INIT_LIST_HEAD(&ring->gpu_write_list);
1549
1550 ring->size = size;
1551 ring->effective_size = ring->size;
1552 if (IS_I830(ring->dev))
1553 ring->effective_size -= 128;
1554
1555 ring->map.offset = start;
1556 ring->map.size = size;
1557 ring->map.type = 0;
1558 ring->map.flags = 0;
1559 ring->map.mtrr = 0;
1560
1561 drm_core_ioremap_wc(&ring->map, dev);
1562 if (ring->map.handle == NULL) {
1563 DRM_ERROR("can not ioremap virtual address for"
1564 " ring buffer\n");
1565 return -ENOMEM;
1566 }
1567
1568 ring->virtual_start = (void __force __iomem *)ring->map.handle;
1569 return 0;
1570}
1571
5c1143bb
XH		 1572int intel_init_bsd_ring_buffer(struct drm_device *dev)
1573{
1574 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3 1575 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
5c1143bb 1576
65d3eb1e 1577 if (IS_GEN6(dev) || IS_GEN7(dev))
1ec14ad3 1578 *ring = gen6_bsd_ring;
881f47b6 1579 else
1ec14ad3 1580 *ring = bsd_ring;
5c1143bb 1581
1ec14ad3 1582 return intel_init_ring_buffer(dev, ring);
5c1143bb 1583}
549f7365
CW		 1584
1585int intel_init_blt_ring_buffer(struct drm_device *dev)
1586{
1587 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3 1588 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
549f7365 1589
1ec14ad3 1590 *ring = gen6_blt_ring;
549f7365 1591
1ec14ad3 1592 return intel_init_ring_buffer(dev, ring);
549f7365 1593}
Linux 6.x block layer and io_uring tree(s)