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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
a4d8a0fe | 30 | #include <linux/log2.h> |
760285e7 | 31 | #include <drm/drmP.h> |
62fdfeaf | 32 | #include "i915_drv.h" |
760285e7 | 33 | #include <drm/i915_drm.h> |
62fdfeaf | 34 | #include "i915_trace.h" |
881f47b6 | 35 | #include "intel_drv.h" |
62fdfeaf | 36 | |
82e104cc | 37 | int __intel_ring_space(int head, int tail, int size) |
c7dca47b | 38 | { |
4f54741e DG |
39 | int space = head - tail; |
40 | if (space <= 0) | |
1cf0ba14 | 41 | space += size; |
4f54741e | 42 | return space - I915_RING_FREE_SPACE; |
c7dca47b CW |
43 | } |
44 | ||
ebd0fd4b DG |
45 | void intel_ring_update_space(struct intel_ringbuffer *ringbuf) |
46 | { | |
47 | if (ringbuf->last_retired_head != -1) { | |
48 | ringbuf->head = ringbuf->last_retired_head; | |
49 | ringbuf->last_retired_head = -1; | |
50 | } | |
51 | ||
52 | ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR, | |
53 | ringbuf->tail, ringbuf->size); | |
54 | } | |
55 | ||
117897f4 | 56 | bool intel_engine_stopped(struct intel_engine_cs *engine) |
09246732 | 57 | { |
0bc40be8 | 58 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
666796da | 59 | return dev_priv->gpu_error.stop_rings & intel_engine_flag(engine); |
88b4aa87 | 60 | } |
09246732 | 61 | |
0bc40be8 | 62 | static void __intel_ring_advance(struct intel_engine_cs *engine) |
88b4aa87 | 63 | { |
0bc40be8 | 64 | struct intel_ringbuffer *ringbuf = engine->buffer; |
93b0a4e0 | 65 | ringbuf->tail &= ringbuf->size - 1; |
117897f4 | 66 | if (intel_engine_stopped(engine)) |
09246732 | 67 | return; |
0bc40be8 | 68 | engine->write_tail(engine, ringbuf->tail); |
09246732 CW |
69 | } |
70 | ||
b72f3acb | 71 | static int |
a84c3ae1 | 72 | gen2_render_ring_flush(struct drm_i915_gem_request *req, |
46f0f8d1 CW |
73 | u32 invalidate_domains, |
74 | u32 flush_domains) | |
75 | { | |
4a570db5 | 76 | struct intel_engine_cs *engine = req->engine; |
46f0f8d1 CW |
77 | u32 cmd; |
78 | int ret; | |
79 | ||
80 | cmd = MI_FLUSH; | |
31b14c9f | 81 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
46f0f8d1 CW |
82 | cmd |= MI_NO_WRITE_FLUSH; |
83 | ||
84 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
85 | cmd |= MI_READ_FLUSH; | |
86 | ||
5fb9de1a | 87 | ret = intel_ring_begin(req, 2); |
46f0f8d1 CW |
88 | if (ret) |
89 | return ret; | |
90 | ||
e2f80391 TU |
91 | intel_ring_emit(engine, cmd); |
92 | intel_ring_emit(engine, MI_NOOP); | |
93 | intel_ring_advance(engine); | |
46f0f8d1 CW |
94 | |
95 | return 0; | |
96 | } | |
97 | ||
98 | static int | |
a84c3ae1 | 99 | gen4_render_ring_flush(struct drm_i915_gem_request *req, |
46f0f8d1 CW |
100 | u32 invalidate_domains, |
101 | u32 flush_domains) | |
62fdfeaf | 102 | { |
4a570db5 | 103 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 104 | struct drm_device *dev = engine->dev; |
6f392d54 | 105 | u32 cmd; |
b72f3acb | 106 | int ret; |
6f392d54 | 107 | |
36d527de CW |
108 | /* |
109 | * read/write caches: | |
110 | * | |
111 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
112 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
113 | * also flushed at 2d versus 3d pipeline switches. | |
114 | * | |
115 | * read-only caches: | |
116 | * | |
117 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
118 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
119 | * | |
120 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
121 | * | |
122 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
123 | * invalidated when MI_EXE_FLUSH is set. | |
124 | * | |
125 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
126 | * invalidated with every MI_FLUSH. | |
127 | * | |
128 | * TLBs: | |
129 | * | |
130 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
131 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
132 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
133 | * are flushed at any MI_FLUSH. | |
134 | */ | |
135 | ||
136 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
46f0f8d1 | 137 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
36d527de | 138 | cmd &= ~MI_NO_WRITE_FLUSH; |
36d527de CW |
139 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
140 | cmd |= MI_EXE_FLUSH; | |
62fdfeaf | 141 | |
36d527de CW |
142 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
143 | (IS_G4X(dev) || IS_GEN5(dev))) | |
144 | cmd |= MI_INVALIDATE_ISP; | |
70eac33e | 145 | |
5fb9de1a | 146 | ret = intel_ring_begin(req, 2); |
36d527de CW |
147 | if (ret) |
148 | return ret; | |
b72f3acb | 149 | |
e2f80391 TU |
150 | intel_ring_emit(engine, cmd); |
151 | intel_ring_emit(engine, MI_NOOP); | |
152 | intel_ring_advance(engine); | |
b72f3acb CW |
153 | |
154 | return 0; | |
8187a2b7 ZN |
155 | } |
156 | ||
8d315287 JB |
157 | /** |
158 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
159 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
160 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
161 | * | |
162 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
163 | * produced by non-pipelined state commands), software needs to first | |
164 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
165 | * 0. | |
166 | * | |
167 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
168 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
169 | * | |
170 | * And the workaround for these two requires this workaround first: | |
171 | * | |
172 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
173 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
174 | * flushes. | |
175 | * | |
176 | * And this last workaround is tricky because of the requirements on | |
177 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
178 | * volume 2 part 1: | |
179 | * | |
180 | * "1 of the following must also be set: | |
181 | * - Render Target Cache Flush Enable ([12] of DW1) | |
182 | * - Depth Cache Flush Enable ([0] of DW1) | |
183 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
184 | * - Depth Stall ([13] of DW1) | |
185 | * - Post-Sync Operation ([13] of DW1) | |
186 | * - Notify Enable ([8] of DW1)" | |
187 | * | |
188 | * The cache flushes require the workaround flush that triggered this | |
189 | * one, so we can't use it. Depth stall would trigger the same. | |
190 | * Post-sync nonzero is what triggered this second workaround, so we | |
191 | * can't use that one either. Notify enable is IRQs, which aren't | |
192 | * really our business. That leaves only stall at scoreboard. | |
193 | */ | |
194 | static int | |
f2cf1fcc | 195 | intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req) |
8d315287 | 196 | { |
4a570db5 | 197 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 198 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
199 | int ret; |
200 | ||
5fb9de1a | 201 | ret = intel_ring_begin(req, 6); |
8d315287 JB |
202 | if (ret) |
203 | return ret; | |
204 | ||
e2f80391 TU |
205 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5)); |
206 | intel_ring_emit(engine, PIPE_CONTROL_CS_STALL | | |
8d315287 | 207 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
e2f80391 TU |
208 | intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
209 | intel_ring_emit(engine, 0); /* low dword */ | |
210 | intel_ring_emit(engine, 0); /* high dword */ | |
211 | intel_ring_emit(engine, MI_NOOP); | |
212 | intel_ring_advance(engine); | |
8d315287 | 213 | |
5fb9de1a | 214 | ret = intel_ring_begin(req, 6); |
8d315287 JB |
215 | if (ret) |
216 | return ret; | |
217 | ||
e2f80391 TU |
218 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5)); |
219 | intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE); | |
220 | intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
221 | intel_ring_emit(engine, 0); | |
222 | intel_ring_emit(engine, 0); | |
223 | intel_ring_emit(engine, MI_NOOP); | |
224 | intel_ring_advance(engine); | |
8d315287 JB |
225 | |
226 | return 0; | |
227 | } | |
228 | ||
229 | static int | |
a84c3ae1 JH |
230 | gen6_render_ring_flush(struct drm_i915_gem_request *req, |
231 | u32 invalidate_domains, u32 flush_domains) | |
8d315287 | 232 | { |
4a570db5 | 233 | struct intel_engine_cs *engine = req->engine; |
8d315287 | 234 | u32 flags = 0; |
e2f80391 | 235 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
236 | int ret; |
237 | ||
b3111509 | 238 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
f2cf1fcc | 239 | ret = intel_emit_post_sync_nonzero_flush(req); |
b3111509 PZ |
240 | if (ret) |
241 | return ret; | |
242 | ||
8d315287 JB |
243 | /* Just flush everything. Experiments have shown that reducing the |
244 | * number of bits based on the write domains has little performance | |
245 | * impact. | |
246 | */ | |
7d54a904 CW |
247 | if (flush_domains) { |
248 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
249 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
250 | /* | |
251 | * Ensure that any following seqno writes only happen | |
252 | * when the render cache is indeed flushed. | |
253 | */ | |
97f209bc | 254 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 CW |
255 | } |
256 | if (invalidate_domains) { | |
257 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
258 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
259 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
260 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
261 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
262 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
263 | /* | |
264 | * TLB invalidate requires a post-sync write. | |
265 | */ | |
3ac78313 | 266 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 267 | } |
8d315287 | 268 | |
5fb9de1a | 269 | ret = intel_ring_begin(req, 4); |
8d315287 JB |
270 | if (ret) |
271 | return ret; | |
272 | ||
e2f80391 TU |
273 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4)); |
274 | intel_ring_emit(engine, flags); | |
275 | intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
276 | intel_ring_emit(engine, 0); | |
277 | intel_ring_advance(engine); | |
8d315287 JB |
278 | |
279 | return 0; | |
280 | } | |
281 | ||
f3987631 | 282 | static int |
f2cf1fcc | 283 | gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req) |
f3987631 | 284 | { |
4a570db5 | 285 | struct intel_engine_cs *engine = req->engine; |
f3987631 PZ |
286 | int ret; |
287 | ||
5fb9de1a | 288 | ret = intel_ring_begin(req, 4); |
f3987631 PZ |
289 | if (ret) |
290 | return ret; | |
291 | ||
e2f80391 TU |
292 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4)); |
293 | intel_ring_emit(engine, PIPE_CONTROL_CS_STALL | | |
f3987631 | 294 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
e2f80391 TU |
295 | intel_ring_emit(engine, 0); |
296 | intel_ring_emit(engine, 0); | |
297 | intel_ring_advance(engine); | |
f3987631 PZ |
298 | |
299 | return 0; | |
300 | } | |
301 | ||
4772eaeb | 302 | static int |
a84c3ae1 | 303 | gen7_render_ring_flush(struct drm_i915_gem_request *req, |
4772eaeb PZ |
304 | u32 invalidate_domains, u32 flush_domains) |
305 | { | |
4a570db5 | 306 | struct intel_engine_cs *engine = req->engine; |
4772eaeb | 307 | u32 flags = 0; |
e2f80391 | 308 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
4772eaeb PZ |
309 | int ret; |
310 | ||
f3987631 PZ |
311 | /* |
312 | * Ensure that any following seqno writes only happen when the render | |
313 | * cache is indeed flushed. | |
314 | * | |
315 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
316 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
317 | * don't try to be clever and just set it unconditionally. | |
318 | */ | |
319 | flags |= PIPE_CONTROL_CS_STALL; | |
320 | ||
4772eaeb PZ |
321 | /* Just flush everything. Experiments have shown that reducing the |
322 | * number of bits based on the write domains has little performance | |
323 | * impact. | |
324 | */ | |
325 | if (flush_domains) { | |
326 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
327 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 328 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 329 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4772eaeb PZ |
330 | } |
331 | if (invalidate_domains) { | |
332 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
333 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
334 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
335 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
336 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
337 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
148b83d0 | 338 | flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; |
4772eaeb PZ |
339 | /* |
340 | * TLB invalidate requires a post-sync write. | |
341 | */ | |
342 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 343 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 | 344 | |
add284a3 CW |
345 | flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; |
346 | ||
f3987631 PZ |
347 | /* Workaround: we must issue a pipe_control with CS-stall bit |
348 | * set before a pipe_control command that has the state cache | |
349 | * invalidate bit set. */ | |
f2cf1fcc | 350 | gen7_render_ring_cs_stall_wa(req); |
4772eaeb PZ |
351 | } |
352 | ||
5fb9de1a | 353 | ret = intel_ring_begin(req, 4); |
4772eaeb PZ |
354 | if (ret) |
355 | return ret; | |
356 | ||
e2f80391 TU |
357 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4)); |
358 | intel_ring_emit(engine, flags); | |
359 | intel_ring_emit(engine, scratch_addr); | |
360 | intel_ring_emit(engine, 0); | |
361 | intel_ring_advance(engine); | |
4772eaeb PZ |
362 | |
363 | return 0; | |
364 | } | |
365 | ||
884ceace | 366 | static int |
f2cf1fcc | 367 | gen8_emit_pipe_control(struct drm_i915_gem_request *req, |
884ceace KG |
368 | u32 flags, u32 scratch_addr) |
369 | { | |
4a570db5 | 370 | struct intel_engine_cs *engine = req->engine; |
884ceace KG |
371 | int ret; |
372 | ||
5fb9de1a | 373 | ret = intel_ring_begin(req, 6); |
884ceace KG |
374 | if (ret) |
375 | return ret; | |
376 | ||
e2f80391 TU |
377 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6)); |
378 | intel_ring_emit(engine, flags); | |
379 | intel_ring_emit(engine, scratch_addr); | |
380 | intel_ring_emit(engine, 0); | |
381 | intel_ring_emit(engine, 0); | |
382 | intel_ring_emit(engine, 0); | |
383 | intel_ring_advance(engine); | |
884ceace KG |
384 | |
385 | return 0; | |
386 | } | |
387 | ||
a5f3d68e | 388 | static int |
a84c3ae1 | 389 | gen8_render_ring_flush(struct drm_i915_gem_request *req, |
a5f3d68e BW |
390 | u32 invalidate_domains, u32 flush_domains) |
391 | { | |
392 | u32 flags = 0; | |
4a570db5 | 393 | u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
02c9f7e3 | 394 | int ret; |
a5f3d68e BW |
395 | |
396 | flags |= PIPE_CONTROL_CS_STALL; | |
397 | ||
398 | if (flush_domains) { | |
399 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
400 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 401 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 402 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
a5f3d68e BW |
403 | } |
404 | if (invalidate_domains) { | |
405 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
406 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
407 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
408 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
409 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
410 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
411 | flags |= PIPE_CONTROL_QW_WRITE; | |
412 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
02c9f7e3 KG |
413 | |
414 | /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ | |
f2cf1fcc | 415 | ret = gen8_emit_pipe_control(req, |
02c9f7e3 KG |
416 | PIPE_CONTROL_CS_STALL | |
417 | PIPE_CONTROL_STALL_AT_SCOREBOARD, | |
418 | 0); | |
419 | if (ret) | |
420 | return ret; | |
a5f3d68e BW |
421 | } |
422 | ||
f2cf1fcc | 423 | return gen8_emit_pipe_control(req, flags, scratch_addr); |
a5f3d68e BW |
424 | } |
425 | ||
0bc40be8 | 426 | static void ring_write_tail(struct intel_engine_cs *engine, |
297b0c5b | 427 | u32 value) |
d46eefa2 | 428 | { |
0bc40be8 TU |
429 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
430 | I915_WRITE_TAIL(engine, value); | |
d46eefa2 XH |
431 | } |
432 | ||
0bc40be8 | 433 | u64 intel_ring_get_active_head(struct intel_engine_cs *engine) |
8187a2b7 | 434 | { |
0bc40be8 | 435 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
50877445 | 436 | u64 acthd; |
8187a2b7 | 437 | |
0bc40be8 TU |
438 | if (INTEL_INFO(engine->dev)->gen >= 8) |
439 | acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base), | |
440 | RING_ACTHD_UDW(engine->mmio_base)); | |
441 | else if (INTEL_INFO(engine->dev)->gen >= 4) | |
442 | acthd = I915_READ(RING_ACTHD(engine->mmio_base)); | |
50877445 CW |
443 | else |
444 | acthd = I915_READ(ACTHD); | |
445 | ||
446 | return acthd; | |
8187a2b7 ZN |
447 | } |
448 | ||
0bc40be8 | 449 | static void ring_setup_phys_status_page(struct intel_engine_cs *engine) |
035dc1e0 | 450 | { |
0bc40be8 | 451 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
035dc1e0 DV |
452 | u32 addr; |
453 | ||
454 | addr = dev_priv->status_page_dmah->busaddr; | |
0bc40be8 | 455 | if (INTEL_INFO(engine->dev)->gen >= 4) |
035dc1e0 DV |
456 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
457 | I915_WRITE(HWS_PGA, addr); | |
458 | } | |
459 | ||
0bc40be8 | 460 | static void intel_ring_setup_status_page(struct intel_engine_cs *engine) |
af75f269 | 461 | { |
0bc40be8 TU |
462 | struct drm_device *dev = engine->dev; |
463 | struct drm_i915_private *dev_priv = engine->dev->dev_private; | |
f0f59a00 | 464 | i915_reg_t mmio; |
af75f269 DL |
465 | |
466 | /* The ring status page addresses are no longer next to the rest of | |
467 | * the ring registers as of gen7. | |
468 | */ | |
469 | if (IS_GEN7(dev)) { | |
0bc40be8 | 470 | switch (engine->id) { |
af75f269 DL |
471 | case RCS: |
472 | mmio = RENDER_HWS_PGA_GEN7; | |
473 | break; | |
474 | case BCS: | |
475 | mmio = BLT_HWS_PGA_GEN7; | |
476 | break; | |
477 | /* | |
478 | * VCS2 actually doesn't exist on Gen7. Only shut up | |
479 | * gcc switch check warning | |
480 | */ | |
481 | case VCS2: | |
482 | case VCS: | |
483 | mmio = BSD_HWS_PGA_GEN7; | |
484 | break; | |
485 | case VECS: | |
486 | mmio = VEBOX_HWS_PGA_GEN7; | |
487 | break; | |
488 | } | |
0bc40be8 TU |
489 | } else if (IS_GEN6(engine->dev)) { |
490 | mmio = RING_HWS_PGA_GEN6(engine->mmio_base); | |
af75f269 DL |
491 | } else { |
492 | /* XXX: gen8 returns to sanity */ | |
0bc40be8 | 493 | mmio = RING_HWS_PGA(engine->mmio_base); |
af75f269 DL |
494 | } |
495 | ||
0bc40be8 | 496 | I915_WRITE(mmio, (u32)engine->status_page.gfx_addr); |
af75f269 DL |
497 | POSTING_READ(mmio); |
498 | ||
499 | /* | |
500 | * Flush the TLB for this page | |
501 | * | |
502 | * FIXME: These two bits have disappeared on gen8, so a question | |
503 | * arises: do we still need this and if so how should we go about | |
504 | * invalidating the TLB? | |
505 | */ | |
506 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) { | |
0bc40be8 | 507 | i915_reg_t reg = RING_INSTPM(engine->mmio_base); |
af75f269 DL |
508 | |
509 | /* ring should be idle before issuing a sync flush*/ | |
0bc40be8 | 510 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
af75f269 DL |
511 | |
512 | I915_WRITE(reg, | |
513 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
514 | INSTPM_SYNC_FLUSH)); | |
515 | if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, | |
516 | 1000)) | |
517 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", | |
0bc40be8 | 518 | engine->name); |
af75f269 DL |
519 | } |
520 | } | |
521 | ||
0bc40be8 | 522 | static bool stop_ring(struct intel_engine_cs *engine) |
8187a2b7 | 523 | { |
0bc40be8 | 524 | struct drm_i915_private *dev_priv = to_i915(engine->dev); |
8187a2b7 | 525 | |
0bc40be8 TU |
526 | if (!IS_GEN2(engine->dev)) { |
527 | I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); | |
528 | if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) { | |
529 | DRM_ERROR("%s : timed out trying to stop ring\n", | |
530 | engine->name); | |
9bec9b13 CW |
531 | /* Sometimes we observe that the idle flag is not |
532 | * set even though the ring is empty. So double | |
533 | * check before giving up. | |
534 | */ | |
0bc40be8 | 535 | if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine)) |
9bec9b13 | 536 | return false; |
9991ae78 CW |
537 | } |
538 | } | |
b7884eb4 | 539 | |
0bc40be8 TU |
540 | I915_WRITE_CTL(engine, 0); |
541 | I915_WRITE_HEAD(engine, 0); | |
542 | engine->write_tail(engine, 0); | |
8187a2b7 | 543 | |
0bc40be8 TU |
544 | if (!IS_GEN2(engine->dev)) { |
545 | (void)I915_READ_CTL(engine); | |
546 | I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); | |
9991ae78 | 547 | } |
a51435a3 | 548 | |
0bc40be8 | 549 | return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0; |
9991ae78 | 550 | } |
8187a2b7 | 551 | |
fc0768ce TE |
552 | void intel_engine_init_hangcheck(struct intel_engine_cs *engine) |
553 | { | |
554 | memset(&engine->hangcheck, 0, sizeof(engine->hangcheck)); | |
555 | } | |
556 | ||
0bc40be8 | 557 | static int init_ring_common(struct intel_engine_cs *engine) |
9991ae78 | 558 | { |
0bc40be8 | 559 | struct drm_device *dev = engine->dev; |
9991ae78 | 560 | struct drm_i915_private *dev_priv = dev->dev_private; |
0bc40be8 | 561 | struct intel_ringbuffer *ringbuf = engine->buffer; |
93b0a4e0 | 562 | struct drm_i915_gem_object *obj = ringbuf->obj; |
9991ae78 CW |
563 | int ret = 0; |
564 | ||
59bad947 | 565 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
9991ae78 | 566 | |
0bc40be8 | 567 | if (!stop_ring(engine)) { |
9991ae78 | 568 | /* G45 ring initialization often fails to reset head to zero */ |
6fd0d56e CW |
569 | DRM_DEBUG_KMS("%s head not reset to zero " |
570 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
571 | engine->name, |
572 | I915_READ_CTL(engine), | |
573 | I915_READ_HEAD(engine), | |
574 | I915_READ_TAIL(engine), | |
575 | I915_READ_START(engine)); | |
8187a2b7 | 576 | |
0bc40be8 | 577 | if (!stop_ring(engine)) { |
6fd0d56e CW |
578 | DRM_ERROR("failed to set %s head to zero " |
579 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
580 | engine->name, |
581 | I915_READ_CTL(engine), | |
582 | I915_READ_HEAD(engine), | |
583 | I915_READ_TAIL(engine), | |
584 | I915_READ_START(engine)); | |
9991ae78 CW |
585 | ret = -EIO; |
586 | goto out; | |
6fd0d56e | 587 | } |
8187a2b7 ZN |
588 | } |
589 | ||
9991ae78 | 590 | if (I915_NEED_GFX_HWS(dev)) |
0bc40be8 | 591 | intel_ring_setup_status_page(engine); |
9991ae78 | 592 | else |
0bc40be8 | 593 | ring_setup_phys_status_page(engine); |
9991ae78 | 594 | |
ece4a17d | 595 | /* Enforce ordering by reading HEAD register back */ |
0bc40be8 | 596 | I915_READ_HEAD(engine); |
ece4a17d | 597 | |
0d8957c8 DV |
598 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
599 | * registers with the above sequence (the readback of the HEAD registers | |
600 | * also enforces ordering), otherwise the hw might lose the new ring | |
601 | * register values. */ | |
0bc40be8 | 602 | I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj)); |
95468892 CW |
603 | |
604 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ | |
0bc40be8 | 605 | if (I915_READ_HEAD(engine)) |
95468892 | 606 | DRM_DEBUG("%s initialization failed [head=%08x], fudging\n", |
0bc40be8 TU |
607 | engine->name, I915_READ_HEAD(engine)); |
608 | I915_WRITE_HEAD(engine, 0); | |
609 | (void)I915_READ_HEAD(engine); | |
95468892 | 610 | |
0bc40be8 | 611 | I915_WRITE_CTL(engine, |
93b0a4e0 | 612 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 613 | | RING_VALID); |
8187a2b7 | 614 | |
8187a2b7 | 615 | /* If the head is still not zero, the ring is dead */ |
0bc40be8 TU |
616 | if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 && |
617 | I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) && | |
618 | (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) { | |
e74cfed5 | 619 | DRM_ERROR("%s initialization failed " |
48e48a0b | 620 | "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n", |
0bc40be8 TU |
621 | engine->name, |
622 | I915_READ_CTL(engine), | |
623 | I915_READ_CTL(engine) & RING_VALID, | |
624 | I915_READ_HEAD(engine), I915_READ_TAIL(engine), | |
625 | I915_READ_START(engine), | |
626 | (unsigned long)i915_gem_obj_ggtt_offset(obj)); | |
b7884eb4 DV |
627 | ret = -EIO; |
628 | goto out; | |
8187a2b7 ZN |
629 | } |
630 | ||
ebd0fd4b | 631 | ringbuf->last_retired_head = -1; |
0bc40be8 TU |
632 | ringbuf->head = I915_READ_HEAD(engine); |
633 | ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR; | |
ebd0fd4b | 634 | intel_ring_update_space(ringbuf); |
1ec14ad3 | 635 | |
fc0768ce | 636 | intel_engine_init_hangcheck(engine); |
50f018df | 637 | |
b7884eb4 | 638 | out: |
59bad947 | 639 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
640 | |
641 | return ret; | |
8187a2b7 ZN |
642 | } |
643 | ||
9b1136d5 | 644 | void |
0bc40be8 | 645 | intel_fini_pipe_control(struct intel_engine_cs *engine) |
9b1136d5 | 646 | { |
0bc40be8 | 647 | struct drm_device *dev = engine->dev; |
9b1136d5 | 648 | |
0bc40be8 | 649 | if (engine->scratch.obj == NULL) |
9b1136d5 OM |
650 | return; |
651 | ||
652 | if (INTEL_INFO(dev)->gen >= 5) { | |
0bc40be8 TU |
653 | kunmap(sg_page(engine->scratch.obj->pages->sgl)); |
654 | i915_gem_object_ggtt_unpin(engine->scratch.obj); | |
9b1136d5 OM |
655 | } |
656 | ||
0bc40be8 TU |
657 | drm_gem_object_unreference(&engine->scratch.obj->base); |
658 | engine->scratch.obj = NULL; | |
9b1136d5 OM |
659 | } |
660 | ||
661 | int | |
0bc40be8 | 662 | intel_init_pipe_control(struct intel_engine_cs *engine) |
c6df541c | 663 | { |
c6df541c CW |
664 | int ret; |
665 | ||
0bc40be8 | 666 | WARN_ON(engine->scratch.obj); |
c6df541c | 667 | |
0bc40be8 TU |
668 | engine->scratch.obj = i915_gem_alloc_object(engine->dev, 4096); |
669 | if (engine->scratch.obj == NULL) { | |
c6df541c CW |
670 | DRM_ERROR("Failed to allocate seqno page\n"); |
671 | ret = -ENOMEM; | |
672 | goto err; | |
673 | } | |
e4ffd173 | 674 | |
0bc40be8 TU |
675 | ret = i915_gem_object_set_cache_level(engine->scratch.obj, |
676 | I915_CACHE_LLC); | |
a9cc726c DV |
677 | if (ret) |
678 | goto err_unref; | |
c6df541c | 679 | |
0bc40be8 | 680 | ret = i915_gem_obj_ggtt_pin(engine->scratch.obj, 4096, 0); |
c6df541c CW |
681 | if (ret) |
682 | goto err_unref; | |
683 | ||
0bc40be8 TU |
684 | engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(engine->scratch.obj); |
685 | engine->scratch.cpu_page = kmap(sg_page(engine->scratch.obj->pages->sgl)); | |
686 | if (engine->scratch.cpu_page == NULL) { | |
56b085a0 | 687 | ret = -ENOMEM; |
c6df541c | 688 | goto err_unpin; |
56b085a0 | 689 | } |
c6df541c | 690 | |
2b1086cc | 691 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
0bc40be8 | 692 | engine->name, engine->scratch.gtt_offset); |
c6df541c CW |
693 | return 0; |
694 | ||
695 | err_unpin: | |
0bc40be8 | 696 | i915_gem_object_ggtt_unpin(engine->scratch.obj); |
c6df541c | 697 | err_unref: |
0bc40be8 | 698 | drm_gem_object_unreference(&engine->scratch.obj->base); |
c6df541c | 699 | err: |
c6df541c CW |
700 | return ret; |
701 | } | |
702 | ||
e2be4faf | 703 | static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req) |
86d7f238 | 704 | { |
7225342a | 705 | int ret, i; |
4a570db5 | 706 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 707 | struct drm_device *dev = engine->dev; |
888b5995 | 708 | struct drm_i915_private *dev_priv = dev->dev_private; |
7225342a | 709 | struct i915_workarounds *w = &dev_priv->workarounds; |
888b5995 | 710 | |
02235808 | 711 | if (w->count == 0) |
7225342a | 712 | return 0; |
888b5995 | 713 | |
e2f80391 | 714 | engine->gpu_caches_dirty = true; |
4866d729 | 715 | ret = intel_ring_flush_all_caches(req); |
7225342a MK |
716 | if (ret) |
717 | return ret; | |
888b5995 | 718 | |
5fb9de1a | 719 | ret = intel_ring_begin(req, (w->count * 2 + 2)); |
7225342a MK |
720 | if (ret) |
721 | return ret; | |
722 | ||
e2f80391 | 723 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count)); |
7225342a | 724 | for (i = 0; i < w->count; i++) { |
e2f80391 TU |
725 | intel_ring_emit_reg(engine, w->reg[i].addr); |
726 | intel_ring_emit(engine, w->reg[i].value); | |
7225342a | 727 | } |
e2f80391 | 728 | intel_ring_emit(engine, MI_NOOP); |
7225342a | 729 | |
e2f80391 | 730 | intel_ring_advance(engine); |
7225342a | 731 | |
e2f80391 | 732 | engine->gpu_caches_dirty = true; |
4866d729 | 733 | ret = intel_ring_flush_all_caches(req); |
7225342a MK |
734 | if (ret) |
735 | return ret; | |
888b5995 | 736 | |
7225342a | 737 | DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count); |
888b5995 | 738 | |
7225342a | 739 | return 0; |
86d7f238 AS |
740 | } |
741 | ||
8753181e | 742 | static int intel_rcs_ctx_init(struct drm_i915_gem_request *req) |
8f0e2b9d DV |
743 | { |
744 | int ret; | |
745 | ||
e2be4faf | 746 | ret = intel_ring_workarounds_emit(req); |
8f0e2b9d DV |
747 | if (ret != 0) |
748 | return ret; | |
749 | ||
be01363f | 750 | ret = i915_gem_render_state_init(req); |
8f0e2b9d | 751 | if (ret) |
e26e1b97 | 752 | return ret; |
8f0e2b9d | 753 | |
e26e1b97 | 754 | return 0; |
8f0e2b9d DV |
755 | } |
756 | ||
7225342a | 757 | static int wa_add(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
758 | i915_reg_t addr, |
759 | const u32 mask, const u32 val) | |
7225342a MK |
760 | { |
761 | const u32 idx = dev_priv->workarounds.count; | |
762 | ||
763 | if (WARN_ON(idx >= I915_MAX_WA_REGS)) | |
764 | return -ENOSPC; | |
765 | ||
766 | dev_priv->workarounds.reg[idx].addr = addr; | |
767 | dev_priv->workarounds.reg[idx].value = val; | |
768 | dev_priv->workarounds.reg[idx].mask = mask; | |
769 | ||
770 | dev_priv->workarounds.count++; | |
771 | ||
772 | return 0; | |
86d7f238 AS |
773 | } |
774 | ||
ca5a0fbd | 775 | #define WA_REG(addr, mask, val) do { \ |
cf4b0de6 | 776 | const int r = wa_add(dev_priv, (addr), (mask), (val)); \ |
7225342a MK |
777 | if (r) \ |
778 | return r; \ | |
ca5a0fbd | 779 | } while (0) |
7225342a MK |
780 | |
781 | #define WA_SET_BIT_MASKED(addr, mask) \ | |
26459343 | 782 | WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask)) |
7225342a MK |
783 | |
784 | #define WA_CLR_BIT_MASKED(addr, mask) \ | |
26459343 | 785 | WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask)) |
7225342a | 786 | |
98533251 | 787 | #define WA_SET_FIELD_MASKED(addr, mask, value) \ |
cf4b0de6 | 788 | WA_REG(addr, mask, _MASKED_FIELD(mask, value)) |
7225342a | 789 | |
cf4b0de6 DL |
790 | #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask)) |
791 | #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask)) | |
7225342a | 792 | |
cf4b0de6 | 793 | #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val) |
7225342a | 794 | |
0bc40be8 TU |
795 | static int wa_ring_whitelist_reg(struct intel_engine_cs *engine, |
796 | i915_reg_t reg) | |
33136b06 | 797 | { |
0bc40be8 | 798 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
33136b06 | 799 | struct i915_workarounds *wa = &dev_priv->workarounds; |
0bc40be8 | 800 | const uint32_t index = wa->hw_whitelist_count[engine->id]; |
33136b06 AS |
801 | |
802 | if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS)) | |
803 | return -EINVAL; | |
804 | ||
0bc40be8 | 805 | WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index), |
33136b06 | 806 | i915_mmio_reg_offset(reg)); |
0bc40be8 | 807 | wa->hw_whitelist_count[engine->id]++; |
33136b06 AS |
808 | |
809 | return 0; | |
810 | } | |
811 | ||
0bc40be8 | 812 | static int gen8_init_workarounds(struct intel_engine_cs *engine) |
e9a64ada | 813 | { |
0bc40be8 | 814 | struct drm_device *dev = engine->dev; |
68c6198b AS |
815 | struct drm_i915_private *dev_priv = dev->dev_private; |
816 | ||
817 | WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); | |
e9a64ada | 818 | |
717d84d6 AS |
819 | /* WaDisableAsyncFlipPerfMode:bdw,chv */ |
820 | WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE); | |
821 | ||
d0581194 AS |
822 | /* WaDisablePartialInstShootdown:bdw,chv */ |
823 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
824 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); | |
825 | ||
a340af58 AS |
826 | /* Use Force Non-Coherent whenever executing a 3D context. This is a |
827 | * workaround for for a possible hang in the unlikely event a TLB | |
828 | * invalidation occurs during a PSD flush. | |
829 | */ | |
830 | /* WaForceEnableNonCoherent:bdw,chv */ | |
120f5d28 | 831 | /* WaHdcDisableFetchWhenMasked:bdw,chv */ |
a340af58 | 832 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
120f5d28 | 833 | HDC_DONOT_FETCH_MEM_WHEN_MASKED | |
a340af58 AS |
834 | HDC_FORCE_NON_COHERENT); |
835 | ||
6def8fdd AS |
836 | /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: |
837 | * "The Hierarchical Z RAW Stall Optimization allows non-overlapping | |
838 | * polygons in the same 8x4 pixel/sample area to be processed without | |
839 | * stalling waiting for the earlier ones to write to Hierarchical Z | |
840 | * buffer." | |
841 | * | |
842 | * This optimization is off by default for BDW and CHV; turn it on. | |
843 | */ | |
844 | WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); | |
845 | ||
48404636 AS |
846 | /* Wa4x4STCOptimizationDisable:bdw,chv */ |
847 | WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); | |
848 | ||
7eebcde6 AS |
849 | /* |
850 | * BSpec recommends 8x4 when MSAA is used, | |
851 | * however in practice 16x4 seems fastest. | |
852 | * | |
853 | * Note that PS/WM thread counts depend on the WIZ hashing | |
854 | * disable bit, which we don't touch here, but it's good | |
855 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
856 | */ | |
857 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
858 | GEN6_WIZ_HASHING_MASK, | |
859 | GEN6_WIZ_HASHING_16x4); | |
860 | ||
e9a64ada AS |
861 | return 0; |
862 | } | |
863 | ||
0bc40be8 | 864 | static int bdw_init_workarounds(struct intel_engine_cs *engine) |
86d7f238 | 865 | { |
e9a64ada | 866 | int ret; |
0bc40be8 | 867 | struct drm_device *dev = engine->dev; |
888b5995 | 868 | struct drm_i915_private *dev_priv = dev->dev_private; |
86d7f238 | 869 | |
0bc40be8 | 870 | ret = gen8_init_workarounds(engine); |
e9a64ada AS |
871 | if (ret) |
872 | return ret; | |
873 | ||
101b376d | 874 | /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ |
d0581194 | 875 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
86d7f238 | 876 | |
101b376d | 877 | /* WaDisableDopClockGating:bdw */ |
7225342a MK |
878 | WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, |
879 | DOP_CLOCK_GATING_DISABLE); | |
86d7f238 | 880 | |
7225342a MK |
881 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
882 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
86d7f238 | 883 | |
7225342a | 884 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
35cb6f3b DL |
885 | /* WaForceContextSaveRestoreNonCoherent:bdw */ |
886 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | | |
35cb6f3b | 887 | /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ |
7225342a | 888 | (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); |
86d7f238 | 889 | |
86d7f238 AS |
890 | return 0; |
891 | } | |
892 | ||
0bc40be8 | 893 | static int chv_init_workarounds(struct intel_engine_cs *engine) |
00e1e623 | 894 | { |
e9a64ada | 895 | int ret; |
0bc40be8 | 896 | struct drm_device *dev = engine->dev; |
00e1e623 VS |
897 | struct drm_i915_private *dev_priv = dev->dev_private; |
898 | ||
0bc40be8 | 899 | ret = gen8_init_workarounds(engine); |
e9a64ada AS |
900 | if (ret) |
901 | return ret; | |
902 | ||
00e1e623 | 903 | /* WaDisableThreadStallDopClockGating:chv */ |
d0581194 | 904 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
00e1e623 | 905 | |
d60de81d KG |
906 | /* Improve HiZ throughput on CHV. */ |
907 | WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); | |
908 | ||
7225342a MK |
909 | return 0; |
910 | } | |
911 | ||
0bc40be8 | 912 | static int gen9_init_workarounds(struct intel_engine_cs *engine) |
3b106531 | 913 | { |
0bc40be8 | 914 | struct drm_device *dev = engine->dev; |
ab0dfafe | 915 | struct drm_i915_private *dev_priv = dev->dev_private; |
e0f3fa09 | 916 | int ret; |
ab0dfafe | 917 | |
12be73a0 TG |
918 | /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */ |
919 | I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE)); | |
920 | ||
68370e0a | 921 | /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */ |
9c4cbf82 MK |
922 | I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | |
923 | GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); | |
924 | ||
68370e0a | 925 | /* WaDisableKillLogic:bxt,skl,kbl */ |
9c4cbf82 MK |
926 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | |
927 | ECOCHK_DIS_TLB); | |
928 | ||
68370e0a MK |
929 | /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */ |
930 | /* WaDisablePartialInstShootdown:skl,bxt,kbl */ | |
ab0dfafe | 931 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
950b2aae | 932 | FLOW_CONTROL_ENABLE | |
ab0dfafe HN |
933 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); |
934 | ||
68370e0a | 935 | /* Syncing dependencies between camera and graphics:skl,bxt,kbl */ |
8424171e NH |
936 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
937 | GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC); | |
938 | ||
e87a005d JN |
939 | /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */ |
940 | if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) || | |
941 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) | |
a86eb582 DL |
942 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
943 | GEN9_DG_MIRROR_FIX_ENABLE); | |
1de4582f | 944 | |
e87a005d JN |
945 | /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ |
946 | if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) || | |
947 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { | |
183c6dac DL |
948 | WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, |
949 | GEN9_RHWO_OPTIMIZATION_DISABLE); | |
9b01435d AS |
950 | /* |
951 | * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set | |
952 | * but we do that in per ctx batchbuffer as there is an issue | |
953 | * with this register not getting restored on ctx restore | |
954 | */ | |
183c6dac DL |
955 | } |
956 | ||
68370e0a MK |
957 | /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */ |
958 | /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */ | |
bfd8ad4e TG |
959 | WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, |
960 | GEN9_ENABLE_YV12_BUGFIX | | |
961 | GEN9_ENABLE_GPGPU_PREEMPTION); | |
cac23df4 | 962 | |
68370e0a MK |
963 | /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */ |
964 | /* WaDisablePartialResolveInVc:skl,bxt,kbl */ | |
60294683 AS |
965 | WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE | |
966 | GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE)); | |
9370cd98 | 967 | |
68370e0a | 968 | /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */ |
e2db7071 DL |
969 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
970 | GEN9_CCS_TLB_PREFETCH_ENABLE); | |
971 | ||
5a2ae95e | 972 | /* WaDisableMaskBasedCammingInRCC:skl,bxt */ |
e87a005d JN |
973 | if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) || |
974 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) | |
38a39a7b BW |
975 | WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, |
976 | PIXEL_MASK_CAMMING_DISABLE); | |
977 | ||
6fd72492 MK |
978 | /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */ |
979 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
980 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | | |
981 | HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); | |
8ea6f892 | 982 | |
60f452e6 MK |
983 | /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are |
984 | * both tied to WaForceContextSaveRestoreNonCoherent | |
985 | * in some hsds for skl. We keep the tie for all gen9. The | |
986 | * documentation is a bit hazy and so we want to get common behaviour, | |
987 | * even though there is no clear evidence we would need both on kbl/bxt. | |
988 | * This area has been source of system hangs so we play it safe | |
989 | * and mimic the skl regardless of what bspec says. | |
990 | * | |
991 | * Use Force Non-Coherent whenever executing a 3D context. This | |
992 | * is a workaround for a possible hang in the unlikely event | |
993 | * a TLB invalidation occurs during a PSD flush. | |
994 | */ | |
995 | ||
996 | /* WaForceEnableNonCoherent:skl,bxt,kbl */ | |
997 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
998 | HDC_FORCE_NON_COHERENT); | |
999 | ||
1000 | /* WaDisableHDCInvalidation:skl,bxt,kbl */ | |
1001 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | | |
1002 | BDW_DISABLE_HDC_INVALIDATION); | |
1003 | ||
68370e0a MK |
1004 | /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */ |
1005 | if (IS_SKYLAKE(dev_priv) || | |
1006 | IS_KABYLAKE(dev_priv) || | |
1007 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) | |
8c761609 AS |
1008 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
1009 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
8c761609 | 1010 | |
68370e0a | 1011 | /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */ |
6b6d5626 RB |
1012 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); |
1013 | ||
68370e0a | 1014 | /* WaOCLCoherentLineFlush:skl,bxt,kbl */ |
6ecf56ae AS |
1015 | I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | |
1016 | GEN8_LQSC_FLUSH_COHERENT_LINES)); | |
1017 | ||
f98edb2b | 1018 | /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */ |
1019 | ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG); | |
1020 | if (ret) | |
1021 | return ret; | |
1022 | ||
68370e0a | 1023 | /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */ |
0bc40be8 | 1024 | ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); |
e0f3fa09 AS |
1025 | if (ret) |
1026 | return ret; | |
1027 | ||
68370e0a | 1028 | /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */ |
0bc40be8 | 1029 | ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); |
3669ab61 AS |
1030 | if (ret) |
1031 | return ret; | |
1032 | ||
3b106531 HN |
1033 | return 0; |
1034 | } | |
1035 | ||
0bc40be8 | 1036 | static int skl_tune_iz_hashing(struct intel_engine_cs *engine) |
b7668791 | 1037 | { |
0bc40be8 | 1038 | struct drm_device *dev = engine->dev; |
b7668791 DL |
1039 | struct drm_i915_private *dev_priv = dev->dev_private; |
1040 | u8 vals[3] = { 0, 0, 0 }; | |
1041 | unsigned int i; | |
1042 | ||
1043 | for (i = 0; i < 3; i++) { | |
1044 | u8 ss; | |
1045 | ||
1046 | /* | |
1047 | * Only consider slices where one, and only one, subslice has 7 | |
1048 | * EUs | |
1049 | */ | |
a4d8a0fe | 1050 | if (!is_power_of_2(dev_priv->info.subslice_7eu[i])) |
b7668791 DL |
1051 | continue; |
1052 | ||
1053 | /* | |
1054 | * subslice_7eu[i] != 0 (because of the check above) and | |
1055 | * ss_max == 4 (maximum number of subslices possible per slice) | |
1056 | * | |
1057 | * -> 0 <= ss <= 3; | |
1058 | */ | |
1059 | ss = ffs(dev_priv->info.subslice_7eu[i]) - 1; | |
1060 | vals[i] = 3 - ss; | |
1061 | } | |
1062 | ||
1063 | if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) | |
1064 | return 0; | |
1065 | ||
1066 | /* Tune IZ hashing. See intel_device_info_runtime_init() */ | |
1067 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
1068 | GEN9_IZ_HASHING_MASK(2) | | |
1069 | GEN9_IZ_HASHING_MASK(1) | | |
1070 | GEN9_IZ_HASHING_MASK(0), | |
1071 | GEN9_IZ_HASHING(2, vals[2]) | | |
1072 | GEN9_IZ_HASHING(1, vals[1]) | | |
1073 | GEN9_IZ_HASHING(0, vals[0])); | |
1074 | ||
1075 | return 0; | |
1076 | } | |
1077 | ||
0bc40be8 | 1078 | static int skl_init_workarounds(struct intel_engine_cs *engine) |
8d205494 | 1079 | { |
aa0011a8 | 1080 | int ret; |
0bc40be8 | 1081 | struct drm_device *dev = engine->dev; |
d0bbbc4f DL |
1082 | struct drm_i915_private *dev_priv = dev->dev_private; |
1083 | ||
0bc40be8 | 1084 | ret = gen9_init_workarounds(engine); |
aa0011a8 AS |
1085 | if (ret) |
1086 | return ret; | |
8d205494 | 1087 | |
a78536e7 AS |
1088 | /* |
1089 | * Actual WA is to disable percontext preemption granularity control | |
1090 | * until D0 which is the default case so this is equivalent to | |
1091 | * !WaDisablePerCtxtPreemptionGranularityControl:skl | |
1092 | */ | |
1093 | if (IS_SKL_REVID(dev, SKL_REVID_E0, REVID_FOREVER)) { | |
1094 | I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1, | |
1095 | _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL)); | |
1096 | } | |
1097 | ||
e87a005d | 1098 | if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) { |
9c4cbf82 MK |
1099 | /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */ |
1100 | I915_WRITE(FF_SLICE_CS_CHICKEN2, | |
1101 | _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE)); | |
1102 | } | |
1103 | ||
1104 | /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes | |
1105 | * involving this register should also be added to WA batch as required. | |
1106 | */ | |
e87a005d | 1107 | if (IS_SKL_REVID(dev, 0, SKL_REVID_E0)) |
9c4cbf82 MK |
1108 | /* WaDisableLSQCROPERFforOCL:skl */ |
1109 | I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | | |
1110 | GEN8_LQSC_RO_PERF_DIS); | |
1111 | ||
1112 | /* WaEnableGapsTsvCreditFix:skl */ | |
e87a005d | 1113 | if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) { |
9c4cbf82 MK |
1114 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | |
1115 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
1116 | } | |
1117 | ||
d0bbbc4f | 1118 | /* WaDisablePowerCompilerClockGating:skl */ |
e87a005d | 1119 | if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0)) |
d0bbbc4f DL |
1120 | WA_SET_BIT_MASKED(HIZ_CHICKEN, |
1121 | BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE); | |
1122 | ||
e87a005d JN |
1123 | /* WaBarrierPerformanceFixDisable:skl */ |
1124 | if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0)) | |
5b6fd12a VS |
1125 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
1126 | HDC_FENCE_DEST_SLM_DISABLE | | |
1127 | HDC_BARRIER_PERFORMANCE_DISABLE); | |
1128 | ||
9bd9dfb4 | 1129 | /* WaDisableSbeCacheDispatchPortSharing:skl */ |
e87a005d | 1130 | if (IS_SKL_REVID(dev, 0, SKL_REVID_F0)) |
9bd9dfb4 MK |
1131 | WA_SET_BIT_MASKED( |
1132 | GEN7_HALF_SLICE_CHICKEN1, | |
1133 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
9bd9dfb4 | 1134 | |
c000456c MK |
1135 | /* WaDisableGafsUnitClkGating:skl */ |
1136 | WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); | |
1137 | ||
6107497e | 1138 | /* WaDisableLSQCROPERFforOCL:skl */ |
0bc40be8 | 1139 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
6107497e AS |
1140 | if (ret) |
1141 | return ret; | |
1142 | ||
0bc40be8 | 1143 | return skl_tune_iz_hashing(engine); |
7225342a MK |
1144 | } |
1145 | ||
0bc40be8 | 1146 | static int bxt_init_workarounds(struct intel_engine_cs *engine) |
cae0437f | 1147 | { |
aa0011a8 | 1148 | int ret; |
0bc40be8 | 1149 | struct drm_device *dev = engine->dev; |
dfb601e6 NH |
1150 | struct drm_i915_private *dev_priv = dev->dev_private; |
1151 | ||
0bc40be8 | 1152 | ret = gen9_init_workarounds(engine); |
aa0011a8 AS |
1153 | if (ret) |
1154 | return ret; | |
cae0437f | 1155 | |
9c4cbf82 MK |
1156 | /* WaStoreMultiplePTEenable:bxt */ |
1157 | /* This is a requirement according to Hardware specification */ | |
cbdc12a9 | 1158 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) |
9c4cbf82 MK |
1159 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF); |
1160 | ||
1161 | /* WaSetClckGatingDisableMedia:bxt */ | |
cbdc12a9 | 1162 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { |
9c4cbf82 MK |
1163 | I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) & |
1164 | ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE)); | |
1165 | } | |
1166 | ||
dfb601e6 NH |
1167 | /* WaDisableThreadStallDopClockGating:bxt */ |
1168 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
1169 | STALL_DOP_GATING_DISABLE); | |
1170 | ||
983b4b9d | 1171 | /* WaDisableSbeCacheDispatchPortSharing:bxt */ |
e87a005d | 1172 | if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) { |
983b4b9d NH |
1173 | WA_SET_BIT_MASKED( |
1174 | GEN7_HALF_SLICE_CHICKEN1, | |
1175 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
1176 | } | |
1177 | ||
2c8580e4 AS |
1178 | /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */ |
1179 | /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */ | |
1180 | /* WaDisableObjectLevelPreemtionForInstanceId:bxt */ | |
a786d53a | 1181 | /* WaDisableLSQCROPERFforOCL:bxt */ |
2c8580e4 | 1182 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { |
0bc40be8 | 1183 | ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1); |
2c8580e4 AS |
1184 | if (ret) |
1185 | return ret; | |
a786d53a | 1186 | |
0bc40be8 | 1187 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
a786d53a AS |
1188 | if (ret) |
1189 | return ret; | |
2c8580e4 AS |
1190 | } |
1191 | ||
7b9005cd MK |
1192 | /* WaInsertDummyPushConstPs:bxt */ |
1193 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) | |
1194 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | |
1195 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1196 | ||
cae0437f NH |
1197 | return 0; |
1198 | } | |
1199 | ||
68370e0a MK |
1200 | static int kbl_init_workarounds(struct intel_engine_cs *engine) |
1201 | { | |
79164509 | 1202 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
68370e0a MK |
1203 | int ret; |
1204 | ||
1205 | ret = gen9_init_workarounds(engine); | |
1206 | if (ret) | |
1207 | return ret; | |
1208 | ||
79164509 MK |
1209 | /* WaEnableGapsTsvCreditFix:kbl */ |
1210 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | | |
1211 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
1212 | ||
b9042046 MK |
1213 | /* WaDisableDynamicCreditSharing:kbl */ |
1214 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) | |
1215 | WA_SET_BIT(GAMT_CHKN_BIT_REG, | |
1216 | GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); | |
1217 | ||
3d042d46 MK |
1218 | /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */ |
1219 | if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0)) | |
1220 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
1221 | HDC_FENCE_DEST_SLM_DISABLE); | |
1222 | ||
738fa1b3 MK |
1223 | /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes |
1224 | * involving this register should also be added to WA batch as required. | |
1225 | */ | |
1226 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0)) | |
1227 | /* WaDisableLSQCROPERFforOCL:kbl */ | |
1228 | I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | | |
1229 | GEN8_LQSC_RO_PERF_DIS); | |
1230 | ||
7b9005cd MK |
1231 | /* WaInsertDummyPushConstPs:kbl */ |
1232 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) | |
1233 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | |
1234 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1235 | ||
3af5f113 MK |
1236 | /* WaDisableGafsUnitClkGating:kbl */ |
1237 | WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); | |
1238 | ||
0a3e3f04 MK |
1239 | /* WaDisableSbeCacheDispatchPortSharing:kbl */ |
1240 | WA_SET_BIT_MASKED( | |
1241 | GEN7_HALF_SLICE_CHICKEN1, | |
1242 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
1243 | ||
738fa1b3 MK |
1244 | /* WaDisableLSQCROPERFforOCL:kbl */ |
1245 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); | |
1246 | if (ret) | |
1247 | return ret; | |
1248 | ||
68370e0a MK |
1249 | return 0; |
1250 | } | |
1251 | ||
0bc40be8 | 1252 | int init_workarounds_ring(struct intel_engine_cs *engine) |
7225342a | 1253 | { |
0bc40be8 | 1254 | struct drm_device *dev = engine->dev; |
7225342a MK |
1255 | struct drm_i915_private *dev_priv = dev->dev_private; |
1256 | ||
0bc40be8 | 1257 | WARN_ON(engine->id != RCS); |
7225342a MK |
1258 | |
1259 | dev_priv->workarounds.count = 0; | |
33136b06 | 1260 | dev_priv->workarounds.hw_whitelist_count[RCS] = 0; |
7225342a MK |
1261 | |
1262 | if (IS_BROADWELL(dev)) | |
0bc40be8 | 1263 | return bdw_init_workarounds(engine); |
7225342a MK |
1264 | |
1265 | if (IS_CHERRYVIEW(dev)) | |
0bc40be8 | 1266 | return chv_init_workarounds(engine); |
00e1e623 | 1267 | |
8d205494 | 1268 | if (IS_SKYLAKE(dev)) |
0bc40be8 | 1269 | return skl_init_workarounds(engine); |
cae0437f NH |
1270 | |
1271 | if (IS_BROXTON(dev)) | |
0bc40be8 | 1272 | return bxt_init_workarounds(engine); |
3b106531 | 1273 | |
68370e0a MK |
1274 | if (IS_KABYLAKE(dev_priv)) |
1275 | return kbl_init_workarounds(engine); | |
1276 | ||
00e1e623 VS |
1277 | return 0; |
1278 | } | |
1279 | ||
0bc40be8 | 1280 | static int init_render_ring(struct intel_engine_cs *engine) |
8187a2b7 | 1281 | { |
0bc40be8 | 1282 | struct drm_device *dev = engine->dev; |
1ec14ad3 | 1283 | struct drm_i915_private *dev_priv = dev->dev_private; |
0bc40be8 | 1284 | int ret = init_ring_common(engine); |
9c33baa6 KZ |
1285 | if (ret) |
1286 | return ret; | |
a69ffdbf | 1287 | |
61a563a2 AG |
1288 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
1289 | if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7) | |
6b26c86d | 1290 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
1291 | |
1292 | /* We need to disable the AsyncFlip performance optimisations in order | |
1293 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1294 | * programmed to '1' on all products. | |
8693a824 | 1295 | * |
2441f877 | 1296 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv |
1c8c38c5 | 1297 | */ |
2441f877 | 1298 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) |
1c8c38c5 CW |
1299 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
1300 | ||
f05bb0c7 | 1301 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 1302 | /* WaEnableFlushTlbInvalidationMode:snb */ |
f05bb0c7 CW |
1303 | if (INTEL_INFO(dev)->gen == 6) |
1304 | I915_WRITE(GFX_MODE, | |
aa83e30d | 1305 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 1306 | |
01fa0302 | 1307 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
1c8c38c5 CW |
1308 | if (IS_GEN7(dev)) |
1309 | I915_WRITE(GFX_MODE_GEN7, | |
01fa0302 | 1310 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 1311 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 1312 | |
5e13a0c5 | 1313 | if (IS_GEN6(dev)) { |
3a69ddd6 KG |
1314 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
1315 | * "If this bit is set, STCunit will have LRA as replacement | |
1316 | * policy. [...] This bit must be reset. LRA replacement | |
1317 | * policy is not supported." | |
1318 | */ | |
1319 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 1320 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
1321 | } |
1322 | ||
9cc83020 | 1323 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) |
6b26c86d | 1324 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
84f9f938 | 1325 | |
040d2baa | 1326 | if (HAS_L3_DPF(dev)) |
0bc40be8 | 1327 | I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev)); |
15b9f80e | 1328 | |
0bc40be8 | 1329 | return init_workarounds_ring(engine); |
8187a2b7 ZN |
1330 | } |
1331 | ||
0bc40be8 | 1332 | static void render_ring_cleanup(struct intel_engine_cs *engine) |
c6df541c | 1333 | { |
0bc40be8 | 1334 | struct drm_device *dev = engine->dev; |
3e78998a BW |
1335 | struct drm_i915_private *dev_priv = dev->dev_private; |
1336 | ||
1337 | if (dev_priv->semaphore_obj) { | |
1338 | i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj); | |
1339 | drm_gem_object_unreference(&dev_priv->semaphore_obj->base); | |
1340 | dev_priv->semaphore_obj = NULL; | |
1341 | } | |
b45305fc | 1342 | |
0bc40be8 | 1343 | intel_fini_pipe_control(engine); |
c6df541c CW |
1344 | } |
1345 | ||
f7169687 | 1346 | static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req, |
3e78998a BW |
1347 | unsigned int num_dwords) |
1348 | { | |
1349 | #define MBOX_UPDATE_DWORDS 8 | |
4a570db5 | 1350 | struct intel_engine_cs *signaller = signaller_req->engine; |
3e78998a BW |
1351 | struct drm_device *dev = signaller->dev; |
1352 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1353 | struct intel_engine_cs *waiter; | |
c3232b18 DG |
1354 | enum intel_engine_id id; |
1355 | int ret, num_rings; | |
3e78998a BW |
1356 | |
1357 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
1358 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; | |
1359 | #undef MBOX_UPDATE_DWORDS | |
1360 | ||
5fb9de1a | 1361 | ret = intel_ring_begin(signaller_req, num_dwords); |
3e78998a BW |
1362 | if (ret) |
1363 | return ret; | |
1364 | ||
c3232b18 | 1365 | for_each_engine_id(waiter, dev_priv, id) { |
6259cead | 1366 | u32 seqno; |
c3232b18 | 1367 | u64 gtt_offset = signaller->semaphore.signal_ggtt[id]; |
3e78998a BW |
1368 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
1369 | continue; | |
1370 | ||
f7169687 | 1371 | seqno = i915_gem_request_get_seqno(signaller_req); |
3e78998a BW |
1372 | intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6)); |
1373 | intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1374 | PIPE_CONTROL_QW_WRITE | | |
1375 | PIPE_CONTROL_FLUSH_ENABLE); | |
1376 | intel_ring_emit(signaller, lower_32_bits(gtt_offset)); | |
1377 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
6259cead | 1378 | intel_ring_emit(signaller, seqno); |
3e78998a BW |
1379 | intel_ring_emit(signaller, 0); |
1380 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | | |
83e53802 | 1381 | MI_SEMAPHORE_TARGET(waiter->hw_id)); |
3e78998a BW |
1382 | intel_ring_emit(signaller, 0); |
1383 | } | |
1384 | ||
1385 | return 0; | |
1386 | } | |
1387 | ||
f7169687 | 1388 | static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req, |
3e78998a BW |
1389 | unsigned int num_dwords) |
1390 | { | |
1391 | #define MBOX_UPDATE_DWORDS 6 | |
4a570db5 | 1392 | struct intel_engine_cs *signaller = signaller_req->engine; |
3e78998a BW |
1393 | struct drm_device *dev = signaller->dev; |
1394 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1395 | struct intel_engine_cs *waiter; | |
c3232b18 DG |
1396 | enum intel_engine_id id; |
1397 | int ret, num_rings; | |
3e78998a BW |
1398 | |
1399 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
1400 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; | |
1401 | #undef MBOX_UPDATE_DWORDS | |
1402 | ||
5fb9de1a | 1403 | ret = intel_ring_begin(signaller_req, num_dwords); |
3e78998a BW |
1404 | if (ret) |
1405 | return ret; | |
1406 | ||
c3232b18 | 1407 | for_each_engine_id(waiter, dev_priv, id) { |
6259cead | 1408 | u32 seqno; |
c3232b18 | 1409 | u64 gtt_offset = signaller->semaphore.signal_ggtt[id]; |
3e78998a BW |
1410 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
1411 | continue; | |
1412 | ||
f7169687 | 1413 | seqno = i915_gem_request_get_seqno(signaller_req); |
3e78998a BW |
1414 | intel_ring_emit(signaller, (MI_FLUSH_DW + 1) | |
1415 | MI_FLUSH_DW_OP_STOREDW); | |
1416 | intel_ring_emit(signaller, lower_32_bits(gtt_offset) | | |
1417 | MI_FLUSH_DW_USE_GTT); | |
1418 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
6259cead | 1419 | intel_ring_emit(signaller, seqno); |
3e78998a | 1420 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | |
83e53802 | 1421 | MI_SEMAPHORE_TARGET(waiter->hw_id)); |
3e78998a BW |
1422 | intel_ring_emit(signaller, 0); |
1423 | } | |
1424 | ||
1425 | return 0; | |
1426 | } | |
1427 | ||
f7169687 | 1428 | static int gen6_signal(struct drm_i915_gem_request *signaller_req, |
024a43e1 | 1429 | unsigned int num_dwords) |
1ec14ad3 | 1430 | { |
4a570db5 | 1431 | struct intel_engine_cs *signaller = signaller_req->engine; |
024a43e1 BW |
1432 | struct drm_device *dev = signaller->dev; |
1433 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 1434 | struct intel_engine_cs *useless; |
c3232b18 DG |
1435 | enum intel_engine_id id; |
1436 | int ret, num_rings; | |
78325f2d | 1437 | |
a1444b79 BW |
1438 | #define MBOX_UPDATE_DWORDS 3 |
1439 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
1440 | num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2); | |
1441 | #undef MBOX_UPDATE_DWORDS | |
024a43e1 | 1442 | |
5fb9de1a | 1443 | ret = intel_ring_begin(signaller_req, num_dwords); |
024a43e1 BW |
1444 | if (ret) |
1445 | return ret; | |
024a43e1 | 1446 | |
c3232b18 DG |
1447 | for_each_engine_id(useless, dev_priv, id) { |
1448 | i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[id]; | |
f0f59a00 VS |
1449 | |
1450 | if (i915_mmio_reg_valid(mbox_reg)) { | |
f7169687 | 1451 | u32 seqno = i915_gem_request_get_seqno(signaller_req); |
f0f59a00 | 1452 | |
78325f2d | 1453 | intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1)); |
f92a9162 | 1454 | intel_ring_emit_reg(signaller, mbox_reg); |
6259cead | 1455 | intel_ring_emit(signaller, seqno); |
78325f2d BW |
1456 | } |
1457 | } | |
024a43e1 | 1458 | |
a1444b79 BW |
1459 | /* If num_dwords was rounded, make sure the tail pointer is correct */ |
1460 | if (num_rings % 2 == 0) | |
1461 | intel_ring_emit(signaller, MI_NOOP); | |
1462 | ||
024a43e1 | 1463 | return 0; |
1ec14ad3 CW |
1464 | } |
1465 | ||
c8c99b0f BW |
1466 | /** |
1467 | * gen6_add_request - Update the semaphore mailbox registers | |
ee044a88 JH |
1468 | * |
1469 | * @request - request to write to the ring | |
c8c99b0f BW |
1470 | * |
1471 | * Update the mailbox registers in the *other* rings with the current seqno. | |
1472 | * This acts like a signal in the canonical semaphore. | |
1473 | */ | |
1ec14ad3 | 1474 | static int |
ee044a88 | 1475 | gen6_add_request(struct drm_i915_gem_request *req) |
1ec14ad3 | 1476 | { |
4a570db5 | 1477 | struct intel_engine_cs *engine = req->engine; |
024a43e1 | 1478 | int ret; |
52ed2325 | 1479 | |
e2f80391 TU |
1480 | if (engine->semaphore.signal) |
1481 | ret = engine->semaphore.signal(req, 4); | |
707d9cf9 | 1482 | else |
5fb9de1a | 1483 | ret = intel_ring_begin(req, 4); |
707d9cf9 | 1484 | |
1ec14ad3 CW |
1485 | if (ret) |
1486 | return ret; | |
1487 | ||
e2f80391 TU |
1488 | intel_ring_emit(engine, MI_STORE_DWORD_INDEX); |
1489 | intel_ring_emit(engine, | |
1490 | I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1491 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); | |
1492 | intel_ring_emit(engine, MI_USER_INTERRUPT); | |
1493 | __intel_ring_advance(engine); | |
1ec14ad3 | 1494 | |
1ec14ad3 CW |
1495 | return 0; |
1496 | } | |
1497 | ||
f72b3435 MK |
1498 | static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, |
1499 | u32 seqno) | |
1500 | { | |
1501 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1502 | return dev_priv->last_seqno < seqno; | |
1503 | } | |
1504 | ||
c8c99b0f BW |
1505 | /** |
1506 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
1507 | * | |
1508 | * @waiter - ring that is waiting | |
1509 | * @signaller - ring which has, or will signal | |
1510 | * @seqno - seqno which the waiter will block on | |
1511 | */ | |
5ee426ca BW |
1512 | |
1513 | static int | |
599d924c | 1514 | gen8_ring_sync(struct drm_i915_gem_request *waiter_req, |
5ee426ca BW |
1515 | struct intel_engine_cs *signaller, |
1516 | u32 seqno) | |
1517 | { | |
4a570db5 | 1518 | struct intel_engine_cs *waiter = waiter_req->engine; |
5ee426ca BW |
1519 | struct drm_i915_private *dev_priv = waiter->dev->dev_private; |
1520 | int ret; | |
1521 | ||
5fb9de1a | 1522 | ret = intel_ring_begin(waiter_req, 4); |
5ee426ca BW |
1523 | if (ret) |
1524 | return ret; | |
1525 | ||
1526 | intel_ring_emit(waiter, MI_SEMAPHORE_WAIT | | |
1527 | MI_SEMAPHORE_GLOBAL_GTT | | |
bae4fcd2 | 1528 | MI_SEMAPHORE_POLL | |
5ee426ca BW |
1529 | MI_SEMAPHORE_SAD_GTE_SDD); |
1530 | intel_ring_emit(waiter, seqno); | |
1531 | intel_ring_emit(waiter, | |
1532 | lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); | |
1533 | intel_ring_emit(waiter, | |
1534 | upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); | |
1535 | intel_ring_advance(waiter); | |
1536 | return 0; | |
1537 | } | |
1538 | ||
c8c99b0f | 1539 | static int |
599d924c | 1540 | gen6_ring_sync(struct drm_i915_gem_request *waiter_req, |
a4872ba6 | 1541 | struct intel_engine_cs *signaller, |
686cb5f9 | 1542 | u32 seqno) |
1ec14ad3 | 1543 | { |
4a570db5 | 1544 | struct intel_engine_cs *waiter = waiter_req->engine; |
c8c99b0f BW |
1545 | u32 dw1 = MI_SEMAPHORE_MBOX | |
1546 | MI_SEMAPHORE_COMPARE | | |
1547 | MI_SEMAPHORE_REGISTER; | |
ebc348b2 BW |
1548 | u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id]; |
1549 | int ret; | |
1ec14ad3 | 1550 | |
1500f7ea BW |
1551 | /* Throughout all of the GEM code, seqno passed implies our current |
1552 | * seqno is >= the last seqno executed. However for hardware the | |
1553 | * comparison is strictly greater than. | |
1554 | */ | |
1555 | seqno -= 1; | |
1556 | ||
ebc348b2 | 1557 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
686cb5f9 | 1558 | |
5fb9de1a | 1559 | ret = intel_ring_begin(waiter_req, 4); |
1ec14ad3 CW |
1560 | if (ret) |
1561 | return ret; | |
1562 | ||
f72b3435 MK |
1563 | /* If seqno wrap happened, omit the wait with no-ops */ |
1564 | if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) { | |
ebc348b2 | 1565 | intel_ring_emit(waiter, dw1 | wait_mbox); |
f72b3435 MK |
1566 | intel_ring_emit(waiter, seqno); |
1567 | intel_ring_emit(waiter, 0); | |
1568 | intel_ring_emit(waiter, MI_NOOP); | |
1569 | } else { | |
1570 | intel_ring_emit(waiter, MI_NOOP); | |
1571 | intel_ring_emit(waiter, MI_NOOP); | |
1572 | intel_ring_emit(waiter, MI_NOOP); | |
1573 | intel_ring_emit(waiter, MI_NOOP); | |
1574 | } | |
c8c99b0f | 1575 | intel_ring_advance(waiter); |
1ec14ad3 CW |
1576 | |
1577 | return 0; | |
1578 | } | |
1579 | ||
c6df541c CW |
1580 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
1581 | do { \ | |
fcbc34e4 KG |
1582 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
1583 | PIPE_CONTROL_DEPTH_STALL); \ | |
c6df541c CW |
1584 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
1585 | intel_ring_emit(ring__, 0); \ | |
1586 | intel_ring_emit(ring__, 0); \ | |
1587 | } while (0) | |
1588 | ||
1589 | static int | |
ee044a88 | 1590 | pc_render_add_request(struct drm_i915_gem_request *req) |
c6df541c | 1591 | { |
4a570db5 | 1592 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 1593 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
c6df541c CW |
1594 | int ret; |
1595 | ||
1596 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently | |
1597 | * incoherent with writes to memory, i.e. completely fubar, | |
1598 | * so we need to use PIPE_NOTIFY instead. | |
1599 | * | |
1600 | * However, we also need to workaround the qword write | |
1601 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to | |
1602 | * memory before requesting an interrupt. | |
1603 | */ | |
5fb9de1a | 1604 | ret = intel_ring_begin(req, 32); |
c6df541c CW |
1605 | if (ret) |
1606 | return ret; | |
1607 | ||
e2f80391 TU |
1608 | intel_ring_emit(engine, |
1609 | GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | | |
9d971b37 KG |
1610 | PIPE_CONTROL_WRITE_FLUSH | |
1611 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); | |
e2f80391 TU |
1612 | intel_ring_emit(engine, |
1613 | engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); | |
1614 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); | |
1615 | intel_ring_emit(engine, 0); | |
1616 | PIPE_CONTROL_FLUSH(engine, scratch_addr); | |
18393f63 | 1617 | scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */ |
e2f80391 | 1618 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
18393f63 | 1619 | scratch_addr += 2 * CACHELINE_BYTES; |
e2f80391 | 1620 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
18393f63 | 1621 | scratch_addr += 2 * CACHELINE_BYTES; |
e2f80391 | 1622 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
18393f63 | 1623 | scratch_addr += 2 * CACHELINE_BYTES; |
e2f80391 | 1624 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
18393f63 | 1625 | scratch_addr += 2 * CACHELINE_BYTES; |
e2f80391 | 1626 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
a71d8d94 | 1627 | |
e2f80391 TU |
1628 | intel_ring_emit(engine, |
1629 | GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | | |
9d971b37 KG |
1630 | PIPE_CONTROL_WRITE_FLUSH | |
1631 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | | |
c6df541c | 1632 | PIPE_CONTROL_NOTIFY); |
e2f80391 TU |
1633 | intel_ring_emit(engine, |
1634 | engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); | |
1635 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); | |
1636 | intel_ring_emit(engine, 0); | |
1637 | __intel_ring_advance(engine); | |
c6df541c | 1638 | |
c6df541c CW |
1639 | return 0; |
1640 | } | |
1641 | ||
c04e0f3b CW |
1642 | static void |
1643 | gen6_seqno_barrier(struct intel_engine_cs *engine) | |
4cd53c0c | 1644 | { |
e32da7ad CW |
1645 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
1646 | ||
4cd53c0c DV |
1647 | /* Workaround to force correct ordering between irq and seqno writes on |
1648 | * ivb (and maybe also on snb) by reading from a CS register (like | |
9b9ed309 CW |
1649 | * ACTHD) before reading the status page. |
1650 | * | |
1651 | * Note that this effectively stalls the read by the time it takes to | |
1652 | * do a memory transaction, which more or less ensures that the write | |
1653 | * from the GPU has sufficient time to invalidate the CPU cacheline. | |
1654 | * Alternatively we could delay the interrupt from the CS ring to give | |
1655 | * the write time to land, but that would incur a delay after every | |
1656 | * batch i.e. much more frequent than a delay when waiting for the | |
1657 | * interrupt (with the same net latency). | |
e32da7ad CW |
1658 | * |
1659 | * Also note that to prevent whole machine hangs on gen7, we have to | |
1660 | * take the spinlock to guard against concurrent cacheline access. | |
9b9ed309 | 1661 | */ |
e32da7ad | 1662 | spin_lock_irq(&dev_priv->uncore.lock); |
c04e0f3b | 1663 | POSTING_READ_FW(RING_ACTHD(engine->mmio_base)); |
e32da7ad | 1664 | spin_unlock_irq(&dev_priv->uncore.lock); |
4cd53c0c DV |
1665 | } |
1666 | ||
8187a2b7 | 1667 | static u32 |
c04e0f3b | 1668 | ring_get_seqno(struct intel_engine_cs *engine) |
8187a2b7 | 1669 | { |
0bc40be8 | 1670 | return intel_read_status_page(engine, I915_GEM_HWS_INDEX); |
1ec14ad3 CW |
1671 | } |
1672 | ||
b70ec5bf | 1673 | static void |
0bc40be8 | 1674 | ring_set_seqno(struct intel_engine_cs *engine, u32 seqno) |
b70ec5bf | 1675 | { |
0bc40be8 | 1676 | intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno); |
b70ec5bf MK |
1677 | } |
1678 | ||
c6df541c | 1679 | static u32 |
c04e0f3b | 1680 | pc_render_get_seqno(struct intel_engine_cs *engine) |
c6df541c | 1681 | { |
0bc40be8 | 1682 | return engine->scratch.cpu_page[0]; |
c6df541c CW |
1683 | } |
1684 | ||
b70ec5bf | 1685 | static void |
0bc40be8 | 1686 | pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno) |
b70ec5bf | 1687 | { |
0bc40be8 | 1688 | engine->scratch.cpu_page[0] = seqno; |
b70ec5bf MK |
1689 | } |
1690 | ||
e48d8634 | 1691 | static bool |
0bc40be8 | 1692 | gen5_ring_get_irq(struct intel_engine_cs *engine) |
e48d8634 | 1693 | { |
0bc40be8 | 1694 | struct drm_device *dev = engine->dev; |
4640c4ff | 1695 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1696 | unsigned long flags; |
e48d8634 | 1697 | |
7cd512f1 | 1698 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
e48d8634 DV |
1699 | return false; |
1700 | ||
7338aefa | 1701 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1702 | if (engine->irq_refcount++ == 0) |
1703 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); | |
7338aefa | 1704 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
1705 | |
1706 | return true; | |
1707 | } | |
1708 | ||
1709 | static void | |
0bc40be8 | 1710 | gen5_ring_put_irq(struct intel_engine_cs *engine) |
e48d8634 | 1711 | { |
0bc40be8 | 1712 | struct drm_device *dev = engine->dev; |
4640c4ff | 1713 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1714 | unsigned long flags; |
e48d8634 | 1715 | |
7338aefa | 1716 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1717 | if (--engine->irq_refcount == 0) |
1718 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); | |
7338aefa | 1719 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
1720 | } |
1721 | ||
b13c2b96 | 1722 | static bool |
0bc40be8 | 1723 | i9xx_ring_get_irq(struct intel_engine_cs *engine) |
62fdfeaf | 1724 | { |
0bc40be8 | 1725 | struct drm_device *dev = engine->dev; |
4640c4ff | 1726 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1727 | unsigned long flags; |
62fdfeaf | 1728 | |
7cd512f1 | 1729 | if (!intel_irqs_enabled(dev_priv)) |
b13c2b96 CW |
1730 | return false; |
1731 | ||
7338aefa | 1732 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1733 | if (engine->irq_refcount++ == 0) { |
1734 | dev_priv->irq_mask &= ~engine->irq_enable_mask; | |
f637fde4 DV |
1735 | I915_WRITE(IMR, dev_priv->irq_mask); |
1736 | POSTING_READ(IMR); | |
1737 | } | |
7338aefa | 1738 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
b13c2b96 CW |
1739 | |
1740 | return true; | |
62fdfeaf EA |
1741 | } |
1742 | ||
8187a2b7 | 1743 | static void |
0bc40be8 | 1744 | i9xx_ring_put_irq(struct intel_engine_cs *engine) |
62fdfeaf | 1745 | { |
0bc40be8 | 1746 | struct drm_device *dev = engine->dev; |
4640c4ff | 1747 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1748 | unsigned long flags; |
62fdfeaf | 1749 | |
7338aefa | 1750 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1751 | if (--engine->irq_refcount == 0) { |
1752 | dev_priv->irq_mask |= engine->irq_enable_mask; | |
f637fde4 DV |
1753 | I915_WRITE(IMR, dev_priv->irq_mask); |
1754 | POSTING_READ(IMR); | |
1755 | } | |
7338aefa | 1756 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
62fdfeaf EA |
1757 | } |
1758 | ||
c2798b19 | 1759 | static bool |
0bc40be8 | 1760 | i8xx_ring_get_irq(struct intel_engine_cs *engine) |
c2798b19 | 1761 | { |
0bc40be8 | 1762 | struct drm_device *dev = engine->dev; |
4640c4ff | 1763 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1764 | unsigned long flags; |
c2798b19 | 1765 | |
7cd512f1 | 1766 | if (!intel_irqs_enabled(dev_priv)) |
c2798b19 CW |
1767 | return false; |
1768 | ||
7338aefa | 1769 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1770 | if (engine->irq_refcount++ == 0) { |
1771 | dev_priv->irq_mask &= ~engine->irq_enable_mask; | |
c2798b19 CW |
1772 | I915_WRITE16(IMR, dev_priv->irq_mask); |
1773 | POSTING_READ16(IMR); | |
1774 | } | |
7338aefa | 1775 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
1776 | |
1777 | return true; | |
1778 | } | |
1779 | ||
1780 | static void | |
0bc40be8 | 1781 | i8xx_ring_put_irq(struct intel_engine_cs *engine) |
c2798b19 | 1782 | { |
0bc40be8 | 1783 | struct drm_device *dev = engine->dev; |
4640c4ff | 1784 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1785 | unsigned long flags; |
c2798b19 | 1786 | |
7338aefa | 1787 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1788 | if (--engine->irq_refcount == 0) { |
1789 | dev_priv->irq_mask |= engine->irq_enable_mask; | |
c2798b19 CW |
1790 | I915_WRITE16(IMR, dev_priv->irq_mask); |
1791 | POSTING_READ16(IMR); | |
1792 | } | |
7338aefa | 1793 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
1794 | } |
1795 | ||
b72f3acb | 1796 | static int |
a84c3ae1 | 1797 | bsd_ring_flush(struct drm_i915_gem_request *req, |
78501eac CW |
1798 | u32 invalidate_domains, |
1799 | u32 flush_domains) | |
d1b851fc | 1800 | { |
4a570db5 | 1801 | struct intel_engine_cs *engine = req->engine; |
b72f3acb CW |
1802 | int ret; |
1803 | ||
5fb9de1a | 1804 | ret = intel_ring_begin(req, 2); |
b72f3acb CW |
1805 | if (ret) |
1806 | return ret; | |
1807 | ||
e2f80391 TU |
1808 | intel_ring_emit(engine, MI_FLUSH); |
1809 | intel_ring_emit(engine, MI_NOOP); | |
1810 | intel_ring_advance(engine); | |
b72f3acb | 1811 | return 0; |
d1b851fc ZN |
1812 | } |
1813 | ||
3cce469c | 1814 | static int |
ee044a88 | 1815 | i9xx_add_request(struct drm_i915_gem_request *req) |
d1b851fc | 1816 | { |
4a570db5 | 1817 | struct intel_engine_cs *engine = req->engine; |
3cce469c CW |
1818 | int ret; |
1819 | ||
5fb9de1a | 1820 | ret = intel_ring_begin(req, 4); |
3cce469c CW |
1821 | if (ret) |
1822 | return ret; | |
6f392d54 | 1823 | |
e2f80391 TU |
1824 | intel_ring_emit(engine, MI_STORE_DWORD_INDEX); |
1825 | intel_ring_emit(engine, | |
1826 | I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1827 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); | |
1828 | intel_ring_emit(engine, MI_USER_INTERRUPT); | |
1829 | __intel_ring_advance(engine); | |
d1b851fc | 1830 | |
3cce469c | 1831 | return 0; |
d1b851fc ZN |
1832 | } |
1833 | ||
0f46832f | 1834 | static bool |
0bc40be8 | 1835 | gen6_ring_get_irq(struct intel_engine_cs *engine) |
0f46832f | 1836 | { |
0bc40be8 | 1837 | struct drm_device *dev = engine->dev; |
4640c4ff | 1838 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1839 | unsigned long flags; |
0f46832f | 1840 | |
7cd512f1 DV |
1841 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
1842 | return false; | |
0f46832f | 1843 | |
7338aefa | 1844 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1845 | if (engine->irq_refcount++ == 0) { |
1846 | if (HAS_L3_DPF(dev) && engine->id == RCS) | |
1847 | I915_WRITE_IMR(engine, | |
1848 | ~(engine->irq_enable_mask | | |
35a85ac6 | 1849 | GT_PARITY_ERROR(dev))); |
15b9f80e | 1850 | else |
0bc40be8 TU |
1851 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
1852 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); | |
0f46832f | 1853 | } |
7338aefa | 1854 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
0f46832f CW |
1855 | |
1856 | return true; | |
1857 | } | |
1858 | ||
1859 | static void | |
0bc40be8 | 1860 | gen6_ring_put_irq(struct intel_engine_cs *engine) |
0f46832f | 1861 | { |
0bc40be8 | 1862 | struct drm_device *dev = engine->dev; |
4640c4ff | 1863 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1864 | unsigned long flags; |
0f46832f | 1865 | |
7338aefa | 1866 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1867 | if (--engine->irq_refcount == 0) { |
1868 | if (HAS_L3_DPF(dev) && engine->id == RCS) | |
1869 | I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev)); | |
15b9f80e | 1870 | else |
0bc40be8 TU |
1871 | I915_WRITE_IMR(engine, ~0); |
1872 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); | |
1ec14ad3 | 1873 | } |
7338aefa | 1874 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
d1b851fc ZN |
1875 | } |
1876 | ||
a19d2933 | 1877 | static bool |
0bc40be8 | 1878 | hsw_vebox_get_irq(struct intel_engine_cs *engine) |
a19d2933 | 1879 | { |
0bc40be8 | 1880 | struct drm_device *dev = engine->dev; |
a19d2933 BW |
1881 | struct drm_i915_private *dev_priv = dev->dev_private; |
1882 | unsigned long flags; | |
1883 | ||
7cd512f1 | 1884 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
a19d2933 BW |
1885 | return false; |
1886 | ||
59cdb63d | 1887 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1888 | if (engine->irq_refcount++ == 0) { |
1889 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); | |
1890 | gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask); | |
a19d2933 | 1891 | } |
59cdb63d | 1892 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1893 | |
1894 | return true; | |
1895 | } | |
1896 | ||
1897 | static void | |
0bc40be8 | 1898 | hsw_vebox_put_irq(struct intel_engine_cs *engine) |
a19d2933 | 1899 | { |
0bc40be8 | 1900 | struct drm_device *dev = engine->dev; |
a19d2933 BW |
1901 | struct drm_i915_private *dev_priv = dev->dev_private; |
1902 | unsigned long flags; | |
1903 | ||
59cdb63d | 1904 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1905 | if (--engine->irq_refcount == 0) { |
1906 | I915_WRITE_IMR(engine, ~0); | |
1907 | gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask); | |
a19d2933 | 1908 | } |
59cdb63d | 1909 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1910 | } |
1911 | ||
abd58f01 | 1912 | static bool |
0bc40be8 | 1913 | gen8_ring_get_irq(struct intel_engine_cs *engine) |
abd58f01 | 1914 | { |
0bc40be8 | 1915 | struct drm_device *dev = engine->dev; |
abd58f01 BW |
1916 | struct drm_i915_private *dev_priv = dev->dev_private; |
1917 | unsigned long flags; | |
1918 | ||
7cd512f1 | 1919 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
abd58f01 BW |
1920 | return false; |
1921 | ||
1922 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
0bc40be8 TU |
1923 | if (engine->irq_refcount++ == 0) { |
1924 | if (HAS_L3_DPF(dev) && engine->id == RCS) { | |
1925 | I915_WRITE_IMR(engine, | |
1926 | ~(engine->irq_enable_mask | | |
abd58f01 BW |
1927 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); |
1928 | } else { | |
0bc40be8 | 1929 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
abd58f01 | 1930 | } |
0bc40be8 | 1931 | POSTING_READ(RING_IMR(engine->mmio_base)); |
abd58f01 BW |
1932 | } |
1933 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1934 | ||
1935 | return true; | |
1936 | } | |
1937 | ||
1938 | static void | |
0bc40be8 | 1939 | gen8_ring_put_irq(struct intel_engine_cs *engine) |
abd58f01 | 1940 | { |
0bc40be8 | 1941 | struct drm_device *dev = engine->dev; |
abd58f01 BW |
1942 | struct drm_i915_private *dev_priv = dev->dev_private; |
1943 | unsigned long flags; | |
1944 | ||
1945 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
0bc40be8 TU |
1946 | if (--engine->irq_refcount == 0) { |
1947 | if (HAS_L3_DPF(dev) && engine->id == RCS) { | |
1948 | I915_WRITE_IMR(engine, | |
abd58f01 BW |
1949 | ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); |
1950 | } else { | |
0bc40be8 | 1951 | I915_WRITE_IMR(engine, ~0); |
abd58f01 | 1952 | } |
0bc40be8 | 1953 | POSTING_READ(RING_IMR(engine->mmio_base)); |
abd58f01 BW |
1954 | } |
1955 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1956 | } | |
1957 | ||
d1b851fc | 1958 | static int |
53fddaf7 | 1959 | i965_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 1960 | u64 offset, u32 length, |
8e004efc | 1961 | unsigned dispatch_flags) |
d1b851fc | 1962 | { |
4a570db5 | 1963 | struct intel_engine_cs *engine = req->engine; |
e1f99ce6 | 1964 | int ret; |
78501eac | 1965 | |
5fb9de1a | 1966 | ret = intel_ring_begin(req, 2); |
e1f99ce6 CW |
1967 | if (ret) |
1968 | return ret; | |
1969 | ||
e2f80391 | 1970 | intel_ring_emit(engine, |
65f56876 CW |
1971 | MI_BATCH_BUFFER_START | |
1972 | MI_BATCH_GTT | | |
8e004efc JH |
1973 | (dispatch_flags & I915_DISPATCH_SECURE ? |
1974 | 0 : MI_BATCH_NON_SECURE_I965)); | |
e2f80391 TU |
1975 | intel_ring_emit(engine, offset); |
1976 | intel_ring_advance(engine); | |
78501eac | 1977 | |
d1b851fc ZN |
1978 | return 0; |
1979 | } | |
1980 | ||
b45305fc DV |
1981 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1982 | #define I830_BATCH_LIMIT (256*1024) | |
c4d69da1 CW |
1983 | #define I830_TLB_ENTRIES (2) |
1984 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) | |
8187a2b7 | 1985 | static int |
53fddaf7 | 1986 | i830_dispatch_execbuffer(struct drm_i915_gem_request *req, |
8e004efc JH |
1987 | u64 offset, u32 len, |
1988 | unsigned dispatch_flags) | |
62fdfeaf | 1989 | { |
4a570db5 | 1990 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 1991 | u32 cs_offset = engine->scratch.gtt_offset; |
c4e7a414 | 1992 | int ret; |
62fdfeaf | 1993 | |
5fb9de1a | 1994 | ret = intel_ring_begin(req, 6); |
c4d69da1 CW |
1995 | if (ret) |
1996 | return ret; | |
62fdfeaf | 1997 | |
c4d69da1 | 1998 | /* Evict the invalid PTE TLBs */ |
e2f80391 TU |
1999 | intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA); |
2000 | intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096); | |
2001 | intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */ | |
2002 | intel_ring_emit(engine, cs_offset); | |
2003 | intel_ring_emit(engine, 0xdeadbeef); | |
2004 | intel_ring_emit(engine, MI_NOOP); | |
2005 | intel_ring_advance(engine); | |
b45305fc | 2006 | |
8e004efc | 2007 | if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { |
b45305fc DV |
2008 | if (len > I830_BATCH_LIMIT) |
2009 | return -ENOSPC; | |
2010 | ||
5fb9de1a | 2011 | ret = intel_ring_begin(req, 6 + 2); |
b45305fc DV |
2012 | if (ret) |
2013 | return ret; | |
c4d69da1 CW |
2014 | |
2015 | /* Blit the batch (which has now all relocs applied) to the | |
2016 | * stable batch scratch bo area (so that the CS never | |
2017 | * stumbles over its tlb invalidation bug) ... | |
2018 | */ | |
e2f80391 TU |
2019 | intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA); |
2020 | intel_ring_emit(engine, | |
2021 | BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096); | |
2022 | intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096); | |
2023 | intel_ring_emit(engine, cs_offset); | |
2024 | intel_ring_emit(engine, 4096); | |
2025 | intel_ring_emit(engine, offset); | |
2026 | ||
2027 | intel_ring_emit(engine, MI_FLUSH); | |
2028 | intel_ring_emit(engine, MI_NOOP); | |
2029 | intel_ring_advance(engine); | |
b45305fc DV |
2030 | |
2031 | /* ... and execute it. */ | |
c4d69da1 | 2032 | offset = cs_offset; |
b45305fc | 2033 | } |
e1f99ce6 | 2034 | |
9d611c03 | 2035 | ret = intel_ring_begin(req, 2); |
c4d69da1 CW |
2036 | if (ret) |
2037 | return ret; | |
2038 | ||
e2f80391 TU |
2039 | intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
2040 | intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ? | |
2041 | 0 : MI_BATCH_NON_SECURE)); | |
2042 | intel_ring_advance(engine); | |
c4d69da1 | 2043 | |
fb3256da DV |
2044 | return 0; |
2045 | } | |
2046 | ||
2047 | static int | |
53fddaf7 | 2048 | i915_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 2049 | u64 offset, u32 len, |
8e004efc | 2050 | unsigned dispatch_flags) |
fb3256da | 2051 | { |
4a570db5 | 2052 | struct intel_engine_cs *engine = req->engine; |
fb3256da DV |
2053 | int ret; |
2054 | ||
5fb9de1a | 2055 | ret = intel_ring_begin(req, 2); |
fb3256da DV |
2056 | if (ret) |
2057 | return ret; | |
2058 | ||
e2f80391 TU |
2059 | intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
2060 | intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ? | |
2061 | 0 : MI_BATCH_NON_SECURE)); | |
2062 | intel_ring_advance(engine); | |
62fdfeaf | 2063 | |
62fdfeaf EA |
2064 | return 0; |
2065 | } | |
2066 | ||
0bc40be8 | 2067 | static void cleanup_phys_status_page(struct intel_engine_cs *engine) |
7d3fdfff | 2068 | { |
0bc40be8 | 2069 | struct drm_i915_private *dev_priv = to_i915(engine->dev); |
7d3fdfff VS |
2070 | |
2071 | if (!dev_priv->status_page_dmah) | |
2072 | return; | |
2073 | ||
0bc40be8 TU |
2074 | drm_pci_free(engine->dev, dev_priv->status_page_dmah); |
2075 | engine->status_page.page_addr = NULL; | |
7d3fdfff VS |
2076 | } |
2077 | ||
0bc40be8 | 2078 | static void cleanup_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 2079 | { |
05394f39 | 2080 | struct drm_i915_gem_object *obj; |
62fdfeaf | 2081 | |
0bc40be8 | 2082 | obj = engine->status_page.obj; |
8187a2b7 | 2083 | if (obj == NULL) |
62fdfeaf | 2084 | return; |
62fdfeaf | 2085 | |
9da3da66 | 2086 | kunmap(sg_page(obj->pages->sgl)); |
d7f46fc4 | 2087 | i915_gem_object_ggtt_unpin(obj); |
05394f39 | 2088 | drm_gem_object_unreference(&obj->base); |
0bc40be8 | 2089 | engine->status_page.obj = NULL; |
62fdfeaf EA |
2090 | } |
2091 | ||
0bc40be8 | 2092 | static int init_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 2093 | { |
0bc40be8 | 2094 | struct drm_i915_gem_object *obj = engine->status_page.obj; |
62fdfeaf | 2095 | |
7d3fdfff | 2096 | if (obj == NULL) { |
1f767e02 | 2097 | unsigned flags; |
e3efda49 | 2098 | int ret; |
e4ffd173 | 2099 | |
0bc40be8 | 2100 | obj = i915_gem_alloc_object(engine->dev, 4096); |
e3efda49 CW |
2101 | if (obj == NULL) { |
2102 | DRM_ERROR("Failed to allocate status page\n"); | |
2103 | return -ENOMEM; | |
2104 | } | |
62fdfeaf | 2105 | |
e3efda49 CW |
2106 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
2107 | if (ret) | |
2108 | goto err_unref; | |
2109 | ||
1f767e02 | 2110 | flags = 0; |
0bc40be8 | 2111 | if (!HAS_LLC(engine->dev)) |
1f767e02 CW |
2112 | /* On g33, we cannot place HWS above 256MiB, so |
2113 | * restrict its pinning to the low mappable arena. | |
2114 | * Though this restriction is not documented for | |
2115 | * gen4, gen5, or byt, they also behave similarly | |
2116 | * and hang if the HWS is placed at the top of the | |
2117 | * GTT. To generalise, it appears that all !llc | |
2118 | * platforms have issues with us placing the HWS | |
2119 | * above the mappable region (even though we never | |
2120 | * actualy map it). | |
2121 | */ | |
2122 | flags |= PIN_MAPPABLE; | |
2123 | ret = i915_gem_obj_ggtt_pin(obj, 4096, flags); | |
e3efda49 CW |
2124 | if (ret) { |
2125 | err_unref: | |
2126 | drm_gem_object_unreference(&obj->base); | |
2127 | return ret; | |
2128 | } | |
2129 | ||
0bc40be8 | 2130 | engine->status_page.obj = obj; |
e3efda49 | 2131 | } |
62fdfeaf | 2132 | |
0bc40be8 TU |
2133 | engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
2134 | engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); | |
2135 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); | |
62fdfeaf | 2136 | |
8187a2b7 | 2137 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
0bc40be8 | 2138 | engine->name, engine->status_page.gfx_addr); |
62fdfeaf EA |
2139 | |
2140 | return 0; | |
62fdfeaf EA |
2141 | } |
2142 | ||
0bc40be8 | 2143 | static int init_phys_status_page(struct intel_engine_cs *engine) |
6b8294a4 | 2144 | { |
0bc40be8 | 2145 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
6b8294a4 CW |
2146 | |
2147 | if (!dev_priv->status_page_dmah) { | |
2148 | dev_priv->status_page_dmah = | |
0bc40be8 | 2149 | drm_pci_alloc(engine->dev, PAGE_SIZE, PAGE_SIZE); |
6b8294a4 CW |
2150 | if (!dev_priv->status_page_dmah) |
2151 | return -ENOMEM; | |
2152 | } | |
2153 | ||
0bc40be8 TU |
2154 | engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
2155 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); | |
6b8294a4 CW |
2156 | |
2157 | return 0; | |
2158 | } | |
2159 | ||
7ba717cf | 2160 | void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
2919d291 | 2161 | { |
def0c5f6 | 2162 | if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen) |
0a798eb9 | 2163 | i915_gem_object_unpin_map(ringbuf->obj); |
def0c5f6 CW |
2164 | else |
2165 | iounmap(ringbuf->virtual_start); | |
8305216f | 2166 | ringbuf->virtual_start = NULL; |
0eb973d3 | 2167 | ringbuf->vma = NULL; |
2919d291 | 2168 | i915_gem_object_ggtt_unpin(ringbuf->obj); |
7ba717cf TD |
2169 | } |
2170 | ||
2171 | int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev, | |
2172 | struct intel_ringbuffer *ringbuf) | |
2173 | { | |
2174 | struct drm_i915_private *dev_priv = to_i915(dev); | |
72e96d64 | 2175 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
7ba717cf | 2176 | struct drm_i915_gem_object *obj = ringbuf->obj; |
a687a43a CW |
2177 | /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ |
2178 | unsigned flags = PIN_OFFSET_BIAS | 4096; | |
8305216f | 2179 | void *addr; |
7ba717cf TD |
2180 | int ret; |
2181 | ||
def0c5f6 | 2182 | if (HAS_LLC(dev_priv) && !obj->stolen) { |
a687a43a | 2183 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags); |
def0c5f6 CW |
2184 | if (ret) |
2185 | return ret; | |
7ba717cf | 2186 | |
def0c5f6 | 2187 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
d2cad535 CW |
2188 | if (ret) |
2189 | goto err_unpin; | |
def0c5f6 | 2190 | |
8305216f DG |
2191 | addr = i915_gem_object_pin_map(obj); |
2192 | if (IS_ERR(addr)) { | |
2193 | ret = PTR_ERR(addr); | |
d2cad535 | 2194 | goto err_unpin; |
def0c5f6 CW |
2195 | } |
2196 | } else { | |
a687a43a CW |
2197 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, |
2198 | flags | PIN_MAPPABLE); | |
def0c5f6 CW |
2199 | if (ret) |
2200 | return ret; | |
7ba717cf | 2201 | |
def0c5f6 | 2202 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
d2cad535 CW |
2203 | if (ret) |
2204 | goto err_unpin; | |
def0c5f6 | 2205 | |
ff3dc087 DCS |
2206 | /* Access through the GTT requires the device to be awake. */ |
2207 | assert_rpm_wakelock_held(dev_priv); | |
2208 | ||
8305216f DG |
2209 | addr = ioremap_wc(ggtt->mappable_base + |
2210 | i915_gem_obj_ggtt_offset(obj), ringbuf->size); | |
2211 | if (addr == NULL) { | |
d2cad535 CW |
2212 | ret = -ENOMEM; |
2213 | goto err_unpin; | |
def0c5f6 | 2214 | } |
7ba717cf TD |
2215 | } |
2216 | ||
8305216f | 2217 | ringbuf->virtual_start = addr; |
0eb973d3 | 2218 | ringbuf->vma = i915_gem_obj_to_ggtt(obj); |
7ba717cf | 2219 | return 0; |
d2cad535 CW |
2220 | |
2221 | err_unpin: | |
2222 | i915_gem_object_ggtt_unpin(obj); | |
2223 | return ret; | |
7ba717cf TD |
2224 | } |
2225 | ||
01101fa7 | 2226 | static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
7ba717cf | 2227 | { |
2919d291 OM |
2228 | drm_gem_object_unreference(&ringbuf->obj->base); |
2229 | ringbuf->obj = NULL; | |
2230 | } | |
2231 | ||
01101fa7 CW |
2232 | static int intel_alloc_ringbuffer_obj(struct drm_device *dev, |
2233 | struct intel_ringbuffer *ringbuf) | |
62fdfeaf | 2234 | { |
05394f39 | 2235 | struct drm_i915_gem_object *obj; |
62fdfeaf | 2236 | |
ebc052e0 CW |
2237 | obj = NULL; |
2238 | if (!HAS_LLC(dev)) | |
93b0a4e0 | 2239 | obj = i915_gem_object_create_stolen(dev, ringbuf->size); |
ebc052e0 | 2240 | if (obj == NULL) |
93b0a4e0 | 2241 | obj = i915_gem_alloc_object(dev, ringbuf->size); |
e3efda49 CW |
2242 | if (obj == NULL) |
2243 | return -ENOMEM; | |
8187a2b7 | 2244 | |
24f3a8cf AG |
2245 | /* mark ring buffers as read-only from GPU side by default */ |
2246 | obj->gt_ro = 1; | |
2247 | ||
93b0a4e0 | 2248 | ringbuf->obj = obj; |
e3efda49 | 2249 | |
7ba717cf | 2250 | return 0; |
e3efda49 CW |
2251 | } |
2252 | ||
01101fa7 CW |
2253 | struct intel_ringbuffer * |
2254 | intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size) | |
2255 | { | |
2256 | struct intel_ringbuffer *ring; | |
2257 | int ret; | |
2258 | ||
2259 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); | |
608c1a52 CW |
2260 | if (ring == NULL) { |
2261 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n", | |
2262 | engine->name); | |
01101fa7 | 2263 | return ERR_PTR(-ENOMEM); |
608c1a52 | 2264 | } |
01101fa7 | 2265 | |
4a570db5 | 2266 | ring->engine = engine; |
608c1a52 | 2267 | list_add(&ring->link, &engine->buffers); |
01101fa7 CW |
2268 | |
2269 | ring->size = size; | |
2270 | /* Workaround an erratum on the i830 which causes a hang if | |
2271 | * the TAIL pointer points to within the last 2 cachelines | |
2272 | * of the buffer. | |
2273 | */ | |
2274 | ring->effective_size = size; | |
2275 | if (IS_I830(engine->dev) || IS_845G(engine->dev)) | |
2276 | ring->effective_size -= 2 * CACHELINE_BYTES; | |
2277 | ||
2278 | ring->last_retired_head = -1; | |
2279 | intel_ring_update_space(ring); | |
2280 | ||
2281 | ret = intel_alloc_ringbuffer_obj(engine->dev, ring); | |
2282 | if (ret) { | |
608c1a52 CW |
2283 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n", |
2284 | engine->name, ret); | |
2285 | list_del(&ring->link); | |
01101fa7 CW |
2286 | kfree(ring); |
2287 | return ERR_PTR(ret); | |
2288 | } | |
2289 | ||
2290 | return ring; | |
2291 | } | |
2292 | ||
2293 | void | |
2294 | intel_ringbuffer_free(struct intel_ringbuffer *ring) | |
2295 | { | |
2296 | intel_destroy_ringbuffer_obj(ring); | |
608c1a52 | 2297 | list_del(&ring->link); |
01101fa7 CW |
2298 | kfree(ring); |
2299 | } | |
2300 | ||
e3efda49 | 2301 | static int intel_init_ring_buffer(struct drm_device *dev, |
0bc40be8 | 2302 | struct intel_engine_cs *engine) |
e3efda49 | 2303 | { |
bfc882b4 | 2304 | struct intel_ringbuffer *ringbuf; |
e3efda49 CW |
2305 | int ret; |
2306 | ||
0bc40be8 | 2307 | WARN_ON(engine->buffer); |
bfc882b4 | 2308 | |
0bc40be8 TU |
2309 | engine->dev = dev; |
2310 | INIT_LIST_HEAD(&engine->active_list); | |
2311 | INIT_LIST_HEAD(&engine->request_list); | |
2312 | INIT_LIST_HEAD(&engine->execlist_queue); | |
2313 | INIT_LIST_HEAD(&engine->buffers); | |
2314 | i915_gem_batch_pool_init(dev, &engine->batch_pool); | |
2315 | memset(engine->semaphore.sync_seqno, 0, | |
2316 | sizeof(engine->semaphore.sync_seqno)); | |
e3efda49 | 2317 | |
0bc40be8 | 2318 | init_waitqueue_head(&engine->irq_queue); |
e3efda49 | 2319 | |
0bc40be8 | 2320 | ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE); |
b0366a54 DG |
2321 | if (IS_ERR(ringbuf)) { |
2322 | ret = PTR_ERR(ringbuf); | |
2323 | goto error; | |
2324 | } | |
0bc40be8 | 2325 | engine->buffer = ringbuf; |
01101fa7 | 2326 | |
e3efda49 | 2327 | if (I915_NEED_GFX_HWS(dev)) { |
0bc40be8 | 2328 | ret = init_status_page(engine); |
e3efda49 | 2329 | if (ret) |
8ee14975 | 2330 | goto error; |
e3efda49 | 2331 | } else { |
0bc40be8 TU |
2332 | WARN_ON(engine->id != RCS); |
2333 | ret = init_phys_status_page(engine); | |
e3efda49 | 2334 | if (ret) |
8ee14975 | 2335 | goto error; |
e3efda49 CW |
2336 | } |
2337 | ||
bfc882b4 DV |
2338 | ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf); |
2339 | if (ret) { | |
2340 | DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n", | |
0bc40be8 | 2341 | engine->name, ret); |
bfc882b4 DV |
2342 | intel_destroy_ringbuffer_obj(ringbuf); |
2343 | goto error; | |
e3efda49 | 2344 | } |
62fdfeaf | 2345 | |
0bc40be8 | 2346 | ret = i915_cmd_parser_init_ring(engine); |
44e895a8 | 2347 | if (ret) |
8ee14975 OM |
2348 | goto error; |
2349 | ||
8ee14975 | 2350 | return 0; |
351e3db2 | 2351 | |
8ee14975 | 2352 | error: |
117897f4 | 2353 | intel_cleanup_engine(engine); |
8ee14975 | 2354 | return ret; |
62fdfeaf EA |
2355 | } |
2356 | ||
117897f4 | 2357 | void intel_cleanup_engine(struct intel_engine_cs *engine) |
62fdfeaf | 2358 | { |
6402c330 | 2359 | struct drm_i915_private *dev_priv; |
33626e6a | 2360 | |
117897f4 | 2361 | if (!intel_engine_initialized(engine)) |
62fdfeaf EA |
2362 | return; |
2363 | ||
0bc40be8 | 2364 | dev_priv = to_i915(engine->dev); |
6402c330 | 2365 | |
0bc40be8 | 2366 | if (engine->buffer) { |
117897f4 | 2367 | intel_stop_engine(engine); |
0bc40be8 | 2368 | WARN_ON(!IS_GEN2(engine->dev) && (I915_READ_MODE(engine) & MODE_IDLE) == 0); |
33626e6a | 2369 | |
0bc40be8 TU |
2370 | intel_unpin_ringbuffer_obj(engine->buffer); |
2371 | intel_ringbuffer_free(engine->buffer); | |
2372 | engine->buffer = NULL; | |
b0366a54 | 2373 | } |
78501eac | 2374 | |
0bc40be8 TU |
2375 | if (engine->cleanup) |
2376 | engine->cleanup(engine); | |
8d19215b | 2377 | |
0bc40be8 TU |
2378 | if (I915_NEED_GFX_HWS(engine->dev)) { |
2379 | cleanup_status_page(engine); | |
7d3fdfff | 2380 | } else { |
0bc40be8 TU |
2381 | WARN_ON(engine->id != RCS); |
2382 | cleanup_phys_status_page(engine); | |
7d3fdfff | 2383 | } |
44e895a8 | 2384 | |
0bc40be8 TU |
2385 | i915_cmd_parser_fini_ring(engine); |
2386 | i915_gem_batch_pool_fini(&engine->batch_pool); | |
2387 | engine->dev = NULL; | |
62fdfeaf EA |
2388 | } |
2389 | ||
666796da | 2390 | int intel_engine_idle(struct intel_engine_cs *engine) |
3e960501 | 2391 | { |
a4b3a571 | 2392 | struct drm_i915_gem_request *req; |
3e960501 | 2393 | |
3e960501 | 2394 | /* Wait upon the last request to be completed */ |
0bc40be8 | 2395 | if (list_empty(&engine->request_list)) |
3e960501 CW |
2396 | return 0; |
2397 | ||
0bc40be8 TU |
2398 | req = list_entry(engine->request_list.prev, |
2399 | struct drm_i915_gem_request, | |
2400 | list); | |
b4716185 CW |
2401 | |
2402 | /* Make sure we do not trigger any retires */ | |
2403 | return __i915_wait_request(req, | |
c19ae989 | 2404 | req->i915->mm.interruptible, |
b4716185 | 2405 | NULL, NULL); |
3e960501 CW |
2406 | } |
2407 | ||
6689cb2b | 2408 | int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request) |
9d773091 | 2409 | { |
4a570db5 | 2410 | request->ringbuf = request->engine->buffer; |
9eba5d4a | 2411 | return 0; |
9d773091 CW |
2412 | } |
2413 | ||
ccd98fe4 JH |
2414 | int intel_ring_reserve_space(struct drm_i915_gem_request *request) |
2415 | { | |
2416 | /* | |
2417 | * The first call merely notes the reserve request and is common for | |
2418 | * all back ends. The subsequent localised _begin() call actually | |
2419 | * ensures that the reservation is available. Without the begin, if | |
2420 | * the request creator immediately submitted the request without | |
2421 | * adding any commands to it then there might not actually be | |
2422 | * sufficient room for the submission commands. | |
2423 | */ | |
2424 | intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST); | |
2425 | ||
2426 | return intel_ring_begin(request, 0); | |
2427 | } | |
2428 | ||
29b1b415 JH |
2429 | void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size) |
2430 | { | |
92dcc67c | 2431 | GEM_BUG_ON(ringbuf->reserved_size); |
29b1b415 | 2432 | ringbuf->reserved_size = size; |
29b1b415 JH |
2433 | } |
2434 | ||
2435 | void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf) | |
2436 | { | |
92dcc67c | 2437 | GEM_BUG_ON(!ringbuf->reserved_size); |
29b1b415 | 2438 | ringbuf->reserved_size = 0; |
29b1b415 JH |
2439 | } |
2440 | ||
2441 | void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf) | |
2442 | { | |
92dcc67c CW |
2443 | GEM_BUG_ON(!ringbuf->reserved_size); |
2444 | ringbuf->reserved_size = 0; | |
29b1b415 JH |
2445 | } |
2446 | ||
2447 | void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf) | |
2448 | { | |
92dcc67c CW |
2449 | GEM_BUG_ON(ringbuf->reserved_size); |
2450 | } | |
2451 | ||
2452 | static int wait_for_space(struct drm_i915_gem_request *req, int bytes) | |
2453 | { | |
2454 | struct intel_ringbuffer *ringbuf = req->ringbuf; | |
2455 | struct intel_engine_cs *engine = req->engine; | |
2456 | struct drm_i915_gem_request *target; | |
2457 | ||
2458 | intel_ring_update_space(ringbuf); | |
2459 | if (ringbuf->space >= bytes) | |
2460 | return 0; | |
2461 | ||
2462 | /* | |
2463 | * Space is reserved in the ringbuffer for finalising the request, | |
2464 | * as that cannot be allowed to fail. During request finalisation, | |
2465 | * reserved_space is set to 0 to stop the overallocation and the | |
2466 | * assumption is that then we never need to wait (which has the | |
2467 | * risk of failing with EINTR). | |
2468 | * | |
2469 | * See also i915_gem_request_alloc() and i915_add_request(). | |
2470 | */ | |
2471 | GEM_BUG_ON(!ringbuf->reserved_size); | |
2472 | ||
2473 | list_for_each_entry(target, &engine->request_list, list) { | |
2474 | unsigned space; | |
2475 | ||
79bbcc29 | 2476 | /* |
92dcc67c CW |
2477 | * The request queue is per-engine, so can contain requests |
2478 | * from multiple ringbuffers. Here, we must ignore any that | |
2479 | * aren't from the ringbuffer we're considering. | |
79bbcc29 | 2480 | */ |
92dcc67c CW |
2481 | if (target->ringbuf != ringbuf) |
2482 | continue; | |
2483 | ||
2484 | /* Would completion of this request free enough space? */ | |
2485 | space = __intel_ring_space(target->postfix, ringbuf->tail, | |
2486 | ringbuf->size); | |
2487 | if (space >= bytes) | |
2488 | break; | |
79bbcc29 | 2489 | } |
29b1b415 | 2490 | |
92dcc67c CW |
2491 | if (WARN_ON(&target->list == &engine->request_list)) |
2492 | return -ENOSPC; | |
2493 | ||
2494 | return i915_wait_request(target); | |
29b1b415 JH |
2495 | } |
2496 | ||
92dcc67c | 2497 | int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords) |
cbcc80df | 2498 | { |
92dcc67c | 2499 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
79bbcc29 | 2500 | int remain_actual = ringbuf->size - ringbuf->tail; |
92dcc67c CW |
2501 | int remain_usable = ringbuf->effective_size - ringbuf->tail; |
2502 | int bytes = num_dwords * sizeof(u32); | |
2503 | int total_bytes, wait_bytes; | |
79bbcc29 | 2504 | bool need_wrap = false; |
29b1b415 | 2505 | |
92dcc67c | 2506 | total_bytes = bytes + ringbuf->reserved_size; |
29b1b415 | 2507 | |
79bbcc29 JH |
2508 | if (unlikely(bytes > remain_usable)) { |
2509 | /* | |
2510 | * Not enough space for the basic request. So need to flush | |
2511 | * out the remainder and then wait for base + reserved. | |
2512 | */ | |
2513 | wait_bytes = remain_actual + total_bytes; | |
2514 | need_wrap = true; | |
92dcc67c CW |
2515 | } else if (unlikely(total_bytes > remain_usable)) { |
2516 | /* | |
2517 | * The base request will fit but the reserved space | |
2518 | * falls off the end. So we don't need an immediate wrap | |
2519 | * and only need to effectively wait for the reserved | |
2520 | * size space from the start of ringbuffer. | |
2521 | */ | |
2522 | wait_bytes = remain_actual + ringbuf->reserved_size; | |
79bbcc29 | 2523 | } else { |
92dcc67c CW |
2524 | /* No wrapping required, just waiting. */ |
2525 | wait_bytes = total_bytes; | |
cbcc80df MK |
2526 | } |
2527 | ||
92dcc67c CW |
2528 | if (wait_bytes > ringbuf->space) { |
2529 | int ret = wait_for_space(req, wait_bytes); | |
cbcc80df MK |
2530 | if (unlikely(ret)) |
2531 | return ret; | |
79bbcc29 | 2532 | |
92dcc67c | 2533 | intel_ring_update_space(ringbuf); |
157d2c7f CW |
2534 | if (unlikely(ringbuf->space < wait_bytes)) |
2535 | return -EAGAIN; | |
cbcc80df MK |
2536 | } |
2537 | ||
92dcc67c CW |
2538 | if (unlikely(need_wrap)) { |
2539 | GEM_BUG_ON(remain_actual > ringbuf->space); | |
2540 | GEM_BUG_ON(ringbuf->tail + remain_actual > ringbuf->size); | |
78501eac | 2541 | |
92dcc67c CW |
2542 | /* Fill the tail with MI_NOOP */ |
2543 | memset(ringbuf->virtual_start + ringbuf->tail, | |
2544 | 0, remain_actual); | |
2545 | ringbuf->tail = 0; | |
2546 | ringbuf->space -= remain_actual; | |
2547 | } | |
304d695c | 2548 | |
92dcc67c CW |
2549 | ringbuf->space -= bytes; |
2550 | GEM_BUG_ON(ringbuf->space < 0); | |
304d695c | 2551 | return 0; |
8187a2b7 | 2552 | } |
78501eac | 2553 | |
753b1ad4 | 2554 | /* Align the ring tail to a cacheline boundary */ |
bba09b12 | 2555 | int intel_ring_cacheline_align(struct drm_i915_gem_request *req) |
753b1ad4 | 2556 | { |
4a570db5 | 2557 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 2558 | int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); |
753b1ad4 VS |
2559 | int ret; |
2560 | ||
2561 | if (num_dwords == 0) | |
2562 | return 0; | |
2563 | ||
18393f63 | 2564 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
5fb9de1a | 2565 | ret = intel_ring_begin(req, num_dwords); |
753b1ad4 VS |
2566 | if (ret) |
2567 | return ret; | |
2568 | ||
2569 | while (num_dwords--) | |
e2f80391 | 2570 | intel_ring_emit(engine, MI_NOOP); |
753b1ad4 | 2571 | |
e2f80391 | 2572 | intel_ring_advance(engine); |
753b1ad4 VS |
2573 | |
2574 | return 0; | |
2575 | } | |
2576 | ||
0bc40be8 | 2577 | void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno) |
498d2ac1 | 2578 | { |
d04bce48 | 2579 | struct drm_i915_private *dev_priv = to_i915(engine->dev); |
498d2ac1 | 2580 | |
29dcb570 CW |
2581 | /* Our semaphore implementation is strictly monotonic (i.e. we proceed |
2582 | * so long as the semaphore value in the register/page is greater | |
2583 | * than the sync value), so whenever we reset the seqno, | |
2584 | * so long as we reset the tracking semaphore value to 0, it will | |
2585 | * always be before the next request's seqno. If we don't reset | |
2586 | * the semaphore value, then when the seqno moves backwards all | |
2587 | * future waits will complete instantly (causing rendering corruption). | |
2588 | */ | |
d04bce48 | 2589 | if (INTEL_INFO(dev_priv)->gen == 6 || INTEL_INFO(dev_priv)->gen == 7) { |
0bc40be8 TU |
2590 | I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); |
2591 | I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); | |
d04bce48 | 2592 | if (HAS_VEBOX(dev_priv)) |
0bc40be8 | 2593 | I915_WRITE(RING_SYNC_2(engine->mmio_base), 0); |
e1f99ce6 | 2594 | } |
a058d934 CW |
2595 | if (dev_priv->semaphore_obj) { |
2596 | struct drm_i915_gem_object *obj = dev_priv->semaphore_obj; | |
2597 | struct page *page = i915_gem_object_get_dirty_page(obj, 0); | |
2598 | void *semaphores = kmap(page); | |
2599 | memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0), | |
2600 | 0, I915_NUM_ENGINES * gen8_semaphore_seqno_size); | |
2601 | kunmap(page); | |
2602 | } | |
29dcb570 CW |
2603 | memset(engine->semaphore.sync_seqno, 0, |
2604 | sizeof(engine->semaphore.sync_seqno)); | |
d97ed339 | 2605 | |
0bc40be8 | 2606 | engine->set_seqno(engine, seqno); |
01347126 | 2607 | engine->last_submitted_seqno = seqno; |
29dcb570 | 2608 | |
0bc40be8 | 2609 | engine->hangcheck.seqno = seqno; |
8187a2b7 | 2610 | } |
62fdfeaf | 2611 | |
0bc40be8 | 2612 | static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine, |
297b0c5b | 2613 | u32 value) |
881f47b6 | 2614 | { |
0bc40be8 | 2615 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
881f47b6 XH |
2616 | |
2617 | /* Every tail move must follow the sequence below */ | |
12f55818 CW |
2618 | |
2619 | /* Disable notification that the ring is IDLE. The GT | |
2620 | * will then assume that it is busy and bring it out of rc6. | |
2621 | */ | |
0206e353 | 2622 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 CW |
2623 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
2624 | ||
2625 | /* Clear the context id. Here be magic! */ | |
2626 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); | |
0206e353 | 2627 | |
12f55818 | 2628 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
0206e353 | 2629 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
12f55818 CW |
2630 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
2631 | 50)) | |
2632 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); | |
0206e353 | 2633 | |
12f55818 | 2634 | /* Now that the ring is fully powered up, update the tail */ |
0bc40be8 TU |
2635 | I915_WRITE_TAIL(engine, value); |
2636 | POSTING_READ(RING_TAIL(engine->mmio_base)); | |
12f55818 CW |
2637 | |
2638 | /* Let the ring send IDLE messages to the GT again, | |
2639 | * and so let it sleep to conserve power when idle. | |
2640 | */ | |
0206e353 | 2641 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 | 2642 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
881f47b6 XH |
2643 | } |
2644 | ||
a84c3ae1 | 2645 | static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, |
ea251324 | 2646 | u32 invalidate, u32 flush) |
881f47b6 | 2647 | { |
4a570db5 | 2648 | struct intel_engine_cs *engine = req->engine; |
71a77e07 | 2649 | uint32_t cmd; |
b72f3acb CW |
2650 | int ret; |
2651 | ||
5fb9de1a | 2652 | ret = intel_ring_begin(req, 4); |
b72f3acb CW |
2653 | if (ret) |
2654 | return ret; | |
2655 | ||
71a77e07 | 2656 | cmd = MI_FLUSH_DW; |
e2f80391 | 2657 | if (INTEL_INFO(engine->dev)->gen >= 8) |
075b3bba | 2658 | cmd += 1; |
f0a1fb10 CW |
2659 | |
2660 | /* We always require a command barrier so that subsequent | |
2661 | * commands, such as breadcrumb interrupts, are strictly ordered | |
2662 | * wrt the contents of the write cache being flushed to memory | |
2663 | * (and thus being coherent from the CPU). | |
2664 | */ | |
2665 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2666 | ||
9a289771 JB |
2667 | /* |
2668 | * Bspec vol 1c.5 - video engine command streamer: | |
2669 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2670 | * operation is complete. This bit is only valid when the | |
2671 | * Post-Sync Operation field is a value of 1h or 3h." | |
2672 | */ | |
71a77e07 | 2673 | if (invalidate & I915_GEM_GPU_DOMAINS) |
f0a1fb10 CW |
2674 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
2675 | ||
e2f80391 TU |
2676 | intel_ring_emit(engine, cmd); |
2677 | intel_ring_emit(engine, | |
2678 | I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); | |
2679 | if (INTEL_INFO(engine->dev)->gen >= 8) { | |
2680 | intel_ring_emit(engine, 0); /* upper addr */ | |
2681 | intel_ring_emit(engine, 0); /* value */ | |
075b3bba | 2682 | } else { |
e2f80391 TU |
2683 | intel_ring_emit(engine, 0); |
2684 | intel_ring_emit(engine, MI_NOOP); | |
075b3bba | 2685 | } |
e2f80391 | 2686 | intel_ring_advance(engine); |
b72f3acb | 2687 | return 0; |
881f47b6 XH |
2688 | } |
2689 | ||
1c7a0623 | 2690 | static int |
53fddaf7 | 2691 | gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 2692 | u64 offset, u32 len, |
8e004efc | 2693 | unsigned dispatch_flags) |
1c7a0623 | 2694 | { |
4a570db5 | 2695 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 2696 | bool ppgtt = USES_PPGTT(engine->dev) && |
8e004efc | 2697 | !(dispatch_flags & I915_DISPATCH_SECURE); |
1c7a0623 BW |
2698 | int ret; |
2699 | ||
5fb9de1a | 2700 | ret = intel_ring_begin(req, 4); |
1c7a0623 BW |
2701 | if (ret) |
2702 | return ret; | |
2703 | ||
2704 | /* FIXME(BDW): Address space and security selectors. */ | |
e2f80391 | 2705 | intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) | |
919032ec AJ |
2706 | (dispatch_flags & I915_DISPATCH_RS ? |
2707 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
e2f80391 TU |
2708 | intel_ring_emit(engine, lower_32_bits(offset)); |
2709 | intel_ring_emit(engine, upper_32_bits(offset)); | |
2710 | intel_ring_emit(engine, MI_NOOP); | |
2711 | intel_ring_advance(engine); | |
1c7a0623 BW |
2712 | |
2713 | return 0; | |
2714 | } | |
2715 | ||
d7d4eedd | 2716 | static int |
53fddaf7 | 2717 | hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
8e004efc JH |
2718 | u64 offset, u32 len, |
2719 | unsigned dispatch_flags) | |
d7d4eedd | 2720 | { |
4a570db5 | 2721 | struct intel_engine_cs *engine = req->engine; |
d7d4eedd CW |
2722 | int ret; |
2723 | ||
5fb9de1a | 2724 | ret = intel_ring_begin(req, 2); |
d7d4eedd CW |
2725 | if (ret) |
2726 | return ret; | |
2727 | ||
e2f80391 | 2728 | intel_ring_emit(engine, |
77072258 | 2729 | MI_BATCH_BUFFER_START | |
8e004efc | 2730 | (dispatch_flags & I915_DISPATCH_SECURE ? |
919032ec AJ |
2731 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) | |
2732 | (dispatch_flags & I915_DISPATCH_RS ? | |
2733 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
d7d4eedd | 2734 | /* bit0-7 is the length on GEN6+ */ |
e2f80391 TU |
2735 | intel_ring_emit(engine, offset); |
2736 | intel_ring_advance(engine); | |
d7d4eedd CW |
2737 | |
2738 | return 0; | |
2739 | } | |
2740 | ||
881f47b6 | 2741 | static int |
53fddaf7 | 2742 | gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 2743 | u64 offset, u32 len, |
8e004efc | 2744 | unsigned dispatch_flags) |
881f47b6 | 2745 | { |
4a570db5 | 2746 | struct intel_engine_cs *engine = req->engine; |
0206e353 | 2747 | int ret; |
ab6f8e32 | 2748 | |
5fb9de1a | 2749 | ret = intel_ring_begin(req, 2); |
0206e353 AJ |
2750 | if (ret) |
2751 | return ret; | |
e1f99ce6 | 2752 | |
e2f80391 | 2753 | intel_ring_emit(engine, |
d7d4eedd | 2754 | MI_BATCH_BUFFER_START | |
8e004efc JH |
2755 | (dispatch_flags & I915_DISPATCH_SECURE ? |
2756 | 0 : MI_BATCH_NON_SECURE_I965)); | |
0206e353 | 2757 | /* bit0-7 is the length on GEN6+ */ |
e2f80391 TU |
2758 | intel_ring_emit(engine, offset); |
2759 | intel_ring_advance(engine); | |
ab6f8e32 | 2760 | |
0206e353 | 2761 | return 0; |
881f47b6 XH |
2762 | } |
2763 | ||
549f7365 CW |
2764 | /* Blitter support (SandyBridge+) */ |
2765 | ||
a84c3ae1 | 2766 | static int gen6_ring_flush(struct drm_i915_gem_request *req, |
ea251324 | 2767 | u32 invalidate, u32 flush) |
8d19215b | 2768 | { |
4a570db5 | 2769 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 2770 | struct drm_device *dev = engine->dev; |
71a77e07 | 2771 | uint32_t cmd; |
b72f3acb CW |
2772 | int ret; |
2773 | ||
5fb9de1a | 2774 | ret = intel_ring_begin(req, 4); |
b72f3acb CW |
2775 | if (ret) |
2776 | return ret; | |
2777 | ||
71a77e07 | 2778 | cmd = MI_FLUSH_DW; |
dbef0f15 | 2779 | if (INTEL_INFO(dev)->gen >= 8) |
075b3bba | 2780 | cmd += 1; |
f0a1fb10 CW |
2781 | |
2782 | /* We always require a command barrier so that subsequent | |
2783 | * commands, such as breadcrumb interrupts, are strictly ordered | |
2784 | * wrt the contents of the write cache being flushed to memory | |
2785 | * (and thus being coherent from the CPU). | |
2786 | */ | |
2787 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2788 | ||
9a289771 JB |
2789 | /* |
2790 | * Bspec vol 1c.3 - blitter engine command streamer: | |
2791 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2792 | * operation is complete. This bit is only valid when the | |
2793 | * Post-Sync Operation field is a value of 1h or 3h." | |
2794 | */ | |
71a77e07 | 2795 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
f0a1fb10 | 2796 | cmd |= MI_INVALIDATE_TLB; |
e2f80391 TU |
2797 | intel_ring_emit(engine, cmd); |
2798 | intel_ring_emit(engine, | |
2799 | I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); | |
dbef0f15 | 2800 | if (INTEL_INFO(dev)->gen >= 8) { |
e2f80391 TU |
2801 | intel_ring_emit(engine, 0); /* upper addr */ |
2802 | intel_ring_emit(engine, 0); /* value */ | |
075b3bba | 2803 | } else { |
e2f80391 TU |
2804 | intel_ring_emit(engine, 0); |
2805 | intel_ring_emit(engine, MI_NOOP); | |
075b3bba | 2806 | } |
e2f80391 | 2807 | intel_ring_advance(engine); |
fd3da6c9 | 2808 | |
b72f3acb | 2809 | return 0; |
8d19215b ZN |
2810 | } |
2811 | ||
5c1143bb XH |
2812 | int intel_init_render_ring_buffer(struct drm_device *dev) |
2813 | { | |
4640c4ff | 2814 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a570db5 | 2815 | struct intel_engine_cs *engine = &dev_priv->engine[RCS]; |
3e78998a BW |
2816 | struct drm_i915_gem_object *obj; |
2817 | int ret; | |
5c1143bb | 2818 | |
e2f80391 TU |
2819 | engine->name = "render ring"; |
2820 | engine->id = RCS; | |
2821 | engine->exec_id = I915_EXEC_RENDER; | |
83e53802 | 2822 | engine->hw_id = 0; |
e2f80391 | 2823 | engine->mmio_base = RENDER_RING_BASE; |
59465b5f | 2824 | |
707d9cf9 | 2825 | if (INTEL_INFO(dev)->gen >= 8) { |
3e78998a BW |
2826 | if (i915_semaphore_is_enabled(dev)) { |
2827 | obj = i915_gem_alloc_object(dev, 4096); | |
2828 | if (obj == NULL) { | |
2829 | DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n"); | |
2830 | i915.semaphores = 0; | |
2831 | } else { | |
2832 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
2833 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK); | |
2834 | if (ret != 0) { | |
2835 | drm_gem_object_unreference(&obj->base); | |
2836 | DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n"); | |
2837 | i915.semaphores = 0; | |
2838 | } else | |
2839 | dev_priv->semaphore_obj = obj; | |
2840 | } | |
2841 | } | |
7225342a | 2842 | |
e2f80391 TU |
2843 | engine->init_context = intel_rcs_ctx_init; |
2844 | engine->add_request = gen6_add_request; | |
2845 | engine->flush = gen8_render_ring_flush; | |
2846 | engine->irq_get = gen8_ring_get_irq; | |
2847 | engine->irq_put = gen8_ring_put_irq; | |
2848 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; | |
c04e0f3b CW |
2849 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2850 | engine->get_seqno = ring_get_seqno; | |
e2f80391 | 2851 | engine->set_seqno = ring_set_seqno; |
707d9cf9 | 2852 | if (i915_semaphore_is_enabled(dev)) { |
3e78998a | 2853 | WARN_ON(!dev_priv->semaphore_obj); |
e2f80391 TU |
2854 | engine->semaphore.sync_to = gen8_ring_sync; |
2855 | engine->semaphore.signal = gen8_rcs_signal; | |
2856 | GEN8_RING_SEMAPHORE_INIT(engine); | |
707d9cf9 BW |
2857 | } |
2858 | } else if (INTEL_INFO(dev)->gen >= 6) { | |
e2f80391 TU |
2859 | engine->init_context = intel_rcs_ctx_init; |
2860 | engine->add_request = gen6_add_request; | |
2861 | engine->flush = gen7_render_ring_flush; | |
6c6cf5aa | 2862 | if (INTEL_INFO(dev)->gen == 6) |
e2f80391 TU |
2863 | engine->flush = gen6_render_ring_flush; |
2864 | engine->irq_get = gen6_ring_get_irq; | |
2865 | engine->irq_put = gen6_ring_put_irq; | |
2866 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; | |
c04e0f3b CW |
2867 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2868 | engine->get_seqno = ring_get_seqno; | |
e2f80391 | 2869 | engine->set_seqno = ring_set_seqno; |
707d9cf9 | 2870 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
2871 | engine->semaphore.sync_to = gen6_ring_sync; |
2872 | engine->semaphore.signal = gen6_signal; | |
707d9cf9 BW |
2873 | /* |
2874 | * The current semaphore is only applied on pre-gen8 | |
2875 | * platform. And there is no VCS2 ring on the pre-gen8 | |
2876 | * platform. So the semaphore between RCS and VCS2 is | |
2877 | * initialized as INVALID. Gen8 will initialize the | |
2878 | * sema between VCS2 and RCS later. | |
2879 | */ | |
e2f80391 TU |
2880 | engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID; |
2881 | engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV; | |
2882 | engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB; | |
2883 | engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE; | |
2884 | engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2885 | engine->semaphore.mbox.signal[RCS] = GEN6_NOSYNC; | |
2886 | engine->semaphore.mbox.signal[VCS] = GEN6_VRSYNC; | |
2887 | engine->semaphore.mbox.signal[BCS] = GEN6_BRSYNC; | |
2888 | engine->semaphore.mbox.signal[VECS] = GEN6_VERSYNC; | |
2889 | engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
707d9cf9 | 2890 | } |
c6df541c | 2891 | } else if (IS_GEN5(dev)) { |
e2f80391 TU |
2892 | engine->add_request = pc_render_add_request; |
2893 | engine->flush = gen4_render_ring_flush; | |
2894 | engine->get_seqno = pc_render_get_seqno; | |
2895 | engine->set_seqno = pc_render_set_seqno; | |
2896 | engine->irq_get = gen5_ring_get_irq; | |
2897 | engine->irq_put = gen5_ring_put_irq; | |
2898 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT | | |
cc609d5d | 2899 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; |
59465b5f | 2900 | } else { |
e2f80391 | 2901 | engine->add_request = i9xx_add_request; |
46f0f8d1 | 2902 | if (INTEL_INFO(dev)->gen < 4) |
e2f80391 | 2903 | engine->flush = gen2_render_ring_flush; |
46f0f8d1 | 2904 | else |
e2f80391 TU |
2905 | engine->flush = gen4_render_ring_flush; |
2906 | engine->get_seqno = ring_get_seqno; | |
2907 | engine->set_seqno = ring_set_seqno; | |
c2798b19 | 2908 | if (IS_GEN2(dev)) { |
e2f80391 TU |
2909 | engine->irq_get = i8xx_ring_get_irq; |
2910 | engine->irq_put = i8xx_ring_put_irq; | |
c2798b19 | 2911 | } else { |
e2f80391 TU |
2912 | engine->irq_get = i9xx_ring_get_irq; |
2913 | engine->irq_put = i9xx_ring_put_irq; | |
c2798b19 | 2914 | } |
e2f80391 | 2915 | engine->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2916 | } |
e2f80391 | 2917 | engine->write_tail = ring_write_tail; |
707d9cf9 | 2918 | |
d7d4eedd | 2919 | if (IS_HASWELL(dev)) |
e2f80391 | 2920 | engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; |
1c7a0623 | 2921 | else if (IS_GEN8(dev)) |
e2f80391 | 2922 | engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
d7d4eedd | 2923 | else if (INTEL_INFO(dev)->gen >= 6) |
e2f80391 | 2924 | engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
fb3256da | 2925 | else if (INTEL_INFO(dev)->gen >= 4) |
e2f80391 | 2926 | engine->dispatch_execbuffer = i965_dispatch_execbuffer; |
fb3256da | 2927 | else if (IS_I830(dev) || IS_845G(dev)) |
e2f80391 | 2928 | engine->dispatch_execbuffer = i830_dispatch_execbuffer; |
fb3256da | 2929 | else |
e2f80391 TU |
2930 | engine->dispatch_execbuffer = i915_dispatch_execbuffer; |
2931 | engine->init_hw = init_render_ring; | |
2932 | engine->cleanup = render_ring_cleanup; | |
59465b5f | 2933 | |
b45305fc DV |
2934 | /* Workaround batchbuffer to combat CS tlb bug. */ |
2935 | if (HAS_BROKEN_CS_TLB(dev)) { | |
c4d69da1 | 2936 | obj = i915_gem_alloc_object(dev, I830_WA_SIZE); |
b45305fc DV |
2937 | if (obj == NULL) { |
2938 | DRM_ERROR("Failed to allocate batch bo\n"); | |
2939 | return -ENOMEM; | |
2940 | } | |
2941 | ||
be1fa129 | 2942 | ret = i915_gem_obj_ggtt_pin(obj, 0, 0); |
b45305fc DV |
2943 | if (ret != 0) { |
2944 | drm_gem_object_unreference(&obj->base); | |
2945 | DRM_ERROR("Failed to ping batch bo\n"); | |
2946 | return ret; | |
2947 | } | |
2948 | ||
e2f80391 TU |
2949 | engine->scratch.obj = obj; |
2950 | engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); | |
b45305fc DV |
2951 | } |
2952 | ||
e2f80391 | 2953 | ret = intel_init_ring_buffer(dev, engine); |
99be1dfe DV |
2954 | if (ret) |
2955 | return ret; | |
2956 | ||
2957 | if (INTEL_INFO(dev)->gen >= 5) { | |
e2f80391 | 2958 | ret = intel_init_pipe_control(engine); |
99be1dfe DV |
2959 | if (ret) |
2960 | return ret; | |
2961 | } | |
2962 | ||
2963 | return 0; | |
5c1143bb XH |
2964 | } |
2965 | ||
2966 | int intel_init_bsd_ring_buffer(struct drm_device *dev) | |
2967 | { | |
4640c4ff | 2968 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a570db5 | 2969 | struct intel_engine_cs *engine = &dev_priv->engine[VCS]; |
5c1143bb | 2970 | |
e2f80391 TU |
2971 | engine->name = "bsd ring"; |
2972 | engine->id = VCS; | |
2973 | engine->exec_id = I915_EXEC_BSD; | |
83e53802 | 2974 | engine->hw_id = 1; |
58fa3835 | 2975 | |
e2f80391 | 2976 | engine->write_tail = ring_write_tail; |
780f18c8 | 2977 | if (INTEL_INFO(dev)->gen >= 6) { |
e2f80391 | 2978 | engine->mmio_base = GEN6_BSD_RING_BASE; |
0fd2c201 DV |
2979 | /* gen6 bsd needs a special wa for tail updates */ |
2980 | if (IS_GEN6(dev)) | |
e2f80391 TU |
2981 | engine->write_tail = gen6_bsd_ring_write_tail; |
2982 | engine->flush = gen6_bsd_ring_flush; | |
2983 | engine->add_request = gen6_add_request; | |
c04e0f3b CW |
2984 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2985 | engine->get_seqno = ring_get_seqno; | |
e2f80391 | 2986 | engine->set_seqno = ring_set_seqno; |
abd58f01 | 2987 | if (INTEL_INFO(dev)->gen >= 8) { |
e2f80391 | 2988 | engine->irq_enable_mask = |
abd58f01 | 2989 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; |
e2f80391 TU |
2990 | engine->irq_get = gen8_ring_get_irq; |
2991 | engine->irq_put = gen8_ring_put_irq; | |
2992 | engine->dispatch_execbuffer = | |
1c7a0623 | 2993 | gen8_ring_dispatch_execbuffer; |
707d9cf9 | 2994 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
2995 | engine->semaphore.sync_to = gen8_ring_sync; |
2996 | engine->semaphore.signal = gen8_xcs_signal; | |
2997 | GEN8_RING_SEMAPHORE_INIT(engine); | |
707d9cf9 | 2998 | } |
abd58f01 | 2999 | } else { |
e2f80391 TU |
3000 | engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
3001 | engine->irq_get = gen6_ring_get_irq; | |
3002 | engine->irq_put = gen6_ring_put_irq; | |
3003 | engine->dispatch_execbuffer = | |
1c7a0623 | 3004 | gen6_ring_dispatch_execbuffer; |
707d9cf9 | 3005 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
3006 | engine->semaphore.sync_to = gen6_ring_sync; |
3007 | engine->semaphore.signal = gen6_signal; | |
3008 | engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR; | |
3009 | engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID; | |
3010 | engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB; | |
3011 | engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE; | |
3012 | engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
3013 | engine->semaphore.mbox.signal[RCS] = GEN6_RVSYNC; | |
3014 | engine->semaphore.mbox.signal[VCS] = GEN6_NOSYNC; | |
3015 | engine->semaphore.mbox.signal[BCS] = GEN6_BVSYNC; | |
3016 | engine->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC; | |
3017 | engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
707d9cf9 | 3018 | } |
abd58f01 | 3019 | } |
58fa3835 | 3020 | } else { |
e2f80391 TU |
3021 | engine->mmio_base = BSD_RING_BASE; |
3022 | engine->flush = bsd_ring_flush; | |
3023 | engine->add_request = i9xx_add_request; | |
3024 | engine->get_seqno = ring_get_seqno; | |
3025 | engine->set_seqno = ring_set_seqno; | |
e48d8634 | 3026 | if (IS_GEN5(dev)) { |
e2f80391 TU |
3027 | engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
3028 | engine->irq_get = gen5_ring_get_irq; | |
3029 | engine->irq_put = gen5_ring_put_irq; | |
e48d8634 | 3030 | } else { |
e2f80391 TU |
3031 | engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
3032 | engine->irq_get = i9xx_ring_get_irq; | |
3033 | engine->irq_put = i9xx_ring_put_irq; | |
e48d8634 | 3034 | } |
e2f80391 | 3035 | engine->dispatch_execbuffer = i965_dispatch_execbuffer; |
58fa3835 | 3036 | } |
e2f80391 | 3037 | engine->init_hw = init_ring_common; |
58fa3835 | 3038 | |
e2f80391 | 3039 | return intel_init_ring_buffer(dev, engine); |
5c1143bb | 3040 | } |
549f7365 | 3041 | |
845f74a7 | 3042 | /** |
62659920 | 3043 | * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3) |
845f74a7 ZY |
3044 | */ |
3045 | int intel_init_bsd2_ring_buffer(struct drm_device *dev) | |
3046 | { | |
3047 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a570db5 | 3048 | struct intel_engine_cs *engine = &dev_priv->engine[VCS2]; |
e2f80391 TU |
3049 | |
3050 | engine->name = "bsd2 ring"; | |
3051 | engine->id = VCS2; | |
3052 | engine->exec_id = I915_EXEC_BSD; | |
83e53802 | 3053 | engine->hw_id = 4; |
e2f80391 TU |
3054 | |
3055 | engine->write_tail = ring_write_tail; | |
3056 | engine->mmio_base = GEN8_BSD2_RING_BASE; | |
3057 | engine->flush = gen6_bsd_ring_flush; | |
3058 | engine->add_request = gen6_add_request; | |
c04e0f3b CW |
3059 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
3060 | engine->get_seqno = ring_get_seqno; | |
e2f80391 TU |
3061 | engine->set_seqno = ring_set_seqno; |
3062 | engine->irq_enable_mask = | |
845f74a7 | 3063 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; |
e2f80391 TU |
3064 | engine->irq_get = gen8_ring_get_irq; |
3065 | engine->irq_put = gen8_ring_put_irq; | |
3066 | engine->dispatch_execbuffer = | |
845f74a7 | 3067 | gen8_ring_dispatch_execbuffer; |
3e78998a | 3068 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
3069 | engine->semaphore.sync_to = gen8_ring_sync; |
3070 | engine->semaphore.signal = gen8_xcs_signal; | |
3071 | GEN8_RING_SEMAPHORE_INIT(engine); | |
3e78998a | 3072 | } |
e2f80391 | 3073 | engine->init_hw = init_ring_common; |
845f74a7 | 3074 | |
e2f80391 | 3075 | return intel_init_ring_buffer(dev, engine); |
845f74a7 ZY |
3076 | } |
3077 | ||
549f7365 CW |
3078 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
3079 | { | |
4640c4ff | 3080 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a570db5 | 3081 | struct intel_engine_cs *engine = &dev_priv->engine[BCS]; |
e2f80391 TU |
3082 | |
3083 | engine->name = "blitter ring"; | |
3084 | engine->id = BCS; | |
3085 | engine->exec_id = I915_EXEC_BLT; | |
83e53802 | 3086 | engine->hw_id = 2; |
e2f80391 TU |
3087 | |
3088 | engine->mmio_base = BLT_RING_BASE; | |
3089 | engine->write_tail = ring_write_tail; | |
3090 | engine->flush = gen6_ring_flush; | |
3091 | engine->add_request = gen6_add_request; | |
c04e0f3b CW |
3092 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
3093 | engine->get_seqno = ring_get_seqno; | |
e2f80391 | 3094 | engine->set_seqno = ring_set_seqno; |
abd58f01 | 3095 | if (INTEL_INFO(dev)->gen >= 8) { |
e2f80391 | 3096 | engine->irq_enable_mask = |
abd58f01 | 3097 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; |
e2f80391 TU |
3098 | engine->irq_get = gen8_ring_get_irq; |
3099 | engine->irq_put = gen8_ring_put_irq; | |
3100 | engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; | |
707d9cf9 | 3101 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
3102 | engine->semaphore.sync_to = gen8_ring_sync; |
3103 | engine->semaphore.signal = gen8_xcs_signal; | |
3104 | GEN8_RING_SEMAPHORE_INIT(engine); | |
707d9cf9 | 3105 | } |
abd58f01 | 3106 | } else { |
e2f80391 TU |
3107 | engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
3108 | engine->irq_get = gen6_ring_get_irq; | |
3109 | engine->irq_put = gen6_ring_put_irq; | |
3110 | engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; | |
707d9cf9 | 3111 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
3112 | engine->semaphore.signal = gen6_signal; |
3113 | engine->semaphore.sync_to = gen6_ring_sync; | |
707d9cf9 BW |
3114 | /* |
3115 | * The current semaphore is only applied on pre-gen8 | |
3116 | * platform. And there is no VCS2 ring on the pre-gen8 | |
3117 | * platform. So the semaphore between BCS and VCS2 is | |
3118 | * initialized as INVALID. Gen8 will initialize the | |
3119 | * sema between BCS and VCS2 later. | |
3120 | */ | |
e2f80391 TU |
3121 | engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR; |
3122 | engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV; | |
3123 | engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID; | |
3124 | engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE; | |
3125 | engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
3126 | engine->semaphore.mbox.signal[RCS] = GEN6_RBSYNC; | |
3127 | engine->semaphore.mbox.signal[VCS] = GEN6_VBSYNC; | |
3128 | engine->semaphore.mbox.signal[BCS] = GEN6_NOSYNC; | |
3129 | engine->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC; | |
3130 | engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
707d9cf9 | 3131 | } |
abd58f01 | 3132 | } |
e2f80391 | 3133 | engine->init_hw = init_ring_common; |
549f7365 | 3134 | |
e2f80391 | 3135 | return intel_init_ring_buffer(dev, engine); |
549f7365 | 3136 | } |
a7b9761d | 3137 | |
9a8a2213 BW |
3138 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
3139 | { | |
4640c4ff | 3140 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a570db5 | 3141 | struct intel_engine_cs *engine = &dev_priv->engine[VECS]; |
9a8a2213 | 3142 | |
e2f80391 TU |
3143 | engine->name = "video enhancement ring"; |
3144 | engine->id = VECS; | |
3145 | engine->exec_id = I915_EXEC_VEBOX; | |
83e53802 | 3146 | engine->hw_id = 3; |
9a8a2213 | 3147 | |
e2f80391 TU |
3148 | engine->mmio_base = VEBOX_RING_BASE; |
3149 | engine->write_tail = ring_write_tail; | |
3150 | engine->flush = gen6_ring_flush; | |
3151 | engine->add_request = gen6_add_request; | |
c04e0f3b CW |
3152 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
3153 | engine->get_seqno = ring_get_seqno; | |
e2f80391 | 3154 | engine->set_seqno = ring_set_seqno; |
abd58f01 BW |
3155 | |
3156 | if (INTEL_INFO(dev)->gen >= 8) { | |
e2f80391 | 3157 | engine->irq_enable_mask = |
40c499f9 | 3158 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
e2f80391 TU |
3159 | engine->irq_get = gen8_ring_get_irq; |
3160 | engine->irq_put = gen8_ring_put_irq; | |
3161 | engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; | |
707d9cf9 | 3162 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
3163 | engine->semaphore.sync_to = gen8_ring_sync; |
3164 | engine->semaphore.signal = gen8_xcs_signal; | |
3165 | GEN8_RING_SEMAPHORE_INIT(engine); | |
707d9cf9 | 3166 | } |
abd58f01 | 3167 | } else { |
e2f80391 TU |
3168 | engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
3169 | engine->irq_get = hsw_vebox_get_irq; | |
3170 | engine->irq_put = hsw_vebox_put_irq; | |
3171 | engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; | |
707d9cf9 | 3172 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
3173 | engine->semaphore.sync_to = gen6_ring_sync; |
3174 | engine->semaphore.signal = gen6_signal; | |
3175 | engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER; | |
3176 | engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV; | |
3177 | engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB; | |
3178 | engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID; | |
3179 | engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
3180 | engine->semaphore.mbox.signal[RCS] = GEN6_RVESYNC; | |
3181 | engine->semaphore.mbox.signal[VCS] = GEN6_VVESYNC; | |
3182 | engine->semaphore.mbox.signal[BCS] = GEN6_BVESYNC; | |
3183 | engine->semaphore.mbox.signal[VECS] = GEN6_NOSYNC; | |
3184 | engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
707d9cf9 | 3185 | } |
abd58f01 | 3186 | } |
e2f80391 | 3187 | engine->init_hw = init_ring_common; |
9a8a2213 | 3188 | |
e2f80391 | 3189 | return intel_init_ring_buffer(dev, engine); |
9a8a2213 BW |
3190 | } |
3191 | ||
a7b9761d | 3192 | int |
4866d729 | 3193 | intel_ring_flush_all_caches(struct drm_i915_gem_request *req) |
a7b9761d | 3194 | { |
4a570db5 | 3195 | struct intel_engine_cs *engine = req->engine; |
a7b9761d CW |
3196 | int ret; |
3197 | ||
e2f80391 | 3198 | if (!engine->gpu_caches_dirty) |
a7b9761d CW |
3199 | return 0; |
3200 | ||
e2f80391 | 3201 | ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS); |
a7b9761d CW |
3202 | if (ret) |
3203 | return ret; | |
3204 | ||
a84c3ae1 | 3205 | trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS); |
a7b9761d | 3206 | |
e2f80391 | 3207 | engine->gpu_caches_dirty = false; |
a7b9761d CW |
3208 | return 0; |
3209 | } | |
3210 | ||
3211 | int | |
2f20055d | 3212 | intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req) |
a7b9761d | 3213 | { |
4a570db5 | 3214 | struct intel_engine_cs *engine = req->engine; |
a7b9761d CW |
3215 | uint32_t flush_domains; |
3216 | int ret; | |
3217 | ||
3218 | flush_domains = 0; | |
e2f80391 | 3219 | if (engine->gpu_caches_dirty) |
a7b9761d CW |
3220 | flush_domains = I915_GEM_GPU_DOMAINS; |
3221 | ||
e2f80391 | 3222 | ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
a7b9761d CW |
3223 | if (ret) |
3224 | return ret; | |
3225 | ||
a84c3ae1 | 3226 | trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
a7b9761d | 3227 | |
e2f80391 | 3228 | engine->gpu_caches_dirty = false; |
a7b9761d CW |
3229 | return 0; |
3230 | } | |
e3efda49 CW |
3231 | |
3232 | void | |
117897f4 | 3233 | intel_stop_engine(struct intel_engine_cs *engine) |
e3efda49 CW |
3234 | { |
3235 | int ret; | |
3236 | ||
117897f4 | 3237 | if (!intel_engine_initialized(engine)) |
e3efda49 CW |
3238 | return; |
3239 | ||
666796da | 3240 | ret = intel_engine_idle(engine); |
f4457ae7 | 3241 | if (ret) |
e3efda49 | 3242 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
0bc40be8 | 3243 | engine->name, ret); |
e3efda49 | 3244 | |
0bc40be8 | 3245 | stop_ring(engine); |
e3efda49 | 3246 | } |