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drm/i915/kbl: Add Kabylake GT4 PCI ID
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
CommitLineData
62fdfeaf
EA		 1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
760285e7 30#include <drm/drmP.h>
62fdfeaf 31#include "i915_drv.h"
760285e7 32#include <drm/i915_drm.h>
62fdfeaf 33#include "i915_trace.h"
881f47b6 34#include "intel_drv.h"
62fdfeaf 35
48d82387
OM		 36bool
37intel_ring_initialized(struct intel_engine_cs *ring)
38{
39 struct drm_device *dev = ring->dev;
40
41 if (!dev)
42 return false;
43
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
47
48 return ringbuf->obj;
49 } else
50 return ring->buffer && ring->buffer->obj;
51}
18393f63 52
82e104cc 53int __intel_ring_space(int head, int tail, int size)
c7dca47b 54{
4f54741e
DG		 55 int space = head - tail;
56 if (space <= 0)
1cf0ba14 57 space += size;
4f54741e 58 return space - I915_RING_FREE_SPACE;
c7dca47b
CW		 59}
60
ebd0fd4b
DG		 61void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
62{
63 if (ringbuf->last_retired_head != -1) {
64 ringbuf->head = ringbuf->last_retired_head;
65 ringbuf->last_retired_head = -1;
66 }
67
68 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
69 ringbuf->tail, ringbuf->size);
70}
71
82e104cc 72int intel_ring_space(struct intel_ringbuffer *ringbuf)
1cf0ba14 73{
ebd0fd4b
DG		 74 intel_ring_update_space(ringbuf);
75 return ringbuf->space;
1cf0ba14
CW		 76}
77
82e104cc 78bool intel_ring_stopped(struct intel_engine_cs *ring)
09246732
CW		 79{
80 struct drm_i915_private *dev_priv = ring->dev->dev_private;
88b4aa87
MK		 81 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
82}
09246732 83
6258fbe2 84static void __intel_ring_advance(struct intel_engine_cs *ring)
88b4aa87 85{
93b0a4e0
OM		 86 struct intel_ringbuffer *ringbuf = ring->buffer;
87 ringbuf->tail &= ringbuf->size - 1;
88b4aa87 88 if (intel_ring_stopped(ring))
09246732 89 return;
93b0a4e0 90 ring->write_tail(ring, ringbuf->tail);
09246732
CW		 91}
92
b72f3acb 93static int
a84c3ae1 94gen2_render_ring_flush(struct drm_i915_gem_request *req,
46f0f8d1
CW		 95 u32 invalidate_domains,
96 u32 flush_domains)
97{
a84c3ae1 98 struct intel_engine_cs *ring = req->ring;
46f0f8d1
CW		 99 u32 cmd;
100 int ret;
101
102 cmd = MI_FLUSH;
31b14c9f 103 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
46f0f8d1
CW		 104 cmd |= MI_NO_WRITE_FLUSH;
105
106 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
107 cmd |= MI_READ_FLUSH;
108
5fb9de1a 109 ret = intel_ring_begin(req, 2);
46f0f8d1
CW		 110 if (ret)
111 return ret;
112
113 intel_ring_emit(ring, cmd);
114 intel_ring_emit(ring, MI_NOOP);
115 intel_ring_advance(ring);
116
117 return 0;
118}
119
120static int
a84c3ae1 121gen4_render_ring_flush(struct drm_i915_gem_request *req,
46f0f8d1
CW		 122 u32 invalidate_domains,
123 u32 flush_domains)
62fdfeaf 124{
a84c3ae1 125 struct intel_engine_cs *ring = req->ring;
78501eac 126 struct drm_device *dev = ring->dev;
6f392d54 127 u32 cmd;
b72f3acb 128 int ret;
6f392d54 129
36d527de
CW		 130 /*
131 * read/write caches:
132 *
133 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
134 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
135 * also flushed at 2d versus 3d pipeline switches.
136 *
137 * read-only caches:
138 *
139 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
140 * MI_READ_FLUSH is set, and is always flushed on 965.
141 *
142 * I915_GEM_DOMAIN_COMMAND may not exist?
143 *
144 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
145 * invalidated when MI_EXE_FLUSH is set.
146 *
147 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
148 * invalidated with every MI_FLUSH.
149 *
150 * TLBs:
151 *
152 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
153 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
154 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
155 * are flushed at any MI_FLUSH.
156 */
157
158 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
46f0f8d1 159 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
36d527de 160 cmd &= ~MI_NO_WRITE_FLUSH;
36d527de
CW		 161 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
162 cmd |= MI_EXE_FLUSH;
62fdfeaf 163
36d527de
CW		 164 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
165 (IS_G4X(dev) || IS_GEN5(dev)))
166 cmd |= MI_INVALIDATE_ISP;
70eac33e 167
5fb9de1a 168 ret = intel_ring_begin(req, 2);
36d527de
CW		 169 if (ret)
170 return ret;
b72f3acb 171
36d527de
CW		 172 intel_ring_emit(ring, cmd);
173 intel_ring_emit(ring, MI_NOOP);
174 intel_ring_advance(ring);
b72f3acb
CW		 175
176 return 0;
8187a2b7
ZN		 177}
178
8d315287
JB		 179/**
180 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
181 * implementing two workarounds on gen6. From section 1.4.7.1
182 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
183 *
184 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
185 * produced by non-pipelined state commands), software needs to first
186 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
187 * 0.
188 *
189 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
190 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
191 *
192 * And the workaround for these two requires this workaround first:
193 *
194 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
195 * BEFORE the pipe-control with a post-sync op and no write-cache
196 * flushes.
197 *
198 * And this last workaround is tricky because of the requirements on
199 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
200 * volume 2 part 1:
201 *
202 * "1 of the following must also be set:
203 * - Render Target Cache Flush Enable ([12] of DW1)
204 * - Depth Cache Flush Enable ([0] of DW1)
205 * - Stall at Pixel Scoreboard ([1] of DW1)
206 * - Depth Stall ([13] of DW1)
207 * - Post-Sync Operation ([13] of DW1)
208 * - Notify Enable ([8] of DW1)"
209 *
210 * The cache flushes require the workaround flush that triggered this
211 * one, so we can't use it. Depth stall would trigger the same.
212 * Post-sync nonzero is what triggered this second workaround, so we
213 * can't use that one either. Notify enable is IRQs, which aren't
214 * really our business. That leaves only stall at scoreboard.
215 */
216static int
f2cf1fcc 217intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
8d315287 218{
f2cf1fcc 219 struct intel_engine_cs *ring = req->ring;
18393f63 220 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 221 int ret;
222
5fb9de1a 223 ret = intel_ring_begin(req, 6);
8d315287
JB		 224 if (ret)
225 return ret;
226
227 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
228 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
229 PIPE_CONTROL_STALL_AT_SCOREBOARD);
230 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
231 intel_ring_emit(ring, 0); /* low dword */
232 intel_ring_emit(ring, 0); /* high dword */
233 intel_ring_emit(ring, MI_NOOP);
234 intel_ring_advance(ring);
235
5fb9de1a 236 ret = intel_ring_begin(req, 6);
8d315287
JB		 237 if (ret)
238 return ret;
239
240 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
241 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
242 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
243 intel_ring_emit(ring, 0);
244 intel_ring_emit(ring, 0);
245 intel_ring_emit(ring, MI_NOOP);
246 intel_ring_advance(ring);
247
248 return 0;
249}
250
251static int
a84c3ae1
JH		 252gen6_render_ring_flush(struct drm_i915_gem_request *req,
253 u32 invalidate_domains, u32 flush_domains)
8d315287 254{
a84c3ae1 255 struct intel_engine_cs *ring = req->ring;
8d315287 256 u32 flags = 0;
18393f63 257 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 258 int ret;
259
b3111509 260 /* Force SNB workarounds for PIPE_CONTROL flushes */
f2cf1fcc 261 ret = intel_emit_post_sync_nonzero_flush(req);
b3111509
PZ		 262 if (ret)
263 return ret;
264
8d315287
JB		 265 /* Just flush everything. Experiments have shown that reducing the
266 * number of bits based on the write domains has little performance
267 * impact.
268 */
7d54a904
CW		 269 if (flush_domains) {
270 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
271 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
272 /*
273 * Ensure that any following seqno writes only happen
274 * when the render cache is indeed flushed.
275 */
97f209bc 276 flags |= PIPE_CONTROL_CS_STALL;
7d54a904
CW		 277 }
278 if (invalidate_domains) {
279 flags |= PIPE_CONTROL_TLB_INVALIDATE;
280 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
281 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
282 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
283 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
284 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
285 /*
286 * TLB invalidate requires a post-sync write.
287 */
3ac78313 288 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
7d54a904 289 }
8d315287 290
5fb9de1a 291 ret = intel_ring_begin(req, 4);
8d315287
JB		 292 if (ret)
293 return ret;
294
6c6cf5aa 295 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
8d315287
JB		 296 intel_ring_emit(ring, flags);
297 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
6c6cf5aa 298 intel_ring_emit(ring, 0);
8d315287
JB		 299 intel_ring_advance(ring);
300
301 return 0;
302}
303
f3987631 304static int
f2cf1fcc 305gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
f3987631 306{
f2cf1fcc 307 struct intel_engine_cs *ring = req->ring;
f3987631
PZ		 308 int ret;
309
5fb9de1a 310 ret = intel_ring_begin(req, 4);
f3987631
PZ		 311 if (ret)
312 return ret;
313
314 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
315 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
316 PIPE_CONTROL_STALL_AT_SCOREBOARD);
317 intel_ring_emit(ring, 0);
318 intel_ring_emit(ring, 0);
319 intel_ring_advance(ring);
320
321 return 0;
322}
323
4772eaeb 324static int
a84c3ae1 325gen7_render_ring_flush(struct drm_i915_gem_request *req,
4772eaeb
PZ		 326 u32 invalidate_domains, u32 flush_domains)
327{
a84c3ae1 328 struct intel_engine_cs *ring = req->ring;
4772eaeb 329 u32 flags = 0;
18393f63 330 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
4772eaeb
PZ		 331 int ret;
332
f3987631
PZ		 333 /*
334 * Ensure that any following seqno writes only happen when the render
335 * cache is indeed flushed.
336 *
337 * Workaround: 4th PIPE_CONTROL command (except the ones with only
338 * read-cache invalidate bits set) must have the CS_STALL bit set. We
339 * don't try to be clever and just set it unconditionally.
340 */
341 flags |= PIPE_CONTROL_CS_STALL;
342
4772eaeb
PZ		 343 /* Just flush everything. Experiments have shown that reducing the
344 * number of bits based on the write domains has little performance
345 * impact.
346 */
347 if (flush_domains) {
348 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
349 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
4772eaeb
PZ		 350 }
351 if (invalidate_domains) {
352 flags |= PIPE_CONTROL_TLB_INVALIDATE;
353 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
354 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
355 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
356 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
357 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
148b83d0 358 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
4772eaeb
PZ		 359 /*
360 * TLB invalidate requires a post-sync write.
361 */
362 flags |= PIPE_CONTROL_QW_WRITE;
b9e1faa7 363 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
f3987631 364
add284a3
CW		 365 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
366
f3987631
PZ		 367 /* Workaround: we must issue a pipe_control with CS-stall bit
368 * set before a pipe_control command that has the state cache
369 * invalidate bit set. */
f2cf1fcc 370 gen7_render_ring_cs_stall_wa(req);
4772eaeb
PZ		 371 }
372
5fb9de1a 373 ret = intel_ring_begin(req, 4);
4772eaeb
PZ		 374 if (ret)
375 return ret;
376
377 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
378 intel_ring_emit(ring, flags);
b9e1faa7 379 intel_ring_emit(ring, scratch_addr);
4772eaeb
PZ		 380 intel_ring_emit(ring, 0);
381 intel_ring_advance(ring);
382
383 return 0;
384}
385
884ceace 386static int
f2cf1fcc 387gen8_emit_pipe_control(struct drm_i915_gem_request *req,
884ceace
KG		 388 u32 flags, u32 scratch_addr)
389{
f2cf1fcc 390 struct intel_engine_cs *ring = req->ring;
884ceace
KG		 391 int ret;
392
5fb9de1a 393 ret = intel_ring_begin(req, 6);
884ceace
KG		 394 if (ret)
395 return ret;
396
397 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
398 intel_ring_emit(ring, flags);
399 intel_ring_emit(ring, scratch_addr);
400 intel_ring_emit(ring, 0);
401 intel_ring_emit(ring, 0);
402 intel_ring_emit(ring, 0);
403 intel_ring_advance(ring);
404
405 return 0;
406}
407
a5f3d68e 408static int
a84c3ae1 409gen8_render_ring_flush(struct drm_i915_gem_request *req,
a5f3d68e
BW		 410 u32 invalidate_domains, u32 flush_domains)
411{
412 u32 flags = 0;
f2cf1fcc 413 u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
02c9f7e3 414 int ret;
a5f3d68e
BW		 415
416 flags |= PIPE_CONTROL_CS_STALL;
417
418 if (flush_domains) {
419 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
420 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
421 }
422 if (invalidate_domains) {
423 flags |= PIPE_CONTROL_TLB_INVALIDATE;
424 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
425 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
426 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
427 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
428 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
429 flags |= PIPE_CONTROL_QW_WRITE;
430 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
02c9f7e3
KG		 431
432 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
f2cf1fcc 433 ret = gen8_emit_pipe_control(req,
02c9f7e3
KG		 434 PIPE_CONTROL_CS_STALL |
435 PIPE_CONTROL_STALL_AT_SCOREBOARD,
436 0);
437 if (ret)
438 return ret;
a5f3d68e
BW		 439 }
440
f2cf1fcc 441 return gen8_emit_pipe_control(req, flags, scratch_addr);
a5f3d68e
BW		 442}
443
a4872ba6 444static void ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 445 u32 value)
d46eefa2 446{
4640c4ff 447 struct drm_i915_private *dev_priv = ring->dev->dev_private;
297b0c5b 448 I915_WRITE_TAIL(ring, value);
d46eefa2
XH		 449}
450
a4872ba6 451u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
8187a2b7 452{
4640c4ff 453 struct drm_i915_private *dev_priv = ring->dev->dev_private;
50877445 454 u64 acthd;
8187a2b7 455
50877445
CW		 456 if (INTEL_INFO(ring->dev)->gen >= 8)
457 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
458 RING_ACTHD_UDW(ring->mmio_base));
459 else if (INTEL_INFO(ring->dev)->gen >= 4)
460 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
461 else
462 acthd = I915_READ(ACTHD);
463
464 return acthd;
8187a2b7
ZN		 465}
466
a4872ba6 467static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
035dc1e0
DV		 468{
469 struct drm_i915_private *dev_priv = ring->dev->dev_private;
470 u32 addr;
471
472 addr = dev_priv->status_page_dmah->busaddr;
473 if (INTEL_INFO(ring->dev)->gen >= 4)
474 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
475 I915_WRITE(HWS_PGA, addr);
476}
477
af75f269
DL		 478static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
479{
480 struct drm_device *dev = ring->dev;
481 struct drm_i915_private *dev_priv = ring->dev->dev_private;
482 u32 mmio = 0;
483
484 /* The ring status page addresses are no longer next to the rest of
485 * the ring registers as of gen7.
486 */
487 if (IS_GEN7(dev)) {
488 switch (ring->id) {
489 case RCS:
490 mmio = RENDER_HWS_PGA_GEN7;
491 break;
492 case BCS:
493 mmio = BLT_HWS_PGA_GEN7;
494 break;
495 /*
496 * VCS2 actually doesn't exist on Gen7. Only shut up
497 * gcc switch check warning
498 */
499 case VCS2:
500 case VCS:
501 mmio = BSD_HWS_PGA_GEN7;
502 break;
503 case VECS:
504 mmio = VEBOX_HWS_PGA_GEN7;
505 break;
506 }
507 } else if (IS_GEN6(ring->dev)) {
508 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
509 } else {
510 /* XXX: gen8 returns to sanity */
511 mmio = RING_HWS_PGA(ring->mmio_base);
512 }
513
514 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
515 POSTING_READ(mmio);
516
517 /*
518 * Flush the TLB for this page
519 *
520 * FIXME: These two bits have disappeared on gen8, so a question
521 * arises: do we still need this and if so how should we go about
522 * invalidating the TLB?
523 */
524 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
525 u32 reg = RING_INSTPM(ring->mmio_base);
526
527 /* ring should be idle before issuing a sync flush*/
528 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
529
530 I915_WRITE(reg,
531 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
532 INSTPM_SYNC_FLUSH));
533 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
534 1000))
535 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
536 ring->name);
537 }
538}
539
a4872ba6 540static bool stop_ring(struct intel_engine_cs *ring)
8187a2b7 541{
9991ae78 542 struct drm_i915_private *dev_priv = to_i915(ring->dev);
8187a2b7 543
9991ae78
CW		 544 if (!IS_GEN2(ring->dev)) {
545 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
403bdd10
DV		 546 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
547 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
9bec9b13
CW		 548 /* Sometimes we observe that the idle flag is not
549 * set even though the ring is empty. So double
550 * check before giving up.
551 */
552 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
553 return false;
9991ae78
CW		 554 }
555 }
b7884eb4 556
7f2ab699 557 I915_WRITE_CTL(ring, 0);
570ef608 558 I915_WRITE_HEAD(ring, 0);
78501eac 559 ring->write_tail(ring, 0);
8187a2b7 560
9991ae78
CW		 561 if (!IS_GEN2(ring->dev)) {
562 (void)I915_READ_CTL(ring);
563 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
564 }
a51435a3 565
9991ae78
CW		 566 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
567}
8187a2b7 568
a4872ba6 569static int init_ring_common(struct intel_engine_cs *ring)
9991ae78
CW		 570{
571 struct drm_device *dev = ring->dev;
572 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0
OM		 573 struct intel_ringbuffer *ringbuf = ring->buffer;
574 struct drm_i915_gem_object *obj = ringbuf->obj;
9991ae78
CW		 575 int ret = 0;
576
59bad947 577 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9991ae78
CW		 578
579 if (!stop_ring(ring)) {
580 /* G45 ring initialization often fails to reset head to zero */
6fd0d56e
CW		 581 DRM_DEBUG_KMS("%s head not reset to zero "
582 "ctl %08x head %08x tail %08x start %08x\n",
583 ring->name,
584 I915_READ_CTL(ring),
585 I915_READ_HEAD(ring),
586 I915_READ_TAIL(ring),
587 I915_READ_START(ring));
8187a2b7 588
9991ae78 589 if (!stop_ring(ring)) {
6fd0d56e
CW		 590 DRM_ERROR("failed to set %s head to zero "
591 "ctl %08x head %08x tail %08x start %08x\n",
592 ring->name,
593 I915_READ_CTL(ring),
594 I915_READ_HEAD(ring),
595 I915_READ_TAIL(ring),
596 I915_READ_START(ring));
9991ae78
CW		 597 ret = -EIO;
598 goto out;
6fd0d56e 599 }
8187a2b7
ZN		 600 }
601
9991ae78
CW		 602 if (I915_NEED_GFX_HWS(dev))
603 intel_ring_setup_status_page(ring);
604 else
605 ring_setup_phys_status_page(ring);
606
ece4a17d
JK		 607 /* Enforce ordering by reading HEAD register back */
608 I915_READ_HEAD(ring);
609
0d8957c8
DV		 610 /* Initialize the ring. This must happen _after_ we've cleared the ring
611 * registers with the above sequence (the readback of the HEAD registers
612 * also enforces ordering), otherwise the hw might lose the new ring
613 * register values. */
f343c5f6 614 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
95468892
CW		 615
616 /* WaClearRingBufHeadRegAtInit:ctg,elk */
617 if (I915_READ_HEAD(ring))
618 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
619 ring->name, I915_READ_HEAD(ring));
620 I915_WRITE_HEAD(ring, 0);
621 (void)I915_READ_HEAD(ring);
622
7f2ab699 623 I915_WRITE_CTL(ring,
93b0a4e0 624 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
5d031e5b 625 | RING_VALID);
8187a2b7 626
8187a2b7 627 /* If the head is still not zero, the ring is dead */
f01db988 628 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
f343c5f6 629 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
f01db988 630 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
e74cfed5 631 DRM_ERROR("%s initialization failed "
48e48a0b
CW		 632 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
633 ring->name,
634 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
635 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
636 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
b7884eb4
DV		 637 ret = -EIO;
638 goto out;
8187a2b7
ZN		 639 }
640
ebd0fd4b 641 ringbuf->last_retired_head = -1;
5c6c6003
CW		 642 ringbuf->head = I915_READ_HEAD(ring);
643 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
ebd0fd4b 644 intel_ring_update_space(ringbuf);
1ec14ad3 645
50f018df
CW		 646 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
647
b7884eb4 648out:
59bad947 649 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b7884eb4
DV		 650
651 return ret;
8187a2b7
ZN		 652}
653
9b1136d5
OM		 654void
655intel_fini_pipe_control(struct intel_engine_cs *ring)
656{
657 struct drm_device *dev = ring->dev;
658
659 if (ring->scratch.obj == NULL)
660 return;
661
662 if (INTEL_INFO(dev)->gen >= 5) {
663 kunmap(sg_page(ring->scratch.obj->pages->sgl));
664 i915_gem_object_ggtt_unpin(ring->scratch.obj);
665 }
666
667 drm_gem_object_unreference(&ring->scratch.obj->base);
668 ring->scratch.obj = NULL;
669}
670
671int
672intel_init_pipe_control(struct intel_engine_cs *ring)
c6df541c 673{
c6df541c
CW		 674 int ret;
675
bfc882b4 676 WARN_ON(ring->scratch.obj);
c6df541c 677
0d1aacac
CW		 678 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
679 if (ring->scratch.obj == NULL) {
c6df541c
CW		 680 DRM_ERROR("Failed to allocate seqno page\n");
681 ret = -ENOMEM;
682 goto err;
683 }
e4ffd173 684
a9cc726c
DV		 685 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
686 if (ret)
687 goto err_unref;
c6df541c 688
1ec9e26d 689 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
c6df541c
CW		 690 if (ret)
691 goto err_unref;
692
0d1aacac
CW		 693 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
694 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
695 if (ring->scratch.cpu_page == NULL) {
56b085a0 696 ret = -ENOMEM;
c6df541c 697 goto err_unpin;
56b085a0 698 }
c6df541c 699
2b1086cc 700 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
0d1aacac 701 ring->name, ring->scratch.gtt_offset);
c6df541c
CW		 702 return 0;
703
704err_unpin:
d7f46fc4 705 i915_gem_object_ggtt_unpin(ring->scratch.obj);
c6df541c 706err_unref:
0d1aacac 707 drm_gem_object_unreference(&ring->scratch.obj->base);
c6df541c 708err:
c6df541c
CW		 709 return ret;
710}
711
e2be4faf 712static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
86d7f238 713{
7225342a 714 int ret, i;
e2be4faf 715 struct intel_engine_cs *ring = req->ring;
888b5995
AS		 716 struct drm_device *dev = ring->dev;
717 struct drm_i915_private *dev_priv = dev->dev_private;
7225342a 718 struct i915_workarounds *w = &dev_priv->workarounds;
888b5995 719
02235808 720 if (w->count == 0)
7225342a 721 return 0;
888b5995 722
7225342a 723 ring->gpu_caches_dirty = true;
4866d729 724 ret = intel_ring_flush_all_caches(req);
7225342a
MK		 725 if (ret)
726 return ret;
888b5995 727
5fb9de1a 728 ret = intel_ring_begin(req, (w->count * 2 + 2));
7225342a
MK		 729 if (ret)
730 return ret;
731
22a916aa 732 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
7225342a 733 for (i = 0; i < w->count; i++) {
7225342a
MK		 734 intel_ring_emit(ring, w->reg[i].addr);
735 intel_ring_emit(ring, w->reg[i].value);
736 }
22a916aa 737 intel_ring_emit(ring, MI_NOOP);
7225342a
MK		 738
739 intel_ring_advance(ring);
740
741 ring->gpu_caches_dirty = true;
4866d729 742 ret = intel_ring_flush_all_caches(req);
7225342a
MK		 743 if (ret)
744 return ret;
888b5995 745
7225342a 746 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
888b5995 747
7225342a 748 return 0;
86d7f238
AS		 749}
750
8753181e 751static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
8f0e2b9d
DV		 752{
753 int ret;
754
e2be4faf 755 ret = intel_ring_workarounds_emit(req);
8f0e2b9d
DV		 756 if (ret != 0)
757 return ret;
758
be01363f 759 ret = i915_gem_render_state_init(req);
8f0e2b9d
DV		 760 if (ret)
761 DRM_ERROR("init render state: %d\n", ret);
762
763 return ret;
764}
765
7225342a 766static int wa_add(struct drm_i915_private *dev_priv,
cf4b0de6 767 const u32 addr, const u32 mask, const u32 val)
7225342a
MK		 768{
769 const u32 idx = dev_priv->workarounds.count;
770
771 if (WARN_ON(idx >= I915_MAX_WA_REGS))
772 return -ENOSPC;
773
774 dev_priv->workarounds.reg[idx].addr = addr;
775 dev_priv->workarounds.reg[idx].value = val;
776 dev_priv->workarounds.reg[idx].mask = mask;
777
778 dev_priv->workarounds.count++;
779
780 return 0;
86d7f238
AS		 781}
782
ca5a0fbd 783#define WA_REG(addr, mask, val) do { \
cf4b0de6 784 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
7225342a
MK		 785 if (r) \
786 return r; \
ca5a0fbd 787 } while (0)
7225342a
MK		 788
789#define WA_SET_BIT_MASKED(addr, mask) \
26459343 790 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
7225342a
MK		 791
792#define WA_CLR_BIT_MASKED(addr, mask) \
26459343 793 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
7225342a 794
98533251 795#define WA_SET_FIELD_MASKED(addr, mask, value) \
cf4b0de6 796 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
7225342a 797
cf4b0de6
DL		 798#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
799#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
7225342a 800
cf4b0de6 801#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
7225342a 802
e9a64ada
AS		 803static int gen8_init_workarounds(struct intel_engine_cs *ring)
804{
68c6198b
AS		 805 struct drm_device *dev = ring->dev;
806 struct drm_i915_private *dev_priv = dev->dev_private;
807
808 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
e9a64ada 809
717d84d6
AS		 810 /* WaDisableAsyncFlipPerfMode:bdw,chv */
811 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
812
d0581194
AS		 813 /* WaDisablePartialInstShootdown:bdw,chv */
814 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
815 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
816
a340af58
AS		 817 /* Use Force Non-Coherent whenever executing a 3D context. This is a
818 * workaround for for a possible hang in the unlikely event a TLB
819 * invalidation occurs during a PSD flush.
820 */
821 /* WaForceEnableNonCoherent:bdw,chv */
120f5d28 822 /* WaHdcDisableFetchWhenMasked:bdw,chv */
a340af58 823 WA_SET_BIT_MASKED(HDC_CHICKEN0,
120f5d28 824 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
a340af58
AS		 825 HDC_FORCE_NON_COHERENT);
826
6def8fdd
AS		 827 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
828 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
829 * polygons in the same 8x4 pixel/sample area to be processed without
830 * stalling waiting for the earlier ones to write to Hierarchical Z
831 * buffer."
832 *
833 * This optimization is off by default for BDW and CHV; turn it on.
834 */
835 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
836
48404636
AS		 837 /* Wa4x4STCOptimizationDisable:bdw,chv */
838 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
839
7eebcde6
AS		 840 /*
841 * BSpec recommends 8x4 when MSAA is used,
842 * however in practice 16x4 seems fastest.
843 *
844 * Note that PS/WM thread counts depend on the WIZ hashing
845 * disable bit, which we don't touch here, but it's good
846 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
847 */
848 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
849 GEN6_WIZ_HASHING_MASK,
850 GEN6_WIZ_HASHING_16x4);
851
e9a64ada
AS		 852 return 0;
853}
854
00e1e623 855static int bdw_init_workarounds(struct intel_engine_cs *ring)
86d7f238 856{
e9a64ada 857 int ret;
888b5995
AS		 858 struct drm_device *dev = ring->dev;
859 struct drm_i915_private *dev_priv = dev->dev_private;
86d7f238 860
e9a64ada
AS		 861 ret = gen8_init_workarounds(ring);
862 if (ret)
863 return ret;
864
101b376d 865 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
d0581194 866 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
86d7f238 867
101b376d 868 /* WaDisableDopClockGating:bdw */
7225342a
MK		 869 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
870 DOP_CLOCK_GATING_DISABLE);
86d7f238 871
7225342a
MK		 872 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
873 GEN8_SAMPLER_POWER_BYPASS_DIS);
86d7f238 874
7225342a 875 WA_SET_BIT_MASKED(HDC_CHICKEN0,
35cb6f3b
DL		 876 /* WaForceContextSaveRestoreNonCoherent:bdw */
877 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
35cb6f3b 878 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
7225342a 879 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
86d7f238 880
86d7f238
AS		 881 return 0;
882}
883
00e1e623
VS		 884static int chv_init_workarounds(struct intel_engine_cs *ring)
885{
e9a64ada 886 int ret;
00e1e623
VS		 887 struct drm_device *dev = ring->dev;
888 struct drm_i915_private *dev_priv = dev->dev_private;
889
e9a64ada
AS		 890 ret = gen8_init_workarounds(ring);
891 if (ret)
892 return ret;
893
00e1e623 894 /* WaDisableThreadStallDopClockGating:chv */
d0581194 895 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
00e1e623 896
d60de81d
KG		 897 /* Improve HiZ throughput on CHV. */
898 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
899
7225342a
MK		 900 return 0;
901}
902
3b106531
HN		 903static int gen9_init_workarounds(struct intel_engine_cs *ring)
904{
ab0dfafe
HN		 905 struct drm_device *dev = ring->dev;
906 struct drm_i915_private *dev_priv = dev->dev_private;
8ea6f892 907 uint32_t tmp;
ab0dfafe 908
9c4cbf82
MK		 909 /* WaEnableLbsSlaRetryTimerDecrement:skl */
910 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
911 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
912
913 /* WaDisableKillLogic:bxt,skl */
914 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
915 ECOCHK_DIS_TLB);
916
b0e6f6d4 917 /* WaDisablePartialInstShootdown:skl,bxt */
ab0dfafe
HN		 918 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
919 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
920
a119a6e6 921 /* Syncing dependencies between camera and graphics:skl,bxt */
8424171e
NH		 922 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
923 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
924
e87a005d
JN		 925 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
926 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
927 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
a86eb582
DL		 928 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
929 GEN9_DG_MIRROR_FIX_ENABLE);
1de4582f 930
e87a005d
JN		 931 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
932 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
933 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
183c6dac
DL		 934 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
935 GEN9_RHWO_OPTIMIZATION_DISABLE);
9b01435d
AS		 936 /*
937 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
938 * but we do that in per ctx batchbuffer as there is an issue
939 * with this register not getting restored on ctx restore
940 */
183c6dac
DL		 941 }
942
e87a005d
JN		 943 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
944 if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER) || IS_BROXTON(dev))
cac23df4
NH		 945 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
946 GEN9_ENABLE_YV12_BUGFIX);
cac23df4 947
5068368c 948 /* Wa4x4STCOptimizationDisable:skl,bxt */
27160c96 949 /* WaDisablePartialResolveInVc:skl,bxt */
60294683
AS		 950 WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
951 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
9370cd98 952
16be17af 953 /* WaCcsTlbPrefetchDisable:skl,bxt */
e2db7071
DL		 954 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
955 GEN9_CCS_TLB_PREFETCH_ENABLE);
956
5a2ae95e 957 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
e87a005d
JN		 958 if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) ||
959 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
38a39a7b
BW		 960 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
961 PIXEL_MASK_CAMMING_DISABLE);
962
8ea6f892
ID		 963 /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
964 tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
e87a005d
JN		 965 if (IS_SKL_REVID(dev, SKL_REVID_F0, SKL_REVID_F0) ||
966 IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
8ea6f892
ID		 967 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
968 WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
969
8c761609 970 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
e87a005d 971 if (IS_SKYLAKE(dev) || IS_BXT_REVID(dev, 0, BXT_REVID_B0))
8c761609
AS		 972 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
973 GEN8_SAMPLER_POWER_BYPASS_DIS);
8c761609 974
6b6d5626
RB		 975 /* WaDisableSTUnitPowerOptimization:skl,bxt */
976 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
977
3b106531
HN		 978 return 0;
979}
980
b7668791
DL		 981static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
982{
983 struct drm_device *dev = ring->dev;
984 struct drm_i915_private *dev_priv = dev->dev_private;
985 u8 vals[3] = { 0, 0, 0 };
986 unsigned int i;
987
988 for (i = 0; i < 3; i++) {
989 u8 ss;
990
991 /*
992 * Only consider slices where one, and only one, subslice has 7
993 * EUs
994 */
995 if (hweight8(dev_priv->info.subslice_7eu[i]) != 1)
996 continue;
997
998 /*
999 * subslice_7eu[i] != 0 (because of the check above) and
1000 * ss_max == 4 (maximum number of subslices possible per slice)
1001 *
1002 * -> 0 <= ss <= 3;
1003 */
1004 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1005 vals[i] = 3 - ss;
1006 }
1007
1008 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1009 return 0;
1010
1011 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1012 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1013 GEN9_IZ_HASHING_MASK(2) |
1014 GEN9_IZ_HASHING_MASK(1) |
1015 GEN9_IZ_HASHING_MASK(0),
1016 GEN9_IZ_HASHING(2, vals[2]) |
1017 GEN9_IZ_HASHING(1, vals[1]) |
1018 GEN9_IZ_HASHING(0, vals[0]));
1019
1020 return 0;
1021}
1022
8d205494
DL		 1023static int skl_init_workarounds(struct intel_engine_cs *ring)
1024{
aa0011a8 1025 int ret;
d0bbbc4f
DL		 1026 struct drm_device *dev = ring->dev;
1027 struct drm_i915_private *dev_priv = dev->dev_private;
1028
aa0011a8
AS		 1029 ret = gen9_init_workarounds(ring);
1030 if (ret)
1031 return ret;
8d205494 1032
e87a005d 1033 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
9c4cbf82
MK		 1034 /* WaDisableHDCInvalidation:skl */
1035 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
1036 BDW_DISABLE_HDC_INVALIDATION);
1037
1038 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1039 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1040 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1041 }
1042
1043 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1044 * involving this register should also be added to WA batch as required.
1045 */
e87a005d 1046 if (IS_SKL_REVID(dev, 0, SKL_REVID_E0))
9c4cbf82
MK		 1047 /* WaDisableLSQCROPERFforOCL:skl */
1048 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1049 GEN8_LQSC_RO_PERF_DIS);
1050
1051 /* WaEnableGapsTsvCreditFix:skl */
e87a005d 1052 if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) {
9c4cbf82
MK		 1053 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1054 GEN9_GAPS_TSV_CREDIT_DISABLE));
1055 }
1056
d0bbbc4f 1057 /* WaDisablePowerCompilerClockGating:skl */
e87a005d 1058 if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0))
d0bbbc4f
DL		 1059 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1060 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1061
e87a005d 1062 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
b62adbd1
NH		 1063 /*
1064 *Use Force Non-Coherent whenever executing a 3D context. This
1065 * is a workaround for a possible hang in the unlikely event
1066 * a TLB invalidation occurs during a PSD flush.
1067 */
1068 /* WaForceEnableNonCoherent:skl */
1069 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1070 HDC_FORCE_NON_COHERENT);
1071 }
1072
e87a005d
JN		 1073 /* WaBarrierPerformanceFixDisable:skl */
1074 if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0))
5b6fd12a
VS		 1075 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1076 HDC_FENCE_DEST_SLM_DISABLE |
1077 HDC_BARRIER_PERFORMANCE_DISABLE);
1078
9bd9dfb4 1079 /* WaDisableSbeCacheDispatchPortSharing:skl */
e87a005d 1080 if (IS_SKL_REVID(dev, 0, SKL_REVID_F0))
9bd9dfb4
MK		 1081 WA_SET_BIT_MASKED(
1082 GEN7_HALF_SLICE_CHICKEN1,
1083 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
9bd9dfb4 1084
b7668791 1085 return skl_tune_iz_hashing(ring);
7225342a
MK		 1086}
1087
cae0437f
NH		 1088static int bxt_init_workarounds(struct intel_engine_cs *ring)
1089{
aa0011a8 1090 int ret;
dfb601e6
NH		 1091 struct drm_device *dev = ring->dev;
1092 struct drm_i915_private *dev_priv = dev->dev_private;
1093
aa0011a8
AS		 1094 ret = gen9_init_workarounds(ring);
1095 if (ret)
1096 return ret;
cae0437f 1097
9c4cbf82
MK		 1098 /* WaStoreMultiplePTEenable:bxt */
1099 /* This is a requirement according to Hardware specification */
e87a005d 1100 if (IS_BXT_REVID(dev, 0, BXT_REVID_A0))
9c4cbf82
MK		 1101 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1102
1103 /* WaSetClckGatingDisableMedia:bxt */
e87a005d 1104 if (IS_BXT_REVID(dev, 0, BXT_REVID_A0)) {
9c4cbf82
MK		 1105 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1106 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1107 }
1108
dfb601e6
NH		 1109 /* WaDisableThreadStallDopClockGating:bxt */
1110 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1111 STALL_DOP_GATING_DISABLE);
1112
983b4b9d 1113 /* WaDisableSbeCacheDispatchPortSharing:bxt */
e87a005d 1114 if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
983b4b9d
NH		 1115 WA_SET_BIT_MASKED(
1116 GEN7_HALF_SLICE_CHICKEN1,
1117 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1118 }
1119
cae0437f
NH		 1120 return 0;
1121}
1122
771b9a53 1123int init_workarounds_ring(struct intel_engine_cs *ring)
7225342a
MK		 1124{
1125 struct drm_device *dev = ring->dev;
1126 struct drm_i915_private *dev_priv = dev->dev_private;
1127
1128 WARN_ON(ring->id != RCS);
1129
1130 dev_priv->workarounds.count = 0;
1131
1132 if (IS_BROADWELL(dev))
1133 return bdw_init_workarounds(ring);
1134
1135 if (IS_CHERRYVIEW(dev))
1136 return chv_init_workarounds(ring);
00e1e623 1137
8d205494
DL		 1138 if (IS_SKYLAKE(dev))
1139 return skl_init_workarounds(ring);
cae0437f
NH		 1140
1141 if (IS_BROXTON(dev))
1142 return bxt_init_workarounds(ring);
3b106531 1143
00e1e623
VS		 1144 return 0;
1145}
1146
a4872ba6 1147static int init_render_ring(struct intel_engine_cs *ring)
8187a2b7 1148{
78501eac 1149 struct drm_device *dev = ring->dev;
1ec14ad3 1150 struct drm_i915_private *dev_priv = dev->dev_private;
78501eac 1151 int ret = init_ring_common(ring);
9c33baa6
KZ		 1152 if (ret)
1153 return ret;
a69ffdbf 1154
61a563a2
AG		 1155 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1156 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
6b26c86d 1157 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1c8c38c5
CW		 1158
1159 /* We need to disable the AsyncFlip performance optimisations in order
1160 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1161 * programmed to '1' on all products.
8693a824 1162 *
2441f877 1163 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1c8c38c5 1164 */
2441f877 1165 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1c8c38c5
CW		 1166 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1167
f05bb0c7 1168 /* Required for the hardware to program scanline values for waiting */
01fa0302 1169 /* WaEnableFlushTlbInvalidationMode:snb */
f05bb0c7
CW		 1170 if (INTEL_INFO(dev)->gen == 6)
1171 I915_WRITE(GFX_MODE,
aa83e30d 1172 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
f05bb0c7 1173
01fa0302 1174 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1c8c38c5
CW		 1175 if (IS_GEN7(dev))
1176 I915_WRITE(GFX_MODE_GEN7,
01fa0302 1177 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1c8c38c5 1178 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
78501eac 1179
5e13a0c5 1180 if (IS_GEN6(dev)) {
3a69ddd6
KG		 1181 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1182 * "If this bit is set, STCunit will have LRA as replacement
1183 * policy. [...] This bit must be reset. LRA replacement
1184 * policy is not supported."
1185 */
1186 I915_WRITE(CACHE_MODE_0,
5e13a0c5 1187 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
84f9f938
BW		 1188 }
1189
9cc83020 1190 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
6b26c86d 1191 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
84f9f938 1192
040d2baa 1193 if (HAS_L3_DPF(dev))
35a85ac6 1194 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e 1195
7225342a 1196 return init_workarounds_ring(ring);
8187a2b7
ZN		 1197}
1198
a4872ba6 1199static void render_ring_cleanup(struct intel_engine_cs *ring)
c6df541c 1200{
b45305fc 1201 struct drm_device *dev = ring->dev;
3e78998a
BW		 1202 struct drm_i915_private *dev_priv = dev->dev_private;
1203
1204 if (dev_priv->semaphore_obj) {
1205 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1206 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1207 dev_priv->semaphore_obj = NULL;
1208 }
b45305fc 1209
9b1136d5 1210 intel_fini_pipe_control(ring);
c6df541c
CW		 1211}
1212
f7169687 1213static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
3e78998a
BW		 1214 unsigned int num_dwords)
1215{
1216#define MBOX_UPDATE_DWORDS 8
f7169687 1217 struct intel_engine_cs *signaller = signaller_req->ring;
3e78998a
BW		 1218 struct drm_device *dev = signaller->dev;
1219 struct drm_i915_private *dev_priv = dev->dev_private;
1220 struct intel_engine_cs *waiter;
1221 int i, ret, num_rings;
1222
1223 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1224 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1225#undef MBOX_UPDATE_DWORDS
1226
5fb9de1a 1227 ret = intel_ring_begin(signaller_req, num_dwords);
3e78998a
BW		 1228 if (ret)
1229 return ret;
1230
1231 for_each_ring(waiter, dev_priv, i) {
6259cead 1232 u32 seqno;
3e78998a
BW		 1233 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1234 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1235 continue;
1236
f7169687 1237 seqno = i915_gem_request_get_seqno(signaller_req);
3e78998a
BW		 1238 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1239 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1240 PIPE_CONTROL_QW_WRITE |
1241 PIPE_CONTROL_FLUSH_ENABLE);
1242 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1243 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1244 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1245 intel_ring_emit(signaller, 0);
1246 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1247 MI_SEMAPHORE_TARGET(waiter->id));
1248 intel_ring_emit(signaller, 0);
1249 }
1250
1251 return 0;
1252}
1253
f7169687 1254static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
3e78998a
BW		 1255 unsigned int num_dwords)
1256{
1257#define MBOX_UPDATE_DWORDS 6
f7169687 1258 struct intel_engine_cs *signaller = signaller_req->ring;
3e78998a
BW		 1259 struct drm_device *dev = signaller->dev;
1260 struct drm_i915_private *dev_priv = dev->dev_private;
1261 struct intel_engine_cs *waiter;
1262 int i, ret, num_rings;
1263
1264 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1265 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1266#undef MBOX_UPDATE_DWORDS
1267
5fb9de1a 1268 ret = intel_ring_begin(signaller_req, num_dwords);
3e78998a
BW		 1269 if (ret)
1270 return ret;
1271
1272 for_each_ring(waiter, dev_priv, i) {
6259cead 1273 u32 seqno;
3e78998a
BW		 1274 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1275 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1276 continue;
1277
f7169687 1278 seqno = i915_gem_request_get_seqno(signaller_req);
3e78998a
BW		 1279 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1280 MI_FLUSH_DW_OP_STOREDW);
1281 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1282 MI_FLUSH_DW_USE_GTT);
1283 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1284 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1285 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1286 MI_SEMAPHORE_TARGET(waiter->id));
1287 intel_ring_emit(signaller, 0);
1288 }
1289
1290 return 0;
1291}
1292
f7169687 1293static int gen6_signal(struct drm_i915_gem_request *signaller_req,
024a43e1 1294 unsigned int num_dwords)
1ec14ad3 1295{
f7169687 1296 struct intel_engine_cs *signaller = signaller_req->ring;
024a43e1
BW		 1297 struct drm_device *dev = signaller->dev;
1298 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1299 struct intel_engine_cs *useless;
a1444b79 1300 int i, ret, num_rings;
78325f2d 1301
a1444b79
BW		 1302#define MBOX_UPDATE_DWORDS 3
1303 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1304 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1305#undef MBOX_UPDATE_DWORDS
024a43e1 1306
5fb9de1a 1307 ret = intel_ring_begin(signaller_req, num_dwords);
024a43e1
BW		 1308 if (ret)
1309 return ret;
024a43e1 1310
78325f2d
BW		 1311 for_each_ring(useless, dev_priv, i) {
1312 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1313 if (mbox_reg != GEN6_NOSYNC) {
f7169687 1314 u32 seqno = i915_gem_request_get_seqno(signaller_req);
78325f2d
BW		 1315 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1316 intel_ring_emit(signaller, mbox_reg);
6259cead 1317 intel_ring_emit(signaller, seqno);
78325f2d
BW		 1318 }
1319 }
024a43e1 1320
a1444b79
BW		 1321 /* If num_dwords was rounded, make sure the tail pointer is correct */
1322 if (num_rings % 2 == 0)
1323 intel_ring_emit(signaller, MI_NOOP);
1324
024a43e1 1325 return 0;
1ec14ad3
CW		 1326}
1327
c8c99b0f
BW		 1328/**
1329 * gen6_add_request - Update the semaphore mailbox registers
ee044a88
JH		 1330 *
1331 * @request - request to write to the ring
c8c99b0f
BW		 1332 *
1333 * Update the mailbox registers in the *other* rings with the current seqno.
1334 * This acts like a signal in the canonical semaphore.
1335 */
1ec14ad3 1336static int
ee044a88 1337gen6_add_request(struct drm_i915_gem_request *req)
1ec14ad3 1338{
ee044a88 1339 struct intel_engine_cs *ring = req->ring;
024a43e1 1340 int ret;
52ed2325 1341
707d9cf9 1342 if (ring->semaphore.signal)
f7169687 1343 ret = ring->semaphore.signal(req, 4);
707d9cf9 1344 else
5fb9de1a 1345 ret = intel_ring_begin(req, 4);
707d9cf9 1346
1ec14ad3
CW		 1347 if (ret)
1348 return ret;
1349
1ec14ad3
CW		 1350 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1351 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
ee044a88 1352 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1ec14ad3 1353 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1354 __intel_ring_advance(ring);
1ec14ad3 1355
1ec14ad3
CW		 1356 return 0;
1357}
1358
f72b3435
MK		 1359static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1360 u32 seqno)
1361{
1362 struct drm_i915_private *dev_priv = dev->dev_private;
1363 return dev_priv->last_seqno < seqno;
1364}
1365
c8c99b0f
BW		 1366/**
1367 * intel_ring_sync - sync the waiter to the signaller on seqno
1368 *
1369 * @waiter - ring that is waiting
1370 * @signaller - ring which has, or will signal
1371 * @seqno - seqno which the waiter will block on
1372 */
5ee426ca
BW		 1373
1374static int
599d924c 1375gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
5ee426ca
BW		 1376 struct intel_engine_cs *signaller,
1377 u32 seqno)
1378{
599d924c 1379 struct intel_engine_cs *waiter = waiter_req->ring;
5ee426ca
BW		 1380 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1381 int ret;
1382
5fb9de1a 1383 ret = intel_ring_begin(waiter_req, 4);
5ee426ca
BW		 1384 if (ret)
1385 return ret;
1386
1387 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1388 MI_SEMAPHORE_GLOBAL_GTT |
bae4fcd2 1389 MI_SEMAPHORE_POLL |
5ee426ca
BW		 1390 MI_SEMAPHORE_SAD_GTE_SDD);
1391 intel_ring_emit(waiter, seqno);
1392 intel_ring_emit(waiter,
1393 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1394 intel_ring_emit(waiter,
1395 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1396 intel_ring_advance(waiter);
1397 return 0;
1398}
1399
c8c99b0f 1400static int
599d924c 1401gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
a4872ba6 1402 struct intel_engine_cs *signaller,
686cb5f9 1403 u32 seqno)
1ec14ad3 1404{
599d924c 1405 struct intel_engine_cs *waiter = waiter_req->ring;
c8c99b0f
BW		 1406 u32 dw1 = MI_SEMAPHORE_MBOX |
1407 MI_SEMAPHORE_COMPARE |
1408 MI_SEMAPHORE_REGISTER;
ebc348b2
BW		 1409 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1410 int ret;
1ec14ad3 1411
1500f7ea
BW		 1412 /* Throughout all of the GEM code, seqno passed implies our current
1413 * seqno is >= the last seqno executed. However for hardware the
1414 * comparison is strictly greater than.
1415 */
1416 seqno -= 1;
1417
ebc348b2 1418 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
686cb5f9 1419
5fb9de1a 1420 ret = intel_ring_begin(waiter_req, 4);
1ec14ad3
CW		 1421 if (ret)
1422 return ret;
1423
f72b3435
MK		 1424 /* If seqno wrap happened, omit the wait with no-ops */
1425 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
ebc348b2 1426 intel_ring_emit(waiter, dw1 | wait_mbox);
f72b3435
MK		 1427 intel_ring_emit(waiter, seqno);
1428 intel_ring_emit(waiter, 0);
1429 intel_ring_emit(waiter, MI_NOOP);
1430 } else {
1431 intel_ring_emit(waiter, MI_NOOP);
1432 intel_ring_emit(waiter, MI_NOOP);
1433 intel_ring_emit(waiter, MI_NOOP);
1434 intel_ring_emit(waiter, MI_NOOP);
1435 }
c8c99b0f 1436 intel_ring_advance(waiter);
1ec14ad3
CW		 1437
1438 return 0;
1439}
1440
c6df541c
CW		 1441#define PIPE_CONTROL_FLUSH(ring__, addr__) \
1442do { \
fcbc34e4
KG		 1443 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1444 PIPE_CONTROL_DEPTH_STALL); \
c6df541c
CW		 1445 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1446 intel_ring_emit(ring__, 0); \
1447 intel_ring_emit(ring__, 0); \
1448} while (0)
1449
1450static int
ee044a88 1451pc_render_add_request(struct drm_i915_gem_request *req)
c6df541c 1452{
ee044a88 1453 struct intel_engine_cs *ring = req->ring;
18393f63 1454 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
c6df541c
CW		 1455 int ret;
1456
1457 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1458 * incoherent with writes to memory, i.e. completely fubar,
1459 * so we need to use PIPE_NOTIFY instead.
1460 *
1461 * However, we also need to workaround the qword write
1462 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1463 * memory before requesting an interrupt.
1464 */
5fb9de1a 1465 ret = intel_ring_begin(req, 32);
c6df541c
CW		 1466 if (ret)
1467 return ret;
1468
fcbc34e4 1469 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1470 PIPE_CONTROL_WRITE_FLUSH |
1471 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
0d1aacac 1472 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
ee044a88 1473 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
c6df541c
CW		 1474 intel_ring_emit(ring, 0);
1475 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1476 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
c6df541c 1477 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1478 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1479 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1480 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1481 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1482 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1483 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1484 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1485 PIPE_CONTROL_FLUSH(ring, scratch_addr);
a71d8d94 1486
fcbc34e4 1487 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1488 PIPE_CONTROL_WRITE_FLUSH |
1489 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
c6df541c 1490 PIPE_CONTROL_NOTIFY);
0d1aacac 1491 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
ee044a88 1492 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
c6df541c 1493 intel_ring_emit(ring, 0);
09246732 1494 __intel_ring_advance(ring);
c6df541c 1495
c6df541c
CW		 1496 return 0;
1497}
1498
4cd53c0c 1499static u32
a4872ba6 1500gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
4cd53c0c 1501{
4cd53c0c
DV		 1502 /* Workaround to force correct ordering between irq and seqno writes on
1503 * ivb (and maybe also on snb) by reading from a CS register (like
1504 * ACTHD) before reading the status page. */
50877445
CW		 1505 if (!lazy_coherency) {
1506 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1507 POSTING_READ(RING_ACTHD(ring->mmio_base));
1508 }
1509
4cd53c0c
DV		 1510 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1511}
1512
8187a2b7 1513static u32
a4872ba6 1514ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
8187a2b7 1515{
1ec14ad3
CW		 1516 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1517}
1518
b70ec5bf 1519static void
a4872ba6 1520ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf
MK		 1521{
1522 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1523}
1524
c6df541c 1525static u32
a4872ba6 1526pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
c6df541c 1527{
0d1aacac 1528 return ring->scratch.cpu_page[0];
c6df541c
CW		 1529}
1530
b70ec5bf 1531static void
a4872ba6 1532pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf 1533{
0d1aacac 1534 ring->scratch.cpu_page[0] = seqno;
b70ec5bf
MK		 1535}
1536
e48d8634 1537static bool
a4872ba6 1538gen5_ring_get_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1539{
1540 struct drm_device *dev = ring->dev;
4640c4ff 1541 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1542 unsigned long flags;
e48d8634 1543
7cd512f1 1544 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
e48d8634
DV		 1545 return false;
1546
7338aefa 1547 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1548 if (ring->irq_refcount++ == 0)
480c8033 1549 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1550 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1551
1552 return true;
1553}
1554
1555static void
a4872ba6 1556gen5_ring_put_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1557{
1558 struct drm_device *dev = ring->dev;
4640c4ff 1559 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1560 unsigned long flags;
e48d8634 1561
7338aefa 1562 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1563 if (--ring->irq_refcount == 0)
480c8033 1564 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1565 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1566}
1567
b13c2b96 1568static bool
a4872ba6 1569i9xx_ring_get_irq(struct intel_engine_cs *ring)
62fdfeaf 1570{
78501eac 1571 struct drm_device *dev = ring->dev;
4640c4ff 1572 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1573 unsigned long flags;
62fdfeaf 1574
7cd512f1 1575 if (!intel_irqs_enabled(dev_priv))
b13c2b96
CW		 1576 return false;
1577
7338aefa 1578 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1579 if (ring->irq_refcount++ == 0) {
f637fde4
DV		 1580 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1581 I915_WRITE(IMR, dev_priv->irq_mask);
1582 POSTING_READ(IMR);
1583 }
7338aefa 1584 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
b13c2b96
CW		 1585
1586 return true;
62fdfeaf
EA		 1587}
1588
8187a2b7 1589static void
a4872ba6 1590i9xx_ring_put_irq(struct intel_engine_cs *ring)
62fdfeaf 1591{
78501eac 1592 struct drm_device *dev = ring->dev;
4640c4ff 1593 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1594 unsigned long flags;
62fdfeaf 1595
7338aefa 1596 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1597 if (--ring->irq_refcount == 0) {
f637fde4
DV		 1598 dev_priv->irq_mask |= ring->irq_enable_mask;
1599 I915_WRITE(IMR, dev_priv->irq_mask);
1600 POSTING_READ(IMR);
1601 }
7338aefa 1602 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
62fdfeaf
EA		 1603}
1604
c2798b19 1605static bool
a4872ba6 1606i8xx_ring_get_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1607{
1608 struct drm_device *dev = ring->dev;
4640c4ff 1609 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1610 unsigned long flags;
c2798b19 1611
7cd512f1 1612 if (!intel_irqs_enabled(dev_priv))
c2798b19
CW		 1613 return false;
1614
7338aefa 1615 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1616 if (ring->irq_refcount++ == 0) {
c2798b19
CW		 1617 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1618 I915_WRITE16(IMR, dev_priv->irq_mask);
1619 POSTING_READ16(IMR);
1620 }
7338aefa 1621 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1622
1623 return true;
1624}
1625
1626static void
a4872ba6 1627i8xx_ring_put_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1628{
1629 struct drm_device *dev = ring->dev;
4640c4ff 1630 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1631 unsigned long flags;
c2798b19 1632
7338aefa 1633 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1634 if (--ring->irq_refcount == 0) {
c2798b19
CW		 1635 dev_priv->irq_mask |= ring->irq_enable_mask;
1636 I915_WRITE16(IMR, dev_priv->irq_mask);
1637 POSTING_READ16(IMR);
1638 }
7338aefa 1639 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1640}
1641
b72f3acb 1642static int
a84c3ae1 1643bsd_ring_flush(struct drm_i915_gem_request *req,
78501eac
CW		 1644 u32 invalidate_domains,
1645 u32 flush_domains)
d1b851fc 1646{
a84c3ae1 1647 struct intel_engine_cs *ring = req->ring;
b72f3acb
CW		 1648 int ret;
1649
5fb9de1a 1650 ret = intel_ring_begin(req, 2);
b72f3acb
CW		 1651 if (ret)
1652 return ret;
1653
1654 intel_ring_emit(ring, MI_FLUSH);
1655 intel_ring_emit(ring, MI_NOOP);
1656 intel_ring_advance(ring);
1657 return 0;
d1b851fc
ZN		 1658}
1659
3cce469c 1660static int
ee044a88 1661i9xx_add_request(struct drm_i915_gem_request *req)
d1b851fc 1662{
ee044a88 1663 struct intel_engine_cs *ring = req->ring;
3cce469c
CW		 1664 int ret;
1665
5fb9de1a 1666 ret = intel_ring_begin(req, 4);
3cce469c
CW		 1667 if (ret)
1668 return ret;
6f392d54 1669
3cce469c
CW		 1670 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1671 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
ee044a88 1672 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
3cce469c 1673 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1674 __intel_ring_advance(ring);
d1b851fc 1675
3cce469c 1676 return 0;
d1b851fc
ZN		 1677}
1678
0f46832f 1679static bool
a4872ba6 1680gen6_ring_get_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1681{
1682 struct drm_device *dev = ring->dev;
4640c4ff 1683 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1684 unsigned long flags;
0f46832f 1685
7cd512f1
DV		 1686 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1687 return false;
0f46832f 1688
7338aefa 1689 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1690 if (ring->irq_refcount++ == 0) {
040d2baa 1691 if (HAS_L3_DPF(dev) && ring->id == RCS)
cc609d5d
BW		 1692 I915_WRITE_IMR(ring,
1693 ~(ring->irq_enable_mask |
35a85ac6 1694 GT_PARITY_ERROR(dev)));
15b9f80e
BW		 1695 else
1696 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1697 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
0f46832f 1698 }
7338aefa 1699 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
0f46832f
CW		 1700
1701 return true;
1702}
1703
1704static void
a4872ba6 1705gen6_ring_put_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1706{
1707 struct drm_device *dev = ring->dev;
4640c4ff 1708 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1709 unsigned long flags;
0f46832f 1710
7338aefa 1711 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1712 if (--ring->irq_refcount == 0) {
040d2baa 1713 if (HAS_L3_DPF(dev) && ring->id == RCS)
35a85ac6 1714 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e
BW		 1715 else
1716 I915_WRITE_IMR(ring, ~0);
480c8033 1717 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1ec14ad3 1718 }
7338aefa 1719 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
d1b851fc
ZN		 1720}
1721
a19d2933 1722static bool
a4872ba6 1723hsw_vebox_get_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1724{
1725 struct drm_device *dev = ring->dev;
1726 struct drm_i915_private *dev_priv = dev->dev_private;
1727 unsigned long flags;
1728
7cd512f1 1729 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
a19d2933
BW		 1730 return false;
1731
59cdb63d 1732 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1733 if (ring->irq_refcount++ == 0) {
a19d2933 1734 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1735 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1736 }
59cdb63d 1737 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1738
1739 return true;
1740}
1741
1742static void
a4872ba6 1743hsw_vebox_put_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1744{
1745 struct drm_device *dev = ring->dev;
1746 struct drm_i915_private *dev_priv = dev->dev_private;
1747 unsigned long flags;
1748
59cdb63d 1749 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1750 if (--ring->irq_refcount == 0) {
a19d2933 1751 I915_WRITE_IMR(ring, ~0);
480c8033 1752 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1753 }
59cdb63d 1754 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1755}
1756
abd58f01 1757static bool
a4872ba6 1758gen8_ring_get_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1759{
1760 struct drm_device *dev = ring->dev;
1761 struct drm_i915_private *dev_priv = dev->dev_private;
1762 unsigned long flags;
1763
7cd512f1 1764 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
abd58f01
BW		 1765 return false;
1766
1767 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1768 if (ring->irq_refcount++ == 0) {
1769 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1770 I915_WRITE_IMR(ring,
1771 ~(ring->irq_enable_mask |
1772 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1773 } else {
1774 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1775 }
1776 POSTING_READ(RING_IMR(ring->mmio_base));
1777 }
1778 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1779
1780 return true;
1781}
1782
1783static void
a4872ba6 1784gen8_ring_put_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1785{
1786 struct drm_device *dev = ring->dev;
1787 struct drm_i915_private *dev_priv = dev->dev_private;
1788 unsigned long flags;
1789
1790 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1791 if (--ring->irq_refcount == 0) {
1792 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1793 I915_WRITE_IMR(ring,
1794 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1795 } else {
1796 I915_WRITE_IMR(ring, ~0);
1797 }
1798 POSTING_READ(RING_IMR(ring->mmio_base));
1799 }
1800 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1801}
1802
d1b851fc 1803static int
53fddaf7 1804i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 1805 u64 offset, u32 length,
8e004efc 1806 unsigned dispatch_flags)
d1b851fc 1807{
53fddaf7 1808 struct intel_engine_cs *ring = req->ring;
e1f99ce6 1809 int ret;
78501eac 1810
5fb9de1a 1811 ret = intel_ring_begin(req, 2);
e1f99ce6
CW		 1812 if (ret)
1813 return ret;
1814
78501eac 1815 intel_ring_emit(ring,
65f56876
CW		 1816 MI_BATCH_BUFFER_START |
1817 MI_BATCH_GTT |
8e004efc
JH		 1818 (dispatch_flags & I915_DISPATCH_SECURE ?
1819 0 : MI_BATCH_NON_SECURE_I965));
c4e7a414 1820 intel_ring_emit(ring, offset);
78501eac
CW		 1821 intel_ring_advance(ring);
1822
d1b851fc
ZN		 1823 return 0;
1824}
1825
b45305fc
DV		 1826/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1827#define I830_BATCH_LIMIT (256*1024)
c4d69da1
CW		 1828#define I830_TLB_ENTRIES (2)
1829#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
8187a2b7 1830static int
53fddaf7 1831i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
8e004efc
JH		 1832 u64 offset, u32 len,
1833 unsigned dispatch_flags)
62fdfeaf 1834{
53fddaf7 1835 struct intel_engine_cs *ring = req->ring;
c4d69da1 1836 u32 cs_offset = ring->scratch.gtt_offset;
c4e7a414 1837 int ret;
62fdfeaf 1838
5fb9de1a 1839 ret = intel_ring_begin(req, 6);
c4d69da1
CW		 1840 if (ret)
1841 return ret;
62fdfeaf 1842
c4d69da1
CW		 1843 /* Evict the invalid PTE TLBs */
1844 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1845 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1846 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1847 intel_ring_emit(ring, cs_offset);
1848 intel_ring_emit(ring, 0xdeadbeef);
1849 intel_ring_emit(ring, MI_NOOP);
1850 intel_ring_advance(ring);
b45305fc 1851
8e004efc 1852 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
b45305fc
DV		 1853 if (len > I830_BATCH_LIMIT)
1854 return -ENOSPC;
1855
5fb9de1a 1856 ret = intel_ring_begin(req, 6 + 2);
b45305fc
DV		 1857 if (ret)
1858 return ret;
c4d69da1
CW		 1859
1860 /* Blit the batch (which has now all relocs applied) to the
1861 * stable batch scratch bo area (so that the CS never
1862 * stumbles over its tlb invalidation bug) ...
1863 */
1864 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1865 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
611a7a4f 1866 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
b45305fc 1867 intel_ring_emit(ring, cs_offset);
b45305fc
DV		 1868 intel_ring_emit(ring, 4096);
1869 intel_ring_emit(ring, offset);
c4d69da1 1870
b45305fc 1871 intel_ring_emit(ring, MI_FLUSH);
c4d69da1
CW		 1872 intel_ring_emit(ring, MI_NOOP);
1873 intel_ring_advance(ring);
b45305fc
DV		 1874
1875 /* ... and execute it. */
c4d69da1 1876 offset = cs_offset;
b45305fc 1877 }
e1f99ce6 1878
5fb9de1a 1879 ret = intel_ring_begin(req, 4);
c4d69da1
CW		 1880 if (ret)
1881 return ret;
1882
1883 intel_ring_emit(ring, MI_BATCH_BUFFER);
8e004efc
JH		 1884 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1885 0 : MI_BATCH_NON_SECURE));
c4d69da1
CW		 1886 intel_ring_emit(ring, offset + len - 8);
1887 intel_ring_emit(ring, MI_NOOP);
1888 intel_ring_advance(ring);
1889
fb3256da
DV		 1890 return 0;
1891}
1892
1893static int
53fddaf7 1894i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 1895 u64 offset, u32 len,
8e004efc 1896 unsigned dispatch_flags)
fb3256da 1897{
53fddaf7 1898 struct intel_engine_cs *ring = req->ring;
fb3256da
DV		 1899 int ret;
1900
5fb9de1a 1901 ret = intel_ring_begin(req, 2);
fb3256da
DV		 1902 if (ret)
1903 return ret;
1904
65f56876 1905 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
8e004efc
JH		 1906 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1907 0 : MI_BATCH_NON_SECURE));
c4e7a414 1908 intel_ring_advance(ring);
62fdfeaf 1909
62fdfeaf
EA		 1910 return 0;
1911}
1912
a4872ba6 1913static void cleanup_status_page(struct intel_engine_cs *ring)
62fdfeaf 1914{
05394f39 1915 struct drm_i915_gem_object *obj;
62fdfeaf 1916
8187a2b7
ZN		 1917 obj = ring->status_page.obj;
1918 if (obj == NULL)
62fdfeaf 1919 return;
62fdfeaf 1920
9da3da66 1921 kunmap(sg_page(obj->pages->sgl));
d7f46fc4 1922 i915_gem_object_ggtt_unpin(obj);
05394f39 1923 drm_gem_object_unreference(&obj->base);
8187a2b7 1924 ring->status_page.obj = NULL;
62fdfeaf
EA		 1925}
1926
a4872ba6 1927static int init_status_page(struct intel_engine_cs *ring)
62fdfeaf 1928{
05394f39 1929 struct drm_i915_gem_object *obj;
62fdfeaf 1930
e3efda49 1931 if ((obj = ring->status_page.obj) == NULL) {
1f767e02 1932 unsigned flags;
e3efda49 1933 int ret;
e4ffd173 1934
e3efda49
CW		 1935 obj = i915_gem_alloc_object(ring->dev, 4096);
1936 if (obj == NULL) {
1937 DRM_ERROR("Failed to allocate status page\n");
1938 return -ENOMEM;
1939 }
62fdfeaf 1940
e3efda49
CW		 1941 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1942 if (ret)
1943 goto err_unref;
1944
1f767e02
CW		 1945 flags = 0;
1946 if (!HAS_LLC(ring->dev))
1947 /* On g33, we cannot place HWS above 256MiB, so
1948 * restrict its pinning to the low mappable arena.
1949 * Though this restriction is not documented for
1950 * gen4, gen5, or byt, they also behave similarly
1951 * and hang if the HWS is placed at the top of the
1952 * GTT. To generalise, it appears that all !llc
1953 * platforms have issues with us placing the HWS
1954 * above the mappable region (even though we never
1955 * actualy map it).
1956 */
1957 flags |= PIN_MAPPABLE;
1958 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
e3efda49
CW		 1959 if (ret) {
1960err_unref:
1961 drm_gem_object_unreference(&obj->base);
1962 return ret;
1963 }
1964
1965 ring->status_page.obj = obj;
1966 }
62fdfeaf 1967
f343c5f6 1968 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
9da3da66 1969 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
8187a2b7 1970 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
62fdfeaf 1971
8187a2b7
ZN		 1972 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1973 ring->name, ring->status_page.gfx_addr);
62fdfeaf
EA		 1974
1975 return 0;
62fdfeaf
EA		 1976}
1977
a4872ba6 1978static int init_phys_status_page(struct intel_engine_cs *ring)
6b8294a4
CW		 1979{
1980 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6b8294a4
CW		 1981
1982 if (!dev_priv->status_page_dmah) {
1983 dev_priv->status_page_dmah =
1984 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1985 if (!dev_priv->status_page_dmah)
1986 return -ENOMEM;
1987 }
1988
6b8294a4
CW		 1989 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1990 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1991
1992 return 0;
1993}
1994
7ba717cf 1995void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2919d291 1996{
def0c5f6
CW		 1997 if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
1998 vunmap(ringbuf->virtual_start);
1999 else
2000 iounmap(ringbuf->virtual_start);
7ba717cf 2001 ringbuf->virtual_start = NULL;
2919d291 2002 i915_gem_object_ggtt_unpin(ringbuf->obj);
7ba717cf
TD		 2003}
2004
def0c5f6
CW		 2005static u32 *vmap_obj(struct drm_i915_gem_object *obj)
2006{
2007 struct sg_page_iter sg_iter;
2008 struct page **pages;
2009 void *addr;
2010 int i;
2011
2012 pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages));
2013 if (pages == NULL)
2014 return NULL;
2015
2016 i = 0;
2017 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0)
2018 pages[i++] = sg_page_iter_page(&sg_iter);
2019
2020 addr = vmap(pages, i, 0, PAGE_KERNEL);
2021 drm_free_large(pages);
2022
2023 return addr;
2024}
2025
7ba717cf
TD		 2026int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
2027 struct intel_ringbuffer *ringbuf)
2028{
2029 struct drm_i915_private *dev_priv = to_i915(dev);
2030 struct drm_i915_gem_object *obj = ringbuf->obj;
2031 int ret;
2032
def0c5f6
CW		 2033 if (HAS_LLC(dev_priv) && !obj->stolen) {
2034 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, 0);
2035 if (ret)
2036 return ret;
7ba717cf 2037
def0c5f6
CW		 2038 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2039 if (ret) {
2040 i915_gem_object_ggtt_unpin(obj);
2041 return ret;
2042 }
2043
2044 ringbuf->virtual_start = vmap_obj(obj);
2045 if (ringbuf->virtual_start == NULL) {
2046 i915_gem_object_ggtt_unpin(obj);
2047 return -ENOMEM;
2048 }
2049 } else {
2050 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
2051 if (ret)
2052 return ret;
7ba717cf 2053
def0c5f6
CW		 2054 ret = i915_gem_object_set_to_gtt_domain(obj, true);
2055 if (ret) {
2056 i915_gem_object_ggtt_unpin(obj);
2057 return ret;
2058 }
2059
2060 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
2061 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
2062 if (ringbuf->virtual_start == NULL) {
2063 i915_gem_object_ggtt_unpin(obj);
2064 return -EINVAL;
2065 }
7ba717cf
TD		 2066 }
2067
2068 return 0;
2069}
2070
01101fa7 2071static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
7ba717cf 2072{
2919d291
OM		 2073 drm_gem_object_unreference(&ringbuf->obj->base);
2074 ringbuf->obj = NULL;
2075}
2076
01101fa7
CW		 2077static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2078 struct intel_ringbuffer *ringbuf)
62fdfeaf 2079{
05394f39 2080 struct drm_i915_gem_object *obj;
62fdfeaf 2081
ebc052e0
CW		 2082 obj = NULL;
2083 if (!HAS_LLC(dev))
93b0a4e0 2084 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
ebc052e0 2085 if (obj == NULL)
93b0a4e0 2086 obj = i915_gem_alloc_object(dev, ringbuf->size);
e3efda49
CW		 2087 if (obj == NULL)
2088 return -ENOMEM;
8187a2b7 2089
24f3a8cf
AG		 2090 /* mark ring buffers as read-only from GPU side by default */
2091 obj->gt_ro = 1;
2092
93b0a4e0 2093 ringbuf->obj = obj;
e3efda49 2094
7ba717cf 2095 return 0;
e3efda49
CW		 2096}
2097
01101fa7
CW		 2098struct intel_ringbuffer *
2099intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2100{
2101 struct intel_ringbuffer *ring;
2102 int ret;
2103
2104 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
608c1a52
CW		 2105 if (ring == NULL) {
2106 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2107 engine->name);
01101fa7 2108 return ERR_PTR(-ENOMEM);
608c1a52 2109 }
01101fa7
CW		 2110
2111 ring->ring = engine;
608c1a52 2112 list_add(&ring->link, &engine->buffers);
01101fa7
CW		 2113
2114 ring->size = size;
2115 /* Workaround an erratum on the i830 which causes a hang if
2116 * the TAIL pointer points to within the last 2 cachelines
2117 * of the buffer.
2118 */
2119 ring->effective_size = size;
2120 if (IS_I830(engine->dev) || IS_845G(engine->dev))
2121 ring->effective_size -= 2 * CACHELINE_BYTES;
2122
2123 ring->last_retired_head = -1;
2124 intel_ring_update_space(ring);
2125
2126 ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
2127 if (ret) {
608c1a52
CW		 2128 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2129 engine->name, ret);
2130 list_del(&ring->link);
01101fa7
CW		 2131 kfree(ring);
2132 return ERR_PTR(ret);
2133 }
2134
2135 return ring;
2136}
2137
2138void
2139intel_ringbuffer_free(struct intel_ringbuffer *ring)
2140{
2141 intel_destroy_ringbuffer_obj(ring);
608c1a52 2142 list_del(&ring->link);
01101fa7
CW		 2143 kfree(ring);
2144}
2145
e3efda49 2146static int intel_init_ring_buffer(struct drm_device *dev,
a4872ba6 2147 struct intel_engine_cs *ring)
e3efda49 2148{
bfc882b4 2149 struct intel_ringbuffer *ringbuf;
e3efda49
CW		 2150 int ret;
2151
bfc882b4
DV		 2152 WARN_ON(ring->buffer);
2153
e3efda49
CW		 2154 ring->dev = dev;
2155 INIT_LIST_HEAD(&ring->active_list);
2156 INIT_LIST_HEAD(&ring->request_list);
cc9130be 2157 INIT_LIST_HEAD(&ring->execlist_queue);
608c1a52 2158 INIT_LIST_HEAD(&ring->buffers);
06fbca71 2159 i915_gem_batch_pool_init(dev, &ring->batch_pool);
ebc348b2 2160 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
e3efda49
CW		 2161
2162 init_waitqueue_head(&ring->irq_queue);
2163
01101fa7
CW		 2164 ringbuf = intel_engine_create_ringbuffer(ring, 32 * PAGE_SIZE);
2165 if (IS_ERR(ringbuf))
2166 return PTR_ERR(ringbuf);
2167 ring->buffer = ringbuf;
2168
e3efda49
CW		 2169 if (I915_NEED_GFX_HWS(dev)) {
2170 ret = init_status_page(ring);
2171 if (ret)
8ee14975 2172 goto error;
e3efda49
CW		 2173 } else {
2174 BUG_ON(ring->id != RCS);
2175 ret = init_phys_status_page(ring);
2176 if (ret)
8ee14975 2177 goto error;
e3efda49
CW		 2178 }
2179
bfc882b4
DV		 2180 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2181 if (ret) {
2182 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2183 ring->name, ret);
2184 intel_destroy_ringbuffer_obj(ringbuf);
2185 goto error;
e3efda49 2186 }
62fdfeaf 2187
44e895a8
BV		 2188 ret = i915_cmd_parser_init_ring(ring);
2189 if (ret)
8ee14975
OM		 2190 goto error;
2191
8ee14975 2192 return 0;
351e3db2 2193
8ee14975 2194error:
01101fa7 2195 intel_ringbuffer_free(ringbuf);
8ee14975
OM		 2196 ring->buffer = NULL;
2197 return ret;
62fdfeaf
EA		 2198}
2199
a4872ba6 2200void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
62fdfeaf 2201{
6402c330 2202 struct drm_i915_private *dev_priv;
33626e6a 2203
93b0a4e0 2204 if (!intel_ring_initialized(ring))
62fdfeaf
EA		 2205 return;
2206
6402c330 2207 dev_priv = to_i915(ring->dev);
6402c330 2208
e3efda49 2209 intel_stop_ring_buffer(ring);
de8f0a50 2210 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
33626e6a 2211
01101fa7
CW		 2212 intel_unpin_ringbuffer_obj(ring->buffer);
2213 intel_ringbuffer_free(ring->buffer);
2214 ring->buffer = NULL;
78501eac 2215
8d19215b
ZN		 2216 if (ring->cleanup)
2217 ring->cleanup(ring);
2218
78501eac 2219 cleanup_status_page(ring);
44e895a8
BV		 2220
2221 i915_cmd_parser_fini_ring(ring);
06fbca71 2222 i915_gem_batch_pool_fini(&ring->batch_pool);
62fdfeaf
EA		 2223}
2224
595e1eeb 2225static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
a71d8d94 2226{
93b0a4e0 2227 struct intel_ringbuffer *ringbuf = ring->buffer;
a71d8d94 2228 struct drm_i915_gem_request *request;
b4716185
CW		 2229 unsigned space;
2230 int ret;
a71d8d94 2231
ebd0fd4b
DG		 2232 if (intel_ring_space(ringbuf) >= n)
2233 return 0;
a71d8d94 2234
79bbcc29
JH		 2235 /* The whole point of reserving space is to not wait! */
2236 WARN_ON(ringbuf->reserved_in_use);
2237
a71d8d94 2238 list_for_each_entry(request, &ring->request_list, list) {
b4716185
CW		 2239 space = __intel_ring_space(request->postfix, ringbuf->tail,
2240 ringbuf->size);
2241 if (space >= n)
a71d8d94 2242 break;
a71d8d94
CW		 2243 }
2244
595e1eeb 2245 if (WARN_ON(&request->list == &ring->request_list))
a71d8d94
CW		 2246 return -ENOSPC;
2247
a4b3a571 2248 ret = i915_wait_request(request);
a71d8d94
CW		 2249 if (ret)
2250 return ret;
2251
b4716185 2252 ringbuf->space = space;
a71d8d94
CW		 2253 return 0;
2254}
2255
79bbcc29 2256static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
3e960501
CW		 2257{
2258 uint32_t __iomem *virt;
93b0a4e0 2259 int rem = ringbuf->size - ringbuf->tail;
3e960501 2260
93b0a4e0 2261 virt = ringbuf->virtual_start + ringbuf->tail;
3e960501
CW		 2262 rem /= 4;
2263 while (rem--)
2264 iowrite32(MI_NOOP, virt++);
2265
93b0a4e0 2266 ringbuf->tail = 0;
ebd0fd4b 2267 intel_ring_update_space(ringbuf);
3e960501
CW		 2268}
2269
a4872ba6 2270int intel_ring_idle(struct intel_engine_cs *ring)
3e960501 2271{
a4b3a571 2272 struct drm_i915_gem_request *req;
3e960501 2273
3e960501
CW		 2274 /* Wait upon the last request to be completed */
2275 if (list_empty(&ring->request_list))
2276 return 0;
2277
a4b3a571 2278 req = list_entry(ring->request_list.prev,
b4716185
CW		 2279 struct drm_i915_gem_request,
2280 list);
2281
2282 /* Make sure we do not trigger any retires */
2283 return __i915_wait_request(req,
2284 atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter),
2285 to_i915(ring->dev)->mm.interruptible,
2286 NULL, NULL);
3e960501
CW		 2287}
2288
6689cb2b 2289int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
9d773091 2290{
6689cb2b 2291 request->ringbuf = request->ring->buffer;
9eba5d4a 2292 return 0;
9d773091
CW		 2293}
2294
ccd98fe4
JH		 2295int intel_ring_reserve_space(struct drm_i915_gem_request *request)
2296{
2297 /*
2298 * The first call merely notes the reserve request and is common for
2299 * all back ends. The subsequent localised _begin() call actually
2300 * ensures that the reservation is available. Without the begin, if
2301 * the request creator immediately submitted the request without
2302 * adding any commands to it then there might not actually be
2303 * sufficient room for the submission commands.
2304 */
2305 intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
2306
2307 return intel_ring_begin(request, 0);
2308}
2309
29b1b415
JH		 2310void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2311{
ccd98fe4 2312 WARN_ON(ringbuf->reserved_size);
29b1b415
JH		 2313 WARN_ON(ringbuf->reserved_in_use);
2314
2315 ringbuf->reserved_size = size;
29b1b415
JH		 2316}
2317
2318void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2319{
2320 WARN_ON(ringbuf->reserved_in_use);
2321
2322 ringbuf->reserved_size = 0;
2323 ringbuf->reserved_in_use = false;
2324}
2325
2326void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2327{
2328 WARN_ON(ringbuf->reserved_in_use);
2329
2330 ringbuf->reserved_in_use = true;
2331 ringbuf->reserved_tail = ringbuf->tail;
2332}
2333
2334void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2335{
2336 WARN_ON(!ringbuf->reserved_in_use);
79bbcc29
JH		 2337 if (ringbuf->tail > ringbuf->reserved_tail) {
2338 WARN(ringbuf->tail > ringbuf->reserved_tail + ringbuf->reserved_size,
2339 "request reserved size too small: %d vs %d!\n",
2340 ringbuf->tail - ringbuf->reserved_tail, ringbuf->reserved_size);
2341 } else {
2342 /*
2343 * The ring was wrapped while the reserved space was in use.
2344 * That means that some unknown amount of the ring tail was
2345 * no-op filled and skipped. Thus simply adding the ring size
2346 * to the tail and doing the above space check will not work.
2347 * Rather than attempt to track how much tail was skipped,
2348 * it is much simpler to say that also skipping the sanity
2349 * check every once in a while is not a big issue.
2350 */
2351 }
29b1b415
JH		 2352
2353 ringbuf->reserved_size = 0;
2354 ringbuf->reserved_in_use = false;
2355}
2356
2357static int __intel_ring_prepare(struct intel_engine_cs *ring, int bytes)
cbcc80df 2358{
93b0a4e0 2359 struct intel_ringbuffer *ringbuf = ring->buffer;
79bbcc29
JH		 2360 int remain_usable = ringbuf->effective_size - ringbuf->tail;
2361 int remain_actual = ringbuf->size - ringbuf->tail;
2362 int ret, total_bytes, wait_bytes = 0;
2363 bool need_wrap = false;
29b1b415 2364
79bbcc29
JH		 2365 if (ringbuf->reserved_in_use)
2366 total_bytes = bytes;
2367 else
2368 total_bytes = bytes + ringbuf->reserved_size;
29b1b415 2369
79bbcc29
JH		 2370 if (unlikely(bytes > remain_usable)) {
2371 /*
2372 * Not enough space for the basic request. So need to flush
2373 * out the remainder and then wait for base + reserved.
2374 */
2375 wait_bytes = remain_actual + total_bytes;
2376 need_wrap = true;
2377 } else {
2378 if (unlikely(total_bytes > remain_usable)) {
2379 /*
2380 * The base request will fit but the reserved space
2381 * falls off the end. So only need to to wait for the
2382 * reserved size after flushing out the remainder.
2383 */
2384 wait_bytes = remain_actual + ringbuf->reserved_size;
2385 need_wrap = true;
2386 } else if (total_bytes > ringbuf->space) {
2387 /* No wrapping required, just waiting. */
2388 wait_bytes = total_bytes;
29b1b415 2389 }
cbcc80df
MK		 2390 }
2391
79bbcc29
JH		 2392 if (wait_bytes) {
2393 ret = ring_wait_for_space(ring, wait_bytes);
cbcc80df
MK		 2394 if (unlikely(ret))
2395 return ret;
79bbcc29
JH		 2396
2397 if (need_wrap)
2398 __wrap_ring_buffer(ringbuf);
cbcc80df
MK		 2399 }
2400
cbcc80df
MK		 2401 return 0;
2402}
2403
5fb9de1a 2404int intel_ring_begin(struct drm_i915_gem_request *req,
e1f99ce6 2405 int num_dwords)
8187a2b7 2406{
5fb9de1a
JH		 2407 struct intel_engine_cs *ring;
2408 struct drm_i915_private *dev_priv;
e1f99ce6 2409 int ret;
78501eac 2410
5fb9de1a
JH		 2411 WARN_ON(req == NULL);
2412 ring = req->ring;
2413 dev_priv = ring->dev->dev_private;
2414
33196ded
DV		 2415 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2416 dev_priv->mm.interruptible);
de2b9985
DV		 2417 if (ret)
2418 return ret;
21dd3734 2419
304d695c
CW		 2420 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2421 if (ret)
2422 return ret;
2423
ee1b1e5e 2424 ring->buffer->space -= num_dwords * sizeof(uint32_t);
304d695c 2425 return 0;
8187a2b7 2426}
78501eac 2427
753b1ad4 2428/* Align the ring tail to a cacheline boundary */
bba09b12 2429int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
753b1ad4 2430{
bba09b12 2431 struct intel_engine_cs *ring = req->ring;
ee1b1e5e 2432 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
753b1ad4
VS		 2433 int ret;
2434
2435 if (num_dwords == 0)
2436 return 0;
2437
18393f63 2438 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
5fb9de1a 2439 ret = intel_ring_begin(req, num_dwords);
753b1ad4
VS		 2440 if (ret)
2441 return ret;
2442
2443 while (num_dwords--)
2444 intel_ring_emit(ring, MI_NOOP);
2445
2446 intel_ring_advance(ring);
2447
2448 return 0;
2449}
2450
a4872ba6 2451void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
498d2ac1 2452{
3b2cc8ab
OM		 2453 struct drm_device *dev = ring->dev;
2454 struct drm_i915_private *dev_priv = dev->dev_private;
498d2ac1 2455
3b2cc8ab 2456 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
f7e98ad4
MK		 2457 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2458 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
3b2cc8ab 2459 if (HAS_VEBOX(dev))
5020150b 2460 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
e1f99ce6 2461 }
d97ed339 2462
f7e98ad4 2463 ring->set_seqno(ring, seqno);
92cab734 2464 ring->hangcheck.seqno = seqno;
8187a2b7 2465}
62fdfeaf 2466
a4872ba6 2467static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 2468 u32 value)
881f47b6 2469{
4640c4ff 2470 struct drm_i915_private *dev_priv = ring->dev->dev_private;
881f47b6
XH		 2471
2472 /* Every tail move must follow the sequence below */
12f55818
CW		 2473
2474 /* Disable notification that the ring is IDLE. The GT
2475 * will then assume that it is busy and bring it out of rc6.
2476 */
0206e353 2477 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818
CW		 2478 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2479
2480 /* Clear the context id. Here be magic! */
2481 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
0206e353 2482
12f55818 2483 /* Wait for the ring not to be idle, i.e. for it to wake up. */
0206e353 2484 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
12f55818
CW		 2485 GEN6_BSD_SLEEP_INDICATOR) == 0,
2486 50))
2487 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
0206e353 2488
12f55818 2489 /* Now that the ring is fully powered up, update the tail */
0206e353 2490 I915_WRITE_TAIL(ring, value);
12f55818
CW		 2491 POSTING_READ(RING_TAIL(ring->mmio_base));
2492
2493 /* Let the ring send IDLE messages to the GT again,
2494 * and so let it sleep to conserve power when idle.
2495 */
0206e353 2496 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818 2497 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
881f47b6
XH		 2498}
2499
a84c3ae1 2500static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
ea251324 2501 u32 invalidate, u32 flush)
881f47b6 2502{
a84c3ae1 2503 struct intel_engine_cs *ring = req->ring;
71a77e07 2504 uint32_t cmd;
b72f3acb
CW		 2505 int ret;
2506
5fb9de1a 2507 ret = intel_ring_begin(req, 4);
b72f3acb
CW		 2508 if (ret)
2509 return ret;
2510
71a77e07 2511 cmd = MI_FLUSH_DW;
075b3bba
BW		 2512 if (INTEL_INFO(ring->dev)->gen >= 8)
2513 cmd += 1;
f0a1fb10
CW		 2514
2515 /* We always require a command barrier so that subsequent
2516 * commands, such as breadcrumb interrupts, are strictly ordered
2517 * wrt the contents of the write cache being flushed to memory
2518 * (and thus being coherent from the CPU).
2519 */
2520 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2521
9a289771
JB		 2522 /*
2523 * Bspec vol 1c.5 - video engine command streamer:
2524 * "If ENABLED, all TLBs will be invalidated once the flush
2525 * operation is complete. This bit is only valid when the
2526 * Post-Sync Operation field is a value of 1h or 3h."
2527 */
71a77e07 2528 if (invalidate & I915_GEM_GPU_DOMAINS)
f0a1fb10
CW		 2529 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2530
71a77e07 2531 intel_ring_emit(ring, cmd);
9a289771 2532 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
075b3bba
BW		 2533 if (INTEL_INFO(ring->dev)->gen >= 8) {
2534 intel_ring_emit(ring, 0); /* upper addr */
2535 intel_ring_emit(ring, 0); /* value */
2536 } else {
2537 intel_ring_emit(ring, 0);
2538 intel_ring_emit(ring, MI_NOOP);
2539 }
b72f3acb
CW		 2540 intel_ring_advance(ring);
2541 return 0;
881f47b6
XH		 2542}
2543
1c7a0623 2544static int
53fddaf7 2545gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 2546 u64 offset, u32 len,
8e004efc 2547 unsigned dispatch_flags)
1c7a0623 2548{
53fddaf7 2549 struct intel_engine_cs *ring = req->ring;
8e004efc
JH		 2550 bool ppgtt = USES_PPGTT(ring->dev) &&
2551 !(dispatch_flags & I915_DISPATCH_SECURE);
1c7a0623
BW		 2552 int ret;
2553
5fb9de1a 2554 ret = intel_ring_begin(req, 4);
1c7a0623
BW		 2555 if (ret)
2556 return ret;
2557
2558 /* FIXME(BDW): Address space and security selectors. */
919032ec
AJ		 2559 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2560 (dispatch_flags & I915_DISPATCH_RS ?
2561 MI_BATCH_RESOURCE_STREAMER : 0));
9bcb144c
BW		 2562 intel_ring_emit(ring, lower_32_bits(offset));
2563 intel_ring_emit(ring, upper_32_bits(offset));
1c7a0623
BW		 2564 intel_ring_emit(ring, MI_NOOP);
2565 intel_ring_advance(ring);
2566
2567 return 0;
2568}
2569
d7d4eedd 2570static int
53fddaf7 2571hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
8e004efc
JH		 2572 u64 offset, u32 len,
2573 unsigned dispatch_flags)
d7d4eedd 2574{
53fddaf7 2575 struct intel_engine_cs *ring = req->ring;
d7d4eedd
CW		 2576 int ret;
2577
5fb9de1a 2578 ret = intel_ring_begin(req, 2);
d7d4eedd
CW		 2579 if (ret)
2580 return ret;
2581
2582 intel_ring_emit(ring,
77072258 2583 MI_BATCH_BUFFER_START |
8e004efc 2584 (dispatch_flags & I915_DISPATCH_SECURE ?
919032ec
AJ		 2585 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2586 (dispatch_flags & I915_DISPATCH_RS ?
2587 MI_BATCH_RESOURCE_STREAMER : 0));
d7d4eedd
CW		 2588 /* bit0-7 is the length on GEN6+ */
2589 intel_ring_emit(ring, offset);
2590 intel_ring_advance(ring);
2591
2592 return 0;
2593}
2594
881f47b6 2595static int
53fddaf7 2596gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 2597 u64 offset, u32 len,
8e004efc 2598 unsigned dispatch_flags)
881f47b6 2599{
53fddaf7 2600 struct intel_engine_cs *ring = req->ring;
0206e353 2601 int ret;
ab6f8e32 2602
5fb9de1a 2603 ret = intel_ring_begin(req, 2);
0206e353
AJ		 2604 if (ret)
2605 return ret;
e1f99ce6 2606
d7d4eedd
CW		 2607 intel_ring_emit(ring,
2608 MI_BATCH_BUFFER_START |
8e004efc
JH		 2609 (dispatch_flags & I915_DISPATCH_SECURE ?
2610 0 : MI_BATCH_NON_SECURE_I965));
0206e353
AJ		 2611 /* bit0-7 is the length on GEN6+ */
2612 intel_ring_emit(ring, offset);
2613 intel_ring_advance(ring);
ab6f8e32 2614
0206e353 2615 return 0;
881f47b6
XH		 2616}
2617
549f7365
CW		 2618/* Blitter support (SandyBridge+) */
2619
a84c3ae1 2620static int gen6_ring_flush(struct drm_i915_gem_request *req,
ea251324 2621 u32 invalidate, u32 flush)
8d19215b 2622{
a84c3ae1 2623 struct intel_engine_cs *ring = req->ring;
fd3da6c9 2624 struct drm_device *dev = ring->dev;
71a77e07 2625 uint32_t cmd;
b72f3acb
CW		 2626 int ret;
2627
5fb9de1a 2628 ret = intel_ring_begin(req, 4);
b72f3acb
CW		 2629 if (ret)
2630 return ret;
2631
71a77e07 2632 cmd = MI_FLUSH_DW;
dbef0f15 2633 if (INTEL_INFO(dev)->gen >= 8)
075b3bba 2634 cmd += 1;
f0a1fb10
CW		 2635
2636 /* We always require a command barrier so that subsequent
2637 * commands, such as breadcrumb interrupts, are strictly ordered
2638 * wrt the contents of the write cache being flushed to memory
2639 * (and thus being coherent from the CPU).
2640 */
2641 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2642
9a289771
JB		 2643 /*
2644 * Bspec vol 1c.3 - blitter engine command streamer:
2645 * "If ENABLED, all TLBs will be invalidated once the flush
2646 * operation is complete. This bit is only valid when the
2647 * Post-Sync Operation field is a value of 1h or 3h."
2648 */
71a77e07 2649 if (invalidate & I915_GEM_DOMAIN_RENDER)
f0a1fb10 2650 cmd |= MI_INVALIDATE_TLB;
71a77e07 2651 intel_ring_emit(ring, cmd);
9a289771 2652 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
dbef0f15 2653 if (INTEL_INFO(dev)->gen >= 8) {
075b3bba
BW		 2654 intel_ring_emit(ring, 0); /* upper addr */
2655 intel_ring_emit(ring, 0); /* value */
2656 } else {
2657 intel_ring_emit(ring, 0);
2658 intel_ring_emit(ring, MI_NOOP);
2659 }
b72f3acb 2660 intel_ring_advance(ring);
fd3da6c9 2661
b72f3acb 2662 return 0;
8d19215b
ZN		 2663}
2664
5c1143bb
XH		 2665int intel_init_render_ring_buffer(struct drm_device *dev)
2666{
4640c4ff 2667 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2668 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3e78998a
BW		 2669 struct drm_i915_gem_object *obj;
2670 int ret;
5c1143bb 2671
59465b5f
DV		 2672 ring->name = "render ring";
2673 ring->id = RCS;
2674 ring->mmio_base = RENDER_RING_BASE;
2675
707d9cf9 2676 if (INTEL_INFO(dev)->gen >= 8) {
3e78998a
BW		 2677 if (i915_semaphore_is_enabled(dev)) {
2678 obj = i915_gem_alloc_object(dev, 4096);
2679 if (obj == NULL) {
2680 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2681 i915.semaphores = 0;
2682 } else {
2683 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2684 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2685 if (ret != 0) {
2686 drm_gem_object_unreference(&obj->base);
2687 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2688 i915.semaphores = 0;
2689 } else
2690 dev_priv->semaphore_obj = obj;
2691 }
2692 }
7225342a 2693
8f0e2b9d 2694 ring->init_context = intel_rcs_ctx_init;
707d9cf9
BW		 2695 ring->add_request = gen6_add_request;
2696 ring->flush = gen8_render_ring_flush;
2697 ring->irq_get = gen8_ring_get_irq;
2698 ring->irq_put = gen8_ring_put_irq;
2699 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2700 ring->get_seqno = gen6_ring_get_seqno;
2701 ring->set_seqno = ring_set_seqno;
2702 if (i915_semaphore_is_enabled(dev)) {
3e78998a 2703 WARN_ON(!dev_priv->semaphore_obj);
5ee426ca 2704 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2705 ring->semaphore.signal = gen8_rcs_signal;
2706 GEN8_RING_SEMAPHORE_INIT;
707d9cf9
BW		 2707 }
2708 } else if (INTEL_INFO(dev)->gen >= 6) {
4f91fc6d 2709 ring->init_context = intel_rcs_ctx_init;
1ec14ad3 2710 ring->add_request = gen6_add_request;
4772eaeb 2711 ring->flush = gen7_render_ring_flush;
6c6cf5aa 2712 if (INTEL_INFO(dev)->gen == 6)
b3111509 2713 ring->flush = gen6_render_ring_flush;
707d9cf9
BW		 2714 ring->irq_get = gen6_ring_get_irq;
2715 ring->irq_put = gen6_ring_put_irq;
cc609d5d 2716 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
4cd53c0c 2717 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2718 ring->set_seqno = ring_set_seqno;
707d9cf9
BW		 2719 if (i915_semaphore_is_enabled(dev)) {
2720 ring->semaphore.sync_to = gen6_ring_sync;
2721 ring->semaphore.signal = gen6_signal;
2722 /*
2723 * The current semaphore is only applied on pre-gen8
2724 * platform. And there is no VCS2 ring on the pre-gen8
2725 * platform. So the semaphore between RCS and VCS2 is
2726 * initialized as INVALID. Gen8 will initialize the
2727 * sema between VCS2 and RCS later.
2728 */
2729 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2730 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2731 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2732 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2733 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2734 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2735 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2736 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2737 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2738 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2739 }
c6df541c
CW		 2740 } else if (IS_GEN5(dev)) {
2741 ring->add_request = pc_render_add_request;
46f0f8d1 2742 ring->flush = gen4_render_ring_flush;
c6df541c 2743 ring->get_seqno = pc_render_get_seqno;
b70ec5bf 2744 ring->set_seqno = pc_render_set_seqno;
e48d8634
DV		 2745 ring->irq_get = gen5_ring_get_irq;
2746 ring->irq_put = gen5_ring_put_irq;
cc609d5d
BW		 2747 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2748 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
59465b5f 2749 } else {
8620a3a9 2750 ring->add_request = i9xx_add_request;
46f0f8d1
CW		 2751 if (INTEL_INFO(dev)->gen < 4)
2752 ring->flush = gen2_render_ring_flush;
2753 else
2754 ring->flush = gen4_render_ring_flush;
59465b5f 2755 ring->get_seqno = ring_get_seqno;
b70ec5bf 2756 ring->set_seqno = ring_set_seqno;
c2798b19
CW		 2757 if (IS_GEN2(dev)) {
2758 ring->irq_get = i8xx_ring_get_irq;
2759 ring->irq_put = i8xx_ring_put_irq;
2760 } else {
2761 ring->irq_get = i9xx_ring_get_irq;
2762 ring->irq_put = i9xx_ring_put_irq;
2763 }
e3670319 2764 ring->irq_enable_mask = I915_USER_INTERRUPT;
1ec14ad3 2765 }
59465b5f 2766 ring->write_tail = ring_write_tail;
707d9cf9 2767
d7d4eedd
CW		 2768 if (IS_HASWELL(dev))
2769 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1c7a0623
BW		 2770 else if (IS_GEN8(dev))
2771 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
d7d4eedd 2772 else if (INTEL_INFO(dev)->gen >= 6)
fb3256da
DV		 2773 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2774 else if (INTEL_INFO(dev)->gen >= 4)
2775 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2776 else if (IS_I830(dev) || IS_845G(dev))
2777 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2778 else
2779 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
ecfe00d8 2780 ring->init_hw = init_render_ring;
59465b5f
DV		 2781 ring->cleanup = render_ring_cleanup;
2782
b45305fc
DV		 2783 /* Workaround batchbuffer to combat CS tlb bug. */
2784 if (HAS_BROKEN_CS_TLB(dev)) {
c4d69da1 2785 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
b45305fc
DV		 2786 if (obj == NULL) {
2787 DRM_ERROR("Failed to allocate batch bo\n");
2788 return -ENOMEM;
2789 }
2790
be1fa129 2791 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
b45305fc
DV		 2792 if (ret != 0) {
2793 drm_gem_object_unreference(&obj->base);
2794 DRM_ERROR("Failed to ping batch bo\n");
2795 return ret;
2796 }
2797
0d1aacac
CW		 2798 ring->scratch.obj = obj;
2799 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
b45305fc
DV		 2800 }
2801
99be1dfe
DV		 2802 ret = intel_init_ring_buffer(dev, ring);
2803 if (ret)
2804 return ret;
2805
2806 if (INTEL_INFO(dev)->gen >= 5) {
2807 ret = intel_init_pipe_control(ring);
2808 if (ret)
2809 return ret;
2810 }
2811
2812 return 0;
5c1143bb
XH		 2813}
2814
2815int intel_init_bsd_ring_buffer(struct drm_device *dev)
2816{
4640c4ff 2817 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2818 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
5c1143bb 2819
58fa3835
DV		 2820 ring->name = "bsd ring";
2821 ring->id = VCS;
2822
0fd2c201 2823 ring->write_tail = ring_write_tail;
780f18c8 2824 if (INTEL_INFO(dev)->gen >= 6) {
58fa3835 2825 ring->mmio_base = GEN6_BSD_RING_BASE;
0fd2c201
DV		 2826 /* gen6 bsd needs a special wa for tail updates */
2827 if (IS_GEN6(dev))
2828 ring->write_tail = gen6_bsd_ring_write_tail;
ea251324 2829 ring->flush = gen6_bsd_ring_flush;
58fa3835
DV		 2830 ring->add_request = gen6_add_request;
2831 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2832 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2833 if (INTEL_INFO(dev)->gen >= 8) {
2834 ring->irq_enable_mask =
2835 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2836 ring->irq_get = gen8_ring_get_irq;
2837 ring->irq_put = gen8_ring_put_irq;
1c7a0623
BW		 2838 ring->dispatch_execbuffer =
2839 gen8_ring_dispatch_execbuffer;
707d9cf9 2840 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2841 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2842 ring->semaphore.signal = gen8_xcs_signal;
2843 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2844 }
abd58f01
BW		 2845 } else {
2846 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2847 ring->irq_get = gen6_ring_get_irq;
2848 ring->irq_put = gen6_ring_put_irq;
1c7a0623
BW		 2849 ring->dispatch_execbuffer =
2850 gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2851 if (i915_semaphore_is_enabled(dev)) {
2852 ring->semaphore.sync_to = gen6_ring_sync;
2853 ring->semaphore.signal = gen6_signal;
2854 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2855 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2856 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2857 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2858 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2859 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2860 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2861 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2862 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2863 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2864 }
abd58f01 2865 }
58fa3835
DV		 2866 } else {
2867 ring->mmio_base = BSD_RING_BASE;
58fa3835 2868 ring->flush = bsd_ring_flush;
8620a3a9 2869 ring->add_request = i9xx_add_request;
58fa3835 2870 ring->get_seqno = ring_get_seqno;
b70ec5bf 2871 ring->set_seqno = ring_set_seqno;
e48d8634 2872 if (IS_GEN5(dev)) {
cc609d5d 2873 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
e48d8634
DV		 2874 ring->irq_get = gen5_ring_get_irq;
2875 ring->irq_put = gen5_ring_put_irq;
2876 } else {
e3670319 2877 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
e48d8634
DV		 2878 ring->irq_get = i9xx_ring_get_irq;
2879 ring->irq_put = i9xx_ring_put_irq;
2880 }
fb3256da 2881 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
58fa3835 2882 }
ecfe00d8 2883 ring->init_hw = init_ring_common;
58fa3835 2884
1ec14ad3 2885 return intel_init_ring_buffer(dev, ring);
5c1143bb 2886}
549f7365 2887
845f74a7 2888/**
62659920 2889 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
845f74a7
ZY		 2890 */
2891int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2892{
2893 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2894 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
845f74a7 2895
f7b64236 2896 ring->name = "bsd2 ring";
845f74a7
ZY		 2897 ring->id = VCS2;
2898
2899 ring->write_tail = ring_write_tail;
2900 ring->mmio_base = GEN8_BSD2_RING_BASE;
2901 ring->flush = gen6_bsd_ring_flush;
2902 ring->add_request = gen6_add_request;
2903 ring->get_seqno = gen6_ring_get_seqno;
2904 ring->set_seqno = ring_set_seqno;
2905 ring->irq_enable_mask =
2906 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2907 ring->irq_get = gen8_ring_get_irq;
2908 ring->irq_put = gen8_ring_put_irq;
2909 ring->dispatch_execbuffer =
2910 gen8_ring_dispatch_execbuffer;
3e78998a 2911 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2912 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2913 ring->semaphore.signal = gen8_xcs_signal;
2914 GEN8_RING_SEMAPHORE_INIT;
2915 }
ecfe00d8 2916 ring->init_hw = init_ring_common;
845f74a7
ZY		 2917
2918 return intel_init_ring_buffer(dev, ring);
2919}
2920
549f7365
CW		 2921int intel_init_blt_ring_buffer(struct drm_device *dev)
2922{
4640c4ff 2923 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2924 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
549f7365 2925
3535d9dd
DV		 2926 ring->name = "blitter ring";
2927 ring->id = BCS;
2928
2929 ring->mmio_base = BLT_RING_BASE;
2930 ring->write_tail = ring_write_tail;
ea251324 2931 ring->flush = gen6_ring_flush;
3535d9dd
DV		 2932 ring->add_request = gen6_add_request;
2933 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2934 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2935 if (INTEL_INFO(dev)->gen >= 8) {
2936 ring->irq_enable_mask =
2937 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2938 ring->irq_get = gen8_ring_get_irq;
2939 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2940 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2941 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2942 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2943 ring->semaphore.signal = gen8_xcs_signal;
2944 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2945 }
abd58f01
BW		 2946 } else {
2947 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2948 ring->irq_get = gen6_ring_get_irq;
2949 ring->irq_put = gen6_ring_put_irq;
1c7a0623 2950 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2951 if (i915_semaphore_is_enabled(dev)) {
2952 ring->semaphore.signal = gen6_signal;
2953 ring->semaphore.sync_to = gen6_ring_sync;
2954 /*
2955 * The current semaphore is only applied on pre-gen8
2956 * platform. And there is no VCS2 ring on the pre-gen8
2957 * platform. So the semaphore between BCS and VCS2 is
2958 * initialized as INVALID. Gen8 will initialize the
2959 * sema between BCS and VCS2 later.
2960 */
2961 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2962 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2963 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2964 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2965 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2966 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2967 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2968 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2969 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2970 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2971 }
abd58f01 2972 }
ecfe00d8 2973 ring->init_hw = init_ring_common;
549f7365 2974
1ec14ad3 2975 return intel_init_ring_buffer(dev, ring);
549f7365 2976}
a7b9761d 2977
9a8a2213
BW		 2978int intel_init_vebox_ring_buffer(struct drm_device *dev)
2979{
4640c4ff 2980 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2981 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
9a8a2213
BW		 2982
2983 ring->name = "video enhancement ring";
2984 ring->id = VECS;
2985
2986 ring->mmio_base = VEBOX_RING_BASE;
2987 ring->write_tail = ring_write_tail;
2988 ring->flush = gen6_ring_flush;
2989 ring->add_request = gen6_add_request;
2990 ring->get_seqno = gen6_ring_get_seqno;
2991 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2992
2993 if (INTEL_INFO(dev)->gen >= 8) {
2994 ring->irq_enable_mask =
40c499f9 2995 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
abd58f01
BW		 2996 ring->irq_get = gen8_ring_get_irq;
2997 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2998 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2999 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 3000 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 3001 ring->semaphore.signal = gen8_xcs_signal;
3002 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 3003 }
abd58f01
BW		 3004 } else {
3005 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
3006 ring->irq_get = hsw_vebox_get_irq;
3007 ring->irq_put = hsw_vebox_put_irq;
1c7a0623 3008 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 3009 if (i915_semaphore_is_enabled(dev)) {
3010 ring->semaphore.sync_to = gen6_ring_sync;
3011 ring->semaphore.signal = gen6_signal;
3012 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
3013 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
3014 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
3015 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
3016 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3017 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
3018 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
3019 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
3020 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
3021 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3022 }
abd58f01 3023 }
ecfe00d8 3024 ring->init_hw = init_ring_common;
9a8a2213
BW		 3025
3026 return intel_init_ring_buffer(dev, ring);
3027}
3028
a7b9761d 3029int
4866d729 3030intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
a7b9761d 3031{
4866d729 3032 struct intel_engine_cs *ring = req->ring;
a7b9761d
CW		 3033 int ret;
3034
3035 if (!ring->gpu_caches_dirty)
3036 return 0;
3037
a84c3ae1 3038 ret = ring->flush(req, 0, I915_GEM_GPU_DOMAINS);
a7b9761d
CW		 3039 if (ret)
3040 return ret;
3041
a84c3ae1 3042 trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
a7b9761d
CW		 3043
3044 ring->gpu_caches_dirty = false;
3045 return 0;
3046}
3047
3048int
2f20055d 3049intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
a7b9761d 3050{
2f20055d 3051 struct intel_engine_cs *ring = req->ring;
a7b9761d
CW		 3052 uint32_t flush_domains;
3053 int ret;
3054
3055 flush_domains = 0;
3056 if (ring->gpu_caches_dirty)
3057 flush_domains = I915_GEM_GPU_DOMAINS;
3058
a84c3ae1 3059 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
a7b9761d
CW		 3060 if (ret)
3061 return ret;
3062
a84c3ae1 3063 trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
a7b9761d
CW		 3064
3065 ring->gpu_caches_dirty = false;
3066 return 0;
3067}
e3efda49
CW		 3068
3069void
a4872ba6 3070intel_stop_ring_buffer(struct intel_engine_cs *ring)
e3efda49
CW		 3071{
3072 int ret;
3073
3074 if (!intel_ring_initialized(ring))
3075 return;
3076
3077 ret = intel_ring_idle(ring);
3078 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
3079 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
3080 ring->name, ret);
3081
3082 stop_ring(ring);
3083}
Linux 6.x block layer and io_uring tree(s)