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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
a4d8a0fe | 30 | #include <linux/log2.h> |
760285e7 | 31 | #include <drm/drmP.h> |
62fdfeaf | 32 | #include "i915_drv.h" |
760285e7 | 33 | #include <drm/i915_drm.h> |
62fdfeaf | 34 | #include "i915_trace.h" |
881f47b6 | 35 | #include "intel_drv.h" |
62fdfeaf | 36 | |
a0442461 CW |
37 | /* Rough estimate of the typical request size, performing a flush, |
38 | * set-context and then emitting the batch. | |
39 | */ | |
40 | #define LEGACY_REQUEST_SIZE 200 | |
41 | ||
82e104cc | 42 | int __intel_ring_space(int head, int tail, int size) |
c7dca47b | 43 | { |
4f54741e DG |
44 | int space = head - tail; |
45 | if (space <= 0) | |
1cf0ba14 | 46 | space += size; |
4f54741e | 47 | return space - I915_RING_FREE_SPACE; |
c7dca47b CW |
48 | } |
49 | ||
32c04f16 | 50 | void intel_ring_update_space(struct intel_ring *ring) |
ebd0fd4b | 51 | { |
32c04f16 CW |
52 | if (ring->last_retired_head != -1) { |
53 | ring->head = ring->last_retired_head; | |
54 | ring->last_retired_head = -1; | |
ebd0fd4b DG |
55 | } |
56 | ||
32c04f16 CW |
57 | ring->space = __intel_ring_space(ring->head & HEAD_ADDR, |
58 | ring->tail, ring->size); | |
ebd0fd4b DG |
59 | } |
60 | ||
b5321f30 | 61 | static void __intel_engine_submit(struct intel_engine_cs *engine) |
88b4aa87 | 62 | { |
7e37f889 CW |
63 | struct intel_ring *ring = engine->buffer; |
64 | ||
65 | ring->tail &= ring->size - 1; | |
66 | engine->write_tail(engine, ring->tail); | |
09246732 CW |
67 | } |
68 | ||
b72f3acb | 69 | static int |
7c9cf4e3 | 70 | gen2_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
46f0f8d1 | 71 | { |
7e37f889 | 72 | struct intel_ring *ring = req->ring; |
46f0f8d1 CW |
73 | u32 cmd; |
74 | int ret; | |
75 | ||
76 | cmd = MI_FLUSH; | |
46f0f8d1 | 77 | |
7c9cf4e3 | 78 | if (mode & EMIT_INVALIDATE) |
46f0f8d1 CW |
79 | cmd |= MI_READ_FLUSH; |
80 | ||
5fb9de1a | 81 | ret = intel_ring_begin(req, 2); |
46f0f8d1 CW |
82 | if (ret) |
83 | return ret; | |
84 | ||
b5321f30 CW |
85 | intel_ring_emit(ring, cmd); |
86 | intel_ring_emit(ring, MI_NOOP); | |
87 | intel_ring_advance(ring); | |
46f0f8d1 CW |
88 | |
89 | return 0; | |
90 | } | |
91 | ||
92 | static int | |
7c9cf4e3 | 93 | gen4_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
62fdfeaf | 94 | { |
7e37f889 | 95 | struct intel_ring *ring = req->ring; |
6f392d54 | 96 | u32 cmd; |
b72f3acb | 97 | int ret; |
6f392d54 | 98 | |
36d527de CW |
99 | /* |
100 | * read/write caches: | |
101 | * | |
102 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
103 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
104 | * also flushed at 2d versus 3d pipeline switches. | |
105 | * | |
106 | * read-only caches: | |
107 | * | |
108 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
109 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
110 | * | |
111 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
112 | * | |
113 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
114 | * invalidated when MI_EXE_FLUSH is set. | |
115 | * | |
116 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
117 | * invalidated with every MI_FLUSH. | |
118 | * | |
119 | * TLBs: | |
120 | * | |
121 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
122 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
123 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
124 | * are flushed at any MI_FLUSH. | |
125 | */ | |
126 | ||
b5321f30 | 127 | cmd = MI_FLUSH; |
7c9cf4e3 | 128 | if (mode & EMIT_INVALIDATE) { |
36d527de | 129 | cmd |= MI_EXE_FLUSH; |
b5321f30 CW |
130 | if (IS_G4X(req->i915) || IS_GEN5(req->i915)) |
131 | cmd |= MI_INVALIDATE_ISP; | |
132 | } | |
70eac33e | 133 | |
5fb9de1a | 134 | ret = intel_ring_begin(req, 2); |
36d527de CW |
135 | if (ret) |
136 | return ret; | |
b72f3acb | 137 | |
b5321f30 CW |
138 | intel_ring_emit(ring, cmd); |
139 | intel_ring_emit(ring, MI_NOOP); | |
140 | intel_ring_advance(ring); | |
b72f3acb CW |
141 | |
142 | return 0; | |
8187a2b7 ZN |
143 | } |
144 | ||
8d315287 JB |
145 | /** |
146 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
147 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
148 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
149 | * | |
150 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
151 | * produced by non-pipelined state commands), software needs to first | |
152 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
153 | * 0. | |
154 | * | |
155 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
156 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
157 | * | |
158 | * And the workaround for these two requires this workaround first: | |
159 | * | |
160 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
161 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
162 | * flushes. | |
163 | * | |
164 | * And this last workaround is tricky because of the requirements on | |
165 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
166 | * volume 2 part 1: | |
167 | * | |
168 | * "1 of the following must also be set: | |
169 | * - Render Target Cache Flush Enable ([12] of DW1) | |
170 | * - Depth Cache Flush Enable ([0] of DW1) | |
171 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
172 | * - Depth Stall ([13] of DW1) | |
173 | * - Post-Sync Operation ([13] of DW1) | |
174 | * - Notify Enable ([8] of DW1)" | |
175 | * | |
176 | * The cache flushes require the workaround flush that triggered this | |
177 | * one, so we can't use it. Depth stall would trigger the same. | |
178 | * Post-sync nonzero is what triggered this second workaround, so we | |
179 | * can't use that one either. Notify enable is IRQs, which aren't | |
180 | * really our business. That leaves only stall at scoreboard. | |
181 | */ | |
182 | static int | |
f2cf1fcc | 183 | intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req) |
8d315287 | 184 | { |
7e37f889 | 185 | struct intel_ring *ring = req->ring; |
b5321f30 CW |
186 | u32 scratch_addr = |
187 | req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; | |
8d315287 JB |
188 | int ret; |
189 | ||
5fb9de1a | 190 | ret = intel_ring_begin(req, 6); |
8d315287 JB |
191 | if (ret) |
192 | return ret; | |
193 | ||
b5321f30 CW |
194 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
195 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
8d315287 | 196 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
b5321f30 CW |
197 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); |
198 | intel_ring_emit(ring, 0); /* low dword */ | |
199 | intel_ring_emit(ring, 0); /* high dword */ | |
200 | intel_ring_emit(ring, MI_NOOP); | |
201 | intel_ring_advance(ring); | |
8d315287 | 202 | |
5fb9de1a | 203 | ret = intel_ring_begin(req, 6); |
8d315287 JB |
204 | if (ret) |
205 | return ret; | |
206 | ||
b5321f30 CW |
207 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
208 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); | |
209 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
210 | intel_ring_emit(ring, 0); | |
211 | intel_ring_emit(ring, 0); | |
212 | intel_ring_emit(ring, MI_NOOP); | |
213 | intel_ring_advance(ring); | |
8d315287 JB |
214 | |
215 | return 0; | |
216 | } | |
217 | ||
218 | static int | |
7c9cf4e3 | 219 | gen6_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
8d315287 | 220 | { |
7e37f889 | 221 | struct intel_ring *ring = req->ring; |
b5321f30 CW |
222 | u32 scratch_addr = |
223 | req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; | |
8d315287 | 224 | u32 flags = 0; |
8d315287 JB |
225 | int ret; |
226 | ||
b3111509 | 227 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
f2cf1fcc | 228 | ret = intel_emit_post_sync_nonzero_flush(req); |
b3111509 PZ |
229 | if (ret) |
230 | return ret; | |
231 | ||
8d315287 JB |
232 | /* Just flush everything. Experiments have shown that reducing the |
233 | * number of bits based on the write domains has little performance | |
234 | * impact. | |
235 | */ | |
7c9cf4e3 | 236 | if (mode & EMIT_FLUSH) { |
7d54a904 CW |
237 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
238 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
239 | /* | |
240 | * Ensure that any following seqno writes only happen | |
241 | * when the render cache is indeed flushed. | |
242 | */ | |
97f209bc | 243 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 | 244 | } |
7c9cf4e3 | 245 | if (mode & EMIT_INVALIDATE) { |
7d54a904 CW |
246 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
247 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
248 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
249 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
250 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
251 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
252 | /* | |
253 | * TLB invalidate requires a post-sync write. | |
254 | */ | |
3ac78313 | 255 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 256 | } |
8d315287 | 257 | |
5fb9de1a | 258 | ret = intel_ring_begin(req, 4); |
8d315287 JB |
259 | if (ret) |
260 | return ret; | |
261 | ||
b5321f30 CW |
262 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
263 | intel_ring_emit(ring, flags); | |
264 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
265 | intel_ring_emit(ring, 0); | |
266 | intel_ring_advance(ring); | |
8d315287 JB |
267 | |
268 | return 0; | |
269 | } | |
270 | ||
f3987631 | 271 | static int |
f2cf1fcc | 272 | gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req) |
f3987631 | 273 | { |
7e37f889 | 274 | struct intel_ring *ring = req->ring; |
f3987631 PZ |
275 | int ret; |
276 | ||
5fb9de1a | 277 | ret = intel_ring_begin(req, 4); |
f3987631 PZ |
278 | if (ret) |
279 | return ret; | |
280 | ||
b5321f30 CW |
281 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
282 | intel_ring_emit(ring, | |
283 | PIPE_CONTROL_CS_STALL | | |
284 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
285 | intel_ring_emit(ring, 0); | |
286 | intel_ring_emit(ring, 0); | |
287 | intel_ring_advance(ring); | |
f3987631 PZ |
288 | |
289 | return 0; | |
290 | } | |
291 | ||
4772eaeb | 292 | static int |
7c9cf4e3 | 293 | gen7_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
4772eaeb | 294 | { |
7e37f889 | 295 | struct intel_ring *ring = req->ring; |
b5321f30 CW |
296 | u32 scratch_addr = |
297 | req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; | |
4772eaeb | 298 | u32 flags = 0; |
4772eaeb PZ |
299 | int ret; |
300 | ||
f3987631 PZ |
301 | /* |
302 | * Ensure that any following seqno writes only happen when the render | |
303 | * cache is indeed flushed. | |
304 | * | |
305 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
306 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
307 | * don't try to be clever and just set it unconditionally. | |
308 | */ | |
309 | flags |= PIPE_CONTROL_CS_STALL; | |
310 | ||
4772eaeb PZ |
311 | /* Just flush everything. Experiments have shown that reducing the |
312 | * number of bits based on the write domains has little performance | |
313 | * impact. | |
314 | */ | |
7c9cf4e3 | 315 | if (mode & EMIT_FLUSH) { |
4772eaeb PZ |
316 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
317 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 318 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 319 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4772eaeb | 320 | } |
7c9cf4e3 | 321 | if (mode & EMIT_INVALIDATE) { |
4772eaeb PZ |
322 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
323 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
324 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
325 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
326 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
327 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
148b83d0 | 328 | flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; |
4772eaeb PZ |
329 | /* |
330 | * TLB invalidate requires a post-sync write. | |
331 | */ | |
332 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 333 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 | 334 | |
add284a3 CW |
335 | flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; |
336 | ||
f3987631 PZ |
337 | /* Workaround: we must issue a pipe_control with CS-stall bit |
338 | * set before a pipe_control command that has the state cache | |
339 | * invalidate bit set. */ | |
f2cf1fcc | 340 | gen7_render_ring_cs_stall_wa(req); |
4772eaeb PZ |
341 | } |
342 | ||
5fb9de1a | 343 | ret = intel_ring_begin(req, 4); |
4772eaeb PZ |
344 | if (ret) |
345 | return ret; | |
346 | ||
b5321f30 CW |
347 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
348 | intel_ring_emit(ring, flags); | |
349 | intel_ring_emit(ring, scratch_addr); | |
350 | intel_ring_emit(ring, 0); | |
351 | intel_ring_advance(ring); | |
4772eaeb PZ |
352 | |
353 | return 0; | |
354 | } | |
355 | ||
884ceace | 356 | static int |
f2cf1fcc | 357 | gen8_emit_pipe_control(struct drm_i915_gem_request *req, |
884ceace KG |
358 | u32 flags, u32 scratch_addr) |
359 | { | |
7e37f889 | 360 | struct intel_ring *ring = req->ring; |
884ceace KG |
361 | int ret; |
362 | ||
5fb9de1a | 363 | ret = intel_ring_begin(req, 6); |
884ceace KG |
364 | if (ret) |
365 | return ret; | |
366 | ||
b5321f30 CW |
367 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
368 | intel_ring_emit(ring, flags); | |
369 | intel_ring_emit(ring, scratch_addr); | |
370 | intel_ring_emit(ring, 0); | |
371 | intel_ring_emit(ring, 0); | |
372 | intel_ring_emit(ring, 0); | |
373 | intel_ring_advance(ring); | |
884ceace KG |
374 | |
375 | return 0; | |
376 | } | |
377 | ||
a5f3d68e | 378 | static int |
7c9cf4e3 | 379 | gen8_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
a5f3d68e | 380 | { |
4a570db5 | 381 | u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
b5321f30 | 382 | u32 flags = 0; |
02c9f7e3 | 383 | int ret; |
a5f3d68e BW |
384 | |
385 | flags |= PIPE_CONTROL_CS_STALL; | |
386 | ||
7c9cf4e3 | 387 | if (mode & EMIT_FLUSH) { |
a5f3d68e BW |
388 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
389 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 390 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 391 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
a5f3d68e | 392 | } |
7c9cf4e3 | 393 | if (mode & EMIT_INVALIDATE) { |
a5f3d68e BW |
394 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
395 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
396 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
397 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
398 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
399 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
400 | flags |= PIPE_CONTROL_QW_WRITE; | |
401 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
02c9f7e3 KG |
402 | |
403 | /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ | |
f2cf1fcc | 404 | ret = gen8_emit_pipe_control(req, |
02c9f7e3 KG |
405 | PIPE_CONTROL_CS_STALL | |
406 | PIPE_CONTROL_STALL_AT_SCOREBOARD, | |
407 | 0); | |
408 | if (ret) | |
409 | return ret; | |
a5f3d68e BW |
410 | } |
411 | ||
f2cf1fcc | 412 | return gen8_emit_pipe_control(req, flags, scratch_addr); |
a5f3d68e BW |
413 | } |
414 | ||
0bc40be8 | 415 | static void ring_write_tail(struct intel_engine_cs *engine, |
297b0c5b | 416 | u32 value) |
d46eefa2 | 417 | { |
c033666a | 418 | struct drm_i915_private *dev_priv = engine->i915; |
0bc40be8 | 419 | I915_WRITE_TAIL(engine, value); |
d46eefa2 XH |
420 | } |
421 | ||
7e37f889 | 422 | u64 intel_engine_get_active_head(struct intel_engine_cs *engine) |
8187a2b7 | 423 | { |
c033666a | 424 | struct drm_i915_private *dev_priv = engine->i915; |
50877445 | 425 | u64 acthd; |
8187a2b7 | 426 | |
c033666a | 427 | if (INTEL_GEN(dev_priv) >= 8) |
0bc40be8 TU |
428 | acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base), |
429 | RING_ACTHD_UDW(engine->mmio_base)); | |
c033666a | 430 | else if (INTEL_GEN(dev_priv) >= 4) |
0bc40be8 | 431 | acthd = I915_READ(RING_ACTHD(engine->mmio_base)); |
50877445 CW |
432 | else |
433 | acthd = I915_READ(ACTHD); | |
434 | ||
435 | return acthd; | |
8187a2b7 ZN |
436 | } |
437 | ||
0bc40be8 | 438 | static void ring_setup_phys_status_page(struct intel_engine_cs *engine) |
035dc1e0 | 439 | { |
c033666a | 440 | struct drm_i915_private *dev_priv = engine->i915; |
035dc1e0 DV |
441 | u32 addr; |
442 | ||
443 | addr = dev_priv->status_page_dmah->busaddr; | |
c033666a | 444 | if (INTEL_GEN(dev_priv) >= 4) |
035dc1e0 DV |
445 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
446 | I915_WRITE(HWS_PGA, addr); | |
447 | } | |
448 | ||
0bc40be8 | 449 | static void intel_ring_setup_status_page(struct intel_engine_cs *engine) |
af75f269 | 450 | { |
c033666a | 451 | struct drm_i915_private *dev_priv = engine->i915; |
f0f59a00 | 452 | i915_reg_t mmio; |
af75f269 DL |
453 | |
454 | /* The ring status page addresses are no longer next to the rest of | |
455 | * the ring registers as of gen7. | |
456 | */ | |
c033666a | 457 | if (IS_GEN7(dev_priv)) { |
0bc40be8 | 458 | switch (engine->id) { |
af75f269 DL |
459 | case RCS: |
460 | mmio = RENDER_HWS_PGA_GEN7; | |
461 | break; | |
462 | case BCS: | |
463 | mmio = BLT_HWS_PGA_GEN7; | |
464 | break; | |
465 | /* | |
466 | * VCS2 actually doesn't exist on Gen7. Only shut up | |
467 | * gcc switch check warning | |
468 | */ | |
469 | case VCS2: | |
470 | case VCS: | |
471 | mmio = BSD_HWS_PGA_GEN7; | |
472 | break; | |
473 | case VECS: | |
474 | mmio = VEBOX_HWS_PGA_GEN7; | |
475 | break; | |
476 | } | |
c033666a | 477 | } else if (IS_GEN6(dev_priv)) { |
0bc40be8 | 478 | mmio = RING_HWS_PGA_GEN6(engine->mmio_base); |
af75f269 DL |
479 | } else { |
480 | /* XXX: gen8 returns to sanity */ | |
0bc40be8 | 481 | mmio = RING_HWS_PGA(engine->mmio_base); |
af75f269 DL |
482 | } |
483 | ||
0bc40be8 | 484 | I915_WRITE(mmio, (u32)engine->status_page.gfx_addr); |
af75f269 DL |
485 | POSTING_READ(mmio); |
486 | ||
487 | /* | |
488 | * Flush the TLB for this page | |
489 | * | |
490 | * FIXME: These two bits have disappeared on gen8, so a question | |
491 | * arises: do we still need this and if so how should we go about | |
492 | * invalidating the TLB? | |
493 | */ | |
ac657f64 | 494 | if (IS_GEN(dev_priv, 6, 7)) { |
0bc40be8 | 495 | i915_reg_t reg = RING_INSTPM(engine->mmio_base); |
af75f269 DL |
496 | |
497 | /* ring should be idle before issuing a sync flush*/ | |
0bc40be8 | 498 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
af75f269 DL |
499 | |
500 | I915_WRITE(reg, | |
501 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
502 | INSTPM_SYNC_FLUSH)); | |
25ab57f4 CW |
503 | if (intel_wait_for_register(dev_priv, |
504 | reg, INSTPM_SYNC_FLUSH, 0, | |
505 | 1000)) | |
af75f269 | 506 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", |
0bc40be8 | 507 | engine->name); |
af75f269 DL |
508 | } |
509 | } | |
510 | ||
0bc40be8 | 511 | static bool stop_ring(struct intel_engine_cs *engine) |
8187a2b7 | 512 | { |
c033666a | 513 | struct drm_i915_private *dev_priv = engine->i915; |
8187a2b7 | 514 | |
c033666a | 515 | if (!IS_GEN2(dev_priv)) { |
0bc40be8 | 516 | I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); |
3d808eb1 CW |
517 | if (intel_wait_for_register(dev_priv, |
518 | RING_MI_MODE(engine->mmio_base), | |
519 | MODE_IDLE, | |
520 | MODE_IDLE, | |
521 | 1000)) { | |
0bc40be8 TU |
522 | DRM_ERROR("%s : timed out trying to stop ring\n", |
523 | engine->name); | |
9bec9b13 CW |
524 | /* Sometimes we observe that the idle flag is not |
525 | * set even though the ring is empty. So double | |
526 | * check before giving up. | |
527 | */ | |
0bc40be8 | 528 | if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine)) |
9bec9b13 | 529 | return false; |
9991ae78 CW |
530 | } |
531 | } | |
b7884eb4 | 532 | |
0bc40be8 TU |
533 | I915_WRITE_CTL(engine, 0); |
534 | I915_WRITE_HEAD(engine, 0); | |
535 | engine->write_tail(engine, 0); | |
8187a2b7 | 536 | |
c033666a | 537 | if (!IS_GEN2(dev_priv)) { |
0bc40be8 TU |
538 | (void)I915_READ_CTL(engine); |
539 | I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); | |
9991ae78 | 540 | } |
a51435a3 | 541 | |
0bc40be8 | 542 | return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0; |
9991ae78 | 543 | } |
8187a2b7 | 544 | |
0bc40be8 | 545 | static int init_ring_common(struct intel_engine_cs *engine) |
9991ae78 | 546 | { |
c033666a | 547 | struct drm_i915_private *dev_priv = engine->i915; |
7e37f889 CW |
548 | struct intel_ring *ring = engine->buffer; |
549 | struct drm_i915_gem_object *obj = ring->obj; | |
9991ae78 CW |
550 | int ret = 0; |
551 | ||
59bad947 | 552 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
9991ae78 | 553 | |
0bc40be8 | 554 | if (!stop_ring(engine)) { |
9991ae78 | 555 | /* G45 ring initialization often fails to reset head to zero */ |
6fd0d56e CW |
556 | DRM_DEBUG_KMS("%s head not reset to zero " |
557 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
558 | engine->name, |
559 | I915_READ_CTL(engine), | |
560 | I915_READ_HEAD(engine), | |
561 | I915_READ_TAIL(engine), | |
562 | I915_READ_START(engine)); | |
8187a2b7 | 563 | |
0bc40be8 | 564 | if (!stop_ring(engine)) { |
6fd0d56e CW |
565 | DRM_ERROR("failed to set %s head to zero " |
566 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
567 | engine->name, |
568 | I915_READ_CTL(engine), | |
569 | I915_READ_HEAD(engine), | |
570 | I915_READ_TAIL(engine), | |
571 | I915_READ_START(engine)); | |
9991ae78 CW |
572 | ret = -EIO; |
573 | goto out; | |
6fd0d56e | 574 | } |
8187a2b7 ZN |
575 | } |
576 | ||
c033666a | 577 | if (I915_NEED_GFX_HWS(dev_priv)) |
0bc40be8 | 578 | intel_ring_setup_status_page(engine); |
9991ae78 | 579 | else |
0bc40be8 | 580 | ring_setup_phys_status_page(engine); |
9991ae78 | 581 | |
ece4a17d | 582 | /* Enforce ordering by reading HEAD register back */ |
0bc40be8 | 583 | I915_READ_HEAD(engine); |
ece4a17d | 584 | |
0d8957c8 DV |
585 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
586 | * registers with the above sequence (the readback of the HEAD registers | |
587 | * also enforces ordering), otherwise the hw might lose the new ring | |
588 | * register values. */ | |
0bc40be8 | 589 | I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj)); |
95468892 CW |
590 | |
591 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ | |
0bc40be8 | 592 | if (I915_READ_HEAD(engine)) |
95468892 | 593 | DRM_DEBUG("%s initialization failed [head=%08x], fudging\n", |
0bc40be8 TU |
594 | engine->name, I915_READ_HEAD(engine)); |
595 | I915_WRITE_HEAD(engine, 0); | |
596 | (void)I915_READ_HEAD(engine); | |
95468892 | 597 | |
0bc40be8 | 598 | I915_WRITE_CTL(engine, |
7e37f889 | 599 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 600 | | RING_VALID); |
8187a2b7 | 601 | |
8187a2b7 | 602 | /* If the head is still not zero, the ring is dead */ |
0bc40be8 TU |
603 | if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 && |
604 | I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) && | |
605 | (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) { | |
e74cfed5 | 606 | DRM_ERROR("%s initialization failed " |
48e48a0b | 607 | "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n", |
0bc40be8 TU |
608 | engine->name, |
609 | I915_READ_CTL(engine), | |
610 | I915_READ_CTL(engine) & RING_VALID, | |
611 | I915_READ_HEAD(engine), I915_READ_TAIL(engine), | |
612 | I915_READ_START(engine), | |
613 | (unsigned long)i915_gem_obj_ggtt_offset(obj)); | |
b7884eb4 DV |
614 | ret = -EIO; |
615 | goto out; | |
8187a2b7 ZN |
616 | } |
617 | ||
7e37f889 CW |
618 | ring->last_retired_head = -1; |
619 | ring->head = I915_READ_HEAD(engine); | |
620 | ring->tail = I915_READ_TAIL(engine) & TAIL_ADDR; | |
621 | intel_ring_update_space(ring); | |
1ec14ad3 | 622 | |
fc0768ce | 623 | intel_engine_init_hangcheck(engine); |
50f018df | 624 | |
b7884eb4 | 625 | out: |
59bad947 | 626 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
627 | |
628 | return ret; | |
8187a2b7 ZN |
629 | } |
630 | ||
f8291952 | 631 | void intel_fini_pipe_control(struct intel_engine_cs *engine) |
9b1136d5 | 632 | { |
0bc40be8 | 633 | if (engine->scratch.obj == NULL) |
9b1136d5 OM |
634 | return; |
635 | ||
f8291952 | 636 | i915_gem_object_ggtt_unpin(engine->scratch.obj); |
f8c417cd | 637 | i915_gem_object_put(engine->scratch.obj); |
0bc40be8 | 638 | engine->scratch.obj = NULL; |
9b1136d5 OM |
639 | } |
640 | ||
7d5ea807 | 641 | int intel_init_pipe_control(struct intel_engine_cs *engine, int size) |
c6df541c | 642 | { |
f8291952 | 643 | struct drm_i915_gem_object *obj; |
c6df541c CW |
644 | int ret; |
645 | ||
0bc40be8 | 646 | WARN_ON(engine->scratch.obj); |
c6df541c | 647 | |
91c8a326 | 648 | obj = i915_gem_object_create_stolen(&engine->i915->drm, size); |
de8fe166 | 649 | if (!obj) |
91c8a326 | 650 | obj = i915_gem_object_create(&engine->i915->drm, size); |
f8291952 CW |
651 | if (IS_ERR(obj)) { |
652 | DRM_ERROR("Failed to allocate scratch page\n"); | |
653 | ret = PTR_ERR(obj); | |
c6df541c CW |
654 | goto err; |
655 | } | |
e4ffd173 | 656 | |
f8291952 | 657 | ret = i915_gem_obj_ggtt_pin(obj, 4096, PIN_HIGH); |
a9cc726c DV |
658 | if (ret) |
659 | goto err_unref; | |
c6df541c | 660 | |
f8291952 CW |
661 | engine->scratch.obj = obj; |
662 | engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); | |
2b1086cc | 663 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
0bc40be8 | 664 | engine->name, engine->scratch.gtt_offset); |
c6df541c CW |
665 | return 0; |
666 | ||
c6df541c | 667 | err_unref: |
f8c417cd | 668 | i915_gem_object_put(engine->scratch.obj); |
c6df541c | 669 | err: |
c6df541c CW |
670 | return ret; |
671 | } | |
672 | ||
e2be4faf | 673 | static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req) |
86d7f238 | 674 | { |
7e37f889 | 675 | struct intel_ring *ring = req->ring; |
c033666a CW |
676 | struct i915_workarounds *w = &req->i915->workarounds; |
677 | int ret, i; | |
888b5995 | 678 | |
02235808 | 679 | if (w->count == 0) |
7225342a | 680 | return 0; |
888b5995 | 681 | |
7c9cf4e3 | 682 | ret = req->engine->emit_flush(req, EMIT_BARRIER); |
7225342a MK |
683 | if (ret) |
684 | return ret; | |
888b5995 | 685 | |
5fb9de1a | 686 | ret = intel_ring_begin(req, (w->count * 2 + 2)); |
7225342a MK |
687 | if (ret) |
688 | return ret; | |
689 | ||
b5321f30 | 690 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count)); |
7225342a | 691 | for (i = 0; i < w->count; i++) { |
b5321f30 CW |
692 | intel_ring_emit_reg(ring, w->reg[i].addr); |
693 | intel_ring_emit(ring, w->reg[i].value); | |
7225342a | 694 | } |
b5321f30 | 695 | intel_ring_emit(ring, MI_NOOP); |
7225342a | 696 | |
b5321f30 | 697 | intel_ring_advance(ring); |
7225342a | 698 | |
7c9cf4e3 | 699 | ret = req->engine->emit_flush(req, EMIT_BARRIER); |
7225342a MK |
700 | if (ret) |
701 | return ret; | |
888b5995 | 702 | |
7225342a | 703 | DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count); |
888b5995 | 704 | |
7225342a | 705 | return 0; |
86d7f238 AS |
706 | } |
707 | ||
8753181e | 708 | static int intel_rcs_ctx_init(struct drm_i915_gem_request *req) |
8f0e2b9d DV |
709 | { |
710 | int ret; | |
711 | ||
e2be4faf | 712 | ret = intel_ring_workarounds_emit(req); |
8f0e2b9d DV |
713 | if (ret != 0) |
714 | return ret; | |
715 | ||
be01363f | 716 | ret = i915_gem_render_state_init(req); |
8f0e2b9d | 717 | if (ret) |
e26e1b97 | 718 | return ret; |
8f0e2b9d | 719 | |
e26e1b97 | 720 | return 0; |
8f0e2b9d DV |
721 | } |
722 | ||
7225342a | 723 | static int wa_add(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
724 | i915_reg_t addr, |
725 | const u32 mask, const u32 val) | |
7225342a MK |
726 | { |
727 | const u32 idx = dev_priv->workarounds.count; | |
728 | ||
729 | if (WARN_ON(idx >= I915_MAX_WA_REGS)) | |
730 | return -ENOSPC; | |
731 | ||
732 | dev_priv->workarounds.reg[idx].addr = addr; | |
733 | dev_priv->workarounds.reg[idx].value = val; | |
734 | dev_priv->workarounds.reg[idx].mask = mask; | |
735 | ||
736 | dev_priv->workarounds.count++; | |
737 | ||
738 | return 0; | |
86d7f238 AS |
739 | } |
740 | ||
ca5a0fbd | 741 | #define WA_REG(addr, mask, val) do { \ |
cf4b0de6 | 742 | const int r = wa_add(dev_priv, (addr), (mask), (val)); \ |
7225342a MK |
743 | if (r) \ |
744 | return r; \ | |
ca5a0fbd | 745 | } while (0) |
7225342a MK |
746 | |
747 | #define WA_SET_BIT_MASKED(addr, mask) \ | |
26459343 | 748 | WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask)) |
7225342a MK |
749 | |
750 | #define WA_CLR_BIT_MASKED(addr, mask) \ | |
26459343 | 751 | WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask)) |
7225342a | 752 | |
98533251 | 753 | #define WA_SET_FIELD_MASKED(addr, mask, value) \ |
cf4b0de6 | 754 | WA_REG(addr, mask, _MASKED_FIELD(mask, value)) |
7225342a | 755 | |
cf4b0de6 DL |
756 | #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask)) |
757 | #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask)) | |
7225342a | 758 | |
cf4b0de6 | 759 | #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val) |
7225342a | 760 | |
0bc40be8 TU |
761 | static int wa_ring_whitelist_reg(struct intel_engine_cs *engine, |
762 | i915_reg_t reg) | |
33136b06 | 763 | { |
c033666a | 764 | struct drm_i915_private *dev_priv = engine->i915; |
33136b06 | 765 | struct i915_workarounds *wa = &dev_priv->workarounds; |
0bc40be8 | 766 | const uint32_t index = wa->hw_whitelist_count[engine->id]; |
33136b06 AS |
767 | |
768 | if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS)) | |
769 | return -EINVAL; | |
770 | ||
0bc40be8 | 771 | WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index), |
33136b06 | 772 | i915_mmio_reg_offset(reg)); |
0bc40be8 | 773 | wa->hw_whitelist_count[engine->id]++; |
33136b06 AS |
774 | |
775 | return 0; | |
776 | } | |
777 | ||
0bc40be8 | 778 | static int gen8_init_workarounds(struct intel_engine_cs *engine) |
e9a64ada | 779 | { |
c033666a | 780 | struct drm_i915_private *dev_priv = engine->i915; |
68c6198b AS |
781 | |
782 | WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); | |
e9a64ada | 783 | |
717d84d6 AS |
784 | /* WaDisableAsyncFlipPerfMode:bdw,chv */ |
785 | WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE); | |
786 | ||
d0581194 AS |
787 | /* WaDisablePartialInstShootdown:bdw,chv */ |
788 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
789 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); | |
790 | ||
a340af58 AS |
791 | /* Use Force Non-Coherent whenever executing a 3D context. This is a |
792 | * workaround for for a possible hang in the unlikely event a TLB | |
793 | * invalidation occurs during a PSD flush. | |
794 | */ | |
795 | /* WaForceEnableNonCoherent:bdw,chv */ | |
120f5d28 | 796 | /* WaHdcDisableFetchWhenMasked:bdw,chv */ |
a340af58 | 797 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
120f5d28 | 798 | HDC_DONOT_FETCH_MEM_WHEN_MASKED | |
a340af58 AS |
799 | HDC_FORCE_NON_COHERENT); |
800 | ||
6def8fdd AS |
801 | /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: |
802 | * "The Hierarchical Z RAW Stall Optimization allows non-overlapping | |
803 | * polygons in the same 8x4 pixel/sample area to be processed without | |
804 | * stalling waiting for the earlier ones to write to Hierarchical Z | |
805 | * buffer." | |
806 | * | |
807 | * This optimization is off by default for BDW and CHV; turn it on. | |
808 | */ | |
809 | WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); | |
810 | ||
48404636 AS |
811 | /* Wa4x4STCOptimizationDisable:bdw,chv */ |
812 | WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); | |
813 | ||
7eebcde6 AS |
814 | /* |
815 | * BSpec recommends 8x4 when MSAA is used, | |
816 | * however in practice 16x4 seems fastest. | |
817 | * | |
818 | * Note that PS/WM thread counts depend on the WIZ hashing | |
819 | * disable bit, which we don't touch here, but it's good | |
820 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
821 | */ | |
822 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
823 | GEN6_WIZ_HASHING_MASK, | |
824 | GEN6_WIZ_HASHING_16x4); | |
825 | ||
e9a64ada AS |
826 | return 0; |
827 | } | |
828 | ||
0bc40be8 | 829 | static int bdw_init_workarounds(struct intel_engine_cs *engine) |
86d7f238 | 830 | { |
c033666a | 831 | struct drm_i915_private *dev_priv = engine->i915; |
e9a64ada | 832 | int ret; |
86d7f238 | 833 | |
0bc40be8 | 834 | ret = gen8_init_workarounds(engine); |
e9a64ada AS |
835 | if (ret) |
836 | return ret; | |
837 | ||
101b376d | 838 | /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ |
d0581194 | 839 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
86d7f238 | 840 | |
101b376d | 841 | /* WaDisableDopClockGating:bdw */ |
7225342a MK |
842 | WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, |
843 | DOP_CLOCK_GATING_DISABLE); | |
86d7f238 | 844 | |
7225342a MK |
845 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
846 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
86d7f238 | 847 | |
7225342a | 848 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
35cb6f3b DL |
849 | /* WaForceContextSaveRestoreNonCoherent:bdw */ |
850 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | | |
35cb6f3b | 851 | /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ |
c033666a | 852 | (IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); |
86d7f238 | 853 | |
86d7f238 AS |
854 | return 0; |
855 | } | |
856 | ||
0bc40be8 | 857 | static int chv_init_workarounds(struct intel_engine_cs *engine) |
00e1e623 | 858 | { |
c033666a | 859 | struct drm_i915_private *dev_priv = engine->i915; |
e9a64ada | 860 | int ret; |
00e1e623 | 861 | |
0bc40be8 | 862 | ret = gen8_init_workarounds(engine); |
e9a64ada AS |
863 | if (ret) |
864 | return ret; | |
865 | ||
00e1e623 | 866 | /* WaDisableThreadStallDopClockGating:chv */ |
d0581194 | 867 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
00e1e623 | 868 | |
d60de81d KG |
869 | /* Improve HiZ throughput on CHV. */ |
870 | WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); | |
871 | ||
7225342a MK |
872 | return 0; |
873 | } | |
874 | ||
0bc40be8 | 875 | static int gen9_init_workarounds(struct intel_engine_cs *engine) |
3b106531 | 876 | { |
c033666a | 877 | struct drm_i915_private *dev_priv = engine->i915; |
e0f3fa09 | 878 | int ret; |
ab0dfafe | 879 | |
a8ab5ed5 TG |
880 | /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */ |
881 | I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE)); | |
882 | ||
e5f81d65 | 883 | /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */ |
9c4cbf82 MK |
884 | I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | |
885 | GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); | |
886 | ||
e5f81d65 | 887 | /* WaDisableKillLogic:bxt,skl,kbl */ |
9c4cbf82 MK |
888 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | |
889 | ECOCHK_DIS_TLB); | |
890 | ||
e5f81d65 MK |
891 | /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */ |
892 | /* WaDisablePartialInstShootdown:skl,bxt,kbl */ | |
ab0dfafe | 893 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
950b2aae | 894 | FLOW_CONTROL_ENABLE | |
ab0dfafe HN |
895 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); |
896 | ||
e5f81d65 | 897 | /* Syncing dependencies between camera and graphics:skl,bxt,kbl */ |
8424171e NH |
898 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
899 | GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC); | |
900 | ||
e87a005d | 901 | /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */ |
c033666a CW |
902 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) || |
903 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) | |
a86eb582 DL |
904 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
905 | GEN9_DG_MIRROR_FIX_ENABLE); | |
1de4582f | 906 | |
e87a005d | 907 | /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ |
c033666a CW |
908 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) || |
909 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { | |
183c6dac DL |
910 | WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, |
911 | GEN9_RHWO_OPTIMIZATION_DISABLE); | |
9b01435d AS |
912 | /* |
913 | * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set | |
914 | * but we do that in per ctx batchbuffer as there is an issue | |
915 | * with this register not getting restored on ctx restore | |
916 | */ | |
183c6dac DL |
917 | } |
918 | ||
e5f81d65 MK |
919 | /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */ |
920 | /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */ | |
bfd8ad4e TG |
921 | WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, |
922 | GEN9_ENABLE_YV12_BUGFIX | | |
923 | GEN9_ENABLE_GPGPU_PREEMPTION); | |
cac23df4 | 924 | |
e5f81d65 MK |
925 | /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */ |
926 | /* WaDisablePartialResolveInVc:skl,bxt,kbl */ | |
60294683 AS |
927 | WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE | |
928 | GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE)); | |
9370cd98 | 929 | |
e5f81d65 | 930 | /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */ |
e2db7071 DL |
931 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
932 | GEN9_CCS_TLB_PREFETCH_ENABLE); | |
933 | ||
5a2ae95e | 934 | /* WaDisableMaskBasedCammingInRCC:skl,bxt */ |
c033666a CW |
935 | if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_C0) || |
936 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) | |
38a39a7b BW |
937 | WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, |
938 | PIXEL_MASK_CAMMING_DISABLE); | |
939 | ||
5b0e3659 MK |
940 | /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */ |
941 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
942 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | | |
943 | HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); | |
8ea6f892 | 944 | |
bbaefe72 MK |
945 | /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are |
946 | * both tied to WaForceContextSaveRestoreNonCoherent | |
947 | * in some hsds for skl. We keep the tie for all gen9. The | |
948 | * documentation is a bit hazy and so we want to get common behaviour, | |
949 | * even though there is no clear evidence we would need both on kbl/bxt. | |
950 | * This area has been source of system hangs so we play it safe | |
951 | * and mimic the skl regardless of what bspec says. | |
952 | * | |
953 | * Use Force Non-Coherent whenever executing a 3D context. This | |
954 | * is a workaround for a possible hang in the unlikely event | |
955 | * a TLB invalidation occurs during a PSD flush. | |
956 | */ | |
957 | ||
958 | /* WaForceEnableNonCoherent:skl,bxt,kbl */ | |
959 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
960 | HDC_FORCE_NON_COHERENT); | |
961 | ||
962 | /* WaDisableHDCInvalidation:skl,bxt,kbl */ | |
963 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | | |
964 | BDW_DISABLE_HDC_INVALIDATION); | |
965 | ||
e5f81d65 MK |
966 | /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */ |
967 | if (IS_SKYLAKE(dev_priv) || | |
968 | IS_KABYLAKE(dev_priv) || | |
969 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) | |
8c761609 AS |
970 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
971 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
8c761609 | 972 | |
e5f81d65 | 973 | /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */ |
6b6d5626 RB |
974 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); |
975 | ||
e5f81d65 | 976 | /* WaOCLCoherentLineFlush:skl,bxt,kbl */ |
6ecf56ae AS |
977 | I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | |
978 | GEN8_LQSC_FLUSH_COHERENT_LINES)); | |
979 | ||
6bb62855 | 980 | /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */ |
981 | ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG); | |
982 | if (ret) | |
983 | return ret; | |
984 | ||
e5f81d65 | 985 | /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */ |
0bc40be8 | 986 | ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); |
e0f3fa09 AS |
987 | if (ret) |
988 | return ret; | |
989 | ||
e5f81d65 | 990 | /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */ |
0bc40be8 | 991 | ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); |
3669ab61 AS |
992 | if (ret) |
993 | return ret; | |
994 | ||
3b106531 HN |
995 | return 0; |
996 | } | |
997 | ||
0bc40be8 | 998 | static int skl_tune_iz_hashing(struct intel_engine_cs *engine) |
b7668791 | 999 | { |
c033666a | 1000 | struct drm_i915_private *dev_priv = engine->i915; |
b7668791 DL |
1001 | u8 vals[3] = { 0, 0, 0 }; |
1002 | unsigned int i; | |
1003 | ||
1004 | for (i = 0; i < 3; i++) { | |
1005 | u8 ss; | |
1006 | ||
1007 | /* | |
1008 | * Only consider slices where one, and only one, subslice has 7 | |
1009 | * EUs | |
1010 | */ | |
a4d8a0fe | 1011 | if (!is_power_of_2(dev_priv->info.subslice_7eu[i])) |
b7668791 DL |
1012 | continue; |
1013 | ||
1014 | /* | |
1015 | * subslice_7eu[i] != 0 (because of the check above) and | |
1016 | * ss_max == 4 (maximum number of subslices possible per slice) | |
1017 | * | |
1018 | * -> 0 <= ss <= 3; | |
1019 | */ | |
1020 | ss = ffs(dev_priv->info.subslice_7eu[i]) - 1; | |
1021 | vals[i] = 3 - ss; | |
1022 | } | |
1023 | ||
1024 | if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) | |
1025 | return 0; | |
1026 | ||
1027 | /* Tune IZ hashing. See intel_device_info_runtime_init() */ | |
1028 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
1029 | GEN9_IZ_HASHING_MASK(2) | | |
1030 | GEN9_IZ_HASHING_MASK(1) | | |
1031 | GEN9_IZ_HASHING_MASK(0), | |
1032 | GEN9_IZ_HASHING(2, vals[2]) | | |
1033 | GEN9_IZ_HASHING(1, vals[1]) | | |
1034 | GEN9_IZ_HASHING(0, vals[0])); | |
1035 | ||
1036 | return 0; | |
1037 | } | |
1038 | ||
0bc40be8 | 1039 | static int skl_init_workarounds(struct intel_engine_cs *engine) |
8d205494 | 1040 | { |
c033666a | 1041 | struct drm_i915_private *dev_priv = engine->i915; |
aa0011a8 | 1042 | int ret; |
d0bbbc4f | 1043 | |
0bc40be8 | 1044 | ret = gen9_init_workarounds(engine); |
aa0011a8 AS |
1045 | if (ret) |
1046 | return ret; | |
8d205494 | 1047 | |
a78536e7 AS |
1048 | /* |
1049 | * Actual WA is to disable percontext preemption granularity control | |
1050 | * until D0 which is the default case so this is equivalent to | |
1051 | * !WaDisablePerCtxtPreemptionGranularityControl:skl | |
1052 | */ | |
c033666a | 1053 | if (IS_SKL_REVID(dev_priv, SKL_REVID_E0, REVID_FOREVER)) { |
a78536e7 AS |
1054 | I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1, |
1055 | _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL)); | |
1056 | } | |
1057 | ||
71dce58c | 1058 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0)) { |
9c4cbf82 MK |
1059 | /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */ |
1060 | I915_WRITE(FF_SLICE_CS_CHICKEN2, | |
1061 | _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE)); | |
1062 | } | |
1063 | ||
1064 | /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes | |
1065 | * involving this register should also be added to WA batch as required. | |
1066 | */ | |
c033666a | 1067 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0)) |
9c4cbf82 MK |
1068 | /* WaDisableLSQCROPERFforOCL:skl */ |
1069 | I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | | |
1070 | GEN8_LQSC_RO_PERF_DIS); | |
1071 | ||
1072 | /* WaEnableGapsTsvCreditFix:skl */ | |
c033666a | 1073 | if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER)) { |
9c4cbf82 MK |
1074 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | |
1075 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
1076 | } | |
1077 | ||
d0bbbc4f | 1078 | /* WaDisablePowerCompilerClockGating:skl */ |
c033666a | 1079 | if (IS_SKL_REVID(dev_priv, SKL_REVID_B0, SKL_REVID_B0)) |
d0bbbc4f DL |
1080 | WA_SET_BIT_MASKED(HIZ_CHICKEN, |
1081 | BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE); | |
1082 | ||
e87a005d | 1083 | /* WaBarrierPerformanceFixDisable:skl */ |
c033666a | 1084 | if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0)) |
5b6fd12a VS |
1085 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
1086 | HDC_FENCE_DEST_SLM_DISABLE | | |
1087 | HDC_BARRIER_PERFORMANCE_DISABLE); | |
1088 | ||
9bd9dfb4 | 1089 | /* WaDisableSbeCacheDispatchPortSharing:skl */ |
c033666a | 1090 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0)) |
9bd9dfb4 MK |
1091 | WA_SET_BIT_MASKED( |
1092 | GEN7_HALF_SLICE_CHICKEN1, | |
1093 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
9bd9dfb4 | 1094 | |
eee8efb0 MK |
1095 | /* WaDisableGafsUnitClkGating:skl */ |
1096 | WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); | |
1097 | ||
4ba9c1f7 MK |
1098 | /* WaInPlaceDecompressionHang:skl */ |
1099 | if (IS_SKL_REVID(dev_priv, SKL_REVID_H0, REVID_FOREVER)) | |
1100 | WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA, | |
1101 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); | |
1102 | ||
6107497e | 1103 | /* WaDisableLSQCROPERFforOCL:skl */ |
0bc40be8 | 1104 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
6107497e AS |
1105 | if (ret) |
1106 | return ret; | |
1107 | ||
0bc40be8 | 1108 | return skl_tune_iz_hashing(engine); |
7225342a MK |
1109 | } |
1110 | ||
0bc40be8 | 1111 | static int bxt_init_workarounds(struct intel_engine_cs *engine) |
cae0437f | 1112 | { |
c033666a | 1113 | struct drm_i915_private *dev_priv = engine->i915; |
aa0011a8 | 1114 | int ret; |
dfb601e6 | 1115 | |
0bc40be8 | 1116 | ret = gen9_init_workarounds(engine); |
aa0011a8 AS |
1117 | if (ret) |
1118 | return ret; | |
cae0437f | 1119 | |
9c4cbf82 MK |
1120 | /* WaStoreMultiplePTEenable:bxt */ |
1121 | /* This is a requirement according to Hardware specification */ | |
c033666a | 1122 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) |
9c4cbf82 MK |
1123 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF); |
1124 | ||
1125 | /* WaSetClckGatingDisableMedia:bxt */ | |
c033666a | 1126 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { |
9c4cbf82 MK |
1127 | I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) & |
1128 | ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE)); | |
1129 | } | |
1130 | ||
dfb601e6 NH |
1131 | /* WaDisableThreadStallDopClockGating:bxt */ |
1132 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
1133 | STALL_DOP_GATING_DISABLE); | |
1134 | ||
780f0aeb | 1135 | /* WaDisablePooledEuLoadBalancingFix:bxt */ |
1136 | if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) { | |
1137 | WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2, | |
1138 | GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); | |
1139 | } | |
1140 | ||
983b4b9d | 1141 | /* WaDisableSbeCacheDispatchPortSharing:bxt */ |
c033666a | 1142 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) { |
983b4b9d NH |
1143 | WA_SET_BIT_MASKED( |
1144 | GEN7_HALF_SLICE_CHICKEN1, | |
1145 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
1146 | } | |
1147 | ||
2c8580e4 AS |
1148 | /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */ |
1149 | /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */ | |
1150 | /* WaDisableObjectLevelPreemtionForInstanceId:bxt */ | |
a786d53a | 1151 | /* WaDisableLSQCROPERFforOCL:bxt */ |
c033666a | 1152 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { |
0bc40be8 | 1153 | ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1); |
2c8580e4 AS |
1154 | if (ret) |
1155 | return ret; | |
a786d53a | 1156 | |
0bc40be8 | 1157 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
a786d53a AS |
1158 | if (ret) |
1159 | return ret; | |
2c8580e4 AS |
1160 | } |
1161 | ||
050fc465 | 1162 | /* WaProgramL3SqcReg1DefaultForPerf:bxt */ |
c033666a | 1163 | if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) |
36579cb6 ID |
1164 | I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) | |
1165 | L3_HIGH_PRIO_CREDITS(2)); | |
050fc465 | 1166 | |
ad2bdb44 MK |
1167 | /* WaInsertDummyPushConstPs:bxt */ |
1168 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) | |
1169 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | |
1170 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1171 | ||
4ba9c1f7 MK |
1172 | /* WaInPlaceDecompressionHang:bxt */ |
1173 | if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER)) | |
1174 | WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA, | |
1175 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); | |
1176 | ||
cae0437f NH |
1177 | return 0; |
1178 | } | |
1179 | ||
e5f81d65 MK |
1180 | static int kbl_init_workarounds(struct intel_engine_cs *engine) |
1181 | { | |
e587f6cb | 1182 | struct drm_i915_private *dev_priv = engine->i915; |
e5f81d65 MK |
1183 | int ret; |
1184 | ||
1185 | ret = gen9_init_workarounds(engine); | |
1186 | if (ret) | |
1187 | return ret; | |
1188 | ||
e587f6cb MK |
1189 | /* WaEnableGapsTsvCreditFix:kbl */ |
1190 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | | |
1191 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
1192 | ||
c0b730d5 MK |
1193 | /* WaDisableDynamicCreditSharing:kbl */ |
1194 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) | |
1195 | WA_SET_BIT(GAMT_CHKN_BIT_REG, | |
1196 | GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); | |
1197 | ||
8401d42f MK |
1198 | /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */ |
1199 | if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0)) | |
1200 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
1201 | HDC_FENCE_DEST_SLM_DISABLE); | |
1202 | ||
fe905819 MK |
1203 | /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes |
1204 | * involving this register should also be added to WA batch as required. | |
1205 | */ | |
1206 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0)) | |
1207 | /* WaDisableLSQCROPERFforOCL:kbl */ | |
1208 | I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | | |
1209 | GEN8_LQSC_RO_PERF_DIS); | |
1210 | ||
ad2bdb44 MK |
1211 | /* WaInsertDummyPushConstPs:kbl */ |
1212 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) | |
1213 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | |
1214 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1215 | ||
4de5d7cc MK |
1216 | /* WaDisableGafsUnitClkGating:kbl */ |
1217 | WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); | |
1218 | ||
954337aa MK |
1219 | /* WaDisableSbeCacheDispatchPortSharing:kbl */ |
1220 | WA_SET_BIT_MASKED( | |
1221 | GEN7_HALF_SLICE_CHICKEN1, | |
1222 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
1223 | ||
4ba9c1f7 MK |
1224 | /* WaInPlaceDecompressionHang:kbl */ |
1225 | WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA, | |
1226 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); | |
1227 | ||
fe905819 MK |
1228 | /* WaDisableLSQCROPERFforOCL:kbl */ |
1229 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); | |
1230 | if (ret) | |
1231 | return ret; | |
1232 | ||
e5f81d65 MK |
1233 | return 0; |
1234 | } | |
1235 | ||
0bc40be8 | 1236 | int init_workarounds_ring(struct intel_engine_cs *engine) |
7225342a | 1237 | { |
c033666a | 1238 | struct drm_i915_private *dev_priv = engine->i915; |
7225342a | 1239 | |
0bc40be8 | 1240 | WARN_ON(engine->id != RCS); |
7225342a MK |
1241 | |
1242 | dev_priv->workarounds.count = 0; | |
33136b06 | 1243 | dev_priv->workarounds.hw_whitelist_count[RCS] = 0; |
7225342a | 1244 | |
c033666a | 1245 | if (IS_BROADWELL(dev_priv)) |
0bc40be8 | 1246 | return bdw_init_workarounds(engine); |
7225342a | 1247 | |
c033666a | 1248 | if (IS_CHERRYVIEW(dev_priv)) |
0bc40be8 | 1249 | return chv_init_workarounds(engine); |
00e1e623 | 1250 | |
c033666a | 1251 | if (IS_SKYLAKE(dev_priv)) |
0bc40be8 | 1252 | return skl_init_workarounds(engine); |
cae0437f | 1253 | |
c033666a | 1254 | if (IS_BROXTON(dev_priv)) |
0bc40be8 | 1255 | return bxt_init_workarounds(engine); |
3b106531 | 1256 | |
e5f81d65 MK |
1257 | if (IS_KABYLAKE(dev_priv)) |
1258 | return kbl_init_workarounds(engine); | |
1259 | ||
00e1e623 VS |
1260 | return 0; |
1261 | } | |
1262 | ||
0bc40be8 | 1263 | static int init_render_ring(struct intel_engine_cs *engine) |
8187a2b7 | 1264 | { |
c033666a | 1265 | struct drm_i915_private *dev_priv = engine->i915; |
0bc40be8 | 1266 | int ret = init_ring_common(engine); |
9c33baa6 KZ |
1267 | if (ret) |
1268 | return ret; | |
a69ffdbf | 1269 | |
61a563a2 | 1270 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
ac657f64 | 1271 | if (IS_GEN(dev_priv, 4, 6)) |
6b26c86d | 1272 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
1273 | |
1274 | /* We need to disable the AsyncFlip performance optimisations in order | |
1275 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1276 | * programmed to '1' on all products. | |
8693a824 | 1277 | * |
2441f877 | 1278 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv |
1c8c38c5 | 1279 | */ |
ac657f64 | 1280 | if (IS_GEN(dev_priv, 6, 7)) |
1c8c38c5 CW |
1281 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
1282 | ||
f05bb0c7 | 1283 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 1284 | /* WaEnableFlushTlbInvalidationMode:snb */ |
c033666a | 1285 | if (IS_GEN6(dev_priv)) |
f05bb0c7 | 1286 | I915_WRITE(GFX_MODE, |
aa83e30d | 1287 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 1288 | |
01fa0302 | 1289 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
c033666a | 1290 | if (IS_GEN7(dev_priv)) |
1c8c38c5 | 1291 | I915_WRITE(GFX_MODE_GEN7, |
01fa0302 | 1292 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 1293 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 1294 | |
c033666a | 1295 | if (IS_GEN6(dev_priv)) { |
3a69ddd6 KG |
1296 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
1297 | * "If this bit is set, STCunit will have LRA as replacement | |
1298 | * policy. [...] This bit must be reset. LRA replacement | |
1299 | * policy is not supported." | |
1300 | */ | |
1301 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 1302 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
1303 | } |
1304 | ||
ac657f64 | 1305 | if (IS_GEN(dev_priv, 6, 7)) |
6b26c86d | 1306 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
84f9f938 | 1307 | |
035ea405 VS |
1308 | if (INTEL_INFO(dev_priv)->gen >= 6) |
1309 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); | |
15b9f80e | 1310 | |
0bc40be8 | 1311 | return init_workarounds_ring(engine); |
8187a2b7 ZN |
1312 | } |
1313 | ||
0bc40be8 | 1314 | static void render_ring_cleanup(struct intel_engine_cs *engine) |
c6df541c | 1315 | { |
c033666a | 1316 | struct drm_i915_private *dev_priv = engine->i915; |
3e78998a BW |
1317 | |
1318 | if (dev_priv->semaphore_obj) { | |
1319 | i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj); | |
f8c417cd | 1320 | i915_gem_object_put(dev_priv->semaphore_obj); |
3e78998a BW |
1321 | dev_priv->semaphore_obj = NULL; |
1322 | } | |
b45305fc | 1323 | |
0bc40be8 | 1324 | intel_fini_pipe_control(engine); |
c6df541c CW |
1325 | } |
1326 | ||
f7169687 | 1327 | static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req, |
3e78998a BW |
1328 | unsigned int num_dwords) |
1329 | { | |
1330 | #define MBOX_UPDATE_DWORDS 8 | |
7e37f889 | 1331 | struct intel_ring *signaller = signaller_req->ring; |
c033666a | 1332 | struct drm_i915_private *dev_priv = signaller_req->i915; |
3e78998a | 1333 | struct intel_engine_cs *waiter; |
c3232b18 DG |
1334 | enum intel_engine_id id; |
1335 | int ret, num_rings; | |
3e78998a | 1336 | |
c033666a | 1337 | num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask); |
3e78998a BW |
1338 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; |
1339 | #undef MBOX_UPDATE_DWORDS | |
1340 | ||
5fb9de1a | 1341 | ret = intel_ring_begin(signaller_req, num_dwords); |
3e78998a BW |
1342 | if (ret) |
1343 | return ret; | |
1344 | ||
c3232b18 | 1345 | for_each_engine_id(waiter, dev_priv, id) { |
b5321f30 CW |
1346 | u64 gtt_offset = |
1347 | signaller_req->engine->semaphore.signal_ggtt[id]; | |
3e78998a BW |
1348 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
1349 | continue; | |
1350 | ||
1351 | intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6)); | |
b5321f30 CW |
1352 | intel_ring_emit(signaller, |
1353 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1354 | PIPE_CONTROL_QW_WRITE | | |
1355 | PIPE_CONTROL_CS_STALL); | |
3e78998a BW |
1356 | intel_ring_emit(signaller, lower_32_bits(gtt_offset)); |
1357 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
04769652 | 1358 | intel_ring_emit(signaller, signaller_req->fence.seqno); |
3e78998a | 1359 | intel_ring_emit(signaller, 0); |
b5321f30 CW |
1360 | intel_ring_emit(signaller, |
1361 | MI_SEMAPHORE_SIGNAL | | |
1362 | MI_SEMAPHORE_TARGET(waiter->hw_id)); | |
3e78998a BW |
1363 | intel_ring_emit(signaller, 0); |
1364 | } | |
1365 | ||
1366 | return 0; | |
1367 | } | |
1368 | ||
f7169687 | 1369 | static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req, |
3e78998a BW |
1370 | unsigned int num_dwords) |
1371 | { | |
1372 | #define MBOX_UPDATE_DWORDS 6 | |
7e37f889 | 1373 | struct intel_ring *signaller = signaller_req->ring; |
c033666a | 1374 | struct drm_i915_private *dev_priv = signaller_req->i915; |
3e78998a | 1375 | struct intel_engine_cs *waiter; |
c3232b18 DG |
1376 | enum intel_engine_id id; |
1377 | int ret, num_rings; | |
3e78998a | 1378 | |
c033666a | 1379 | num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask); |
3e78998a BW |
1380 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; |
1381 | #undef MBOX_UPDATE_DWORDS | |
1382 | ||
5fb9de1a | 1383 | ret = intel_ring_begin(signaller_req, num_dwords); |
3e78998a BW |
1384 | if (ret) |
1385 | return ret; | |
1386 | ||
c3232b18 | 1387 | for_each_engine_id(waiter, dev_priv, id) { |
b5321f30 CW |
1388 | u64 gtt_offset = |
1389 | signaller_req->engine->semaphore.signal_ggtt[id]; | |
3e78998a BW |
1390 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
1391 | continue; | |
1392 | ||
b5321f30 CW |
1393 | intel_ring_emit(signaller, |
1394 | (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW); | |
1395 | intel_ring_emit(signaller, | |
1396 | lower_32_bits(gtt_offset) | | |
1397 | MI_FLUSH_DW_USE_GTT); | |
3e78998a | 1398 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); |
04769652 | 1399 | intel_ring_emit(signaller, signaller_req->fence.seqno); |
b5321f30 CW |
1400 | intel_ring_emit(signaller, |
1401 | MI_SEMAPHORE_SIGNAL | | |
1402 | MI_SEMAPHORE_TARGET(waiter->hw_id)); | |
3e78998a BW |
1403 | intel_ring_emit(signaller, 0); |
1404 | } | |
1405 | ||
1406 | return 0; | |
1407 | } | |
1408 | ||
f7169687 | 1409 | static int gen6_signal(struct drm_i915_gem_request *signaller_req, |
024a43e1 | 1410 | unsigned int num_dwords) |
1ec14ad3 | 1411 | { |
7e37f889 | 1412 | struct intel_ring *signaller = signaller_req->ring; |
c033666a | 1413 | struct drm_i915_private *dev_priv = signaller_req->i915; |
a4872ba6 | 1414 | struct intel_engine_cs *useless; |
c3232b18 DG |
1415 | enum intel_engine_id id; |
1416 | int ret, num_rings; | |
78325f2d | 1417 | |
a1444b79 | 1418 | #define MBOX_UPDATE_DWORDS 3 |
c033666a | 1419 | num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask); |
a1444b79 BW |
1420 | num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2); |
1421 | #undef MBOX_UPDATE_DWORDS | |
024a43e1 | 1422 | |
5fb9de1a | 1423 | ret = intel_ring_begin(signaller_req, num_dwords); |
024a43e1 BW |
1424 | if (ret) |
1425 | return ret; | |
024a43e1 | 1426 | |
c3232b18 | 1427 | for_each_engine_id(useless, dev_priv, id) { |
b5321f30 CW |
1428 | i915_reg_t mbox_reg = |
1429 | signaller_req->engine->semaphore.mbox.signal[id]; | |
f0f59a00 VS |
1430 | |
1431 | if (i915_mmio_reg_valid(mbox_reg)) { | |
78325f2d | 1432 | intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1)); |
f92a9162 | 1433 | intel_ring_emit_reg(signaller, mbox_reg); |
04769652 | 1434 | intel_ring_emit(signaller, signaller_req->fence.seqno); |
78325f2d BW |
1435 | } |
1436 | } | |
024a43e1 | 1437 | |
a1444b79 BW |
1438 | /* If num_dwords was rounded, make sure the tail pointer is correct */ |
1439 | if (num_rings % 2 == 0) | |
1440 | intel_ring_emit(signaller, MI_NOOP); | |
1441 | ||
024a43e1 | 1442 | return 0; |
1ec14ad3 CW |
1443 | } |
1444 | ||
c8c99b0f BW |
1445 | /** |
1446 | * gen6_add_request - Update the semaphore mailbox registers | |
ee044a88 JH |
1447 | * |
1448 | * @request - request to write to the ring | |
c8c99b0f BW |
1449 | * |
1450 | * Update the mailbox registers in the *other* rings with the current seqno. | |
1451 | * This acts like a signal in the canonical semaphore. | |
1452 | */ | |
1ec14ad3 | 1453 | static int |
ee044a88 | 1454 | gen6_add_request(struct drm_i915_gem_request *req) |
1ec14ad3 | 1455 | { |
4a570db5 | 1456 | struct intel_engine_cs *engine = req->engine; |
7e37f889 | 1457 | struct intel_ring *ring = req->ring; |
024a43e1 | 1458 | int ret; |
52ed2325 | 1459 | |
e2f80391 TU |
1460 | if (engine->semaphore.signal) |
1461 | ret = engine->semaphore.signal(req, 4); | |
707d9cf9 | 1462 | else |
5fb9de1a | 1463 | ret = intel_ring_begin(req, 4); |
707d9cf9 | 1464 | |
1ec14ad3 CW |
1465 | if (ret) |
1466 | return ret; | |
1467 | ||
b5321f30 CW |
1468 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
1469 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1470 | intel_ring_emit(ring, req->fence.seqno); | |
1471 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
1472 | __intel_engine_submit(engine); | |
1ec14ad3 | 1473 | |
1ec14ad3 CW |
1474 | return 0; |
1475 | } | |
1476 | ||
a58c01aa CW |
1477 | static int |
1478 | gen8_render_add_request(struct drm_i915_gem_request *req) | |
1479 | { | |
1480 | struct intel_engine_cs *engine = req->engine; | |
7e37f889 | 1481 | struct intel_ring *ring = req->ring; |
a58c01aa CW |
1482 | int ret; |
1483 | ||
1484 | if (engine->semaphore.signal) | |
1485 | ret = engine->semaphore.signal(req, 8); | |
1486 | else | |
1487 | ret = intel_ring_begin(req, 8); | |
1488 | if (ret) | |
1489 | return ret; | |
1490 | ||
b5321f30 CW |
1491 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
1492 | intel_ring_emit(ring, (PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1493 | PIPE_CONTROL_CS_STALL | | |
1494 | PIPE_CONTROL_QW_WRITE)); | |
1495 | intel_ring_emit(ring, intel_hws_seqno_address(engine)); | |
1496 | intel_ring_emit(ring, 0); | |
1497 | intel_ring_emit(ring, i915_gem_request_get_seqno(req)); | |
a58c01aa | 1498 | /* We're thrashing one dword of HWS. */ |
b5321f30 CW |
1499 | intel_ring_emit(ring, 0); |
1500 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
1501 | intel_ring_emit(ring, MI_NOOP); | |
1502 | __intel_engine_submit(engine); | |
a58c01aa CW |
1503 | |
1504 | return 0; | |
1505 | } | |
1506 | ||
c033666a | 1507 | static inline bool i915_gem_has_seqno_wrapped(struct drm_i915_private *dev_priv, |
f72b3435 MK |
1508 | u32 seqno) |
1509 | { | |
f72b3435 MK |
1510 | return dev_priv->last_seqno < seqno; |
1511 | } | |
1512 | ||
c8c99b0f BW |
1513 | /** |
1514 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
1515 | * | |
1516 | * @waiter - ring that is waiting | |
1517 | * @signaller - ring which has, or will signal | |
1518 | * @seqno - seqno which the waiter will block on | |
1519 | */ | |
5ee426ca BW |
1520 | |
1521 | static int | |
599d924c | 1522 | gen8_ring_sync(struct drm_i915_gem_request *waiter_req, |
5ee426ca BW |
1523 | struct intel_engine_cs *signaller, |
1524 | u32 seqno) | |
1525 | { | |
7e37f889 | 1526 | struct intel_ring *waiter = waiter_req->ring; |
c033666a | 1527 | struct drm_i915_private *dev_priv = waiter_req->i915; |
b5321f30 | 1528 | u64 offset = GEN8_WAIT_OFFSET(waiter_req->engine, signaller->id); |
6ef48d7f | 1529 | struct i915_hw_ppgtt *ppgtt; |
5ee426ca BW |
1530 | int ret; |
1531 | ||
5fb9de1a | 1532 | ret = intel_ring_begin(waiter_req, 4); |
5ee426ca BW |
1533 | if (ret) |
1534 | return ret; | |
1535 | ||
1536 | intel_ring_emit(waiter, MI_SEMAPHORE_WAIT | | |
1537 | MI_SEMAPHORE_GLOBAL_GTT | | |
1538 | MI_SEMAPHORE_SAD_GTE_SDD); | |
1539 | intel_ring_emit(waiter, seqno); | |
c38c651b TU |
1540 | intel_ring_emit(waiter, lower_32_bits(offset)); |
1541 | intel_ring_emit(waiter, upper_32_bits(offset)); | |
5ee426ca | 1542 | intel_ring_advance(waiter); |
6ef48d7f CW |
1543 | |
1544 | /* When the !RCS engines idle waiting upon a semaphore, they lose their | |
1545 | * pagetables and we must reload them before executing the batch. | |
1546 | * We do this on the i915_switch_context() following the wait and | |
1547 | * before the dispatch. | |
1548 | */ | |
1549 | ppgtt = waiter_req->ctx->ppgtt; | |
1550 | if (ppgtt && waiter_req->engine->id != RCS) | |
1551 | ppgtt->pd_dirty_rings |= intel_engine_flag(waiter_req->engine); | |
5ee426ca BW |
1552 | return 0; |
1553 | } | |
1554 | ||
c8c99b0f | 1555 | static int |
599d924c | 1556 | gen6_ring_sync(struct drm_i915_gem_request *waiter_req, |
a4872ba6 | 1557 | struct intel_engine_cs *signaller, |
686cb5f9 | 1558 | u32 seqno) |
1ec14ad3 | 1559 | { |
7e37f889 | 1560 | struct intel_ring *waiter = waiter_req->ring; |
c8c99b0f BW |
1561 | u32 dw1 = MI_SEMAPHORE_MBOX | |
1562 | MI_SEMAPHORE_COMPARE | | |
1563 | MI_SEMAPHORE_REGISTER; | |
b5321f30 | 1564 | u32 wait_mbox = signaller->semaphore.mbox.wait[waiter_req->engine->id]; |
ebc348b2 | 1565 | int ret; |
1ec14ad3 | 1566 | |
1500f7ea BW |
1567 | /* Throughout all of the GEM code, seqno passed implies our current |
1568 | * seqno is >= the last seqno executed. However for hardware the | |
1569 | * comparison is strictly greater than. | |
1570 | */ | |
1571 | seqno -= 1; | |
1572 | ||
ebc348b2 | 1573 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
686cb5f9 | 1574 | |
5fb9de1a | 1575 | ret = intel_ring_begin(waiter_req, 4); |
1ec14ad3 CW |
1576 | if (ret) |
1577 | return ret; | |
1578 | ||
f72b3435 | 1579 | /* If seqno wrap happened, omit the wait with no-ops */ |
c033666a | 1580 | if (likely(!i915_gem_has_seqno_wrapped(waiter_req->i915, seqno))) { |
ebc348b2 | 1581 | intel_ring_emit(waiter, dw1 | wait_mbox); |
f72b3435 MK |
1582 | intel_ring_emit(waiter, seqno); |
1583 | intel_ring_emit(waiter, 0); | |
1584 | intel_ring_emit(waiter, MI_NOOP); | |
1585 | } else { | |
1586 | intel_ring_emit(waiter, MI_NOOP); | |
1587 | intel_ring_emit(waiter, MI_NOOP); | |
1588 | intel_ring_emit(waiter, MI_NOOP); | |
1589 | intel_ring_emit(waiter, MI_NOOP); | |
1590 | } | |
c8c99b0f | 1591 | intel_ring_advance(waiter); |
1ec14ad3 CW |
1592 | |
1593 | return 0; | |
1594 | } | |
1595 | ||
f8973c21 | 1596 | static void |
38a0f2db | 1597 | gen5_seqno_barrier(struct intel_engine_cs *engine) |
c6df541c | 1598 | { |
f8973c21 CW |
1599 | /* MI_STORE are internally buffered by the GPU and not flushed |
1600 | * either by MI_FLUSH or SyncFlush or any other combination of | |
1601 | * MI commands. | |
c6df541c | 1602 | * |
f8973c21 CW |
1603 | * "Only the submission of the store operation is guaranteed. |
1604 | * The write result will be complete (coherent) some time later | |
1605 | * (this is practically a finite period but there is no guaranteed | |
1606 | * latency)." | |
1607 | * | |
1608 | * Empirically, we observe that we need a delay of at least 75us to | |
1609 | * be sure that the seqno write is visible by the CPU. | |
c6df541c | 1610 | */ |
f8973c21 | 1611 | usleep_range(125, 250); |
c6df541c CW |
1612 | } |
1613 | ||
c04e0f3b CW |
1614 | static void |
1615 | gen6_seqno_barrier(struct intel_engine_cs *engine) | |
4cd53c0c | 1616 | { |
c033666a | 1617 | struct drm_i915_private *dev_priv = engine->i915; |
bcbdb6d0 | 1618 | |
4cd53c0c DV |
1619 | /* Workaround to force correct ordering between irq and seqno writes on |
1620 | * ivb (and maybe also on snb) by reading from a CS register (like | |
9b9ed309 CW |
1621 | * ACTHD) before reading the status page. |
1622 | * | |
1623 | * Note that this effectively stalls the read by the time it takes to | |
1624 | * do a memory transaction, which more or less ensures that the write | |
1625 | * from the GPU has sufficient time to invalidate the CPU cacheline. | |
1626 | * Alternatively we could delay the interrupt from the CS ring to give | |
1627 | * the write time to land, but that would incur a delay after every | |
1628 | * batch i.e. much more frequent than a delay when waiting for the | |
1629 | * interrupt (with the same net latency). | |
bcbdb6d0 CW |
1630 | * |
1631 | * Also note that to prevent whole machine hangs on gen7, we have to | |
1632 | * take the spinlock to guard against concurrent cacheline access. | |
9b9ed309 | 1633 | */ |
bcbdb6d0 | 1634 | spin_lock_irq(&dev_priv->uncore.lock); |
c04e0f3b | 1635 | POSTING_READ_FW(RING_ACTHD(engine->mmio_base)); |
bcbdb6d0 | 1636 | spin_unlock_irq(&dev_priv->uncore.lock); |
4cd53c0c DV |
1637 | } |
1638 | ||
31bb59cc CW |
1639 | static void |
1640 | gen5_irq_enable(struct intel_engine_cs *engine) | |
e48d8634 | 1641 | { |
31bb59cc | 1642 | gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
1643 | } |
1644 | ||
1645 | static void | |
31bb59cc | 1646 | gen5_irq_disable(struct intel_engine_cs *engine) |
e48d8634 | 1647 | { |
31bb59cc | 1648 | gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
1649 | } |
1650 | ||
31bb59cc CW |
1651 | static void |
1652 | i9xx_irq_enable(struct intel_engine_cs *engine) | |
62fdfeaf | 1653 | { |
c033666a | 1654 | struct drm_i915_private *dev_priv = engine->i915; |
b13c2b96 | 1655 | |
31bb59cc CW |
1656 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
1657 | I915_WRITE(IMR, dev_priv->irq_mask); | |
1658 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
62fdfeaf EA |
1659 | } |
1660 | ||
8187a2b7 | 1661 | static void |
31bb59cc | 1662 | i9xx_irq_disable(struct intel_engine_cs *engine) |
62fdfeaf | 1663 | { |
c033666a | 1664 | struct drm_i915_private *dev_priv = engine->i915; |
62fdfeaf | 1665 | |
31bb59cc CW |
1666 | dev_priv->irq_mask |= engine->irq_enable_mask; |
1667 | I915_WRITE(IMR, dev_priv->irq_mask); | |
62fdfeaf EA |
1668 | } |
1669 | ||
31bb59cc CW |
1670 | static void |
1671 | i8xx_irq_enable(struct intel_engine_cs *engine) | |
c2798b19 | 1672 | { |
c033666a | 1673 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 1674 | |
31bb59cc CW |
1675 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
1676 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
1677 | POSTING_READ16(RING_IMR(engine->mmio_base)); | |
c2798b19 CW |
1678 | } |
1679 | ||
1680 | static void | |
31bb59cc | 1681 | i8xx_irq_disable(struct intel_engine_cs *engine) |
c2798b19 | 1682 | { |
c033666a | 1683 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 1684 | |
31bb59cc CW |
1685 | dev_priv->irq_mask |= engine->irq_enable_mask; |
1686 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
c2798b19 CW |
1687 | } |
1688 | ||
b72f3acb | 1689 | static int |
7c9cf4e3 | 1690 | bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
d1b851fc | 1691 | { |
7e37f889 | 1692 | struct intel_ring *ring = req->ring; |
b72f3acb CW |
1693 | int ret; |
1694 | ||
5fb9de1a | 1695 | ret = intel_ring_begin(req, 2); |
b72f3acb CW |
1696 | if (ret) |
1697 | return ret; | |
1698 | ||
b5321f30 CW |
1699 | intel_ring_emit(ring, MI_FLUSH); |
1700 | intel_ring_emit(ring, MI_NOOP); | |
1701 | intel_ring_advance(ring); | |
b72f3acb | 1702 | return 0; |
d1b851fc ZN |
1703 | } |
1704 | ||
3cce469c | 1705 | static int |
ee044a88 | 1706 | i9xx_add_request(struct drm_i915_gem_request *req) |
d1b851fc | 1707 | { |
7e37f889 | 1708 | struct intel_ring *ring = req->ring; |
3cce469c CW |
1709 | int ret; |
1710 | ||
5fb9de1a | 1711 | ret = intel_ring_begin(req, 4); |
3cce469c CW |
1712 | if (ret) |
1713 | return ret; | |
6f392d54 | 1714 | |
b5321f30 CW |
1715 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
1716 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1717 | intel_ring_emit(ring, req->fence.seqno); | |
1718 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
1719 | __intel_engine_submit(req->engine); | |
d1b851fc | 1720 | |
3cce469c | 1721 | return 0; |
d1b851fc ZN |
1722 | } |
1723 | ||
31bb59cc CW |
1724 | static void |
1725 | gen6_irq_enable(struct intel_engine_cs *engine) | |
0f46832f | 1726 | { |
c033666a | 1727 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 1728 | |
61ff75ac CW |
1729 | I915_WRITE_IMR(engine, |
1730 | ~(engine->irq_enable_mask | | |
1731 | engine->irq_keep_mask)); | |
31bb59cc | 1732 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); |
0f46832f CW |
1733 | } |
1734 | ||
1735 | static void | |
31bb59cc | 1736 | gen6_irq_disable(struct intel_engine_cs *engine) |
0f46832f | 1737 | { |
c033666a | 1738 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 1739 | |
61ff75ac | 1740 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
31bb59cc | 1741 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); |
d1b851fc ZN |
1742 | } |
1743 | ||
31bb59cc CW |
1744 | static void |
1745 | hsw_vebox_irq_enable(struct intel_engine_cs *engine) | |
a19d2933 | 1746 | { |
c033666a | 1747 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 1748 | |
31bb59cc CW |
1749 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
1750 | gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask); | |
a19d2933 BW |
1751 | } |
1752 | ||
1753 | static void | |
31bb59cc | 1754 | hsw_vebox_irq_disable(struct intel_engine_cs *engine) |
a19d2933 | 1755 | { |
c033666a | 1756 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 1757 | |
31bb59cc CW |
1758 | I915_WRITE_IMR(engine, ~0); |
1759 | gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask); | |
a19d2933 BW |
1760 | } |
1761 | ||
31bb59cc CW |
1762 | static void |
1763 | gen8_irq_enable(struct intel_engine_cs *engine) | |
abd58f01 | 1764 | { |
c033666a | 1765 | struct drm_i915_private *dev_priv = engine->i915; |
abd58f01 | 1766 | |
61ff75ac CW |
1767 | I915_WRITE_IMR(engine, |
1768 | ~(engine->irq_enable_mask | | |
1769 | engine->irq_keep_mask)); | |
31bb59cc | 1770 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); |
abd58f01 BW |
1771 | } |
1772 | ||
1773 | static void | |
31bb59cc | 1774 | gen8_irq_disable(struct intel_engine_cs *engine) |
abd58f01 | 1775 | { |
c033666a | 1776 | struct drm_i915_private *dev_priv = engine->i915; |
abd58f01 | 1777 | |
61ff75ac | 1778 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
abd58f01 BW |
1779 | } |
1780 | ||
d1b851fc | 1781 | static int |
53fddaf7 | 1782 | i965_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 1783 | u64 offset, u32 length, |
8e004efc | 1784 | unsigned dispatch_flags) |
d1b851fc | 1785 | { |
7e37f889 | 1786 | struct intel_ring *ring = req->ring; |
e1f99ce6 | 1787 | int ret; |
78501eac | 1788 | |
5fb9de1a | 1789 | ret = intel_ring_begin(req, 2); |
e1f99ce6 CW |
1790 | if (ret) |
1791 | return ret; | |
1792 | ||
b5321f30 | 1793 | intel_ring_emit(ring, |
65f56876 CW |
1794 | MI_BATCH_BUFFER_START | |
1795 | MI_BATCH_GTT | | |
8e004efc JH |
1796 | (dispatch_flags & I915_DISPATCH_SECURE ? |
1797 | 0 : MI_BATCH_NON_SECURE_I965)); | |
b5321f30 CW |
1798 | intel_ring_emit(ring, offset); |
1799 | intel_ring_advance(ring); | |
78501eac | 1800 | |
d1b851fc ZN |
1801 | return 0; |
1802 | } | |
1803 | ||
b45305fc DV |
1804 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1805 | #define I830_BATCH_LIMIT (256*1024) | |
c4d69da1 CW |
1806 | #define I830_TLB_ENTRIES (2) |
1807 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) | |
8187a2b7 | 1808 | static int |
53fddaf7 | 1809 | i830_dispatch_execbuffer(struct drm_i915_gem_request *req, |
8e004efc JH |
1810 | u64 offset, u32 len, |
1811 | unsigned dispatch_flags) | |
62fdfeaf | 1812 | { |
7e37f889 | 1813 | struct intel_ring *ring = req->ring; |
b5321f30 | 1814 | u32 cs_offset = req->engine->scratch.gtt_offset; |
c4e7a414 | 1815 | int ret; |
62fdfeaf | 1816 | |
5fb9de1a | 1817 | ret = intel_ring_begin(req, 6); |
c4d69da1 CW |
1818 | if (ret) |
1819 | return ret; | |
62fdfeaf | 1820 | |
c4d69da1 | 1821 | /* Evict the invalid PTE TLBs */ |
b5321f30 CW |
1822 | intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA); |
1823 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096); | |
1824 | intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */ | |
1825 | intel_ring_emit(ring, cs_offset); | |
1826 | intel_ring_emit(ring, 0xdeadbeef); | |
1827 | intel_ring_emit(ring, MI_NOOP); | |
1828 | intel_ring_advance(ring); | |
b45305fc | 1829 | |
8e004efc | 1830 | if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { |
b45305fc DV |
1831 | if (len > I830_BATCH_LIMIT) |
1832 | return -ENOSPC; | |
1833 | ||
5fb9de1a | 1834 | ret = intel_ring_begin(req, 6 + 2); |
b45305fc DV |
1835 | if (ret) |
1836 | return ret; | |
c4d69da1 CW |
1837 | |
1838 | /* Blit the batch (which has now all relocs applied) to the | |
1839 | * stable batch scratch bo area (so that the CS never | |
1840 | * stumbles over its tlb invalidation bug) ... | |
1841 | */ | |
b5321f30 CW |
1842 | intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA); |
1843 | intel_ring_emit(ring, | |
e2f80391 | 1844 | BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096); |
b5321f30 CW |
1845 | intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096); |
1846 | intel_ring_emit(ring, cs_offset); | |
1847 | intel_ring_emit(ring, 4096); | |
1848 | intel_ring_emit(ring, offset); | |
e2f80391 | 1849 | |
b5321f30 CW |
1850 | intel_ring_emit(ring, MI_FLUSH); |
1851 | intel_ring_emit(ring, MI_NOOP); | |
1852 | intel_ring_advance(ring); | |
b45305fc DV |
1853 | |
1854 | /* ... and execute it. */ | |
c4d69da1 | 1855 | offset = cs_offset; |
b45305fc | 1856 | } |
e1f99ce6 | 1857 | |
9d611c03 | 1858 | ret = intel_ring_begin(req, 2); |
c4d69da1 CW |
1859 | if (ret) |
1860 | return ret; | |
1861 | ||
b5321f30 CW |
1862 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
1863 | intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ? | |
1864 | 0 : MI_BATCH_NON_SECURE)); | |
1865 | intel_ring_advance(ring); | |
c4d69da1 | 1866 | |
fb3256da DV |
1867 | return 0; |
1868 | } | |
1869 | ||
1870 | static int | |
53fddaf7 | 1871 | i915_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 1872 | u64 offset, u32 len, |
8e004efc | 1873 | unsigned dispatch_flags) |
fb3256da | 1874 | { |
7e37f889 | 1875 | struct intel_ring *ring = req->ring; |
fb3256da DV |
1876 | int ret; |
1877 | ||
5fb9de1a | 1878 | ret = intel_ring_begin(req, 2); |
fb3256da DV |
1879 | if (ret) |
1880 | return ret; | |
1881 | ||
b5321f30 CW |
1882 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
1883 | intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ? | |
1884 | 0 : MI_BATCH_NON_SECURE)); | |
1885 | intel_ring_advance(ring); | |
62fdfeaf | 1886 | |
62fdfeaf EA |
1887 | return 0; |
1888 | } | |
1889 | ||
0bc40be8 | 1890 | static void cleanup_phys_status_page(struct intel_engine_cs *engine) |
7d3fdfff | 1891 | { |
c033666a | 1892 | struct drm_i915_private *dev_priv = engine->i915; |
7d3fdfff VS |
1893 | |
1894 | if (!dev_priv->status_page_dmah) | |
1895 | return; | |
1896 | ||
91c8a326 | 1897 | drm_pci_free(&dev_priv->drm, dev_priv->status_page_dmah); |
0bc40be8 | 1898 | engine->status_page.page_addr = NULL; |
7d3fdfff VS |
1899 | } |
1900 | ||
0bc40be8 | 1901 | static void cleanup_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 1902 | { |
05394f39 | 1903 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1904 | |
0bc40be8 | 1905 | obj = engine->status_page.obj; |
8187a2b7 | 1906 | if (obj == NULL) |
62fdfeaf | 1907 | return; |
62fdfeaf | 1908 | |
9da3da66 | 1909 | kunmap(sg_page(obj->pages->sgl)); |
d7f46fc4 | 1910 | i915_gem_object_ggtt_unpin(obj); |
f8c417cd | 1911 | i915_gem_object_put(obj); |
0bc40be8 | 1912 | engine->status_page.obj = NULL; |
62fdfeaf EA |
1913 | } |
1914 | ||
0bc40be8 | 1915 | static int init_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 1916 | { |
0bc40be8 | 1917 | struct drm_i915_gem_object *obj = engine->status_page.obj; |
62fdfeaf | 1918 | |
7d3fdfff | 1919 | if (obj == NULL) { |
1f767e02 | 1920 | unsigned flags; |
e3efda49 | 1921 | int ret; |
e4ffd173 | 1922 | |
91c8a326 | 1923 | obj = i915_gem_object_create(&engine->i915->drm, 4096); |
fe3db79b | 1924 | if (IS_ERR(obj)) { |
e3efda49 | 1925 | DRM_ERROR("Failed to allocate status page\n"); |
fe3db79b | 1926 | return PTR_ERR(obj); |
e3efda49 | 1927 | } |
62fdfeaf | 1928 | |
e3efda49 CW |
1929 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
1930 | if (ret) | |
1931 | goto err_unref; | |
1932 | ||
1f767e02 | 1933 | flags = 0; |
c033666a | 1934 | if (!HAS_LLC(engine->i915)) |
1f767e02 CW |
1935 | /* On g33, we cannot place HWS above 256MiB, so |
1936 | * restrict its pinning to the low mappable arena. | |
1937 | * Though this restriction is not documented for | |
1938 | * gen4, gen5, or byt, they also behave similarly | |
1939 | * and hang if the HWS is placed at the top of the | |
1940 | * GTT. To generalise, it appears that all !llc | |
1941 | * platforms have issues with us placing the HWS | |
1942 | * above the mappable region (even though we never | |
1943 | * actualy map it). | |
1944 | */ | |
1945 | flags |= PIN_MAPPABLE; | |
1946 | ret = i915_gem_obj_ggtt_pin(obj, 4096, flags); | |
e3efda49 CW |
1947 | if (ret) { |
1948 | err_unref: | |
f8c417cd | 1949 | i915_gem_object_put(obj); |
e3efda49 CW |
1950 | return ret; |
1951 | } | |
1952 | ||
0bc40be8 | 1953 | engine->status_page.obj = obj; |
e3efda49 | 1954 | } |
62fdfeaf | 1955 | |
0bc40be8 TU |
1956 | engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
1957 | engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); | |
1958 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); | |
62fdfeaf | 1959 | |
8187a2b7 | 1960 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
0bc40be8 | 1961 | engine->name, engine->status_page.gfx_addr); |
62fdfeaf EA |
1962 | |
1963 | return 0; | |
62fdfeaf EA |
1964 | } |
1965 | ||
0bc40be8 | 1966 | static int init_phys_status_page(struct intel_engine_cs *engine) |
6b8294a4 | 1967 | { |
c033666a | 1968 | struct drm_i915_private *dev_priv = engine->i915; |
6b8294a4 CW |
1969 | |
1970 | if (!dev_priv->status_page_dmah) { | |
1971 | dev_priv->status_page_dmah = | |
91c8a326 | 1972 | drm_pci_alloc(&dev_priv->drm, PAGE_SIZE, PAGE_SIZE); |
6b8294a4 CW |
1973 | if (!dev_priv->status_page_dmah) |
1974 | return -ENOMEM; | |
1975 | } | |
1976 | ||
0bc40be8 TU |
1977 | engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1978 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); | |
6b8294a4 CW |
1979 | |
1980 | return 0; | |
1981 | } | |
1982 | ||
aad29fbb | 1983 | int intel_ring_pin(struct intel_ring *ring) |
7ba717cf | 1984 | { |
aad29fbb | 1985 | struct drm_i915_private *dev_priv = ring->engine->i915; |
32c04f16 | 1986 | struct drm_i915_gem_object *obj = ring->obj; |
a687a43a CW |
1987 | /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ |
1988 | unsigned flags = PIN_OFFSET_BIAS | 4096; | |
8305216f | 1989 | void *addr; |
7ba717cf TD |
1990 | int ret; |
1991 | ||
def0c5f6 | 1992 | if (HAS_LLC(dev_priv) && !obj->stolen) { |
a687a43a | 1993 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags); |
def0c5f6 CW |
1994 | if (ret) |
1995 | return ret; | |
7ba717cf | 1996 | |
def0c5f6 | 1997 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
d2cad535 CW |
1998 | if (ret) |
1999 | goto err_unpin; | |
def0c5f6 | 2000 | |
8305216f DG |
2001 | addr = i915_gem_object_pin_map(obj); |
2002 | if (IS_ERR(addr)) { | |
2003 | ret = PTR_ERR(addr); | |
d2cad535 | 2004 | goto err_unpin; |
def0c5f6 CW |
2005 | } |
2006 | } else { | |
a687a43a CW |
2007 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, |
2008 | flags | PIN_MAPPABLE); | |
def0c5f6 CW |
2009 | if (ret) |
2010 | return ret; | |
7ba717cf | 2011 | |
def0c5f6 | 2012 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
d2cad535 CW |
2013 | if (ret) |
2014 | goto err_unpin; | |
def0c5f6 | 2015 | |
ff3dc087 DCS |
2016 | /* Access through the GTT requires the device to be awake. */ |
2017 | assert_rpm_wakelock_held(dev_priv); | |
2018 | ||
406ea8d2 CW |
2019 | addr = (void __force *) |
2020 | i915_vma_pin_iomap(i915_gem_obj_to_ggtt(obj)); | |
3d77e9be CW |
2021 | if (IS_ERR(addr)) { |
2022 | ret = PTR_ERR(addr); | |
d2cad535 | 2023 | goto err_unpin; |
def0c5f6 | 2024 | } |
7ba717cf TD |
2025 | } |
2026 | ||
32c04f16 CW |
2027 | ring->vaddr = addr; |
2028 | ring->vma = i915_gem_obj_to_ggtt(obj); | |
7ba717cf | 2029 | return 0; |
d2cad535 CW |
2030 | |
2031 | err_unpin: | |
2032 | i915_gem_object_ggtt_unpin(obj); | |
2033 | return ret; | |
7ba717cf TD |
2034 | } |
2035 | ||
aad29fbb CW |
2036 | void intel_ring_unpin(struct intel_ring *ring) |
2037 | { | |
2038 | GEM_BUG_ON(!ring->vma); | |
2039 | GEM_BUG_ON(!ring->vaddr); | |
2040 | ||
2041 | if (HAS_LLC(ring->engine->i915) && !ring->obj->stolen) | |
2042 | i915_gem_object_unpin_map(ring->obj); | |
2043 | else | |
2044 | i915_vma_unpin_iomap(ring->vma); | |
2045 | ring->vaddr = NULL; | |
2046 | ||
2047 | i915_gem_object_ggtt_unpin(ring->obj); | |
2048 | ring->vma = NULL; | |
2049 | } | |
2050 | ||
32c04f16 | 2051 | static void intel_destroy_ringbuffer_obj(struct intel_ring *ring) |
7ba717cf | 2052 | { |
32c04f16 CW |
2053 | i915_gem_object_put(ring->obj); |
2054 | ring->obj = NULL; | |
2919d291 OM |
2055 | } |
2056 | ||
01101fa7 | 2057 | static int intel_alloc_ringbuffer_obj(struct drm_device *dev, |
32c04f16 | 2058 | struct intel_ring *ring) |
62fdfeaf | 2059 | { |
05394f39 | 2060 | struct drm_i915_gem_object *obj; |
62fdfeaf | 2061 | |
ebc052e0 CW |
2062 | obj = NULL; |
2063 | if (!HAS_LLC(dev)) | |
32c04f16 | 2064 | obj = i915_gem_object_create_stolen(dev, ring->size); |
ebc052e0 | 2065 | if (obj == NULL) |
32c04f16 | 2066 | obj = i915_gem_object_create(dev, ring->size); |
fe3db79b CW |
2067 | if (IS_ERR(obj)) |
2068 | return PTR_ERR(obj); | |
8187a2b7 | 2069 | |
24f3a8cf AG |
2070 | /* mark ring buffers as read-only from GPU side by default */ |
2071 | obj->gt_ro = 1; | |
2072 | ||
32c04f16 | 2073 | ring->obj = obj; |
e3efda49 | 2074 | |
7ba717cf | 2075 | return 0; |
e3efda49 CW |
2076 | } |
2077 | ||
7e37f889 CW |
2078 | struct intel_ring * |
2079 | intel_engine_create_ring(struct intel_engine_cs *engine, int size) | |
01101fa7 | 2080 | { |
7e37f889 | 2081 | struct intel_ring *ring; |
01101fa7 CW |
2082 | int ret; |
2083 | ||
2084 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); | |
608c1a52 CW |
2085 | if (ring == NULL) { |
2086 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n", | |
2087 | engine->name); | |
01101fa7 | 2088 | return ERR_PTR(-ENOMEM); |
608c1a52 | 2089 | } |
01101fa7 | 2090 | |
4a570db5 | 2091 | ring->engine = engine; |
608c1a52 | 2092 | list_add(&ring->link, &engine->buffers); |
01101fa7 CW |
2093 | |
2094 | ring->size = size; | |
2095 | /* Workaround an erratum on the i830 which causes a hang if | |
2096 | * the TAIL pointer points to within the last 2 cachelines | |
2097 | * of the buffer. | |
2098 | */ | |
2099 | ring->effective_size = size; | |
c033666a | 2100 | if (IS_I830(engine->i915) || IS_845G(engine->i915)) |
01101fa7 CW |
2101 | ring->effective_size -= 2 * CACHELINE_BYTES; |
2102 | ||
2103 | ring->last_retired_head = -1; | |
2104 | intel_ring_update_space(ring); | |
2105 | ||
91c8a326 | 2106 | ret = intel_alloc_ringbuffer_obj(&engine->i915->drm, ring); |
01101fa7 | 2107 | if (ret) { |
608c1a52 CW |
2108 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n", |
2109 | engine->name, ret); | |
2110 | list_del(&ring->link); | |
01101fa7 CW |
2111 | kfree(ring); |
2112 | return ERR_PTR(ret); | |
2113 | } | |
2114 | ||
2115 | return ring; | |
2116 | } | |
2117 | ||
2118 | void | |
7e37f889 | 2119 | intel_ring_free(struct intel_ring *ring) |
01101fa7 CW |
2120 | { |
2121 | intel_destroy_ringbuffer_obj(ring); | |
608c1a52 | 2122 | list_del(&ring->link); |
01101fa7 CW |
2123 | kfree(ring); |
2124 | } | |
2125 | ||
0cb26a8e CW |
2126 | static int intel_ring_context_pin(struct i915_gem_context *ctx, |
2127 | struct intel_engine_cs *engine) | |
2128 | { | |
2129 | struct intel_context *ce = &ctx->engine[engine->id]; | |
2130 | int ret; | |
2131 | ||
91c8a326 | 2132 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
0cb26a8e CW |
2133 | |
2134 | if (ce->pin_count++) | |
2135 | return 0; | |
2136 | ||
2137 | if (ce->state) { | |
2138 | ret = i915_gem_obj_ggtt_pin(ce->state, ctx->ggtt_alignment, 0); | |
2139 | if (ret) | |
2140 | goto error; | |
2141 | } | |
2142 | ||
c7c3c07d CW |
2143 | /* The kernel context is only used as a placeholder for flushing the |
2144 | * active context. It is never used for submitting user rendering and | |
2145 | * as such never requires the golden render context, and so we can skip | |
2146 | * emitting it when we switch to the kernel context. This is required | |
2147 | * as during eviction we cannot allocate and pin the renderstate in | |
2148 | * order to initialise the context. | |
2149 | */ | |
2150 | if (ctx == ctx->i915->kernel_context) | |
2151 | ce->initialised = true; | |
2152 | ||
9a6feaf0 | 2153 | i915_gem_context_get(ctx); |
0cb26a8e CW |
2154 | return 0; |
2155 | ||
2156 | error: | |
2157 | ce->pin_count = 0; | |
2158 | return ret; | |
2159 | } | |
2160 | ||
2161 | static void intel_ring_context_unpin(struct i915_gem_context *ctx, | |
2162 | struct intel_engine_cs *engine) | |
2163 | { | |
2164 | struct intel_context *ce = &ctx->engine[engine->id]; | |
2165 | ||
91c8a326 | 2166 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
0cb26a8e CW |
2167 | |
2168 | if (--ce->pin_count) | |
2169 | return; | |
2170 | ||
2171 | if (ce->state) | |
2172 | i915_gem_object_ggtt_unpin(ce->state); | |
2173 | ||
9a6feaf0 | 2174 | i915_gem_context_put(ctx); |
0cb26a8e CW |
2175 | } |
2176 | ||
acd27845 | 2177 | static int intel_init_ring_buffer(struct intel_engine_cs *engine) |
e3efda49 | 2178 | { |
acd27845 | 2179 | struct drm_i915_private *dev_priv = engine->i915; |
32c04f16 | 2180 | struct intel_ring *ring; |
e3efda49 CW |
2181 | int ret; |
2182 | ||
0bc40be8 | 2183 | WARN_ON(engine->buffer); |
bfc882b4 | 2184 | |
019bf277 TU |
2185 | intel_engine_setup_common(engine); |
2186 | ||
0bc40be8 TU |
2187 | memset(engine->semaphore.sync_seqno, 0, |
2188 | sizeof(engine->semaphore.sync_seqno)); | |
e3efda49 | 2189 | |
019bf277 | 2190 | ret = intel_engine_init_common(engine); |
688e6c72 CW |
2191 | if (ret) |
2192 | goto error; | |
e3efda49 | 2193 | |
0cb26a8e CW |
2194 | /* We may need to do things with the shrinker which |
2195 | * require us to immediately switch back to the default | |
2196 | * context. This can cause a problem as pinning the | |
2197 | * default context also requires GTT space which may not | |
2198 | * be available. To avoid this we always pin the default | |
2199 | * context. | |
2200 | */ | |
2201 | ret = intel_ring_context_pin(dev_priv->kernel_context, engine); | |
2202 | if (ret) | |
2203 | goto error; | |
2204 | ||
32c04f16 CW |
2205 | ring = intel_engine_create_ring(engine, 32 * PAGE_SIZE); |
2206 | if (IS_ERR(ring)) { | |
2207 | ret = PTR_ERR(ring); | |
b0366a54 DG |
2208 | goto error; |
2209 | } | |
32c04f16 | 2210 | engine->buffer = ring; |
01101fa7 | 2211 | |
c033666a | 2212 | if (I915_NEED_GFX_HWS(dev_priv)) { |
0bc40be8 | 2213 | ret = init_status_page(engine); |
e3efda49 | 2214 | if (ret) |
8ee14975 | 2215 | goto error; |
e3efda49 | 2216 | } else { |
0bc40be8 TU |
2217 | WARN_ON(engine->id != RCS); |
2218 | ret = init_phys_status_page(engine); | |
e3efda49 | 2219 | if (ret) |
8ee14975 | 2220 | goto error; |
e3efda49 CW |
2221 | } |
2222 | ||
aad29fbb | 2223 | ret = intel_ring_pin(ring); |
bfc882b4 DV |
2224 | if (ret) { |
2225 | DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n", | |
0bc40be8 | 2226 | engine->name, ret); |
32c04f16 | 2227 | intel_destroy_ringbuffer_obj(ring); |
bfc882b4 | 2228 | goto error; |
e3efda49 | 2229 | } |
62fdfeaf | 2230 | |
8ee14975 | 2231 | return 0; |
351e3db2 | 2232 | |
8ee14975 | 2233 | error: |
7e37f889 | 2234 | intel_engine_cleanup(engine); |
8ee14975 | 2235 | return ret; |
62fdfeaf EA |
2236 | } |
2237 | ||
7e37f889 | 2238 | void intel_engine_cleanup(struct intel_engine_cs *engine) |
62fdfeaf | 2239 | { |
6402c330 | 2240 | struct drm_i915_private *dev_priv; |
33626e6a | 2241 | |
117897f4 | 2242 | if (!intel_engine_initialized(engine)) |
62fdfeaf EA |
2243 | return; |
2244 | ||
c033666a | 2245 | dev_priv = engine->i915; |
6402c330 | 2246 | |
0bc40be8 | 2247 | if (engine->buffer) { |
7e37f889 | 2248 | intel_engine_stop(engine); |
c033666a | 2249 | WARN_ON(!IS_GEN2(dev_priv) && (I915_READ_MODE(engine) & MODE_IDLE) == 0); |
33626e6a | 2250 | |
aad29fbb | 2251 | intel_ring_unpin(engine->buffer); |
7e37f889 | 2252 | intel_ring_free(engine->buffer); |
0bc40be8 | 2253 | engine->buffer = NULL; |
b0366a54 | 2254 | } |
78501eac | 2255 | |
0bc40be8 TU |
2256 | if (engine->cleanup) |
2257 | engine->cleanup(engine); | |
8d19215b | 2258 | |
c033666a | 2259 | if (I915_NEED_GFX_HWS(dev_priv)) { |
0bc40be8 | 2260 | cleanup_status_page(engine); |
7d3fdfff | 2261 | } else { |
0bc40be8 TU |
2262 | WARN_ON(engine->id != RCS); |
2263 | cleanup_phys_status_page(engine); | |
7d3fdfff | 2264 | } |
44e895a8 | 2265 | |
33a051a5 | 2266 | intel_engine_cleanup_cmd_parser(engine); |
0bc40be8 | 2267 | i915_gem_batch_pool_fini(&engine->batch_pool); |
688e6c72 | 2268 | intel_engine_fini_breadcrumbs(engine); |
0cb26a8e CW |
2269 | |
2270 | intel_ring_context_unpin(dev_priv->kernel_context, engine); | |
2271 | ||
c033666a | 2272 | engine->i915 = NULL; |
62fdfeaf EA |
2273 | } |
2274 | ||
666796da | 2275 | int intel_engine_idle(struct intel_engine_cs *engine) |
3e960501 | 2276 | { |
a4b3a571 | 2277 | struct drm_i915_gem_request *req; |
3e960501 | 2278 | |
3e960501 | 2279 | /* Wait upon the last request to be completed */ |
0bc40be8 | 2280 | if (list_empty(&engine->request_list)) |
3e960501 CW |
2281 | return 0; |
2282 | ||
0bc40be8 TU |
2283 | req = list_entry(engine->request_list.prev, |
2284 | struct drm_i915_gem_request, | |
2285 | list); | |
b4716185 CW |
2286 | |
2287 | /* Make sure we do not trigger any retires */ | |
2288 | return __i915_wait_request(req, | |
c19ae989 | 2289 | req->i915->mm.interruptible, |
b4716185 | 2290 | NULL, NULL); |
3e960501 CW |
2291 | } |
2292 | ||
6689cb2b | 2293 | int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request) |
9d773091 | 2294 | { |
6310346e CW |
2295 | int ret; |
2296 | ||
2297 | /* Flush enough space to reduce the likelihood of waiting after | |
2298 | * we start building the request - in which case we will just | |
2299 | * have to repeat work. | |
2300 | */ | |
a0442461 | 2301 | request->reserved_space += LEGACY_REQUEST_SIZE; |
6310346e | 2302 | |
1dae2dfb | 2303 | request->ring = request->engine->buffer; |
6310346e CW |
2304 | |
2305 | ret = intel_ring_begin(request, 0); | |
2306 | if (ret) | |
2307 | return ret; | |
2308 | ||
a0442461 | 2309 | request->reserved_space -= LEGACY_REQUEST_SIZE; |
6310346e | 2310 | return 0; |
9d773091 CW |
2311 | } |
2312 | ||
987046ad CW |
2313 | static int wait_for_space(struct drm_i915_gem_request *req, int bytes) |
2314 | { | |
7e37f889 | 2315 | struct intel_ring *ring = req->ring; |
987046ad CW |
2316 | struct intel_engine_cs *engine = req->engine; |
2317 | struct drm_i915_gem_request *target; | |
2318 | ||
1dae2dfb CW |
2319 | intel_ring_update_space(ring); |
2320 | if (ring->space >= bytes) | |
987046ad CW |
2321 | return 0; |
2322 | ||
2323 | /* | |
2324 | * Space is reserved in the ringbuffer for finalising the request, | |
2325 | * as that cannot be allowed to fail. During request finalisation, | |
2326 | * reserved_space is set to 0 to stop the overallocation and the | |
2327 | * assumption is that then we never need to wait (which has the | |
2328 | * risk of failing with EINTR). | |
2329 | * | |
2330 | * See also i915_gem_request_alloc() and i915_add_request(). | |
2331 | */ | |
0251a963 | 2332 | GEM_BUG_ON(!req->reserved_space); |
987046ad CW |
2333 | |
2334 | list_for_each_entry(target, &engine->request_list, list) { | |
2335 | unsigned space; | |
2336 | ||
79bbcc29 | 2337 | /* |
987046ad CW |
2338 | * The request queue is per-engine, so can contain requests |
2339 | * from multiple ringbuffers. Here, we must ignore any that | |
2340 | * aren't from the ringbuffer we're considering. | |
79bbcc29 | 2341 | */ |
1dae2dfb | 2342 | if (target->ring != ring) |
987046ad CW |
2343 | continue; |
2344 | ||
2345 | /* Would completion of this request free enough space? */ | |
1dae2dfb CW |
2346 | space = __intel_ring_space(target->postfix, ring->tail, |
2347 | ring->size); | |
987046ad CW |
2348 | if (space >= bytes) |
2349 | break; | |
79bbcc29 | 2350 | } |
29b1b415 | 2351 | |
987046ad CW |
2352 | if (WARN_ON(&target->list == &engine->request_list)) |
2353 | return -ENOSPC; | |
2354 | ||
2355 | return i915_wait_request(target); | |
29b1b415 JH |
2356 | } |
2357 | ||
987046ad | 2358 | int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords) |
cbcc80df | 2359 | { |
7e37f889 | 2360 | struct intel_ring *ring = req->ring; |
1dae2dfb CW |
2361 | int remain_actual = ring->size - ring->tail; |
2362 | int remain_usable = ring->effective_size - ring->tail; | |
987046ad CW |
2363 | int bytes = num_dwords * sizeof(u32); |
2364 | int total_bytes, wait_bytes; | |
79bbcc29 | 2365 | bool need_wrap = false; |
29b1b415 | 2366 | |
0251a963 | 2367 | total_bytes = bytes + req->reserved_space; |
29b1b415 | 2368 | |
79bbcc29 JH |
2369 | if (unlikely(bytes > remain_usable)) { |
2370 | /* | |
2371 | * Not enough space for the basic request. So need to flush | |
2372 | * out the remainder and then wait for base + reserved. | |
2373 | */ | |
2374 | wait_bytes = remain_actual + total_bytes; | |
2375 | need_wrap = true; | |
987046ad CW |
2376 | } else if (unlikely(total_bytes > remain_usable)) { |
2377 | /* | |
2378 | * The base request will fit but the reserved space | |
2379 | * falls off the end. So we don't need an immediate wrap | |
2380 | * and only need to effectively wait for the reserved | |
2381 | * size space from the start of ringbuffer. | |
2382 | */ | |
0251a963 | 2383 | wait_bytes = remain_actual + req->reserved_space; |
79bbcc29 | 2384 | } else { |
987046ad CW |
2385 | /* No wrapping required, just waiting. */ |
2386 | wait_bytes = total_bytes; | |
cbcc80df MK |
2387 | } |
2388 | ||
1dae2dfb | 2389 | if (wait_bytes > ring->space) { |
987046ad | 2390 | int ret = wait_for_space(req, wait_bytes); |
cbcc80df MK |
2391 | if (unlikely(ret)) |
2392 | return ret; | |
79bbcc29 | 2393 | |
1dae2dfb CW |
2394 | intel_ring_update_space(ring); |
2395 | if (unlikely(ring->space < wait_bytes)) | |
e075a32f | 2396 | return -EAGAIN; |
cbcc80df MK |
2397 | } |
2398 | ||
987046ad | 2399 | if (unlikely(need_wrap)) { |
1dae2dfb CW |
2400 | GEM_BUG_ON(remain_actual > ring->space); |
2401 | GEM_BUG_ON(ring->tail + remain_actual > ring->size); | |
78501eac | 2402 | |
987046ad | 2403 | /* Fill the tail with MI_NOOP */ |
1dae2dfb CW |
2404 | memset(ring->vaddr + ring->tail, 0, remain_actual); |
2405 | ring->tail = 0; | |
2406 | ring->space -= remain_actual; | |
987046ad | 2407 | } |
304d695c | 2408 | |
1dae2dfb CW |
2409 | ring->space -= bytes; |
2410 | GEM_BUG_ON(ring->space < 0); | |
304d695c | 2411 | return 0; |
8187a2b7 | 2412 | } |
78501eac | 2413 | |
753b1ad4 | 2414 | /* Align the ring tail to a cacheline boundary */ |
bba09b12 | 2415 | int intel_ring_cacheline_align(struct drm_i915_gem_request *req) |
753b1ad4 | 2416 | { |
7e37f889 | 2417 | struct intel_ring *ring = req->ring; |
b5321f30 CW |
2418 | int num_dwords = |
2419 | (ring->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); | |
753b1ad4 VS |
2420 | int ret; |
2421 | ||
2422 | if (num_dwords == 0) | |
2423 | return 0; | |
2424 | ||
18393f63 | 2425 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
5fb9de1a | 2426 | ret = intel_ring_begin(req, num_dwords); |
753b1ad4 VS |
2427 | if (ret) |
2428 | return ret; | |
2429 | ||
2430 | while (num_dwords--) | |
b5321f30 | 2431 | intel_ring_emit(ring, MI_NOOP); |
753b1ad4 | 2432 | |
b5321f30 | 2433 | intel_ring_advance(ring); |
753b1ad4 VS |
2434 | |
2435 | return 0; | |
2436 | } | |
2437 | ||
7e37f889 | 2438 | void intel_engine_init_seqno(struct intel_engine_cs *engine, u32 seqno) |
498d2ac1 | 2439 | { |
c033666a | 2440 | struct drm_i915_private *dev_priv = engine->i915; |
498d2ac1 | 2441 | |
29dcb570 CW |
2442 | /* Our semaphore implementation is strictly monotonic (i.e. we proceed |
2443 | * so long as the semaphore value in the register/page is greater | |
2444 | * than the sync value), so whenever we reset the seqno, | |
2445 | * so long as we reset the tracking semaphore value to 0, it will | |
2446 | * always be before the next request's seqno. If we don't reset | |
2447 | * the semaphore value, then when the seqno moves backwards all | |
2448 | * future waits will complete instantly (causing rendering corruption). | |
2449 | */ | |
7e22dbbb | 2450 | if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { |
0bc40be8 TU |
2451 | I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); |
2452 | I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); | |
d04bce48 | 2453 | if (HAS_VEBOX(dev_priv)) |
0bc40be8 | 2454 | I915_WRITE(RING_SYNC_2(engine->mmio_base), 0); |
e1f99ce6 | 2455 | } |
a058d934 CW |
2456 | if (dev_priv->semaphore_obj) { |
2457 | struct drm_i915_gem_object *obj = dev_priv->semaphore_obj; | |
2458 | struct page *page = i915_gem_object_get_dirty_page(obj, 0); | |
2459 | void *semaphores = kmap(page); | |
2460 | memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0), | |
2461 | 0, I915_NUM_ENGINES * gen8_semaphore_seqno_size); | |
2462 | kunmap(page); | |
2463 | } | |
29dcb570 CW |
2464 | memset(engine->semaphore.sync_seqno, 0, |
2465 | sizeof(engine->semaphore.sync_seqno)); | |
d97ed339 | 2466 | |
1b7744e7 CW |
2467 | intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno); |
2468 | if (engine->irq_seqno_barrier) | |
2469 | engine->irq_seqno_barrier(engine); | |
01347126 | 2470 | engine->last_submitted_seqno = seqno; |
29dcb570 | 2471 | |
0bc40be8 | 2472 | engine->hangcheck.seqno = seqno; |
688e6c72 CW |
2473 | |
2474 | /* After manually advancing the seqno, fake the interrupt in case | |
2475 | * there are any waiters for that seqno. | |
2476 | */ | |
2477 | rcu_read_lock(); | |
2478 | intel_engine_wakeup(engine); | |
2479 | rcu_read_unlock(); | |
8187a2b7 | 2480 | } |
62fdfeaf | 2481 | |
0bc40be8 | 2482 | static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine, |
297b0c5b | 2483 | u32 value) |
881f47b6 | 2484 | { |
c033666a | 2485 | struct drm_i915_private *dev_priv = engine->i915; |
881f47b6 | 2486 | |
76f8421f CW |
2487 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
2488 | ||
881f47b6 | 2489 | /* Every tail move must follow the sequence below */ |
12f55818 CW |
2490 | |
2491 | /* Disable notification that the ring is IDLE. The GT | |
2492 | * will then assume that it is busy and bring it out of rc6. | |
2493 | */ | |
76f8421f CW |
2494 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
2495 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
12f55818 CW |
2496 | |
2497 | /* Clear the context id. Here be magic! */ | |
76f8421f | 2498 | I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0); |
0206e353 | 2499 | |
12f55818 | 2500 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
76f8421f CW |
2501 | if (intel_wait_for_register_fw(dev_priv, |
2502 | GEN6_BSD_SLEEP_PSMI_CONTROL, | |
2503 | GEN6_BSD_SLEEP_INDICATOR, | |
2504 | 0, | |
2505 | 50)) | |
12f55818 | 2506 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
0206e353 | 2507 | |
12f55818 | 2508 | /* Now that the ring is fully powered up, update the tail */ |
76f8421f CW |
2509 | I915_WRITE_FW(RING_TAIL(engine->mmio_base), value); |
2510 | POSTING_READ_FW(RING_TAIL(engine->mmio_base)); | |
12f55818 CW |
2511 | |
2512 | /* Let the ring send IDLE messages to the GT again, | |
2513 | * and so let it sleep to conserve power when idle. | |
2514 | */ | |
76f8421f CW |
2515 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
2516 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
2517 | ||
2518 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
881f47b6 XH |
2519 | } |
2520 | ||
7c9cf4e3 | 2521 | static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
881f47b6 | 2522 | { |
7e37f889 | 2523 | struct intel_ring *ring = req->ring; |
71a77e07 | 2524 | uint32_t cmd; |
b72f3acb CW |
2525 | int ret; |
2526 | ||
5fb9de1a | 2527 | ret = intel_ring_begin(req, 4); |
b72f3acb CW |
2528 | if (ret) |
2529 | return ret; | |
2530 | ||
71a77e07 | 2531 | cmd = MI_FLUSH_DW; |
c033666a | 2532 | if (INTEL_GEN(req->i915) >= 8) |
075b3bba | 2533 | cmd += 1; |
f0a1fb10 CW |
2534 | |
2535 | /* We always require a command barrier so that subsequent | |
2536 | * commands, such as breadcrumb interrupts, are strictly ordered | |
2537 | * wrt the contents of the write cache being flushed to memory | |
2538 | * (and thus being coherent from the CPU). | |
2539 | */ | |
2540 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2541 | ||
9a289771 JB |
2542 | /* |
2543 | * Bspec vol 1c.5 - video engine command streamer: | |
2544 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2545 | * operation is complete. This bit is only valid when the | |
2546 | * Post-Sync Operation field is a value of 1h or 3h." | |
2547 | */ | |
7c9cf4e3 | 2548 | if (mode & EMIT_INVALIDATE) |
f0a1fb10 CW |
2549 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
2550 | ||
b5321f30 CW |
2551 | intel_ring_emit(ring, cmd); |
2552 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); | |
c033666a | 2553 | if (INTEL_GEN(req->i915) >= 8) { |
b5321f30 CW |
2554 | intel_ring_emit(ring, 0); /* upper addr */ |
2555 | intel_ring_emit(ring, 0); /* value */ | |
075b3bba | 2556 | } else { |
b5321f30 CW |
2557 | intel_ring_emit(ring, 0); |
2558 | intel_ring_emit(ring, MI_NOOP); | |
075b3bba | 2559 | } |
b5321f30 | 2560 | intel_ring_advance(ring); |
b72f3acb | 2561 | return 0; |
881f47b6 XH |
2562 | } |
2563 | ||
1c7a0623 | 2564 | static int |
53fddaf7 | 2565 | gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 2566 | u64 offset, u32 len, |
8e004efc | 2567 | unsigned dispatch_flags) |
1c7a0623 | 2568 | { |
7e37f889 | 2569 | struct intel_ring *ring = req->ring; |
b5321f30 | 2570 | bool ppgtt = USES_PPGTT(req->i915) && |
8e004efc | 2571 | !(dispatch_flags & I915_DISPATCH_SECURE); |
1c7a0623 BW |
2572 | int ret; |
2573 | ||
5fb9de1a | 2574 | ret = intel_ring_begin(req, 4); |
1c7a0623 BW |
2575 | if (ret) |
2576 | return ret; | |
2577 | ||
2578 | /* FIXME(BDW): Address space and security selectors. */ | |
b5321f30 | 2579 | intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) | |
919032ec AJ |
2580 | (dispatch_flags & I915_DISPATCH_RS ? |
2581 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
b5321f30 CW |
2582 | intel_ring_emit(ring, lower_32_bits(offset)); |
2583 | intel_ring_emit(ring, upper_32_bits(offset)); | |
2584 | intel_ring_emit(ring, MI_NOOP); | |
2585 | intel_ring_advance(ring); | |
1c7a0623 BW |
2586 | |
2587 | return 0; | |
2588 | } | |
2589 | ||
d7d4eedd | 2590 | static int |
53fddaf7 | 2591 | hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
8e004efc JH |
2592 | u64 offset, u32 len, |
2593 | unsigned dispatch_flags) | |
d7d4eedd | 2594 | { |
7e37f889 | 2595 | struct intel_ring *ring = req->ring; |
d7d4eedd CW |
2596 | int ret; |
2597 | ||
5fb9de1a | 2598 | ret = intel_ring_begin(req, 2); |
d7d4eedd CW |
2599 | if (ret) |
2600 | return ret; | |
2601 | ||
b5321f30 | 2602 | intel_ring_emit(ring, |
77072258 | 2603 | MI_BATCH_BUFFER_START | |
8e004efc | 2604 | (dispatch_flags & I915_DISPATCH_SECURE ? |
919032ec AJ |
2605 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) | |
2606 | (dispatch_flags & I915_DISPATCH_RS ? | |
2607 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
d7d4eedd | 2608 | /* bit0-7 is the length on GEN6+ */ |
b5321f30 CW |
2609 | intel_ring_emit(ring, offset); |
2610 | intel_ring_advance(ring); | |
d7d4eedd CW |
2611 | |
2612 | return 0; | |
2613 | } | |
2614 | ||
881f47b6 | 2615 | static int |
53fddaf7 | 2616 | gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 2617 | u64 offset, u32 len, |
8e004efc | 2618 | unsigned dispatch_flags) |
881f47b6 | 2619 | { |
7e37f889 | 2620 | struct intel_ring *ring = req->ring; |
0206e353 | 2621 | int ret; |
ab6f8e32 | 2622 | |
5fb9de1a | 2623 | ret = intel_ring_begin(req, 2); |
0206e353 AJ |
2624 | if (ret) |
2625 | return ret; | |
e1f99ce6 | 2626 | |
b5321f30 | 2627 | intel_ring_emit(ring, |
d7d4eedd | 2628 | MI_BATCH_BUFFER_START | |
8e004efc JH |
2629 | (dispatch_flags & I915_DISPATCH_SECURE ? |
2630 | 0 : MI_BATCH_NON_SECURE_I965)); | |
0206e353 | 2631 | /* bit0-7 is the length on GEN6+ */ |
b5321f30 CW |
2632 | intel_ring_emit(ring, offset); |
2633 | intel_ring_advance(ring); | |
ab6f8e32 | 2634 | |
0206e353 | 2635 | return 0; |
881f47b6 XH |
2636 | } |
2637 | ||
549f7365 CW |
2638 | /* Blitter support (SandyBridge+) */ |
2639 | ||
7c9cf4e3 | 2640 | static int gen6_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
8d19215b | 2641 | { |
7e37f889 | 2642 | struct intel_ring *ring = req->ring; |
71a77e07 | 2643 | uint32_t cmd; |
b72f3acb CW |
2644 | int ret; |
2645 | ||
5fb9de1a | 2646 | ret = intel_ring_begin(req, 4); |
b72f3acb CW |
2647 | if (ret) |
2648 | return ret; | |
2649 | ||
71a77e07 | 2650 | cmd = MI_FLUSH_DW; |
c033666a | 2651 | if (INTEL_GEN(req->i915) >= 8) |
075b3bba | 2652 | cmd += 1; |
f0a1fb10 CW |
2653 | |
2654 | /* We always require a command barrier so that subsequent | |
2655 | * commands, such as breadcrumb interrupts, are strictly ordered | |
2656 | * wrt the contents of the write cache being flushed to memory | |
2657 | * (and thus being coherent from the CPU). | |
2658 | */ | |
2659 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2660 | ||
9a289771 JB |
2661 | /* |
2662 | * Bspec vol 1c.3 - blitter engine command streamer: | |
2663 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2664 | * operation is complete. This bit is only valid when the | |
2665 | * Post-Sync Operation field is a value of 1h or 3h." | |
2666 | */ | |
7c9cf4e3 | 2667 | if (mode & EMIT_INVALIDATE) |
f0a1fb10 | 2668 | cmd |= MI_INVALIDATE_TLB; |
b5321f30 CW |
2669 | intel_ring_emit(ring, cmd); |
2670 | intel_ring_emit(ring, | |
e2f80391 | 2671 | I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
c033666a | 2672 | if (INTEL_GEN(req->i915) >= 8) { |
b5321f30 CW |
2673 | intel_ring_emit(ring, 0); /* upper addr */ |
2674 | intel_ring_emit(ring, 0); /* value */ | |
075b3bba | 2675 | } else { |
b5321f30 CW |
2676 | intel_ring_emit(ring, 0); |
2677 | intel_ring_emit(ring, MI_NOOP); | |
075b3bba | 2678 | } |
b5321f30 | 2679 | intel_ring_advance(ring); |
fd3da6c9 | 2680 | |
b72f3acb | 2681 | return 0; |
8d19215b ZN |
2682 | } |
2683 | ||
d9a64610 TU |
2684 | static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv, |
2685 | struct intel_engine_cs *engine) | |
2686 | { | |
db3d4019 | 2687 | struct drm_i915_gem_object *obj; |
1b9e6650 | 2688 | int ret, i; |
db3d4019 | 2689 | |
39df9190 | 2690 | if (!i915.semaphores) |
db3d4019 TU |
2691 | return; |
2692 | ||
2693 | if (INTEL_GEN(dev_priv) >= 8 && !dev_priv->semaphore_obj) { | |
91c8a326 | 2694 | obj = i915_gem_object_create(&dev_priv->drm, 4096); |
db3d4019 TU |
2695 | if (IS_ERR(obj)) { |
2696 | DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n"); | |
2697 | i915.semaphores = 0; | |
2698 | } else { | |
2699 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
2700 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK); | |
2701 | if (ret != 0) { | |
f8c417cd | 2702 | i915_gem_object_put(obj); |
db3d4019 TU |
2703 | DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n"); |
2704 | i915.semaphores = 0; | |
2705 | } else { | |
2706 | dev_priv->semaphore_obj = obj; | |
2707 | } | |
2708 | } | |
2709 | } | |
2710 | ||
39df9190 | 2711 | if (!i915.semaphores) |
d9a64610 TU |
2712 | return; |
2713 | ||
2714 | if (INTEL_GEN(dev_priv) >= 8) { | |
1b9e6650 TU |
2715 | u64 offset = i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj); |
2716 | ||
d9a64610 TU |
2717 | engine->semaphore.sync_to = gen8_ring_sync; |
2718 | engine->semaphore.signal = gen8_xcs_signal; | |
1b9e6650 TU |
2719 | |
2720 | for (i = 0; i < I915_NUM_ENGINES; i++) { | |
2721 | u64 ring_offset; | |
2722 | ||
2723 | if (i != engine->id) | |
2724 | ring_offset = offset + GEN8_SEMAPHORE_OFFSET(engine->id, i); | |
2725 | else | |
2726 | ring_offset = MI_SEMAPHORE_SYNC_INVALID; | |
2727 | ||
2728 | engine->semaphore.signal_ggtt[i] = ring_offset; | |
2729 | } | |
d9a64610 TU |
2730 | } else if (INTEL_GEN(dev_priv) >= 6) { |
2731 | engine->semaphore.sync_to = gen6_ring_sync; | |
2732 | engine->semaphore.signal = gen6_signal; | |
4b8e38a9 TU |
2733 | |
2734 | /* | |
2735 | * The current semaphore is only applied on pre-gen8 | |
2736 | * platform. And there is no VCS2 ring on the pre-gen8 | |
2737 | * platform. So the semaphore between RCS and VCS2 is | |
2738 | * initialized as INVALID. Gen8 will initialize the | |
2739 | * sema between VCS2 and RCS later. | |
2740 | */ | |
2741 | for (i = 0; i < I915_NUM_ENGINES; i++) { | |
2742 | static const struct { | |
2743 | u32 wait_mbox; | |
2744 | i915_reg_t mbox_reg; | |
2745 | } sem_data[I915_NUM_ENGINES][I915_NUM_ENGINES] = { | |
2746 | [RCS] = { | |
2747 | [VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RV, .mbox_reg = GEN6_VRSYNC }, | |
2748 | [BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RB, .mbox_reg = GEN6_BRSYNC }, | |
2749 | [VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC }, | |
2750 | }, | |
2751 | [VCS] = { | |
2752 | [RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VR, .mbox_reg = GEN6_RVSYNC }, | |
2753 | [BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VB, .mbox_reg = GEN6_BVSYNC }, | |
2754 | [VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC }, | |
2755 | }, | |
2756 | [BCS] = { | |
2757 | [RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BR, .mbox_reg = GEN6_RBSYNC }, | |
2758 | [VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BV, .mbox_reg = GEN6_VBSYNC }, | |
2759 | [VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC }, | |
2760 | }, | |
2761 | [VECS] = { | |
2762 | [RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC }, | |
2763 | [VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC }, | |
2764 | [BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC }, | |
2765 | }, | |
2766 | }; | |
2767 | u32 wait_mbox; | |
2768 | i915_reg_t mbox_reg; | |
2769 | ||
2770 | if (i == engine->id || i == VCS2) { | |
2771 | wait_mbox = MI_SEMAPHORE_SYNC_INVALID; | |
2772 | mbox_reg = GEN6_NOSYNC; | |
2773 | } else { | |
2774 | wait_mbox = sem_data[engine->id][i].wait_mbox; | |
2775 | mbox_reg = sem_data[engine->id][i].mbox_reg; | |
2776 | } | |
2777 | ||
2778 | engine->semaphore.mbox.wait[i] = wait_mbox; | |
2779 | engine->semaphore.mbox.signal[i] = mbox_reg; | |
2780 | } | |
d9a64610 TU |
2781 | } |
2782 | } | |
2783 | ||
ed003078 CW |
2784 | static void intel_ring_init_irq(struct drm_i915_private *dev_priv, |
2785 | struct intel_engine_cs *engine) | |
2786 | { | |
c78d6061 TU |
2787 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << engine->irq_shift; |
2788 | ||
ed003078 | 2789 | if (INTEL_GEN(dev_priv) >= 8) { |
31bb59cc CW |
2790 | engine->irq_enable = gen8_irq_enable; |
2791 | engine->irq_disable = gen8_irq_disable; | |
ed003078 CW |
2792 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2793 | } else if (INTEL_GEN(dev_priv) >= 6) { | |
31bb59cc CW |
2794 | engine->irq_enable = gen6_irq_enable; |
2795 | engine->irq_disable = gen6_irq_disable; | |
ed003078 CW |
2796 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2797 | } else if (INTEL_GEN(dev_priv) >= 5) { | |
31bb59cc CW |
2798 | engine->irq_enable = gen5_irq_enable; |
2799 | engine->irq_disable = gen5_irq_disable; | |
f8973c21 | 2800 | engine->irq_seqno_barrier = gen5_seqno_barrier; |
ed003078 | 2801 | } else if (INTEL_GEN(dev_priv) >= 3) { |
31bb59cc CW |
2802 | engine->irq_enable = i9xx_irq_enable; |
2803 | engine->irq_disable = i9xx_irq_disable; | |
ed003078 | 2804 | } else { |
31bb59cc CW |
2805 | engine->irq_enable = i8xx_irq_enable; |
2806 | engine->irq_disable = i8xx_irq_disable; | |
ed003078 CW |
2807 | } |
2808 | } | |
2809 | ||
06a2fe22 TU |
2810 | static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv, |
2811 | struct intel_engine_cs *engine) | |
2812 | { | |
1d8a1337 | 2813 | engine->init_hw = init_ring_common; |
06a2fe22 | 2814 | engine->write_tail = ring_write_tail; |
7445a2a4 | 2815 | |
6f7bef75 CW |
2816 | engine->add_request = i9xx_add_request; |
2817 | if (INTEL_GEN(dev_priv) >= 6) | |
960ecaad | 2818 | engine->add_request = gen6_add_request; |
6f7bef75 CW |
2819 | |
2820 | if (INTEL_GEN(dev_priv) >= 8) | |
2821 | engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; | |
2822 | else if (INTEL_GEN(dev_priv) >= 6) | |
960ecaad | 2823 | engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
6f7bef75 | 2824 | else if (INTEL_GEN(dev_priv) >= 4) |
960ecaad | 2825 | engine->dispatch_execbuffer = i965_dispatch_execbuffer; |
6f7bef75 CW |
2826 | else if (IS_I830(dev_priv) || IS_845G(dev_priv)) |
2827 | engine->dispatch_execbuffer = i830_dispatch_execbuffer; | |
2828 | else | |
2829 | engine->dispatch_execbuffer = i915_dispatch_execbuffer; | |
b9700325 | 2830 | |
ed003078 | 2831 | intel_ring_init_irq(dev_priv, engine); |
d9a64610 | 2832 | intel_ring_init_semaphores(dev_priv, engine); |
06a2fe22 TU |
2833 | } |
2834 | ||
8b3e2d36 | 2835 | int intel_init_render_ring_buffer(struct intel_engine_cs *engine) |
5c1143bb | 2836 | { |
8b3e2d36 | 2837 | struct drm_i915_private *dev_priv = engine->i915; |
3e78998a | 2838 | int ret; |
5c1143bb | 2839 | |
06a2fe22 TU |
2840 | intel_ring_default_vfuncs(dev_priv, engine); |
2841 | ||
61ff75ac CW |
2842 | if (HAS_L3_DPF(dev_priv)) |
2843 | engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
f8973c21 | 2844 | |
c033666a | 2845 | if (INTEL_GEN(dev_priv) >= 8) { |
e2f80391 | 2846 | engine->init_context = intel_rcs_ctx_init; |
a58c01aa | 2847 | engine->add_request = gen8_render_add_request; |
c7fe7d25 | 2848 | engine->emit_flush = gen8_render_ring_flush; |
39df9190 | 2849 | if (i915.semaphores) |
e2f80391 | 2850 | engine->semaphore.signal = gen8_rcs_signal; |
c033666a | 2851 | } else if (INTEL_GEN(dev_priv) >= 6) { |
e2f80391 | 2852 | engine->init_context = intel_rcs_ctx_init; |
c7fe7d25 | 2853 | engine->emit_flush = gen7_render_ring_flush; |
c033666a | 2854 | if (IS_GEN6(dev_priv)) |
c7fe7d25 | 2855 | engine->emit_flush = gen6_render_ring_flush; |
c033666a | 2856 | } else if (IS_GEN5(dev_priv)) { |
c7fe7d25 | 2857 | engine->emit_flush = gen4_render_ring_flush; |
59465b5f | 2858 | } else { |
c033666a | 2859 | if (INTEL_GEN(dev_priv) < 4) |
c7fe7d25 | 2860 | engine->emit_flush = gen2_render_ring_flush; |
46f0f8d1 | 2861 | else |
c7fe7d25 | 2862 | engine->emit_flush = gen4_render_ring_flush; |
e2f80391 | 2863 | engine->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2864 | } |
707d9cf9 | 2865 | |
c033666a | 2866 | if (IS_HASWELL(dev_priv)) |
e2f80391 | 2867 | engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; |
6f7bef75 | 2868 | |
e2f80391 TU |
2869 | engine->init_hw = init_render_ring; |
2870 | engine->cleanup = render_ring_cleanup; | |
59465b5f | 2871 | |
acd27845 | 2872 | ret = intel_init_ring_buffer(engine); |
99be1dfe DV |
2873 | if (ret) |
2874 | return ret; | |
2875 | ||
f8973c21 | 2876 | if (INTEL_GEN(dev_priv) >= 6) { |
7d5ea807 CW |
2877 | ret = intel_init_pipe_control(engine, 4096); |
2878 | if (ret) | |
2879 | return ret; | |
2880 | } else if (HAS_BROKEN_CS_TLB(dev_priv)) { | |
2881 | ret = intel_init_pipe_control(engine, I830_WA_SIZE); | |
99be1dfe DV |
2882 | if (ret) |
2883 | return ret; | |
2884 | } | |
2885 | ||
2886 | return 0; | |
5c1143bb XH |
2887 | } |
2888 | ||
8b3e2d36 | 2889 | int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine) |
5c1143bb | 2890 | { |
8b3e2d36 | 2891 | struct drm_i915_private *dev_priv = engine->i915; |
58fa3835 | 2892 | |
06a2fe22 TU |
2893 | intel_ring_default_vfuncs(dev_priv, engine); |
2894 | ||
c033666a | 2895 | if (INTEL_GEN(dev_priv) >= 6) { |
0fd2c201 | 2896 | /* gen6 bsd needs a special wa for tail updates */ |
c033666a | 2897 | if (IS_GEN6(dev_priv)) |
e2f80391 | 2898 | engine->write_tail = gen6_bsd_ring_write_tail; |
c7fe7d25 | 2899 | engine->emit_flush = gen6_bsd_ring_flush; |
c78d6061 | 2900 | if (INTEL_GEN(dev_priv) < 8) |
e2f80391 | 2901 | engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
58fa3835 | 2902 | } else { |
e2f80391 | 2903 | engine->mmio_base = BSD_RING_BASE; |
c7fe7d25 | 2904 | engine->emit_flush = bsd_ring_flush; |
8d228911 | 2905 | if (IS_GEN5(dev_priv)) |
e2f80391 | 2906 | engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
8d228911 | 2907 | else |
e2f80391 | 2908 | engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
58fa3835 | 2909 | } |
58fa3835 | 2910 | |
acd27845 | 2911 | return intel_init_ring_buffer(engine); |
5c1143bb | 2912 | } |
549f7365 | 2913 | |
845f74a7 | 2914 | /** |
62659920 | 2915 | * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3) |
845f74a7 | 2916 | */ |
8b3e2d36 | 2917 | int intel_init_bsd2_ring_buffer(struct intel_engine_cs *engine) |
845f74a7 | 2918 | { |
8b3e2d36 | 2919 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 TU |
2920 | |
2921 | intel_ring_default_vfuncs(dev_priv, engine); | |
2922 | ||
c7fe7d25 | 2923 | engine->emit_flush = gen6_bsd_ring_flush; |
845f74a7 | 2924 | |
acd27845 | 2925 | return intel_init_ring_buffer(engine); |
845f74a7 ZY |
2926 | } |
2927 | ||
8b3e2d36 | 2928 | int intel_init_blt_ring_buffer(struct intel_engine_cs *engine) |
549f7365 | 2929 | { |
8b3e2d36 | 2930 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 TU |
2931 | |
2932 | intel_ring_default_vfuncs(dev_priv, engine); | |
2933 | ||
c7fe7d25 | 2934 | engine->emit_flush = gen6_ring_flush; |
c78d6061 | 2935 | if (INTEL_GEN(dev_priv) < 8) |
e2f80391 | 2936 | engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
549f7365 | 2937 | |
acd27845 | 2938 | return intel_init_ring_buffer(engine); |
549f7365 | 2939 | } |
a7b9761d | 2940 | |
8b3e2d36 | 2941 | int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine) |
9a8a2213 | 2942 | { |
8b3e2d36 | 2943 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 TU |
2944 | |
2945 | intel_ring_default_vfuncs(dev_priv, engine); | |
2946 | ||
c7fe7d25 | 2947 | engine->emit_flush = gen6_ring_flush; |
abd58f01 | 2948 | |
c78d6061 | 2949 | if (INTEL_GEN(dev_priv) < 8) { |
e2f80391 | 2950 | engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
31bb59cc CW |
2951 | engine->irq_enable = hsw_vebox_irq_enable; |
2952 | engine->irq_disable = hsw_vebox_irq_disable; | |
abd58f01 | 2953 | } |
9a8a2213 | 2954 | |
acd27845 | 2955 | return intel_init_ring_buffer(engine); |
9a8a2213 BW |
2956 | } |
2957 | ||
7e37f889 | 2958 | void intel_engine_stop(struct intel_engine_cs *engine) |
e3efda49 CW |
2959 | { |
2960 | int ret; | |
2961 | ||
117897f4 | 2962 | if (!intel_engine_initialized(engine)) |
e3efda49 CW |
2963 | return; |
2964 | ||
666796da | 2965 | ret = intel_engine_idle(engine); |
f4457ae7 | 2966 | if (ret) |
e3efda49 | 2967 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
0bc40be8 | 2968 | engine->name, ret); |
e3efda49 | 2969 | |
0bc40be8 | 2970 | stop_ring(engine); |
e3efda49 | 2971 | } |