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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
a4d8a0fe | 30 | #include <linux/log2.h> |
7c2fa7fa | 31 | |
760285e7 | 32 | #include <drm/i915_drm.h> |
7c2fa7fa CW |
33 | |
34 | #include "i915_drv.h" | |
35 | #include "i915_gem_render_state.h" | |
eb8d0f5a | 36 | #include "i915_reset.h" |
62fdfeaf | 37 | #include "i915_trace.h" |
881f47b6 | 38 | #include "intel_drv.h" |
7d3c425f | 39 | #include "intel_workarounds.h" |
62fdfeaf | 40 | |
a0442461 CW |
41 | /* Rough estimate of the typical request size, performing a flush, |
42 | * set-context and then emitting the batch. | |
43 | */ | |
44 | #define LEGACY_REQUEST_SIZE 200 | |
45 | ||
0ca88ba0 CW |
46 | static inline u32 intel_hws_seqno_address(struct intel_engine_cs *engine) |
47 | { | |
48 | return (i915_ggtt_offset(engine->status_page.vma) + | |
49 | I915_GEM_HWS_INDEX_ADDR); | |
50 | } | |
51 | ||
605d5b32 CW |
52 | static unsigned int __intel_ring_space(unsigned int head, |
53 | unsigned int tail, | |
54 | unsigned int size) | |
c7dca47b | 55 | { |
605d5b32 CW |
56 | /* |
57 | * "If the Ring Buffer Head Pointer and the Tail Pointer are on the | |
58 | * same cacheline, the Head Pointer must not be greater than the Tail | |
59 | * Pointer." | |
60 | */ | |
61 | GEM_BUG_ON(!is_power_of_2(size)); | |
62 | return (head - tail - CACHELINE_BYTES) & (size - 1); | |
c7dca47b CW |
63 | } |
64 | ||
95aebcb2 | 65 | unsigned int intel_ring_update_space(struct intel_ring *ring) |
ebd0fd4b | 66 | { |
95aebcb2 CW |
67 | unsigned int space; |
68 | ||
69 | space = __intel_ring_space(ring->head, ring->emit, ring->size); | |
70 | ||
71 | ring->space = space; | |
72 | return space; | |
ebd0fd4b DG |
73 | } |
74 | ||
b72f3acb | 75 | static int |
e61e0f51 | 76 | gen2_render_ring_flush(struct i915_request *rq, u32 mode) |
46f0f8d1 | 77 | { |
a889580c | 78 | unsigned int num_store_dw; |
73dec95e | 79 | u32 cmd, *cs; |
46f0f8d1 CW |
80 | |
81 | cmd = MI_FLUSH; | |
a889580c | 82 | num_store_dw = 0; |
7c9cf4e3 | 83 | if (mode & EMIT_INVALIDATE) |
46f0f8d1 | 84 | cmd |= MI_READ_FLUSH; |
a889580c CW |
85 | if (mode & EMIT_FLUSH) |
86 | num_store_dw = 4; | |
46f0f8d1 | 87 | |
a889580c | 88 | cs = intel_ring_begin(rq, 2 + 3 * num_store_dw); |
73dec95e TU |
89 | if (IS_ERR(cs)) |
90 | return PTR_ERR(cs); | |
46f0f8d1 | 91 | |
73dec95e | 92 | *cs++ = cmd; |
a889580c CW |
93 | while (num_store_dw--) { |
94 | *cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL; | |
95 | *cs++ = i915_scratch_offset(rq->i915); | |
96 | *cs++ = 0; | |
97 | } | |
98 | *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
99 | ||
e61e0f51 | 100 | intel_ring_advance(rq, cs); |
46f0f8d1 CW |
101 | |
102 | return 0; | |
103 | } | |
104 | ||
105 | static int | |
e61e0f51 | 106 | gen4_render_ring_flush(struct i915_request *rq, u32 mode) |
62fdfeaf | 107 | { |
73dec95e | 108 | u32 cmd, *cs; |
55f99bf2 | 109 | int i; |
6f392d54 | 110 | |
36d527de CW |
111 | /* |
112 | * read/write caches: | |
113 | * | |
114 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
115 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
116 | * also flushed at 2d versus 3d pipeline switches. | |
117 | * | |
118 | * read-only caches: | |
119 | * | |
120 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
121 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
122 | * | |
123 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
124 | * | |
125 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
126 | * invalidated when MI_EXE_FLUSH is set. | |
127 | * | |
128 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
129 | * invalidated with every MI_FLUSH. | |
130 | * | |
131 | * TLBs: | |
132 | * | |
133 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
134 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
135 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
136 | * are flushed at any MI_FLUSH. | |
137 | */ | |
138 | ||
b5321f30 | 139 | cmd = MI_FLUSH; |
7c9cf4e3 | 140 | if (mode & EMIT_INVALIDATE) { |
36d527de | 141 | cmd |= MI_EXE_FLUSH; |
cf819eff | 142 | if (IS_G4X(rq->i915) || IS_GEN(rq->i915, 5)) |
b5321f30 CW |
143 | cmd |= MI_INVALIDATE_ISP; |
144 | } | |
70eac33e | 145 | |
55f99bf2 CW |
146 | i = 2; |
147 | if (mode & EMIT_INVALIDATE) | |
148 | i += 20; | |
149 | ||
150 | cs = intel_ring_begin(rq, i); | |
73dec95e TU |
151 | if (IS_ERR(cs)) |
152 | return PTR_ERR(cs); | |
b72f3acb | 153 | |
73dec95e | 154 | *cs++ = cmd; |
55f99bf2 CW |
155 | |
156 | /* | |
157 | * A random delay to let the CS invalidate take effect? Without this | |
158 | * delay, the GPU relocation path fails as the CS does not see | |
159 | * the updated contents. Just as important, if we apply the flushes | |
160 | * to the EMIT_FLUSH branch (i.e. immediately after the relocation | |
161 | * write and before the invalidate on the next batch), the relocations | |
162 | * still fail. This implies that is a delay following invalidation | |
163 | * that is required to reset the caches as opposed to a delay to | |
164 | * ensure the memory is written. | |
165 | */ | |
166 | if (mode & EMIT_INVALIDATE) { | |
167 | *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; | |
51797499 | 168 | *cs++ = i915_scratch_offset(rq->i915) | PIPE_CONTROL_GLOBAL_GTT; |
55f99bf2 CW |
169 | *cs++ = 0; |
170 | *cs++ = 0; | |
171 | ||
172 | for (i = 0; i < 12; i++) | |
173 | *cs++ = MI_FLUSH; | |
174 | ||
175 | *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; | |
51797499 | 176 | *cs++ = i915_scratch_offset(rq->i915) | PIPE_CONTROL_GLOBAL_GTT; |
55f99bf2 CW |
177 | *cs++ = 0; |
178 | *cs++ = 0; | |
179 | } | |
180 | ||
181 | *cs++ = cmd; | |
182 | ||
e61e0f51 | 183 | intel_ring_advance(rq, cs); |
b72f3acb CW |
184 | |
185 | return 0; | |
8187a2b7 ZN |
186 | } |
187 | ||
179f4025 | 188 | /* |
8d315287 JB |
189 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for |
190 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
191 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
192 | * | |
193 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
194 | * produced by non-pipelined state commands), software needs to first | |
195 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
196 | * 0. | |
197 | * | |
198 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
199 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
200 | * | |
201 | * And the workaround for these two requires this workaround first: | |
202 | * | |
203 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
204 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
205 | * flushes. | |
206 | * | |
207 | * And this last workaround is tricky because of the requirements on | |
208 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
209 | * volume 2 part 1: | |
210 | * | |
211 | * "1 of the following must also be set: | |
212 | * - Render Target Cache Flush Enable ([12] of DW1) | |
213 | * - Depth Cache Flush Enable ([0] of DW1) | |
214 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
215 | * - Depth Stall ([13] of DW1) | |
216 | * - Post-Sync Operation ([13] of DW1) | |
217 | * - Notify Enable ([8] of DW1)" | |
218 | * | |
219 | * The cache flushes require the workaround flush that triggered this | |
220 | * one, so we can't use it. Depth stall would trigger the same. | |
221 | * Post-sync nonzero is what triggered this second workaround, so we | |
222 | * can't use that one either. Notify enable is IRQs, which aren't | |
223 | * really our business. That leaves only stall at scoreboard. | |
224 | */ | |
225 | static int | |
caa5915b | 226 | gen6_emit_post_sync_nonzero_flush(struct i915_request *rq) |
8d315287 | 227 | { |
51797499 | 228 | u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES; |
73dec95e TU |
229 | u32 *cs; |
230 | ||
e61e0f51 | 231 | cs = intel_ring_begin(rq, 6); |
73dec95e TU |
232 | if (IS_ERR(cs)) |
233 | return PTR_ERR(cs); | |
234 | ||
235 | *cs++ = GFX_OP_PIPE_CONTROL(5); | |
236 | *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; | |
237 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
238 | *cs++ = 0; /* low dword */ | |
239 | *cs++ = 0; /* high dword */ | |
240 | *cs++ = MI_NOOP; | |
e61e0f51 | 241 | intel_ring_advance(rq, cs); |
73dec95e | 242 | |
e61e0f51 | 243 | cs = intel_ring_begin(rq, 6); |
73dec95e TU |
244 | if (IS_ERR(cs)) |
245 | return PTR_ERR(cs); | |
246 | ||
247 | *cs++ = GFX_OP_PIPE_CONTROL(5); | |
248 | *cs++ = PIPE_CONTROL_QW_WRITE; | |
249 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
250 | *cs++ = 0; | |
251 | *cs++ = 0; | |
252 | *cs++ = MI_NOOP; | |
e61e0f51 | 253 | intel_ring_advance(rq, cs); |
8d315287 JB |
254 | |
255 | return 0; | |
256 | } | |
257 | ||
258 | static int | |
e61e0f51 | 259 | gen6_render_ring_flush(struct i915_request *rq, u32 mode) |
8d315287 | 260 | { |
51797499 | 261 | u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES; |
73dec95e | 262 | u32 *cs, flags = 0; |
8d315287 JB |
263 | int ret; |
264 | ||
b3111509 | 265 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
caa5915b | 266 | ret = gen6_emit_post_sync_nonzero_flush(rq); |
b3111509 PZ |
267 | if (ret) |
268 | return ret; | |
269 | ||
8d315287 JB |
270 | /* Just flush everything. Experiments have shown that reducing the |
271 | * number of bits based on the write domains has little performance | |
272 | * impact. | |
273 | */ | |
7c9cf4e3 | 274 | if (mode & EMIT_FLUSH) { |
7d54a904 CW |
275 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
276 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
277 | /* | |
278 | * Ensure that any following seqno writes only happen | |
279 | * when the render cache is indeed flushed. | |
280 | */ | |
97f209bc | 281 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 | 282 | } |
7c9cf4e3 | 283 | if (mode & EMIT_INVALIDATE) { |
7d54a904 CW |
284 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
285 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
286 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
287 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
288 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
289 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
290 | /* | |
291 | * TLB invalidate requires a post-sync write. | |
292 | */ | |
3ac78313 | 293 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 294 | } |
8d315287 | 295 | |
e61e0f51 | 296 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
297 | if (IS_ERR(cs)) |
298 | return PTR_ERR(cs); | |
8d315287 | 299 | |
73dec95e TU |
300 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
301 | *cs++ = flags; | |
302 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
303 | *cs++ = 0; | |
e61e0f51 | 304 | intel_ring_advance(rq, cs); |
8d315287 JB |
305 | |
306 | return 0; | |
307 | } | |
308 | ||
e1a73a54 | 309 | static u32 *gen6_rcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
caa5915b CW |
310 | { |
311 | /* First we do the gen6_emit_post_sync_nonzero_flush w/a */ | |
312 | *cs++ = GFX_OP_PIPE_CONTROL(4); | |
313 | *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; | |
314 | *cs++ = 0; | |
315 | *cs++ = 0; | |
316 | ||
317 | *cs++ = GFX_OP_PIPE_CONTROL(4); | |
318 | *cs++ = PIPE_CONTROL_QW_WRITE; | |
319 | *cs++ = i915_scratch_offset(rq->i915) | PIPE_CONTROL_GLOBAL_GTT; | |
320 | *cs++ = 0; | |
321 | ||
322 | /* Finally we can flush and with it emit the breadcrumb */ | |
323 | *cs++ = GFX_OP_PIPE_CONTROL(4); | |
324 | *cs++ = (PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | | |
325 | PIPE_CONTROL_DEPTH_CACHE_FLUSH | | |
326 | PIPE_CONTROL_DC_FLUSH_ENABLE | | |
327 | PIPE_CONTROL_QW_WRITE | | |
328 | PIPE_CONTROL_CS_STALL); | |
5013eb8c CW |
329 | *cs++ = rq->timeline->hwsp_offset | PIPE_CONTROL_GLOBAL_GTT; |
330 | *cs++ = rq->fence.seqno; | |
331 | ||
332 | *cs++ = GFX_OP_PIPE_CONTROL(4); | |
333 | *cs++ = PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; | |
caa5915b CW |
334 | *cs++ = intel_hws_seqno_address(rq->engine) | PIPE_CONTROL_GLOBAL_GTT; |
335 | *cs++ = rq->global_seqno; | |
336 | ||
337 | *cs++ = MI_USER_INTERRUPT; | |
338 | *cs++ = MI_NOOP; | |
339 | ||
340 | rq->tail = intel_ring_offset(rq, cs); | |
341 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
342 | |
343 | return cs; | |
caa5915b | 344 | } |
caa5915b | 345 | |
f3987631 | 346 | static int |
e61e0f51 | 347 | gen7_render_ring_cs_stall_wa(struct i915_request *rq) |
f3987631 | 348 | { |
73dec95e | 349 | u32 *cs; |
f3987631 | 350 | |
e61e0f51 | 351 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
352 | if (IS_ERR(cs)) |
353 | return PTR_ERR(cs); | |
f3987631 | 354 | |
73dec95e TU |
355 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
356 | *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; | |
357 | *cs++ = 0; | |
358 | *cs++ = 0; | |
e61e0f51 | 359 | intel_ring_advance(rq, cs); |
f3987631 PZ |
360 | |
361 | return 0; | |
362 | } | |
363 | ||
4772eaeb | 364 | static int |
e61e0f51 | 365 | gen7_render_ring_flush(struct i915_request *rq, u32 mode) |
4772eaeb | 366 | { |
51797499 | 367 | u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES; |
73dec95e | 368 | u32 *cs, flags = 0; |
4772eaeb | 369 | |
f3987631 PZ |
370 | /* |
371 | * Ensure that any following seqno writes only happen when the render | |
372 | * cache is indeed flushed. | |
373 | * | |
374 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
375 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
376 | * don't try to be clever and just set it unconditionally. | |
377 | */ | |
378 | flags |= PIPE_CONTROL_CS_STALL; | |
379 | ||
4772eaeb PZ |
380 | /* Just flush everything. Experiments have shown that reducing the |
381 | * number of bits based on the write domains has little performance | |
382 | * impact. | |
383 | */ | |
7c9cf4e3 | 384 | if (mode & EMIT_FLUSH) { |
4772eaeb PZ |
385 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
386 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 387 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 388 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4772eaeb | 389 | } |
7c9cf4e3 | 390 | if (mode & EMIT_INVALIDATE) { |
4772eaeb PZ |
391 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
392 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
393 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
394 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
395 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
396 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
148b83d0 | 397 | flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; |
4772eaeb PZ |
398 | /* |
399 | * TLB invalidate requires a post-sync write. | |
400 | */ | |
401 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 402 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 | 403 | |
add284a3 CW |
404 | flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; |
405 | ||
f3987631 PZ |
406 | /* Workaround: we must issue a pipe_control with CS-stall bit |
407 | * set before a pipe_control command that has the state cache | |
408 | * invalidate bit set. */ | |
e61e0f51 | 409 | gen7_render_ring_cs_stall_wa(rq); |
4772eaeb PZ |
410 | } |
411 | ||
e61e0f51 | 412 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
413 | if (IS_ERR(cs)) |
414 | return PTR_ERR(cs); | |
4772eaeb | 415 | |
73dec95e TU |
416 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
417 | *cs++ = flags; | |
418 | *cs++ = scratch_addr; | |
419 | *cs++ = 0; | |
e61e0f51 | 420 | intel_ring_advance(rq, cs); |
4772eaeb PZ |
421 | |
422 | return 0; | |
423 | } | |
424 | ||
e1a73a54 | 425 | static u32 *gen7_rcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
caa5915b CW |
426 | { |
427 | *cs++ = GFX_OP_PIPE_CONTROL(4); | |
428 | *cs++ = (PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | | |
429 | PIPE_CONTROL_DEPTH_CACHE_FLUSH | | |
430 | PIPE_CONTROL_DC_FLUSH_ENABLE | | |
431 | PIPE_CONTROL_FLUSH_ENABLE | | |
432 | PIPE_CONTROL_QW_WRITE | | |
433 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
434 | PIPE_CONTROL_CS_STALL); | |
5013eb8c CW |
435 | *cs++ = rq->timeline->hwsp_offset; |
436 | *cs++ = rq->fence.seqno; | |
437 | ||
438 | *cs++ = GFX_OP_PIPE_CONTROL(4); | |
439 | *cs++ = (PIPE_CONTROL_QW_WRITE | | |
440 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
441 | PIPE_CONTROL_CS_STALL); | |
caa5915b CW |
442 | *cs++ = intel_hws_seqno_address(rq->engine); |
443 | *cs++ = rq->global_seqno; | |
444 | ||
445 | *cs++ = MI_USER_INTERRUPT; | |
446 | *cs++ = MI_NOOP; | |
447 | ||
448 | rq->tail = intel_ring_offset(rq, cs); | |
449 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
450 | |
451 | return cs; | |
caa5915b | 452 | } |
caa5915b | 453 | |
e1a73a54 | 454 | static u32 *gen6_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
caa5915b | 455 | { |
5013eb8c CW |
456 | GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma); |
457 | GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); | |
458 | ||
459 | *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; | |
460 | *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; | |
461 | *cs++ = rq->fence.seqno; | |
462 | ||
463 | *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; | |
464 | *cs++ = I915_GEM_HWS_INDEX_ADDR | MI_FLUSH_DW_USE_GTT; | |
caa5915b | 465 | *cs++ = rq->global_seqno; |
5013eb8c | 466 | |
caa5915b | 467 | *cs++ = MI_USER_INTERRUPT; |
5013eb8c | 468 | *cs++ = MI_NOOP; |
caa5915b CW |
469 | |
470 | rq->tail = intel_ring_offset(rq, cs); | |
471 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
472 | |
473 | return cs; | |
caa5915b | 474 | } |
caa5915b | 475 | |
1212bd82 | 476 | #define GEN7_XCS_WA 32 |
e1a73a54 | 477 | static u32 *gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
1212bd82 CW |
478 | { |
479 | int i; | |
480 | ||
5013eb8c CW |
481 | GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma); |
482 | GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); | |
483 | ||
484 | *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; | |
485 | *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; | |
486 | *cs++ = rq->fence.seqno; | |
487 | ||
488 | *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; | |
489 | *cs++ = I915_GEM_HWS_INDEX_ADDR | MI_FLUSH_DW_USE_GTT; | |
1212bd82 CW |
490 | *cs++ = rq->global_seqno; |
491 | ||
492 | for (i = 0; i < GEN7_XCS_WA; i++) { | |
493 | *cs++ = MI_STORE_DWORD_INDEX; | |
5013eb8c CW |
494 | *cs++ = I915_GEM_HWS_SEQNO_ADDR; |
495 | *cs++ = rq->fence.seqno; | |
1212bd82 CW |
496 | } |
497 | ||
498 | *cs++ = MI_FLUSH_DW; | |
499 | *cs++ = 0; | |
500 | *cs++ = 0; | |
501 | ||
502 | *cs++ = MI_USER_INTERRUPT; | |
1212bd82 CW |
503 | |
504 | rq->tail = intel_ring_offset(rq, cs); | |
505 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
506 | |
507 | return cs; | |
1212bd82 | 508 | } |
1212bd82 CW |
509 | #undef GEN7_XCS_WA |
510 | ||
060f2322 CW |
511 | static void set_hwstam(struct intel_engine_cs *engine, u32 mask) |
512 | { | |
513 | /* | |
514 | * Keep the render interrupt unmasked as this papers over | |
515 | * lost interrupts following a reset. | |
516 | */ | |
517 | if (engine->class == RENDER_CLASS) { | |
518 | if (INTEL_GEN(engine->i915) >= 6) | |
519 | mask &= ~BIT(0); | |
520 | else | |
521 | mask &= ~I915_USER_INTERRUPT; | |
522 | } | |
523 | ||
524 | intel_engine_set_hwsp_writemask(engine, mask); | |
525 | } | |
526 | ||
527 | static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys) | |
035dc1e0 | 528 | { |
c033666a | 529 | struct drm_i915_private *dev_priv = engine->i915; |
035dc1e0 DV |
530 | u32 addr; |
531 | ||
d6acae36 | 532 | addr = lower_32_bits(phys); |
c033666a | 533 | if (INTEL_GEN(dev_priv) >= 4) |
d6acae36 CW |
534 | addr |= (phys >> 28) & 0xf0; |
535 | ||
035dc1e0 DV |
536 | I915_WRITE(HWS_PGA, addr); |
537 | } | |
538 | ||
0ca88ba0 | 539 | static struct page *status_page(struct intel_engine_cs *engine) |
060f2322 | 540 | { |
0ca88ba0 | 541 | struct drm_i915_gem_object *obj = engine->status_page.vma->obj; |
060f2322 | 542 | |
0ca88ba0 CW |
543 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); |
544 | return sg_page(obj->mm.pages->sgl); | |
545 | } | |
546 | ||
547 | static void ring_setup_phys_status_page(struct intel_engine_cs *engine) | |
548 | { | |
549 | set_hws_pga(engine, PFN_PHYS(page_to_pfn(status_page(engine)))); | |
060f2322 CW |
550 | set_hwstam(engine, ~0u); |
551 | } | |
552 | ||
553 | static void set_hwsp(struct intel_engine_cs *engine, u32 offset) | |
af75f269 | 554 | { |
c033666a | 555 | struct drm_i915_private *dev_priv = engine->i915; |
060f2322 | 556 | i915_reg_t hwsp; |
af75f269 | 557 | |
060f2322 CW |
558 | /* |
559 | * The ring status page addresses are no longer next to the rest of | |
af75f269 DL |
560 | * the ring registers as of gen7. |
561 | */ | |
cf819eff | 562 | if (IS_GEN(dev_priv, 7)) { |
0bc40be8 | 563 | switch (engine->id) { |
a2d3d265 MT |
564 | /* |
565 | * No more rings exist on Gen7. Default case is only to shut up | |
566 | * gcc switch check warning. | |
567 | */ | |
568 | default: | |
569 | GEM_BUG_ON(engine->id); | |
af75f269 | 570 | case RCS: |
060f2322 | 571 | hwsp = RENDER_HWS_PGA_GEN7; |
af75f269 DL |
572 | break; |
573 | case BCS: | |
060f2322 | 574 | hwsp = BLT_HWS_PGA_GEN7; |
af75f269 | 575 | break; |
af75f269 | 576 | case VCS: |
060f2322 | 577 | hwsp = BSD_HWS_PGA_GEN7; |
af75f269 DL |
578 | break; |
579 | case VECS: | |
060f2322 | 580 | hwsp = VEBOX_HWS_PGA_GEN7; |
af75f269 DL |
581 | break; |
582 | } | |
cf819eff | 583 | } else if (IS_GEN(dev_priv, 6)) { |
060f2322 | 584 | hwsp = RING_HWS_PGA_GEN6(engine->mmio_base); |
af75f269 | 585 | } else { |
060f2322 | 586 | hwsp = RING_HWS_PGA(engine->mmio_base); |
a4a71701 | 587 | } |
c5498089 | 588 | |
060f2322 CW |
589 | I915_WRITE(hwsp, offset); |
590 | POSTING_READ(hwsp); | |
591 | } | |
af75f269 | 592 | |
060f2322 CW |
593 | static void flush_cs_tlb(struct intel_engine_cs *engine) |
594 | { | |
595 | struct drm_i915_private *dev_priv = engine->i915; | |
596 | i915_reg_t instpm = RING_INSTPM(engine->mmio_base); | |
597 | ||
598 | if (!IS_GEN_RANGE(dev_priv, 6, 7)) | |
599 | return; | |
600 | ||
601 | /* ring should be idle before issuing a sync flush*/ | |
602 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); | |
603 | ||
604 | I915_WRITE(instpm, | |
605 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
606 | INSTPM_SYNC_FLUSH)); | |
607 | if (intel_wait_for_register(dev_priv, | |
608 | instpm, INSTPM_SYNC_FLUSH, 0, | |
609 | 1000)) | |
610 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", | |
611 | engine->name); | |
612 | } | |
af75f269 | 613 | |
060f2322 CW |
614 | static void ring_setup_status_page(struct intel_engine_cs *engine) |
615 | { | |
0ca88ba0 | 616 | set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma)); |
060f2322 | 617 | set_hwstam(engine, ~0u); |
af75f269 | 618 | |
060f2322 | 619 | flush_cs_tlb(engine); |
af75f269 DL |
620 | } |
621 | ||
0bc40be8 | 622 | static bool stop_ring(struct intel_engine_cs *engine) |
8187a2b7 | 623 | { |
c033666a | 624 | struct drm_i915_private *dev_priv = engine->i915; |
8187a2b7 | 625 | |
21a2c58a | 626 | if (INTEL_GEN(dev_priv) > 2) { |
0bc40be8 | 627 | I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); |
3d808eb1 CW |
628 | if (intel_wait_for_register(dev_priv, |
629 | RING_MI_MODE(engine->mmio_base), | |
630 | MODE_IDLE, | |
631 | MODE_IDLE, | |
632 | 1000)) { | |
0bc40be8 TU |
633 | DRM_ERROR("%s : timed out trying to stop ring\n", |
634 | engine->name); | |
9bec9b13 CW |
635 | /* Sometimes we observe that the idle flag is not |
636 | * set even though the ring is empty. So double | |
637 | * check before giving up. | |
638 | */ | |
0bc40be8 | 639 | if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine)) |
9bec9b13 | 640 | return false; |
9991ae78 CW |
641 | } |
642 | } | |
b7884eb4 | 643 | |
11caf551 CW |
644 | I915_WRITE_HEAD(engine, I915_READ_TAIL(engine)); |
645 | ||
0bc40be8 | 646 | I915_WRITE_HEAD(engine, 0); |
c5efa1ad | 647 | I915_WRITE_TAIL(engine, 0); |
8187a2b7 | 648 | |
11caf551 CW |
649 | /* The ring must be empty before it is disabled */ |
650 | I915_WRITE_CTL(engine, 0); | |
651 | ||
0bc40be8 | 652 | return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0; |
9991ae78 | 653 | } |
8187a2b7 | 654 | |
0bc40be8 | 655 | static int init_ring_common(struct intel_engine_cs *engine) |
9991ae78 | 656 | { |
c033666a | 657 | struct drm_i915_private *dev_priv = engine->i915; |
7e37f889 | 658 | struct intel_ring *ring = engine->buffer; |
9991ae78 CW |
659 | int ret = 0; |
660 | ||
59bad947 | 661 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
9991ae78 | 662 | |
0bc40be8 | 663 | if (!stop_ring(engine)) { |
9991ae78 | 664 | /* G45 ring initialization often fails to reset head to zero */ |
8177e112 CW |
665 | DRM_DEBUG_DRIVER("%s head not reset to zero " |
666 | "ctl %08x head %08x tail %08x start %08x\n", | |
667 | engine->name, | |
668 | I915_READ_CTL(engine), | |
669 | I915_READ_HEAD(engine), | |
670 | I915_READ_TAIL(engine), | |
671 | I915_READ_START(engine)); | |
8187a2b7 | 672 | |
0bc40be8 | 673 | if (!stop_ring(engine)) { |
6fd0d56e CW |
674 | DRM_ERROR("failed to set %s head to zero " |
675 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
676 | engine->name, |
677 | I915_READ_CTL(engine), | |
678 | I915_READ_HEAD(engine), | |
679 | I915_READ_TAIL(engine), | |
680 | I915_READ_START(engine)); | |
9991ae78 CW |
681 | ret = -EIO; |
682 | goto out; | |
6fd0d56e | 683 | } |
8187a2b7 ZN |
684 | } |
685 | ||
3177659a | 686 | if (HWS_NEEDS_PHYSICAL(dev_priv)) |
0bc40be8 | 687 | ring_setup_phys_status_page(engine); |
3177659a | 688 | else |
060f2322 | 689 | ring_setup_status_page(engine); |
9991ae78 | 690 | |
ad07dfcd | 691 | intel_engine_reset_breadcrumbs(engine); |
821ed7df | 692 | |
ece4a17d | 693 | /* Enforce ordering by reading HEAD register back */ |
0bc40be8 | 694 | I915_READ_HEAD(engine); |
ece4a17d | 695 | |
0d8957c8 DV |
696 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
697 | * registers with the above sequence (the readback of the HEAD registers | |
698 | * also enforces ordering), otherwise the hw might lose the new ring | |
699 | * register values. */ | |
bde13ebd | 700 | I915_WRITE_START(engine, i915_ggtt_offset(ring->vma)); |
95468892 CW |
701 | |
702 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ | |
0bc40be8 | 703 | if (I915_READ_HEAD(engine)) |
8177e112 CW |
704 | DRM_DEBUG_DRIVER("%s initialization failed [head=%08x], fudging\n", |
705 | engine->name, I915_READ_HEAD(engine)); | |
821ed7df | 706 | |
41d37680 CW |
707 | /* Check that the ring offsets point within the ring! */ |
708 | GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head)); | |
709 | GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail)); | |
821ed7df | 710 | intel_ring_update_space(ring); |
b7f21899 CW |
711 | |
712 | /* First wake the ring up to an empty/idle ring */ | |
821ed7df | 713 | I915_WRITE_HEAD(engine, ring->head); |
b7f21899 | 714 | I915_WRITE_TAIL(engine, ring->head); |
821ed7df | 715 | (void)I915_READ_TAIL(engine); |
95468892 | 716 | |
62ae14b1 | 717 | I915_WRITE_CTL(engine, RING_CTL_SIZE(ring->size) | RING_VALID); |
8187a2b7 | 718 | |
8187a2b7 | 719 | /* If the head is still not zero, the ring is dead */ |
f42bb651 CW |
720 | if (intel_wait_for_register(dev_priv, RING_CTL(engine->mmio_base), |
721 | RING_VALID, RING_VALID, | |
722 | 50)) { | |
e74cfed5 | 723 | DRM_ERROR("%s initialization failed " |
821ed7df | 724 | "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n", |
0bc40be8 TU |
725 | engine->name, |
726 | I915_READ_CTL(engine), | |
727 | I915_READ_CTL(engine) & RING_VALID, | |
821ed7df CW |
728 | I915_READ_HEAD(engine), ring->head, |
729 | I915_READ_TAIL(engine), ring->tail, | |
0bc40be8 | 730 | I915_READ_START(engine), |
bde13ebd | 731 | i915_ggtt_offset(ring->vma)); |
b7884eb4 DV |
732 | ret = -EIO; |
733 | goto out; | |
8187a2b7 ZN |
734 | } |
735 | ||
7836cd02 CW |
736 | if (INTEL_GEN(dev_priv) > 2) |
737 | I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); | |
738 | ||
b7f21899 CW |
739 | /* Now awake, let it get started */ |
740 | if (ring->tail != ring->head) { | |
741 | I915_WRITE_TAIL(engine, ring->tail); | |
742 | (void)I915_READ_TAIL(engine); | |
743 | } | |
744 | ||
d6fee0de | 745 | /* Papering over lost _interrupts_ immediately following the restart */ |
52c0fdb2 | 746 | intel_engine_queue_breadcrumbs(engine); |
b7884eb4 | 747 | out: |
59bad947 | 748 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
749 | |
750 | return ret; | |
8187a2b7 ZN |
751 | } |
752 | ||
eb8d0f5a | 753 | static void reset_prepare(struct intel_engine_cs *engine) |
821ed7df | 754 | { |
3f6e9822 | 755 | intel_engine_stop_cs(engine); |
5adfb772 CW |
756 | } |
757 | ||
eb8d0f5a | 758 | static void reset_ring(struct intel_engine_cs *engine, bool stalled) |
5adfb772 | 759 | { |
eb8d0f5a CW |
760 | struct i915_timeline *tl = &engine->timeline; |
761 | struct i915_request *pos, *rq; | |
762 | unsigned long flags; | |
b3ee09a4 | 763 | u32 head; |
5adfb772 | 764 | |
eb8d0f5a CW |
765 | rq = NULL; |
766 | spin_lock_irqsave(&tl->lock, flags); | |
767 | list_for_each_entry(pos, &tl->requests, link) { | |
5013eb8c | 768 | if (!i915_request_completed(pos)) { |
eb8d0f5a CW |
769 | rq = pos; |
770 | break; | |
771 | } | |
b3ee09a4 | 772 | } |
67e64564 | 773 | |
eb8d0f5a CW |
774 | GEM_TRACE("%s seqno=%d, current=%d, stalled? %s\n", |
775 | engine->name, | |
776 | rq ? rq->global_seqno : 0, | |
777 | intel_engine_get_seqno(engine), | |
778 | yesno(stalled)); | |
67e64564 | 779 | /* |
eb8d0f5a | 780 | * The guilty request will get skipped on a hung engine. |
c0dcb203 | 781 | * |
eb8d0f5a CW |
782 | * Users of client default contexts do not rely on logical |
783 | * state preserved between batches so it is safe to execute | |
784 | * queued requests following the hang. Non default contexts | |
785 | * rely on preserved state, so skipping a batch loses the | |
786 | * evolution of the state and it needs to be considered corrupted. | |
787 | * Executing more queued batches on top of corrupted state is | |
788 | * risky. But we take the risk by trying to advance through | |
789 | * the queued requests in order to make the client behaviour | |
790 | * more predictable around resets, by not throwing away random | |
791 | * amount of batches it has prepared for execution. Sophisticated | |
792 | * clients can use gem_reset_stats_ioctl and dma fence status | |
793 | * (exported via sync_file info ioctl on explicit fences) to observe | |
794 | * when it loses the context state and should rebuild accordingly. | |
c0dcb203 | 795 | * |
eb8d0f5a CW |
796 | * The context ban, and ultimately the client ban, mechanism are safety |
797 | * valves if client submission ends up resulting in nothing more than | |
798 | * subsequent hangs. | |
c0dcb203 | 799 | */ |
eb8d0f5a | 800 | |
b3ee09a4 | 801 | if (rq) { |
eb8d0f5a CW |
802 | /* |
803 | * Try to restore the logical GPU state to match the | |
804 | * continuation of the request queue. If we skip the | |
805 | * context/PD restore, then the next request may try to execute | |
806 | * assuming that its context is valid and loaded on the GPU and | |
807 | * so may try to access invalid memory, prompting repeated GPU | |
808 | * hangs. | |
809 | * | |
810 | * If the request was guilty, we still restore the logical | |
811 | * state in case the next request requires it (e.g. the | |
812 | * aliasing ppgtt), but skip over the hung batch. | |
813 | * | |
814 | * If the request was innocent, we try to replay the request | |
815 | * with the restored context. | |
816 | */ | |
817 | i915_reset_request(rq, stalled); | |
818 | ||
819 | GEM_BUG_ON(rq->ring != engine->buffer); | |
820 | head = rq->head; | |
821 | } else { | |
822 | head = engine->buffer->tail; | |
c0dcb203 | 823 | } |
eb8d0f5a CW |
824 | engine->buffer->head = intel_ring_wrap(engine->buffer, head); |
825 | ||
826 | spin_unlock_irqrestore(&tl->lock, flags); | |
821ed7df CW |
827 | } |
828 | ||
5adfb772 CW |
829 | static void reset_finish(struct intel_engine_cs *engine) |
830 | { | |
831 | } | |
832 | ||
e61e0f51 | 833 | static int intel_rcs_ctx_init(struct i915_request *rq) |
8f0e2b9d DV |
834 | { |
835 | int ret; | |
836 | ||
452420d2 | 837 | ret = intel_engine_emit_ctx_wa(rq); |
8f0e2b9d DV |
838 | if (ret != 0) |
839 | return ret; | |
840 | ||
e61e0f51 | 841 | ret = i915_gem_render_state_emit(rq); |
8f0e2b9d | 842 | if (ret) |
e26e1b97 | 843 | return ret; |
8f0e2b9d | 844 | |
e26e1b97 | 845 | return 0; |
8f0e2b9d DV |
846 | } |
847 | ||
0bc40be8 | 848 | static int init_render_ring(struct intel_engine_cs *engine) |
8187a2b7 | 849 | { |
c033666a | 850 | struct drm_i915_private *dev_priv = engine->i915; |
0bc40be8 | 851 | int ret = init_ring_common(engine); |
9c33baa6 KZ |
852 | if (ret) |
853 | return ret; | |
a69ffdbf | 854 | |
61a563a2 | 855 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
00690008 | 856 | if (IS_GEN_RANGE(dev_priv, 4, 6)) |
6b26c86d | 857 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
858 | |
859 | /* We need to disable the AsyncFlip performance optimisations in order | |
860 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
861 | * programmed to '1' on all products. | |
8693a824 | 862 | * |
2441f877 | 863 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv |
1c8c38c5 | 864 | */ |
00690008 | 865 | if (IS_GEN_RANGE(dev_priv, 6, 7)) |
1c8c38c5 CW |
866 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
867 | ||
f05bb0c7 | 868 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 869 | /* WaEnableFlushTlbInvalidationMode:snb */ |
cf819eff | 870 | if (IS_GEN(dev_priv, 6)) |
f05bb0c7 | 871 | I915_WRITE(GFX_MODE, |
aa83e30d | 872 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 873 | |
01fa0302 | 874 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
cf819eff | 875 | if (IS_GEN(dev_priv, 7)) |
1c8c38c5 | 876 | I915_WRITE(GFX_MODE_GEN7, |
01fa0302 | 877 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 878 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 879 | |
cf819eff | 880 | if (IS_GEN(dev_priv, 6)) { |
3a69ddd6 KG |
881 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
882 | * "If this bit is set, STCunit will have LRA as replacement | |
883 | * policy. [...] This bit must be reset. LRA replacement | |
884 | * policy is not supported." | |
885 | */ | |
886 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 887 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
888 | } |
889 | ||
00690008 | 890 | if (IS_GEN_RANGE(dev_priv, 6, 7)) |
6b26c86d | 891 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
84f9f938 | 892 | |
c56b89f1 | 893 | if (INTEL_GEN(dev_priv) >= 6) |
035ea405 | 894 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
15b9f80e | 895 | |
59b449d5 | 896 | return 0; |
8187a2b7 ZN |
897 | } |
898 | ||
27a5f61b CW |
899 | static void cancel_requests(struct intel_engine_cs *engine) |
900 | { | |
e61e0f51 | 901 | struct i915_request *request; |
27a5f61b CW |
902 | unsigned long flags; |
903 | ||
a89d1f92 | 904 | spin_lock_irqsave(&engine->timeline.lock, flags); |
27a5f61b CW |
905 | |
906 | /* Mark all submitted requests as skipped. */ | |
a89d1f92 | 907 | list_for_each_entry(request, &engine->timeline.requests, link) { |
27a5f61b | 908 | GEM_BUG_ON(!request->global_seqno); |
3800960a | 909 | |
5013eb8c CW |
910 | if (!i915_request_signaled(request)) |
911 | dma_fence_set_error(&request->fence, -EIO); | |
3800960a | 912 | |
5013eb8c | 913 | i915_request_mark_complete(request); |
27a5f61b | 914 | } |
3800960a CW |
915 | |
916 | intel_write_status_page(engine, | |
917 | I915_GEM_HWS_INDEX, | |
918 | intel_engine_last_submit(engine)); | |
919 | ||
27a5f61b CW |
920 | /* Remaining _unready_ requests will be nop'ed when submitted */ |
921 | ||
a89d1f92 | 922 | spin_unlock_irqrestore(&engine->timeline.lock, flags); |
27a5f61b CW |
923 | } |
924 | ||
e61e0f51 | 925 | static void i9xx_submit_request(struct i915_request *request) |
b0411e7d CW |
926 | { |
927 | struct drm_i915_private *dev_priv = request->i915; | |
928 | ||
e61e0f51 | 929 | i915_request_submit(request); |
d55ac5bf | 930 | |
e6ba9992 CW |
931 | I915_WRITE_TAIL(request->engine, |
932 | intel_ring_set_tail(request->ring, request->tail)); | |
b0411e7d CW |
933 | } |
934 | ||
e1a73a54 | 935 | static u32 *i9xx_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
1ec14ad3 | 936 | { |
5013eb8c CW |
937 | GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma); |
938 | GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); | |
939 | ||
caa5915b CW |
940 | *cs++ = MI_FLUSH; |
941 | ||
5013eb8c CW |
942 | *cs++ = MI_STORE_DWORD_INDEX; |
943 | *cs++ = I915_GEM_HWS_SEQNO_ADDR; | |
944 | *cs++ = rq->fence.seqno; | |
945 | ||
73dec95e | 946 | *cs++ = MI_STORE_DWORD_INDEX; |
caa5915b | 947 | *cs++ = I915_GEM_HWS_INDEX_ADDR; |
e61e0f51 | 948 | *cs++ = rq->global_seqno; |
caa5915b | 949 | |
73dec95e | 950 | *cs++ = MI_USER_INTERRUPT; |
1ec14ad3 | 951 | |
e61e0f51 CW |
952 | rq->tail = intel_ring_offset(rq, cs); |
953 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
954 | |
955 | return cs; | |
1ec14ad3 | 956 | } |
98f29e8d | 957 | |
835051d3 | 958 | #define GEN5_WA_STORES 8 /* must be at least 1! */ |
e1a73a54 | 959 | static u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
c6df541c | 960 | { |
835051d3 CW |
961 | int i; |
962 | ||
5013eb8c CW |
963 | GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma); |
964 | GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); | |
965 | ||
835051d3 CW |
966 | *cs++ = MI_FLUSH; |
967 | ||
5013eb8c CW |
968 | *cs++ = MI_STORE_DWORD_INDEX; |
969 | *cs++ = I915_GEM_HWS_SEQNO_ADDR; | |
970 | *cs++ = rq->fence.seqno; | |
971 | ||
835051d3 CW |
972 | BUILD_BUG_ON(GEN5_WA_STORES < 1); |
973 | for (i = 0; i < GEN5_WA_STORES; i++) { | |
974 | *cs++ = MI_STORE_DWORD_INDEX; | |
975 | *cs++ = I915_GEM_HWS_INDEX_ADDR; | |
976 | *cs++ = rq->global_seqno; | |
977 | } | |
978 | ||
979 | *cs++ = MI_USER_INTERRUPT; | |
5013eb8c | 980 | *cs++ = MI_NOOP; |
835051d3 CW |
981 | |
982 | rq->tail = intel_ring_offset(rq, cs); | |
983 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
984 | |
985 | return cs; | |
c6df541c | 986 | } |
835051d3 | 987 | #undef GEN5_WA_STORES |
c6df541c | 988 | |
31bb59cc CW |
989 | static void |
990 | gen5_irq_enable(struct intel_engine_cs *engine) | |
e48d8634 | 991 | { |
31bb59cc | 992 | gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
993 | } |
994 | ||
995 | static void | |
31bb59cc | 996 | gen5_irq_disable(struct intel_engine_cs *engine) |
e48d8634 | 997 | { |
31bb59cc | 998 | gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
999 | } |
1000 | ||
31bb59cc CW |
1001 | static void |
1002 | i9xx_irq_enable(struct intel_engine_cs *engine) | |
62fdfeaf | 1003 | { |
c033666a | 1004 | struct drm_i915_private *dev_priv = engine->i915; |
b13c2b96 | 1005 | |
31bb59cc CW |
1006 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
1007 | I915_WRITE(IMR, dev_priv->irq_mask); | |
1008 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
62fdfeaf EA |
1009 | } |
1010 | ||
8187a2b7 | 1011 | static void |
31bb59cc | 1012 | i9xx_irq_disable(struct intel_engine_cs *engine) |
62fdfeaf | 1013 | { |
c033666a | 1014 | struct drm_i915_private *dev_priv = engine->i915; |
62fdfeaf | 1015 | |
31bb59cc CW |
1016 | dev_priv->irq_mask |= engine->irq_enable_mask; |
1017 | I915_WRITE(IMR, dev_priv->irq_mask); | |
62fdfeaf EA |
1018 | } |
1019 | ||
31bb59cc CW |
1020 | static void |
1021 | i8xx_irq_enable(struct intel_engine_cs *engine) | |
c2798b19 | 1022 | { |
c033666a | 1023 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 1024 | |
31bb59cc CW |
1025 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
1026 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
1027 | POSTING_READ16(RING_IMR(engine->mmio_base)); | |
c2798b19 CW |
1028 | } |
1029 | ||
1030 | static void | |
31bb59cc | 1031 | i8xx_irq_disable(struct intel_engine_cs *engine) |
c2798b19 | 1032 | { |
c033666a | 1033 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 1034 | |
31bb59cc CW |
1035 | dev_priv->irq_mask |= engine->irq_enable_mask; |
1036 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
c2798b19 CW |
1037 | } |
1038 | ||
b72f3acb | 1039 | static int |
e61e0f51 | 1040 | bsd_ring_flush(struct i915_request *rq, u32 mode) |
d1b851fc | 1041 | { |
73dec95e | 1042 | u32 *cs; |
b72f3acb | 1043 | |
e61e0f51 | 1044 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
1045 | if (IS_ERR(cs)) |
1046 | return PTR_ERR(cs); | |
b72f3acb | 1047 | |
73dec95e TU |
1048 | *cs++ = MI_FLUSH; |
1049 | *cs++ = MI_NOOP; | |
e61e0f51 | 1050 | intel_ring_advance(rq, cs); |
b72f3acb | 1051 | return 0; |
d1b851fc ZN |
1052 | } |
1053 | ||
31bb59cc CW |
1054 | static void |
1055 | gen6_irq_enable(struct intel_engine_cs *engine) | |
0f46832f | 1056 | { |
c033666a | 1057 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 1058 | |
61ff75ac CW |
1059 | I915_WRITE_IMR(engine, |
1060 | ~(engine->irq_enable_mask | | |
1061 | engine->irq_keep_mask)); | |
476af9c2 CW |
1062 | |
1063 | /* Flush/delay to ensure the RING_IMR is active before the GT IMR */ | |
1064 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
1065 | ||
31bb59cc | 1066 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); |
0f46832f CW |
1067 | } |
1068 | ||
1069 | static void | |
31bb59cc | 1070 | gen6_irq_disable(struct intel_engine_cs *engine) |
0f46832f | 1071 | { |
c033666a | 1072 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 1073 | |
61ff75ac | 1074 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
31bb59cc | 1075 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); |
d1b851fc ZN |
1076 | } |
1077 | ||
31bb59cc CW |
1078 | static void |
1079 | hsw_vebox_irq_enable(struct intel_engine_cs *engine) | |
a19d2933 | 1080 | { |
c033666a | 1081 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 1082 | |
31bb59cc | 1083 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
e4fc69f2 CW |
1084 | |
1085 | /* Flush/delay to ensure the RING_IMR is active before the GT IMR */ | |
1086 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
1087 | ||
f4e9af4f | 1088 | gen6_unmask_pm_irq(dev_priv, engine->irq_enable_mask); |
a19d2933 BW |
1089 | } |
1090 | ||
1091 | static void | |
31bb59cc | 1092 | hsw_vebox_irq_disable(struct intel_engine_cs *engine) |
a19d2933 | 1093 | { |
c033666a | 1094 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 1095 | |
31bb59cc | 1096 | I915_WRITE_IMR(engine, ~0); |
f4e9af4f | 1097 | gen6_mask_pm_irq(dev_priv, engine->irq_enable_mask); |
a19d2933 BW |
1098 | } |
1099 | ||
d1b851fc | 1100 | static int |
e61e0f51 | 1101 | i965_emit_bb_start(struct i915_request *rq, |
803688ba CW |
1102 | u64 offset, u32 length, |
1103 | unsigned int dispatch_flags) | |
d1b851fc | 1104 | { |
73dec95e | 1105 | u32 *cs; |
78501eac | 1106 | |
e61e0f51 | 1107 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
1108 | if (IS_ERR(cs)) |
1109 | return PTR_ERR(cs); | |
e1f99ce6 | 1110 | |
73dec95e TU |
1111 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | (dispatch_flags & |
1112 | I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965); | |
1113 | *cs++ = offset; | |
e61e0f51 | 1114 | intel_ring_advance(rq, cs); |
78501eac | 1115 | |
d1b851fc ZN |
1116 | return 0; |
1117 | } | |
1118 | ||
b45305fc | 1119 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
51797499 | 1120 | #define I830_BATCH_LIMIT SZ_256K |
c4d69da1 CW |
1121 | #define I830_TLB_ENTRIES (2) |
1122 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) | |
8187a2b7 | 1123 | static int |
e61e0f51 | 1124 | i830_emit_bb_start(struct i915_request *rq, |
803688ba CW |
1125 | u64 offset, u32 len, |
1126 | unsigned int dispatch_flags) | |
62fdfeaf | 1127 | { |
51797499 CW |
1128 | u32 *cs, cs_offset = i915_scratch_offset(rq->i915); |
1129 | ||
1130 | GEM_BUG_ON(rq->i915->gt.scratch->size < I830_WA_SIZE); | |
62fdfeaf | 1131 | |
e61e0f51 | 1132 | cs = intel_ring_begin(rq, 6); |
73dec95e TU |
1133 | if (IS_ERR(cs)) |
1134 | return PTR_ERR(cs); | |
62fdfeaf | 1135 | |
c4d69da1 | 1136 | /* Evict the invalid PTE TLBs */ |
73dec95e TU |
1137 | *cs++ = COLOR_BLT_CMD | BLT_WRITE_RGBA; |
1138 | *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096; | |
1139 | *cs++ = I830_TLB_ENTRIES << 16 | 4; /* load each page */ | |
1140 | *cs++ = cs_offset; | |
1141 | *cs++ = 0xdeadbeef; | |
1142 | *cs++ = MI_NOOP; | |
e61e0f51 | 1143 | intel_ring_advance(rq, cs); |
b45305fc | 1144 | |
8e004efc | 1145 | if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { |
b45305fc DV |
1146 | if (len > I830_BATCH_LIMIT) |
1147 | return -ENOSPC; | |
1148 | ||
e61e0f51 | 1149 | cs = intel_ring_begin(rq, 6 + 2); |
73dec95e TU |
1150 | if (IS_ERR(cs)) |
1151 | return PTR_ERR(cs); | |
c4d69da1 CW |
1152 | |
1153 | /* Blit the batch (which has now all relocs applied) to the | |
1154 | * stable batch scratch bo area (so that the CS never | |
1155 | * stumbles over its tlb invalidation bug) ... | |
1156 | */ | |
73dec95e TU |
1157 | *cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA; |
1158 | *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096; | |
1159 | *cs++ = DIV_ROUND_UP(len, 4096) << 16 | 4096; | |
1160 | *cs++ = cs_offset; | |
1161 | *cs++ = 4096; | |
1162 | *cs++ = offset; | |
1163 | ||
1164 | *cs++ = MI_FLUSH; | |
1165 | *cs++ = MI_NOOP; | |
e61e0f51 | 1166 | intel_ring_advance(rq, cs); |
b45305fc DV |
1167 | |
1168 | /* ... and execute it. */ | |
c4d69da1 | 1169 | offset = cs_offset; |
b45305fc | 1170 | } |
e1f99ce6 | 1171 | |
e61e0f51 | 1172 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
1173 | if (IS_ERR(cs)) |
1174 | return PTR_ERR(cs); | |
c4d69da1 | 1175 | |
73dec95e TU |
1176 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; |
1177 | *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 : | |
1178 | MI_BATCH_NON_SECURE); | |
e61e0f51 | 1179 | intel_ring_advance(rq, cs); |
c4d69da1 | 1180 | |
fb3256da DV |
1181 | return 0; |
1182 | } | |
1183 | ||
1184 | static int | |
e61e0f51 | 1185 | i915_emit_bb_start(struct i915_request *rq, |
803688ba CW |
1186 | u64 offset, u32 len, |
1187 | unsigned int dispatch_flags) | |
fb3256da | 1188 | { |
73dec95e | 1189 | u32 *cs; |
fb3256da | 1190 | |
e61e0f51 | 1191 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
1192 | if (IS_ERR(cs)) |
1193 | return PTR_ERR(cs); | |
fb3256da | 1194 | |
73dec95e TU |
1195 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; |
1196 | *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 : | |
1197 | MI_BATCH_NON_SECURE); | |
e61e0f51 | 1198 | intel_ring_advance(rq, cs); |
62fdfeaf | 1199 | |
62fdfeaf EA |
1200 | return 0; |
1201 | } | |
1202 | ||
5503cb0d | 1203 | int intel_ring_pin(struct intel_ring *ring) |
7ba717cf | 1204 | { |
57e88531 | 1205 | struct i915_vma *vma = ring->vma; |
89d5efcc | 1206 | enum i915_map_type map = i915_coherent_map_type(vma->vm->i915); |
d822bb18 | 1207 | unsigned int flags; |
8305216f | 1208 | void *addr; |
7ba717cf TD |
1209 | int ret; |
1210 | ||
57e88531 | 1211 | GEM_BUG_ON(ring->vaddr); |
7ba717cf | 1212 | |
5013eb8c CW |
1213 | ret = i915_timeline_pin(ring->timeline); |
1214 | if (ret) | |
1215 | return ret; | |
1216 | ||
d3ef1af6 | 1217 | flags = PIN_GLOBAL; |
496bcce3 JB |
1218 | |
1219 | /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ | |
1220 | flags |= PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma); | |
1221 | ||
9d80841e | 1222 | if (vma->obj->stolen) |
57e88531 | 1223 | flags |= PIN_MAPPABLE; |
2edd4e69 CW |
1224 | else |
1225 | flags |= PIN_HIGH; | |
def0c5f6 | 1226 | |
57e88531 | 1227 | if (!(vma->flags & I915_VMA_GLOBAL_BIND)) { |
9d80841e | 1228 | if (flags & PIN_MAPPABLE || map == I915_MAP_WC) |
57e88531 CW |
1229 | ret = i915_gem_object_set_to_gtt_domain(vma->obj, true); |
1230 | else | |
1231 | ret = i915_gem_object_set_to_cpu_domain(vma->obj, true); | |
1232 | if (unlikely(ret)) | |
5013eb8c | 1233 | goto unpin_timeline; |
57e88531 | 1234 | } |
7ba717cf | 1235 | |
7a859c65 | 1236 | ret = i915_vma_pin(vma, 0, 0, flags); |
57e88531 | 1237 | if (unlikely(ret)) |
5013eb8c | 1238 | goto unpin_timeline; |
def0c5f6 | 1239 | |
9d80841e | 1240 | if (i915_vma_is_map_and_fenceable(vma)) |
57e88531 CW |
1241 | addr = (void __force *)i915_vma_pin_iomap(vma); |
1242 | else | |
9d80841e | 1243 | addr = i915_gem_object_pin_map(vma->obj, map); |
5013eb8c CW |
1244 | if (IS_ERR(addr)) { |
1245 | ret = PTR_ERR(addr); | |
1246 | goto unpin_ring; | |
1247 | } | |
7ba717cf | 1248 | |
3d574a6b CW |
1249 | vma->obj->pin_global++; |
1250 | ||
32c04f16 | 1251 | ring->vaddr = addr; |
7ba717cf | 1252 | return 0; |
d2cad535 | 1253 | |
5013eb8c | 1254 | unpin_ring: |
57e88531 | 1255 | i915_vma_unpin(vma); |
5013eb8c CW |
1256 | unpin_timeline: |
1257 | i915_timeline_unpin(ring->timeline); | |
1258 | return ret; | |
7ba717cf TD |
1259 | } |
1260 | ||
e6ba9992 CW |
1261 | void intel_ring_reset(struct intel_ring *ring, u32 tail) |
1262 | { | |
41d37680 CW |
1263 | GEM_BUG_ON(!intel_ring_offset_valid(ring, tail)); |
1264 | ||
e6ba9992 CW |
1265 | ring->tail = tail; |
1266 | ring->head = tail; | |
1267 | ring->emit = tail; | |
1268 | intel_ring_update_space(ring); | |
1269 | } | |
1270 | ||
aad29fbb CW |
1271 | void intel_ring_unpin(struct intel_ring *ring) |
1272 | { | |
1273 | GEM_BUG_ON(!ring->vma); | |
1274 | GEM_BUG_ON(!ring->vaddr); | |
1275 | ||
e6ba9992 CW |
1276 | /* Discard any unused bytes beyond that submitted to hw. */ |
1277 | intel_ring_reset(ring, ring->tail); | |
1278 | ||
9d80841e | 1279 | if (i915_vma_is_map_and_fenceable(ring->vma)) |
aad29fbb | 1280 | i915_vma_unpin_iomap(ring->vma); |
57e88531 CW |
1281 | else |
1282 | i915_gem_object_unpin_map(ring->vma->obj); | |
aad29fbb CW |
1283 | ring->vaddr = NULL; |
1284 | ||
3d574a6b | 1285 | ring->vma->obj->pin_global--; |
57e88531 | 1286 | i915_vma_unpin(ring->vma); |
5013eb8c CW |
1287 | |
1288 | i915_timeline_unpin(ring->timeline); | |
2919d291 OM |
1289 | } |
1290 | ||
57e88531 CW |
1291 | static struct i915_vma * |
1292 | intel_ring_create_vma(struct drm_i915_private *dev_priv, int size) | |
62fdfeaf | 1293 | { |
250f8c81 | 1294 | struct i915_address_space *vm = &dev_priv->ggtt.vm; |
05394f39 | 1295 | struct drm_i915_gem_object *obj; |
57e88531 | 1296 | struct i915_vma *vma; |
62fdfeaf | 1297 | |
187685cb | 1298 | obj = i915_gem_object_create_stolen(dev_priv, size); |
c58b735f | 1299 | if (!obj) |
2d6c4c84 | 1300 | obj = i915_gem_object_create_internal(dev_priv, size); |
57e88531 CW |
1301 | if (IS_ERR(obj)) |
1302 | return ERR_CAST(obj); | |
8187a2b7 | 1303 | |
250f8c81 JB |
1304 | /* |
1305 | * Mark ring buffers as read-only from GPU side (so no stray overwrites) | |
1306 | * if supported by the platform's GGTT. | |
1307 | */ | |
1308 | if (vm->has_read_only) | |
3e977ac6 | 1309 | i915_gem_object_set_readonly(obj); |
24f3a8cf | 1310 | |
250f8c81 | 1311 | vma = i915_vma_instance(obj, vm, NULL); |
57e88531 CW |
1312 | if (IS_ERR(vma)) |
1313 | goto err; | |
1314 | ||
1315 | return vma; | |
e3efda49 | 1316 | |
57e88531 CW |
1317 | err: |
1318 | i915_gem_object_put(obj); | |
1319 | return vma; | |
e3efda49 CW |
1320 | } |
1321 | ||
7e37f889 | 1322 | struct intel_ring * |
65fcb806 | 1323 | intel_engine_create_ring(struct intel_engine_cs *engine, |
a89d1f92 | 1324 | struct i915_timeline *timeline, |
65fcb806 | 1325 | int size) |
01101fa7 | 1326 | { |
7e37f889 | 1327 | struct intel_ring *ring; |
57e88531 | 1328 | struct i915_vma *vma; |
01101fa7 | 1329 | |
8f942018 | 1330 | GEM_BUG_ON(!is_power_of_2(size)); |
62ae14b1 | 1331 | GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES); |
a89d1f92 | 1332 | GEM_BUG_ON(timeline == &engine->timeline); |
b887d615 | 1333 | lockdep_assert_held(&engine->i915->drm.struct_mutex); |
8f942018 | 1334 | |
01101fa7 | 1335 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
57e88531 | 1336 | if (!ring) |
01101fa7 CW |
1337 | return ERR_PTR(-ENOMEM); |
1338 | ||
675d9ad7 | 1339 | INIT_LIST_HEAD(&ring->request_list); |
a89d1f92 | 1340 | ring->timeline = i915_timeline_get(timeline); |
675d9ad7 | 1341 | |
01101fa7 CW |
1342 | ring->size = size; |
1343 | /* Workaround an erratum on the i830 which causes a hang if | |
1344 | * the TAIL pointer points to within the last 2 cachelines | |
1345 | * of the buffer. | |
1346 | */ | |
1347 | ring->effective_size = size; | |
2a307c2e | 1348 | if (IS_I830(engine->i915) || IS_I845G(engine->i915)) |
01101fa7 CW |
1349 | ring->effective_size -= 2 * CACHELINE_BYTES; |
1350 | ||
01101fa7 CW |
1351 | intel_ring_update_space(ring); |
1352 | ||
57e88531 CW |
1353 | vma = intel_ring_create_vma(engine->i915, size); |
1354 | if (IS_ERR(vma)) { | |
01101fa7 | 1355 | kfree(ring); |
57e88531 | 1356 | return ERR_CAST(vma); |
01101fa7 | 1357 | } |
57e88531 | 1358 | ring->vma = vma; |
01101fa7 CW |
1359 | |
1360 | return ring; | |
1361 | } | |
1362 | ||
1363 | void | |
7e37f889 | 1364 | intel_ring_free(struct intel_ring *ring) |
01101fa7 | 1365 | { |
f8a7fde4 CW |
1366 | struct drm_i915_gem_object *obj = ring->vma->obj; |
1367 | ||
1368 | i915_vma_close(ring->vma); | |
1369 | __i915_gem_object_release_unless_active(obj); | |
1370 | ||
a89d1f92 | 1371 | i915_timeline_put(ring->timeline); |
01101fa7 CW |
1372 | kfree(ring); |
1373 | } | |
1374 | ||
1fc44d9b CW |
1375 | static void intel_ring_context_destroy(struct intel_context *ce) |
1376 | { | |
1377 | GEM_BUG_ON(ce->pin_count); | |
1378 | ||
efe79d48 CW |
1379 | if (!ce->state) |
1380 | return; | |
1381 | ||
1382 | GEM_BUG_ON(i915_gem_object_is_active(ce->state->obj)); | |
1383 | i915_gem_object_put(ce->state->obj); | |
1fc44d9b CW |
1384 | } |
1385 | ||
a2bbf714 CW |
1386 | static int __context_pin_ppgtt(struct i915_gem_context *ctx) |
1387 | { | |
1388 | struct i915_hw_ppgtt *ppgtt; | |
1389 | int err = 0; | |
1390 | ||
1391 | ppgtt = ctx->ppgtt ?: ctx->i915->mm.aliasing_ppgtt; | |
1392 | if (ppgtt) | |
1393 | err = gen6_ppgtt_pin(ppgtt); | |
1394 | ||
1395 | return err; | |
1396 | } | |
1397 | ||
1398 | static void __context_unpin_ppgtt(struct i915_gem_context *ctx) | |
1399 | { | |
1400 | struct i915_hw_ppgtt *ppgtt; | |
1401 | ||
1402 | ppgtt = ctx->ppgtt ?: ctx->i915->mm.aliasing_ppgtt; | |
1403 | if (ppgtt) | |
1404 | gen6_ppgtt_unpin(ppgtt); | |
1405 | } | |
1406 | ||
1fc44d9b | 1407 | static int __context_pin(struct intel_context *ce) |
e8a9c58f | 1408 | { |
d901e8e6 CW |
1409 | struct i915_vma *vma; |
1410 | int err; | |
1411 | ||
1412 | vma = ce->state; | |
1413 | if (!vma) | |
1414 | return 0; | |
e8a9c58f | 1415 | |
f4e15af7 CW |
1416 | /* |
1417 | * Clear this page out of any CPU caches for coherent swap-in/out. | |
e8a9c58f CW |
1418 | * We only want to do this on the first bind so that we do not stall |
1419 | * on an active context (which by nature is already on the GPU). | |
1420 | */ | |
1421 | if (!(vma->flags & I915_VMA_GLOBAL_BIND)) { | |
d901e8e6 CW |
1422 | err = i915_gem_object_set_to_gtt_domain(vma->obj, true); |
1423 | if (err) | |
1424 | return err; | |
e8a9c58f CW |
1425 | } |
1426 | ||
7a859c65 | 1427 | err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH); |
d901e8e6 CW |
1428 | if (err) |
1429 | return err; | |
1430 | ||
1431 | /* | |
1432 | * And mark is as a globally pinned object to let the shrinker know | |
1433 | * it cannot reclaim the object until we release it. | |
1434 | */ | |
1435 | vma->obj->pin_global++; | |
1436 | ||
1437 | return 0; | |
1438 | } | |
1439 | ||
1440 | static void __context_unpin(struct intel_context *ce) | |
1441 | { | |
1442 | struct i915_vma *vma; | |
1443 | ||
1444 | vma = ce->state; | |
1445 | if (!vma) | |
1446 | return; | |
1447 | ||
1448 | vma->obj->pin_global--; | |
1449 | i915_vma_unpin(vma); | |
1450 | } | |
1451 | ||
1452 | static void intel_ring_context_unpin(struct intel_context *ce) | |
1453 | { | |
a2bbf714 | 1454 | __context_unpin_ppgtt(ce->gem_context); |
d901e8e6 CW |
1455 | __context_unpin(ce); |
1456 | ||
1457 | i915_gem_context_put(ce->gem_context); | |
e8a9c58f CW |
1458 | } |
1459 | ||
3204c343 CW |
1460 | static struct i915_vma * |
1461 | alloc_context_vma(struct intel_engine_cs *engine) | |
1462 | { | |
1463 | struct drm_i915_private *i915 = engine->i915; | |
1464 | struct drm_i915_gem_object *obj; | |
1465 | struct i915_vma *vma; | |
d2b4b979 | 1466 | int err; |
3204c343 | 1467 | |
63ffbcda | 1468 | obj = i915_gem_object_create(i915, engine->context_size); |
3204c343 CW |
1469 | if (IS_ERR(obj)) |
1470 | return ERR_CAST(obj); | |
1471 | ||
d2b4b979 CW |
1472 | if (engine->default_state) { |
1473 | void *defaults, *vaddr; | |
1474 | ||
1475 | vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); | |
1476 | if (IS_ERR(vaddr)) { | |
1477 | err = PTR_ERR(vaddr); | |
1478 | goto err_obj; | |
1479 | } | |
1480 | ||
1481 | defaults = i915_gem_object_pin_map(engine->default_state, | |
1482 | I915_MAP_WB); | |
1483 | if (IS_ERR(defaults)) { | |
1484 | err = PTR_ERR(defaults); | |
1485 | goto err_map; | |
1486 | } | |
1487 | ||
1488 | memcpy(vaddr, defaults, engine->context_size); | |
1489 | ||
1490 | i915_gem_object_unpin_map(engine->default_state); | |
1491 | i915_gem_object_unpin_map(obj); | |
1492 | } | |
1493 | ||
3204c343 CW |
1494 | /* |
1495 | * Try to make the context utilize L3 as well as LLC. | |
1496 | * | |
1497 | * On VLV we don't have L3 controls in the PTEs so we | |
1498 | * shouldn't touch the cache level, especially as that | |
1499 | * would make the object snooped which might have a | |
1500 | * negative performance impact. | |
1501 | * | |
1502 | * Snooping is required on non-llc platforms in execlist | |
1503 | * mode, but since all GGTT accesses use PAT entry 0 we | |
1504 | * get snooping anyway regardless of cache_level. | |
1505 | * | |
1506 | * This is only applicable for Ivy Bridge devices since | |
1507 | * later platforms don't have L3 control bits in the PTE. | |
1508 | */ | |
1509 | if (IS_IVYBRIDGE(i915)) { | |
1510 | /* Ignore any error, regard it as a simple optimisation */ | |
1511 | i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC); | |
1512 | } | |
1513 | ||
82ad6443 | 1514 | vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL); |
d2b4b979 CW |
1515 | if (IS_ERR(vma)) { |
1516 | err = PTR_ERR(vma); | |
1517 | goto err_obj; | |
1518 | } | |
3204c343 CW |
1519 | |
1520 | return vma; | |
d2b4b979 CW |
1521 | |
1522 | err_map: | |
1523 | i915_gem_object_unpin_map(obj); | |
1524 | err_obj: | |
1525 | i915_gem_object_put(obj); | |
1526 | return ERR_PTR(err); | |
3204c343 CW |
1527 | } |
1528 | ||
1fc44d9b CW |
1529 | static struct intel_context * |
1530 | __ring_context_pin(struct intel_engine_cs *engine, | |
1531 | struct i915_gem_context *ctx, | |
1532 | struct intel_context *ce) | |
0cb26a8e | 1533 | { |
1fc44d9b | 1534 | int err; |
0cb26a8e | 1535 | |
63ffbcda | 1536 | if (!ce->state && engine->context_size) { |
3204c343 CW |
1537 | struct i915_vma *vma; |
1538 | ||
1539 | vma = alloc_context_vma(engine); | |
1540 | if (IS_ERR(vma)) { | |
1fc44d9b | 1541 | err = PTR_ERR(vma); |
266a240b | 1542 | goto err; |
3204c343 CW |
1543 | } |
1544 | ||
1545 | ce->state = vma; | |
1546 | } | |
1547 | ||
d901e8e6 CW |
1548 | err = __context_pin(ce); |
1549 | if (err) | |
1550 | goto err; | |
0cb26a8e | 1551 | |
a2bbf714 CW |
1552 | err = __context_pin_ppgtt(ce->gem_context); |
1553 | if (err) | |
1554 | goto err_unpin; | |
1555 | ||
9a6feaf0 | 1556 | i915_gem_context_get(ctx); |
0cb26a8e | 1557 | |
266a240b | 1558 | /* One ringbuffer to rule them all */ |
1fc44d9b CW |
1559 | GEM_BUG_ON(!engine->buffer); |
1560 | ce->ring = engine->buffer; | |
1561 | ||
1562 | return ce; | |
266a240b | 1563 | |
a2bbf714 CW |
1564 | err_unpin: |
1565 | __context_unpin(ce); | |
266a240b | 1566 | err: |
0cb26a8e | 1567 | ce->pin_count = 0; |
1fc44d9b | 1568 | return ERR_PTR(err); |
0cb26a8e CW |
1569 | } |
1570 | ||
1fc44d9b CW |
1571 | static const struct intel_context_ops ring_context_ops = { |
1572 | .unpin = intel_ring_context_unpin, | |
1573 | .destroy = intel_ring_context_destroy, | |
1574 | }; | |
1575 | ||
1576 | static struct intel_context * | |
1577 | intel_ring_context_pin(struct intel_engine_cs *engine, | |
1578 | struct i915_gem_context *ctx) | |
0cb26a8e | 1579 | { |
ab82a063 | 1580 | struct intel_context *ce = to_intel_context(ctx, engine); |
0cb26a8e | 1581 | |
91c8a326 | 1582 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
0cb26a8e | 1583 | |
1fc44d9b CW |
1584 | if (likely(ce->pin_count++)) |
1585 | return ce; | |
1586 | GEM_BUG_ON(!ce->pin_count); /* no overflow please! */ | |
0cb26a8e | 1587 | |
1fc44d9b | 1588 | ce->ops = &ring_context_ops; |
0cb26a8e | 1589 | |
1fc44d9b | 1590 | return __ring_context_pin(engine, ctx, ce); |
0cb26a8e CW |
1591 | } |
1592 | ||
acd27845 | 1593 | static int intel_init_ring_buffer(struct intel_engine_cs *engine) |
e3efda49 | 1594 | { |
a89d1f92 | 1595 | struct i915_timeline *timeline; |
d9d117e4 | 1596 | struct intel_ring *ring; |
1a5788bf | 1597 | int err; |
bfc882b4 | 1598 | |
52954edd CW |
1599 | err = intel_engine_setup_common(engine); |
1600 | if (err) | |
1601 | return err; | |
019bf277 | 1602 | |
52954edd CW |
1603 | timeline = i915_timeline_create(engine->i915, |
1604 | engine->name, | |
1605 | engine->status_page.vma); | |
a89d1f92 CW |
1606 | if (IS_ERR(timeline)) { |
1607 | err = PTR_ERR(timeline); | |
1608 | goto err; | |
1609 | } | |
85474441 | 1610 | GEM_BUG_ON(timeline->has_initial_breadcrumb); |
a89d1f92 CW |
1611 | |
1612 | ring = intel_engine_create_ring(engine, timeline, 32 * PAGE_SIZE); | |
1613 | i915_timeline_put(timeline); | |
d822bb18 | 1614 | if (IS_ERR(ring)) { |
1a5788bf | 1615 | err = PTR_ERR(ring); |
486e93f7 | 1616 | goto err; |
d822bb18 CW |
1617 | } |
1618 | ||
5503cb0d | 1619 | err = intel_ring_pin(ring); |
1a5788bf CW |
1620 | if (err) |
1621 | goto err_ring; | |
1622 | ||
1623 | GEM_BUG_ON(engine->buffer); | |
57e88531 | 1624 | engine->buffer = ring; |
62fdfeaf | 1625 | |
d9d117e4 CW |
1626 | err = intel_engine_init_common(engine); |
1627 | if (err) | |
51797499 | 1628 | goto err_unpin; |
d9d117e4 | 1629 | |
52954edd CW |
1630 | GEM_BUG_ON(ring->timeline->hwsp_ggtt != engine->status_page.vma); |
1631 | ||
8ee14975 | 1632 | return 0; |
351e3db2 | 1633 | |
1fc44d9b CW |
1634 | err_unpin: |
1635 | intel_ring_unpin(ring); | |
1a5788bf CW |
1636 | err_ring: |
1637 | intel_ring_free(ring); | |
1a5788bf CW |
1638 | err: |
1639 | intel_engine_cleanup_common(engine); | |
1640 | return err; | |
62fdfeaf EA |
1641 | } |
1642 | ||
7e37f889 | 1643 | void intel_engine_cleanup(struct intel_engine_cs *engine) |
62fdfeaf | 1644 | { |
1a5788bf | 1645 | struct drm_i915_private *dev_priv = engine->i915; |
6402c330 | 1646 | |
1a5788bf CW |
1647 | WARN_ON(INTEL_GEN(dev_priv) > 2 && |
1648 | (I915_READ_MODE(engine) & MODE_IDLE) == 0); | |
33626e6a | 1649 | |
1a5788bf CW |
1650 | intel_ring_unpin(engine->buffer); |
1651 | intel_ring_free(engine->buffer); | |
78501eac | 1652 | |
0bc40be8 TU |
1653 | if (engine->cleanup) |
1654 | engine->cleanup(engine); | |
8d19215b | 1655 | |
96a945aa | 1656 | intel_engine_cleanup_common(engine); |
0cb26a8e | 1657 | |
3b3f1650 AG |
1658 | dev_priv->engine[engine->id] = NULL; |
1659 | kfree(engine); | |
62fdfeaf EA |
1660 | } |
1661 | ||
821ed7df CW |
1662 | void intel_legacy_submission_resume(struct drm_i915_private *dev_priv) |
1663 | { | |
1664 | struct intel_engine_cs *engine; | |
3b3f1650 | 1665 | enum intel_engine_id id; |
821ed7df | 1666 | |
e6ba9992 | 1667 | /* Restart from the beginning of the rings for convenience */ |
fe085f13 | 1668 | for_each_engine(engine, dev_priv, id) |
e6ba9992 | 1669 | intel_ring_reset(engine->buffer, 0); |
821ed7df CW |
1670 | } |
1671 | ||
b3ee09a4 CW |
1672 | static int load_pd_dir(struct i915_request *rq, |
1673 | const struct i915_hw_ppgtt *ppgtt) | |
1674 | { | |
1675 | const struct intel_engine_cs * const engine = rq->engine; | |
1676 | u32 *cs; | |
1677 | ||
1678 | cs = intel_ring_begin(rq, 6); | |
1679 | if (IS_ERR(cs)) | |
1680 | return PTR_ERR(cs); | |
1681 | ||
1682 | *cs++ = MI_LOAD_REGISTER_IMM(1); | |
1683 | *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine)); | |
1684 | *cs++ = PP_DIR_DCLV_2G; | |
1685 | ||
1686 | *cs++ = MI_LOAD_REGISTER_IMM(1); | |
1687 | *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine)); | |
1688 | *cs++ = ppgtt->pd.base.ggtt_offset << 10; | |
1689 | ||
1690 | intel_ring_advance(rq, cs); | |
1691 | ||
1692 | return 0; | |
1693 | } | |
1694 | ||
d9d117e4 CW |
1695 | static int flush_pd_dir(struct i915_request *rq) |
1696 | { | |
1697 | const struct intel_engine_cs * const engine = rq->engine; | |
1698 | u32 *cs; | |
1699 | ||
1700 | cs = intel_ring_begin(rq, 4); | |
1701 | if (IS_ERR(cs)) | |
1702 | return PTR_ERR(cs); | |
1703 | ||
1704 | /* Stall until the page table load is complete */ | |
1705 | *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; | |
1706 | *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine)); | |
51797499 | 1707 | *cs++ = i915_scratch_offset(rq->i915); |
d9d117e4 CW |
1708 | *cs++ = MI_NOOP; |
1709 | ||
1710 | intel_ring_advance(rq, cs); | |
1711 | return 0; | |
1712 | } | |
1713 | ||
e61e0f51 | 1714 | static inline int mi_set_context(struct i915_request *rq, u32 flags) |
8911a31c CW |
1715 | { |
1716 | struct drm_i915_private *i915 = rq->i915; | |
1717 | struct intel_engine_cs *engine = rq->engine; | |
1718 | enum intel_engine_id id; | |
1719 | const int num_rings = | |
0258404f | 1720 | IS_HSW_GT1(i915) ? RUNTIME_INFO(i915)->num_rings - 1 : 0; |
1fc719d1 | 1721 | bool force_restore = false; |
8911a31c CW |
1722 | int len; |
1723 | u32 *cs; | |
1724 | ||
1725 | flags |= MI_MM_SPACE_GTT; | |
1726 | if (IS_HASWELL(i915)) | |
1727 | /* These flags are for resource streamer on HSW+ */ | |
1728 | flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN; | |
1729 | else | |
1730 | flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN; | |
1731 | ||
1732 | len = 4; | |
cf819eff | 1733 | if (IS_GEN(i915, 7)) |
8911a31c | 1734 | len += 2 + (num_rings ? 4*num_rings + 6 : 0); |
1fc719d1 CW |
1735 | if (flags & MI_FORCE_RESTORE) { |
1736 | GEM_BUG_ON(flags & MI_RESTORE_INHIBIT); | |
1737 | flags &= ~MI_FORCE_RESTORE; | |
1738 | force_restore = true; | |
1739 | len += 2; | |
1740 | } | |
8911a31c CW |
1741 | |
1742 | cs = intel_ring_begin(rq, len); | |
1743 | if (IS_ERR(cs)) | |
1744 | return PTR_ERR(cs); | |
1745 | ||
1746 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ | |
cf819eff | 1747 | if (IS_GEN(i915, 7)) { |
8911a31c CW |
1748 | *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; |
1749 | if (num_rings) { | |
1750 | struct intel_engine_cs *signaller; | |
1751 | ||
1752 | *cs++ = MI_LOAD_REGISTER_IMM(num_rings); | |
1753 | for_each_engine(signaller, i915, id) { | |
1754 | if (signaller == engine) | |
1755 | continue; | |
1756 | ||
1757 | *cs++ = i915_mmio_reg_offset( | |
1758 | RING_PSMI_CTL(signaller->mmio_base)); | |
1759 | *cs++ = _MASKED_BIT_ENABLE( | |
1760 | GEN6_PSMI_SLEEP_MSG_DISABLE); | |
1761 | } | |
1762 | } | |
1763 | } | |
1764 | ||
1fc719d1 CW |
1765 | if (force_restore) { |
1766 | /* | |
1767 | * The HW doesn't handle being told to restore the current | |
1768 | * context very well. Quite often it likes goes to go off and | |
1769 | * sulk, especially when it is meant to be reloading PP_DIR. | |
1770 | * A very simple fix to force the reload is to simply switch | |
1771 | * away from the current context and back again. | |
1772 | * | |
1773 | * Note that the kernel_context will contain random state | |
1774 | * following the INHIBIT_RESTORE. We accept this since we | |
1775 | * never use the kernel_context state; it is merely a | |
1776 | * placeholder we use to flush other contexts. | |
1777 | */ | |
1778 | *cs++ = MI_SET_CONTEXT; | |
1779 | *cs++ = i915_ggtt_offset(to_intel_context(i915->kernel_context, | |
1780 | engine)->state) | | |
1781 | MI_MM_SPACE_GTT | | |
1782 | MI_RESTORE_INHIBIT; | |
1783 | } | |
1784 | ||
8911a31c CW |
1785 | *cs++ = MI_NOOP; |
1786 | *cs++ = MI_SET_CONTEXT; | |
1fc44d9b | 1787 | *cs++ = i915_ggtt_offset(rq->hw_context->state) | flags; |
8911a31c CW |
1788 | /* |
1789 | * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP | |
1790 | * WaMiSetContext_Hang:snb,ivb,vlv | |
1791 | */ | |
1792 | *cs++ = MI_NOOP; | |
1793 | ||
cf819eff | 1794 | if (IS_GEN(i915, 7)) { |
8911a31c CW |
1795 | if (num_rings) { |
1796 | struct intel_engine_cs *signaller; | |
1797 | i915_reg_t last_reg = {}; /* keep gcc quiet */ | |
1798 | ||
1799 | *cs++ = MI_LOAD_REGISTER_IMM(num_rings); | |
1800 | for_each_engine(signaller, i915, id) { | |
1801 | if (signaller == engine) | |
1802 | continue; | |
1803 | ||
1804 | last_reg = RING_PSMI_CTL(signaller->mmio_base); | |
1805 | *cs++ = i915_mmio_reg_offset(last_reg); | |
1806 | *cs++ = _MASKED_BIT_DISABLE( | |
1807 | GEN6_PSMI_SLEEP_MSG_DISABLE); | |
1808 | } | |
1809 | ||
1810 | /* Insert a delay before the next switch! */ | |
1811 | *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; | |
1812 | *cs++ = i915_mmio_reg_offset(last_reg); | |
51797499 | 1813 | *cs++ = i915_scratch_offset(rq->i915); |
8911a31c CW |
1814 | *cs++ = MI_NOOP; |
1815 | } | |
1816 | *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; | |
1817 | } | |
1818 | ||
1819 | intel_ring_advance(rq, cs); | |
1820 | ||
1821 | return 0; | |
1822 | } | |
1823 | ||
e61e0f51 | 1824 | static int remap_l3(struct i915_request *rq, int slice) |
8911a31c CW |
1825 | { |
1826 | u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice]; | |
1827 | int i; | |
1828 | ||
1829 | if (!remap_info) | |
1830 | return 0; | |
1831 | ||
1832 | cs = intel_ring_begin(rq, GEN7_L3LOG_SIZE/4 * 2 + 2); | |
1833 | if (IS_ERR(cs)) | |
1834 | return PTR_ERR(cs); | |
1835 | ||
1836 | /* | |
1837 | * Note: We do not worry about the concurrent register cacheline hang | |
1838 | * here because no other code should access these registers other than | |
1839 | * at initialization time. | |
1840 | */ | |
1841 | *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4); | |
1842 | for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) { | |
1843 | *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i)); | |
1844 | *cs++ = remap_info[i]; | |
1845 | } | |
1846 | *cs++ = MI_NOOP; | |
1847 | intel_ring_advance(rq, cs); | |
1848 | ||
1849 | return 0; | |
1850 | } | |
1851 | ||
e61e0f51 | 1852 | static int switch_context(struct i915_request *rq) |
8911a31c CW |
1853 | { |
1854 | struct intel_engine_cs *engine = rq->engine; | |
b3ee09a4 CW |
1855 | struct i915_gem_context *ctx = rq->gem_context; |
1856 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt; | |
1857 | unsigned int unwind_mm = 0; | |
8911a31c CW |
1858 | u32 hw_flags = 0; |
1859 | int ret, i; | |
1860 | ||
1861 | lockdep_assert_held(&rq->i915->drm.struct_mutex); | |
1862 | GEM_BUG_ON(HAS_EXECLISTS(rq->i915)); | |
1863 | ||
b3ee09a4 | 1864 | if (ppgtt) { |
e2a13d1b CW |
1865 | int loops; |
1866 | ||
1867 | /* | |
1868 | * Baytail takes a little more convincing that it really needs | |
1869 | * to reload the PD between contexts. It is not just a little | |
1870 | * longer, as adding more stalls after the load_pd_dir (i.e. | |
1871 | * adding a long loop around flush_pd_dir) is not as effective | |
1872 | * as reloading the PD umpteen times. 32 is derived from | |
1873 | * experimentation (gem_exec_parallel/fds) and has no good | |
1874 | * explanation. | |
1875 | */ | |
1876 | loops = 1; | |
1877 | if (engine->id == BCS && IS_VALLEYVIEW(engine->i915)) | |
1878 | loops = 32; | |
1879 | ||
1880 | do { | |
1881 | ret = load_pd_dir(rq, ppgtt); | |
1882 | if (ret) | |
1883 | goto err; | |
1884 | } while (--loops); | |
8911a31c | 1885 | |
b3ee09a4 CW |
1886 | if (intel_engine_flag(engine) & ppgtt->pd_dirty_rings) { |
1887 | unwind_mm = intel_engine_flag(engine); | |
1888 | ppgtt->pd_dirty_rings &= ~unwind_mm; | |
1889 | hw_flags = MI_FORCE_RESTORE; | |
1890 | } | |
8911a31c CW |
1891 | } |
1892 | ||
b3ee09a4 | 1893 | if (rq->hw_context->state) { |
8911a31c CW |
1894 | GEM_BUG_ON(engine->id != RCS); |
1895 | ||
1896 | /* | |
1897 | * The kernel context(s) is treated as pure scratch and is not | |
1898 | * expected to retain any state (as we sacrifice it during | |
1899 | * suspend and on resume it may be corrupted). This is ok, | |
1900 | * as nothing actually executes using the kernel context; it | |
1901 | * is purely used for flushing user contexts. | |
1902 | */ | |
b3ee09a4 | 1903 | if (i915_gem_context_is_kernel(ctx)) |
8911a31c CW |
1904 | hw_flags = MI_RESTORE_INHIBIT; |
1905 | ||
1906 | ret = mi_set_context(rq, hw_flags); | |
1907 | if (ret) | |
1908 | goto err_mm; | |
8911a31c | 1909 | } |
8911a31c | 1910 | |
d9d117e4 | 1911 | if (ppgtt) { |
06348d30 CW |
1912 | ret = engine->emit_flush(rq, EMIT_INVALIDATE); |
1913 | if (ret) | |
1914 | goto err_mm; | |
1915 | ||
d9d117e4 CW |
1916 | ret = flush_pd_dir(rq); |
1917 | if (ret) | |
1918 | goto err_mm; | |
06348d30 CW |
1919 | |
1920 | /* | |
1921 | * Not only do we need a full barrier (post-sync write) after | |
1922 | * invalidating the TLBs, but we need to wait a little bit | |
1923 | * longer. Whether this is merely delaying us, or the | |
1924 | * subsequent flush is a key part of serialising with the | |
1925 | * post-sync op, this extra pass appears vital before a | |
1926 | * mm switch! | |
1927 | */ | |
1928 | ret = engine->emit_flush(rq, EMIT_INVALIDATE); | |
1929 | if (ret) | |
1930 | goto err_mm; | |
1931 | ||
1932 | ret = engine->emit_flush(rq, EMIT_FLUSH); | |
1933 | if (ret) | |
1934 | goto err_mm; | |
8911a31c CW |
1935 | } |
1936 | ||
b3ee09a4 | 1937 | if (ctx->remap_slice) { |
8911a31c | 1938 | for (i = 0; i < MAX_L3_SLICES; i++) { |
b3ee09a4 | 1939 | if (!(ctx->remap_slice & BIT(i))) |
8911a31c CW |
1940 | continue; |
1941 | ||
1942 | ret = remap_l3(rq, i); | |
1943 | if (ret) | |
b3ee09a4 | 1944 | goto err_mm; |
8911a31c CW |
1945 | } |
1946 | ||
b3ee09a4 | 1947 | ctx->remap_slice = 0; |
8911a31c CW |
1948 | } |
1949 | ||
1950 | return 0; | |
1951 | ||
8911a31c | 1952 | err_mm: |
b3ee09a4 CW |
1953 | if (unwind_mm) |
1954 | ppgtt->pd_dirty_rings |= unwind_mm; | |
8911a31c CW |
1955 | err: |
1956 | return ret; | |
1957 | } | |
1958 | ||
e61e0f51 | 1959 | static int ring_request_alloc(struct i915_request *request) |
9d773091 | 1960 | { |
fd138212 | 1961 | int ret; |
6310346e | 1962 | |
1fc44d9b | 1963 | GEM_BUG_ON(!request->hw_context->pin_count); |
85474441 | 1964 | GEM_BUG_ON(request->timeline->has_initial_breadcrumb); |
e8a9c58f | 1965 | |
5f5800a7 CW |
1966 | /* |
1967 | * Flush enough space to reduce the likelihood of waiting after | |
6310346e CW |
1968 | * we start building the request - in which case we will just |
1969 | * have to repeat work. | |
1970 | */ | |
a0442461 | 1971 | request->reserved_space += LEGACY_REQUEST_SIZE; |
6310346e | 1972 | |
f2253bd9 | 1973 | ret = switch_context(request); |
fd138212 CW |
1974 | if (ret) |
1975 | return ret; | |
6310346e | 1976 | |
f2253bd9 CW |
1977 | /* Unconditionally invalidate GPU caches and TLBs. */ |
1978 | ret = request->engine->emit_flush(request, EMIT_INVALIDATE); | |
3fef5cda CW |
1979 | if (ret) |
1980 | return ret; | |
1981 | ||
a0442461 | 1982 | request->reserved_space -= LEGACY_REQUEST_SIZE; |
6310346e | 1983 | return 0; |
9d773091 CW |
1984 | } |
1985 | ||
fd138212 | 1986 | static noinline int wait_for_space(struct intel_ring *ring, unsigned int bytes) |
987046ad | 1987 | { |
e61e0f51 | 1988 | struct i915_request *target; |
e95433c7 CW |
1989 | long timeout; |
1990 | ||
fd138212 | 1991 | lockdep_assert_held(&ring->vma->vm->i915->drm.struct_mutex); |
987046ad | 1992 | |
95aebcb2 | 1993 | if (intel_ring_update_space(ring) >= bytes) |
987046ad CW |
1994 | return 0; |
1995 | ||
36620032 | 1996 | GEM_BUG_ON(list_empty(&ring->request_list)); |
675d9ad7 | 1997 | list_for_each_entry(target, &ring->request_list, ring_link) { |
987046ad | 1998 | /* Would completion of this request free enough space? */ |
605d5b32 CW |
1999 | if (bytes <= __intel_ring_space(target->postfix, |
2000 | ring->emit, ring->size)) | |
987046ad | 2001 | break; |
79bbcc29 | 2002 | } |
29b1b415 | 2003 | |
675d9ad7 | 2004 | if (WARN_ON(&target->ring_link == &ring->request_list)) |
987046ad CW |
2005 | return -ENOSPC; |
2006 | ||
e61e0f51 | 2007 | timeout = i915_request_wait(target, |
e95433c7 CW |
2008 | I915_WAIT_INTERRUPTIBLE | I915_WAIT_LOCKED, |
2009 | MAX_SCHEDULE_TIMEOUT); | |
2010 | if (timeout < 0) | |
2011 | return timeout; | |
7da844c5 | 2012 | |
e61e0f51 | 2013 | i915_request_retire_upto(target); |
7da844c5 CW |
2014 | |
2015 | intel_ring_update_space(ring); | |
2016 | GEM_BUG_ON(ring->space < bytes); | |
2017 | return 0; | |
29b1b415 JH |
2018 | } |
2019 | ||
e61e0f51 | 2020 | u32 *intel_ring_begin(struct i915_request *rq, unsigned int num_dwords) |
cbcc80df | 2021 | { |
e61e0f51 | 2022 | struct intel_ring *ring = rq->ring; |
5e5655c3 CW |
2023 | const unsigned int remain_usable = ring->effective_size - ring->emit; |
2024 | const unsigned int bytes = num_dwords * sizeof(u32); | |
2025 | unsigned int need_wrap = 0; | |
2026 | unsigned int total_bytes; | |
73dec95e | 2027 | u32 *cs; |
29b1b415 | 2028 | |
6492ca79 CW |
2029 | /* Packets must be qword aligned. */ |
2030 | GEM_BUG_ON(num_dwords & 1); | |
2031 | ||
e61e0f51 | 2032 | total_bytes = bytes + rq->reserved_space; |
5e5655c3 | 2033 | GEM_BUG_ON(total_bytes > ring->effective_size); |
29b1b415 | 2034 | |
5e5655c3 CW |
2035 | if (unlikely(total_bytes > remain_usable)) { |
2036 | const int remain_actual = ring->size - ring->emit; | |
2037 | ||
2038 | if (bytes > remain_usable) { | |
2039 | /* | |
2040 | * Not enough space for the basic request. So need to | |
2041 | * flush out the remainder and then wait for | |
2042 | * base + reserved. | |
2043 | */ | |
2044 | total_bytes += remain_actual; | |
2045 | need_wrap = remain_actual | 1; | |
2046 | } else { | |
2047 | /* | |
2048 | * The base request will fit but the reserved space | |
2049 | * falls off the end. So we don't need an immediate | |
2050 | * wrap and only need to effectively wait for the | |
2051 | * reserved size from the start of ringbuffer. | |
2052 | */ | |
e61e0f51 | 2053 | total_bytes = rq->reserved_space + remain_actual; |
5e5655c3 | 2054 | } |
cbcc80df MK |
2055 | } |
2056 | ||
5e5655c3 | 2057 | if (unlikely(total_bytes > ring->space)) { |
fd138212 CW |
2058 | int ret; |
2059 | ||
2060 | /* | |
2061 | * Space is reserved in the ringbuffer for finalising the | |
2062 | * request, as that cannot be allowed to fail. During request | |
2063 | * finalisation, reserved_space is set to 0 to stop the | |
2064 | * overallocation and the assumption is that then we never need | |
2065 | * to wait (which has the risk of failing with EINTR). | |
2066 | * | |
e61e0f51 | 2067 | * See also i915_request_alloc() and i915_request_add(). |
fd138212 | 2068 | */ |
e61e0f51 | 2069 | GEM_BUG_ON(!rq->reserved_space); |
fd138212 CW |
2070 | |
2071 | ret = wait_for_space(ring, total_bytes); | |
cbcc80df | 2072 | if (unlikely(ret)) |
73dec95e | 2073 | return ERR_PTR(ret); |
cbcc80df MK |
2074 | } |
2075 | ||
987046ad | 2076 | if (unlikely(need_wrap)) { |
5e5655c3 CW |
2077 | need_wrap &= ~1; |
2078 | GEM_BUG_ON(need_wrap > ring->space); | |
2079 | GEM_BUG_ON(ring->emit + need_wrap > ring->size); | |
46b86332 | 2080 | GEM_BUG_ON(!IS_ALIGNED(need_wrap, sizeof(u64))); |
78501eac | 2081 | |
987046ad | 2082 | /* Fill the tail with MI_NOOP */ |
46b86332 | 2083 | memset64(ring->vaddr + ring->emit, 0, need_wrap / sizeof(u64)); |
5e5655c3 | 2084 | ring->space -= need_wrap; |
46b86332 | 2085 | ring->emit = 0; |
987046ad | 2086 | } |
304d695c | 2087 | |
e6ba9992 | 2088 | GEM_BUG_ON(ring->emit > ring->size - bytes); |
605d5b32 | 2089 | GEM_BUG_ON(ring->space < bytes); |
e6ba9992 | 2090 | cs = ring->vaddr + ring->emit; |
46b86332 | 2091 | GEM_DEBUG_EXEC(memset32(cs, POISON_INUSE, bytes / sizeof(*cs))); |
e6ba9992 | 2092 | ring->emit += bytes; |
1dae2dfb | 2093 | ring->space -= bytes; |
73dec95e TU |
2094 | |
2095 | return cs; | |
8187a2b7 | 2096 | } |
78501eac | 2097 | |
753b1ad4 | 2098 | /* Align the ring tail to a cacheline boundary */ |
e61e0f51 | 2099 | int intel_ring_cacheline_align(struct i915_request *rq) |
753b1ad4 | 2100 | { |
1f177a13 CW |
2101 | int num_dwords; |
2102 | void *cs; | |
753b1ad4 | 2103 | |
1f177a13 | 2104 | num_dwords = (rq->ring->emit & (CACHELINE_BYTES - 1)) / sizeof(u32); |
753b1ad4 VS |
2105 | if (num_dwords == 0) |
2106 | return 0; | |
2107 | ||
1f177a13 CW |
2108 | num_dwords = CACHELINE_DWORDS - num_dwords; |
2109 | GEM_BUG_ON(num_dwords & 1); | |
2110 | ||
e61e0f51 | 2111 | cs = intel_ring_begin(rq, num_dwords); |
73dec95e TU |
2112 | if (IS_ERR(cs)) |
2113 | return PTR_ERR(cs); | |
753b1ad4 | 2114 | |
1f177a13 | 2115 | memset64(cs, (u64)MI_NOOP << 32 | MI_NOOP, num_dwords / 2); |
e61e0f51 | 2116 | intel_ring_advance(rq, cs); |
753b1ad4 | 2117 | |
1f177a13 | 2118 | GEM_BUG_ON(rq->ring->emit & (CACHELINE_BYTES - 1)); |
753b1ad4 VS |
2119 | return 0; |
2120 | } | |
2121 | ||
e61e0f51 | 2122 | static void gen6_bsd_submit_request(struct i915_request *request) |
881f47b6 | 2123 | { |
c5efa1ad | 2124 | struct drm_i915_private *dev_priv = request->i915; |
881f47b6 | 2125 | |
76f8421f CW |
2126 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
2127 | ||
881f47b6 | 2128 | /* Every tail move must follow the sequence below */ |
12f55818 CW |
2129 | |
2130 | /* Disable notification that the ring is IDLE. The GT | |
2131 | * will then assume that it is busy and bring it out of rc6. | |
2132 | */ | |
76f8421f CW |
2133 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
2134 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
12f55818 CW |
2135 | |
2136 | /* Clear the context id. Here be magic! */ | |
76f8421f | 2137 | I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0); |
0206e353 | 2138 | |
12f55818 | 2139 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
02b312d0 CW |
2140 | if (__intel_wait_for_register_fw(dev_priv, |
2141 | GEN6_BSD_SLEEP_PSMI_CONTROL, | |
2142 | GEN6_BSD_SLEEP_INDICATOR, | |
2143 | 0, | |
2144 | 1000, 0, NULL)) | |
12f55818 | 2145 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
0206e353 | 2146 | |
12f55818 | 2147 | /* Now that the ring is fully powered up, update the tail */ |
b0411e7d | 2148 | i9xx_submit_request(request); |
12f55818 CW |
2149 | |
2150 | /* Let the ring send IDLE messages to the GT again, | |
2151 | * and so let it sleep to conserve power when idle. | |
2152 | */ | |
76f8421f CW |
2153 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
2154 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
2155 | ||
2156 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
881f47b6 XH |
2157 | } |
2158 | ||
06348d30 | 2159 | static int mi_flush_dw(struct i915_request *rq, u32 flags) |
881f47b6 | 2160 | { |
73dec95e | 2161 | u32 cmd, *cs; |
b72f3acb | 2162 | |
e61e0f51 | 2163 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
2164 | if (IS_ERR(cs)) |
2165 | return PTR_ERR(cs); | |
b72f3acb | 2166 | |
71a77e07 | 2167 | cmd = MI_FLUSH_DW; |
f0a1fb10 | 2168 | |
70b73f9a CW |
2169 | /* |
2170 | * We always require a command barrier so that subsequent | |
f0a1fb10 CW |
2171 | * commands, such as breadcrumb interrupts, are strictly ordered |
2172 | * wrt the contents of the write cache being flushed to memory | |
2173 | * (and thus being coherent from the CPU). | |
2174 | */ | |
2175 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2176 | ||
9a289771 | 2177 | /* |
70b73f9a | 2178 | * Bspec vol 1c.3 - blitter engine command streamer: |
9a289771 JB |
2179 | * "If ENABLED, all TLBs will be invalidated once the flush |
2180 | * operation is complete. This bit is only valid when the | |
2181 | * Post-Sync Operation field is a value of 1h or 3h." | |
2182 | */ | |
70b73f9a | 2183 | cmd |= flags; |
f0a1fb10 | 2184 | |
73dec95e TU |
2185 | *cs++ = cmd; |
2186 | *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; | |
79e6770c | 2187 | *cs++ = 0; |
73dec95e | 2188 | *cs++ = MI_NOOP; |
70b73f9a | 2189 | |
e61e0f51 | 2190 | intel_ring_advance(rq, cs); |
70b73f9a | 2191 | |
1c7a0623 BW |
2192 | return 0; |
2193 | } | |
2194 | ||
70b73f9a CW |
2195 | static int gen6_flush_dw(struct i915_request *rq, u32 mode, u32 invflags) |
2196 | { | |
06348d30 | 2197 | return mi_flush_dw(rq, mode & EMIT_INVALIDATE ? invflags : 0); |
70b73f9a CW |
2198 | } |
2199 | ||
2200 | static int gen6_bsd_ring_flush(struct i915_request *rq, u32 mode) | |
2201 | { | |
2202 | return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB | MI_INVALIDATE_BSD); | |
2203 | } | |
2204 | ||
d7d4eedd | 2205 | static int |
e61e0f51 | 2206 | hsw_emit_bb_start(struct i915_request *rq, |
803688ba CW |
2207 | u64 offset, u32 len, |
2208 | unsigned int dispatch_flags) | |
d7d4eedd | 2209 | { |
73dec95e | 2210 | u32 *cs; |
d7d4eedd | 2211 | |
e61e0f51 | 2212 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
2213 | if (IS_ERR(cs)) |
2214 | return PTR_ERR(cs); | |
d7d4eedd | 2215 | |
73dec95e | 2216 | *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ? |
08e3e21a | 2217 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW); |
d7d4eedd | 2218 | /* bit0-7 is the length on GEN6+ */ |
73dec95e | 2219 | *cs++ = offset; |
e61e0f51 | 2220 | intel_ring_advance(rq, cs); |
d7d4eedd CW |
2221 | |
2222 | return 0; | |
2223 | } | |
2224 | ||
881f47b6 | 2225 | static int |
e61e0f51 | 2226 | gen6_emit_bb_start(struct i915_request *rq, |
803688ba CW |
2227 | u64 offset, u32 len, |
2228 | unsigned int dispatch_flags) | |
881f47b6 | 2229 | { |
73dec95e | 2230 | u32 *cs; |
ab6f8e32 | 2231 | |
e61e0f51 | 2232 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
2233 | if (IS_ERR(cs)) |
2234 | return PTR_ERR(cs); | |
e1f99ce6 | 2235 | |
73dec95e TU |
2236 | *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ? |
2237 | 0 : MI_BATCH_NON_SECURE_I965); | |
0206e353 | 2238 | /* bit0-7 is the length on GEN6+ */ |
73dec95e | 2239 | *cs++ = offset; |
e61e0f51 | 2240 | intel_ring_advance(rq, cs); |
ab6f8e32 | 2241 | |
0206e353 | 2242 | return 0; |
881f47b6 XH |
2243 | } |
2244 | ||
549f7365 CW |
2245 | /* Blitter support (SandyBridge+) */ |
2246 | ||
e61e0f51 | 2247 | static int gen6_ring_flush(struct i915_request *rq, u32 mode) |
8d19215b | 2248 | { |
70b73f9a | 2249 | return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB); |
8d19215b ZN |
2250 | } |
2251 | ||
ed003078 CW |
2252 | static void intel_ring_init_irq(struct drm_i915_private *dev_priv, |
2253 | struct intel_engine_cs *engine) | |
2254 | { | |
79e6770c | 2255 | if (INTEL_GEN(dev_priv) >= 6) { |
31bb59cc CW |
2256 | engine->irq_enable = gen6_irq_enable; |
2257 | engine->irq_disable = gen6_irq_disable; | |
ed003078 | 2258 | } else if (INTEL_GEN(dev_priv) >= 5) { |
31bb59cc CW |
2259 | engine->irq_enable = gen5_irq_enable; |
2260 | engine->irq_disable = gen5_irq_disable; | |
ed003078 | 2261 | } else if (INTEL_GEN(dev_priv) >= 3) { |
31bb59cc CW |
2262 | engine->irq_enable = i9xx_irq_enable; |
2263 | engine->irq_disable = i9xx_irq_disable; | |
ed003078 | 2264 | } else { |
31bb59cc CW |
2265 | engine->irq_enable = i8xx_irq_enable; |
2266 | engine->irq_disable = i8xx_irq_disable; | |
ed003078 CW |
2267 | } |
2268 | } | |
2269 | ||
ff44ad51 CW |
2270 | static void i9xx_set_default_submission(struct intel_engine_cs *engine) |
2271 | { | |
2272 | engine->submit_request = i9xx_submit_request; | |
27a5f61b | 2273 | engine->cancel_requests = cancel_requests; |
aba5e278 CW |
2274 | |
2275 | engine->park = NULL; | |
2276 | engine->unpark = NULL; | |
ff44ad51 CW |
2277 | } |
2278 | ||
2279 | static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine) | |
2280 | { | |
aba5e278 | 2281 | i9xx_set_default_submission(engine); |
ff44ad51 CW |
2282 | engine->submit_request = gen6_bsd_submit_request; |
2283 | } | |
2284 | ||
06a2fe22 TU |
2285 | static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv, |
2286 | struct intel_engine_cs *engine) | |
2287 | { | |
79e6770c CW |
2288 | /* gen8+ are only supported with execlists */ |
2289 | GEM_BUG_ON(INTEL_GEN(dev_priv) >= 8); | |
2290 | ||
618e4ca7 | 2291 | intel_ring_init_irq(dev_priv, engine); |
618e4ca7 | 2292 | |
1d8a1337 | 2293 | engine->init_hw = init_ring_common; |
5adfb772 CW |
2294 | engine->reset.prepare = reset_prepare; |
2295 | engine->reset.reset = reset_ring; | |
2296 | engine->reset.finish = reset_finish; | |
7445a2a4 | 2297 | |
e8a9c58f | 2298 | engine->context_pin = intel_ring_context_pin; |
f73e7399 CW |
2299 | engine->request_alloc = ring_request_alloc; |
2300 | ||
85474441 CW |
2301 | /* |
2302 | * Using a global execution timeline; the previous final breadcrumb is | |
2303 | * equivalent to our next initial bread so we can elide | |
2304 | * engine->emit_init_breadcrumb(). | |
2305 | */ | |
2306 | engine->emit_fini_breadcrumb = i9xx_emit_breadcrumb; | |
9fa4973e | 2307 | if (IS_GEN(dev_priv, 5)) |
85474441 | 2308 | engine->emit_fini_breadcrumb = gen5_emit_breadcrumb; |
ff44ad51 CW |
2309 | |
2310 | engine->set_default_submission = i9xx_set_default_submission; | |
6f7bef75 | 2311 | |
79e6770c | 2312 | if (INTEL_GEN(dev_priv) >= 6) |
803688ba | 2313 | engine->emit_bb_start = gen6_emit_bb_start; |
6f7bef75 | 2314 | else if (INTEL_GEN(dev_priv) >= 4) |
803688ba | 2315 | engine->emit_bb_start = i965_emit_bb_start; |
2a307c2e | 2316 | else if (IS_I830(dev_priv) || IS_I845G(dev_priv)) |
803688ba | 2317 | engine->emit_bb_start = i830_emit_bb_start; |
6f7bef75 | 2318 | else |
803688ba | 2319 | engine->emit_bb_start = i915_emit_bb_start; |
06a2fe22 TU |
2320 | } |
2321 | ||
8b3e2d36 | 2322 | int intel_init_render_ring_buffer(struct intel_engine_cs *engine) |
5c1143bb | 2323 | { |
8b3e2d36 | 2324 | struct drm_i915_private *dev_priv = engine->i915; |
3e78998a | 2325 | int ret; |
5c1143bb | 2326 | |
06a2fe22 TU |
2327 | intel_ring_default_vfuncs(dev_priv, engine); |
2328 | ||
61ff75ac CW |
2329 | if (HAS_L3_DPF(dev_priv)) |
2330 | engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
f8973c21 | 2331 | |
fa6f071d DCS |
2332 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
2333 | ||
caa5915b | 2334 | if (INTEL_GEN(dev_priv) >= 7) { |
e2f80391 | 2335 | engine->init_context = intel_rcs_ctx_init; |
c7fe7d25 | 2336 | engine->emit_flush = gen7_render_ring_flush; |
85474441 | 2337 | engine->emit_fini_breadcrumb = gen7_rcs_emit_breadcrumb; |
caa5915b CW |
2338 | } else if (IS_GEN(dev_priv, 6)) { |
2339 | engine->init_context = intel_rcs_ctx_init; | |
2340 | engine->emit_flush = gen6_render_ring_flush; | |
85474441 | 2341 | engine->emit_fini_breadcrumb = gen6_rcs_emit_breadcrumb; |
cf819eff | 2342 | } else if (IS_GEN(dev_priv, 5)) { |
c7fe7d25 | 2343 | engine->emit_flush = gen4_render_ring_flush; |
59465b5f | 2344 | } else { |
c033666a | 2345 | if (INTEL_GEN(dev_priv) < 4) |
c7fe7d25 | 2346 | engine->emit_flush = gen2_render_ring_flush; |
46f0f8d1 | 2347 | else |
c7fe7d25 | 2348 | engine->emit_flush = gen4_render_ring_flush; |
e2f80391 | 2349 | engine->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2350 | } |
707d9cf9 | 2351 | |
c033666a | 2352 | if (IS_HASWELL(dev_priv)) |
803688ba | 2353 | engine->emit_bb_start = hsw_emit_bb_start; |
6f7bef75 | 2354 | |
e2f80391 | 2355 | engine->init_hw = init_render_ring; |
59465b5f | 2356 | |
acd27845 | 2357 | ret = intel_init_ring_buffer(engine); |
99be1dfe DV |
2358 | if (ret) |
2359 | return ret; | |
2360 | ||
99be1dfe | 2361 | return 0; |
5c1143bb XH |
2362 | } |
2363 | ||
8b3e2d36 | 2364 | int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine) |
5c1143bb | 2365 | { |
8b3e2d36 | 2366 | struct drm_i915_private *dev_priv = engine->i915; |
58fa3835 | 2367 | |
06a2fe22 TU |
2368 | intel_ring_default_vfuncs(dev_priv, engine); |
2369 | ||
c033666a | 2370 | if (INTEL_GEN(dev_priv) >= 6) { |
0fd2c201 | 2371 | /* gen6 bsd needs a special wa for tail updates */ |
cf819eff | 2372 | if (IS_GEN(dev_priv, 6)) |
ff44ad51 | 2373 | engine->set_default_submission = gen6_bsd_set_default_submission; |
c7fe7d25 | 2374 | engine->emit_flush = gen6_bsd_ring_flush; |
79e6770c | 2375 | engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
caa5915b | 2376 | |
9fa4973e | 2377 | if (IS_GEN(dev_priv, 6)) |
85474441 | 2378 | engine->emit_fini_breadcrumb = gen6_xcs_emit_breadcrumb; |
9fa4973e | 2379 | else |
85474441 | 2380 | engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb; |
58fa3835 | 2381 | } else { |
c7fe7d25 | 2382 | engine->emit_flush = bsd_ring_flush; |
cf819eff | 2383 | if (IS_GEN(dev_priv, 5)) |
e2f80391 | 2384 | engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
8d228911 | 2385 | else |
e2f80391 | 2386 | engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
58fa3835 | 2387 | } |
58fa3835 | 2388 | |
acd27845 | 2389 | return intel_init_ring_buffer(engine); |
5c1143bb | 2390 | } |
549f7365 | 2391 | |
8b3e2d36 | 2392 | int intel_init_blt_ring_buffer(struct intel_engine_cs *engine) |
549f7365 | 2393 | { |
8b3e2d36 | 2394 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 | 2395 | |
caa5915b CW |
2396 | GEM_BUG_ON(INTEL_GEN(dev_priv) < 6); |
2397 | ||
06a2fe22 TU |
2398 | intel_ring_default_vfuncs(dev_priv, engine); |
2399 | ||
c7fe7d25 | 2400 | engine->emit_flush = gen6_ring_flush; |
79e6770c | 2401 | engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
549f7365 | 2402 | |
9fa4973e | 2403 | if (IS_GEN(dev_priv, 6)) |
85474441 | 2404 | engine->emit_fini_breadcrumb = gen6_xcs_emit_breadcrumb; |
9fa4973e | 2405 | else |
85474441 | 2406 | engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb; |
caa5915b | 2407 | |
acd27845 | 2408 | return intel_init_ring_buffer(engine); |
549f7365 | 2409 | } |
a7b9761d | 2410 | |
8b3e2d36 | 2411 | int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine) |
9a8a2213 | 2412 | { |
8b3e2d36 | 2413 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 | 2414 | |
caa5915b CW |
2415 | GEM_BUG_ON(INTEL_GEN(dev_priv) < 7); |
2416 | ||
06a2fe22 TU |
2417 | intel_ring_default_vfuncs(dev_priv, engine); |
2418 | ||
c7fe7d25 | 2419 | engine->emit_flush = gen6_ring_flush; |
79e6770c CW |
2420 | engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
2421 | engine->irq_enable = hsw_vebox_irq_enable; | |
2422 | engine->irq_disable = hsw_vebox_irq_disable; | |
9a8a2213 | 2423 | |
85474441 | 2424 | engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb; |
caa5915b | 2425 | |
acd27845 | 2426 | return intel_init_ring_buffer(engine); |
9a8a2213 | 2427 | } |