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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
760285e7 | 30 | #include <drm/drmP.h> |
62fdfeaf | 31 | #include "i915_drv.h" |
760285e7 | 32 | #include <drm/i915_drm.h> |
62fdfeaf | 33 | #include "i915_trace.h" |
881f47b6 | 34 | #include "intel_drv.h" |
62fdfeaf | 35 | |
18393f63 CW |
36 | /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill, |
37 | * but keeps the logic simple. Indeed, the whole purpose of this macro is just | |
38 | * to give some inclination as to some of the magic values used in the various | |
39 | * workarounds! | |
40 | */ | |
41 | #define CACHELINE_BYTES 64 | |
42 | ||
48d82387 OM |
43 | bool |
44 | intel_ring_initialized(struct intel_engine_cs *ring) | |
45 | { | |
46 | struct drm_device *dev = ring->dev; | |
47 | ||
48 | if (!dev) | |
49 | return false; | |
50 | ||
51 | if (i915.enable_execlists) { | |
52 | struct intel_context *dctx = ring->default_context; | |
53 | struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf; | |
54 | ||
55 | return ringbuf->obj; | |
56 | } else | |
57 | return ring->buffer && ring->buffer->obj; | |
58 | } | |
59 | ||
1cf0ba14 | 60 | static inline int __ring_space(int head, int tail, int size) |
c7dca47b | 61 | { |
1cf0ba14 | 62 | int space = head - (tail + I915_RING_FREE_SPACE); |
c7dca47b | 63 | if (space < 0) |
1cf0ba14 | 64 | space += size; |
c7dca47b CW |
65 | return space; |
66 | } | |
67 | ||
64c58f2c | 68 | static inline int ring_space(struct intel_ringbuffer *ringbuf) |
1cf0ba14 | 69 | { |
93b0a4e0 | 70 | return __ring_space(ringbuf->head & HEAD_ADDR, ringbuf->tail, ringbuf->size); |
1cf0ba14 CW |
71 | } |
72 | ||
a4872ba6 | 73 | static bool intel_ring_stopped(struct intel_engine_cs *ring) |
09246732 CW |
74 | { |
75 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
88b4aa87 MK |
76 | return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring); |
77 | } | |
09246732 | 78 | |
a4872ba6 | 79 | void __intel_ring_advance(struct intel_engine_cs *ring) |
88b4aa87 | 80 | { |
93b0a4e0 OM |
81 | struct intel_ringbuffer *ringbuf = ring->buffer; |
82 | ringbuf->tail &= ringbuf->size - 1; | |
88b4aa87 | 83 | if (intel_ring_stopped(ring)) |
09246732 | 84 | return; |
93b0a4e0 | 85 | ring->write_tail(ring, ringbuf->tail); |
09246732 CW |
86 | } |
87 | ||
b72f3acb | 88 | static int |
a4872ba6 | 89 | gen2_render_ring_flush(struct intel_engine_cs *ring, |
46f0f8d1 CW |
90 | u32 invalidate_domains, |
91 | u32 flush_domains) | |
92 | { | |
93 | u32 cmd; | |
94 | int ret; | |
95 | ||
96 | cmd = MI_FLUSH; | |
31b14c9f | 97 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
46f0f8d1 CW |
98 | cmd |= MI_NO_WRITE_FLUSH; |
99 | ||
100 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
101 | cmd |= MI_READ_FLUSH; | |
102 | ||
103 | ret = intel_ring_begin(ring, 2); | |
104 | if (ret) | |
105 | return ret; | |
106 | ||
107 | intel_ring_emit(ring, cmd); | |
108 | intel_ring_emit(ring, MI_NOOP); | |
109 | intel_ring_advance(ring); | |
110 | ||
111 | return 0; | |
112 | } | |
113 | ||
114 | static int | |
a4872ba6 | 115 | gen4_render_ring_flush(struct intel_engine_cs *ring, |
46f0f8d1 CW |
116 | u32 invalidate_domains, |
117 | u32 flush_domains) | |
62fdfeaf | 118 | { |
78501eac | 119 | struct drm_device *dev = ring->dev; |
6f392d54 | 120 | u32 cmd; |
b72f3acb | 121 | int ret; |
6f392d54 | 122 | |
36d527de CW |
123 | /* |
124 | * read/write caches: | |
125 | * | |
126 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
127 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
128 | * also flushed at 2d versus 3d pipeline switches. | |
129 | * | |
130 | * read-only caches: | |
131 | * | |
132 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
133 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
134 | * | |
135 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
136 | * | |
137 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
138 | * invalidated when MI_EXE_FLUSH is set. | |
139 | * | |
140 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
141 | * invalidated with every MI_FLUSH. | |
142 | * | |
143 | * TLBs: | |
144 | * | |
145 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
146 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
147 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
148 | * are flushed at any MI_FLUSH. | |
149 | */ | |
150 | ||
151 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
46f0f8d1 | 152 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
36d527de | 153 | cmd &= ~MI_NO_WRITE_FLUSH; |
36d527de CW |
154 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
155 | cmd |= MI_EXE_FLUSH; | |
62fdfeaf | 156 | |
36d527de CW |
157 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
158 | (IS_G4X(dev) || IS_GEN5(dev))) | |
159 | cmd |= MI_INVALIDATE_ISP; | |
70eac33e | 160 | |
36d527de CW |
161 | ret = intel_ring_begin(ring, 2); |
162 | if (ret) | |
163 | return ret; | |
b72f3acb | 164 | |
36d527de CW |
165 | intel_ring_emit(ring, cmd); |
166 | intel_ring_emit(ring, MI_NOOP); | |
167 | intel_ring_advance(ring); | |
b72f3acb CW |
168 | |
169 | return 0; | |
8187a2b7 ZN |
170 | } |
171 | ||
8d315287 JB |
172 | /** |
173 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
174 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
175 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
176 | * | |
177 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
178 | * produced by non-pipelined state commands), software needs to first | |
179 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
180 | * 0. | |
181 | * | |
182 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
183 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
184 | * | |
185 | * And the workaround for these two requires this workaround first: | |
186 | * | |
187 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
188 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
189 | * flushes. | |
190 | * | |
191 | * And this last workaround is tricky because of the requirements on | |
192 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
193 | * volume 2 part 1: | |
194 | * | |
195 | * "1 of the following must also be set: | |
196 | * - Render Target Cache Flush Enable ([12] of DW1) | |
197 | * - Depth Cache Flush Enable ([0] of DW1) | |
198 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
199 | * - Depth Stall ([13] of DW1) | |
200 | * - Post-Sync Operation ([13] of DW1) | |
201 | * - Notify Enable ([8] of DW1)" | |
202 | * | |
203 | * The cache flushes require the workaround flush that triggered this | |
204 | * one, so we can't use it. Depth stall would trigger the same. | |
205 | * Post-sync nonzero is what triggered this second workaround, so we | |
206 | * can't use that one either. Notify enable is IRQs, which aren't | |
207 | * really our business. That leaves only stall at scoreboard. | |
208 | */ | |
209 | static int | |
a4872ba6 | 210 | intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring) |
8d315287 | 211 | { |
18393f63 | 212 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
213 | int ret; |
214 | ||
215 | ||
216 | ret = intel_ring_begin(ring, 6); | |
217 | if (ret) | |
218 | return ret; | |
219 | ||
220 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
221 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
222 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
223 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
224 | intel_ring_emit(ring, 0); /* low dword */ | |
225 | intel_ring_emit(ring, 0); /* high dword */ | |
226 | intel_ring_emit(ring, MI_NOOP); | |
227 | intel_ring_advance(ring); | |
228 | ||
229 | ret = intel_ring_begin(ring, 6); | |
230 | if (ret) | |
231 | return ret; | |
232 | ||
233 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
234 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); | |
235 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
236 | intel_ring_emit(ring, 0); | |
237 | intel_ring_emit(ring, 0); | |
238 | intel_ring_emit(ring, MI_NOOP); | |
239 | intel_ring_advance(ring); | |
240 | ||
241 | return 0; | |
242 | } | |
243 | ||
244 | static int | |
a4872ba6 | 245 | gen6_render_ring_flush(struct intel_engine_cs *ring, |
8d315287 JB |
246 | u32 invalidate_domains, u32 flush_domains) |
247 | { | |
248 | u32 flags = 0; | |
18393f63 | 249 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
250 | int ret; |
251 | ||
b3111509 PZ |
252 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
253 | ret = intel_emit_post_sync_nonzero_flush(ring); | |
254 | if (ret) | |
255 | return ret; | |
256 | ||
8d315287 JB |
257 | /* Just flush everything. Experiments have shown that reducing the |
258 | * number of bits based on the write domains has little performance | |
259 | * impact. | |
260 | */ | |
7d54a904 CW |
261 | if (flush_domains) { |
262 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
263 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
264 | /* | |
265 | * Ensure that any following seqno writes only happen | |
266 | * when the render cache is indeed flushed. | |
267 | */ | |
97f209bc | 268 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 CW |
269 | } |
270 | if (invalidate_domains) { | |
271 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
272 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
273 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
274 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
275 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
276 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
277 | /* | |
278 | * TLB invalidate requires a post-sync write. | |
279 | */ | |
3ac78313 | 280 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 281 | } |
8d315287 | 282 | |
6c6cf5aa | 283 | ret = intel_ring_begin(ring, 4); |
8d315287 JB |
284 | if (ret) |
285 | return ret; | |
286 | ||
6c6cf5aa | 287 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
8d315287 JB |
288 | intel_ring_emit(ring, flags); |
289 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
6c6cf5aa | 290 | intel_ring_emit(ring, 0); |
8d315287 JB |
291 | intel_ring_advance(ring); |
292 | ||
293 | return 0; | |
294 | } | |
295 | ||
f3987631 | 296 | static int |
a4872ba6 | 297 | gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring) |
f3987631 PZ |
298 | { |
299 | int ret; | |
300 | ||
301 | ret = intel_ring_begin(ring, 4); | |
302 | if (ret) | |
303 | return ret; | |
304 | ||
305 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
306 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
307 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
308 | intel_ring_emit(ring, 0); | |
309 | intel_ring_emit(ring, 0); | |
310 | intel_ring_advance(ring); | |
311 | ||
312 | return 0; | |
313 | } | |
314 | ||
a4872ba6 | 315 | static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value) |
fd3da6c9 RV |
316 | { |
317 | int ret; | |
318 | ||
319 | if (!ring->fbc_dirty) | |
320 | return 0; | |
321 | ||
37c1d94f | 322 | ret = intel_ring_begin(ring, 6); |
fd3da6c9 RV |
323 | if (ret) |
324 | return ret; | |
fd3da6c9 RV |
325 | /* WaFbcNukeOn3DBlt:ivb/hsw */ |
326 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
327 | intel_ring_emit(ring, MSG_FBC_REND_STATE); | |
328 | intel_ring_emit(ring, value); | |
37c1d94f VS |
329 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT); |
330 | intel_ring_emit(ring, MSG_FBC_REND_STATE); | |
331 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
fd3da6c9 RV |
332 | intel_ring_advance(ring); |
333 | ||
334 | ring->fbc_dirty = false; | |
335 | return 0; | |
336 | } | |
337 | ||
4772eaeb | 338 | static int |
a4872ba6 | 339 | gen7_render_ring_flush(struct intel_engine_cs *ring, |
4772eaeb PZ |
340 | u32 invalidate_domains, u32 flush_domains) |
341 | { | |
342 | u32 flags = 0; | |
18393f63 | 343 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
4772eaeb PZ |
344 | int ret; |
345 | ||
f3987631 PZ |
346 | /* |
347 | * Ensure that any following seqno writes only happen when the render | |
348 | * cache is indeed flushed. | |
349 | * | |
350 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
351 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
352 | * don't try to be clever and just set it unconditionally. | |
353 | */ | |
354 | flags |= PIPE_CONTROL_CS_STALL; | |
355 | ||
4772eaeb PZ |
356 | /* Just flush everything. Experiments have shown that reducing the |
357 | * number of bits based on the write domains has little performance | |
358 | * impact. | |
359 | */ | |
360 | if (flush_domains) { | |
361 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
362 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
4772eaeb PZ |
363 | } |
364 | if (invalidate_domains) { | |
365 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
366 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
367 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
368 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
369 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
370 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
371 | /* | |
372 | * TLB invalidate requires a post-sync write. | |
373 | */ | |
374 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 375 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 PZ |
376 | |
377 | /* Workaround: we must issue a pipe_control with CS-stall bit | |
378 | * set before a pipe_control command that has the state cache | |
379 | * invalidate bit set. */ | |
380 | gen7_render_ring_cs_stall_wa(ring); | |
4772eaeb PZ |
381 | } |
382 | ||
383 | ret = intel_ring_begin(ring, 4); | |
384 | if (ret) | |
385 | return ret; | |
386 | ||
387 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
388 | intel_ring_emit(ring, flags); | |
b9e1faa7 | 389 | intel_ring_emit(ring, scratch_addr); |
4772eaeb PZ |
390 | intel_ring_emit(ring, 0); |
391 | intel_ring_advance(ring); | |
392 | ||
9688ecad | 393 | if (!invalidate_domains && flush_domains) |
fd3da6c9 RV |
394 | return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); |
395 | ||
4772eaeb PZ |
396 | return 0; |
397 | } | |
398 | ||
884ceace KG |
399 | static int |
400 | gen8_emit_pipe_control(struct intel_engine_cs *ring, | |
401 | u32 flags, u32 scratch_addr) | |
402 | { | |
403 | int ret; | |
404 | ||
405 | ret = intel_ring_begin(ring, 6); | |
406 | if (ret) | |
407 | return ret; | |
408 | ||
409 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); | |
410 | intel_ring_emit(ring, flags); | |
411 | intel_ring_emit(ring, scratch_addr); | |
412 | intel_ring_emit(ring, 0); | |
413 | intel_ring_emit(ring, 0); | |
414 | intel_ring_emit(ring, 0); | |
415 | intel_ring_advance(ring); | |
416 | ||
417 | return 0; | |
418 | } | |
419 | ||
a5f3d68e | 420 | static int |
a4872ba6 | 421 | gen8_render_ring_flush(struct intel_engine_cs *ring, |
a5f3d68e BW |
422 | u32 invalidate_domains, u32 flush_domains) |
423 | { | |
424 | u32 flags = 0; | |
18393f63 | 425 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
02c9f7e3 | 426 | int ret; |
a5f3d68e BW |
427 | |
428 | flags |= PIPE_CONTROL_CS_STALL; | |
429 | ||
430 | if (flush_domains) { | |
431 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
432 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
433 | } | |
434 | if (invalidate_domains) { | |
435 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
436 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
437 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
438 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
439 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
440 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
441 | flags |= PIPE_CONTROL_QW_WRITE; | |
442 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
02c9f7e3 KG |
443 | |
444 | /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ | |
445 | ret = gen8_emit_pipe_control(ring, | |
446 | PIPE_CONTROL_CS_STALL | | |
447 | PIPE_CONTROL_STALL_AT_SCOREBOARD, | |
448 | 0); | |
449 | if (ret) | |
450 | return ret; | |
a5f3d68e BW |
451 | } |
452 | ||
884ceace | 453 | return gen8_emit_pipe_control(ring, flags, scratch_addr); |
a5f3d68e BW |
454 | } |
455 | ||
a4872ba6 | 456 | static void ring_write_tail(struct intel_engine_cs *ring, |
297b0c5b | 457 | u32 value) |
d46eefa2 | 458 | { |
4640c4ff | 459 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
297b0c5b | 460 | I915_WRITE_TAIL(ring, value); |
d46eefa2 XH |
461 | } |
462 | ||
a4872ba6 | 463 | u64 intel_ring_get_active_head(struct intel_engine_cs *ring) |
8187a2b7 | 464 | { |
4640c4ff | 465 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
50877445 | 466 | u64 acthd; |
8187a2b7 | 467 | |
50877445 CW |
468 | if (INTEL_INFO(ring->dev)->gen >= 8) |
469 | acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base), | |
470 | RING_ACTHD_UDW(ring->mmio_base)); | |
471 | else if (INTEL_INFO(ring->dev)->gen >= 4) | |
472 | acthd = I915_READ(RING_ACTHD(ring->mmio_base)); | |
473 | else | |
474 | acthd = I915_READ(ACTHD); | |
475 | ||
476 | return acthd; | |
8187a2b7 ZN |
477 | } |
478 | ||
a4872ba6 | 479 | static void ring_setup_phys_status_page(struct intel_engine_cs *ring) |
035dc1e0 DV |
480 | { |
481 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
482 | u32 addr; | |
483 | ||
484 | addr = dev_priv->status_page_dmah->busaddr; | |
485 | if (INTEL_INFO(ring->dev)->gen >= 4) | |
486 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; | |
487 | I915_WRITE(HWS_PGA, addr); | |
488 | } | |
489 | ||
a4872ba6 | 490 | static bool stop_ring(struct intel_engine_cs *ring) |
8187a2b7 | 491 | { |
9991ae78 | 492 | struct drm_i915_private *dev_priv = to_i915(ring->dev); |
8187a2b7 | 493 | |
9991ae78 CW |
494 | if (!IS_GEN2(ring->dev)) { |
495 | I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); | |
403bdd10 DV |
496 | if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { |
497 | DRM_ERROR("%s : timed out trying to stop ring\n", ring->name); | |
9bec9b13 CW |
498 | /* Sometimes we observe that the idle flag is not |
499 | * set even though the ring is empty. So double | |
500 | * check before giving up. | |
501 | */ | |
502 | if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring)) | |
503 | return false; | |
9991ae78 CW |
504 | } |
505 | } | |
b7884eb4 | 506 | |
7f2ab699 | 507 | I915_WRITE_CTL(ring, 0); |
570ef608 | 508 | I915_WRITE_HEAD(ring, 0); |
78501eac | 509 | ring->write_tail(ring, 0); |
8187a2b7 | 510 | |
9991ae78 CW |
511 | if (!IS_GEN2(ring->dev)) { |
512 | (void)I915_READ_CTL(ring); | |
513 | I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); | |
514 | } | |
a51435a3 | 515 | |
9991ae78 CW |
516 | return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0; |
517 | } | |
8187a2b7 | 518 | |
a4872ba6 | 519 | static int init_ring_common(struct intel_engine_cs *ring) |
9991ae78 CW |
520 | { |
521 | struct drm_device *dev = ring->dev; | |
522 | struct drm_i915_private *dev_priv = dev->dev_private; | |
93b0a4e0 OM |
523 | struct intel_ringbuffer *ringbuf = ring->buffer; |
524 | struct drm_i915_gem_object *obj = ringbuf->obj; | |
9991ae78 CW |
525 | int ret = 0; |
526 | ||
527 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); | |
528 | ||
529 | if (!stop_ring(ring)) { | |
530 | /* G45 ring initialization often fails to reset head to zero */ | |
6fd0d56e CW |
531 | DRM_DEBUG_KMS("%s head not reset to zero " |
532 | "ctl %08x head %08x tail %08x start %08x\n", | |
533 | ring->name, | |
534 | I915_READ_CTL(ring), | |
535 | I915_READ_HEAD(ring), | |
536 | I915_READ_TAIL(ring), | |
537 | I915_READ_START(ring)); | |
8187a2b7 | 538 | |
9991ae78 | 539 | if (!stop_ring(ring)) { |
6fd0d56e CW |
540 | DRM_ERROR("failed to set %s head to zero " |
541 | "ctl %08x head %08x tail %08x start %08x\n", | |
542 | ring->name, | |
543 | I915_READ_CTL(ring), | |
544 | I915_READ_HEAD(ring), | |
545 | I915_READ_TAIL(ring), | |
546 | I915_READ_START(ring)); | |
9991ae78 CW |
547 | ret = -EIO; |
548 | goto out; | |
6fd0d56e | 549 | } |
8187a2b7 ZN |
550 | } |
551 | ||
9991ae78 CW |
552 | if (I915_NEED_GFX_HWS(dev)) |
553 | intel_ring_setup_status_page(ring); | |
554 | else | |
555 | ring_setup_phys_status_page(ring); | |
556 | ||
ece4a17d JK |
557 | /* Enforce ordering by reading HEAD register back */ |
558 | I915_READ_HEAD(ring); | |
559 | ||
0d8957c8 DV |
560 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
561 | * registers with the above sequence (the readback of the HEAD registers | |
562 | * also enforces ordering), otherwise the hw might lose the new ring | |
563 | * register values. */ | |
f343c5f6 | 564 | I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj)); |
7f2ab699 | 565 | I915_WRITE_CTL(ring, |
93b0a4e0 | 566 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 567 | | RING_VALID); |
8187a2b7 | 568 | |
8187a2b7 | 569 | /* If the head is still not zero, the ring is dead */ |
f01db988 | 570 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
f343c5f6 | 571 | I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) && |
f01db988 | 572 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { |
e74cfed5 | 573 | DRM_ERROR("%s initialization failed " |
48e48a0b CW |
574 | "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n", |
575 | ring->name, | |
576 | I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID, | |
577 | I915_READ_HEAD(ring), I915_READ_TAIL(ring), | |
578 | I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj)); | |
b7884eb4 DV |
579 | ret = -EIO; |
580 | goto out; | |
8187a2b7 ZN |
581 | } |
582 | ||
78501eac CW |
583 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
584 | i915_kernel_lost_context(ring->dev); | |
8187a2b7 | 585 | else { |
93b0a4e0 OM |
586 | ringbuf->head = I915_READ_HEAD(ring); |
587 | ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR; | |
64c58f2c | 588 | ringbuf->space = ring_space(ringbuf); |
93b0a4e0 | 589 | ringbuf->last_retired_head = -1; |
8187a2b7 | 590 | } |
1ec14ad3 | 591 | |
50f018df CW |
592 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); |
593 | ||
b7884eb4 | 594 | out: |
c8d9a590 | 595 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
596 | |
597 | return ret; | |
8187a2b7 ZN |
598 | } |
599 | ||
c6df541c | 600 | static int |
a4872ba6 | 601 | init_pipe_control(struct intel_engine_cs *ring) |
c6df541c | 602 | { |
c6df541c CW |
603 | int ret; |
604 | ||
0d1aacac | 605 | if (ring->scratch.obj) |
c6df541c CW |
606 | return 0; |
607 | ||
0d1aacac CW |
608 | ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096); |
609 | if (ring->scratch.obj == NULL) { | |
c6df541c CW |
610 | DRM_ERROR("Failed to allocate seqno page\n"); |
611 | ret = -ENOMEM; | |
612 | goto err; | |
613 | } | |
e4ffd173 | 614 | |
a9cc726c DV |
615 | ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC); |
616 | if (ret) | |
617 | goto err_unref; | |
c6df541c | 618 | |
1ec9e26d | 619 | ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0); |
c6df541c CW |
620 | if (ret) |
621 | goto err_unref; | |
622 | ||
0d1aacac CW |
623 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj); |
624 | ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl)); | |
625 | if (ring->scratch.cpu_page == NULL) { | |
56b085a0 | 626 | ret = -ENOMEM; |
c6df541c | 627 | goto err_unpin; |
56b085a0 | 628 | } |
c6df541c | 629 | |
2b1086cc | 630 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
0d1aacac | 631 | ring->name, ring->scratch.gtt_offset); |
c6df541c CW |
632 | return 0; |
633 | ||
634 | err_unpin: | |
d7f46fc4 | 635 | i915_gem_object_ggtt_unpin(ring->scratch.obj); |
c6df541c | 636 | err_unref: |
0d1aacac | 637 | drm_gem_object_unreference(&ring->scratch.obj->base); |
c6df541c | 638 | err: |
c6df541c CW |
639 | return ret; |
640 | } | |
641 | ||
a4872ba6 | 642 | static int init_render_ring(struct intel_engine_cs *ring) |
8187a2b7 | 643 | { |
78501eac | 644 | struct drm_device *dev = ring->dev; |
1ec14ad3 | 645 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 646 | int ret = init_ring_common(ring); |
9c33baa6 KZ |
647 | if (ret) |
648 | return ret; | |
a69ffdbf | 649 | |
61a563a2 AG |
650 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
651 | if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7) | |
6b26c86d | 652 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
653 | |
654 | /* We need to disable the AsyncFlip performance optimisations in order | |
655 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
656 | * programmed to '1' on all products. | |
8693a824 | 657 | * |
b3f797ac | 658 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv |
1c8c38c5 CW |
659 | */ |
660 | if (INTEL_INFO(dev)->gen >= 6) | |
661 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
662 | ||
f05bb0c7 | 663 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 664 | /* WaEnableFlushTlbInvalidationMode:snb */ |
f05bb0c7 CW |
665 | if (INTEL_INFO(dev)->gen == 6) |
666 | I915_WRITE(GFX_MODE, | |
aa83e30d | 667 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 668 | |
01fa0302 | 669 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
1c8c38c5 CW |
670 | if (IS_GEN7(dev)) |
671 | I915_WRITE(GFX_MODE_GEN7, | |
01fa0302 | 672 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 673 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 674 | |
8d315287 | 675 | if (INTEL_INFO(dev)->gen >= 5) { |
c6df541c CW |
676 | ret = init_pipe_control(ring); |
677 | if (ret) | |
678 | return ret; | |
679 | } | |
680 | ||
5e13a0c5 | 681 | if (IS_GEN6(dev)) { |
3a69ddd6 KG |
682 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
683 | * "If this bit is set, STCunit will have LRA as replacement | |
684 | * policy. [...] This bit must be reset. LRA replacement | |
685 | * policy is not supported." | |
686 | */ | |
687 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 688 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
689 | } |
690 | ||
6b26c86d DV |
691 | if (INTEL_INFO(dev)->gen >= 6) |
692 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); | |
84f9f938 | 693 | |
040d2baa | 694 | if (HAS_L3_DPF(dev)) |
35a85ac6 | 695 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
15b9f80e | 696 | |
8187a2b7 ZN |
697 | return ret; |
698 | } | |
699 | ||
a4872ba6 | 700 | static void render_ring_cleanup(struct intel_engine_cs *ring) |
c6df541c | 701 | { |
b45305fc | 702 | struct drm_device *dev = ring->dev; |
3e78998a BW |
703 | struct drm_i915_private *dev_priv = dev->dev_private; |
704 | ||
705 | if (dev_priv->semaphore_obj) { | |
706 | i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj); | |
707 | drm_gem_object_unreference(&dev_priv->semaphore_obj->base); | |
708 | dev_priv->semaphore_obj = NULL; | |
709 | } | |
b45305fc | 710 | |
0d1aacac | 711 | if (ring->scratch.obj == NULL) |
c6df541c CW |
712 | return; |
713 | ||
0d1aacac CW |
714 | if (INTEL_INFO(dev)->gen >= 5) { |
715 | kunmap(sg_page(ring->scratch.obj->pages->sgl)); | |
d7f46fc4 | 716 | i915_gem_object_ggtt_unpin(ring->scratch.obj); |
0d1aacac | 717 | } |
aaf8a516 | 718 | |
0d1aacac CW |
719 | drm_gem_object_unreference(&ring->scratch.obj->base); |
720 | ring->scratch.obj = NULL; | |
c6df541c CW |
721 | } |
722 | ||
3e78998a BW |
723 | static int gen8_rcs_signal(struct intel_engine_cs *signaller, |
724 | unsigned int num_dwords) | |
725 | { | |
726 | #define MBOX_UPDATE_DWORDS 8 | |
727 | struct drm_device *dev = signaller->dev; | |
728 | struct drm_i915_private *dev_priv = dev->dev_private; | |
729 | struct intel_engine_cs *waiter; | |
730 | int i, ret, num_rings; | |
731 | ||
732 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
733 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; | |
734 | #undef MBOX_UPDATE_DWORDS | |
735 | ||
736 | ret = intel_ring_begin(signaller, num_dwords); | |
737 | if (ret) | |
738 | return ret; | |
739 | ||
740 | for_each_ring(waiter, dev_priv, i) { | |
741 | u64 gtt_offset = signaller->semaphore.signal_ggtt[i]; | |
742 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) | |
743 | continue; | |
744 | ||
745 | intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6)); | |
746 | intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB | | |
747 | PIPE_CONTROL_QW_WRITE | | |
748 | PIPE_CONTROL_FLUSH_ENABLE); | |
749 | intel_ring_emit(signaller, lower_32_bits(gtt_offset)); | |
750 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
751 | intel_ring_emit(signaller, signaller->outstanding_lazy_seqno); | |
752 | intel_ring_emit(signaller, 0); | |
753 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | | |
754 | MI_SEMAPHORE_TARGET(waiter->id)); | |
755 | intel_ring_emit(signaller, 0); | |
756 | } | |
757 | ||
758 | return 0; | |
759 | } | |
760 | ||
761 | static int gen8_xcs_signal(struct intel_engine_cs *signaller, | |
762 | unsigned int num_dwords) | |
763 | { | |
764 | #define MBOX_UPDATE_DWORDS 6 | |
765 | struct drm_device *dev = signaller->dev; | |
766 | struct drm_i915_private *dev_priv = dev->dev_private; | |
767 | struct intel_engine_cs *waiter; | |
768 | int i, ret, num_rings; | |
769 | ||
770 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
771 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; | |
772 | #undef MBOX_UPDATE_DWORDS | |
773 | ||
774 | ret = intel_ring_begin(signaller, num_dwords); | |
775 | if (ret) | |
776 | return ret; | |
777 | ||
778 | for_each_ring(waiter, dev_priv, i) { | |
779 | u64 gtt_offset = signaller->semaphore.signal_ggtt[i]; | |
780 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) | |
781 | continue; | |
782 | ||
783 | intel_ring_emit(signaller, (MI_FLUSH_DW + 1) | | |
784 | MI_FLUSH_DW_OP_STOREDW); | |
785 | intel_ring_emit(signaller, lower_32_bits(gtt_offset) | | |
786 | MI_FLUSH_DW_USE_GTT); | |
787 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
788 | intel_ring_emit(signaller, signaller->outstanding_lazy_seqno); | |
789 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | | |
790 | MI_SEMAPHORE_TARGET(waiter->id)); | |
791 | intel_ring_emit(signaller, 0); | |
792 | } | |
793 | ||
794 | return 0; | |
795 | } | |
796 | ||
a4872ba6 | 797 | static int gen6_signal(struct intel_engine_cs *signaller, |
024a43e1 | 798 | unsigned int num_dwords) |
1ec14ad3 | 799 | { |
024a43e1 BW |
800 | struct drm_device *dev = signaller->dev; |
801 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 802 | struct intel_engine_cs *useless; |
a1444b79 | 803 | int i, ret, num_rings; |
78325f2d | 804 | |
a1444b79 BW |
805 | #define MBOX_UPDATE_DWORDS 3 |
806 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
807 | num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2); | |
808 | #undef MBOX_UPDATE_DWORDS | |
024a43e1 BW |
809 | |
810 | ret = intel_ring_begin(signaller, num_dwords); | |
811 | if (ret) | |
812 | return ret; | |
024a43e1 | 813 | |
78325f2d BW |
814 | for_each_ring(useless, dev_priv, i) { |
815 | u32 mbox_reg = signaller->semaphore.mbox.signal[i]; | |
816 | if (mbox_reg != GEN6_NOSYNC) { | |
817 | intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1)); | |
818 | intel_ring_emit(signaller, mbox_reg); | |
819 | intel_ring_emit(signaller, signaller->outstanding_lazy_seqno); | |
78325f2d BW |
820 | } |
821 | } | |
024a43e1 | 822 | |
a1444b79 BW |
823 | /* If num_dwords was rounded, make sure the tail pointer is correct */ |
824 | if (num_rings % 2 == 0) | |
825 | intel_ring_emit(signaller, MI_NOOP); | |
826 | ||
024a43e1 | 827 | return 0; |
1ec14ad3 CW |
828 | } |
829 | ||
c8c99b0f BW |
830 | /** |
831 | * gen6_add_request - Update the semaphore mailbox registers | |
832 | * | |
833 | * @ring - ring that is adding a request | |
834 | * @seqno - return seqno stuck into the ring | |
835 | * | |
836 | * Update the mailbox registers in the *other* rings with the current seqno. | |
837 | * This acts like a signal in the canonical semaphore. | |
838 | */ | |
1ec14ad3 | 839 | static int |
a4872ba6 | 840 | gen6_add_request(struct intel_engine_cs *ring) |
1ec14ad3 | 841 | { |
024a43e1 | 842 | int ret; |
52ed2325 | 843 | |
707d9cf9 BW |
844 | if (ring->semaphore.signal) |
845 | ret = ring->semaphore.signal(ring, 4); | |
846 | else | |
847 | ret = intel_ring_begin(ring, 4); | |
848 | ||
1ec14ad3 CW |
849 | if (ret) |
850 | return ret; | |
851 | ||
1ec14ad3 CW |
852 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
853 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1823521d | 854 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
1ec14ad3 | 855 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
09246732 | 856 | __intel_ring_advance(ring); |
1ec14ad3 | 857 | |
1ec14ad3 CW |
858 | return 0; |
859 | } | |
860 | ||
f72b3435 MK |
861 | static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, |
862 | u32 seqno) | |
863 | { | |
864 | struct drm_i915_private *dev_priv = dev->dev_private; | |
865 | return dev_priv->last_seqno < seqno; | |
866 | } | |
867 | ||
c8c99b0f BW |
868 | /** |
869 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
870 | * | |
871 | * @waiter - ring that is waiting | |
872 | * @signaller - ring which has, or will signal | |
873 | * @seqno - seqno which the waiter will block on | |
874 | */ | |
5ee426ca BW |
875 | |
876 | static int | |
877 | gen8_ring_sync(struct intel_engine_cs *waiter, | |
878 | struct intel_engine_cs *signaller, | |
879 | u32 seqno) | |
880 | { | |
881 | struct drm_i915_private *dev_priv = waiter->dev->dev_private; | |
882 | int ret; | |
883 | ||
884 | ret = intel_ring_begin(waiter, 4); | |
885 | if (ret) | |
886 | return ret; | |
887 | ||
888 | intel_ring_emit(waiter, MI_SEMAPHORE_WAIT | | |
889 | MI_SEMAPHORE_GLOBAL_GTT | | |
bae4fcd2 | 890 | MI_SEMAPHORE_POLL | |
5ee426ca BW |
891 | MI_SEMAPHORE_SAD_GTE_SDD); |
892 | intel_ring_emit(waiter, seqno); | |
893 | intel_ring_emit(waiter, | |
894 | lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); | |
895 | intel_ring_emit(waiter, | |
896 | upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); | |
897 | intel_ring_advance(waiter); | |
898 | return 0; | |
899 | } | |
900 | ||
c8c99b0f | 901 | static int |
a4872ba6 OM |
902 | gen6_ring_sync(struct intel_engine_cs *waiter, |
903 | struct intel_engine_cs *signaller, | |
686cb5f9 | 904 | u32 seqno) |
1ec14ad3 | 905 | { |
c8c99b0f BW |
906 | u32 dw1 = MI_SEMAPHORE_MBOX | |
907 | MI_SEMAPHORE_COMPARE | | |
908 | MI_SEMAPHORE_REGISTER; | |
ebc348b2 BW |
909 | u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id]; |
910 | int ret; | |
1ec14ad3 | 911 | |
1500f7ea BW |
912 | /* Throughout all of the GEM code, seqno passed implies our current |
913 | * seqno is >= the last seqno executed. However for hardware the | |
914 | * comparison is strictly greater than. | |
915 | */ | |
916 | seqno -= 1; | |
917 | ||
ebc348b2 | 918 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
686cb5f9 | 919 | |
c8c99b0f | 920 | ret = intel_ring_begin(waiter, 4); |
1ec14ad3 CW |
921 | if (ret) |
922 | return ret; | |
923 | ||
f72b3435 MK |
924 | /* If seqno wrap happened, omit the wait with no-ops */ |
925 | if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) { | |
ebc348b2 | 926 | intel_ring_emit(waiter, dw1 | wait_mbox); |
f72b3435 MK |
927 | intel_ring_emit(waiter, seqno); |
928 | intel_ring_emit(waiter, 0); | |
929 | intel_ring_emit(waiter, MI_NOOP); | |
930 | } else { | |
931 | intel_ring_emit(waiter, MI_NOOP); | |
932 | intel_ring_emit(waiter, MI_NOOP); | |
933 | intel_ring_emit(waiter, MI_NOOP); | |
934 | intel_ring_emit(waiter, MI_NOOP); | |
935 | } | |
c8c99b0f | 936 | intel_ring_advance(waiter); |
1ec14ad3 CW |
937 | |
938 | return 0; | |
939 | } | |
940 | ||
c6df541c CW |
941 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
942 | do { \ | |
fcbc34e4 KG |
943 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
944 | PIPE_CONTROL_DEPTH_STALL); \ | |
c6df541c CW |
945 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
946 | intel_ring_emit(ring__, 0); \ | |
947 | intel_ring_emit(ring__, 0); \ | |
948 | } while (0) | |
949 | ||
950 | static int | |
a4872ba6 | 951 | pc_render_add_request(struct intel_engine_cs *ring) |
c6df541c | 952 | { |
18393f63 | 953 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
c6df541c CW |
954 | int ret; |
955 | ||
956 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently | |
957 | * incoherent with writes to memory, i.e. completely fubar, | |
958 | * so we need to use PIPE_NOTIFY instead. | |
959 | * | |
960 | * However, we also need to workaround the qword write | |
961 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to | |
962 | * memory before requesting an interrupt. | |
963 | */ | |
964 | ret = intel_ring_begin(ring, 32); | |
965 | if (ret) | |
966 | return ret; | |
967 | ||
fcbc34e4 | 968 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
969 | PIPE_CONTROL_WRITE_FLUSH | |
970 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); | |
0d1aacac | 971 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
1823521d | 972 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
c6df541c CW |
973 | intel_ring_emit(ring, 0); |
974 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
18393f63 | 975 | scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */ |
c6df541c | 976 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 977 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 978 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 979 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 980 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 981 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 982 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 983 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 984 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
a71d8d94 | 985 | |
fcbc34e4 | 986 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
987 | PIPE_CONTROL_WRITE_FLUSH | |
988 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | | |
c6df541c | 989 | PIPE_CONTROL_NOTIFY); |
0d1aacac | 990 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
1823521d | 991 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
c6df541c | 992 | intel_ring_emit(ring, 0); |
09246732 | 993 | __intel_ring_advance(ring); |
c6df541c | 994 | |
c6df541c CW |
995 | return 0; |
996 | } | |
997 | ||
4cd53c0c | 998 | static u32 |
a4872ba6 | 999 | gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
4cd53c0c | 1000 | { |
4cd53c0c DV |
1001 | /* Workaround to force correct ordering between irq and seqno writes on |
1002 | * ivb (and maybe also on snb) by reading from a CS register (like | |
1003 | * ACTHD) before reading the status page. */ | |
50877445 CW |
1004 | if (!lazy_coherency) { |
1005 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
1006 | POSTING_READ(RING_ACTHD(ring->mmio_base)); | |
1007 | } | |
1008 | ||
4cd53c0c DV |
1009 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
1010 | } | |
1011 | ||
8187a2b7 | 1012 | static u32 |
a4872ba6 | 1013 | ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
8187a2b7 | 1014 | { |
1ec14ad3 CW |
1015 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
1016 | } | |
1017 | ||
b70ec5bf | 1018 | static void |
a4872ba6 | 1019 | ring_set_seqno(struct intel_engine_cs *ring, u32 seqno) |
b70ec5bf MK |
1020 | { |
1021 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); | |
1022 | } | |
1023 | ||
c6df541c | 1024 | static u32 |
a4872ba6 | 1025 | pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
c6df541c | 1026 | { |
0d1aacac | 1027 | return ring->scratch.cpu_page[0]; |
c6df541c CW |
1028 | } |
1029 | ||
b70ec5bf | 1030 | static void |
a4872ba6 | 1031 | pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno) |
b70ec5bf | 1032 | { |
0d1aacac | 1033 | ring->scratch.cpu_page[0] = seqno; |
b70ec5bf MK |
1034 | } |
1035 | ||
e48d8634 | 1036 | static bool |
a4872ba6 | 1037 | gen5_ring_get_irq(struct intel_engine_cs *ring) |
e48d8634 DV |
1038 | { |
1039 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1040 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1041 | unsigned long flags; |
e48d8634 DV |
1042 | |
1043 | if (!dev->irq_enabled) | |
1044 | return false; | |
1045 | ||
7338aefa | 1046 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
43eaea13 | 1047 | if (ring->irq_refcount++ == 0) |
480c8033 | 1048 | gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
7338aefa | 1049 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
1050 | |
1051 | return true; | |
1052 | } | |
1053 | ||
1054 | static void | |
a4872ba6 | 1055 | gen5_ring_put_irq(struct intel_engine_cs *ring) |
e48d8634 DV |
1056 | { |
1057 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1058 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1059 | unsigned long flags; |
e48d8634 | 1060 | |
7338aefa | 1061 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
43eaea13 | 1062 | if (--ring->irq_refcount == 0) |
480c8033 | 1063 | gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
7338aefa | 1064 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
1065 | } |
1066 | ||
b13c2b96 | 1067 | static bool |
a4872ba6 | 1068 | i9xx_ring_get_irq(struct intel_engine_cs *ring) |
62fdfeaf | 1069 | { |
78501eac | 1070 | struct drm_device *dev = ring->dev; |
4640c4ff | 1071 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1072 | unsigned long flags; |
62fdfeaf | 1073 | |
b13c2b96 CW |
1074 | if (!dev->irq_enabled) |
1075 | return false; | |
1076 | ||
7338aefa | 1077 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1078 | if (ring->irq_refcount++ == 0) { |
f637fde4 DV |
1079 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
1080 | I915_WRITE(IMR, dev_priv->irq_mask); | |
1081 | POSTING_READ(IMR); | |
1082 | } | |
7338aefa | 1083 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
b13c2b96 CW |
1084 | |
1085 | return true; | |
62fdfeaf EA |
1086 | } |
1087 | ||
8187a2b7 | 1088 | static void |
a4872ba6 | 1089 | i9xx_ring_put_irq(struct intel_engine_cs *ring) |
62fdfeaf | 1090 | { |
78501eac | 1091 | struct drm_device *dev = ring->dev; |
4640c4ff | 1092 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1093 | unsigned long flags; |
62fdfeaf | 1094 | |
7338aefa | 1095 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1096 | if (--ring->irq_refcount == 0) { |
f637fde4 DV |
1097 | dev_priv->irq_mask |= ring->irq_enable_mask; |
1098 | I915_WRITE(IMR, dev_priv->irq_mask); | |
1099 | POSTING_READ(IMR); | |
1100 | } | |
7338aefa | 1101 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
62fdfeaf EA |
1102 | } |
1103 | ||
c2798b19 | 1104 | static bool |
a4872ba6 | 1105 | i8xx_ring_get_irq(struct intel_engine_cs *ring) |
c2798b19 CW |
1106 | { |
1107 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1108 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1109 | unsigned long flags; |
c2798b19 CW |
1110 | |
1111 | if (!dev->irq_enabled) | |
1112 | return false; | |
1113 | ||
7338aefa | 1114 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1115 | if (ring->irq_refcount++ == 0) { |
c2798b19 CW |
1116 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
1117 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
1118 | POSTING_READ16(IMR); | |
1119 | } | |
7338aefa | 1120 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
1121 | |
1122 | return true; | |
1123 | } | |
1124 | ||
1125 | static void | |
a4872ba6 | 1126 | i8xx_ring_put_irq(struct intel_engine_cs *ring) |
c2798b19 CW |
1127 | { |
1128 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1129 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1130 | unsigned long flags; |
c2798b19 | 1131 | |
7338aefa | 1132 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1133 | if (--ring->irq_refcount == 0) { |
c2798b19 CW |
1134 | dev_priv->irq_mask |= ring->irq_enable_mask; |
1135 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
1136 | POSTING_READ16(IMR); | |
1137 | } | |
7338aefa | 1138 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
1139 | } |
1140 | ||
a4872ba6 | 1141 | void intel_ring_setup_status_page(struct intel_engine_cs *ring) |
8187a2b7 | 1142 | { |
4593010b | 1143 | struct drm_device *dev = ring->dev; |
4640c4ff | 1144 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
4593010b EA |
1145 | u32 mmio = 0; |
1146 | ||
1147 | /* The ring status page addresses are no longer next to the rest of | |
1148 | * the ring registers as of gen7. | |
1149 | */ | |
1150 | if (IS_GEN7(dev)) { | |
1151 | switch (ring->id) { | |
96154f2f | 1152 | case RCS: |
4593010b EA |
1153 | mmio = RENDER_HWS_PGA_GEN7; |
1154 | break; | |
96154f2f | 1155 | case BCS: |
4593010b EA |
1156 | mmio = BLT_HWS_PGA_GEN7; |
1157 | break; | |
77fe2ff3 ZY |
1158 | /* |
1159 | * VCS2 actually doesn't exist on Gen7. Only shut up | |
1160 | * gcc switch check warning | |
1161 | */ | |
1162 | case VCS2: | |
96154f2f | 1163 | case VCS: |
4593010b EA |
1164 | mmio = BSD_HWS_PGA_GEN7; |
1165 | break; | |
4a3dd19d | 1166 | case VECS: |
9a8a2213 BW |
1167 | mmio = VEBOX_HWS_PGA_GEN7; |
1168 | break; | |
4593010b EA |
1169 | } |
1170 | } else if (IS_GEN6(ring->dev)) { | |
1171 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); | |
1172 | } else { | |
eb0d4b75 | 1173 | /* XXX: gen8 returns to sanity */ |
4593010b EA |
1174 | mmio = RING_HWS_PGA(ring->mmio_base); |
1175 | } | |
1176 | ||
78501eac CW |
1177 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
1178 | POSTING_READ(mmio); | |
884020bf | 1179 | |
dc616b89 DL |
1180 | /* |
1181 | * Flush the TLB for this page | |
1182 | * | |
1183 | * FIXME: These two bits have disappeared on gen8, so a question | |
1184 | * arises: do we still need this and if so how should we go about | |
1185 | * invalidating the TLB? | |
1186 | */ | |
1187 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) { | |
884020bf | 1188 | u32 reg = RING_INSTPM(ring->mmio_base); |
02f6a1e7 NKK |
1189 | |
1190 | /* ring should be idle before issuing a sync flush*/ | |
1191 | WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); | |
1192 | ||
884020bf CW |
1193 | I915_WRITE(reg, |
1194 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
1195 | INSTPM_SYNC_FLUSH)); | |
1196 | if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, | |
1197 | 1000)) | |
1198 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", | |
1199 | ring->name); | |
1200 | } | |
8187a2b7 ZN |
1201 | } |
1202 | ||
b72f3acb | 1203 | static int |
a4872ba6 | 1204 | bsd_ring_flush(struct intel_engine_cs *ring, |
78501eac CW |
1205 | u32 invalidate_domains, |
1206 | u32 flush_domains) | |
d1b851fc | 1207 | { |
b72f3acb CW |
1208 | int ret; |
1209 | ||
b72f3acb CW |
1210 | ret = intel_ring_begin(ring, 2); |
1211 | if (ret) | |
1212 | return ret; | |
1213 | ||
1214 | intel_ring_emit(ring, MI_FLUSH); | |
1215 | intel_ring_emit(ring, MI_NOOP); | |
1216 | intel_ring_advance(ring); | |
1217 | return 0; | |
d1b851fc ZN |
1218 | } |
1219 | ||
3cce469c | 1220 | static int |
a4872ba6 | 1221 | i9xx_add_request(struct intel_engine_cs *ring) |
d1b851fc | 1222 | { |
3cce469c CW |
1223 | int ret; |
1224 | ||
1225 | ret = intel_ring_begin(ring, 4); | |
1226 | if (ret) | |
1227 | return ret; | |
6f392d54 | 1228 | |
3cce469c CW |
1229 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
1230 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1823521d | 1231 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
3cce469c | 1232 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
09246732 | 1233 | __intel_ring_advance(ring); |
d1b851fc | 1234 | |
3cce469c | 1235 | return 0; |
d1b851fc ZN |
1236 | } |
1237 | ||
0f46832f | 1238 | static bool |
a4872ba6 | 1239 | gen6_ring_get_irq(struct intel_engine_cs *ring) |
0f46832f CW |
1240 | { |
1241 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1242 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1243 | unsigned long flags; |
0f46832f CW |
1244 | |
1245 | if (!dev->irq_enabled) | |
1246 | return false; | |
1247 | ||
7338aefa | 1248 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1249 | if (ring->irq_refcount++ == 0) { |
040d2baa | 1250 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
cc609d5d BW |
1251 | I915_WRITE_IMR(ring, |
1252 | ~(ring->irq_enable_mask | | |
35a85ac6 | 1253 | GT_PARITY_ERROR(dev))); |
15b9f80e BW |
1254 | else |
1255 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
480c8033 | 1256 | gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
0f46832f | 1257 | } |
7338aefa | 1258 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
0f46832f CW |
1259 | |
1260 | return true; | |
1261 | } | |
1262 | ||
1263 | static void | |
a4872ba6 | 1264 | gen6_ring_put_irq(struct intel_engine_cs *ring) |
0f46832f CW |
1265 | { |
1266 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1267 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1268 | unsigned long flags; |
0f46832f | 1269 | |
7338aefa | 1270 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1271 | if (--ring->irq_refcount == 0) { |
040d2baa | 1272 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
35a85ac6 | 1273 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
15b9f80e BW |
1274 | else |
1275 | I915_WRITE_IMR(ring, ~0); | |
480c8033 | 1276 | gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
1ec14ad3 | 1277 | } |
7338aefa | 1278 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
d1b851fc ZN |
1279 | } |
1280 | ||
a19d2933 | 1281 | static bool |
a4872ba6 | 1282 | hsw_vebox_get_irq(struct intel_engine_cs *ring) |
a19d2933 BW |
1283 | { |
1284 | struct drm_device *dev = ring->dev; | |
1285 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1286 | unsigned long flags; | |
1287 | ||
1288 | if (!dev->irq_enabled) | |
1289 | return false; | |
1290 | ||
59cdb63d | 1291 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1292 | if (ring->irq_refcount++ == 0) { |
a19d2933 | 1293 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
480c8033 | 1294 | gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask); |
a19d2933 | 1295 | } |
59cdb63d | 1296 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1297 | |
1298 | return true; | |
1299 | } | |
1300 | ||
1301 | static void | |
a4872ba6 | 1302 | hsw_vebox_put_irq(struct intel_engine_cs *ring) |
a19d2933 BW |
1303 | { |
1304 | struct drm_device *dev = ring->dev; | |
1305 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1306 | unsigned long flags; | |
1307 | ||
1308 | if (!dev->irq_enabled) | |
1309 | return; | |
1310 | ||
59cdb63d | 1311 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1312 | if (--ring->irq_refcount == 0) { |
a19d2933 | 1313 | I915_WRITE_IMR(ring, ~0); |
480c8033 | 1314 | gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask); |
a19d2933 | 1315 | } |
59cdb63d | 1316 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1317 | } |
1318 | ||
abd58f01 | 1319 | static bool |
a4872ba6 | 1320 | gen8_ring_get_irq(struct intel_engine_cs *ring) |
abd58f01 BW |
1321 | { |
1322 | struct drm_device *dev = ring->dev; | |
1323 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1324 | unsigned long flags; | |
1325 | ||
1326 | if (!dev->irq_enabled) | |
1327 | return false; | |
1328 | ||
1329 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1330 | if (ring->irq_refcount++ == 0) { | |
1331 | if (HAS_L3_DPF(dev) && ring->id == RCS) { | |
1332 | I915_WRITE_IMR(ring, | |
1333 | ~(ring->irq_enable_mask | | |
1334 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); | |
1335 | } else { | |
1336 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
1337 | } | |
1338 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1339 | } | |
1340 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1341 | ||
1342 | return true; | |
1343 | } | |
1344 | ||
1345 | static void | |
a4872ba6 | 1346 | gen8_ring_put_irq(struct intel_engine_cs *ring) |
abd58f01 BW |
1347 | { |
1348 | struct drm_device *dev = ring->dev; | |
1349 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1350 | unsigned long flags; | |
1351 | ||
1352 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1353 | if (--ring->irq_refcount == 0) { | |
1354 | if (HAS_L3_DPF(dev) && ring->id == RCS) { | |
1355 | I915_WRITE_IMR(ring, | |
1356 | ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); | |
1357 | } else { | |
1358 | I915_WRITE_IMR(ring, ~0); | |
1359 | } | |
1360 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1361 | } | |
1362 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1363 | } | |
1364 | ||
d1b851fc | 1365 | static int |
a4872ba6 | 1366 | i965_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 1367 | u64 offset, u32 length, |
d7d4eedd | 1368 | unsigned flags) |
d1b851fc | 1369 | { |
e1f99ce6 | 1370 | int ret; |
78501eac | 1371 | |
e1f99ce6 CW |
1372 | ret = intel_ring_begin(ring, 2); |
1373 | if (ret) | |
1374 | return ret; | |
1375 | ||
78501eac | 1376 | intel_ring_emit(ring, |
65f56876 CW |
1377 | MI_BATCH_BUFFER_START | |
1378 | MI_BATCH_GTT | | |
d7d4eedd | 1379 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
c4e7a414 | 1380 | intel_ring_emit(ring, offset); |
78501eac CW |
1381 | intel_ring_advance(ring); |
1382 | ||
d1b851fc ZN |
1383 | return 0; |
1384 | } | |
1385 | ||
b45305fc DV |
1386 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1387 | #define I830_BATCH_LIMIT (256*1024) | |
8187a2b7 | 1388 | static int |
a4872ba6 | 1389 | i830_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 1390 | u64 offset, u32 len, |
d7d4eedd | 1391 | unsigned flags) |
62fdfeaf | 1392 | { |
c4e7a414 | 1393 | int ret; |
62fdfeaf | 1394 | |
b45305fc DV |
1395 | if (flags & I915_DISPATCH_PINNED) { |
1396 | ret = intel_ring_begin(ring, 4); | |
1397 | if (ret) | |
1398 | return ret; | |
62fdfeaf | 1399 | |
b45305fc DV |
1400 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
1401 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); | |
1402 | intel_ring_emit(ring, offset + len - 8); | |
1403 | intel_ring_emit(ring, MI_NOOP); | |
1404 | intel_ring_advance(ring); | |
1405 | } else { | |
0d1aacac | 1406 | u32 cs_offset = ring->scratch.gtt_offset; |
b45305fc DV |
1407 | |
1408 | if (len > I830_BATCH_LIMIT) | |
1409 | return -ENOSPC; | |
1410 | ||
1411 | ret = intel_ring_begin(ring, 9+3); | |
1412 | if (ret) | |
1413 | return ret; | |
1414 | /* Blit the batch (which has now all relocs applied) to the stable batch | |
1415 | * scratch bo area (so that the CS never stumbles over its tlb | |
1416 | * invalidation bug) ... */ | |
1417 | intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD | | |
1418 | XY_SRC_COPY_BLT_WRITE_ALPHA | | |
1419 | XY_SRC_COPY_BLT_WRITE_RGB); | |
1420 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096); | |
1421 | intel_ring_emit(ring, 0); | |
1422 | intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024); | |
1423 | intel_ring_emit(ring, cs_offset); | |
1424 | intel_ring_emit(ring, 0); | |
1425 | intel_ring_emit(ring, 4096); | |
1426 | intel_ring_emit(ring, offset); | |
1427 | intel_ring_emit(ring, MI_FLUSH); | |
1428 | ||
1429 | /* ... and execute it. */ | |
1430 | intel_ring_emit(ring, MI_BATCH_BUFFER); | |
1431 | intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); | |
1432 | intel_ring_emit(ring, cs_offset + len - 8); | |
1433 | intel_ring_advance(ring); | |
1434 | } | |
e1f99ce6 | 1435 | |
fb3256da DV |
1436 | return 0; |
1437 | } | |
1438 | ||
1439 | static int | |
a4872ba6 | 1440 | i915_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 1441 | u64 offset, u32 len, |
d7d4eedd | 1442 | unsigned flags) |
fb3256da DV |
1443 | { |
1444 | int ret; | |
1445 | ||
1446 | ret = intel_ring_begin(ring, 2); | |
1447 | if (ret) | |
1448 | return ret; | |
1449 | ||
65f56876 | 1450 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
d7d4eedd | 1451 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
c4e7a414 | 1452 | intel_ring_advance(ring); |
62fdfeaf | 1453 | |
62fdfeaf EA |
1454 | return 0; |
1455 | } | |
1456 | ||
a4872ba6 | 1457 | static void cleanup_status_page(struct intel_engine_cs *ring) |
62fdfeaf | 1458 | { |
05394f39 | 1459 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1460 | |
8187a2b7 ZN |
1461 | obj = ring->status_page.obj; |
1462 | if (obj == NULL) | |
62fdfeaf | 1463 | return; |
62fdfeaf | 1464 | |
9da3da66 | 1465 | kunmap(sg_page(obj->pages->sgl)); |
d7f46fc4 | 1466 | i915_gem_object_ggtt_unpin(obj); |
05394f39 | 1467 | drm_gem_object_unreference(&obj->base); |
8187a2b7 | 1468 | ring->status_page.obj = NULL; |
62fdfeaf EA |
1469 | } |
1470 | ||
a4872ba6 | 1471 | static int init_status_page(struct intel_engine_cs *ring) |
62fdfeaf | 1472 | { |
05394f39 | 1473 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1474 | |
e3efda49 | 1475 | if ((obj = ring->status_page.obj) == NULL) { |
1f767e02 | 1476 | unsigned flags; |
e3efda49 | 1477 | int ret; |
e4ffd173 | 1478 | |
e3efda49 CW |
1479 | obj = i915_gem_alloc_object(ring->dev, 4096); |
1480 | if (obj == NULL) { | |
1481 | DRM_ERROR("Failed to allocate status page\n"); | |
1482 | return -ENOMEM; | |
1483 | } | |
62fdfeaf | 1484 | |
e3efda49 CW |
1485 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
1486 | if (ret) | |
1487 | goto err_unref; | |
1488 | ||
1f767e02 CW |
1489 | flags = 0; |
1490 | if (!HAS_LLC(ring->dev)) | |
1491 | /* On g33, we cannot place HWS above 256MiB, so | |
1492 | * restrict its pinning to the low mappable arena. | |
1493 | * Though this restriction is not documented for | |
1494 | * gen4, gen5, or byt, they also behave similarly | |
1495 | * and hang if the HWS is placed at the top of the | |
1496 | * GTT. To generalise, it appears that all !llc | |
1497 | * platforms have issues with us placing the HWS | |
1498 | * above the mappable region (even though we never | |
1499 | * actualy map it). | |
1500 | */ | |
1501 | flags |= PIN_MAPPABLE; | |
1502 | ret = i915_gem_obj_ggtt_pin(obj, 4096, flags); | |
e3efda49 CW |
1503 | if (ret) { |
1504 | err_unref: | |
1505 | drm_gem_object_unreference(&obj->base); | |
1506 | return ret; | |
1507 | } | |
1508 | ||
1509 | ring->status_page.obj = obj; | |
1510 | } | |
62fdfeaf | 1511 | |
f343c5f6 | 1512 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
9da3da66 | 1513 | ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); |
8187a2b7 | 1514 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
62fdfeaf | 1515 | |
8187a2b7 ZN |
1516 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
1517 | ring->name, ring->status_page.gfx_addr); | |
62fdfeaf EA |
1518 | |
1519 | return 0; | |
62fdfeaf EA |
1520 | } |
1521 | ||
a4872ba6 | 1522 | static int init_phys_status_page(struct intel_engine_cs *ring) |
6b8294a4 CW |
1523 | { |
1524 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
6b8294a4 CW |
1525 | |
1526 | if (!dev_priv->status_page_dmah) { | |
1527 | dev_priv->status_page_dmah = | |
1528 | drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE); | |
1529 | if (!dev_priv->status_page_dmah) | |
1530 | return -ENOMEM; | |
1531 | } | |
1532 | ||
6b8294a4 CW |
1533 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1534 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
1535 | ||
1536 | return 0; | |
1537 | } | |
1538 | ||
84c2377f | 1539 | void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
2919d291 OM |
1540 | { |
1541 | if (!ringbuf->obj) | |
1542 | return; | |
1543 | ||
1544 | iounmap(ringbuf->virtual_start); | |
1545 | i915_gem_object_ggtt_unpin(ringbuf->obj); | |
1546 | drm_gem_object_unreference(&ringbuf->obj->base); | |
1547 | ringbuf->obj = NULL; | |
1548 | } | |
1549 | ||
84c2377f OM |
1550 | int intel_alloc_ringbuffer_obj(struct drm_device *dev, |
1551 | struct intel_ringbuffer *ringbuf) | |
62fdfeaf | 1552 | { |
e3efda49 | 1553 | struct drm_i915_private *dev_priv = to_i915(dev); |
05394f39 | 1554 | struct drm_i915_gem_object *obj; |
dd785e35 CW |
1555 | int ret; |
1556 | ||
2919d291 | 1557 | if (ringbuf->obj) |
e3efda49 | 1558 | return 0; |
62fdfeaf | 1559 | |
ebc052e0 CW |
1560 | obj = NULL; |
1561 | if (!HAS_LLC(dev)) | |
93b0a4e0 | 1562 | obj = i915_gem_object_create_stolen(dev, ringbuf->size); |
ebc052e0 | 1563 | if (obj == NULL) |
93b0a4e0 | 1564 | obj = i915_gem_alloc_object(dev, ringbuf->size); |
e3efda49 CW |
1565 | if (obj == NULL) |
1566 | return -ENOMEM; | |
8187a2b7 | 1567 | |
24f3a8cf AG |
1568 | /* mark ring buffers as read-only from GPU side by default */ |
1569 | obj->gt_ro = 1; | |
1570 | ||
1ec9e26d | 1571 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE); |
dd785e35 CW |
1572 | if (ret) |
1573 | goto err_unref; | |
62fdfeaf | 1574 | |
3eef8918 CW |
1575 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
1576 | if (ret) | |
1577 | goto err_unpin; | |
1578 | ||
93b0a4e0 | 1579 | ringbuf->virtual_start = |
f343c5f6 | 1580 | ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj), |
93b0a4e0 OM |
1581 | ringbuf->size); |
1582 | if (ringbuf->virtual_start == NULL) { | |
8187a2b7 | 1583 | ret = -EINVAL; |
dd785e35 | 1584 | goto err_unpin; |
62fdfeaf EA |
1585 | } |
1586 | ||
93b0a4e0 | 1587 | ringbuf->obj = obj; |
e3efda49 CW |
1588 | return 0; |
1589 | ||
1590 | err_unpin: | |
1591 | i915_gem_object_ggtt_unpin(obj); | |
1592 | err_unref: | |
1593 | drm_gem_object_unreference(&obj->base); | |
1594 | return ret; | |
1595 | } | |
1596 | ||
1597 | static int intel_init_ring_buffer(struct drm_device *dev, | |
a4872ba6 | 1598 | struct intel_engine_cs *ring) |
e3efda49 | 1599 | { |
8ee14975 | 1600 | struct intel_ringbuffer *ringbuf = ring->buffer; |
e3efda49 CW |
1601 | int ret; |
1602 | ||
8ee14975 OM |
1603 | if (ringbuf == NULL) { |
1604 | ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); | |
1605 | if (!ringbuf) | |
1606 | return -ENOMEM; | |
1607 | ring->buffer = ringbuf; | |
1608 | } | |
1609 | ||
e3efda49 CW |
1610 | ring->dev = dev; |
1611 | INIT_LIST_HEAD(&ring->active_list); | |
1612 | INIT_LIST_HEAD(&ring->request_list); | |
93b0a4e0 | 1613 | ringbuf->size = 32 * PAGE_SIZE; |
0c7dd53b | 1614 | ringbuf->ring = ring; |
ebc348b2 | 1615 | memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno)); |
e3efda49 CW |
1616 | |
1617 | init_waitqueue_head(&ring->irq_queue); | |
1618 | ||
1619 | if (I915_NEED_GFX_HWS(dev)) { | |
1620 | ret = init_status_page(ring); | |
1621 | if (ret) | |
8ee14975 | 1622 | goto error; |
e3efda49 CW |
1623 | } else { |
1624 | BUG_ON(ring->id != RCS); | |
1625 | ret = init_phys_status_page(ring); | |
1626 | if (ret) | |
8ee14975 | 1627 | goto error; |
e3efda49 CW |
1628 | } |
1629 | ||
2919d291 | 1630 | ret = intel_alloc_ringbuffer_obj(dev, ringbuf); |
e3efda49 CW |
1631 | if (ret) { |
1632 | DRM_ERROR("Failed to allocate ringbuffer %s: %d\n", ring->name, ret); | |
8ee14975 | 1633 | goto error; |
e3efda49 | 1634 | } |
62fdfeaf | 1635 | |
55249baa CW |
1636 | /* Workaround an erratum on the i830 which causes a hang if |
1637 | * the TAIL pointer points to within the last 2 cachelines | |
1638 | * of the buffer. | |
1639 | */ | |
93b0a4e0 | 1640 | ringbuf->effective_size = ringbuf->size; |
e3efda49 | 1641 | if (IS_I830(dev) || IS_845G(dev)) |
93b0a4e0 | 1642 | ringbuf->effective_size -= 2 * CACHELINE_BYTES; |
55249baa | 1643 | |
44e895a8 BV |
1644 | ret = i915_cmd_parser_init_ring(ring); |
1645 | if (ret) | |
8ee14975 OM |
1646 | goto error; |
1647 | ||
1648 | ret = ring->init(ring); | |
1649 | if (ret) | |
1650 | goto error; | |
1651 | ||
1652 | return 0; | |
351e3db2 | 1653 | |
8ee14975 OM |
1654 | error: |
1655 | kfree(ringbuf); | |
1656 | ring->buffer = NULL; | |
1657 | return ret; | |
62fdfeaf EA |
1658 | } |
1659 | ||
a4872ba6 | 1660 | void intel_cleanup_ring_buffer(struct intel_engine_cs *ring) |
62fdfeaf | 1661 | { |
e3efda49 | 1662 | struct drm_i915_private *dev_priv = to_i915(ring->dev); |
93b0a4e0 | 1663 | struct intel_ringbuffer *ringbuf = ring->buffer; |
33626e6a | 1664 | |
93b0a4e0 | 1665 | if (!intel_ring_initialized(ring)) |
62fdfeaf EA |
1666 | return; |
1667 | ||
e3efda49 | 1668 | intel_stop_ring_buffer(ring); |
de8f0a50 | 1669 | WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0); |
33626e6a | 1670 | |
2919d291 | 1671 | intel_destroy_ringbuffer_obj(ringbuf); |
3d57e5bd BW |
1672 | ring->preallocated_lazy_request = NULL; |
1673 | ring->outstanding_lazy_seqno = 0; | |
78501eac | 1674 | |
8d19215b ZN |
1675 | if (ring->cleanup) |
1676 | ring->cleanup(ring); | |
1677 | ||
78501eac | 1678 | cleanup_status_page(ring); |
44e895a8 BV |
1679 | |
1680 | i915_cmd_parser_fini_ring(ring); | |
8ee14975 | 1681 | |
93b0a4e0 | 1682 | kfree(ringbuf); |
8ee14975 | 1683 | ring->buffer = NULL; |
62fdfeaf EA |
1684 | } |
1685 | ||
a4872ba6 | 1686 | static int intel_ring_wait_request(struct intel_engine_cs *ring, int n) |
a71d8d94 | 1687 | { |
93b0a4e0 | 1688 | struct intel_ringbuffer *ringbuf = ring->buffer; |
a71d8d94 | 1689 | struct drm_i915_gem_request *request; |
1cf0ba14 | 1690 | u32 seqno = 0; |
a71d8d94 CW |
1691 | int ret; |
1692 | ||
93b0a4e0 OM |
1693 | if (ringbuf->last_retired_head != -1) { |
1694 | ringbuf->head = ringbuf->last_retired_head; | |
1695 | ringbuf->last_retired_head = -1; | |
1f70999f | 1696 | |
64c58f2c | 1697 | ringbuf->space = ring_space(ringbuf); |
93b0a4e0 | 1698 | if (ringbuf->space >= n) |
a71d8d94 CW |
1699 | return 0; |
1700 | } | |
1701 | ||
1702 | list_for_each_entry(request, &ring->request_list, list) { | |
93b0a4e0 | 1703 | if (__ring_space(request->tail, ringbuf->tail, ringbuf->size) >= n) { |
a71d8d94 CW |
1704 | seqno = request->seqno; |
1705 | break; | |
1706 | } | |
a71d8d94 CW |
1707 | } |
1708 | ||
1709 | if (seqno == 0) | |
1710 | return -ENOSPC; | |
1711 | ||
1f70999f | 1712 | ret = i915_wait_seqno(ring, seqno); |
a71d8d94 CW |
1713 | if (ret) |
1714 | return ret; | |
1715 | ||
1cf0ba14 | 1716 | i915_gem_retire_requests_ring(ring); |
93b0a4e0 OM |
1717 | ringbuf->head = ringbuf->last_retired_head; |
1718 | ringbuf->last_retired_head = -1; | |
a71d8d94 | 1719 | |
64c58f2c | 1720 | ringbuf->space = ring_space(ringbuf); |
a71d8d94 CW |
1721 | return 0; |
1722 | } | |
1723 | ||
a4872ba6 | 1724 | static int ring_wait_for_space(struct intel_engine_cs *ring, int n) |
62fdfeaf | 1725 | { |
78501eac | 1726 | struct drm_device *dev = ring->dev; |
cae5852d | 1727 | struct drm_i915_private *dev_priv = dev->dev_private; |
93b0a4e0 | 1728 | struct intel_ringbuffer *ringbuf = ring->buffer; |
78501eac | 1729 | unsigned long end; |
a71d8d94 | 1730 | int ret; |
c7dca47b | 1731 | |
a71d8d94 CW |
1732 | ret = intel_ring_wait_request(ring, n); |
1733 | if (ret != -ENOSPC) | |
1734 | return ret; | |
1735 | ||
09246732 CW |
1736 | /* force the tail write in case we have been skipping them */ |
1737 | __intel_ring_advance(ring); | |
1738 | ||
63ed2cb2 DV |
1739 | /* With GEM the hangcheck timer should kick us out of the loop, |
1740 | * leaving it early runs the risk of corrupting GEM state (due | |
1741 | * to running on almost untested codepaths). But on resume | |
1742 | * timers don't work yet, so prevent a complete hang in that | |
1743 | * case by choosing an insanely large timeout. */ | |
1744 | end = jiffies + 60 * HZ; | |
e6bfaf85 | 1745 | |
dcfe0506 | 1746 | trace_i915_ring_wait_begin(ring); |
8187a2b7 | 1747 | do { |
93b0a4e0 | 1748 | ringbuf->head = I915_READ_HEAD(ring); |
64c58f2c | 1749 | ringbuf->space = ring_space(ringbuf); |
93b0a4e0 | 1750 | if (ringbuf->space >= n) { |
dcfe0506 CW |
1751 | ret = 0; |
1752 | break; | |
62fdfeaf EA |
1753 | } |
1754 | ||
fb19e2ac DV |
1755 | if (!drm_core_check_feature(dev, DRIVER_MODESET) && |
1756 | dev->primary->master) { | |
62fdfeaf EA |
1757 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1758 | if (master_priv->sarea_priv) | |
1759 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1760 | } | |
d1b851fc | 1761 | |
e60a0b10 | 1762 | msleep(1); |
d6b2c790 | 1763 | |
dcfe0506 CW |
1764 | if (dev_priv->mm.interruptible && signal_pending(current)) { |
1765 | ret = -ERESTARTSYS; | |
1766 | break; | |
1767 | } | |
1768 | ||
33196ded DV |
1769 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
1770 | dev_priv->mm.interruptible); | |
d6b2c790 | 1771 | if (ret) |
dcfe0506 CW |
1772 | break; |
1773 | ||
1774 | if (time_after(jiffies, end)) { | |
1775 | ret = -EBUSY; | |
1776 | break; | |
1777 | } | |
1778 | } while (1); | |
db53a302 | 1779 | trace_i915_ring_wait_end(ring); |
dcfe0506 | 1780 | return ret; |
8187a2b7 | 1781 | } |
62fdfeaf | 1782 | |
a4872ba6 | 1783 | static int intel_wrap_ring_buffer(struct intel_engine_cs *ring) |
3e960501 CW |
1784 | { |
1785 | uint32_t __iomem *virt; | |
93b0a4e0 OM |
1786 | struct intel_ringbuffer *ringbuf = ring->buffer; |
1787 | int rem = ringbuf->size - ringbuf->tail; | |
3e960501 | 1788 | |
93b0a4e0 | 1789 | if (ringbuf->space < rem) { |
3e960501 CW |
1790 | int ret = ring_wait_for_space(ring, rem); |
1791 | if (ret) | |
1792 | return ret; | |
1793 | } | |
1794 | ||
93b0a4e0 | 1795 | virt = ringbuf->virtual_start + ringbuf->tail; |
3e960501 CW |
1796 | rem /= 4; |
1797 | while (rem--) | |
1798 | iowrite32(MI_NOOP, virt++); | |
1799 | ||
93b0a4e0 | 1800 | ringbuf->tail = 0; |
64c58f2c | 1801 | ringbuf->space = ring_space(ringbuf); |
3e960501 CW |
1802 | |
1803 | return 0; | |
1804 | } | |
1805 | ||
a4872ba6 | 1806 | int intel_ring_idle(struct intel_engine_cs *ring) |
3e960501 CW |
1807 | { |
1808 | u32 seqno; | |
1809 | int ret; | |
1810 | ||
1811 | /* We need to add any requests required to flush the objects and ring */ | |
1823521d | 1812 | if (ring->outstanding_lazy_seqno) { |
0025c077 | 1813 | ret = i915_add_request(ring, NULL); |
3e960501 CW |
1814 | if (ret) |
1815 | return ret; | |
1816 | } | |
1817 | ||
1818 | /* Wait upon the last request to be completed */ | |
1819 | if (list_empty(&ring->request_list)) | |
1820 | return 0; | |
1821 | ||
1822 | seqno = list_entry(ring->request_list.prev, | |
1823 | struct drm_i915_gem_request, | |
1824 | list)->seqno; | |
1825 | ||
1826 | return i915_wait_seqno(ring, seqno); | |
1827 | } | |
1828 | ||
9d773091 | 1829 | static int |
a4872ba6 | 1830 | intel_ring_alloc_seqno(struct intel_engine_cs *ring) |
9d773091 | 1831 | { |
1823521d | 1832 | if (ring->outstanding_lazy_seqno) |
9d773091 CW |
1833 | return 0; |
1834 | ||
3c0e234c CW |
1835 | if (ring->preallocated_lazy_request == NULL) { |
1836 | struct drm_i915_gem_request *request; | |
1837 | ||
1838 | request = kmalloc(sizeof(*request), GFP_KERNEL); | |
1839 | if (request == NULL) | |
1840 | return -ENOMEM; | |
1841 | ||
1842 | ring->preallocated_lazy_request = request; | |
1843 | } | |
1844 | ||
1823521d | 1845 | return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno); |
9d773091 CW |
1846 | } |
1847 | ||
a4872ba6 | 1848 | static int __intel_ring_prepare(struct intel_engine_cs *ring, |
304d695c | 1849 | int bytes) |
cbcc80df | 1850 | { |
93b0a4e0 | 1851 | struct intel_ringbuffer *ringbuf = ring->buffer; |
cbcc80df MK |
1852 | int ret; |
1853 | ||
93b0a4e0 | 1854 | if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) { |
cbcc80df MK |
1855 | ret = intel_wrap_ring_buffer(ring); |
1856 | if (unlikely(ret)) | |
1857 | return ret; | |
1858 | } | |
1859 | ||
93b0a4e0 | 1860 | if (unlikely(ringbuf->space < bytes)) { |
cbcc80df MK |
1861 | ret = ring_wait_for_space(ring, bytes); |
1862 | if (unlikely(ret)) | |
1863 | return ret; | |
1864 | } | |
1865 | ||
cbcc80df MK |
1866 | return 0; |
1867 | } | |
1868 | ||
a4872ba6 | 1869 | int intel_ring_begin(struct intel_engine_cs *ring, |
e1f99ce6 | 1870 | int num_dwords) |
8187a2b7 | 1871 | { |
4640c4ff | 1872 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
e1f99ce6 | 1873 | int ret; |
78501eac | 1874 | |
33196ded DV |
1875 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
1876 | dev_priv->mm.interruptible); | |
de2b9985 DV |
1877 | if (ret) |
1878 | return ret; | |
21dd3734 | 1879 | |
304d695c CW |
1880 | ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t)); |
1881 | if (ret) | |
1882 | return ret; | |
1883 | ||
9d773091 CW |
1884 | /* Preallocate the olr before touching the ring */ |
1885 | ret = intel_ring_alloc_seqno(ring); | |
1886 | if (ret) | |
1887 | return ret; | |
1888 | ||
ee1b1e5e | 1889 | ring->buffer->space -= num_dwords * sizeof(uint32_t); |
304d695c | 1890 | return 0; |
8187a2b7 | 1891 | } |
78501eac | 1892 | |
753b1ad4 | 1893 | /* Align the ring tail to a cacheline boundary */ |
a4872ba6 | 1894 | int intel_ring_cacheline_align(struct intel_engine_cs *ring) |
753b1ad4 | 1895 | { |
ee1b1e5e | 1896 | int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); |
753b1ad4 VS |
1897 | int ret; |
1898 | ||
1899 | if (num_dwords == 0) | |
1900 | return 0; | |
1901 | ||
18393f63 | 1902 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
753b1ad4 VS |
1903 | ret = intel_ring_begin(ring, num_dwords); |
1904 | if (ret) | |
1905 | return ret; | |
1906 | ||
1907 | while (num_dwords--) | |
1908 | intel_ring_emit(ring, MI_NOOP); | |
1909 | ||
1910 | intel_ring_advance(ring); | |
1911 | ||
1912 | return 0; | |
1913 | } | |
1914 | ||
a4872ba6 | 1915 | void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno) |
498d2ac1 | 1916 | { |
3b2cc8ab OM |
1917 | struct drm_device *dev = ring->dev; |
1918 | struct drm_i915_private *dev_priv = dev->dev_private; | |
498d2ac1 | 1919 | |
1823521d | 1920 | BUG_ON(ring->outstanding_lazy_seqno); |
498d2ac1 | 1921 | |
3b2cc8ab | 1922 | if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) { |
f7e98ad4 MK |
1923 | I915_WRITE(RING_SYNC_0(ring->mmio_base), 0); |
1924 | I915_WRITE(RING_SYNC_1(ring->mmio_base), 0); | |
3b2cc8ab | 1925 | if (HAS_VEBOX(dev)) |
5020150b | 1926 | I915_WRITE(RING_SYNC_2(ring->mmio_base), 0); |
e1f99ce6 | 1927 | } |
d97ed339 | 1928 | |
f7e98ad4 | 1929 | ring->set_seqno(ring, seqno); |
92cab734 | 1930 | ring->hangcheck.seqno = seqno; |
8187a2b7 | 1931 | } |
62fdfeaf | 1932 | |
a4872ba6 | 1933 | static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring, |
297b0c5b | 1934 | u32 value) |
881f47b6 | 1935 | { |
4640c4ff | 1936 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
881f47b6 XH |
1937 | |
1938 | /* Every tail move must follow the sequence below */ | |
12f55818 CW |
1939 | |
1940 | /* Disable notification that the ring is IDLE. The GT | |
1941 | * will then assume that it is busy and bring it out of rc6. | |
1942 | */ | |
0206e353 | 1943 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 CW |
1944 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
1945 | ||
1946 | /* Clear the context id. Here be magic! */ | |
1947 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); | |
0206e353 | 1948 | |
12f55818 | 1949 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
0206e353 | 1950 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
12f55818 CW |
1951 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
1952 | 50)) | |
1953 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); | |
0206e353 | 1954 | |
12f55818 | 1955 | /* Now that the ring is fully powered up, update the tail */ |
0206e353 | 1956 | I915_WRITE_TAIL(ring, value); |
12f55818 CW |
1957 | POSTING_READ(RING_TAIL(ring->mmio_base)); |
1958 | ||
1959 | /* Let the ring send IDLE messages to the GT again, | |
1960 | * and so let it sleep to conserve power when idle. | |
1961 | */ | |
0206e353 | 1962 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 | 1963 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
881f47b6 XH |
1964 | } |
1965 | ||
a4872ba6 | 1966 | static int gen6_bsd_ring_flush(struct intel_engine_cs *ring, |
ea251324 | 1967 | u32 invalidate, u32 flush) |
881f47b6 | 1968 | { |
71a77e07 | 1969 | uint32_t cmd; |
b72f3acb CW |
1970 | int ret; |
1971 | ||
b72f3acb CW |
1972 | ret = intel_ring_begin(ring, 4); |
1973 | if (ret) | |
1974 | return ret; | |
1975 | ||
71a77e07 | 1976 | cmd = MI_FLUSH_DW; |
075b3bba BW |
1977 | if (INTEL_INFO(ring->dev)->gen >= 8) |
1978 | cmd += 1; | |
9a289771 JB |
1979 | /* |
1980 | * Bspec vol 1c.5 - video engine command streamer: | |
1981 | * "If ENABLED, all TLBs will be invalidated once the flush | |
1982 | * operation is complete. This bit is only valid when the | |
1983 | * Post-Sync Operation field is a value of 1h or 3h." | |
1984 | */ | |
71a77e07 | 1985 | if (invalidate & I915_GEM_GPU_DOMAINS) |
9a289771 JB |
1986 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | |
1987 | MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
71a77e07 | 1988 | intel_ring_emit(ring, cmd); |
9a289771 | 1989 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
075b3bba BW |
1990 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
1991 | intel_ring_emit(ring, 0); /* upper addr */ | |
1992 | intel_ring_emit(ring, 0); /* value */ | |
1993 | } else { | |
1994 | intel_ring_emit(ring, 0); | |
1995 | intel_ring_emit(ring, MI_NOOP); | |
1996 | } | |
b72f3acb CW |
1997 | intel_ring_advance(ring); |
1998 | return 0; | |
881f47b6 XH |
1999 | } |
2000 | ||
1c7a0623 | 2001 | static int |
a4872ba6 | 2002 | gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 2003 | u64 offset, u32 len, |
1c7a0623 BW |
2004 | unsigned flags) |
2005 | { | |
28cf5415 BW |
2006 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
2007 | bool ppgtt = dev_priv->mm.aliasing_ppgtt != NULL && | |
2008 | !(flags & I915_DISPATCH_SECURE); | |
1c7a0623 BW |
2009 | int ret; |
2010 | ||
2011 | ret = intel_ring_begin(ring, 4); | |
2012 | if (ret) | |
2013 | return ret; | |
2014 | ||
2015 | /* FIXME(BDW): Address space and security selectors. */ | |
28cf5415 | 2016 | intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); |
9bcb144c BW |
2017 | intel_ring_emit(ring, lower_32_bits(offset)); |
2018 | intel_ring_emit(ring, upper_32_bits(offset)); | |
1c7a0623 BW |
2019 | intel_ring_emit(ring, MI_NOOP); |
2020 | intel_ring_advance(ring); | |
2021 | ||
2022 | return 0; | |
2023 | } | |
2024 | ||
d7d4eedd | 2025 | static int |
a4872ba6 | 2026 | hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 2027 | u64 offset, u32 len, |
d7d4eedd CW |
2028 | unsigned flags) |
2029 | { | |
2030 | int ret; | |
2031 | ||
2032 | ret = intel_ring_begin(ring, 2); | |
2033 | if (ret) | |
2034 | return ret; | |
2035 | ||
2036 | intel_ring_emit(ring, | |
2037 | MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW | | |
2038 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW)); | |
2039 | /* bit0-7 is the length on GEN6+ */ | |
2040 | intel_ring_emit(ring, offset); | |
2041 | intel_ring_advance(ring); | |
2042 | ||
2043 | return 0; | |
2044 | } | |
2045 | ||
881f47b6 | 2046 | static int |
a4872ba6 | 2047 | gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 2048 | u64 offset, u32 len, |
d7d4eedd | 2049 | unsigned flags) |
881f47b6 | 2050 | { |
0206e353 | 2051 | int ret; |
ab6f8e32 | 2052 | |
0206e353 AJ |
2053 | ret = intel_ring_begin(ring, 2); |
2054 | if (ret) | |
2055 | return ret; | |
e1f99ce6 | 2056 | |
d7d4eedd CW |
2057 | intel_ring_emit(ring, |
2058 | MI_BATCH_BUFFER_START | | |
2059 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); | |
0206e353 AJ |
2060 | /* bit0-7 is the length on GEN6+ */ |
2061 | intel_ring_emit(ring, offset); | |
2062 | intel_ring_advance(ring); | |
ab6f8e32 | 2063 | |
0206e353 | 2064 | return 0; |
881f47b6 XH |
2065 | } |
2066 | ||
549f7365 CW |
2067 | /* Blitter support (SandyBridge+) */ |
2068 | ||
a4872ba6 | 2069 | static int gen6_ring_flush(struct intel_engine_cs *ring, |
ea251324 | 2070 | u32 invalidate, u32 flush) |
8d19215b | 2071 | { |
fd3da6c9 | 2072 | struct drm_device *dev = ring->dev; |
71a77e07 | 2073 | uint32_t cmd; |
b72f3acb CW |
2074 | int ret; |
2075 | ||
6a233c78 | 2076 | ret = intel_ring_begin(ring, 4); |
b72f3acb CW |
2077 | if (ret) |
2078 | return ret; | |
2079 | ||
71a77e07 | 2080 | cmd = MI_FLUSH_DW; |
075b3bba BW |
2081 | if (INTEL_INFO(ring->dev)->gen >= 8) |
2082 | cmd += 1; | |
9a289771 JB |
2083 | /* |
2084 | * Bspec vol 1c.3 - blitter engine command streamer: | |
2085 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2086 | * operation is complete. This bit is only valid when the | |
2087 | * Post-Sync Operation field is a value of 1h or 3h." | |
2088 | */ | |
71a77e07 | 2089 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
9a289771 | 2090 | cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | |
b3fcabb1 | 2091 | MI_FLUSH_DW_OP_STOREDW; |
71a77e07 | 2092 | intel_ring_emit(ring, cmd); |
9a289771 | 2093 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
075b3bba BW |
2094 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
2095 | intel_ring_emit(ring, 0); /* upper addr */ | |
2096 | intel_ring_emit(ring, 0); /* value */ | |
2097 | } else { | |
2098 | intel_ring_emit(ring, 0); | |
2099 | intel_ring_emit(ring, MI_NOOP); | |
2100 | } | |
b72f3acb | 2101 | intel_ring_advance(ring); |
fd3da6c9 | 2102 | |
9688ecad | 2103 | if (IS_GEN7(dev) && !invalidate && flush) |
fd3da6c9 RV |
2104 | return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN); |
2105 | ||
b72f3acb | 2106 | return 0; |
8d19215b ZN |
2107 | } |
2108 | ||
5c1143bb XH |
2109 | int intel_init_render_ring_buffer(struct drm_device *dev) |
2110 | { | |
4640c4ff | 2111 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2112 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
3e78998a BW |
2113 | struct drm_i915_gem_object *obj; |
2114 | int ret; | |
5c1143bb | 2115 | |
59465b5f DV |
2116 | ring->name = "render ring"; |
2117 | ring->id = RCS; | |
2118 | ring->mmio_base = RENDER_RING_BASE; | |
2119 | ||
707d9cf9 | 2120 | if (INTEL_INFO(dev)->gen >= 8) { |
3e78998a BW |
2121 | if (i915_semaphore_is_enabled(dev)) { |
2122 | obj = i915_gem_alloc_object(dev, 4096); | |
2123 | if (obj == NULL) { | |
2124 | DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n"); | |
2125 | i915.semaphores = 0; | |
2126 | } else { | |
2127 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
2128 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK); | |
2129 | if (ret != 0) { | |
2130 | drm_gem_object_unreference(&obj->base); | |
2131 | DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n"); | |
2132 | i915.semaphores = 0; | |
2133 | } else | |
2134 | dev_priv->semaphore_obj = obj; | |
2135 | } | |
2136 | } | |
707d9cf9 BW |
2137 | ring->add_request = gen6_add_request; |
2138 | ring->flush = gen8_render_ring_flush; | |
2139 | ring->irq_get = gen8_ring_get_irq; | |
2140 | ring->irq_put = gen8_ring_put_irq; | |
2141 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; | |
2142 | ring->get_seqno = gen6_ring_get_seqno; | |
2143 | ring->set_seqno = ring_set_seqno; | |
2144 | if (i915_semaphore_is_enabled(dev)) { | |
3e78998a | 2145 | WARN_ON(!dev_priv->semaphore_obj); |
5ee426ca | 2146 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2147 | ring->semaphore.signal = gen8_rcs_signal; |
2148 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 BW |
2149 | } |
2150 | } else if (INTEL_INFO(dev)->gen >= 6) { | |
1ec14ad3 | 2151 | ring->add_request = gen6_add_request; |
4772eaeb | 2152 | ring->flush = gen7_render_ring_flush; |
6c6cf5aa | 2153 | if (INTEL_INFO(dev)->gen == 6) |
b3111509 | 2154 | ring->flush = gen6_render_ring_flush; |
707d9cf9 BW |
2155 | ring->irq_get = gen6_ring_get_irq; |
2156 | ring->irq_put = gen6_ring_put_irq; | |
cc609d5d | 2157 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
4cd53c0c | 2158 | ring->get_seqno = gen6_ring_get_seqno; |
b70ec5bf | 2159 | ring->set_seqno = ring_set_seqno; |
707d9cf9 BW |
2160 | if (i915_semaphore_is_enabled(dev)) { |
2161 | ring->semaphore.sync_to = gen6_ring_sync; | |
2162 | ring->semaphore.signal = gen6_signal; | |
2163 | /* | |
2164 | * The current semaphore is only applied on pre-gen8 | |
2165 | * platform. And there is no VCS2 ring on the pre-gen8 | |
2166 | * platform. So the semaphore between RCS and VCS2 is | |
2167 | * initialized as INVALID. Gen8 will initialize the | |
2168 | * sema between VCS2 and RCS later. | |
2169 | */ | |
2170 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2171 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV; | |
2172 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB; | |
2173 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE; | |
2174 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2175 | ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC; | |
2176 | ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC; | |
2177 | ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC; | |
2178 | ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC; | |
2179 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2180 | } | |
c6df541c CW |
2181 | } else if (IS_GEN5(dev)) { |
2182 | ring->add_request = pc_render_add_request; | |
46f0f8d1 | 2183 | ring->flush = gen4_render_ring_flush; |
c6df541c | 2184 | ring->get_seqno = pc_render_get_seqno; |
b70ec5bf | 2185 | ring->set_seqno = pc_render_set_seqno; |
e48d8634 DV |
2186 | ring->irq_get = gen5_ring_get_irq; |
2187 | ring->irq_put = gen5_ring_put_irq; | |
cc609d5d BW |
2188 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT | |
2189 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; | |
59465b5f | 2190 | } else { |
8620a3a9 | 2191 | ring->add_request = i9xx_add_request; |
46f0f8d1 CW |
2192 | if (INTEL_INFO(dev)->gen < 4) |
2193 | ring->flush = gen2_render_ring_flush; | |
2194 | else | |
2195 | ring->flush = gen4_render_ring_flush; | |
59465b5f | 2196 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 2197 | ring->set_seqno = ring_set_seqno; |
c2798b19 CW |
2198 | if (IS_GEN2(dev)) { |
2199 | ring->irq_get = i8xx_ring_get_irq; | |
2200 | ring->irq_put = i8xx_ring_put_irq; | |
2201 | } else { | |
2202 | ring->irq_get = i9xx_ring_get_irq; | |
2203 | ring->irq_put = i9xx_ring_put_irq; | |
2204 | } | |
e3670319 | 2205 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2206 | } |
59465b5f | 2207 | ring->write_tail = ring_write_tail; |
707d9cf9 | 2208 | |
d7d4eedd CW |
2209 | if (IS_HASWELL(dev)) |
2210 | ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; | |
1c7a0623 BW |
2211 | else if (IS_GEN8(dev)) |
2212 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; | |
d7d4eedd | 2213 | else if (INTEL_INFO(dev)->gen >= 6) |
fb3256da DV |
2214 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
2215 | else if (INTEL_INFO(dev)->gen >= 4) | |
2216 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
2217 | else if (IS_I830(dev) || IS_845G(dev)) | |
2218 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
2219 | else | |
2220 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
2221 | ring->init = init_render_ring; |
2222 | ring->cleanup = render_ring_cleanup; | |
2223 | ||
b45305fc DV |
2224 | /* Workaround batchbuffer to combat CS tlb bug. */ |
2225 | if (HAS_BROKEN_CS_TLB(dev)) { | |
b45305fc DV |
2226 | obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT); |
2227 | if (obj == NULL) { | |
2228 | DRM_ERROR("Failed to allocate batch bo\n"); | |
2229 | return -ENOMEM; | |
2230 | } | |
2231 | ||
be1fa129 | 2232 | ret = i915_gem_obj_ggtt_pin(obj, 0, 0); |
b45305fc DV |
2233 | if (ret != 0) { |
2234 | drm_gem_object_unreference(&obj->base); | |
2235 | DRM_ERROR("Failed to ping batch bo\n"); | |
2236 | return ret; | |
2237 | } | |
2238 | ||
0d1aacac CW |
2239 | ring->scratch.obj = obj; |
2240 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); | |
b45305fc DV |
2241 | } |
2242 | ||
1ec14ad3 | 2243 | return intel_init_ring_buffer(dev, ring); |
5c1143bb XH |
2244 | } |
2245 | ||
e8616b6c CW |
2246 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size) |
2247 | { | |
4640c4ff | 2248 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2249 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
8ee14975 | 2250 | struct intel_ringbuffer *ringbuf = ring->buffer; |
6b8294a4 | 2251 | int ret; |
e8616b6c | 2252 | |
8ee14975 OM |
2253 | if (ringbuf == NULL) { |
2254 | ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); | |
2255 | if (!ringbuf) | |
2256 | return -ENOMEM; | |
2257 | ring->buffer = ringbuf; | |
2258 | } | |
2259 | ||
59465b5f DV |
2260 | ring->name = "render ring"; |
2261 | ring->id = RCS; | |
2262 | ring->mmio_base = RENDER_RING_BASE; | |
2263 | ||
e8616b6c | 2264 | if (INTEL_INFO(dev)->gen >= 6) { |
b4178f8a | 2265 | /* non-kms not supported on gen6+ */ |
8ee14975 OM |
2266 | ret = -ENODEV; |
2267 | goto err_ringbuf; | |
e8616b6c | 2268 | } |
28f0cbf7 DV |
2269 | |
2270 | /* Note: gem is not supported on gen5/ilk without kms (the corresponding | |
2271 | * gem_init ioctl returns with -ENODEV). Hence we do not need to set up | |
2272 | * the special gen5 functions. */ | |
2273 | ring->add_request = i9xx_add_request; | |
46f0f8d1 CW |
2274 | if (INTEL_INFO(dev)->gen < 4) |
2275 | ring->flush = gen2_render_ring_flush; | |
2276 | else | |
2277 | ring->flush = gen4_render_ring_flush; | |
28f0cbf7 | 2278 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 2279 | ring->set_seqno = ring_set_seqno; |
c2798b19 CW |
2280 | if (IS_GEN2(dev)) { |
2281 | ring->irq_get = i8xx_ring_get_irq; | |
2282 | ring->irq_put = i8xx_ring_put_irq; | |
2283 | } else { | |
2284 | ring->irq_get = i9xx_ring_get_irq; | |
2285 | ring->irq_put = i9xx_ring_put_irq; | |
2286 | } | |
28f0cbf7 | 2287 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
59465b5f | 2288 | ring->write_tail = ring_write_tail; |
fb3256da DV |
2289 | if (INTEL_INFO(dev)->gen >= 4) |
2290 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
2291 | else if (IS_I830(dev) || IS_845G(dev)) | |
2292 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
2293 | else | |
2294 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
2295 | ring->init = init_render_ring; |
2296 | ring->cleanup = render_ring_cleanup; | |
e8616b6c CW |
2297 | |
2298 | ring->dev = dev; | |
2299 | INIT_LIST_HEAD(&ring->active_list); | |
2300 | INIT_LIST_HEAD(&ring->request_list); | |
e8616b6c | 2301 | |
93b0a4e0 OM |
2302 | ringbuf->size = size; |
2303 | ringbuf->effective_size = ringbuf->size; | |
17f10fdc | 2304 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
93b0a4e0 | 2305 | ringbuf->effective_size -= 2 * CACHELINE_BYTES; |
e8616b6c | 2306 | |
93b0a4e0 OM |
2307 | ringbuf->virtual_start = ioremap_wc(start, size); |
2308 | if (ringbuf->virtual_start == NULL) { | |
e8616b6c CW |
2309 | DRM_ERROR("can not ioremap virtual address for" |
2310 | " ring buffer\n"); | |
8ee14975 OM |
2311 | ret = -ENOMEM; |
2312 | goto err_ringbuf; | |
e8616b6c CW |
2313 | } |
2314 | ||
6b8294a4 | 2315 | if (!I915_NEED_GFX_HWS(dev)) { |
035dc1e0 | 2316 | ret = init_phys_status_page(ring); |
6b8294a4 | 2317 | if (ret) |
8ee14975 | 2318 | goto err_vstart; |
6b8294a4 CW |
2319 | } |
2320 | ||
e8616b6c | 2321 | return 0; |
8ee14975 OM |
2322 | |
2323 | err_vstart: | |
93b0a4e0 | 2324 | iounmap(ringbuf->virtual_start); |
8ee14975 OM |
2325 | err_ringbuf: |
2326 | kfree(ringbuf); | |
2327 | ring->buffer = NULL; | |
2328 | return ret; | |
e8616b6c CW |
2329 | } |
2330 | ||
5c1143bb XH |
2331 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
2332 | { | |
4640c4ff | 2333 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2334 | struct intel_engine_cs *ring = &dev_priv->ring[VCS]; |
5c1143bb | 2335 | |
58fa3835 DV |
2336 | ring->name = "bsd ring"; |
2337 | ring->id = VCS; | |
2338 | ||
0fd2c201 | 2339 | ring->write_tail = ring_write_tail; |
780f18c8 | 2340 | if (INTEL_INFO(dev)->gen >= 6) { |
58fa3835 | 2341 | ring->mmio_base = GEN6_BSD_RING_BASE; |
0fd2c201 DV |
2342 | /* gen6 bsd needs a special wa for tail updates */ |
2343 | if (IS_GEN6(dev)) | |
2344 | ring->write_tail = gen6_bsd_ring_write_tail; | |
ea251324 | 2345 | ring->flush = gen6_bsd_ring_flush; |
58fa3835 DV |
2346 | ring->add_request = gen6_add_request; |
2347 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 2348 | ring->set_seqno = ring_set_seqno; |
abd58f01 BW |
2349 | if (INTEL_INFO(dev)->gen >= 8) { |
2350 | ring->irq_enable_mask = | |
2351 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
2352 | ring->irq_get = gen8_ring_get_irq; | |
2353 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 BW |
2354 | ring->dispatch_execbuffer = |
2355 | gen8_ring_dispatch_execbuffer; | |
707d9cf9 | 2356 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2357 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2358 | ring->semaphore.signal = gen8_xcs_signal; |
2359 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 | 2360 | } |
abd58f01 BW |
2361 | } else { |
2362 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; | |
2363 | ring->irq_get = gen6_ring_get_irq; | |
2364 | ring->irq_put = gen6_ring_put_irq; | |
1c7a0623 BW |
2365 | ring->dispatch_execbuffer = |
2366 | gen6_ring_dispatch_execbuffer; | |
707d9cf9 BW |
2367 | if (i915_semaphore_is_enabled(dev)) { |
2368 | ring->semaphore.sync_to = gen6_ring_sync; | |
2369 | ring->semaphore.signal = gen6_signal; | |
2370 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR; | |
2371 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2372 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB; | |
2373 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE; | |
2374 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2375 | ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC; | |
2376 | ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC; | |
2377 | ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC; | |
2378 | ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC; | |
2379 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2380 | } | |
abd58f01 | 2381 | } |
58fa3835 DV |
2382 | } else { |
2383 | ring->mmio_base = BSD_RING_BASE; | |
58fa3835 | 2384 | ring->flush = bsd_ring_flush; |
8620a3a9 | 2385 | ring->add_request = i9xx_add_request; |
58fa3835 | 2386 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 2387 | ring->set_seqno = ring_set_seqno; |
e48d8634 | 2388 | if (IS_GEN5(dev)) { |
cc609d5d | 2389 | ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
e48d8634 DV |
2390 | ring->irq_get = gen5_ring_get_irq; |
2391 | ring->irq_put = gen5_ring_put_irq; | |
2392 | } else { | |
e3670319 | 2393 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
e48d8634 DV |
2394 | ring->irq_get = i9xx_ring_get_irq; |
2395 | ring->irq_put = i9xx_ring_put_irq; | |
2396 | } | |
fb3256da | 2397 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
58fa3835 DV |
2398 | } |
2399 | ring->init = init_ring_common; | |
2400 | ||
1ec14ad3 | 2401 | return intel_init_ring_buffer(dev, ring); |
5c1143bb | 2402 | } |
549f7365 | 2403 | |
845f74a7 ZY |
2404 | /** |
2405 | * Initialize the second BSD ring for Broadwell GT3. | |
2406 | * It is noted that this only exists on Broadwell GT3. | |
2407 | */ | |
2408 | int intel_init_bsd2_ring_buffer(struct drm_device *dev) | |
2409 | { | |
2410 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 2411 | struct intel_engine_cs *ring = &dev_priv->ring[VCS2]; |
845f74a7 ZY |
2412 | |
2413 | if ((INTEL_INFO(dev)->gen != 8)) { | |
2414 | DRM_ERROR("No dual-BSD ring on non-BDW machine\n"); | |
2415 | return -EINVAL; | |
2416 | } | |
2417 | ||
f7b64236 | 2418 | ring->name = "bsd2 ring"; |
845f74a7 ZY |
2419 | ring->id = VCS2; |
2420 | ||
2421 | ring->write_tail = ring_write_tail; | |
2422 | ring->mmio_base = GEN8_BSD2_RING_BASE; | |
2423 | ring->flush = gen6_bsd_ring_flush; | |
2424 | ring->add_request = gen6_add_request; | |
2425 | ring->get_seqno = gen6_ring_get_seqno; | |
2426 | ring->set_seqno = ring_set_seqno; | |
2427 | ring->irq_enable_mask = | |
2428 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; | |
2429 | ring->irq_get = gen8_ring_get_irq; | |
2430 | ring->irq_put = gen8_ring_put_irq; | |
2431 | ring->dispatch_execbuffer = | |
2432 | gen8_ring_dispatch_execbuffer; | |
3e78998a | 2433 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2434 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2435 | ring->semaphore.signal = gen8_xcs_signal; |
2436 | GEN8_RING_SEMAPHORE_INIT; | |
2437 | } | |
845f74a7 ZY |
2438 | ring->init = init_ring_common; |
2439 | ||
2440 | return intel_init_ring_buffer(dev, ring); | |
2441 | } | |
2442 | ||
549f7365 CW |
2443 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
2444 | { | |
4640c4ff | 2445 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2446 | struct intel_engine_cs *ring = &dev_priv->ring[BCS]; |
549f7365 | 2447 | |
3535d9dd DV |
2448 | ring->name = "blitter ring"; |
2449 | ring->id = BCS; | |
2450 | ||
2451 | ring->mmio_base = BLT_RING_BASE; | |
2452 | ring->write_tail = ring_write_tail; | |
ea251324 | 2453 | ring->flush = gen6_ring_flush; |
3535d9dd DV |
2454 | ring->add_request = gen6_add_request; |
2455 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 2456 | ring->set_seqno = ring_set_seqno; |
abd58f01 BW |
2457 | if (INTEL_INFO(dev)->gen >= 8) { |
2458 | ring->irq_enable_mask = | |
2459 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
2460 | ring->irq_get = gen8_ring_get_irq; | |
2461 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 | 2462 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
707d9cf9 | 2463 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2464 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2465 | ring->semaphore.signal = gen8_xcs_signal; |
2466 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 | 2467 | } |
abd58f01 BW |
2468 | } else { |
2469 | ring->irq_enable_mask = GT_BLT_USER_INTERRUPT; | |
2470 | ring->irq_get = gen6_ring_get_irq; | |
2471 | ring->irq_put = gen6_ring_put_irq; | |
1c7a0623 | 2472 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
707d9cf9 BW |
2473 | if (i915_semaphore_is_enabled(dev)) { |
2474 | ring->semaphore.signal = gen6_signal; | |
2475 | ring->semaphore.sync_to = gen6_ring_sync; | |
2476 | /* | |
2477 | * The current semaphore is only applied on pre-gen8 | |
2478 | * platform. And there is no VCS2 ring on the pre-gen8 | |
2479 | * platform. So the semaphore between BCS and VCS2 is | |
2480 | * initialized as INVALID. Gen8 will initialize the | |
2481 | * sema between BCS and VCS2 later. | |
2482 | */ | |
2483 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR; | |
2484 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV; | |
2485 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2486 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE; | |
2487 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2488 | ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC; | |
2489 | ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC; | |
2490 | ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC; | |
2491 | ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC; | |
2492 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2493 | } | |
abd58f01 | 2494 | } |
3535d9dd | 2495 | ring->init = init_ring_common; |
549f7365 | 2496 | |
1ec14ad3 | 2497 | return intel_init_ring_buffer(dev, ring); |
549f7365 | 2498 | } |
a7b9761d | 2499 | |
9a8a2213 BW |
2500 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
2501 | { | |
4640c4ff | 2502 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2503 | struct intel_engine_cs *ring = &dev_priv->ring[VECS]; |
9a8a2213 BW |
2504 | |
2505 | ring->name = "video enhancement ring"; | |
2506 | ring->id = VECS; | |
2507 | ||
2508 | ring->mmio_base = VEBOX_RING_BASE; | |
2509 | ring->write_tail = ring_write_tail; | |
2510 | ring->flush = gen6_ring_flush; | |
2511 | ring->add_request = gen6_add_request; | |
2512 | ring->get_seqno = gen6_ring_get_seqno; | |
2513 | ring->set_seqno = ring_set_seqno; | |
abd58f01 BW |
2514 | |
2515 | if (INTEL_INFO(dev)->gen >= 8) { | |
2516 | ring->irq_enable_mask = | |
40c499f9 | 2517 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
abd58f01 BW |
2518 | ring->irq_get = gen8_ring_get_irq; |
2519 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 | 2520 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
707d9cf9 | 2521 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2522 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2523 | ring->semaphore.signal = gen8_xcs_signal; |
2524 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 | 2525 | } |
abd58f01 BW |
2526 | } else { |
2527 | ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; | |
2528 | ring->irq_get = hsw_vebox_get_irq; | |
2529 | ring->irq_put = hsw_vebox_put_irq; | |
1c7a0623 | 2530 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
707d9cf9 BW |
2531 | if (i915_semaphore_is_enabled(dev)) { |
2532 | ring->semaphore.sync_to = gen6_ring_sync; | |
2533 | ring->semaphore.signal = gen6_signal; | |
2534 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER; | |
2535 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV; | |
2536 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB; | |
2537 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID; | |
2538 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2539 | ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC; | |
2540 | ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC; | |
2541 | ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC; | |
2542 | ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC; | |
2543 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2544 | } | |
abd58f01 | 2545 | } |
9a8a2213 BW |
2546 | ring->init = init_ring_common; |
2547 | ||
2548 | return intel_init_ring_buffer(dev, ring); | |
2549 | } | |
2550 | ||
a7b9761d | 2551 | int |
a4872ba6 | 2552 | intel_ring_flush_all_caches(struct intel_engine_cs *ring) |
a7b9761d CW |
2553 | { |
2554 | int ret; | |
2555 | ||
2556 | if (!ring->gpu_caches_dirty) | |
2557 | return 0; | |
2558 | ||
2559 | ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
2560 | if (ret) | |
2561 | return ret; | |
2562 | ||
2563 | trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
2564 | ||
2565 | ring->gpu_caches_dirty = false; | |
2566 | return 0; | |
2567 | } | |
2568 | ||
2569 | int | |
a4872ba6 | 2570 | intel_ring_invalidate_all_caches(struct intel_engine_cs *ring) |
a7b9761d CW |
2571 | { |
2572 | uint32_t flush_domains; | |
2573 | int ret; | |
2574 | ||
2575 | flush_domains = 0; | |
2576 | if (ring->gpu_caches_dirty) | |
2577 | flush_domains = I915_GEM_GPU_DOMAINS; | |
2578 | ||
2579 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
2580 | if (ret) | |
2581 | return ret; | |
2582 | ||
2583 | trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
2584 | ||
2585 | ring->gpu_caches_dirty = false; | |
2586 | return 0; | |
2587 | } | |
e3efda49 CW |
2588 | |
2589 | void | |
a4872ba6 | 2590 | intel_stop_ring_buffer(struct intel_engine_cs *ring) |
e3efda49 CW |
2591 | { |
2592 | int ret; | |
2593 | ||
2594 | if (!intel_ring_initialized(ring)) | |
2595 | return; | |
2596 | ||
2597 | ret = intel_ring_idle(ring); | |
2598 | if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error)) | |
2599 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", | |
2600 | ring->name, ret); | |
2601 | ||
2602 | stop_ring(ring); | |
2603 | } |