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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
760285e7 | 30 | #include <drm/drmP.h> |
62fdfeaf | 31 | #include "i915_drv.h" |
760285e7 | 32 | #include <drm/i915_drm.h> |
62fdfeaf | 33 | #include "i915_trace.h" |
881f47b6 | 34 | #include "intel_drv.h" |
62fdfeaf | 35 | |
48d82387 OM |
36 | bool |
37 | intel_ring_initialized(struct intel_engine_cs *ring) | |
38 | { | |
39 | struct drm_device *dev = ring->dev; | |
40 | ||
41 | if (!dev) | |
42 | return false; | |
43 | ||
44 | if (i915.enable_execlists) { | |
45 | struct intel_context *dctx = ring->default_context; | |
46 | struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf; | |
47 | ||
48 | return ringbuf->obj; | |
49 | } else | |
50 | return ring->buffer && ring->buffer->obj; | |
51 | } | |
18393f63 | 52 | |
82e104cc | 53 | int __intel_ring_space(int head, int tail, int size) |
c7dca47b | 54 | { |
4f54741e DG |
55 | int space = head - tail; |
56 | if (space <= 0) | |
1cf0ba14 | 57 | space += size; |
4f54741e | 58 | return space - I915_RING_FREE_SPACE; |
c7dca47b CW |
59 | } |
60 | ||
ebd0fd4b DG |
61 | void intel_ring_update_space(struct intel_ringbuffer *ringbuf) |
62 | { | |
63 | if (ringbuf->last_retired_head != -1) { | |
64 | ringbuf->head = ringbuf->last_retired_head; | |
65 | ringbuf->last_retired_head = -1; | |
66 | } | |
67 | ||
68 | ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR, | |
69 | ringbuf->tail, ringbuf->size); | |
70 | } | |
71 | ||
82e104cc | 72 | int intel_ring_space(struct intel_ringbuffer *ringbuf) |
1cf0ba14 | 73 | { |
ebd0fd4b DG |
74 | intel_ring_update_space(ringbuf); |
75 | return ringbuf->space; | |
1cf0ba14 CW |
76 | } |
77 | ||
82e104cc | 78 | bool intel_ring_stopped(struct intel_engine_cs *ring) |
09246732 CW |
79 | { |
80 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
88b4aa87 MK |
81 | return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring); |
82 | } | |
09246732 | 83 | |
a4872ba6 | 84 | void __intel_ring_advance(struct intel_engine_cs *ring) |
88b4aa87 | 85 | { |
93b0a4e0 OM |
86 | struct intel_ringbuffer *ringbuf = ring->buffer; |
87 | ringbuf->tail &= ringbuf->size - 1; | |
88b4aa87 | 88 | if (intel_ring_stopped(ring)) |
09246732 | 89 | return; |
93b0a4e0 | 90 | ring->write_tail(ring, ringbuf->tail); |
09246732 CW |
91 | } |
92 | ||
b72f3acb | 93 | static int |
a4872ba6 | 94 | gen2_render_ring_flush(struct intel_engine_cs *ring, |
46f0f8d1 CW |
95 | u32 invalidate_domains, |
96 | u32 flush_domains) | |
97 | { | |
98 | u32 cmd; | |
99 | int ret; | |
100 | ||
101 | cmd = MI_FLUSH; | |
31b14c9f | 102 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
46f0f8d1 CW |
103 | cmd |= MI_NO_WRITE_FLUSH; |
104 | ||
105 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
106 | cmd |= MI_READ_FLUSH; | |
107 | ||
108 | ret = intel_ring_begin(ring, 2); | |
109 | if (ret) | |
110 | return ret; | |
111 | ||
112 | intel_ring_emit(ring, cmd); | |
113 | intel_ring_emit(ring, MI_NOOP); | |
114 | intel_ring_advance(ring); | |
115 | ||
116 | return 0; | |
117 | } | |
118 | ||
119 | static int | |
a4872ba6 | 120 | gen4_render_ring_flush(struct intel_engine_cs *ring, |
46f0f8d1 CW |
121 | u32 invalidate_domains, |
122 | u32 flush_domains) | |
62fdfeaf | 123 | { |
78501eac | 124 | struct drm_device *dev = ring->dev; |
6f392d54 | 125 | u32 cmd; |
b72f3acb | 126 | int ret; |
6f392d54 | 127 | |
36d527de CW |
128 | /* |
129 | * read/write caches: | |
130 | * | |
131 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
132 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
133 | * also flushed at 2d versus 3d pipeline switches. | |
134 | * | |
135 | * read-only caches: | |
136 | * | |
137 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
138 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
139 | * | |
140 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
141 | * | |
142 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
143 | * invalidated when MI_EXE_FLUSH is set. | |
144 | * | |
145 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
146 | * invalidated with every MI_FLUSH. | |
147 | * | |
148 | * TLBs: | |
149 | * | |
150 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
151 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
152 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
153 | * are flushed at any MI_FLUSH. | |
154 | */ | |
155 | ||
156 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
46f0f8d1 | 157 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
36d527de | 158 | cmd &= ~MI_NO_WRITE_FLUSH; |
36d527de CW |
159 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
160 | cmd |= MI_EXE_FLUSH; | |
62fdfeaf | 161 | |
36d527de CW |
162 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
163 | (IS_G4X(dev) || IS_GEN5(dev))) | |
164 | cmd |= MI_INVALIDATE_ISP; | |
70eac33e | 165 | |
36d527de CW |
166 | ret = intel_ring_begin(ring, 2); |
167 | if (ret) | |
168 | return ret; | |
b72f3acb | 169 | |
36d527de CW |
170 | intel_ring_emit(ring, cmd); |
171 | intel_ring_emit(ring, MI_NOOP); | |
172 | intel_ring_advance(ring); | |
b72f3acb CW |
173 | |
174 | return 0; | |
8187a2b7 ZN |
175 | } |
176 | ||
8d315287 JB |
177 | /** |
178 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
179 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
180 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
181 | * | |
182 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
183 | * produced by non-pipelined state commands), software needs to first | |
184 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
185 | * 0. | |
186 | * | |
187 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
188 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
189 | * | |
190 | * And the workaround for these two requires this workaround first: | |
191 | * | |
192 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
193 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
194 | * flushes. | |
195 | * | |
196 | * And this last workaround is tricky because of the requirements on | |
197 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
198 | * volume 2 part 1: | |
199 | * | |
200 | * "1 of the following must also be set: | |
201 | * - Render Target Cache Flush Enable ([12] of DW1) | |
202 | * - Depth Cache Flush Enable ([0] of DW1) | |
203 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
204 | * - Depth Stall ([13] of DW1) | |
205 | * - Post-Sync Operation ([13] of DW1) | |
206 | * - Notify Enable ([8] of DW1)" | |
207 | * | |
208 | * The cache flushes require the workaround flush that triggered this | |
209 | * one, so we can't use it. Depth stall would trigger the same. | |
210 | * Post-sync nonzero is what triggered this second workaround, so we | |
211 | * can't use that one either. Notify enable is IRQs, which aren't | |
212 | * really our business. That leaves only stall at scoreboard. | |
213 | */ | |
214 | static int | |
a4872ba6 | 215 | intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring) |
8d315287 | 216 | { |
18393f63 | 217 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
218 | int ret; |
219 | ||
220 | ||
221 | ret = intel_ring_begin(ring, 6); | |
222 | if (ret) | |
223 | return ret; | |
224 | ||
225 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
226 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
227 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
228 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
229 | intel_ring_emit(ring, 0); /* low dword */ | |
230 | intel_ring_emit(ring, 0); /* high dword */ | |
231 | intel_ring_emit(ring, MI_NOOP); | |
232 | intel_ring_advance(ring); | |
233 | ||
234 | ret = intel_ring_begin(ring, 6); | |
235 | if (ret) | |
236 | return ret; | |
237 | ||
238 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
239 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); | |
240 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
241 | intel_ring_emit(ring, 0); | |
242 | intel_ring_emit(ring, 0); | |
243 | intel_ring_emit(ring, MI_NOOP); | |
244 | intel_ring_advance(ring); | |
245 | ||
246 | return 0; | |
247 | } | |
248 | ||
249 | static int | |
a4872ba6 | 250 | gen6_render_ring_flush(struct intel_engine_cs *ring, |
8d315287 JB |
251 | u32 invalidate_domains, u32 flush_domains) |
252 | { | |
253 | u32 flags = 0; | |
18393f63 | 254 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
255 | int ret; |
256 | ||
b3111509 PZ |
257 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
258 | ret = intel_emit_post_sync_nonzero_flush(ring); | |
259 | if (ret) | |
260 | return ret; | |
261 | ||
8d315287 JB |
262 | /* Just flush everything. Experiments have shown that reducing the |
263 | * number of bits based on the write domains has little performance | |
264 | * impact. | |
265 | */ | |
7d54a904 CW |
266 | if (flush_domains) { |
267 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
268 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
269 | /* | |
270 | * Ensure that any following seqno writes only happen | |
271 | * when the render cache is indeed flushed. | |
272 | */ | |
97f209bc | 273 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 CW |
274 | } |
275 | if (invalidate_domains) { | |
276 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
277 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
278 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
279 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
280 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
281 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
282 | /* | |
283 | * TLB invalidate requires a post-sync write. | |
284 | */ | |
3ac78313 | 285 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 286 | } |
8d315287 | 287 | |
6c6cf5aa | 288 | ret = intel_ring_begin(ring, 4); |
8d315287 JB |
289 | if (ret) |
290 | return ret; | |
291 | ||
6c6cf5aa | 292 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
8d315287 JB |
293 | intel_ring_emit(ring, flags); |
294 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
6c6cf5aa | 295 | intel_ring_emit(ring, 0); |
8d315287 JB |
296 | intel_ring_advance(ring); |
297 | ||
298 | return 0; | |
299 | } | |
300 | ||
f3987631 | 301 | static int |
a4872ba6 | 302 | gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring) |
f3987631 PZ |
303 | { |
304 | int ret; | |
305 | ||
306 | ret = intel_ring_begin(ring, 4); | |
307 | if (ret) | |
308 | return ret; | |
309 | ||
310 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
311 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
312 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
313 | intel_ring_emit(ring, 0); | |
314 | intel_ring_emit(ring, 0); | |
315 | intel_ring_advance(ring); | |
316 | ||
317 | return 0; | |
318 | } | |
319 | ||
a4872ba6 | 320 | static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value) |
fd3da6c9 RV |
321 | { |
322 | int ret; | |
323 | ||
324 | if (!ring->fbc_dirty) | |
325 | return 0; | |
326 | ||
37c1d94f | 327 | ret = intel_ring_begin(ring, 6); |
fd3da6c9 RV |
328 | if (ret) |
329 | return ret; | |
fd3da6c9 RV |
330 | /* WaFbcNukeOn3DBlt:ivb/hsw */ |
331 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
332 | intel_ring_emit(ring, MSG_FBC_REND_STATE); | |
333 | intel_ring_emit(ring, value); | |
37c1d94f VS |
334 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT); |
335 | intel_ring_emit(ring, MSG_FBC_REND_STATE); | |
336 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
fd3da6c9 RV |
337 | intel_ring_advance(ring); |
338 | ||
339 | ring->fbc_dirty = false; | |
340 | return 0; | |
341 | } | |
342 | ||
4772eaeb | 343 | static int |
a4872ba6 | 344 | gen7_render_ring_flush(struct intel_engine_cs *ring, |
4772eaeb PZ |
345 | u32 invalidate_domains, u32 flush_domains) |
346 | { | |
347 | u32 flags = 0; | |
18393f63 | 348 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
4772eaeb PZ |
349 | int ret; |
350 | ||
f3987631 PZ |
351 | /* |
352 | * Ensure that any following seqno writes only happen when the render | |
353 | * cache is indeed flushed. | |
354 | * | |
355 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
356 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
357 | * don't try to be clever and just set it unconditionally. | |
358 | */ | |
359 | flags |= PIPE_CONTROL_CS_STALL; | |
360 | ||
4772eaeb PZ |
361 | /* Just flush everything. Experiments have shown that reducing the |
362 | * number of bits based on the write domains has little performance | |
363 | * impact. | |
364 | */ | |
365 | if (flush_domains) { | |
366 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
367 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
4772eaeb PZ |
368 | } |
369 | if (invalidate_domains) { | |
370 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
371 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
372 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
373 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
374 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
375 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
376 | /* | |
377 | * TLB invalidate requires a post-sync write. | |
378 | */ | |
379 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 380 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 PZ |
381 | |
382 | /* Workaround: we must issue a pipe_control with CS-stall bit | |
383 | * set before a pipe_control command that has the state cache | |
384 | * invalidate bit set. */ | |
385 | gen7_render_ring_cs_stall_wa(ring); | |
4772eaeb PZ |
386 | } |
387 | ||
388 | ret = intel_ring_begin(ring, 4); | |
389 | if (ret) | |
390 | return ret; | |
391 | ||
392 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
393 | intel_ring_emit(ring, flags); | |
b9e1faa7 | 394 | intel_ring_emit(ring, scratch_addr); |
4772eaeb PZ |
395 | intel_ring_emit(ring, 0); |
396 | intel_ring_advance(ring); | |
397 | ||
9688ecad | 398 | if (!invalidate_domains && flush_domains) |
fd3da6c9 RV |
399 | return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); |
400 | ||
4772eaeb PZ |
401 | return 0; |
402 | } | |
403 | ||
884ceace KG |
404 | static int |
405 | gen8_emit_pipe_control(struct intel_engine_cs *ring, | |
406 | u32 flags, u32 scratch_addr) | |
407 | { | |
408 | int ret; | |
409 | ||
410 | ret = intel_ring_begin(ring, 6); | |
411 | if (ret) | |
412 | return ret; | |
413 | ||
414 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); | |
415 | intel_ring_emit(ring, flags); | |
416 | intel_ring_emit(ring, scratch_addr); | |
417 | intel_ring_emit(ring, 0); | |
418 | intel_ring_emit(ring, 0); | |
419 | intel_ring_emit(ring, 0); | |
420 | intel_ring_advance(ring); | |
421 | ||
422 | return 0; | |
423 | } | |
424 | ||
a5f3d68e | 425 | static int |
a4872ba6 | 426 | gen8_render_ring_flush(struct intel_engine_cs *ring, |
a5f3d68e BW |
427 | u32 invalidate_domains, u32 flush_domains) |
428 | { | |
429 | u32 flags = 0; | |
18393f63 | 430 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
02c9f7e3 | 431 | int ret; |
a5f3d68e BW |
432 | |
433 | flags |= PIPE_CONTROL_CS_STALL; | |
434 | ||
435 | if (flush_domains) { | |
436 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
437 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
438 | } | |
439 | if (invalidate_domains) { | |
440 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
441 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
442 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
443 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
444 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
445 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
446 | flags |= PIPE_CONTROL_QW_WRITE; | |
447 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
02c9f7e3 KG |
448 | |
449 | /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ | |
450 | ret = gen8_emit_pipe_control(ring, | |
451 | PIPE_CONTROL_CS_STALL | | |
452 | PIPE_CONTROL_STALL_AT_SCOREBOARD, | |
453 | 0); | |
454 | if (ret) | |
455 | return ret; | |
a5f3d68e BW |
456 | } |
457 | ||
c5ad011d RV |
458 | ret = gen8_emit_pipe_control(ring, flags, scratch_addr); |
459 | if (ret) | |
460 | return ret; | |
461 | ||
462 | if (!invalidate_domains && flush_domains) | |
463 | return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); | |
464 | ||
465 | return 0; | |
a5f3d68e BW |
466 | } |
467 | ||
a4872ba6 | 468 | static void ring_write_tail(struct intel_engine_cs *ring, |
297b0c5b | 469 | u32 value) |
d46eefa2 | 470 | { |
4640c4ff | 471 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
297b0c5b | 472 | I915_WRITE_TAIL(ring, value); |
d46eefa2 XH |
473 | } |
474 | ||
a4872ba6 | 475 | u64 intel_ring_get_active_head(struct intel_engine_cs *ring) |
8187a2b7 | 476 | { |
4640c4ff | 477 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
50877445 | 478 | u64 acthd; |
8187a2b7 | 479 | |
50877445 CW |
480 | if (INTEL_INFO(ring->dev)->gen >= 8) |
481 | acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base), | |
482 | RING_ACTHD_UDW(ring->mmio_base)); | |
483 | else if (INTEL_INFO(ring->dev)->gen >= 4) | |
484 | acthd = I915_READ(RING_ACTHD(ring->mmio_base)); | |
485 | else | |
486 | acthd = I915_READ(ACTHD); | |
487 | ||
488 | return acthd; | |
8187a2b7 ZN |
489 | } |
490 | ||
a4872ba6 | 491 | static void ring_setup_phys_status_page(struct intel_engine_cs *ring) |
035dc1e0 DV |
492 | { |
493 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
494 | u32 addr; | |
495 | ||
496 | addr = dev_priv->status_page_dmah->busaddr; | |
497 | if (INTEL_INFO(ring->dev)->gen >= 4) | |
498 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; | |
499 | I915_WRITE(HWS_PGA, addr); | |
500 | } | |
501 | ||
a4872ba6 | 502 | static bool stop_ring(struct intel_engine_cs *ring) |
8187a2b7 | 503 | { |
9991ae78 | 504 | struct drm_i915_private *dev_priv = to_i915(ring->dev); |
8187a2b7 | 505 | |
9991ae78 CW |
506 | if (!IS_GEN2(ring->dev)) { |
507 | I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); | |
403bdd10 DV |
508 | if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { |
509 | DRM_ERROR("%s : timed out trying to stop ring\n", ring->name); | |
9bec9b13 CW |
510 | /* Sometimes we observe that the idle flag is not |
511 | * set even though the ring is empty. So double | |
512 | * check before giving up. | |
513 | */ | |
514 | if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring)) | |
515 | return false; | |
9991ae78 CW |
516 | } |
517 | } | |
b7884eb4 | 518 | |
7f2ab699 | 519 | I915_WRITE_CTL(ring, 0); |
570ef608 | 520 | I915_WRITE_HEAD(ring, 0); |
78501eac | 521 | ring->write_tail(ring, 0); |
8187a2b7 | 522 | |
9991ae78 CW |
523 | if (!IS_GEN2(ring->dev)) { |
524 | (void)I915_READ_CTL(ring); | |
525 | I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); | |
526 | } | |
a51435a3 | 527 | |
9991ae78 CW |
528 | return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0; |
529 | } | |
8187a2b7 | 530 | |
a4872ba6 | 531 | static int init_ring_common(struct intel_engine_cs *ring) |
9991ae78 CW |
532 | { |
533 | struct drm_device *dev = ring->dev; | |
534 | struct drm_i915_private *dev_priv = dev->dev_private; | |
93b0a4e0 OM |
535 | struct intel_ringbuffer *ringbuf = ring->buffer; |
536 | struct drm_i915_gem_object *obj = ringbuf->obj; | |
9991ae78 CW |
537 | int ret = 0; |
538 | ||
539 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); | |
540 | ||
541 | if (!stop_ring(ring)) { | |
542 | /* G45 ring initialization often fails to reset head to zero */ | |
6fd0d56e CW |
543 | DRM_DEBUG_KMS("%s head not reset to zero " |
544 | "ctl %08x head %08x tail %08x start %08x\n", | |
545 | ring->name, | |
546 | I915_READ_CTL(ring), | |
547 | I915_READ_HEAD(ring), | |
548 | I915_READ_TAIL(ring), | |
549 | I915_READ_START(ring)); | |
8187a2b7 | 550 | |
9991ae78 | 551 | if (!stop_ring(ring)) { |
6fd0d56e CW |
552 | DRM_ERROR("failed to set %s head to zero " |
553 | "ctl %08x head %08x tail %08x start %08x\n", | |
554 | ring->name, | |
555 | I915_READ_CTL(ring), | |
556 | I915_READ_HEAD(ring), | |
557 | I915_READ_TAIL(ring), | |
558 | I915_READ_START(ring)); | |
9991ae78 CW |
559 | ret = -EIO; |
560 | goto out; | |
6fd0d56e | 561 | } |
8187a2b7 ZN |
562 | } |
563 | ||
9991ae78 CW |
564 | if (I915_NEED_GFX_HWS(dev)) |
565 | intel_ring_setup_status_page(ring); | |
566 | else | |
567 | ring_setup_phys_status_page(ring); | |
568 | ||
ece4a17d JK |
569 | /* Enforce ordering by reading HEAD register back */ |
570 | I915_READ_HEAD(ring); | |
571 | ||
0d8957c8 DV |
572 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
573 | * registers with the above sequence (the readback of the HEAD registers | |
574 | * also enforces ordering), otherwise the hw might lose the new ring | |
575 | * register values. */ | |
f343c5f6 | 576 | I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj)); |
95468892 CW |
577 | |
578 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ | |
579 | if (I915_READ_HEAD(ring)) | |
580 | DRM_DEBUG("%s initialization failed [head=%08x], fudging\n", | |
581 | ring->name, I915_READ_HEAD(ring)); | |
582 | I915_WRITE_HEAD(ring, 0); | |
583 | (void)I915_READ_HEAD(ring); | |
584 | ||
7f2ab699 | 585 | I915_WRITE_CTL(ring, |
93b0a4e0 | 586 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 587 | | RING_VALID); |
8187a2b7 | 588 | |
8187a2b7 | 589 | /* If the head is still not zero, the ring is dead */ |
f01db988 | 590 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
f343c5f6 | 591 | I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) && |
f01db988 | 592 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { |
e74cfed5 | 593 | DRM_ERROR("%s initialization failed " |
48e48a0b CW |
594 | "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n", |
595 | ring->name, | |
596 | I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID, | |
597 | I915_READ_HEAD(ring), I915_READ_TAIL(ring), | |
598 | I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj)); | |
b7884eb4 DV |
599 | ret = -EIO; |
600 | goto out; | |
8187a2b7 ZN |
601 | } |
602 | ||
ebd0fd4b | 603 | ringbuf->last_retired_head = -1; |
5c6c6003 CW |
604 | ringbuf->head = I915_READ_HEAD(ring); |
605 | ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR; | |
ebd0fd4b | 606 | intel_ring_update_space(ringbuf); |
1ec14ad3 | 607 | |
50f018df CW |
608 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); |
609 | ||
b7884eb4 | 610 | out: |
c8d9a590 | 611 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
612 | |
613 | return ret; | |
8187a2b7 ZN |
614 | } |
615 | ||
9b1136d5 OM |
616 | void |
617 | intel_fini_pipe_control(struct intel_engine_cs *ring) | |
618 | { | |
619 | struct drm_device *dev = ring->dev; | |
620 | ||
621 | if (ring->scratch.obj == NULL) | |
622 | return; | |
623 | ||
624 | if (INTEL_INFO(dev)->gen >= 5) { | |
625 | kunmap(sg_page(ring->scratch.obj->pages->sgl)); | |
626 | i915_gem_object_ggtt_unpin(ring->scratch.obj); | |
627 | } | |
628 | ||
629 | drm_gem_object_unreference(&ring->scratch.obj->base); | |
630 | ring->scratch.obj = NULL; | |
631 | } | |
632 | ||
633 | int | |
634 | intel_init_pipe_control(struct intel_engine_cs *ring) | |
c6df541c | 635 | { |
c6df541c CW |
636 | int ret; |
637 | ||
bfc882b4 | 638 | WARN_ON(ring->scratch.obj); |
c6df541c | 639 | |
0d1aacac CW |
640 | ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096); |
641 | if (ring->scratch.obj == NULL) { | |
c6df541c CW |
642 | DRM_ERROR("Failed to allocate seqno page\n"); |
643 | ret = -ENOMEM; | |
644 | goto err; | |
645 | } | |
e4ffd173 | 646 | |
a9cc726c DV |
647 | ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC); |
648 | if (ret) | |
649 | goto err_unref; | |
c6df541c | 650 | |
1ec9e26d | 651 | ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0); |
c6df541c CW |
652 | if (ret) |
653 | goto err_unref; | |
654 | ||
0d1aacac CW |
655 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj); |
656 | ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl)); | |
657 | if (ring->scratch.cpu_page == NULL) { | |
56b085a0 | 658 | ret = -ENOMEM; |
c6df541c | 659 | goto err_unpin; |
56b085a0 | 660 | } |
c6df541c | 661 | |
2b1086cc | 662 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
0d1aacac | 663 | ring->name, ring->scratch.gtt_offset); |
c6df541c CW |
664 | return 0; |
665 | ||
666 | err_unpin: | |
d7f46fc4 | 667 | i915_gem_object_ggtt_unpin(ring->scratch.obj); |
c6df541c | 668 | err_unref: |
0d1aacac | 669 | drm_gem_object_unreference(&ring->scratch.obj->base); |
c6df541c | 670 | err: |
c6df541c CW |
671 | return ret; |
672 | } | |
673 | ||
771b9a53 MT |
674 | static int intel_ring_workarounds_emit(struct intel_engine_cs *ring, |
675 | struct intel_context *ctx) | |
86d7f238 | 676 | { |
7225342a | 677 | int ret, i; |
888b5995 AS |
678 | struct drm_device *dev = ring->dev; |
679 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7225342a | 680 | struct i915_workarounds *w = &dev_priv->workarounds; |
888b5995 | 681 | |
7225342a MK |
682 | if (WARN_ON(w->count == 0)) |
683 | return 0; | |
888b5995 | 684 | |
7225342a MK |
685 | ring->gpu_caches_dirty = true; |
686 | ret = intel_ring_flush_all_caches(ring); | |
687 | if (ret) | |
688 | return ret; | |
888b5995 | 689 | |
22a916aa | 690 | ret = intel_ring_begin(ring, (w->count * 2 + 2)); |
7225342a MK |
691 | if (ret) |
692 | return ret; | |
693 | ||
22a916aa | 694 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count)); |
7225342a | 695 | for (i = 0; i < w->count; i++) { |
7225342a MK |
696 | intel_ring_emit(ring, w->reg[i].addr); |
697 | intel_ring_emit(ring, w->reg[i].value); | |
698 | } | |
22a916aa | 699 | intel_ring_emit(ring, MI_NOOP); |
7225342a MK |
700 | |
701 | intel_ring_advance(ring); | |
702 | ||
703 | ring->gpu_caches_dirty = true; | |
704 | ret = intel_ring_flush_all_caches(ring); | |
705 | if (ret) | |
706 | return ret; | |
888b5995 | 707 | |
7225342a | 708 | DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count); |
888b5995 | 709 | |
7225342a | 710 | return 0; |
86d7f238 AS |
711 | } |
712 | ||
8f0e2b9d DV |
713 | static int intel_rcs_ctx_init(struct intel_engine_cs *ring, |
714 | struct intel_context *ctx) | |
715 | { | |
716 | int ret; | |
717 | ||
718 | ret = intel_ring_workarounds_emit(ring, ctx); | |
719 | if (ret != 0) | |
720 | return ret; | |
721 | ||
722 | ret = i915_gem_render_state_init(ring); | |
723 | if (ret) | |
724 | DRM_ERROR("init render state: %d\n", ret); | |
725 | ||
726 | return ret; | |
727 | } | |
728 | ||
7225342a MK |
729 | static int wa_add(struct drm_i915_private *dev_priv, |
730 | const u32 addr, const u32 val, const u32 mask) | |
731 | { | |
732 | const u32 idx = dev_priv->workarounds.count; | |
733 | ||
734 | if (WARN_ON(idx >= I915_MAX_WA_REGS)) | |
735 | return -ENOSPC; | |
736 | ||
737 | dev_priv->workarounds.reg[idx].addr = addr; | |
738 | dev_priv->workarounds.reg[idx].value = val; | |
739 | dev_priv->workarounds.reg[idx].mask = mask; | |
740 | ||
741 | dev_priv->workarounds.count++; | |
742 | ||
743 | return 0; | |
86d7f238 AS |
744 | } |
745 | ||
7225342a MK |
746 | #define WA_REG(addr, val, mask) { \ |
747 | const int r = wa_add(dev_priv, (addr), (val), (mask)); \ | |
748 | if (r) \ | |
749 | return r; \ | |
750 | } | |
751 | ||
752 | #define WA_SET_BIT_MASKED(addr, mask) \ | |
753 | WA_REG(addr, _MASKED_BIT_ENABLE(mask), (mask) & 0xffff) | |
754 | ||
755 | #define WA_CLR_BIT_MASKED(addr, mask) \ | |
756 | WA_REG(addr, _MASKED_BIT_DISABLE(mask), (mask) & 0xffff) | |
757 | ||
758 | #define WA_SET_BIT(addr, mask) WA_REG(addr, I915_READ(addr) | (mask), mask) | |
759 | #define WA_CLR_BIT(addr, mask) WA_REG(addr, I915_READ(addr) & ~(mask), mask) | |
760 | ||
761 | #define WA_WRITE(addr, val) WA_REG(addr, val, 0xffffffff) | |
762 | ||
00e1e623 | 763 | static int bdw_init_workarounds(struct intel_engine_cs *ring) |
86d7f238 | 764 | { |
888b5995 AS |
765 | struct drm_device *dev = ring->dev; |
766 | struct drm_i915_private *dev_priv = dev->dev_private; | |
86d7f238 | 767 | |
86d7f238 | 768 | /* WaDisablePartialInstShootdown:bdw */ |
101b376d | 769 | /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ |
7225342a MK |
770 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
771 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE | | |
772 | STALL_DOP_GATING_DISABLE); | |
86d7f238 | 773 | |
101b376d | 774 | /* WaDisableDopClockGating:bdw */ |
7225342a MK |
775 | WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, |
776 | DOP_CLOCK_GATING_DISABLE); | |
86d7f238 | 777 | |
7225342a MK |
778 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
779 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
86d7f238 AS |
780 | |
781 | /* Use Force Non-Coherent whenever executing a 3D context. This is a | |
782 | * workaround for for a possible hang in the unlikely event a TLB | |
783 | * invalidation occurs during a PSD flush. | |
784 | */ | |
1a252058 | 785 | /* WaForceEnableNonCoherent:bdw */ |
f3f32360 | 786 | /* WaHdcDisableFetchWhenMasked:bdw */ |
da09654d | 787 | /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */ |
7225342a MK |
788 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
789 | HDC_FORCE_NON_COHERENT | | |
f3f32360 | 790 | HDC_DONOT_FETCH_MEM_WHEN_MASKED | |
7225342a | 791 | (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); |
86d7f238 AS |
792 | |
793 | /* Wa4x4STCOptimizationDisable:bdw */ | |
7225342a MK |
794 | WA_SET_BIT_MASKED(CACHE_MODE_1, |
795 | GEN8_4x4_STC_OPTIMIZATION_DISABLE); | |
86d7f238 AS |
796 | |
797 | /* | |
798 | * BSpec recommends 8x4 when MSAA is used, | |
799 | * however in practice 16x4 seems fastest. | |
800 | * | |
801 | * Note that PS/WM thread counts depend on the WIZ hashing | |
802 | * disable bit, which we don't touch here, but it's good | |
803 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
804 | */ | |
7225342a MK |
805 | WA_SET_BIT_MASKED(GEN7_GT_MODE, |
806 | GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); | |
888b5995 | 807 | |
86d7f238 AS |
808 | return 0; |
809 | } | |
810 | ||
00e1e623 VS |
811 | static int chv_init_workarounds(struct intel_engine_cs *ring) |
812 | { | |
00e1e623 VS |
813 | struct drm_device *dev = ring->dev; |
814 | struct drm_i915_private *dev_priv = dev->dev_private; | |
815 | ||
00e1e623 | 816 | /* WaDisablePartialInstShootdown:chv */ |
00e1e623 | 817 | /* WaDisableThreadStallDopClockGating:chv */ |
7225342a | 818 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
605f1433 AS |
819 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE | |
820 | STALL_DOP_GATING_DISABLE); | |
00e1e623 | 821 | |
95289009 AS |
822 | /* Use Force Non-Coherent whenever executing a 3D context. This is a |
823 | * workaround for a possible hang in the unlikely event a TLB | |
824 | * invalidation occurs during a PSD flush. | |
825 | */ | |
826 | /* WaForceEnableNonCoherent:chv */ | |
827 | /* WaHdcDisableFetchWhenMasked:chv */ | |
828 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
829 | HDC_FORCE_NON_COHERENT | | |
830 | HDC_DONOT_FETCH_MEM_WHEN_MASKED); | |
831 | ||
7225342a MK |
832 | return 0; |
833 | } | |
834 | ||
771b9a53 | 835 | int init_workarounds_ring(struct intel_engine_cs *ring) |
7225342a MK |
836 | { |
837 | struct drm_device *dev = ring->dev; | |
838 | struct drm_i915_private *dev_priv = dev->dev_private; | |
839 | ||
840 | WARN_ON(ring->id != RCS); | |
841 | ||
842 | dev_priv->workarounds.count = 0; | |
843 | ||
844 | if (IS_BROADWELL(dev)) | |
845 | return bdw_init_workarounds(ring); | |
846 | ||
847 | if (IS_CHERRYVIEW(dev)) | |
848 | return chv_init_workarounds(ring); | |
00e1e623 VS |
849 | |
850 | return 0; | |
851 | } | |
852 | ||
a4872ba6 | 853 | static int init_render_ring(struct intel_engine_cs *ring) |
8187a2b7 | 854 | { |
78501eac | 855 | struct drm_device *dev = ring->dev; |
1ec14ad3 | 856 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 857 | int ret = init_ring_common(ring); |
9c33baa6 KZ |
858 | if (ret) |
859 | return ret; | |
a69ffdbf | 860 | |
61a563a2 AG |
861 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
862 | if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7) | |
6b26c86d | 863 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
864 | |
865 | /* We need to disable the AsyncFlip performance optimisations in order | |
866 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
867 | * programmed to '1' on all products. | |
8693a824 | 868 | * |
b3f797ac | 869 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv |
1c8c38c5 | 870 | */ |
fbdcb068 | 871 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9) |
1c8c38c5 CW |
872 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
873 | ||
f05bb0c7 | 874 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 875 | /* WaEnableFlushTlbInvalidationMode:snb */ |
f05bb0c7 CW |
876 | if (INTEL_INFO(dev)->gen == 6) |
877 | I915_WRITE(GFX_MODE, | |
aa83e30d | 878 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 879 | |
01fa0302 | 880 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
1c8c38c5 CW |
881 | if (IS_GEN7(dev)) |
882 | I915_WRITE(GFX_MODE_GEN7, | |
01fa0302 | 883 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 884 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 885 | |
5e13a0c5 | 886 | if (IS_GEN6(dev)) { |
3a69ddd6 KG |
887 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
888 | * "If this bit is set, STCunit will have LRA as replacement | |
889 | * policy. [...] This bit must be reset. LRA replacement | |
890 | * policy is not supported." | |
891 | */ | |
892 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 893 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
894 | } |
895 | ||
6b26c86d DV |
896 | if (INTEL_INFO(dev)->gen >= 6) |
897 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); | |
84f9f938 | 898 | |
040d2baa | 899 | if (HAS_L3_DPF(dev)) |
35a85ac6 | 900 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
15b9f80e | 901 | |
7225342a | 902 | return init_workarounds_ring(ring); |
8187a2b7 ZN |
903 | } |
904 | ||
a4872ba6 | 905 | static void render_ring_cleanup(struct intel_engine_cs *ring) |
c6df541c | 906 | { |
b45305fc | 907 | struct drm_device *dev = ring->dev; |
3e78998a BW |
908 | struct drm_i915_private *dev_priv = dev->dev_private; |
909 | ||
910 | if (dev_priv->semaphore_obj) { | |
911 | i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj); | |
912 | drm_gem_object_unreference(&dev_priv->semaphore_obj->base); | |
913 | dev_priv->semaphore_obj = NULL; | |
914 | } | |
b45305fc | 915 | |
9b1136d5 | 916 | intel_fini_pipe_control(ring); |
c6df541c CW |
917 | } |
918 | ||
3e78998a BW |
919 | static int gen8_rcs_signal(struct intel_engine_cs *signaller, |
920 | unsigned int num_dwords) | |
921 | { | |
922 | #define MBOX_UPDATE_DWORDS 8 | |
923 | struct drm_device *dev = signaller->dev; | |
924 | struct drm_i915_private *dev_priv = dev->dev_private; | |
925 | struct intel_engine_cs *waiter; | |
926 | int i, ret, num_rings; | |
927 | ||
928 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
929 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; | |
930 | #undef MBOX_UPDATE_DWORDS | |
931 | ||
932 | ret = intel_ring_begin(signaller, num_dwords); | |
933 | if (ret) | |
934 | return ret; | |
935 | ||
936 | for_each_ring(waiter, dev_priv, i) { | |
6259cead | 937 | u32 seqno; |
3e78998a BW |
938 | u64 gtt_offset = signaller->semaphore.signal_ggtt[i]; |
939 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) | |
940 | continue; | |
941 | ||
6259cead JH |
942 | seqno = i915_gem_request_get_seqno( |
943 | signaller->outstanding_lazy_request); | |
3e78998a BW |
944 | intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6)); |
945 | intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB | | |
946 | PIPE_CONTROL_QW_WRITE | | |
947 | PIPE_CONTROL_FLUSH_ENABLE); | |
948 | intel_ring_emit(signaller, lower_32_bits(gtt_offset)); | |
949 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
6259cead | 950 | intel_ring_emit(signaller, seqno); |
3e78998a BW |
951 | intel_ring_emit(signaller, 0); |
952 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | | |
953 | MI_SEMAPHORE_TARGET(waiter->id)); | |
954 | intel_ring_emit(signaller, 0); | |
955 | } | |
956 | ||
957 | return 0; | |
958 | } | |
959 | ||
960 | static int gen8_xcs_signal(struct intel_engine_cs *signaller, | |
961 | unsigned int num_dwords) | |
962 | { | |
963 | #define MBOX_UPDATE_DWORDS 6 | |
964 | struct drm_device *dev = signaller->dev; | |
965 | struct drm_i915_private *dev_priv = dev->dev_private; | |
966 | struct intel_engine_cs *waiter; | |
967 | int i, ret, num_rings; | |
968 | ||
969 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
970 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; | |
971 | #undef MBOX_UPDATE_DWORDS | |
972 | ||
973 | ret = intel_ring_begin(signaller, num_dwords); | |
974 | if (ret) | |
975 | return ret; | |
976 | ||
977 | for_each_ring(waiter, dev_priv, i) { | |
6259cead | 978 | u32 seqno; |
3e78998a BW |
979 | u64 gtt_offset = signaller->semaphore.signal_ggtt[i]; |
980 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) | |
981 | continue; | |
982 | ||
6259cead JH |
983 | seqno = i915_gem_request_get_seqno( |
984 | signaller->outstanding_lazy_request); | |
3e78998a BW |
985 | intel_ring_emit(signaller, (MI_FLUSH_DW + 1) | |
986 | MI_FLUSH_DW_OP_STOREDW); | |
987 | intel_ring_emit(signaller, lower_32_bits(gtt_offset) | | |
988 | MI_FLUSH_DW_USE_GTT); | |
989 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
6259cead | 990 | intel_ring_emit(signaller, seqno); |
3e78998a BW |
991 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | |
992 | MI_SEMAPHORE_TARGET(waiter->id)); | |
993 | intel_ring_emit(signaller, 0); | |
994 | } | |
995 | ||
996 | return 0; | |
997 | } | |
998 | ||
a4872ba6 | 999 | static int gen6_signal(struct intel_engine_cs *signaller, |
024a43e1 | 1000 | unsigned int num_dwords) |
1ec14ad3 | 1001 | { |
024a43e1 BW |
1002 | struct drm_device *dev = signaller->dev; |
1003 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 1004 | struct intel_engine_cs *useless; |
a1444b79 | 1005 | int i, ret, num_rings; |
78325f2d | 1006 | |
a1444b79 BW |
1007 | #define MBOX_UPDATE_DWORDS 3 |
1008 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
1009 | num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2); | |
1010 | #undef MBOX_UPDATE_DWORDS | |
024a43e1 BW |
1011 | |
1012 | ret = intel_ring_begin(signaller, num_dwords); | |
1013 | if (ret) | |
1014 | return ret; | |
024a43e1 | 1015 | |
78325f2d BW |
1016 | for_each_ring(useless, dev_priv, i) { |
1017 | u32 mbox_reg = signaller->semaphore.mbox.signal[i]; | |
1018 | if (mbox_reg != GEN6_NOSYNC) { | |
6259cead JH |
1019 | u32 seqno = i915_gem_request_get_seqno( |
1020 | signaller->outstanding_lazy_request); | |
78325f2d BW |
1021 | intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1)); |
1022 | intel_ring_emit(signaller, mbox_reg); | |
6259cead | 1023 | intel_ring_emit(signaller, seqno); |
78325f2d BW |
1024 | } |
1025 | } | |
024a43e1 | 1026 | |
a1444b79 BW |
1027 | /* If num_dwords was rounded, make sure the tail pointer is correct */ |
1028 | if (num_rings % 2 == 0) | |
1029 | intel_ring_emit(signaller, MI_NOOP); | |
1030 | ||
024a43e1 | 1031 | return 0; |
1ec14ad3 CW |
1032 | } |
1033 | ||
c8c99b0f BW |
1034 | /** |
1035 | * gen6_add_request - Update the semaphore mailbox registers | |
1036 | * | |
1037 | * @ring - ring that is adding a request | |
1038 | * @seqno - return seqno stuck into the ring | |
1039 | * | |
1040 | * Update the mailbox registers in the *other* rings with the current seqno. | |
1041 | * This acts like a signal in the canonical semaphore. | |
1042 | */ | |
1ec14ad3 | 1043 | static int |
a4872ba6 | 1044 | gen6_add_request(struct intel_engine_cs *ring) |
1ec14ad3 | 1045 | { |
024a43e1 | 1046 | int ret; |
52ed2325 | 1047 | |
707d9cf9 BW |
1048 | if (ring->semaphore.signal) |
1049 | ret = ring->semaphore.signal(ring, 4); | |
1050 | else | |
1051 | ret = intel_ring_begin(ring, 4); | |
1052 | ||
1ec14ad3 CW |
1053 | if (ret) |
1054 | return ret; | |
1055 | ||
1ec14ad3 CW |
1056 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
1057 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
6259cead JH |
1058 | intel_ring_emit(ring, |
1059 | i915_gem_request_get_seqno(ring->outstanding_lazy_request)); | |
1ec14ad3 | 1060 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
09246732 | 1061 | __intel_ring_advance(ring); |
1ec14ad3 | 1062 | |
1ec14ad3 CW |
1063 | return 0; |
1064 | } | |
1065 | ||
f72b3435 MK |
1066 | static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, |
1067 | u32 seqno) | |
1068 | { | |
1069 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070 | return dev_priv->last_seqno < seqno; | |
1071 | } | |
1072 | ||
c8c99b0f BW |
1073 | /** |
1074 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
1075 | * | |
1076 | * @waiter - ring that is waiting | |
1077 | * @signaller - ring which has, or will signal | |
1078 | * @seqno - seqno which the waiter will block on | |
1079 | */ | |
5ee426ca BW |
1080 | |
1081 | static int | |
1082 | gen8_ring_sync(struct intel_engine_cs *waiter, | |
1083 | struct intel_engine_cs *signaller, | |
1084 | u32 seqno) | |
1085 | { | |
1086 | struct drm_i915_private *dev_priv = waiter->dev->dev_private; | |
1087 | int ret; | |
1088 | ||
1089 | ret = intel_ring_begin(waiter, 4); | |
1090 | if (ret) | |
1091 | return ret; | |
1092 | ||
1093 | intel_ring_emit(waiter, MI_SEMAPHORE_WAIT | | |
1094 | MI_SEMAPHORE_GLOBAL_GTT | | |
bae4fcd2 | 1095 | MI_SEMAPHORE_POLL | |
5ee426ca BW |
1096 | MI_SEMAPHORE_SAD_GTE_SDD); |
1097 | intel_ring_emit(waiter, seqno); | |
1098 | intel_ring_emit(waiter, | |
1099 | lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); | |
1100 | intel_ring_emit(waiter, | |
1101 | upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); | |
1102 | intel_ring_advance(waiter); | |
1103 | return 0; | |
1104 | } | |
1105 | ||
c8c99b0f | 1106 | static int |
a4872ba6 OM |
1107 | gen6_ring_sync(struct intel_engine_cs *waiter, |
1108 | struct intel_engine_cs *signaller, | |
686cb5f9 | 1109 | u32 seqno) |
1ec14ad3 | 1110 | { |
c8c99b0f BW |
1111 | u32 dw1 = MI_SEMAPHORE_MBOX | |
1112 | MI_SEMAPHORE_COMPARE | | |
1113 | MI_SEMAPHORE_REGISTER; | |
ebc348b2 BW |
1114 | u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id]; |
1115 | int ret; | |
1ec14ad3 | 1116 | |
1500f7ea BW |
1117 | /* Throughout all of the GEM code, seqno passed implies our current |
1118 | * seqno is >= the last seqno executed. However for hardware the | |
1119 | * comparison is strictly greater than. | |
1120 | */ | |
1121 | seqno -= 1; | |
1122 | ||
ebc348b2 | 1123 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
686cb5f9 | 1124 | |
c8c99b0f | 1125 | ret = intel_ring_begin(waiter, 4); |
1ec14ad3 CW |
1126 | if (ret) |
1127 | return ret; | |
1128 | ||
f72b3435 MK |
1129 | /* If seqno wrap happened, omit the wait with no-ops */ |
1130 | if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) { | |
ebc348b2 | 1131 | intel_ring_emit(waiter, dw1 | wait_mbox); |
f72b3435 MK |
1132 | intel_ring_emit(waiter, seqno); |
1133 | intel_ring_emit(waiter, 0); | |
1134 | intel_ring_emit(waiter, MI_NOOP); | |
1135 | } else { | |
1136 | intel_ring_emit(waiter, MI_NOOP); | |
1137 | intel_ring_emit(waiter, MI_NOOP); | |
1138 | intel_ring_emit(waiter, MI_NOOP); | |
1139 | intel_ring_emit(waiter, MI_NOOP); | |
1140 | } | |
c8c99b0f | 1141 | intel_ring_advance(waiter); |
1ec14ad3 CW |
1142 | |
1143 | return 0; | |
1144 | } | |
1145 | ||
c6df541c CW |
1146 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
1147 | do { \ | |
fcbc34e4 KG |
1148 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
1149 | PIPE_CONTROL_DEPTH_STALL); \ | |
c6df541c CW |
1150 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
1151 | intel_ring_emit(ring__, 0); \ | |
1152 | intel_ring_emit(ring__, 0); \ | |
1153 | } while (0) | |
1154 | ||
1155 | static int | |
a4872ba6 | 1156 | pc_render_add_request(struct intel_engine_cs *ring) |
c6df541c | 1157 | { |
18393f63 | 1158 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
c6df541c CW |
1159 | int ret; |
1160 | ||
1161 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently | |
1162 | * incoherent with writes to memory, i.e. completely fubar, | |
1163 | * so we need to use PIPE_NOTIFY instead. | |
1164 | * | |
1165 | * However, we also need to workaround the qword write | |
1166 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to | |
1167 | * memory before requesting an interrupt. | |
1168 | */ | |
1169 | ret = intel_ring_begin(ring, 32); | |
1170 | if (ret) | |
1171 | return ret; | |
1172 | ||
fcbc34e4 | 1173 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
1174 | PIPE_CONTROL_WRITE_FLUSH | |
1175 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); | |
0d1aacac | 1176 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
6259cead JH |
1177 | intel_ring_emit(ring, |
1178 | i915_gem_request_get_seqno(ring->outstanding_lazy_request)); | |
c6df541c CW |
1179 | intel_ring_emit(ring, 0); |
1180 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
18393f63 | 1181 | scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */ |
c6df541c | 1182 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 1183 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 1184 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 1185 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 1186 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 1187 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 1188 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 1189 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 1190 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
a71d8d94 | 1191 | |
fcbc34e4 | 1192 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
1193 | PIPE_CONTROL_WRITE_FLUSH | |
1194 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | | |
c6df541c | 1195 | PIPE_CONTROL_NOTIFY); |
0d1aacac | 1196 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
6259cead JH |
1197 | intel_ring_emit(ring, |
1198 | i915_gem_request_get_seqno(ring->outstanding_lazy_request)); | |
c6df541c | 1199 | intel_ring_emit(ring, 0); |
09246732 | 1200 | __intel_ring_advance(ring); |
c6df541c | 1201 | |
c6df541c CW |
1202 | return 0; |
1203 | } | |
1204 | ||
4cd53c0c | 1205 | static u32 |
a4872ba6 | 1206 | gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
4cd53c0c | 1207 | { |
4cd53c0c DV |
1208 | /* Workaround to force correct ordering between irq and seqno writes on |
1209 | * ivb (and maybe also on snb) by reading from a CS register (like | |
1210 | * ACTHD) before reading the status page. */ | |
50877445 CW |
1211 | if (!lazy_coherency) { |
1212 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
1213 | POSTING_READ(RING_ACTHD(ring->mmio_base)); | |
1214 | } | |
1215 | ||
4cd53c0c DV |
1216 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
1217 | } | |
1218 | ||
8187a2b7 | 1219 | static u32 |
a4872ba6 | 1220 | ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
8187a2b7 | 1221 | { |
1ec14ad3 CW |
1222 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
1223 | } | |
1224 | ||
b70ec5bf | 1225 | static void |
a4872ba6 | 1226 | ring_set_seqno(struct intel_engine_cs *ring, u32 seqno) |
b70ec5bf MK |
1227 | { |
1228 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); | |
1229 | } | |
1230 | ||
c6df541c | 1231 | static u32 |
a4872ba6 | 1232 | pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
c6df541c | 1233 | { |
0d1aacac | 1234 | return ring->scratch.cpu_page[0]; |
c6df541c CW |
1235 | } |
1236 | ||
b70ec5bf | 1237 | static void |
a4872ba6 | 1238 | pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno) |
b70ec5bf | 1239 | { |
0d1aacac | 1240 | ring->scratch.cpu_page[0] = seqno; |
b70ec5bf MK |
1241 | } |
1242 | ||
e48d8634 | 1243 | static bool |
a4872ba6 | 1244 | gen5_ring_get_irq(struct intel_engine_cs *ring) |
e48d8634 DV |
1245 | { |
1246 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1247 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1248 | unsigned long flags; |
e48d8634 | 1249 | |
7cd512f1 | 1250 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
e48d8634 DV |
1251 | return false; |
1252 | ||
7338aefa | 1253 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
43eaea13 | 1254 | if (ring->irq_refcount++ == 0) |
480c8033 | 1255 | gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
7338aefa | 1256 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
1257 | |
1258 | return true; | |
1259 | } | |
1260 | ||
1261 | static void | |
a4872ba6 | 1262 | gen5_ring_put_irq(struct intel_engine_cs *ring) |
e48d8634 DV |
1263 | { |
1264 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1265 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1266 | unsigned long flags; |
e48d8634 | 1267 | |
7338aefa | 1268 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
43eaea13 | 1269 | if (--ring->irq_refcount == 0) |
480c8033 | 1270 | gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
7338aefa | 1271 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
1272 | } |
1273 | ||
b13c2b96 | 1274 | static bool |
a4872ba6 | 1275 | i9xx_ring_get_irq(struct intel_engine_cs *ring) |
62fdfeaf | 1276 | { |
78501eac | 1277 | struct drm_device *dev = ring->dev; |
4640c4ff | 1278 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1279 | unsigned long flags; |
62fdfeaf | 1280 | |
7cd512f1 | 1281 | if (!intel_irqs_enabled(dev_priv)) |
b13c2b96 CW |
1282 | return false; |
1283 | ||
7338aefa | 1284 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1285 | if (ring->irq_refcount++ == 0) { |
f637fde4 DV |
1286 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
1287 | I915_WRITE(IMR, dev_priv->irq_mask); | |
1288 | POSTING_READ(IMR); | |
1289 | } | |
7338aefa | 1290 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
b13c2b96 CW |
1291 | |
1292 | return true; | |
62fdfeaf EA |
1293 | } |
1294 | ||
8187a2b7 | 1295 | static void |
a4872ba6 | 1296 | i9xx_ring_put_irq(struct intel_engine_cs *ring) |
62fdfeaf | 1297 | { |
78501eac | 1298 | struct drm_device *dev = ring->dev; |
4640c4ff | 1299 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1300 | unsigned long flags; |
62fdfeaf | 1301 | |
7338aefa | 1302 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1303 | if (--ring->irq_refcount == 0) { |
f637fde4 DV |
1304 | dev_priv->irq_mask |= ring->irq_enable_mask; |
1305 | I915_WRITE(IMR, dev_priv->irq_mask); | |
1306 | POSTING_READ(IMR); | |
1307 | } | |
7338aefa | 1308 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
62fdfeaf EA |
1309 | } |
1310 | ||
c2798b19 | 1311 | static bool |
a4872ba6 | 1312 | i8xx_ring_get_irq(struct intel_engine_cs *ring) |
c2798b19 CW |
1313 | { |
1314 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1315 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1316 | unsigned long flags; |
c2798b19 | 1317 | |
7cd512f1 | 1318 | if (!intel_irqs_enabled(dev_priv)) |
c2798b19 CW |
1319 | return false; |
1320 | ||
7338aefa | 1321 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1322 | if (ring->irq_refcount++ == 0) { |
c2798b19 CW |
1323 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
1324 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
1325 | POSTING_READ16(IMR); | |
1326 | } | |
7338aefa | 1327 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
1328 | |
1329 | return true; | |
1330 | } | |
1331 | ||
1332 | static void | |
a4872ba6 | 1333 | i8xx_ring_put_irq(struct intel_engine_cs *ring) |
c2798b19 CW |
1334 | { |
1335 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1336 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1337 | unsigned long flags; |
c2798b19 | 1338 | |
7338aefa | 1339 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1340 | if (--ring->irq_refcount == 0) { |
c2798b19 CW |
1341 | dev_priv->irq_mask |= ring->irq_enable_mask; |
1342 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
1343 | POSTING_READ16(IMR); | |
1344 | } | |
7338aefa | 1345 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
1346 | } |
1347 | ||
a4872ba6 | 1348 | void intel_ring_setup_status_page(struct intel_engine_cs *ring) |
8187a2b7 | 1349 | { |
4593010b | 1350 | struct drm_device *dev = ring->dev; |
4640c4ff | 1351 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
4593010b EA |
1352 | u32 mmio = 0; |
1353 | ||
1354 | /* The ring status page addresses are no longer next to the rest of | |
1355 | * the ring registers as of gen7. | |
1356 | */ | |
1357 | if (IS_GEN7(dev)) { | |
1358 | switch (ring->id) { | |
96154f2f | 1359 | case RCS: |
4593010b EA |
1360 | mmio = RENDER_HWS_PGA_GEN7; |
1361 | break; | |
96154f2f | 1362 | case BCS: |
4593010b EA |
1363 | mmio = BLT_HWS_PGA_GEN7; |
1364 | break; | |
77fe2ff3 ZY |
1365 | /* |
1366 | * VCS2 actually doesn't exist on Gen7. Only shut up | |
1367 | * gcc switch check warning | |
1368 | */ | |
1369 | case VCS2: | |
96154f2f | 1370 | case VCS: |
4593010b EA |
1371 | mmio = BSD_HWS_PGA_GEN7; |
1372 | break; | |
4a3dd19d | 1373 | case VECS: |
9a8a2213 BW |
1374 | mmio = VEBOX_HWS_PGA_GEN7; |
1375 | break; | |
4593010b EA |
1376 | } |
1377 | } else if (IS_GEN6(ring->dev)) { | |
1378 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); | |
1379 | } else { | |
eb0d4b75 | 1380 | /* XXX: gen8 returns to sanity */ |
4593010b EA |
1381 | mmio = RING_HWS_PGA(ring->mmio_base); |
1382 | } | |
1383 | ||
78501eac CW |
1384 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
1385 | POSTING_READ(mmio); | |
884020bf | 1386 | |
dc616b89 DL |
1387 | /* |
1388 | * Flush the TLB for this page | |
1389 | * | |
1390 | * FIXME: These two bits have disappeared on gen8, so a question | |
1391 | * arises: do we still need this and if so how should we go about | |
1392 | * invalidating the TLB? | |
1393 | */ | |
1394 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) { | |
884020bf | 1395 | u32 reg = RING_INSTPM(ring->mmio_base); |
02f6a1e7 NKK |
1396 | |
1397 | /* ring should be idle before issuing a sync flush*/ | |
1398 | WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); | |
1399 | ||
884020bf CW |
1400 | I915_WRITE(reg, |
1401 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
1402 | INSTPM_SYNC_FLUSH)); | |
1403 | if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, | |
1404 | 1000)) | |
1405 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", | |
1406 | ring->name); | |
1407 | } | |
8187a2b7 ZN |
1408 | } |
1409 | ||
b72f3acb | 1410 | static int |
a4872ba6 | 1411 | bsd_ring_flush(struct intel_engine_cs *ring, |
78501eac CW |
1412 | u32 invalidate_domains, |
1413 | u32 flush_domains) | |
d1b851fc | 1414 | { |
b72f3acb CW |
1415 | int ret; |
1416 | ||
b72f3acb CW |
1417 | ret = intel_ring_begin(ring, 2); |
1418 | if (ret) | |
1419 | return ret; | |
1420 | ||
1421 | intel_ring_emit(ring, MI_FLUSH); | |
1422 | intel_ring_emit(ring, MI_NOOP); | |
1423 | intel_ring_advance(ring); | |
1424 | return 0; | |
d1b851fc ZN |
1425 | } |
1426 | ||
3cce469c | 1427 | static int |
a4872ba6 | 1428 | i9xx_add_request(struct intel_engine_cs *ring) |
d1b851fc | 1429 | { |
3cce469c CW |
1430 | int ret; |
1431 | ||
1432 | ret = intel_ring_begin(ring, 4); | |
1433 | if (ret) | |
1434 | return ret; | |
6f392d54 | 1435 | |
3cce469c CW |
1436 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
1437 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
6259cead JH |
1438 | intel_ring_emit(ring, |
1439 | i915_gem_request_get_seqno(ring->outstanding_lazy_request)); | |
3cce469c | 1440 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
09246732 | 1441 | __intel_ring_advance(ring); |
d1b851fc | 1442 | |
3cce469c | 1443 | return 0; |
d1b851fc ZN |
1444 | } |
1445 | ||
0f46832f | 1446 | static bool |
a4872ba6 | 1447 | gen6_ring_get_irq(struct intel_engine_cs *ring) |
0f46832f CW |
1448 | { |
1449 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1450 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1451 | unsigned long flags; |
0f46832f | 1452 | |
7cd512f1 DV |
1453 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
1454 | return false; | |
0f46832f | 1455 | |
7338aefa | 1456 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1457 | if (ring->irq_refcount++ == 0) { |
040d2baa | 1458 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
cc609d5d BW |
1459 | I915_WRITE_IMR(ring, |
1460 | ~(ring->irq_enable_mask | | |
35a85ac6 | 1461 | GT_PARITY_ERROR(dev))); |
15b9f80e BW |
1462 | else |
1463 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
480c8033 | 1464 | gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
0f46832f | 1465 | } |
7338aefa | 1466 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
0f46832f CW |
1467 | |
1468 | return true; | |
1469 | } | |
1470 | ||
1471 | static void | |
a4872ba6 | 1472 | gen6_ring_put_irq(struct intel_engine_cs *ring) |
0f46832f CW |
1473 | { |
1474 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1475 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1476 | unsigned long flags; |
0f46832f | 1477 | |
7338aefa | 1478 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1479 | if (--ring->irq_refcount == 0) { |
040d2baa | 1480 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
35a85ac6 | 1481 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
15b9f80e BW |
1482 | else |
1483 | I915_WRITE_IMR(ring, ~0); | |
480c8033 | 1484 | gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
1ec14ad3 | 1485 | } |
7338aefa | 1486 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
d1b851fc ZN |
1487 | } |
1488 | ||
a19d2933 | 1489 | static bool |
a4872ba6 | 1490 | hsw_vebox_get_irq(struct intel_engine_cs *ring) |
a19d2933 BW |
1491 | { |
1492 | struct drm_device *dev = ring->dev; | |
1493 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1494 | unsigned long flags; | |
1495 | ||
7cd512f1 | 1496 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
a19d2933 BW |
1497 | return false; |
1498 | ||
59cdb63d | 1499 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1500 | if (ring->irq_refcount++ == 0) { |
a19d2933 | 1501 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
480c8033 | 1502 | gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask); |
a19d2933 | 1503 | } |
59cdb63d | 1504 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1505 | |
1506 | return true; | |
1507 | } | |
1508 | ||
1509 | static void | |
a4872ba6 | 1510 | hsw_vebox_put_irq(struct intel_engine_cs *ring) |
a19d2933 BW |
1511 | { |
1512 | struct drm_device *dev = ring->dev; | |
1513 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1514 | unsigned long flags; | |
1515 | ||
59cdb63d | 1516 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1517 | if (--ring->irq_refcount == 0) { |
a19d2933 | 1518 | I915_WRITE_IMR(ring, ~0); |
480c8033 | 1519 | gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask); |
a19d2933 | 1520 | } |
59cdb63d | 1521 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1522 | } |
1523 | ||
abd58f01 | 1524 | static bool |
a4872ba6 | 1525 | gen8_ring_get_irq(struct intel_engine_cs *ring) |
abd58f01 BW |
1526 | { |
1527 | struct drm_device *dev = ring->dev; | |
1528 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1529 | unsigned long flags; | |
1530 | ||
7cd512f1 | 1531 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
abd58f01 BW |
1532 | return false; |
1533 | ||
1534 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1535 | if (ring->irq_refcount++ == 0) { | |
1536 | if (HAS_L3_DPF(dev) && ring->id == RCS) { | |
1537 | I915_WRITE_IMR(ring, | |
1538 | ~(ring->irq_enable_mask | | |
1539 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); | |
1540 | } else { | |
1541 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
1542 | } | |
1543 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1544 | } | |
1545 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1546 | ||
1547 | return true; | |
1548 | } | |
1549 | ||
1550 | static void | |
a4872ba6 | 1551 | gen8_ring_put_irq(struct intel_engine_cs *ring) |
abd58f01 BW |
1552 | { |
1553 | struct drm_device *dev = ring->dev; | |
1554 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1555 | unsigned long flags; | |
1556 | ||
1557 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1558 | if (--ring->irq_refcount == 0) { | |
1559 | if (HAS_L3_DPF(dev) && ring->id == RCS) { | |
1560 | I915_WRITE_IMR(ring, | |
1561 | ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); | |
1562 | } else { | |
1563 | I915_WRITE_IMR(ring, ~0); | |
1564 | } | |
1565 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1566 | } | |
1567 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1568 | } | |
1569 | ||
d1b851fc | 1570 | static int |
a4872ba6 | 1571 | i965_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 1572 | u64 offset, u32 length, |
d7d4eedd | 1573 | unsigned flags) |
d1b851fc | 1574 | { |
e1f99ce6 | 1575 | int ret; |
78501eac | 1576 | |
e1f99ce6 CW |
1577 | ret = intel_ring_begin(ring, 2); |
1578 | if (ret) | |
1579 | return ret; | |
1580 | ||
78501eac | 1581 | intel_ring_emit(ring, |
65f56876 CW |
1582 | MI_BATCH_BUFFER_START | |
1583 | MI_BATCH_GTT | | |
d7d4eedd | 1584 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
c4e7a414 | 1585 | intel_ring_emit(ring, offset); |
78501eac CW |
1586 | intel_ring_advance(ring); |
1587 | ||
d1b851fc ZN |
1588 | return 0; |
1589 | } | |
1590 | ||
b45305fc DV |
1591 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1592 | #define I830_BATCH_LIMIT (256*1024) | |
c4d69da1 CW |
1593 | #define I830_TLB_ENTRIES (2) |
1594 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) | |
8187a2b7 | 1595 | static int |
a4872ba6 | 1596 | i830_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 1597 | u64 offset, u32 len, |
d7d4eedd | 1598 | unsigned flags) |
62fdfeaf | 1599 | { |
c4d69da1 | 1600 | u32 cs_offset = ring->scratch.gtt_offset; |
c4e7a414 | 1601 | int ret; |
62fdfeaf | 1602 | |
c4d69da1 CW |
1603 | ret = intel_ring_begin(ring, 6); |
1604 | if (ret) | |
1605 | return ret; | |
62fdfeaf | 1606 | |
c4d69da1 CW |
1607 | /* Evict the invalid PTE TLBs */ |
1608 | intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA); | |
1609 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096); | |
1610 | intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */ | |
1611 | intel_ring_emit(ring, cs_offset); | |
1612 | intel_ring_emit(ring, 0xdeadbeef); | |
1613 | intel_ring_emit(ring, MI_NOOP); | |
1614 | intel_ring_advance(ring); | |
b45305fc | 1615 | |
c4d69da1 | 1616 | if ((flags & I915_DISPATCH_PINNED) == 0) { |
b45305fc DV |
1617 | if (len > I830_BATCH_LIMIT) |
1618 | return -ENOSPC; | |
1619 | ||
c4d69da1 | 1620 | ret = intel_ring_begin(ring, 6 + 2); |
b45305fc DV |
1621 | if (ret) |
1622 | return ret; | |
c4d69da1 CW |
1623 | |
1624 | /* Blit the batch (which has now all relocs applied) to the | |
1625 | * stable batch scratch bo area (so that the CS never | |
1626 | * stumbles over its tlb invalidation bug) ... | |
1627 | */ | |
1628 | intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA); | |
1629 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096); | |
611a7a4f | 1630 | intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096); |
b45305fc | 1631 | intel_ring_emit(ring, cs_offset); |
b45305fc DV |
1632 | intel_ring_emit(ring, 4096); |
1633 | intel_ring_emit(ring, offset); | |
c4d69da1 | 1634 | |
b45305fc | 1635 | intel_ring_emit(ring, MI_FLUSH); |
c4d69da1 CW |
1636 | intel_ring_emit(ring, MI_NOOP); |
1637 | intel_ring_advance(ring); | |
b45305fc DV |
1638 | |
1639 | /* ... and execute it. */ | |
c4d69da1 | 1640 | offset = cs_offset; |
b45305fc | 1641 | } |
e1f99ce6 | 1642 | |
c4d69da1 CW |
1643 | ret = intel_ring_begin(ring, 4); |
1644 | if (ret) | |
1645 | return ret; | |
1646 | ||
1647 | intel_ring_emit(ring, MI_BATCH_BUFFER); | |
1648 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); | |
1649 | intel_ring_emit(ring, offset + len - 8); | |
1650 | intel_ring_emit(ring, MI_NOOP); | |
1651 | intel_ring_advance(ring); | |
1652 | ||
fb3256da DV |
1653 | return 0; |
1654 | } | |
1655 | ||
1656 | static int | |
a4872ba6 | 1657 | i915_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 1658 | u64 offset, u32 len, |
d7d4eedd | 1659 | unsigned flags) |
fb3256da DV |
1660 | { |
1661 | int ret; | |
1662 | ||
1663 | ret = intel_ring_begin(ring, 2); | |
1664 | if (ret) | |
1665 | return ret; | |
1666 | ||
65f56876 | 1667 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
d7d4eedd | 1668 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
c4e7a414 | 1669 | intel_ring_advance(ring); |
62fdfeaf | 1670 | |
62fdfeaf EA |
1671 | return 0; |
1672 | } | |
1673 | ||
a4872ba6 | 1674 | static void cleanup_status_page(struct intel_engine_cs *ring) |
62fdfeaf | 1675 | { |
05394f39 | 1676 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1677 | |
8187a2b7 ZN |
1678 | obj = ring->status_page.obj; |
1679 | if (obj == NULL) | |
62fdfeaf | 1680 | return; |
62fdfeaf | 1681 | |
9da3da66 | 1682 | kunmap(sg_page(obj->pages->sgl)); |
d7f46fc4 | 1683 | i915_gem_object_ggtt_unpin(obj); |
05394f39 | 1684 | drm_gem_object_unreference(&obj->base); |
8187a2b7 | 1685 | ring->status_page.obj = NULL; |
62fdfeaf EA |
1686 | } |
1687 | ||
a4872ba6 | 1688 | static int init_status_page(struct intel_engine_cs *ring) |
62fdfeaf | 1689 | { |
05394f39 | 1690 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1691 | |
e3efda49 | 1692 | if ((obj = ring->status_page.obj) == NULL) { |
1f767e02 | 1693 | unsigned flags; |
e3efda49 | 1694 | int ret; |
e4ffd173 | 1695 | |
e3efda49 CW |
1696 | obj = i915_gem_alloc_object(ring->dev, 4096); |
1697 | if (obj == NULL) { | |
1698 | DRM_ERROR("Failed to allocate status page\n"); | |
1699 | return -ENOMEM; | |
1700 | } | |
62fdfeaf | 1701 | |
e3efda49 CW |
1702 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
1703 | if (ret) | |
1704 | goto err_unref; | |
1705 | ||
1f767e02 CW |
1706 | flags = 0; |
1707 | if (!HAS_LLC(ring->dev)) | |
1708 | /* On g33, we cannot place HWS above 256MiB, so | |
1709 | * restrict its pinning to the low mappable arena. | |
1710 | * Though this restriction is not documented for | |
1711 | * gen4, gen5, or byt, they also behave similarly | |
1712 | * and hang if the HWS is placed at the top of the | |
1713 | * GTT. To generalise, it appears that all !llc | |
1714 | * platforms have issues with us placing the HWS | |
1715 | * above the mappable region (even though we never | |
1716 | * actualy map it). | |
1717 | */ | |
1718 | flags |= PIN_MAPPABLE; | |
1719 | ret = i915_gem_obj_ggtt_pin(obj, 4096, flags); | |
e3efda49 CW |
1720 | if (ret) { |
1721 | err_unref: | |
1722 | drm_gem_object_unreference(&obj->base); | |
1723 | return ret; | |
1724 | } | |
1725 | ||
1726 | ring->status_page.obj = obj; | |
1727 | } | |
62fdfeaf | 1728 | |
f343c5f6 | 1729 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
9da3da66 | 1730 | ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); |
8187a2b7 | 1731 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
62fdfeaf | 1732 | |
8187a2b7 ZN |
1733 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
1734 | ring->name, ring->status_page.gfx_addr); | |
62fdfeaf EA |
1735 | |
1736 | return 0; | |
62fdfeaf EA |
1737 | } |
1738 | ||
a4872ba6 | 1739 | static int init_phys_status_page(struct intel_engine_cs *ring) |
6b8294a4 CW |
1740 | { |
1741 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
6b8294a4 CW |
1742 | |
1743 | if (!dev_priv->status_page_dmah) { | |
1744 | dev_priv->status_page_dmah = | |
1745 | drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE); | |
1746 | if (!dev_priv->status_page_dmah) | |
1747 | return -ENOMEM; | |
1748 | } | |
1749 | ||
6b8294a4 CW |
1750 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1751 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
1752 | ||
1753 | return 0; | |
1754 | } | |
1755 | ||
7ba717cf | 1756 | void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
2919d291 | 1757 | { |
2919d291 | 1758 | iounmap(ringbuf->virtual_start); |
7ba717cf | 1759 | ringbuf->virtual_start = NULL; |
2919d291 | 1760 | i915_gem_object_ggtt_unpin(ringbuf->obj); |
7ba717cf TD |
1761 | } |
1762 | ||
1763 | int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev, | |
1764 | struct intel_ringbuffer *ringbuf) | |
1765 | { | |
1766 | struct drm_i915_private *dev_priv = to_i915(dev); | |
1767 | struct drm_i915_gem_object *obj = ringbuf->obj; | |
1768 | int ret; | |
1769 | ||
1770 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE); | |
1771 | if (ret) | |
1772 | return ret; | |
1773 | ||
1774 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
1775 | if (ret) { | |
1776 | i915_gem_object_ggtt_unpin(obj); | |
1777 | return ret; | |
1778 | } | |
1779 | ||
1780 | ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base + | |
1781 | i915_gem_obj_ggtt_offset(obj), ringbuf->size); | |
1782 | if (ringbuf->virtual_start == NULL) { | |
1783 | i915_gem_object_ggtt_unpin(obj); | |
1784 | return -EINVAL; | |
1785 | } | |
1786 | ||
1787 | return 0; | |
1788 | } | |
1789 | ||
1790 | void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf) | |
1791 | { | |
2919d291 OM |
1792 | drm_gem_object_unreference(&ringbuf->obj->base); |
1793 | ringbuf->obj = NULL; | |
1794 | } | |
1795 | ||
84c2377f OM |
1796 | int intel_alloc_ringbuffer_obj(struct drm_device *dev, |
1797 | struct intel_ringbuffer *ringbuf) | |
62fdfeaf | 1798 | { |
05394f39 | 1799 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1800 | |
ebc052e0 CW |
1801 | obj = NULL; |
1802 | if (!HAS_LLC(dev)) | |
93b0a4e0 | 1803 | obj = i915_gem_object_create_stolen(dev, ringbuf->size); |
ebc052e0 | 1804 | if (obj == NULL) |
93b0a4e0 | 1805 | obj = i915_gem_alloc_object(dev, ringbuf->size); |
e3efda49 CW |
1806 | if (obj == NULL) |
1807 | return -ENOMEM; | |
8187a2b7 | 1808 | |
24f3a8cf AG |
1809 | /* mark ring buffers as read-only from GPU side by default */ |
1810 | obj->gt_ro = 1; | |
1811 | ||
93b0a4e0 | 1812 | ringbuf->obj = obj; |
e3efda49 | 1813 | |
7ba717cf | 1814 | return 0; |
e3efda49 CW |
1815 | } |
1816 | ||
1817 | static int intel_init_ring_buffer(struct drm_device *dev, | |
a4872ba6 | 1818 | struct intel_engine_cs *ring) |
e3efda49 | 1819 | { |
bfc882b4 | 1820 | struct intel_ringbuffer *ringbuf; |
e3efda49 CW |
1821 | int ret; |
1822 | ||
bfc882b4 DV |
1823 | WARN_ON(ring->buffer); |
1824 | ||
1825 | ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); | |
1826 | if (!ringbuf) | |
1827 | return -ENOMEM; | |
1828 | ring->buffer = ringbuf; | |
8ee14975 | 1829 | |
e3efda49 CW |
1830 | ring->dev = dev; |
1831 | INIT_LIST_HEAD(&ring->active_list); | |
1832 | INIT_LIST_HEAD(&ring->request_list); | |
cc9130be | 1833 | INIT_LIST_HEAD(&ring->execlist_queue); |
93b0a4e0 | 1834 | ringbuf->size = 32 * PAGE_SIZE; |
0c7dd53b | 1835 | ringbuf->ring = ring; |
ebc348b2 | 1836 | memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno)); |
e3efda49 CW |
1837 | |
1838 | init_waitqueue_head(&ring->irq_queue); | |
1839 | ||
1840 | if (I915_NEED_GFX_HWS(dev)) { | |
1841 | ret = init_status_page(ring); | |
1842 | if (ret) | |
8ee14975 | 1843 | goto error; |
e3efda49 CW |
1844 | } else { |
1845 | BUG_ON(ring->id != RCS); | |
1846 | ret = init_phys_status_page(ring); | |
1847 | if (ret) | |
8ee14975 | 1848 | goto error; |
e3efda49 CW |
1849 | } |
1850 | ||
bfc882b4 | 1851 | WARN_ON(ringbuf->obj); |
7ba717cf | 1852 | |
bfc882b4 DV |
1853 | ret = intel_alloc_ringbuffer_obj(dev, ringbuf); |
1854 | if (ret) { | |
1855 | DRM_ERROR("Failed to allocate ringbuffer %s: %d\n", | |
1856 | ring->name, ret); | |
1857 | goto error; | |
1858 | } | |
1859 | ||
1860 | ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf); | |
1861 | if (ret) { | |
1862 | DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n", | |
1863 | ring->name, ret); | |
1864 | intel_destroy_ringbuffer_obj(ringbuf); | |
1865 | goto error; | |
e3efda49 | 1866 | } |
62fdfeaf | 1867 | |
55249baa CW |
1868 | /* Workaround an erratum on the i830 which causes a hang if |
1869 | * the TAIL pointer points to within the last 2 cachelines | |
1870 | * of the buffer. | |
1871 | */ | |
93b0a4e0 | 1872 | ringbuf->effective_size = ringbuf->size; |
e3efda49 | 1873 | if (IS_I830(dev) || IS_845G(dev)) |
93b0a4e0 | 1874 | ringbuf->effective_size -= 2 * CACHELINE_BYTES; |
55249baa | 1875 | |
44e895a8 BV |
1876 | ret = i915_cmd_parser_init_ring(ring); |
1877 | if (ret) | |
8ee14975 OM |
1878 | goto error; |
1879 | ||
8ee14975 | 1880 | return 0; |
351e3db2 | 1881 | |
8ee14975 OM |
1882 | error: |
1883 | kfree(ringbuf); | |
1884 | ring->buffer = NULL; | |
1885 | return ret; | |
62fdfeaf EA |
1886 | } |
1887 | ||
a4872ba6 | 1888 | void intel_cleanup_ring_buffer(struct intel_engine_cs *ring) |
62fdfeaf | 1889 | { |
6402c330 JH |
1890 | struct drm_i915_private *dev_priv; |
1891 | struct intel_ringbuffer *ringbuf; | |
33626e6a | 1892 | |
93b0a4e0 | 1893 | if (!intel_ring_initialized(ring)) |
62fdfeaf EA |
1894 | return; |
1895 | ||
6402c330 JH |
1896 | dev_priv = to_i915(ring->dev); |
1897 | ringbuf = ring->buffer; | |
1898 | ||
e3efda49 | 1899 | intel_stop_ring_buffer(ring); |
de8f0a50 | 1900 | WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0); |
33626e6a | 1901 | |
7ba717cf | 1902 | intel_unpin_ringbuffer_obj(ringbuf); |
2919d291 | 1903 | intel_destroy_ringbuffer_obj(ringbuf); |
6259cead | 1904 | i915_gem_request_assign(&ring->outstanding_lazy_request, NULL); |
78501eac | 1905 | |
8d19215b ZN |
1906 | if (ring->cleanup) |
1907 | ring->cleanup(ring); | |
1908 | ||
78501eac | 1909 | cleanup_status_page(ring); |
44e895a8 BV |
1910 | |
1911 | i915_cmd_parser_fini_ring(ring); | |
8ee14975 | 1912 | |
93b0a4e0 | 1913 | kfree(ringbuf); |
8ee14975 | 1914 | ring->buffer = NULL; |
62fdfeaf EA |
1915 | } |
1916 | ||
a4872ba6 | 1917 | static int intel_ring_wait_request(struct intel_engine_cs *ring, int n) |
a71d8d94 | 1918 | { |
93b0a4e0 | 1919 | struct intel_ringbuffer *ringbuf = ring->buffer; |
a71d8d94 | 1920 | struct drm_i915_gem_request *request; |
a71d8d94 CW |
1921 | int ret; |
1922 | ||
ebd0fd4b DG |
1923 | if (intel_ring_space(ringbuf) >= n) |
1924 | return 0; | |
a71d8d94 CW |
1925 | |
1926 | list_for_each_entry(request, &ring->request_list, list) { | |
82e104cc OM |
1927 | if (__intel_ring_space(request->tail, ringbuf->tail, |
1928 | ringbuf->size) >= n) { | |
a71d8d94 CW |
1929 | break; |
1930 | } | |
a71d8d94 CW |
1931 | } |
1932 | ||
a4b3a571 | 1933 | if (&request->list == &ring->request_list) |
a71d8d94 CW |
1934 | return -ENOSPC; |
1935 | ||
a4b3a571 | 1936 | ret = i915_wait_request(request); |
a71d8d94 CW |
1937 | if (ret) |
1938 | return ret; | |
1939 | ||
1cf0ba14 | 1940 | i915_gem_retire_requests_ring(ring); |
a71d8d94 CW |
1941 | |
1942 | return 0; | |
1943 | } | |
1944 | ||
a4872ba6 | 1945 | static int ring_wait_for_space(struct intel_engine_cs *ring, int n) |
62fdfeaf | 1946 | { |
78501eac | 1947 | struct drm_device *dev = ring->dev; |
cae5852d | 1948 | struct drm_i915_private *dev_priv = dev->dev_private; |
93b0a4e0 | 1949 | struct intel_ringbuffer *ringbuf = ring->buffer; |
78501eac | 1950 | unsigned long end; |
a71d8d94 | 1951 | int ret; |
c7dca47b | 1952 | |
a71d8d94 CW |
1953 | ret = intel_ring_wait_request(ring, n); |
1954 | if (ret != -ENOSPC) | |
1955 | return ret; | |
1956 | ||
09246732 CW |
1957 | /* force the tail write in case we have been skipping them */ |
1958 | __intel_ring_advance(ring); | |
1959 | ||
63ed2cb2 DV |
1960 | /* With GEM the hangcheck timer should kick us out of the loop, |
1961 | * leaving it early runs the risk of corrupting GEM state (due | |
1962 | * to running on almost untested codepaths). But on resume | |
1963 | * timers don't work yet, so prevent a complete hang in that | |
1964 | * case by choosing an insanely large timeout. */ | |
1965 | end = jiffies + 60 * HZ; | |
e6bfaf85 | 1966 | |
ebd0fd4b | 1967 | ret = 0; |
dcfe0506 | 1968 | trace_i915_ring_wait_begin(ring); |
8187a2b7 | 1969 | do { |
ebd0fd4b DG |
1970 | if (intel_ring_space(ringbuf) >= n) |
1971 | break; | |
93b0a4e0 | 1972 | ringbuf->head = I915_READ_HEAD(ring); |
ebd0fd4b | 1973 | if (intel_ring_space(ringbuf) >= n) |
dcfe0506 | 1974 | break; |
62fdfeaf | 1975 | |
e60a0b10 | 1976 | msleep(1); |
d6b2c790 | 1977 | |
dcfe0506 CW |
1978 | if (dev_priv->mm.interruptible && signal_pending(current)) { |
1979 | ret = -ERESTARTSYS; | |
1980 | break; | |
1981 | } | |
1982 | ||
33196ded DV |
1983 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
1984 | dev_priv->mm.interruptible); | |
d6b2c790 | 1985 | if (ret) |
dcfe0506 CW |
1986 | break; |
1987 | ||
1988 | if (time_after(jiffies, end)) { | |
1989 | ret = -EBUSY; | |
1990 | break; | |
1991 | } | |
1992 | } while (1); | |
db53a302 | 1993 | trace_i915_ring_wait_end(ring); |
dcfe0506 | 1994 | return ret; |
8187a2b7 | 1995 | } |
62fdfeaf | 1996 | |
a4872ba6 | 1997 | static int intel_wrap_ring_buffer(struct intel_engine_cs *ring) |
3e960501 CW |
1998 | { |
1999 | uint32_t __iomem *virt; | |
93b0a4e0 OM |
2000 | struct intel_ringbuffer *ringbuf = ring->buffer; |
2001 | int rem = ringbuf->size - ringbuf->tail; | |
3e960501 | 2002 | |
93b0a4e0 | 2003 | if (ringbuf->space < rem) { |
3e960501 CW |
2004 | int ret = ring_wait_for_space(ring, rem); |
2005 | if (ret) | |
2006 | return ret; | |
2007 | } | |
2008 | ||
93b0a4e0 | 2009 | virt = ringbuf->virtual_start + ringbuf->tail; |
3e960501 CW |
2010 | rem /= 4; |
2011 | while (rem--) | |
2012 | iowrite32(MI_NOOP, virt++); | |
2013 | ||
93b0a4e0 | 2014 | ringbuf->tail = 0; |
ebd0fd4b | 2015 | intel_ring_update_space(ringbuf); |
3e960501 CW |
2016 | |
2017 | return 0; | |
2018 | } | |
2019 | ||
a4872ba6 | 2020 | int intel_ring_idle(struct intel_engine_cs *ring) |
3e960501 | 2021 | { |
a4b3a571 | 2022 | struct drm_i915_gem_request *req; |
3e960501 CW |
2023 | int ret; |
2024 | ||
2025 | /* We need to add any requests required to flush the objects and ring */ | |
6259cead | 2026 | if (ring->outstanding_lazy_request) { |
9400ae5c | 2027 | ret = i915_add_request(ring); |
3e960501 CW |
2028 | if (ret) |
2029 | return ret; | |
2030 | } | |
2031 | ||
2032 | /* Wait upon the last request to be completed */ | |
2033 | if (list_empty(&ring->request_list)) | |
2034 | return 0; | |
2035 | ||
a4b3a571 | 2036 | req = list_entry(ring->request_list.prev, |
3e960501 | 2037 | struct drm_i915_gem_request, |
a4b3a571 | 2038 | list); |
3e960501 | 2039 | |
a4b3a571 | 2040 | return i915_wait_request(req); |
3e960501 CW |
2041 | } |
2042 | ||
9d773091 | 2043 | static int |
6259cead | 2044 | intel_ring_alloc_request(struct intel_engine_cs *ring) |
9d773091 | 2045 | { |
9eba5d4a JH |
2046 | int ret; |
2047 | struct drm_i915_gem_request *request; | |
67e2937b | 2048 | struct drm_i915_private *dev_private = ring->dev->dev_private; |
9eba5d4a | 2049 | |
6259cead | 2050 | if (ring->outstanding_lazy_request) |
9d773091 | 2051 | return 0; |
3c0e234c | 2052 | |
aaeb1ba0 | 2053 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
9eba5d4a JH |
2054 | if (request == NULL) |
2055 | return -ENOMEM; | |
3c0e234c | 2056 | |
abfe262a | 2057 | kref_init(&request->ref); |
ff79e857 | 2058 | request->ring = ring; |
67e2937b | 2059 | request->uniq = dev_private->request_uniq++; |
abfe262a | 2060 | |
6259cead | 2061 | ret = i915_gem_get_seqno(ring->dev, &request->seqno); |
9eba5d4a JH |
2062 | if (ret) { |
2063 | kfree(request); | |
2064 | return ret; | |
3c0e234c CW |
2065 | } |
2066 | ||
6259cead | 2067 | ring->outstanding_lazy_request = request; |
9eba5d4a | 2068 | return 0; |
9d773091 CW |
2069 | } |
2070 | ||
a4872ba6 | 2071 | static int __intel_ring_prepare(struct intel_engine_cs *ring, |
304d695c | 2072 | int bytes) |
cbcc80df | 2073 | { |
93b0a4e0 | 2074 | struct intel_ringbuffer *ringbuf = ring->buffer; |
cbcc80df MK |
2075 | int ret; |
2076 | ||
93b0a4e0 | 2077 | if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) { |
cbcc80df MK |
2078 | ret = intel_wrap_ring_buffer(ring); |
2079 | if (unlikely(ret)) | |
2080 | return ret; | |
2081 | } | |
2082 | ||
93b0a4e0 | 2083 | if (unlikely(ringbuf->space < bytes)) { |
cbcc80df MK |
2084 | ret = ring_wait_for_space(ring, bytes); |
2085 | if (unlikely(ret)) | |
2086 | return ret; | |
2087 | } | |
2088 | ||
cbcc80df MK |
2089 | return 0; |
2090 | } | |
2091 | ||
a4872ba6 | 2092 | int intel_ring_begin(struct intel_engine_cs *ring, |
e1f99ce6 | 2093 | int num_dwords) |
8187a2b7 | 2094 | { |
4640c4ff | 2095 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
e1f99ce6 | 2096 | int ret; |
78501eac | 2097 | |
33196ded DV |
2098 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
2099 | dev_priv->mm.interruptible); | |
de2b9985 DV |
2100 | if (ret) |
2101 | return ret; | |
21dd3734 | 2102 | |
304d695c CW |
2103 | ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t)); |
2104 | if (ret) | |
2105 | return ret; | |
2106 | ||
9d773091 | 2107 | /* Preallocate the olr before touching the ring */ |
6259cead | 2108 | ret = intel_ring_alloc_request(ring); |
9d773091 CW |
2109 | if (ret) |
2110 | return ret; | |
2111 | ||
ee1b1e5e | 2112 | ring->buffer->space -= num_dwords * sizeof(uint32_t); |
304d695c | 2113 | return 0; |
8187a2b7 | 2114 | } |
78501eac | 2115 | |
753b1ad4 | 2116 | /* Align the ring tail to a cacheline boundary */ |
a4872ba6 | 2117 | int intel_ring_cacheline_align(struct intel_engine_cs *ring) |
753b1ad4 | 2118 | { |
ee1b1e5e | 2119 | int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); |
753b1ad4 VS |
2120 | int ret; |
2121 | ||
2122 | if (num_dwords == 0) | |
2123 | return 0; | |
2124 | ||
18393f63 | 2125 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
753b1ad4 VS |
2126 | ret = intel_ring_begin(ring, num_dwords); |
2127 | if (ret) | |
2128 | return ret; | |
2129 | ||
2130 | while (num_dwords--) | |
2131 | intel_ring_emit(ring, MI_NOOP); | |
2132 | ||
2133 | intel_ring_advance(ring); | |
2134 | ||
2135 | return 0; | |
2136 | } | |
2137 | ||
a4872ba6 | 2138 | void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno) |
498d2ac1 | 2139 | { |
3b2cc8ab OM |
2140 | struct drm_device *dev = ring->dev; |
2141 | struct drm_i915_private *dev_priv = dev->dev_private; | |
498d2ac1 | 2142 | |
6259cead | 2143 | BUG_ON(ring->outstanding_lazy_request); |
498d2ac1 | 2144 | |
3b2cc8ab | 2145 | if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) { |
f7e98ad4 MK |
2146 | I915_WRITE(RING_SYNC_0(ring->mmio_base), 0); |
2147 | I915_WRITE(RING_SYNC_1(ring->mmio_base), 0); | |
3b2cc8ab | 2148 | if (HAS_VEBOX(dev)) |
5020150b | 2149 | I915_WRITE(RING_SYNC_2(ring->mmio_base), 0); |
e1f99ce6 | 2150 | } |
d97ed339 | 2151 | |
f7e98ad4 | 2152 | ring->set_seqno(ring, seqno); |
92cab734 | 2153 | ring->hangcheck.seqno = seqno; |
8187a2b7 | 2154 | } |
62fdfeaf | 2155 | |
a4872ba6 | 2156 | static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring, |
297b0c5b | 2157 | u32 value) |
881f47b6 | 2158 | { |
4640c4ff | 2159 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
881f47b6 XH |
2160 | |
2161 | /* Every tail move must follow the sequence below */ | |
12f55818 CW |
2162 | |
2163 | /* Disable notification that the ring is IDLE. The GT | |
2164 | * will then assume that it is busy and bring it out of rc6. | |
2165 | */ | |
0206e353 | 2166 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 CW |
2167 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
2168 | ||
2169 | /* Clear the context id. Here be magic! */ | |
2170 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); | |
0206e353 | 2171 | |
12f55818 | 2172 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
0206e353 | 2173 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
12f55818 CW |
2174 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
2175 | 50)) | |
2176 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); | |
0206e353 | 2177 | |
12f55818 | 2178 | /* Now that the ring is fully powered up, update the tail */ |
0206e353 | 2179 | I915_WRITE_TAIL(ring, value); |
12f55818 CW |
2180 | POSTING_READ(RING_TAIL(ring->mmio_base)); |
2181 | ||
2182 | /* Let the ring send IDLE messages to the GT again, | |
2183 | * and so let it sleep to conserve power when idle. | |
2184 | */ | |
0206e353 | 2185 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 | 2186 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
881f47b6 XH |
2187 | } |
2188 | ||
a4872ba6 | 2189 | static int gen6_bsd_ring_flush(struct intel_engine_cs *ring, |
ea251324 | 2190 | u32 invalidate, u32 flush) |
881f47b6 | 2191 | { |
71a77e07 | 2192 | uint32_t cmd; |
b72f3acb CW |
2193 | int ret; |
2194 | ||
b72f3acb CW |
2195 | ret = intel_ring_begin(ring, 4); |
2196 | if (ret) | |
2197 | return ret; | |
2198 | ||
71a77e07 | 2199 | cmd = MI_FLUSH_DW; |
075b3bba BW |
2200 | if (INTEL_INFO(ring->dev)->gen >= 8) |
2201 | cmd += 1; | |
9a289771 JB |
2202 | /* |
2203 | * Bspec vol 1c.5 - video engine command streamer: | |
2204 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2205 | * operation is complete. This bit is only valid when the | |
2206 | * Post-Sync Operation field is a value of 1h or 3h." | |
2207 | */ | |
71a77e07 | 2208 | if (invalidate & I915_GEM_GPU_DOMAINS) |
9a289771 JB |
2209 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | |
2210 | MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
71a77e07 | 2211 | intel_ring_emit(ring, cmd); |
9a289771 | 2212 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
075b3bba BW |
2213 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
2214 | intel_ring_emit(ring, 0); /* upper addr */ | |
2215 | intel_ring_emit(ring, 0); /* value */ | |
2216 | } else { | |
2217 | intel_ring_emit(ring, 0); | |
2218 | intel_ring_emit(ring, MI_NOOP); | |
2219 | } | |
b72f3acb CW |
2220 | intel_ring_advance(ring); |
2221 | return 0; | |
881f47b6 XH |
2222 | } |
2223 | ||
1c7a0623 | 2224 | static int |
a4872ba6 | 2225 | gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 2226 | u64 offset, u32 len, |
1c7a0623 BW |
2227 | unsigned flags) |
2228 | { | |
896ab1a5 | 2229 | bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE); |
1c7a0623 BW |
2230 | int ret; |
2231 | ||
2232 | ret = intel_ring_begin(ring, 4); | |
2233 | if (ret) | |
2234 | return ret; | |
2235 | ||
2236 | /* FIXME(BDW): Address space and security selectors. */ | |
28cf5415 | 2237 | intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); |
9bcb144c BW |
2238 | intel_ring_emit(ring, lower_32_bits(offset)); |
2239 | intel_ring_emit(ring, upper_32_bits(offset)); | |
1c7a0623 BW |
2240 | intel_ring_emit(ring, MI_NOOP); |
2241 | intel_ring_advance(ring); | |
2242 | ||
2243 | return 0; | |
2244 | } | |
2245 | ||
d7d4eedd | 2246 | static int |
a4872ba6 | 2247 | hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 2248 | u64 offset, u32 len, |
d7d4eedd CW |
2249 | unsigned flags) |
2250 | { | |
2251 | int ret; | |
2252 | ||
2253 | ret = intel_ring_begin(ring, 2); | |
2254 | if (ret) | |
2255 | return ret; | |
2256 | ||
2257 | intel_ring_emit(ring, | |
77072258 CW |
2258 | MI_BATCH_BUFFER_START | |
2259 | (flags & I915_DISPATCH_SECURE ? | |
2260 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW)); | |
d7d4eedd CW |
2261 | /* bit0-7 is the length on GEN6+ */ |
2262 | intel_ring_emit(ring, offset); | |
2263 | intel_ring_advance(ring); | |
2264 | ||
2265 | return 0; | |
2266 | } | |
2267 | ||
881f47b6 | 2268 | static int |
a4872ba6 | 2269 | gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 2270 | u64 offset, u32 len, |
d7d4eedd | 2271 | unsigned flags) |
881f47b6 | 2272 | { |
0206e353 | 2273 | int ret; |
ab6f8e32 | 2274 | |
0206e353 AJ |
2275 | ret = intel_ring_begin(ring, 2); |
2276 | if (ret) | |
2277 | return ret; | |
e1f99ce6 | 2278 | |
d7d4eedd CW |
2279 | intel_ring_emit(ring, |
2280 | MI_BATCH_BUFFER_START | | |
2281 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); | |
0206e353 AJ |
2282 | /* bit0-7 is the length on GEN6+ */ |
2283 | intel_ring_emit(ring, offset); | |
2284 | intel_ring_advance(ring); | |
ab6f8e32 | 2285 | |
0206e353 | 2286 | return 0; |
881f47b6 XH |
2287 | } |
2288 | ||
549f7365 CW |
2289 | /* Blitter support (SandyBridge+) */ |
2290 | ||
a4872ba6 | 2291 | static int gen6_ring_flush(struct intel_engine_cs *ring, |
ea251324 | 2292 | u32 invalidate, u32 flush) |
8d19215b | 2293 | { |
fd3da6c9 | 2294 | struct drm_device *dev = ring->dev; |
1d73c2a8 | 2295 | struct drm_i915_private *dev_priv = dev->dev_private; |
71a77e07 | 2296 | uint32_t cmd; |
b72f3acb CW |
2297 | int ret; |
2298 | ||
6a233c78 | 2299 | ret = intel_ring_begin(ring, 4); |
b72f3acb CW |
2300 | if (ret) |
2301 | return ret; | |
2302 | ||
71a77e07 | 2303 | cmd = MI_FLUSH_DW; |
075b3bba BW |
2304 | if (INTEL_INFO(ring->dev)->gen >= 8) |
2305 | cmd += 1; | |
9a289771 JB |
2306 | /* |
2307 | * Bspec vol 1c.3 - blitter engine command streamer: | |
2308 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2309 | * operation is complete. This bit is only valid when the | |
2310 | * Post-Sync Operation field is a value of 1h or 3h." | |
2311 | */ | |
71a77e07 | 2312 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
9a289771 | 2313 | cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | |
b3fcabb1 | 2314 | MI_FLUSH_DW_OP_STOREDW; |
71a77e07 | 2315 | intel_ring_emit(ring, cmd); |
9a289771 | 2316 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
075b3bba BW |
2317 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
2318 | intel_ring_emit(ring, 0); /* upper addr */ | |
2319 | intel_ring_emit(ring, 0); /* value */ | |
2320 | } else { | |
2321 | intel_ring_emit(ring, 0); | |
2322 | intel_ring_emit(ring, MI_NOOP); | |
2323 | } | |
b72f3acb | 2324 | intel_ring_advance(ring); |
fd3da6c9 | 2325 | |
1d73c2a8 RV |
2326 | if (!invalidate && flush) { |
2327 | if (IS_GEN7(dev)) | |
2328 | return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN); | |
2329 | else if (IS_BROADWELL(dev)) | |
2330 | dev_priv->fbc.need_sw_cache_clean = true; | |
2331 | } | |
fd3da6c9 | 2332 | |
b72f3acb | 2333 | return 0; |
8d19215b ZN |
2334 | } |
2335 | ||
5c1143bb XH |
2336 | int intel_init_render_ring_buffer(struct drm_device *dev) |
2337 | { | |
4640c4ff | 2338 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2339 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
3e78998a BW |
2340 | struct drm_i915_gem_object *obj; |
2341 | int ret; | |
5c1143bb | 2342 | |
59465b5f DV |
2343 | ring->name = "render ring"; |
2344 | ring->id = RCS; | |
2345 | ring->mmio_base = RENDER_RING_BASE; | |
2346 | ||
707d9cf9 | 2347 | if (INTEL_INFO(dev)->gen >= 8) { |
3e78998a BW |
2348 | if (i915_semaphore_is_enabled(dev)) { |
2349 | obj = i915_gem_alloc_object(dev, 4096); | |
2350 | if (obj == NULL) { | |
2351 | DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n"); | |
2352 | i915.semaphores = 0; | |
2353 | } else { | |
2354 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
2355 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK); | |
2356 | if (ret != 0) { | |
2357 | drm_gem_object_unreference(&obj->base); | |
2358 | DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n"); | |
2359 | i915.semaphores = 0; | |
2360 | } else | |
2361 | dev_priv->semaphore_obj = obj; | |
2362 | } | |
2363 | } | |
7225342a | 2364 | |
8f0e2b9d | 2365 | ring->init_context = intel_rcs_ctx_init; |
707d9cf9 BW |
2366 | ring->add_request = gen6_add_request; |
2367 | ring->flush = gen8_render_ring_flush; | |
2368 | ring->irq_get = gen8_ring_get_irq; | |
2369 | ring->irq_put = gen8_ring_put_irq; | |
2370 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; | |
2371 | ring->get_seqno = gen6_ring_get_seqno; | |
2372 | ring->set_seqno = ring_set_seqno; | |
2373 | if (i915_semaphore_is_enabled(dev)) { | |
3e78998a | 2374 | WARN_ON(!dev_priv->semaphore_obj); |
5ee426ca | 2375 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2376 | ring->semaphore.signal = gen8_rcs_signal; |
2377 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 BW |
2378 | } |
2379 | } else if (INTEL_INFO(dev)->gen >= 6) { | |
1ec14ad3 | 2380 | ring->add_request = gen6_add_request; |
4772eaeb | 2381 | ring->flush = gen7_render_ring_flush; |
6c6cf5aa | 2382 | if (INTEL_INFO(dev)->gen == 6) |
b3111509 | 2383 | ring->flush = gen6_render_ring_flush; |
707d9cf9 BW |
2384 | ring->irq_get = gen6_ring_get_irq; |
2385 | ring->irq_put = gen6_ring_put_irq; | |
cc609d5d | 2386 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
4cd53c0c | 2387 | ring->get_seqno = gen6_ring_get_seqno; |
b70ec5bf | 2388 | ring->set_seqno = ring_set_seqno; |
707d9cf9 BW |
2389 | if (i915_semaphore_is_enabled(dev)) { |
2390 | ring->semaphore.sync_to = gen6_ring_sync; | |
2391 | ring->semaphore.signal = gen6_signal; | |
2392 | /* | |
2393 | * The current semaphore is only applied on pre-gen8 | |
2394 | * platform. And there is no VCS2 ring on the pre-gen8 | |
2395 | * platform. So the semaphore between RCS and VCS2 is | |
2396 | * initialized as INVALID. Gen8 will initialize the | |
2397 | * sema between VCS2 and RCS later. | |
2398 | */ | |
2399 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2400 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV; | |
2401 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB; | |
2402 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE; | |
2403 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2404 | ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC; | |
2405 | ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC; | |
2406 | ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC; | |
2407 | ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC; | |
2408 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2409 | } | |
c6df541c CW |
2410 | } else if (IS_GEN5(dev)) { |
2411 | ring->add_request = pc_render_add_request; | |
46f0f8d1 | 2412 | ring->flush = gen4_render_ring_flush; |
c6df541c | 2413 | ring->get_seqno = pc_render_get_seqno; |
b70ec5bf | 2414 | ring->set_seqno = pc_render_set_seqno; |
e48d8634 DV |
2415 | ring->irq_get = gen5_ring_get_irq; |
2416 | ring->irq_put = gen5_ring_put_irq; | |
cc609d5d BW |
2417 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT | |
2418 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; | |
59465b5f | 2419 | } else { |
8620a3a9 | 2420 | ring->add_request = i9xx_add_request; |
46f0f8d1 CW |
2421 | if (INTEL_INFO(dev)->gen < 4) |
2422 | ring->flush = gen2_render_ring_flush; | |
2423 | else | |
2424 | ring->flush = gen4_render_ring_flush; | |
59465b5f | 2425 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 2426 | ring->set_seqno = ring_set_seqno; |
c2798b19 CW |
2427 | if (IS_GEN2(dev)) { |
2428 | ring->irq_get = i8xx_ring_get_irq; | |
2429 | ring->irq_put = i8xx_ring_put_irq; | |
2430 | } else { | |
2431 | ring->irq_get = i9xx_ring_get_irq; | |
2432 | ring->irq_put = i9xx_ring_put_irq; | |
2433 | } | |
e3670319 | 2434 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2435 | } |
59465b5f | 2436 | ring->write_tail = ring_write_tail; |
707d9cf9 | 2437 | |
d7d4eedd CW |
2438 | if (IS_HASWELL(dev)) |
2439 | ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; | |
1c7a0623 BW |
2440 | else if (IS_GEN8(dev)) |
2441 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; | |
d7d4eedd | 2442 | else if (INTEL_INFO(dev)->gen >= 6) |
fb3256da DV |
2443 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
2444 | else if (INTEL_INFO(dev)->gen >= 4) | |
2445 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
2446 | else if (IS_I830(dev) || IS_845G(dev)) | |
2447 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
2448 | else | |
2449 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
ecfe00d8 | 2450 | ring->init_hw = init_render_ring; |
59465b5f DV |
2451 | ring->cleanup = render_ring_cleanup; |
2452 | ||
b45305fc DV |
2453 | /* Workaround batchbuffer to combat CS tlb bug. */ |
2454 | if (HAS_BROKEN_CS_TLB(dev)) { | |
c4d69da1 | 2455 | obj = i915_gem_alloc_object(dev, I830_WA_SIZE); |
b45305fc DV |
2456 | if (obj == NULL) { |
2457 | DRM_ERROR("Failed to allocate batch bo\n"); | |
2458 | return -ENOMEM; | |
2459 | } | |
2460 | ||
be1fa129 | 2461 | ret = i915_gem_obj_ggtt_pin(obj, 0, 0); |
b45305fc DV |
2462 | if (ret != 0) { |
2463 | drm_gem_object_unreference(&obj->base); | |
2464 | DRM_ERROR("Failed to ping batch bo\n"); | |
2465 | return ret; | |
2466 | } | |
2467 | ||
0d1aacac CW |
2468 | ring->scratch.obj = obj; |
2469 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); | |
b45305fc DV |
2470 | } |
2471 | ||
99be1dfe DV |
2472 | ret = intel_init_ring_buffer(dev, ring); |
2473 | if (ret) | |
2474 | return ret; | |
2475 | ||
2476 | if (INTEL_INFO(dev)->gen >= 5) { | |
2477 | ret = intel_init_pipe_control(ring); | |
2478 | if (ret) | |
2479 | return ret; | |
2480 | } | |
2481 | ||
2482 | return 0; | |
5c1143bb XH |
2483 | } |
2484 | ||
2485 | int intel_init_bsd_ring_buffer(struct drm_device *dev) | |
2486 | { | |
4640c4ff | 2487 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2488 | struct intel_engine_cs *ring = &dev_priv->ring[VCS]; |
5c1143bb | 2489 | |
58fa3835 DV |
2490 | ring->name = "bsd ring"; |
2491 | ring->id = VCS; | |
2492 | ||
0fd2c201 | 2493 | ring->write_tail = ring_write_tail; |
780f18c8 | 2494 | if (INTEL_INFO(dev)->gen >= 6) { |
58fa3835 | 2495 | ring->mmio_base = GEN6_BSD_RING_BASE; |
0fd2c201 DV |
2496 | /* gen6 bsd needs a special wa for tail updates */ |
2497 | if (IS_GEN6(dev)) | |
2498 | ring->write_tail = gen6_bsd_ring_write_tail; | |
ea251324 | 2499 | ring->flush = gen6_bsd_ring_flush; |
58fa3835 DV |
2500 | ring->add_request = gen6_add_request; |
2501 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 2502 | ring->set_seqno = ring_set_seqno; |
abd58f01 BW |
2503 | if (INTEL_INFO(dev)->gen >= 8) { |
2504 | ring->irq_enable_mask = | |
2505 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
2506 | ring->irq_get = gen8_ring_get_irq; | |
2507 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 BW |
2508 | ring->dispatch_execbuffer = |
2509 | gen8_ring_dispatch_execbuffer; | |
707d9cf9 | 2510 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2511 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2512 | ring->semaphore.signal = gen8_xcs_signal; |
2513 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 | 2514 | } |
abd58f01 BW |
2515 | } else { |
2516 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; | |
2517 | ring->irq_get = gen6_ring_get_irq; | |
2518 | ring->irq_put = gen6_ring_put_irq; | |
1c7a0623 BW |
2519 | ring->dispatch_execbuffer = |
2520 | gen6_ring_dispatch_execbuffer; | |
707d9cf9 BW |
2521 | if (i915_semaphore_is_enabled(dev)) { |
2522 | ring->semaphore.sync_to = gen6_ring_sync; | |
2523 | ring->semaphore.signal = gen6_signal; | |
2524 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR; | |
2525 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2526 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB; | |
2527 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE; | |
2528 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2529 | ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC; | |
2530 | ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC; | |
2531 | ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC; | |
2532 | ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC; | |
2533 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2534 | } | |
abd58f01 | 2535 | } |
58fa3835 DV |
2536 | } else { |
2537 | ring->mmio_base = BSD_RING_BASE; | |
58fa3835 | 2538 | ring->flush = bsd_ring_flush; |
8620a3a9 | 2539 | ring->add_request = i9xx_add_request; |
58fa3835 | 2540 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 2541 | ring->set_seqno = ring_set_seqno; |
e48d8634 | 2542 | if (IS_GEN5(dev)) { |
cc609d5d | 2543 | ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
e48d8634 DV |
2544 | ring->irq_get = gen5_ring_get_irq; |
2545 | ring->irq_put = gen5_ring_put_irq; | |
2546 | } else { | |
e3670319 | 2547 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
e48d8634 DV |
2548 | ring->irq_get = i9xx_ring_get_irq; |
2549 | ring->irq_put = i9xx_ring_put_irq; | |
2550 | } | |
fb3256da | 2551 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
58fa3835 | 2552 | } |
ecfe00d8 | 2553 | ring->init_hw = init_ring_common; |
58fa3835 | 2554 | |
1ec14ad3 | 2555 | return intel_init_ring_buffer(dev, ring); |
5c1143bb | 2556 | } |
549f7365 | 2557 | |
845f74a7 ZY |
2558 | /** |
2559 | * Initialize the second BSD ring for Broadwell GT3. | |
2560 | * It is noted that this only exists on Broadwell GT3. | |
2561 | */ | |
2562 | int intel_init_bsd2_ring_buffer(struct drm_device *dev) | |
2563 | { | |
2564 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 2565 | struct intel_engine_cs *ring = &dev_priv->ring[VCS2]; |
845f74a7 ZY |
2566 | |
2567 | if ((INTEL_INFO(dev)->gen != 8)) { | |
2568 | DRM_ERROR("No dual-BSD ring on non-BDW machine\n"); | |
2569 | return -EINVAL; | |
2570 | } | |
2571 | ||
f7b64236 | 2572 | ring->name = "bsd2 ring"; |
845f74a7 ZY |
2573 | ring->id = VCS2; |
2574 | ||
2575 | ring->write_tail = ring_write_tail; | |
2576 | ring->mmio_base = GEN8_BSD2_RING_BASE; | |
2577 | ring->flush = gen6_bsd_ring_flush; | |
2578 | ring->add_request = gen6_add_request; | |
2579 | ring->get_seqno = gen6_ring_get_seqno; | |
2580 | ring->set_seqno = ring_set_seqno; | |
2581 | ring->irq_enable_mask = | |
2582 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; | |
2583 | ring->irq_get = gen8_ring_get_irq; | |
2584 | ring->irq_put = gen8_ring_put_irq; | |
2585 | ring->dispatch_execbuffer = | |
2586 | gen8_ring_dispatch_execbuffer; | |
3e78998a | 2587 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2588 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2589 | ring->semaphore.signal = gen8_xcs_signal; |
2590 | GEN8_RING_SEMAPHORE_INIT; | |
2591 | } | |
ecfe00d8 | 2592 | ring->init_hw = init_ring_common; |
845f74a7 ZY |
2593 | |
2594 | return intel_init_ring_buffer(dev, ring); | |
2595 | } | |
2596 | ||
549f7365 CW |
2597 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
2598 | { | |
4640c4ff | 2599 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2600 | struct intel_engine_cs *ring = &dev_priv->ring[BCS]; |
549f7365 | 2601 | |
3535d9dd DV |
2602 | ring->name = "blitter ring"; |
2603 | ring->id = BCS; | |
2604 | ||
2605 | ring->mmio_base = BLT_RING_BASE; | |
2606 | ring->write_tail = ring_write_tail; | |
ea251324 | 2607 | ring->flush = gen6_ring_flush; |
3535d9dd DV |
2608 | ring->add_request = gen6_add_request; |
2609 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 2610 | ring->set_seqno = ring_set_seqno; |
abd58f01 BW |
2611 | if (INTEL_INFO(dev)->gen >= 8) { |
2612 | ring->irq_enable_mask = | |
2613 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
2614 | ring->irq_get = gen8_ring_get_irq; | |
2615 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 | 2616 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
707d9cf9 | 2617 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2618 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2619 | ring->semaphore.signal = gen8_xcs_signal; |
2620 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 | 2621 | } |
abd58f01 BW |
2622 | } else { |
2623 | ring->irq_enable_mask = GT_BLT_USER_INTERRUPT; | |
2624 | ring->irq_get = gen6_ring_get_irq; | |
2625 | ring->irq_put = gen6_ring_put_irq; | |
1c7a0623 | 2626 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
707d9cf9 BW |
2627 | if (i915_semaphore_is_enabled(dev)) { |
2628 | ring->semaphore.signal = gen6_signal; | |
2629 | ring->semaphore.sync_to = gen6_ring_sync; | |
2630 | /* | |
2631 | * The current semaphore is only applied on pre-gen8 | |
2632 | * platform. And there is no VCS2 ring on the pre-gen8 | |
2633 | * platform. So the semaphore between BCS and VCS2 is | |
2634 | * initialized as INVALID. Gen8 will initialize the | |
2635 | * sema between BCS and VCS2 later. | |
2636 | */ | |
2637 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR; | |
2638 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV; | |
2639 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2640 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE; | |
2641 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2642 | ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC; | |
2643 | ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC; | |
2644 | ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC; | |
2645 | ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC; | |
2646 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2647 | } | |
abd58f01 | 2648 | } |
ecfe00d8 | 2649 | ring->init_hw = init_ring_common; |
549f7365 | 2650 | |
1ec14ad3 | 2651 | return intel_init_ring_buffer(dev, ring); |
549f7365 | 2652 | } |
a7b9761d | 2653 | |
9a8a2213 BW |
2654 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
2655 | { | |
4640c4ff | 2656 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2657 | struct intel_engine_cs *ring = &dev_priv->ring[VECS]; |
9a8a2213 BW |
2658 | |
2659 | ring->name = "video enhancement ring"; | |
2660 | ring->id = VECS; | |
2661 | ||
2662 | ring->mmio_base = VEBOX_RING_BASE; | |
2663 | ring->write_tail = ring_write_tail; | |
2664 | ring->flush = gen6_ring_flush; | |
2665 | ring->add_request = gen6_add_request; | |
2666 | ring->get_seqno = gen6_ring_get_seqno; | |
2667 | ring->set_seqno = ring_set_seqno; | |
abd58f01 BW |
2668 | |
2669 | if (INTEL_INFO(dev)->gen >= 8) { | |
2670 | ring->irq_enable_mask = | |
40c499f9 | 2671 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
abd58f01 BW |
2672 | ring->irq_get = gen8_ring_get_irq; |
2673 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 | 2674 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
707d9cf9 | 2675 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2676 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2677 | ring->semaphore.signal = gen8_xcs_signal; |
2678 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 | 2679 | } |
abd58f01 BW |
2680 | } else { |
2681 | ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; | |
2682 | ring->irq_get = hsw_vebox_get_irq; | |
2683 | ring->irq_put = hsw_vebox_put_irq; | |
1c7a0623 | 2684 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
707d9cf9 BW |
2685 | if (i915_semaphore_is_enabled(dev)) { |
2686 | ring->semaphore.sync_to = gen6_ring_sync; | |
2687 | ring->semaphore.signal = gen6_signal; | |
2688 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER; | |
2689 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV; | |
2690 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB; | |
2691 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID; | |
2692 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2693 | ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC; | |
2694 | ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC; | |
2695 | ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC; | |
2696 | ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC; | |
2697 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2698 | } | |
abd58f01 | 2699 | } |
ecfe00d8 | 2700 | ring->init_hw = init_ring_common; |
9a8a2213 BW |
2701 | |
2702 | return intel_init_ring_buffer(dev, ring); | |
2703 | } | |
2704 | ||
a7b9761d | 2705 | int |
a4872ba6 | 2706 | intel_ring_flush_all_caches(struct intel_engine_cs *ring) |
a7b9761d CW |
2707 | { |
2708 | int ret; | |
2709 | ||
2710 | if (!ring->gpu_caches_dirty) | |
2711 | return 0; | |
2712 | ||
2713 | ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
2714 | if (ret) | |
2715 | return ret; | |
2716 | ||
2717 | trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
2718 | ||
2719 | ring->gpu_caches_dirty = false; | |
2720 | return 0; | |
2721 | } | |
2722 | ||
2723 | int | |
a4872ba6 | 2724 | intel_ring_invalidate_all_caches(struct intel_engine_cs *ring) |
a7b9761d CW |
2725 | { |
2726 | uint32_t flush_domains; | |
2727 | int ret; | |
2728 | ||
2729 | flush_domains = 0; | |
2730 | if (ring->gpu_caches_dirty) | |
2731 | flush_domains = I915_GEM_GPU_DOMAINS; | |
2732 | ||
2733 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
2734 | if (ret) | |
2735 | return ret; | |
2736 | ||
2737 | trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
2738 | ||
2739 | ring->gpu_caches_dirty = false; | |
2740 | return 0; | |
2741 | } | |
e3efda49 CW |
2742 | |
2743 | void | |
a4872ba6 | 2744 | intel_stop_ring_buffer(struct intel_engine_cs *ring) |
e3efda49 CW |
2745 | { |
2746 | int ret; | |
2747 | ||
2748 | if (!intel_ring_initialized(ring)) | |
2749 | return; | |
2750 | ||
2751 | ret = intel_ring_idle(ring); | |
2752 | if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error)) | |
2753 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", | |
2754 | ring->name, ret); | |
2755 | ||
2756 | stop_ring(ring); | |
2757 | } |