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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
760285e7 | 30 | #include <drm/drmP.h> |
62fdfeaf | 31 | #include "i915_drv.h" |
760285e7 | 32 | #include <drm/i915_drm.h> |
62fdfeaf | 33 | #include "i915_trace.h" |
881f47b6 | 34 | #include "intel_drv.h" |
62fdfeaf | 35 | |
c7dca47b CW |
36 | static inline int ring_space(struct intel_ring_buffer *ring) |
37 | { | |
633cf8f5 | 38 | int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE); |
c7dca47b CW |
39 | if (space < 0) |
40 | space += ring->size; | |
41 | return space; | |
42 | } | |
43 | ||
09246732 CW |
44 | void __intel_ring_advance(struct intel_ring_buffer *ring) |
45 | { | |
46 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
47 | ||
48 | ring->tail &= ring->size - 1; | |
49 | if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring)) | |
50 | return; | |
51 | ring->write_tail(ring, ring->tail); | |
52 | } | |
53 | ||
b72f3acb | 54 | static int |
46f0f8d1 CW |
55 | gen2_render_ring_flush(struct intel_ring_buffer *ring, |
56 | u32 invalidate_domains, | |
57 | u32 flush_domains) | |
58 | { | |
59 | u32 cmd; | |
60 | int ret; | |
61 | ||
62 | cmd = MI_FLUSH; | |
31b14c9f | 63 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
46f0f8d1 CW |
64 | cmd |= MI_NO_WRITE_FLUSH; |
65 | ||
66 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
67 | cmd |= MI_READ_FLUSH; | |
68 | ||
69 | ret = intel_ring_begin(ring, 2); | |
70 | if (ret) | |
71 | return ret; | |
72 | ||
73 | intel_ring_emit(ring, cmd); | |
74 | intel_ring_emit(ring, MI_NOOP); | |
75 | intel_ring_advance(ring); | |
76 | ||
77 | return 0; | |
78 | } | |
79 | ||
80 | static int | |
81 | gen4_render_ring_flush(struct intel_ring_buffer *ring, | |
82 | u32 invalidate_domains, | |
83 | u32 flush_domains) | |
62fdfeaf | 84 | { |
78501eac | 85 | struct drm_device *dev = ring->dev; |
6f392d54 | 86 | u32 cmd; |
b72f3acb | 87 | int ret; |
6f392d54 | 88 | |
36d527de CW |
89 | /* |
90 | * read/write caches: | |
91 | * | |
92 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
93 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
94 | * also flushed at 2d versus 3d pipeline switches. | |
95 | * | |
96 | * read-only caches: | |
97 | * | |
98 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
99 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
100 | * | |
101 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
102 | * | |
103 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
104 | * invalidated when MI_EXE_FLUSH is set. | |
105 | * | |
106 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
107 | * invalidated with every MI_FLUSH. | |
108 | * | |
109 | * TLBs: | |
110 | * | |
111 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
112 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
113 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
114 | * are flushed at any MI_FLUSH. | |
115 | */ | |
116 | ||
117 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
46f0f8d1 | 118 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
36d527de | 119 | cmd &= ~MI_NO_WRITE_FLUSH; |
36d527de CW |
120 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
121 | cmd |= MI_EXE_FLUSH; | |
62fdfeaf | 122 | |
36d527de CW |
123 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
124 | (IS_G4X(dev) || IS_GEN5(dev))) | |
125 | cmd |= MI_INVALIDATE_ISP; | |
70eac33e | 126 | |
36d527de CW |
127 | ret = intel_ring_begin(ring, 2); |
128 | if (ret) | |
129 | return ret; | |
b72f3acb | 130 | |
36d527de CW |
131 | intel_ring_emit(ring, cmd); |
132 | intel_ring_emit(ring, MI_NOOP); | |
133 | intel_ring_advance(ring); | |
b72f3acb CW |
134 | |
135 | return 0; | |
8187a2b7 ZN |
136 | } |
137 | ||
8d315287 JB |
138 | /** |
139 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
140 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
141 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
142 | * | |
143 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
144 | * produced by non-pipelined state commands), software needs to first | |
145 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
146 | * 0. | |
147 | * | |
148 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
149 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
150 | * | |
151 | * And the workaround for these two requires this workaround first: | |
152 | * | |
153 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
154 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
155 | * flushes. | |
156 | * | |
157 | * And this last workaround is tricky because of the requirements on | |
158 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
159 | * volume 2 part 1: | |
160 | * | |
161 | * "1 of the following must also be set: | |
162 | * - Render Target Cache Flush Enable ([12] of DW1) | |
163 | * - Depth Cache Flush Enable ([0] of DW1) | |
164 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
165 | * - Depth Stall ([13] of DW1) | |
166 | * - Post-Sync Operation ([13] of DW1) | |
167 | * - Notify Enable ([8] of DW1)" | |
168 | * | |
169 | * The cache flushes require the workaround flush that triggered this | |
170 | * one, so we can't use it. Depth stall would trigger the same. | |
171 | * Post-sync nonzero is what triggered this second workaround, so we | |
172 | * can't use that one either. Notify enable is IRQs, which aren't | |
173 | * really our business. That leaves only stall at scoreboard. | |
174 | */ | |
175 | static int | |
176 | intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring) | |
177 | { | |
0d1aacac | 178 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
8d315287 JB |
179 | int ret; |
180 | ||
181 | ||
182 | ret = intel_ring_begin(ring, 6); | |
183 | if (ret) | |
184 | return ret; | |
185 | ||
186 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
187 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
188 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
189 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
190 | intel_ring_emit(ring, 0); /* low dword */ | |
191 | intel_ring_emit(ring, 0); /* high dword */ | |
192 | intel_ring_emit(ring, MI_NOOP); | |
193 | intel_ring_advance(ring); | |
194 | ||
195 | ret = intel_ring_begin(ring, 6); | |
196 | if (ret) | |
197 | return ret; | |
198 | ||
199 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
200 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); | |
201 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
202 | intel_ring_emit(ring, 0); | |
203 | intel_ring_emit(ring, 0); | |
204 | intel_ring_emit(ring, MI_NOOP); | |
205 | intel_ring_advance(ring); | |
206 | ||
207 | return 0; | |
208 | } | |
209 | ||
210 | static int | |
211 | gen6_render_ring_flush(struct intel_ring_buffer *ring, | |
212 | u32 invalidate_domains, u32 flush_domains) | |
213 | { | |
214 | u32 flags = 0; | |
0d1aacac | 215 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
8d315287 JB |
216 | int ret; |
217 | ||
b3111509 PZ |
218 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
219 | ret = intel_emit_post_sync_nonzero_flush(ring); | |
220 | if (ret) | |
221 | return ret; | |
222 | ||
8d315287 JB |
223 | /* Just flush everything. Experiments have shown that reducing the |
224 | * number of bits based on the write domains has little performance | |
225 | * impact. | |
226 | */ | |
7d54a904 CW |
227 | if (flush_domains) { |
228 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
229 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
230 | /* | |
231 | * Ensure that any following seqno writes only happen | |
232 | * when the render cache is indeed flushed. | |
233 | */ | |
97f209bc | 234 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 CW |
235 | } |
236 | if (invalidate_domains) { | |
237 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
238 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
239 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
240 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
241 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
242 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
243 | /* | |
244 | * TLB invalidate requires a post-sync write. | |
245 | */ | |
3ac78313 | 246 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 247 | } |
8d315287 | 248 | |
6c6cf5aa | 249 | ret = intel_ring_begin(ring, 4); |
8d315287 JB |
250 | if (ret) |
251 | return ret; | |
252 | ||
6c6cf5aa | 253 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
8d315287 JB |
254 | intel_ring_emit(ring, flags); |
255 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
6c6cf5aa | 256 | intel_ring_emit(ring, 0); |
8d315287 JB |
257 | intel_ring_advance(ring); |
258 | ||
259 | return 0; | |
260 | } | |
261 | ||
f3987631 PZ |
262 | static int |
263 | gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring) | |
264 | { | |
265 | int ret; | |
266 | ||
267 | ret = intel_ring_begin(ring, 4); | |
268 | if (ret) | |
269 | return ret; | |
270 | ||
271 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
272 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
273 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
274 | intel_ring_emit(ring, 0); | |
275 | intel_ring_emit(ring, 0); | |
276 | intel_ring_advance(ring); | |
277 | ||
278 | return 0; | |
279 | } | |
280 | ||
fd3da6c9 RV |
281 | static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value) |
282 | { | |
283 | int ret; | |
284 | ||
285 | if (!ring->fbc_dirty) | |
286 | return 0; | |
287 | ||
288 | ret = intel_ring_begin(ring, 4); | |
289 | if (ret) | |
290 | return ret; | |
291 | intel_ring_emit(ring, MI_NOOP); | |
292 | /* WaFbcNukeOn3DBlt:ivb/hsw */ | |
293 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
294 | intel_ring_emit(ring, MSG_FBC_REND_STATE); | |
295 | intel_ring_emit(ring, value); | |
296 | intel_ring_advance(ring); | |
297 | ||
298 | ring->fbc_dirty = false; | |
299 | return 0; | |
300 | } | |
301 | ||
4772eaeb PZ |
302 | static int |
303 | gen7_render_ring_flush(struct intel_ring_buffer *ring, | |
304 | u32 invalidate_domains, u32 flush_domains) | |
305 | { | |
306 | u32 flags = 0; | |
0d1aacac | 307 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
4772eaeb PZ |
308 | int ret; |
309 | ||
f3987631 PZ |
310 | /* |
311 | * Ensure that any following seqno writes only happen when the render | |
312 | * cache is indeed flushed. | |
313 | * | |
314 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
315 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
316 | * don't try to be clever and just set it unconditionally. | |
317 | */ | |
318 | flags |= PIPE_CONTROL_CS_STALL; | |
319 | ||
4772eaeb PZ |
320 | /* Just flush everything. Experiments have shown that reducing the |
321 | * number of bits based on the write domains has little performance | |
322 | * impact. | |
323 | */ | |
324 | if (flush_domains) { | |
325 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
326 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
4772eaeb PZ |
327 | } |
328 | if (invalidate_domains) { | |
329 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
330 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
331 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
332 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
333 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
334 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
335 | /* | |
336 | * TLB invalidate requires a post-sync write. | |
337 | */ | |
338 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 339 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 PZ |
340 | |
341 | /* Workaround: we must issue a pipe_control with CS-stall bit | |
342 | * set before a pipe_control command that has the state cache | |
343 | * invalidate bit set. */ | |
344 | gen7_render_ring_cs_stall_wa(ring); | |
4772eaeb PZ |
345 | } |
346 | ||
347 | ret = intel_ring_begin(ring, 4); | |
348 | if (ret) | |
349 | return ret; | |
350 | ||
351 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
352 | intel_ring_emit(ring, flags); | |
b9e1faa7 | 353 | intel_ring_emit(ring, scratch_addr); |
4772eaeb PZ |
354 | intel_ring_emit(ring, 0); |
355 | intel_ring_advance(ring); | |
356 | ||
fd3da6c9 RV |
357 | if (flush_domains) |
358 | return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); | |
359 | ||
4772eaeb PZ |
360 | return 0; |
361 | } | |
362 | ||
a5f3d68e BW |
363 | static int |
364 | gen8_render_ring_flush(struct intel_ring_buffer *ring, | |
365 | u32 invalidate_domains, u32 flush_domains) | |
366 | { | |
367 | u32 flags = 0; | |
368 | u32 scratch_addr = ring->scratch.gtt_offset + 128; | |
369 | int ret; | |
370 | ||
371 | flags |= PIPE_CONTROL_CS_STALL; | |
372 | ||
373 | if (flush_domains) { | |
374 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
375 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
376 | } | |
377 | if (invalidate_domains) { | |
378 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
379 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
380 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
381 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
382 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
383 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
384 | flags |= PIPE_CONTROL_QW_WRITE; | |
385 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
386 | } | |
387 | ||
388 | ret = intel_ring_begin(ring, 6); | |
389 | if (ret) | |
390 | return ret; | |
391 | ||
392 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); | |
393 | intel_ring_emit(ring, flags); | |
394 | intel_ring_emit(ring, scratch_addr); | |
395 | intel_ring_emit(ring, 0); | |
396 | intel_ring_emit(ring, 0); | |
397 | intel_ring_emit(ring, 0); | |
398 | intel_ring_advance(ring); | |
399 | ||
400 | return 0; | |
401 | ||
402 | } | |
403 | ||
78501eac | 404 | static void ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 405 | u32 value) |
d46eefa2 | 406 | { |
78501eac | 407 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
297b0c5b | 408 | I915_WRITE_TAIL(ring, value); |
d46eefa2 XH |
409 | } |
410 | ||
78501eac | 411 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
8187a2b7 | 412 | { |
78501eac CW |
413 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
414 | u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ? | |
3d281d8c | 415 | RING_ACTHD(ring->mmio_base) : ACTHD; |
8187a2b7 ZN |
416 | |
417 | return I915_READ(acthd_reg); | |
418 | } | |
419 | ||
035dc1e0 DV |
420 | static void ring_setup_phys_status_page(struct intel_ring_buffer *ring) |
421 | { | |
422 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
423 | u32 addr; | |
424 | ||
425 | addr = dev_priv->status_page_dmah->busaddr; | |
426 | if (INTEL_INFO(ring->dev)->gen >= 4) | |
427 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; | |
428 | I915_WRITE(HWS_PGA, addr); | |
429 | } | |
430 | ||
78501eac | 431 | static int init_ring_common(struct intel_ring_buffer *ring) |
8187a2b7 | 432 | { |
b7884eb4 DV |
433 | struct drm_device *dev = ring->dev; |
434 | drm_i915_private_t *dev_priv = dev->dev_private; | |
05394f39 | 435 | struct drm_i915_gem_object *obj = ring->obj; |
b7884eb4 | 436 | int ret = 0; |
8187a2b7 | 437 | u32 head; |
8187a2b7 | 438 | |
ab484f8f | 439 | gen6_gt_force_wake_get(dev_priv); |
b7884eb4 | 440 | |
035dc1e0 DV |
441 | if (I915_NEED_GFX_HWS(dev)) |
442 | intel_ring_setup_status_page(ring); | |
443 | else | |
444 | ring_setup_phys_status_page(ring); | |
445 | ||
8187a2b7 | 446 | /* Stop the ring if it's running. */ |
7f2ab699 | 447 | I915_WRITE_CTL(ring, 0); |
570ef608 | 448 | I915_WRITE_HEAD(ring, 0); |
78501eac | 449 | ring->write_tail(ring, 0); |
8187a2b7 | 450 | |
570ef608 | 451 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
8187a2b7 ZN |
452 | |
453 | /* G45 ring initialization fails to reset head to zero */ | |
454 | if (head != 0) { | |
6fd0d56e CW |
455 | DRM_DEBUG_KMS("%s head not reset to zero " |
456 | "ctl %08x head %08x tail %08x start %08x\n", | |
457 | ring->name, | |
458 | I915_READ_CTL(ring), | |
459 | I915_READ_HEAD(ring), | |
460 | I915_READ_TAIL(ring), | |
461 | I915_READ_START(ring)); | |
8187a2b7 | 462 | |
570ef608 | 463 | I915_WRITE_HEAD(ring, 0); |
8187a2b7 | 464 | |
6fd0d56e CW |
465 | if (I915_READ_HEAD(ring) & HEAD_ADDR) { |
466 | DRM_ERROR("failed to set %s head to zero " | |
467 | "ctl %08x head %08x tail %08x start %08x\n", | |
468 | ring->name, | |
469 | I915_READ_CTL(ring), | |
470 | I915_READ_HEAD(ring), | |
471 | I915_READ_TAIL(ring), | |
472 | I915_READ_START(ring)); | |
473 | } | |
8187a2b7 ZN |
474 | } |
475 | ||
0d8957c8 DV |
476 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
477 | * registers with the above sequence (the readback of the HEAD registers | |
478 | * also enforces ordering), otherwise the hw might lose the new ring | |
479 | * register values. */ | |
f343c5f6 | 480 | I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj)); |
7f2ab699 | 481 | I915_WRITE_CTL(ring, |
ae69b42a | 482 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 483 | | RING_VALID); |
8187a2b7 | 484 | |
8187a2b7 | 485 | /* If the head is still not zero, the ring is dead */ |
f01db988 | 486 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
f343c5f6 | 487 | I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) && |
f01db988 | 488 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { |
e74cfed5 CW |
489 | DRM_ERROR("%s initialization failed " |
490 | "ctl %08x head %08x tail %08x start %08x\n", | |
491 | ring->name, | |
492 | I915_READ_CTL(ring), | |
493 | I915_READ_HEAD(ring), | |
494 | I915_READ_TAIL(ring), | |
495 | I915_READ_START(ring)); | |
b7884eb4 DV |
496 | ret = -EIO; |
497 | goto out; | |
8187a2b7 ZN |
498 | } |
499 | ||
78501eac CW |
500 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
501 | i915_kernel_lost_context(ring->dev); | |
8187a2b7 | 502 | else { |
c7dca47b | 503 | ring->head = I915_READ_HEAD(ring); |
870e86dd | 504 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
c7dca47b | 505 | ring->space = ring_space(ring); |
c3b20037 | 506 | ring->last_retired_head = -1; |
8187a2b7 | 507 | } |
1ec14ad3 | 508 | |
50f018df CW |
509 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); |
510 | ||
b7884eb4 | 511 | out: |
ab484f8f | 512 | gen6_gt_force_wake_put(dev_priv); |
b7884eb4 DV |
513 | |
514 | return ret; | |
8187a2b7 ZN |
515 | } |
516 | ||
c6df541c CW |
517 | static int |
518 | init_pipe_control(struct intel_ring_buffer *ring) | |
519 | { | |
c6df541c CW |
520 | int ret; |
521 | ||
0d1aacac | 522 | if (ring->scratch.obj) |
c6df541c CW |
523 | return 0; |
524 | ||
0d1aacac CW |
525 | ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096); |
526 | if (ring->scratch.obj == NULL) { | |
c6df541c CW |
527 | DRM_ERROR("Failed to allocate seqno page\n"); |
528 | ret = -ENOMEM; | |
529 | goto err; | |
530 | } | |
e4ffd173 | 531 | |
0d1aacac | 532 | i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC); |
c6df541c | 533 | |
0d1aacac | 534 | ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, true, false); |
c6df541c CW |
535 | if (ret) |
536 | goto err_unref; | |
537 | ||
0d1aacac CW |
538 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj); |
539 | ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl)); | |
540 | if (ring->scratch.cpu_page == NULL) { | |
56b085a0 | 541 | ret = -ENOMEM; |
c6df541c | 542 | goto err_unpin; |
56b085a0 | 543 | } |
c6df541c | 544 | |
2b1086cc | 545 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
0d1aacac | 546 | ring->name, ring->scratch.gtt_offset); |
c6df541c CW |
547 | return 0; |
548 | ||
549 | err_unpin: | |
0d1aacac | 550 | i915_gem_object_unpin(ring->scratch.obj); |
c6df541c | 551 | err_unref: |
0d1aacac | 552 | drm_gem_object_unreference(&ring->scratch.obj->base); |
c6df541c | 553 | err: |
c6df541c CW |
554 | return ret; |
555 | } | |
556 | ||
78501eac | 557 | static int init_render_ring(struct intel_ring_buffer *ring) |
8187a2b7 | 558 | { |
78501eac | 559 | struct drm_device *dev = ring->dev; |
1ec14ad3 | 560 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 561 | int ret = init_ring_common(ring); |
a69ffdbf | 562 | |
1c8c38c5 | 563 | if (INTEL_INFO(dev)->gen > 3) |
6b26c86d | 564 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
565 | |
566 | /* We need to disable the AsyncFlip performance optimisations in order | |
567 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
568 | * programmed to '1' on all products. | |
8693a824 DL |
569 | * |
570 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv | |
1c8c38c5 CW |
571 | */ |
572 | if (INTEL_INFO(dev)->gen >= 6) | |
573 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
574 | ||
f05bb0c7 CW |
575 | /* Required for the hardware to program scanline values for waiting */ |
576 | if (INTEL_INFO(dev)->gen == 6) | |
577 | I915_WRITE(GFX_MODE, | |
578 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS)); | |
579 | ||
1c8c38c5 CW |
580 | if (IS_GEN7(dev)) |
581 | I915_WRITE(GFX_MODE_GEN7, | |
582 | _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | | |
583 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); | |
78501eac | 584 | |
8d315287 | 585 | if (INTEL_INFO(dev)->gen >= 5) { |
c6df541c CW |
586 | ret = init_pipe_control(ring); |
587 | if (ret) | |
588 | return ret; | |
589 | } | |
590 | ||
5e13a0c5 | 591 | if (IS_GEN6(dev)) { |
3a69ddd6 KG |
592 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
593 | * "If this bit is set, STCunit will have LRA as replacement | |
594 | * policy. [...] This bit must be reset. LRA replacement | |
595 | * policy is not supported." | |
596 | */ | |
597 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 598 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
12b0286f BW |
599 | |
600 | /* This is not explicitly set for GEN6, so read the register. | |
601 | * see intel_ring_mi_set_context() for why we care. | |
602 | * TODO: consider explicitly setting the bit for GEN5 | |
603 | */ | |
604 | ring->itlb_before_ctx_switch = | |
605 | !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS); | |
84f9f938 BW |
606 | } |
607 | ||
6b26c86d DV |
608 | if (INTEL_INFO(dev)->gen >= 6) |
609 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); | |
84f9f938 | 610 | |
040d2baa | 611 | if (HAS_L3_DPF(dev)) |
35a85ac6 | 612 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
15b9f80e | 613 | |
8187a2b7 ZN |
614 | return ret; |
615 | } | |
616 | ||
c6df541c CW |
617 | static void render_ring_cleanup(struct intel_ring_buffer *ring) |
618 | { | |
b45305fc DV |
619 | struct drm_device *dev = ring->dev; |
620 | ||
0d1aacac | 621 | if (ring->scratch.obj == NULL) |
c6df541c CW |
622 | return; |
623 | ||
0d1aacac CW |
624 | if (INTEL_INFO(dev)->gen >= 5) { |
625 | kunmap(sg_page(ring->scratch.obj->pages->sgl)); | |
626 | i915_gem_object_unpin(ring->scratch.obj); | |
627 | } | |
aaf8a516 | 628 | |
0d1aacac CW |
629 | drm_gem_object_unreference(&ring->scratch.obj->base); |
630 | ring->scratch.obj = NULL; | |
c6df541c CW |
631 | } |
632 | ||
1ec14ad3 | 633 | static void |
c8c99b0f | 634 | update_mboxes(struct intel_ring_buffer *ring, |
9d773091 | 635 | u32 mmio_offset) |
1ec14ad3 | 636 | { |
ad776f8b BW |
637 | /* NB: In order to be able to do semaphore MBOX updates for varying number |
638 | * of rings, it's easiest if we round up each individual update to a | |
639 | * multiple of 2 (since ring updates must always be a multiple of 2) | |
640 | * even though the actual update only requires 3 dwords. | |
641 | */ | |
642 | #define MBOX_UPDATE_DWORDS 4 | |
1c8b46fc | 643 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
c8c99b0f | 644 | intel_ring_emit(ring, mmio_offset); |
1823521d | 645 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
ad776f8b | 646 | intel_ring_emit(ring, MI_NOOP); |
1ec14ad3 CW |
647 | } |
648 | ||
c8c99b0f BW |
649 | /** |
650 | * gen6_add_request - Update the semaphore mailbox registers | |
651 | * | |
652 | * @ring - ring that is adding a request | |
653 | * @seqno - return seqno stuck into the ring | |
654 | * | |
655 | * Update the mailbox registers in the *other* rings with the current seqno. | |
656 | * This acts like a signal in the canonical semaphore. | |
657 | */ | |
1ec14ad3 | 658 | static int |
9d773091 | 659 | gen6_add_request(struct intel_ring_buffer *ring) |
1ec14ad3 | 660 | { |
ad776f8b BW |
661 | struct drm_device *dev = ring->dev; |
662 | struct drm_i915_private *dev_priv = dev->dev_private; | |
663 | struct intel_ring_buffer *useless; | |
664 | int i, ret; | |
1ec14ad3 | 665 | |
ad776f8b BW |
666 | ret = intel_ring_begin(ring, ((I915_NUM_RINGS-1) * |
667 | MBOX_UPDATE_DWORDS) + | |
668 | 4); | |
1ec14ad3 CW |
669 | if (ret) |
670 | return ret; | |
ad776f8b | 671 | #undef MBOX_UPDATE_DWORDS |
1ec14ad3 | 672 | |
ad776f8b BW |
673 | for_each_ring(useless, dev_priv, i) { |
674 | u32 mbox_reg = ring->signal_mbox[i]; | |
675 | if (mbox_reg != GEN6_NOSYNC) | |
676 | update_mboxes(ring, mbox_reg); | |
677 | } | |
1ec14ad3 CW |
678 | |
679 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); | |
680 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1823521d | 681 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
1ec14ad3 | 682 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
09246732 | 683 | __intel_ring_advance(ring); |
1ec14ad3 | 684 | |
1ec14ad3 CW |
685 | return 0; |
686 | } | |
687 | ||
f72b3435 MK |
688 | static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, |
689 | u32 seqno) | |
690 | { | |
691 | struct drm_i915_private *dev_priv = dev->dev_private; | |
692 | return dev_priv->last_seqno < seqno; | |
693 | } | |
694 | ||
c8c99b0f BW |
695 | /** |
696 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
697 | * | |
698 | * @waiter - ring that is waiting | |
699 | * @signaller - ring which has, or will signal | |
700 | * @seqno - seqno which the waiter will block on | |
701 | */ | |
702 | static int | |
686cb5f9 DV |
703 | gen6_ring_sync(struct intel_ring_buffer *waiter, |
704 | struct intel_ring_buffer *signaller, | |
705 | u32 seqno) | |
1ec14ad3 CW |
706 | { |
707 | int ret; | |
c8c99b0f BW |
708 | u32 dw1 = MI_SEMAPHORE_MBOX | |
709 | MI_SEMAPHORE_COMPARE | | |
710 | MI_SEMAPHORE_REGISTER; | |
1ec14ad3 | 711 | |
1500f7ea BW |
712 | /* Throughout all of the GEM code, seqno passed implies our current |
713 | * seqno is >= the last seqno executed. However for hardware the | |
714 | * comparison is strictly greater than. | |
715 | */ | |
716 | seqno -= 1; | |
717 | ||
686cb5f9 DV |
718 | WARN_ON(signaller->semaphore_register[waiter->id] == |
719 | MI_SEMAPHORE_SYNC_INVALID); | |
720 | ||
c8c99b0f | 721 | ret = intel_ring_begin(waiter, 4); |
1ec14ad3 CW |
722 | if (ret) |
723 | return ret; | |
724 | ||
f72b3435 MK |
725 | /* If seqno wrap happened, omit the wait with no-ops */ |
726 | if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) { | |
727 | intel_ring_emit(waiter, | |
728 | dw1 | | |
729 | signaller->semaphore_register[waiter->id]); | |
730 | intel_ring_emit(waiter, seqno); | |
731 | intel_ring_emit(waiter, 0); | |
732 | intel_ring_emit(waiter, MI_NOOP); | |
733 | } else { | |
734 | intel_ring_emit(waiter, MI_NOOP); | |
735 | intel_ring_emit(waiter, MI_NOOP); | |
736 | intel_ring_emit(waiter, MI_NOOP); | |
737 | intel_ring_emit(waiter, MI_NOOP); | |
738 | } | |
c8c99b0f | 739 | intel_ring_advance(waiter); |
1ec14ad3 CW |
740 | |
741 | return 0; | |
742 | } | |
743 | ||
c6df541c CW |
744 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
745 | do { \ | |
fcbc34e4 KG |
746 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
747 | PIPE_CONTROL_DEPTH_STALL); \ | |
c6df541c CW |
748 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
749 | intel_ring_emit(ring__, 0); \ | |
750 | intel_ring_emit(ring__, 0); \ | |
751 | } while (0) | |
752 | ||
753 | static int | |
9d773091 | 754 | pc_render_add_request(struct intel_ring_buffer *ring) |
c6df541c | 755 | { |
0d1aacac | 756 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
c6df541c CW |
757 | int ret; |
758 | ||
759 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently | |
760 | * incoherent with writes to memory, i.e. completely fubar, | |
761 | * so we need to use PIPE_NOTIFY instead. | |
762 | * | |
763 | * However, we also need to workaround the qword write | |
764 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to | |
765 | * memory before requesting an interrupt. | |
766 | */ | |
767 | ret = intel_ring_begin(ring, 32); | |
768 | if (ret) | |
769 | return ret; | |
770 | ||
fcbc34e4 | 771 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
772 | PIPE_CONTROL_WRITE_FLUSH | |
773 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); | |
0d1aacac | 774 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
1823521d | 775 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
c6df541c CW |
776 | intel_ring_emit(ring, 0); |
777 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
778 | scratch_addr += 128; /* write to separate cachelines */ | |
779 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
780 | scratch_addr += 128; | |
781 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
782 | scratch_addr += 128; | |
783 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
784 | scratch_addr += 128; | |
785 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
786 | scratch_addr += 128; | |
787 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
a71d8d94 | 788 | |
fcbc34e4 | 789 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
790 | PIPE_CONTROL_WRITE_FLUSH | |
791 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | | |
c6df541c | 792 | PIPE_CONTROL_NOTIFY); |
0d1aacac | 793 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
1823521d | 794 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
c6df541c | 795 | intel_ring_emit(ring, 0); |
09246732 | 796 | __intel_ring_advance(ring); |
c6df541c | 797 | |
c6df541c CW |
798 | return 0; |
799 | } | |
800 | ||
4cd53c0c | 801 | static u32 |
b2eadbc8 | 802 | gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
4cd53c0c | 803 | { |
4cd53c0c DV |
804 | /* Workaround to force correct ordering between irq and seqno writes on |
805 | * ivb (and maybe also on snb) by reading from a CS register (like | |
806 | * ACTHD) before reading the status page. */ | |
b2eadbc8 | 807 | if (!lazy_coherency) |
4cd53c0c DV |
808 | intel_ring_get_active_head(ring); |
809 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
810 | } | |
811 | ||
8187a2b7 | 812 | static u32 |
b2eadbc8 | 813 | ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
8187a2b7 | 814 | { |
1ec14ad3 CW |
815 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
816 | } | |
817 | ||
b70ec5bf MK |
818 | static void |
819 | ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno) | |
820 | { | |
821 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); | |
822 | } | |
823 | ||
c6df541c | 824 | static u32 |
b2eadbc8 | 825 | pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
c6df541c | 826 | { |
0d1aacac | 827 | return ring->scratch.cpu_page[0]; |
c6df541c CW |
828 | } |
829 | ||
b70ec5bf MK |
830 | static void |
831 | pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno) | |
832 | { | |
0d1aacac | 833 | ring->scratch.cpu_page[0] = seqno; |
b70ec5bf MK |
834 | } |
835 | ||
e48d8634 DV |
836 | static bool |
837 | gen5_ring_get_irq(struct intel_ring_buffer *ring) | |
838 | { | |
839 | struct drm_device *dev = ring->dev; | |
840 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 841 | unsigned long flags; |
e48d8634 DV |
842 | |
843 | if (!dev->irq_enabled) | |
844 | return false; | |
845 | ||
7338aefa | 846 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
43eaea13 PZ |
847 | if (ring->irq_refcount++ == 0) |
848 | ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask); | |
7338aefa | 849 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
850 | |
851 | return true; | |
852 | } | |
853 | ||
854 | static void | |
855 | gen5_ring_put_irq(struct intel_ring_buffer *ring) | |
856 | { | |
857 | struct drm_device *dev = ring->dev; | |
858 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 859 | unsigned long flags; |
e48d8634 | 860 | |
7338aefa | 861 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
43eaea13 PZ |
862 | if (--ring->irq_refcount == 0) |
863 | ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask); | |
7338aefa | 864 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
865 | } |
866 | ||
b13c2b96 | 867 | static bool |
e3670319 | 868 | i9xx_ring_get_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 869 | { |
78501eac | 870 | struct drm_device *dev = ring->dev; |
01a03331 | 871 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 872 | unsigned long flags; |
62fdfeaf | 873 | |
b13c2b96 CW |
874 | if (!dev->irq_enabled) |
875 | return false; | |
876 | ||
7338aefa | 877 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 878 | if (ring->irq_refcount++ == 0) { |
f637fde4 DV |
879 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
880 | I915_WRITE(IMR, dev_priv->irq_mask); | |
881 | POSTING_READ(IMR); | |
882 | } | |
7338aefa | 883 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
b13c2b96 CW |
884 | |
885 | return true; | |
62fdfeaf EA |
886 | } |
887 | ||
8187a2b7 | 888 | static void |
e3670319 | 889 | i9xx_ring_put_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 890 | { |
78501eac | 891 | struct drm_device *dev = ring->dev; |
01a03331 | 892 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 893 | unsigned long flags; |
62fdfeaf | 894 | |
7338aefa | 895 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 896 | if (--ring->irq_refcount == 0) { |
f637fde4 DV |
897 | dev_priv->irq_mask |= ring->irq_enable_mask; |
898 | I915_WRITE(IMR, dev_priv->irq_mask); | |
899 | POSTING_READ(IMR); | |
900 | } | |
7338aefa | 901 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
62fdfeaf EA |
902 | } |
903 | ||
c2798b19 CW |
904 | static bool |
905 | i8xx_ring_get_irq(struct intel_ring_buffer *ring) | |
906 | { | |
907 | struct drm_device *dev = ring->dev; | |
908 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 909 | unsigned long flags; |
c2798b19 CW |
910 | |
911 | if (!dev->irq_enabled) | |
912 | return false; | |
913 | ||
7338aefa | 914 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 915 | if (ring->irq_refcount++ == 0) { |
c2798b19 CW |
916 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
917 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
918 | POSTING_READ16(IMR); | |
919 | } | |
7338aefa | 920 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
921 | |
922 | return true; | |
923 | } | |
924 | ||
925 | static void | |
926 | i8xx_ring_put_irq(struct intel_ring_buffer *ring) | |
927 | { | |
928 | struct drm_device *dev = ring->dev; | |
929 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 930 | unsigned long flags; |
c2798b19 | 931 | |
7338aefa | 932 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 933 | if (--ring->irq_refcount == 0) { |
c2798b19 CW |
934 | dev_priv->irq_mask |= ring->irq_enable_mask; |
935 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
936 | POSTING_READ16(IMR); | |
937 | } | |
7338aefa | 938 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
939 | } |
940 | ||
78501eac | 941 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
8187a2b7 | 942 | { |
4593010b | 943 | struct drm_device *dev = ring->dev; |
78501eac | 944 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
4593010b EA |
945 | u32 mmio = 0; |
946 | ||
947 | /* The ring status page addresses are no longer next to the rest of | |
948 | * the ring registers as of gen7. | |
949 | */ | |
950 | if (IS_GEN7(dev)) { | |
951 | switch (ring->id) { | |
96154f2f | 952 | case RCS: |
4593010b EA |
953 | mmio = RENDER_HWS_PGA_GEN7; |
954 | break; | |
96154f2f | 955 | case BCS: |
4593010b EA |
956 | mmio = BLT_HWS_PGA_GEN7; |
957 | break; | |
96154f2f | 958 | case VCS: |
4593010b EA |
959 | mmio = BSD_HWS_PGA_GEN7; |
960 | break; | |
4a3dd19d | 961 | case VECS: |
9a8a2213 BW |
962 | mmio = VEBOX_HWS_PGA_GEN7; |
963 | break; | |
4593010b EA |
964 | } |
965 | } else if (IS_GEN6(ring->dev)) { | |
966 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); | |
967 | } else { | |
968 | mmio = RING_HWS_PGA(ring->mmio_base); | |
969 | } | |
970 | ||
78501eac CW |
971 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
972 | POSTING_READ(mmio); | |
884020bf CW |
973 | |
974 | /* Flush the TLB for this page */ | |
975 | if (INTEL_INFO(dev)->gen >= 6) { | |
976 | u32 reg = RING_INSTPM(ring->mmio_base); | |
977 | I915_WRITE(reg, | |
978 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
979 | INSTPM_SYNC_FLUSH)); | |
980 | if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, | |
981 | 1000)) | |
982 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", | |
983 | ring->name); | |
984 | } | |
8187a2b7 ZN |
985 | } |
986 | ||
b72f3acb | 987 | static int |
78501eac CW |
988 | bsd_ring_flush(struct intel_ring_buffer *ring, |
989 | u32 invalidate_domains, | |
990 | u32 flush_domains) | |
d1b851fc | 991 | { |
b72f3acb CW |
992 | int ret; |
993 | ||
b72f3acb CW |
994 | ret = intel_ring_begin(ring, 2); |
995 | if (ret) | |
996 | return ret; | |
997 | ||
998 | intel_ring_emit(ring, MI_FLUSH); | |
999 | intel_ring_emit(ring, MI_NOOP); | |
1000 | intel_ring_advance(ring); | |
1001 | return 0; | |
d1b851fc ZN |
1002 | } |
1003 | ||
3cce469c | 1004 | static int |
9d773091 | 1005 | i9xx_add_request(struct intel_ring_buffer *ring) |
d1b851fc | 1006 | { |
3cce469c CW |
1007 | int ret; |
1008 | ||
1009 | ret = intel_ring_begin(ring, 4); | |
1010 | if (ret) | |
1011 | return ret; | |
6f392d54 | 1012 | |
3cce469c CW |
1013 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
1014 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1823521d | 1015 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
3cce469c | 1016 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
09246732 | 1017 | __intel_ring_advance(ring); |
d1b851fc | 1018 | |
3cce469c | 1019 | return 0; |
d1b851fc ZN |
1020 | } |
1021 | ||
0f46832f | 1022 | static bool |
25c06300 | 1023 | gen6_ring_get_irq(struct intel_ring_buffer *ring) |
0f46832f CW |
1024 | { |
1025 | struct drm_device *dev = ring->dev; | |
01a03331 | 1026 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 1027 | unsigned long flags; |
0f46832f CW |
1028 | |
1029 | if (!dev->irq_enabled) | |
1030 | return false; | |
1031 | ||
4cd53c0c DV |
1032 | /* It looks like we need to prevent the gt from suspending while waiting |
1033 | * for an notifiy irq, otherwise irqs seem to get lost on at least the | |
1034 | * blt/bsd rings on ivb. */ | |
99ffa162 | 1035 | gen6_gt_force_wake_get(dev_priv); |
4cd53c0c | 1036 | |
7338aefa | 1037 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1038 | if (ring->irq_refcount++ == 0) { |
040d2baa | 1039 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
cc609d5d BW |
1040 | I915_WRITE_IMR(ring, |
1041 | ~(ring->irq_enable_mask | | |
35a85ac6 | 1042 | GT_PARITY_ERROR(dev))); |
15b9f80e BW |
1043 | else |
1044 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
43eaea13 | 1045 | ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
0f46832f | 1046 | } |
7338aefa | 1047 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
0f46832f CW |
1048 | |
1049 | return true; | |
1050 | } | |
1051 | ||
1052 | static void | |
25c06300 | 1053 | gen6_ring_put_irq(struct intel_ring_buffer *ring) |
0f46832f CW |
1054 | { |
1055 | struct drm_device *dev = ring->dev; | |
01a03331 | 1056 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 1057 | unsigned long flags; |
0f46832f | 1058 | |
7338aefa | 1059 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1060 | if (--ring->irq_refcount == 0) { |
040d2baa | 1061 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
35a85ac6 | 1062 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
15b9f80e BW |
1063 | else |
1064 | I915_WRITE_IMR(ring, ~0); | |
43eaea13 | 1065 | ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
1ec14ad3 | 1066 | } |
7338aefa | 1067 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
4cd53c0c | 1068 | |
99ffa162 | 1069 | gen6_gt_force_wake_put(dev_priv); |
d1b851fc ZN |
1070 | } |
1071 | ||
a19d2933 BW |
1072 | static bool |
1073 | hsw_vebox_get_irq(struct intel_ring_buffer *ring) | |
1074 | { | |
1075 | struct drm_device *dev = ring->dev; | |
1076 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1077 | unsigned long flags; | |
1078 | ||
1079 | if (!dev->irq_enabled) | |
1080 | return false; | |
1081 | ||
59cdb63d | 1082 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1083 | if (ring->irq_refcount++ == 0) { |
a19d2933 | 1084 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
edbfdb45 | 1085 | snb_enable_pm_irq(dev_priv, ring->irq_enable_mask); |
a19d2933 | 1086 | } |
59cdb63d | 1087 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1088 | |
1089 | return true; | |
1090 | } | |
1091 | ||
1092 | static void | |
1093 | hsw_vebox_put_irq(struct intel_ring_buffer *ring) | |
1094 | { | |
1095 | struct drm_device *dev = ring->dev; | |
1096 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1097 | unsigned long flags; | |
1098 | ||
1099 | if (!dev->irq_enabled) | |
1100 | return; | |
1101 | ||
59cdb63d | 1102 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1103 | if (--ring->irq_refcount == 0) { |
a19d2933 | 1104 | I915_WRITE_IMR(ring, ~0); |
edbfdb45 | 1105 | snb_disable_pm_irq(dev_priv, ring->irq_enable_mask); |
a19d2933 | 1106 | } |
59cdb63d | 1107 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1108 | } |
1109 | ||
abd58f01 BW |
1110 | static bool |
1111 | gen8_ring_get_irq(struct intel_ring_buffer *ring) | |
1112 | { | |
1113 | struct drm_device *dev = ring->dev; | |
1114 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1115 | unsigned long flags; | |
1116 | ||
1117 | if (!dev->irq_enabled) | |
1118 | return false; | |
1119 | ||
1120 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1121 | if (ring->irq_refcount++ == 0) { | |
1122 | if (HAS_L3_DPF(dev) && ring->id == RCS) { | |
1123 | I915_WRITE_IMR(ring, | |
1124 | ~(ring->irq_enable_mask | | |
1125 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); | |
1126 | } else { | |
1127 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
1128 | } | |
1129 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1130 | } | |
1131 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1132 | ||
1133 | return true; | |
1134 | } | |
1135 | ||
1136 | static void | |
1137 | gen8_ring_put_irq(struct intel_ring_buffer *ring) | |
1138 | { | |
1139 | struct drm_device *dev = ring->dev; | |
1140 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1141 | unsigned long flags; | |
1142 | ||
1143 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1144 | if (--ring->irq_refcount == 0) { | |
1145 | if (HAS_L3_DPF(dev) && ring->id == RCS) { | |
1146 | I915_WRITE_IMR(ring, | |
1147 | ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); | |
1148 | } else { | |
1149 | I915_WRITE_IMR(ring, ~0); | |
1150 | } | |
1151 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1152 | } | |
1153 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1154 | } | |
1155 | ||
d1b851fc | 1156 | static int |
d7d4eedd CW |
1157 | i965_dispatch_execbuffer(struct intel_ring_buffer *ring, |
1158 | u32 offset, u32 length, | |
1159 | unsigned flags) | |
d1b851fc | 1160 | { |
e1f99ce6 | 1161 | int ret; |
78501eac | 1162 | |
e1f99ce6 CW |
1163 | ret = intel_ring_begin(ring, 2); |
1164 | if (ret) | |
1165 | return ret; | |
1166 | ||
78501eac | 1167 | intel_ring_emit(ring, |
65f56876 CW |
1168 | MI_BATCH_BUFFER_START | |
1169 | MI_BATCH_GTT | | |
d7d4eedd | 1170 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
c4e7a414 | 1171 | intel_ring_emit(ring, offset); |
78501eac CW |
1172 | intel_ring_advance(ring); |
1173 | ||
d1b851fc ZN |
1174 | return 0; |
1175 | } | |
1176 | ||
b45305fc DV |
1177 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1178 | #define I830_BATCH_LIMIT (256*1024) | |
8187a2b7 | 1179 | static int |
fb3256da | 1180 | i830_dispatch_execbuffer(struct intel_ring_buffer *ring, |
d7d4eedd CW |
1181 | u32 offset, u32 len, |
1182 | unsigned flags) | |
62fdfeaf | 1183 | { |
c4e7a414 | 1184 | int ret; |
62fdfeaf | 1185 | |
b45305fc DV |
1186 | if (flags & I915_DISPATCH_PINNED) { |
1187 | ret = intel_ring_begin(ring, 4); | |
1188 | if (ret) | |
1189 | return ret; | |
62fdfeaf | 1190 | |
b45305fc DV |
1191 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
1192 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); | |
1193 | intel_ring_emit(ring, offset + len - 8); | |
1194 | intel_ring_emit(ring, MI_NOOP); | |
1195 | intel_ring_advance(ring); | |
1196 | } else { | |
0d1aacac | 1197 | u32 cs_offset = ring->scratch.gtt_offset; |
b45305fc DV |
1198 | |
1199 | if (len > I830_BATCH_LIMIT) | |
1200 | return -ENOSPC; | |
1201 | ||
1202 | ret = intel_ring_begin(ring, 9+3); | |
1203 | if (ret) | |
1204 | return ret; | |
1205 | /* Blit the batch (which has now all relocs applied) to the stable batch | |
1206 | * scratch bo area (so that the CS never stumbles over its tlb | |
1207 | * invalidation bug) ... */ | |
1208 | intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD | | |
1209 | XY_SRC_COPY_BLT_WRITE_ALPHA | | |
1210 | XY_SRC_COPY_BLT_WRITE_RGB); | |
1211 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096); | |
1212 | intel_ring_emit(ring, 0); | |
1213 | intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024); | |
1214 | intel_ring_emit(ring, cs_offset); | |
1215 | intel_ring_emit(ring, 0); | |
1216 | intel_ring_emit(ring, 4096); | |
1217 | intel_ring_emit(ring, offset); | |
1218 | intel_ring_emit(ring, MI_FLUSH); | |
1219 | ||
1220 | /* ... and execute it. */ | |
1221 | intel_ring_emit(ring, MI_BATCH_BUFFER); | |
1222 | intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); | |
1223 | intel_ring_emit(ring, cs_offset + len - 8); | |
1224 | intel_ring_advance(ring); | |
1225 | } | |
e1f99ce6 | 1226 | |
fb3256da DV |
1227 | return 0; |
1228 | } | |
1229 | ||
1230 | static int | |
1231 | i915_dispatch_execbuffer(struct intel_ring_buffer *ring, | |
d7d4eedd CW |
1232 | u32 offset, u32 len, |
1233 | unsigned flags) | |
fb3256da DV |
1234 | { |
1235 | int ret; | |
1236 | ||
1237 | ret = intel_ring_begin(ring, 2); | |
1238 | if (ret) | |
1239 | return ret; | |
1240 | ||
65f56876 | 1241 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
d7d4eedd | 1242 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
c4e7a414 | 1243 | intel_ring_advance(ring); |
62fdfeaf | 1244 | |
62fdfeaf EA |
1245 | return 0; |
1246 | } | |
1247 | ||
78501eac | 1248 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 1249 | { |
05394f39 | 1250 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1251 | |
8187a2b7 ZN |
1252 | obj = ring->status_page.obj; |
1253 | if (obj == NULL) | |
62fdfeaf | 1254 | return; |
62fdfeaf | 1255 | |
9da3da66 | 1256 | kunmap(sg_page(obj->pages->sgl)); |
62fdfeaf | 1257 | i915_gem_object_unpin(obj); |
05394f39 | 1258 | drm_gem_object_unreference(&obj->base); |
8187a2b7 | 1259 | ring->status_page.obj = NULL; |
62fdfeaf EA |
1260 | } |
1261 | ||
78501eac | 1262 | static int init_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 1263 | { |
78501eac | 1264 | struct drm_device *dev = ring->dev; |
05394f39 | 1265 | struct drm_i915_gem_object *obj; |
62fdfeaf EA |
1266 | int ret; |
1267 | ||
62fdfeaf EA |
1268 | obj = i915_gem_alloc_object(dev, 4096); |
1269 | if (obj == NULL) { | |
1270 | DRM_ERROR("Failed to allocate status page\n"); | |
1271 | ret = -ENOMEM; | |
1272 | goto err; | |
1273 | } | |
e4ffd173 CW |
1274 | |
1275 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
62fdfeaf | 1276 | |
c37e2204 | 1277 | ret = i915_gem_obj_ggtt_pin(obj, 4096, true, false); |
62fdfeaf | 1278 | if (ret != 0) { |
62fdfeaf EA |
1279 | goto err_unref; |
1280 | } | |
1281 | ||
f343c5f6 | 1282 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
9da3da66 | 1283 | ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); |
8187a2b7 | 1284 | if (ring->status_page.page_addr == NULL) { |
2e6c21ed | 1285 | ret = -ENOMEM; |
62fdfeaf EA |
1286 | goto err_unpin; |
1287 | } | |
8187a2b7 ZN |
1288 | ring->status_page.obj = obj; |
1289 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
62fdfeaf | 1290 | |
8187a2b7 ZN |
1291 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
1292 | ring->name, ring->status_page.gfx_addr); | |
62fdfeaf EA |
1293 | |
1294 | return 0; | |
1295 | ||
1296 | err_unpin: | |
1297 | i915_gem_object_unpin(obj); | |
1298 | err_unref: | |
05394f39 | 1299 | drm_gem_object_unreference(&obj->base); |
62fdfeaf | 1300 | err: |
8187a2b7 | 1301 | return ret; |
62fdfeaf EA |
1302 | } |
1303 | ||
035dc1e0 | 1304 | static int init_phys_status_page(struct intel_ring_buffer *ring) |
6b8294a4 CW |
1305 | { |
1306 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
6b8294a4 CW |
1307 | |
1308 | if (!dev_priv->status_page_dmah) { | |
1309 | dev_priv->status_page_dmah = | |
1310 | drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE); | |
1311 | if (!dev_priv->status_page_dmah) | |
1312 | return -ENOMEM; | |
1313 | } | |
1314 | ||
6b8294a4 CW |
1315 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1316 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
1317 | ||
1318 | return 0; | |
1319 | } | |
1320 | ||
c43b5634 BW |
1321 | static int intel_init_ring_buffer(struct drm_device *dev, |
1322 | struct intel_ring_buffer *ring) | |
62fdfeaf | 1323 | { |
05394f39 | 1324 | struct drm_i915_gem_object *obj; |
dd2757f8 | 1325 | struct drm_i915_private *dev_priv = dev->dev_private; |
dd785e35 CW |
1326 | int ret; |
1327 | ||
8187a2b7 | 1328 | ring->dev = dev; |
23bc5982 CW |
1329 | INIT_LIST_HEAD(&ring->active_list); |
1330 | INIT_LIST_HEAD(&ring->request_list); | |
dfc9ef2f | 1331 | ring->size = 32 * PAGE_SIZE; |
9d773091 | 1332 | memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno)); |
0dc79fb2 | 1333 | |
b259f673 | 1334 | init_waitqueue_head(&ring->irq_queue); |
62fdfeaf | 1335 | |
8187a2b7 | 1336 | if (I915_NEED_GFX_HWS(dev)) { |
78501eac | 1337 | ret = init_status_page(ring); |
8187a2b7 ZN |
1338 | if (ret) |
1339 | return ret; | |
6b8294a4 CW |
1340 | } else { |
1341 | BUG_ON(ring->id != RCS); | |
035dc1e0 | 1342 | ret = init_phys_status_page(ring); |
6b8294a4 CW |
1343 | if (ret) |
1344 | return ret; | |
8187a2b7 | 1345 | } |
62fdfeaf | 1346 | |
ebc052e0 CW |
1347 | obj = NULL; |
1348 | if (!HAS_LLC(dev)) | |
1349 | obj = i915_gem_object_create_stolen(dev, ring->size); | |
1350 | if (obj == NULL) | |
1351 | obj = i915_gem_alloc_object(dev, ring->size); | |
62fdfeaf EA |
1352 | if (obj == NULL) { |
1353 | DRM_ERROR("Failed to allocate ringbuffer\n"); | |
8187a2b7 | 1354 | ret = -ENOMEM; |
dd785e35 | 1355 | goto err_hws; |
62fdfeaf | 1356 | } |
62fdfeaf | 1357 | |
05394f39 | 1358 | ring->obj = obj; |
8187a2b7 | 1359 | |
c37e2204 | 1360 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, true, false); |
dd785e35 CW |
1361 | if (ret) |
1362 | goto err_unref; | |
62fdfeaf | 1363 | |
3eef8918 CW |
1364 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
1365 | if (ret) | |
1366 | goto err_unpin; | |
1367 | ||
dd2757f8 | 1368 | ring->virtual_start = |
f343c5f6 | 1369 | ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj), |
dd2757f8 | 1370 | ring->size); |
4225d0f2 | 1371 | if (ring->virtual_start == NULL) { |
62fdfeaf | 1372 | DRM_ERROR("Failed to map ringbuffer.\n"); |
8187a2b7 | 1373 | ret = -EINVAL; |
dd785e35 | 1374 | goto err_unpin; |
62fdfeaf EA |
1375 | } |
1376 | ||
78501eac | 1377 | ret = ring->init(ring); |
dd785e35 CW |
1378 | if (ret) |
1379 | goto err_unmap; | |
62fdfeaf | 1380 | |
55249baa CW |
1381 | /* Workaround an erratum on the i830 which causes a hang if |
1382 | * the TAIL pointer points to within the last 2 cachelines | |
1383 | * of the buffer. | |
1384 | */ | |
1385 | ring->effective_size = ring->size; | |
27c1cbd0 | 1386 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
55249baa CW |
1387 | ring->effective_size -= 128; |
1388 | ||
c584fe47 | 1389 | return 0; |
dd785e35 CW |
1390 | |
1391 | err_unmap: | |
4225d0f2 | 1392 | iounmap(ring->virtual_start); |
dd785e35 CW |
1393 | err_unpin: |
1394 | i915_gem_object_unpin(obj); | |
1395 | err_unref: | |
05394f39 CW |
1396 | drm_gem_object_unreference(&obj->base); |
1397 | ring->obj = NULL; | |
dd785e35 | 1398 | err_hws: |
78501eac | 1399 | cleanup_status_page(ring); |
8187a2b7 | 1400 | return ret; |
62fdfeaf EA |
1401 | } |
1402 | ||
78501eac | 1403 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
62fdfeaf | 1404 | { |
33626e6a CW |
1405 | struct drm_i915_private *dev_priv; |
1406 | int ret; | |
1407 | ||
05394f39 | 1408 | if (ring->obj == NULL) |
62fdfeaf EA |
1409 | return; |
1410 | ||
33626e6a CW |
1411 | /* Disable the ring buffer. The ring must be idle at this point */ |
1412 | dev_priv = ring->dev->dev_private; | |
3e960501 | 1413 | ret = intel_ring_idle(ring); |
3d57e5bd | 1414 | if (ret && !i915_reset_in_progress(&dev_priv->gpu_error)) |
29ee3991 CW |
1415 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
1416 | ring->name, ret); | |
1417 | ||
33626e6a CW |
1418 | I915_WRITE_CTL(ring, 0); |
1419 | ||
4225d0f2 | 1420 | iounmap(ring->virtual_start); |
62fdfeaf | 1421 | |
05394f39 CW |
1422 | i915_gem_object_unpin(ring->obj); |
1423 | drm_gem_object_unreference(&ring->obj->base); | |
1424 | ring->obj = NULL; | |
3d57e5bd BW |
1425 | ring->preallocated_lazy_request = NULL; |
1426 | ring->outstanding_lazy_seqno = 0; | |
78501eac | 1427 | |
8d19215b ZN |
1428 | if (ring->cleanup) |
1429 | ring->cleanup(ring); | |
1430 | ||
78501eac | 1431 | cleanup_status_page(ring); |
62fdfeaf EA |
1432 | } |
1433 | ||
a71d8d94 CW |
1434 | static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno) |
1435 | { | |
a71d8d94 CW |
1436 | int ret; |
1437 | ||
199b2bc2 | 1438 | ret = i915_wait_seqno(ring, seqno); |
b2da9fe5 BW |
1439 | if (!ret) |
1440 | i915_gem_retire_requests_ring(ring); | |
a71d8d94 CW |
1441 | |
1442 | return ret; | |
1443 | } | |
1444 | ||
1445 | static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n) | |
1446 | { | |
1447 | struct drm_i915_gem_request *request; | |
1448 | u32 seqno = 0; | |
1449 | int ret; | |
1450 | ||
1451 | i915_gem_retire_requests_ring(ring); | |
1452 | ||
1453 | if (ring->last_retired_head != -1) { | |
1454 | ring->head = ring->last_retired_head; | |
1455 | ring->last_retired_head = -1; | |
1456 | ring->space = ring_space(ring); | |
1457 | if (ring->space >= n) | |
1458 | return 0; | |
1459 | } | |
1460 | ||
1461 | list_for_each_entry(request, &ring->request_list, list) { | |
1462 | int space; | |
1463 | ||
1464 | if (request->tail == -1) | |
1465 | continue; | |
1466 | ||
633cf8f5 | 1467 | space = request->tail - (ring->tail + I915_RING_FREE_SPACE); |
a71d8d94 CW |
1468 | if (space < 0) |
1469 | space += ring->size; | |
1470 | if (space >= n) { | |
1471 | seqno = request->seqno; | |
1472 | break; | |
1473 | } | |
1474 | ||
1475 | /* Consume this request in case we need more space than | |
1476 | * is available and so need to prevent a race between | |
1477 | * updating last_retired_head and direct reads of | |
1478 | * I915_RING_HEAD. It also provides a nice sanity check. | |
1479 | */ | |
1480 | request->tail = -1; | |
1481 | } | |
1482 | ||
1483 | if (seqno == 0) | |
1484 | return -ENOSPC; | |
1485 | ||
1486 | ret = intel_ring_wait_seqno(ring, seqno); | |
1487 | if (ret) | |
1488 | return ret; | |
1489 | ||
1490 | if (WARN_ON(ring->last_retired_head == -1)) | |
1491 | return -ENOSPC; | |
1492 | ||
1493 | ring->head = ring->last_retired_head; | |
1494 | ring->last_retired_head = -1; | |
1495 | ring->space = ring_space(ring); | |
1496 | if (WARN_ON(ring->space < n)) | |
1497 | return -ENOSPC; | |
1498 | ||
1499 | return 0; | |
1500 | } | |
1501 | ||
3e960501 | 1502 | static int ring_wait_for_space(struct intel_ring_buffer *ring, int n) |
62fdfeaf | 1503 | { |
78501eac | 1504 | struct drm_device *dev = ring->dev; |
cae5852d | 1505 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 1506 | unsigned long end; |
a71d8d94 | 1507 | int ret; |
c7dca47b | 1508 | |
a71d8d94 CW |
1509 | ret = intel_ring_wait_request(ring, n); |
1510 | if (ret != -ENOSPC) | |
1511 | return ret; | |
1512 | ||
09246732 CW |
1513 | /* force the tail write in case we have been skipping them */ |
1514 | __intel_ring_advance(ring); | |
1515 | ||
db53a302 | 1516 | trace_i915_ring_wait_begin(ring); |
63ed2cb2 DV |
1517 | /* With GEM the hangcheck timer should kick us out of the loop, |
1518 | * leaving it early runs the risk of corrupting GEM state (due | |
1519 | * to running on almost untested codepaths). But on resume | |
1520 | * timers don't work yet, so prevent a complete hang in that | |
1521 | * case by choosing an insanely large timeout. */ | |
1522 | end = jiffies + 60 * HZ; | |
e6bfaf85 | 1523 | |
8187a2b7 | 1524 | do { |
c7dca47b CW |
1525 | ring->head = I915_READ_HEAD(ring); |
1526 | ring->space = ring_space(ring); | |
62fdfeaf | 1527 | if (ring->space >= n) { |
db53a302 | 1528 | trace_i915_ring_wait_end(ring); |
62fdfeaf EA |
1529 | return 0; |
1530 | } | |
1531 | ||
1532 | if (dev->primary->master) { | |
1533 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; | |
1534 | if (master_priv->sarea_priv) | |
1535 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1536 | } | |
d1b851fc | 1537 | |
e60a0b10 | 1538 | msleep(1); |
d6b2c790 | 1539 | |
33196ded DV |
1540 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
1541 | dev_priv->mm.interruptible); | |
d6b2c790 DV |
1542 | if (ret) |
1543 | return ret; | |
8187a2b7 | 1544 | } while (!time_after(jiffies, end)); |
db53a302 | 1545 | trace_i915_ring_wait_end(ring); |
8187a2b7 ZN |
1546 | return -EBUSY; |
1547 | } | |
62fdfeaf | 1548 | |
3e960501 CW |
1549 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
1550 | { | |
1551 | uint32_t __iomem *virt; | |
1552 | int rem = ring->size - ring->tail; | |
1553 | ||
1554 | if (ring->space < rem) { | |
1555 | int ret = ring_wait_for_space(ring, rem); | |
1556 | if (ret) | |
1557 | return ret; | |
1558 | } | |
1559 | ||
1560 | virt = ring->virtual_start + ring->tail; | |
1561 | rem /= 4; | |
1562 | while (rem--) | |
1563 | iowrite32(MI_NOOP, virt++); | |
1564 | ||
1565 | ring->tail = 0; | |
1566 | ring->space = ring_space(ring); | |
1567 | ||
1568 | return 0; | |
1569 | } | |
1570 | ||
1571 | int intel_ring_idle(struct intel_ring_buffer *ring) | |
1572 | { | |
1573 | u32 seqno; | |
1574 | int ret; | |
1575 | ||
1576 | /* We need to add any requests required to flush the objects and ring */ | |
1823521d | 1577 | if (ring->outstanding_lazy_seqno) { |
0025c077 | 1578 | ret = i915_add_request(ring, NULL); |
3e960501 CW |
1579 | if (ret) |
1580 | return ret; | |
1581 | } | |
1582 | ||
1583 | /* Wait upon the last request to be completed */ | |
1584 | if (list_empty(&ring->request_list)) | |
1585 | return 0; | |
1586 | ||
1587 | seqno = list_entry(ring->request_list.prev, | |
1588 | struct drm_i915_gem_request, | |
1589 | list)->seqno; | |
1590 | ||
1591 | return i915_wait_seqno(ring, seqno); | |
1592 | } | |
1593 | ||
9d773091 CW |
1594 | static int |
1595 | intel_ring_alloc_seqno(struct intel_ring_buffer *ring) | |
1596 | { | |
1823521d | 1597 | if (ring->outstanding_lazy_seqno) |
9d773091 CW |
1598 | return 0; |
1599 | ||
3c0e234c CW |
1600 | if (ring->preallocated_lazy_request == NULL) { |
1601 | struct drm_i915_gem_request *request; | |
1602 | ||
1603 | request = kmalloc(sizeof(*request), GFP_KERNEL); | |
1604 | if (request == NULL) | |
1605 | return -ENOMEM; | |
1606 | ||
1607 | ring->preallocated_lazy_request = request; | |
1608 | } | |
1609 | ||
1823521d | 1610 | return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno); |
9d773091 CW |
1611 | } |
1612 | ||
cbcc80df MK |
1613 | static int __intel_ring_begin(struct intel_ring_buffer *ring, |
1614 | int bytes) | |
1615 | { | |
1616 | int ret; | |
1617 | ||
1618 | if (unlikely(ring->tail + bytes > ring->effective_size)) { | |
1619 | ret = intel_wrap_ring_buffer(ring); | |
1620 | if (unlikely(ret)) | |
1621 | return ret; | |
1622 | } | |
1623 | ||
1624 | if (unlikely(ring->space < bytes)) { | |
1625 | ret = ring_wait_for_space(ring, bytes); | |
1626 | if (unlikely(ret)) | |
1627 | return ret; | |
1628 | } | |
1629 | ||
1630 | ring->space -= bytes; | |
1631 | return 0; | |
1632 | } | |
1633 | ||
e1f99ce6 CW |
1634 | int intel_ring_begin(struct intel_ring_buffer *ring, |
1635 | int num_dwords) | |
8187a2b7 | 1636 | { |
de2b9985 | 1637 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
e1f99ce6 | 1638 | int ret; |
78501eac | 1639 | |
33196ded DV |
1640 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
1641 | dev_priv->mm.interruptible); | |
de2b9985 DV |
1642 | if (ret) |
1643 | return ret; | |
21dd3734 | 1644 | |
9d773091 CW |
1645 | /* Preallocate the olr before touching the ring */ |
1646 | ret = intel_ring_alloc_seqno(ring); | |
1647 | if (ret) | |
1648 | return ret; | |
1649 | ||
cbcc80df | 1650 | return __intel_ring_begin(ring, num_dwords * sizeof(uint32_t)); |
8187a2b7 | 1651 | } |
78501eac | 1652 | |
f7e98ad4 | 1653 | void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno) |
498d2ac1 | 1654 | { |
f7e98ad4 | 1655 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
498d2ac1 | 1656 | |
1823521d | 1657 | BUG_ON(ring->outstanding_lazy_seqno); |
498d2ac1 | 1658 | |
f7e98ad4 MK |
1659 | if (INTEL_INFO(ring->dev)->gen >= 6) { |
1660 | I915_WRITE(RING_SYNC_0(ring->mmio_base), 0); | |
1661 | I915_WRITE(RING_SYNC_1(ring->mmio_base), 0); | |
5020150b BW |
1662 | if (HAS_VEBOX(ring->dev)) |
1663 | I915_WRITE(RING_SYNC_2(ring->mmio_base), 0); | |
e1f99ce6 | 1664 | } |
d97ed339 | 1665 | |
f7e98ad4 | 1666 | ring->set_seqno(ring, seqno); |
92cab734 | 1667 | ring->hangcheck.seqno = seqno; |
8187a2b7 | 1668 | } |
62fdfeaf | 1669 | |
78501eac | 1670 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 1671 | u32 value) |
881f47b6 | 1672 | { |
0206e353 | 1673 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
881f47b6 XH |
1674 | |
1675 | /* Every tail move must follow the sequence below */ | |
12f55818 CW |
1676 | |
1677 | /* Disable notification that the ring is IDLE. The GT | |
1678 | * will then assume that it is busy and bring it out of rc6. | |
1679 | */ | |
0206e353 | 1680 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 CW |
1681 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
1682 | ||
1683 | /* Clear the context id. Here be magic! */ | |
1684 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); | |
0206e353 | 1685 | |
12f55818 | 1686 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
0206e353 | 1687 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
12f55818 CW |
1688 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
1689 | 50)) | |
1690 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); | |
0206e353 | 1691 | |
12f55818 | 1692 | /* Now that the ring is fully powered up, update the tail */ |
0206e353 | 1693 | I915_WRITE_TAIL(ring, value); |
12f55818 CW |
1694 | POSTING_READ(RING_TAIL(ring->mmio_base)); |
1695 | ||
1696 | /* Let the ring send IDLE messages to the GT again, | |
1697 | * and so let it sleep to conserve power when idle. | |
1698 | */ | |
0206e353 | 1699 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 | 1700 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
881f47b6 XH |
1701 | } |
1702 | ||
ea251324 BW |
1703 | static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring, |
1704 | u32 invalidate, u32 flush) | |
881f47b6 | 1705 | { |
71a77e07 | 1706 | uint32_t cmd; |
b72f3acb CW |
1707 | int ret; |
1708 | ||
b72f3acb CW |
1709 | ret = intel_ring_begin(ring, 4); |
1710 | if (ret) | |
1711 | return ret; | |
1712 | ||
71a77e07 | 1713 | cmd = MI_FLUSH_DW; |
075b3bba BW |
1714 | if (INTEL_INFO(ring->dev)->gen >= 8) |
1715 | cmd += 1; | |
9a289771 JB |
1716 | /* |
1717 | * Bspec vol 1c.5 - video engine command streamer: | |
1718 | * "If ENABLED, all TLBs will be invalidated once the flush | |
1719 | * operation is complete. This bit is only valid when the | |
1720 | * Post-Sync Operation field is a value of 1h or 3h." | |
1721 | */ | |
71a77e07 | 1722 | if (invalidate & I915_GEM_GPU_DOMAINS) |
9a289771 JB |
1723 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | |
1724 | MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
71a77e07 | 1725 | intel_ring_emit(ring, cmd); |
9a289771 | 1726 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
075b3bba BW |
1727 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
1728 | intel_ring_emit(ring, 0); /* upper addr */ | |
1729 | intel_ring_emit(ring, 0); /* value */ | |
1730 | } else { | |
1731 | intel_ring_emit(ring, 0); | |
1732 | intel_ring_emit(ring, MI_NOOP); | |
1733 | } | |
b72f3acb CW |
1734 | intel_ring_advance(ring); |
1735 | return 0; | |
881f47b6 XH |
1736 | } |
1737 | ||
1c7a0623 BW |
1738 | static int |
1739 | gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, | |
1740 | u32 offset, u32 len, | |
1741 | unsigned flags) | |
1742 | { | |
28cf5415 BW |
1743 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
1744 | bool ppgtt = dev_priv->mm.aliasing_ppgtt != NULL && | |
1745 | !(flags & I915_DISPATCH_SECURE); | |
1c7a0623 BW |
1746 | int ret; |
1747 | ||
1748 | ret = intel_ring_begin(ring, 4); | |
1749 | if (ret) | |
1750 | return ret; | |
1751 | ||
1752 | /* FIXME(BDW): Address space and security selectors. */ | |
28cf5415 | 1753 | intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); |
1c7a0623 BW |
1754 | intel_ring_emit(ring, offset); |
1755 | intel_ring_emit(ring, 0); | |
1756 | intel_ring_emit(ring, MI_NOOP); | |
1757 | intel_ring_advance(ring); | |
1758 | ||
1759 | return 0; | |
1760 | } | |
1761 | ||
d7d4eedd CW |
1762 | static int |
1763 | hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, | |
1764 | u32 offset, u32 len, | |
1765 | unsigned flags) | |
1766 | { | |
1767 | int ret; | |
1768 | ||
1769 | ret = intel_ring_begin(ring, 2); | |
1770 | if (ret) | |
1771 | return ret; | |
1772 | ||
1773 | intel_ring_emit(ring, | |
1774 | MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW | | |
1775 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW)); | |
1776 | /* bit0-7 is the length on GEN6+ */ | |
1777 | intel_ring_emit(ring, offset); | |
1778 | intel_ring_advance(ring); | |
1779 | ||
1780 | return 0; | |
1781 | } | |
1782 | ||
881f47b6 | 1783 | static int |
78501eac | 1784 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
d7d4eedd CW |
1785 | u32 offset, u32 len, |
1786 | unsigned flags) | |
881f47b6 | 1787 | { |
0206e353 | 1788 | int ret; |
ab6f8e32 | 1789 | |
0206e353 AJ |
1790 | ret = intel_ring_begin(ring, 2); |
1791 | if (ret) | |
1792 | return ret; | |
e1f99ce6 | 1793 | |
d7d4eedd CW |
1794 | intel_ring_emit(ring, |
1795 | MI_BATCH_BUFFER_START | | |
1796 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); | |
0206e353 AJ |
1797 | /* bit0-7 is the length on GEN6+ */ |
1798 | intel_ring_emit(ring, offset); | |
1799 | intel_ring_advance(ring); | |
ab6f8e32 | 1800 | |
0206e353 | 1801 | return 0; |
881f47b6 XH |
1802 | } |
1803 | ||
549f7365 CW |
1804 | /* Blitter support (SandyBridge+) */ |
1805 | ||
ea251324 BW |
1806 | static int gen6_ring_flush(struct intel_ring_buffer *ring, |
1807 | u32 invalidate, u32 flush) | |
8d19215b | 1808 | { |
fd3da6c9 | 1809 | struct drm_device *dev = ring->dev; |
71a77e07 | 1810 | uint32_t cmd; |
b72f3acb CW |
1811 | int ret; |
1812 | ||
6a233c78 | 1813 | ret = intel_ring_begin(ring, 4); |
b72f3acb CW |
1814 | if (ret) |
1815 | return ret; | |
1816 | ||
71a77e07 | 1817 | cmd = MI_FLUSH_DW; |
075b3bba BW |
1818 | if (INTEL_INFO(ring->dev)->gen >= 8) |
1819 | cmd += 1; | |
9a289771 JB |
1820 | /* |
1821 | * Bspec vol 1c.3 - blitter engine command streamer: | |
1822 | * "If ENABLED, all TLBs will be invalidated once the flush | |
1823 | * operation is complete. This bit is only valid when the | |
1824 | * Post-Sync Operation field is a value of 1h or 3h." | |
1825 | */ | |
71a77e07 | 1826 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
9a289771 | 1827 | cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | |
b3fcabb1 | 1828 | MI_FLUSH_DW_OP_STOREDW; |
71a77e07 | 1829 | intel_ring_emit(ring, cmd); |
9a289771 | 1830 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
075b3bba BW |
1831 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
1832 | intel_ring_emit(ring, 0); /* upper addr */ | |
1833 | intel_ring_emit(ring, 0); /* value */ | |
1834 | } else { | |
1835 | intel_ring_emit(ring, 0); | |
1836 | intel_ring_emit(ring, MI_NOOP); | |
1837 | } | |
b72f3acb | 1838 | intel_ring_advance(ring); |
fd3da6c9 RV |
1839 | |
1840 | if (IS_GEN7(dev) && flush) | |
1841 | return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN); | |
1842 | ||
b72f3acb | 1843 | return 0; |
8d19215b ZN |
1844 | } |
1845 | ||
5c1143bb XH |
1846 | int intel_init_render_ring_buffer(struct drm_device *dev) |
1847 | { | |
1848 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1849 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
5c1143bb | 1850 | |
59465b5f DV |
1851 | ring->name = "render ring"; |
1852 | ring->id = RCS; | |
1853 | ring->mmio_base = RENDER_RING_BASE; | |
1854 | ||
1ec14ad3 CW |
1855 | if (INTEL_INFO(dev)->gen >= 6) { |
1856 | ring->add_request = gen6_add_request; | |
4772eaeb | 1857 | ring->flush = gen7_render_ring_flush; |
6c6cf5aa | 1858 | if (INTEL_INFO(dev)->gen == 6) |
b3111509 | 1859 | ring->flush = gen6_render_ring_flush; |
abd58f01 | 1860 | if (INTEL_INFO(dev)->gen >= 8) { |
a5f3d68e | 1861 | ring->flush = gen8_render_ring_flush; |
abd58f01 BW |
1862 | ring->irq_get = gen8_ring_get_irq; |
1863 | ring->irq_put = gen8_ring_put_irq; | |
1864 | } else { | |
1865 | ring->irq_get = gen6_ring_get_irq; | |
1866 | ring->irq_put = gen6_ring_put_irq; | |
1867 | } | |
cc609d5d | 1868 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
4cd53c0c | 1869 | ring->get_seqno = gen6_ring_get_seqno; |
b70ec5bf | 1870 | ring->set_seqno = ring_set_seqno; |
686cb5f9 | 1871 | ring->sync_to = gen6_ring_sync; |
5586181f BW |
1872 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID; |
1873 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV; | |
1874 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB; | |
1950de14 | 1875 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE; |
ad776f8b BW |
1876 | ring->signal_mbox[RCS] = GEN6_NOSYNC; |
1877 | ring->signal_mbox[VCS] = GEN6_VRSYNC; | |
1878 | ring->signal_mbox[BCS] = GEN6_BRSYNC; | |
1950de14 | 1879 | ring->signal_mbox[VECS] = GEN6_VERSYNC; |
c6df541c CW |
1880 | } else if (IS_GEN5(dev)) { |
1881 | ring->add_request = pc_render_add_request; | |
46f0f8d1 | 1882 | ring->flush = gen4_render_ring_flush; |
c6df541c | 1883 | ring->get_seqno = pc_render_get_seqno; |
b70ec5bf | 1884 | ring->set_seqno = pc_render_set_seqno; |
e48d8634 DV |
1885 | ring->irq_get = gen5_ring_get_irq; |
1886 | ring->irq_put = gen5_ring_put_irq; | |
cc609d5d BW |
1887 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT | |
1888 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; | |
59465b5f | 1889 | } else { |
8620a3a9 | 1890 | ring->add_request = i9xx_add_request; |
46f0f8d1 CW |
1891 | if (INTEL_INFO(dev)->gen < 4) |
1892 | ring->flush = gen2_render_ring_flush; | |
1893 | else | |
1894 | ring->flush = gen4_render_ring_flush; | |
59465b5f | 1895 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 1896 | ring->set_seqno = ring_set_seqno; |
c2798b19 CW |
1897 | if (IS_GEN2(dev)) { |
1898 | ring->irq_get = i8xx_ring_get_irq; | |
1899 | ring->irq_put = i8xx_ring_put_irq; | |
1900 | } else { | |
1901 | ring->irq_get = i9xx_ring_get_irq; | |
1902 | ring->irq_put = i9xx_ring_put_irq; | |
1903 | } | |
e3670319 | 1904 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 1905 | } |
59465b5f | 1906 | ring->write_tail = ring_write_tail; |
d7d4eedd CW |
1907 | if (IS_HASWELL(dev)) |
1908 | ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; | |
1c7a0623 BW |
1909 | else if (IS_GEN8(dev)) |
1910 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; | |
d7d4eedd | 1911 | else if (INTEL_INFO(dev)->gen >= 6) |
fb3256da DV |
1912 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
1913 | else if (INTEL_INFO(dev)->gen >= 4) | |
1914 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
1915 | else if (IS_I830(dev) || IS_845G(dev)) | |
1916 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
1917 | else | |
1918 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
1919 | ring->init = init_render_ring; |
1920 | ring->cleanup = render_ring_cleanup; | |
1921 | ||
b45305fc DV |
1922 | /* Workaround batchbuffer to combat CS tlb bug. */ |
1923 | if (HAS_BROKEN_CS_TLB(dev)) { | |
1924 | struct drm_i915_gem_object *obj; | |
1925 | int ret; | |
1926 | ||
1927 | obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT); | |
1928 | if (obj == NULL) { | |
1929 | DRM_ERROR("Failed to allocate batch bo\n"); | |
1930 | return -ENOMEM; | |
1931 | } | |
1932 | ||
c37e2204 | 1933 | ret = i915_gem_obj_ggtt_pin(obj, 0, true, false); |
b45305fc DV |
1934 | if (ret != 0) { |
1935 | drm_gem_object_unreference(&obj->base); | |
1936 | DRM_ERROR("Failed to ping batch bo\n"); | |
1937 | return ret; | |
1938 | } | |
1939 | ||
0d1aacac CW |
1940 | ring->scratch.obj = obj; |
1941 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); | |
b45305fc DV |
1942 | } |
1943 | ||
1ec14ad3 | 1944 | return intel_init_ring_buffer(dev, ring); |
5c1143bb XH |
1945 | } |
1946 | ||
e8616b6c CW |
1947 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size) |
1948 | { | |
1949 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1950 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; | |
6b8294a4 | 1951 | int ret; |
e8616b6c | 1952 | |
59465b5f DV |
1953 | ring->name = "render ring"; |
1954 | ring->id = RCS; | |
1955 | ring->mmio_base = RENDER_RING_BASE; | |
1956 | ||
e8616b6c | 1957 | if (INTEL_INFO(dev)->gen >= 6) { |
b4178f8a DV |
1958 | /* non-kms not supported on gen6+ */ |
1959 | return -ENODEV; | |
e8616b6c | 1960 | } |
28f0cbf7 DV |
1961 | |
1962 | /* Note: gem is not supported on gen5/ilk without kms (the corresponding | |
1963 | * gem_init ioctl returns with -ENODEV). Hence we do not need to set up | |
1964 | * the special gen5 functions. */ | |
1965 | ring->add_request = i9xx_add_request; | |
46f0f8d1 CW |
1966 | if (INTEL_INFO(dev)->gen < 4) |
1967 | ring->flush = gen2_render_ring_flush; | |
1968 | else | |
1969 | ring->flush = gen4_render_ring_flush; | |
28f0cbf7 | 1970 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 1971 | ring->set_seqno = ring_set_seqno; |
c2798b19 CW |
1972 | if (IS_GEN2(dev)) { |
1973 | ring->irq_get = i8xx_ring_get_irq; | |
1974 | ring->irq_put = i8xx_ring_put_irq; | |
1975 | } else { | |
1976 | ring->irq_get = i9xx_ring_get_irq; | |
1977 | ring->irq_put = i9xx_ring_put_irq; | |
1978 | } | |
28f0cbf7 | 1979 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
59465b5f | 1980 | ring->write_tail = ring_write_tail; |
fb3256da DV |
1981 | if (INTEL_INFO(dev)->gen >= 4) |
1982 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
1983 | else if (IS_I830(dev) || IS_845G(dev)) | |
1984 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
1985 | else | |
1986 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
1987 | ring->init = init_render_ring; |
1988 | ring->cleanup = render_ring_cleanup; | |
e8616b6c CW |
1989 | |
1990 | ring->dev = dev; | |
1991 | INIT_LIST_HEAD(&ring->active_list); | |
1992 | INIT_LIST_HEAD(&ring->request_list); | |
e8616b6c CW |
1993 | |
1994 | ring->size = size; | |
1995 | ring->effective_size = ring->size; | |
17f10fdc | 1996 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
e8616b6c CW |
1997 | ring->effective_size -= 128; |
1998 | ||
4225d0f2 DV |
1999 | ring->virtual_start = ioremap_wc(start, size); |
2000 | if (ring->virtual_start == NULL) { | |
e8616b6c CW |
2001 | DRM_ERROR("can not ioremap virtual address for" |
2002 | " ring buffer\n"); | |
2003 | return -ENOMEM; | |
2004 | } | |
2005 | ||
6b8294a4 | 2006 | if (!I915_NEED_GFX_HWS(dev)) { |
035dc1e0 | 2007 | ret = init_phys_status_page(ring); |
6b8294a4 CW |
2008 | if (ret) |
2009 | return ret; | |
2010 | } | |
2011 | ||
e8616b6c CW |
2012 | return 0; |
2013 | } | |
2014 | ||
5c1143bb XH |
2015 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
2016 | { | |
2017 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 2018 | struct intel_ring_buffer *ring = &dev_priv->ring[VCS]; |
5c1143bb | 2019 | |
58fa3835 DV |
2020 | ring->name = "bsd ring"; |
2021 | ring->id = VCS; | |
2022 | ||
0fd2c201 | 2023 | ring->write_tail = ring_write_tail; |
780f18c8 | 2024 | if (INTEL_INFO(dev)->gen >= 6) { |
58fa3835 | 2025 | ring->mmio_base = GEN6_BSD_RING_BASE; |
0fd2c201 DV |
2026 | /* gen6 bsd needs a special wa for tail updates */ |
2027 | if (IS_GEN6(dev)) | |
2028 | ring->write_tail = gen6_bsd_ring_write_tail; | |
ea251324 | 2029 | ring->flush = gen6_bsd_ring_flush; |
58fa3835 DV |
2030 | ring->add_request = gen6_add_request; |
2031 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 2032 | ring->set_seqno = ring_set_seqno; |
abd58f01 BW |
2033 | if (INTEL_INFO(dev)->gen >= 8) { |
2034 | ring->irq_enable_mask = | |
2035 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
2036 | ring->irq_get = gen8_ring_get_irq; | |
2037 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 BW |
2038 | ring->dispatch_execbuffer = |
2039 | gen8_ring_dispatch_execbuffer; | |
abd58f01 BW |
2040 | } else { |
2041 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; | |
2042 | ring->irq_get = gen6_ring_get_irq; | |
2043 | ring->irq_put = gen6_ring_put_irq; | |
1c7a0623 BW |
2044 | ring->dispatch_execbuffer = |
2045 | gen6_ring_dispatch_execbuffer; | |
abd58f01 | 2046 | } |
686cb5f9 | 2047 | ring->sync_to = gen6_ring_sync; |
5586181f BW |
2048 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR; |
2049 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2050 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB; | |
1950de14 | 2051 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE; |
ad776f8b BW |
2052 | ring->signal_mbox[RCS] = GEN6_RVSYNC; |
2053 | ring->signal_mbox[VCS] = GEN6_NOSYNC; | |
2054 | ring->signal_mbox[BCS] = GEN6_BVSYNC; | |
1950de14 | 2055 | ring->signal_mbox[VECS] = GEN6_VEVSYNC; |
58fa3835 DV |
2056 | } else { |
2057 | ring->mmio_base = BSD_RING_BASE; | |
58fa3835 | 2058 | ring->flush = bsd_ring_flush; |
8620a3a9 | 2059 | ring->add_request = i9xx_add_request; |
58fa3835 | 2060 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 2061 | ring->set_seqno = ring_set_seqno; |
e48d8634 | 2062 | if (IS_GEN5(dev)) { |
cc609d5d | 2063 | ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
e48d8634 DV |
2064 | ring->irq_get = gen5_ring_get_irq; |
2065 | ring->irq_put = gen5_ring_put_irq; | |
2066 | } else { | |
e3670319 | 2067 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
e48d8634 DV |
2068 | ring->irq_get = i9xx_ring_get_irq; |
2069 | ring->irq_put = i9xx_ring_put_irq; | |
2070 | } | |
fb3256da | 2071 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
58fa3835 DV |
2072 | } |
2073 | ring->init = init_ring_common; | |
2074 | ||
1ec14ad3 | 2075 | return intel_init_ring_buffer(dev, ring); |
5c1143bb | 2076 | } |
549f7365 CW |
2077 | |
2078 | int intel_init_blt_ring_buffer(struct drm_device *dev) | |
2079 | { | |
2080 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 2081 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
549f7365 | 2082 | |
3535d9dd DV |
2083 | ring->name = "blitter ring"; |
2084 | ring->id = BCS; | |
2085 | ||
2086 | ring->mmio_base = BLT_RING_BASE; | |
2087 | ring->write_tail = ring_write_tail; | |
ea251324 | 2088 | ring->flush = gen6_ring_flush; |
3535d9dd DV |
2089 | ring->add_request = gen6_add_request; |
2090 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 2091 | ring->set_seqno = ring_set_seqno; |
abd58f01 BW |
2092 | if (INTEL_INFO(dev)->gen >= 8) { |
2093 | ring->irq_enable_mask = | |
2094 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
2095 | ring->irq_get = gen8_ring_get_irq; | |
2096 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 | 2097 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
abd58f01 BW |
2098 | } else { |
2099 | ring->irq_enable_mask = GT_BLT_USER_INTERRUPT; | |
2100 | ring->irq_get = gen6_ring_get_irq; | |
2101 | ring->irq_put = gen6_ring_put_irq; | |
1c7a0623 | 2102 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
abd58f01 | 2103 | } |
686cb5f9 | 2104 | ring->sync_to = gen6_ring_sync; |
5586181f BW |
2105 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR; |
2106 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV; | |
2107 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID; | |
1950de14 | 2108 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE; |
ad776f8b BW |
2109 | ring->signal_mbox[RCS] = GEN6_RBSYNC; |
2110 | ring->signal_mbox[VCS] = GEN6_VBSYNC; | |
2111 | ring->signal_mbox[BCS] = GEN6_NOSYNC; | |
1950de14 | 2112 | ring->signal_mbox[VECS] = GEN6_VEBSYNC; |
3535d9dd | 2113 | ring->init = init_ring_common; |
549f7365 | 2114 | |
1ec14ad3 | 2115 | return intel_init_ring_buffer(dev, ring); |
549f7365 | 2116 | } |
a7b9761d | 2117 | |
9a8a2213 BW |
2118 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
2119 | { | |
2120 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2121 | struct intel_ring_buffer *ring = &dev_priv->ring[VECS]; | |
2122 | ||
2123 | ring->name = "video enhancement ring"; | |
2124 | ring->id = VECS; | |
2125 | ||
2126 | ring->mmio_base = VEBOX_RING_BASE; | |
2127 | ring->write_tail = ring_write_tail; | |
2128 | ring->flush = gen6_ring_flush; | |
2129 | ring->add_request = gen6_add_request; | |
2130 | ring->get_seqno = gen6_ring_get_seqno; | |
2131 | ring->set_seqno = ring_set_seqno; | |
abd58f01 BW |
2132 | |
2133 | if (INTEL_INFO(dev)->gen >= 8) { | |
2134 | ring->irq_enable_mask = | |
40c499f9 | 2135 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
abd58f01 BW |
2136 | ring->irq_get = gen8_ring_get_irq; |
2137 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 | 2138 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
abd58f01 BW |
2139 | } else { |
2140 | ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; | |
2141 | ring->irq_get = hsw_vebox_get_irq; | |
2142 | ring->irq_put = hsw_vebox_put_irq; | |
1c7a0623 | 2143 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
abd58f01 | 2144 | } |
9a8a2213 BW |
2145 | ring->sync_to = gen6_ring_sync; |
2146 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER; | |
2147 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV; | |
2148 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB; | |
2149 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID; | |
2150 | ring->signal_mbox[RCS] = GEN6_RVESYNC; | |
2151 | ring->signal_mbox[VCS] = GEN6_VVESYNC; | |
2152 | ring->signal_mbox[BCS] = GEN6_BVESYNC; | |
2153 | ring->signal_mbox[VECS] = GEN6_NOSYNC; | |
2154 | ring->init = init_ring_common; | |
2155 | ||
2156 | return intel_init_ring_buffer(dev, ring); | |
2157 | } | |
2158 | ||
a7b9761d CW |
2159 | int |
2160 | intel_ring_flush_all_caches(struct intel_ring_buffer *ring) | |
2161 | { | |
2162 | int ret; | |
2163 | ||
2164 | if (!ring->gpu_caches_dirty) | |
2165 | return 0; | |
2166 | ||
2167 | ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
2168 | if (ret) | |
2169 | return ret; | |
2170 | ||
2171 | trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
2172 | ||
2173 | ring->gpu_caches_dirty = false; | |
2174 | return 0; | |
2175 | } | |
2176 | ||
2177 | int | |
2178 | intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring) | |
2179 | { | |
2180 | uint32_t flush_domains; | |
2181 | int ret; | |
2182 | ||
2183 | flush_domains = 0; | |
2184 | if (ring->gpu_caches_dirty) | |
2185 | flush_domains = I915_GEM_GPU_DOMAINS; | |
2186 | ||
2187 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
2188 | if (ret) | |
2189 | return ret; | |
2190 | ||
2191 | trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
2192 | ||
2193 | ring->gpu_caches_dirty = false; | |
2194 | return 0; | |
2195 | } |