Commit | Line | Data |
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0bc12bcb RV |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
b2b89f55 RV |
24 | /** |
25 | * DOC: Panel Self Refresh (PSR/SRD) | |
26 | * | |
27 | * Since Haswell Display controller supports Panel Self-Refresh on display | |
28 | * panels witch have a remote frame buffer (RFB) implemented according to PSR | |
29 | * spec in eDP1.3. PSR feature allows the display to go to lower standby states | |
30 | * when system is idle but display is on as it eliminates display refresh | |
31 | * request to DDR memory completely as long as the frame buffer for that | |
32 | * display is unchanged. | |
33 | * | |
34 | * Panel Self Refresh must be supported by both Hardware (source) and | |
35 | * Panel (sink). | |
36 | * | |
37 | * PSR saves power by caching the framebuffer in the panel RFB, which allows us | |
38 | * to power down the link and memory controller. For DSI panels the same idea | |
39 | * is called "manual mode". | |
40 | * | |
41 | * The implementation uses the hardware-based PSR support which automatically | |
42 | * enters/exits self-refresh mode. The hardware takes care of sending the | |
43 | * required DP aux message and could even retrain the link (that part isn't | |
44 | * enabled yet though). The hardware also keeps track of any frontbuffer | |
45 | * changes to know when to exit self-refresh mode again. Unfortunately that | |
46 | * part doesn't work too well, hence why the i915 PSR support uses the | |
47 | * software frontbuffer tracking to make sure it doesn't miss a screen | |
48 | * update. For this integration intel_psr_invalidate() and intel_psr_flush() | |
49 | * get called by the frontbuffer tracking code. Note that because of locking | |
50 | * issues the self-refresh re-enable code is done from a work queue, which | |
51 | * must be correctly synchronized/cancelled when shutting down the pipe." | |
52 | */ | |
53 | ||
0bc12bcb RV |
54 | #include <drm/drmP.h> |
55 | ||
56 | #include "intel_drv.h" | |
57 | #include "i915_drv.h" | |
58 | ||
59 | static bool is_edp_psr(struct intel_dp *intel_dp) | |
60 | { | |
61 | return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED; | |
62 | } | |
63 | ||
e2bbc343 RV |
64 | static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe) |
65 | { | |
fac5e23e | 66 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2bbc343 RV |
67 | uint32_t val; |
68 | ||
69 | val = I915_READ(VLV_PSRSTAT(pipe)) & | |
70 | VLV_EDP_PSR_CURR_STATE_MASK; | |
71 | return (val == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
72 | (val == VLV_EDP_PSR_ACTIVE_SF_UPDATE); | |
73 | } | |
74 | ||
0bc12bcb | 75 | static void intel_psr_write_vsc(struct intel_dp *intel_dp, |
436c6d4a | 76 | const struct edp_vsc_psr *vsc_psr) |
0bc12bcb RV |
77 | { |
78 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
79 | struct drm_device *dev = dig_port->base.base.dev; | |
fac5e23e | 80 | struct drm_i915_private *dev_priv = to_i915(dev); |
0bc12bcb | 81 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); |
436c6d4a | 82 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
f0f59a00 | 83 | i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); |
0bc12bcb RV |
84 | uint32_t *data = (uint32_t *) vsc_psr; |
85 | unsigned int i; | |
86 | ||
87 | /* As per BSPec (Pipe Video Data Island Packet), we need to disable | |
88 | the video DIP being updated before program video DIP data buffer | |
89 | registers for DIP being updated. */ | |
90 | I915_WRITE(ctl_reg, 0); | |
91 | POSTING_READ(ctl_reg); | |
92 | ||
436c6d4a VS |
93 | for (i = 0; i < sizeof(*vsc_psr); i += 4) { |
94 | I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, | |
95 | i >> 2), *data); | |
96 | data++; | |
0bc12bcb | 97 | } |
436c6d4a VS |
98 | for (; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) |
99 | I915_WRITE(HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, | |
100 | i >> 2), 0); | |
0bc12bcb RV |
101 | |
102 | I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); | |
103 | POSTING_READ(ctl_reg); | |
104 | } | |
105 | ||
e2bbc343 RV |
106 | static void vlv_psr_setup_vsc(struct intel_dp *intel_dp) |
107 | { | |
108 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
109 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 110 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2bbc343 RV |
111 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
112 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
113 | uint32_t val; | |
114 | ||
115 | /* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */ | |
116 | val = I915_READ(VLV_VSCSDP(pipe)); | |
117 | val &= ~VLV_EDP_PSR_SDP_FREQ_MASK; | |
118 | val |= VLV_EDP_PSR_SDP_FREQ_EVFRAME; | |
119 | I915_WRITE(VLV_VSCSDP(pipe), val); | |
120 | } | |
121 | ||
474d1ec4 SJ |
122 | static void skl_psr_setup_su_vsc(struct intel_dp *intel_dp) |
123 | { | |
124 | struct edp_vsc_psr psr_vsc; | |
97da2ef4 NV |
125 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
126 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
127 | struct drm_i915_private *dev_priv = to_i915(dev); | |
474d1ec4 SJ |
128 | |
129 | /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */ | |
130 | memset(&psr_vsc, 0, sizeof(psr_vsc)); | |
131 | psr_vsc.sdp_header.HB0 = 0; | |
132 | psr_vsc.sdp_header.HB1 = 0x7; | |
97da2ef4 NV |
133 | if (dev_priv->psr.colorimetry_support && |
134 | dev_priv->psr.y_cord_support) { | |
135 | psr_vsc.sdp_header.HB2 = 0x5; | |
136 | psr_vsc.sdp_header.HB3 = 0x13; | |
137 | } else if (dev_priv->psr.y_cord_support) { | |
138 | psr_vsc.sdp_header.HB2 = 0x4; | |
139 | psr_vsc.sdp_header.HB3 = 0xe; | |
140 | } else { | |
141 | psr_vsc.sdp_header.HB2 = 0x3; | |
142 | psr_vsc.sdp_header.HB3 = 0xc; | |
143 | } | |
144 | ||
474d1ec4 SJ |
145 | intel_psr_write_vsc(intel_dp, &psr_vsc); |
146 | } | |
147 | ||
e2bbc343 | 148 | static void hsw_psr_setup_vsc(struct intel_dp *intel_dp) |
0bc12bcb RV |
149 | { |
150 | struct edp_vsc_psr psr_vsc; | |
151 | ||
152 | /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ | |
153 | memset(&psr_vsc, 0, sizeof(psr_vsc)); | |
154 | psr_vsc.sdp_header.HB0 = 0; | |
155 | psr_vsc.sdp_header.HB1 = 0x7; | |
156 | psr_vsc.sdp_header.HB2 = 0x2; | |
157 | psr_vsc.sdp_header.HB3 = 0x8; | |
158 | intel_psr_write_vsc(intel_dp, &psr_vsc); | |
159 | } | |
160 | ||
e2bbc343 RV |
161 | static void vlv_psr_enable_sink(struct intel_dp *intel_dp) |
162 | { | |
163 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, | |
670b90d2 | 164 | DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); |
e2bbc343 RV |
165 | } |
166 | ||
f0f59a00 VS |
167 | static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv, |
168 | enum port port) | |
1f38089c VS |
169 | { |
170 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
171 | return DP_AUX_CH_CTL(port); | |
172 | else | |
173 | return EDP_PSR_AUX_CTL; | |
174 | } | |
175 | ||
f0f59a00 VS |
176 | static i915_reg_t psr_aux_data_reg(struct drm_i915_private *dev_priv, |
177 | enum port port, int index) | |
1f38089c VS |
178 | { |
179 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
180 | return DP_AUX_CH_DATA(port, index); | |
181 | else | |
182 | return EDP_PSR_AUX_DATA(index); | |
183 | } | |
184 | ||
e2bbc343 | 185 | static void hsw_psr_enable_sink(struct intel_dp *intel_dp) |
0bc12bcb RV |
186 | { |
187 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
188 | struct drm_device *dev = dig_port->base.base.dev; | |
fac5e23e | 189 | struct drm_i915_private *dev_priv = to_i915(dev); |
0bc12bcb | 190 | uint32_t aux_clock_divider; |
f0f59a00 | 191 | i915_reg_t aux_ctl_reg; |
0bc12bcb RV |
192 | static const uint8_t aux_msg[] = { |
193 | [0] = DP_AUX_NATIVE_WRITE << 4, | |
194 | [1] = DP_SET_POWER >> 8, | |
195 | [2] = DP_SET_POWER & 0xff, | |
196 | [3] = 1 - 1, | |
197 | [4] = DP_SET_POWER_D0, | |
198 | }; | |
750a951f | 199 | enum port port = dig_port->port; |
d4dcbdce | 200 | u32 aux_ctl; |
0bc12bcb RV |
201 | int i; |
202 | ||
203 | BUILD_BUG_ON(sizeof(aux_msg) > 20); | |
204 | ||
205 | aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); | |
206 | ||
474d1ec4 SJ |
207 | /* Enable AUX frame sync at sink */ |
208 | if (dev_priv->psr.aux_frame_sync) | |
209 | drm_dp_dpcd_writeb(&intel_dp->aux, | |
210 | DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF, | |
211 | DP_AUX_FRAME_SYNC_ENABLE); | |
340c93c0 NV |
212 | /* Enable ALPM at sink for psr2 */ |
213 | if (dev_priv->psr.psr2_support && dev_priv->psr.alpm) | |
214 | drm_dp_dpcd_writeb(&intel_dp->aux, | |
215 | DP_RECEIVER_ALPM_CONFIG, | |
216 | DP_ALPM_ENABLE); | |
6f32ea7e DV |
217 | if (dev_priv->psr.link_standby) |
218 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, | |
219 | DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); | |
220 | else | |
221 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, | |
222 | DP_PSR_ENABLE); | |
223 | ||
1f38089c | 224 | aux_ctl_reg = psr_aux_ctl_reg(dev_priv, port); |
e3d99845 | 225 | |
0bc12bcb RV |
226 | /* Setup AUX registers */ |
227 | for (i = 0; i < sizeof(aux_msg); i += 4) | |
1f38089c | 228 | I915_WRITE(psr_aux_data_reg(dev_priv, port, i >> 2), |
0bc12bcb RV |
229 | intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i)); |
230 | ||
d4dcbdce DV |
231 | aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, 0, sizeof(aux_msg), |
232 | aux_clock_divider); | |
233 | I915_WRITE(aux_ctl_reg, aux_ctl); | |
0bc12bcb RV |
234 | } |
235 | ||
e2bbc343 RV |
236 | static void vlv_psr_enable_source(struct intel_dp *intel_dp) |
237 | { | |
238 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
239 | struct drm_device *dev = dig_port->base.base.dev; | |
fac5e23e | 240 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2bbc343 RV |
241 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
242 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
243 | ||
244 | /* Transition from PSR_state 0 to PSR_state 1, i.e. PSR Inactive */ | |
245 | I915_WRITE(VLV_PSRCTL(pipe), | |
246 | VLV_EDP_PSR_MODE_SW_TIMER | | |
247 | VLV_EDP_PSR_SRC_TRANSMITTER_STATE | | |
248 | VLV_EDP_PSR_ENABLE); | |
249 | } | |
250 | ||
995d3047 RV |
251 | static void vlv_psr_activate(struct intel_dp *intel_dp) |
252 | { | |
253 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
254 | struct drm_device *dev = dig_port->base.base.dev; | |
fac5e23e | 255 | struct drm_i915_private *dev_priv = to_i915(dev); |
995d3047 RV |
256 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
257 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
258 | ||
259 | /* Let's do the transition from PSR_state 1 to PSR_state 2 | |
260 | * that is PSR transition to active - static frame transmission. | |
261 | * Then Hardware is responsible for the transition to PSR_state 3 | |
262 | * that is PSR active - no Remote Frame Buffer (RFB) update. | |
263 | */ | |
264 | I915_WRITE(VLV_PSRCTL(pipe), I915_READ(VLV_PSRCTL(pipe)) | | |
265 | VLV_EDP_PSR_ACTIVE_ENTRY); | |
266 | } | |
267 | ||
3fcb0ca1 | 268 | static void intel_enable_source_psr1(struct intel_dp *intel_dp) |
0bc12bcb RV |
269 | { |
270 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
271 | struct drm_device *dev = dig_port->base.base.dev; | |
fac5e23e | 272 | struct drm_i915_private *dev_priv = to_i915(dev); |
474d1ec4 | 273 | |
0bc12bcb | 274 | uint32_t max_sleep_time = 0x1f; |
40918e0b RV |
275 | /* |
276 | * Let's respect VBT in case VBT asks a higher idle_frame value. | |
277 | * Let's use 6 as the minimum to cover all known cases including | |
278 | * the off-by-one issue that HW has in some cases. Also there are | |
279 | * cases where sink should be able to train | |
280 | * with the 5 or 6 idle patterns. | |
d44b4dcb | 281 | */ |
40918e0b | 282 | uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames); |
50db1390 DV |
283 | uint32_t val = EDP_PSR_ENABLE; |
284 | ||
285 | val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT; | |
286 | val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT; | |
7370c68d | 287 | |
772c2a51 | 288 | if (IS_HASWELL(dev_priv)) |
7370c68d | 289 | val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; |
0bc12bcb | 290 | |
60e5ffe3 RV |
291 | if (dev_priv->psr.link_standby) |
292 | val |= EDP_PSR_LINK_STANDBY; | |
293 | ||
50db1390 DV |
294 | if (dev_priv->vbt.psr.tp1_wakeup_time > 5) |
295 | val |= EDP_PSR_TP1_TIME_2500us; | |
296 | else if (dev_priv->vbt.psr.tp1_wakeup_time > 1) | |
297 | val |= EDP_PSR_TP1_TIME_500us; | |
298 | else if (dev_priv->vbt.psr.tp1_wakeup_time > 0) | |
299 | val |= EDP_PSR_TP1_TIME_100us; | |
300 | else | |
301 | val |= EDP_PSR_TP1_TIME_0us; | |
302 | ||
303 | if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) | |
304 | val |= EDP_PSR_TP2_TP3_TIME_2500us; | |
305 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1) | |
306 | val |= EDP_PSR_TP2_TP3_TIME_500us; | |
307 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0) | |
308 | val |= EDP_PSR_TP2_TP3_TIME_100us; | |
309 | else | |
310 | val |= EDP_PSR_TP2_TP3_TIME_0us; | |
311 | ||
312 | if (intel_dp_source_supports_hbr2(intel_dp) && | |
313 | drm_dp_tps3_supported(intel_dp->dpcd)) | |
314 | val |= EDP_PSR_TP1_TP3_SEL; | |
315 | else | |
316 | val |= EDP_PSR_TP1_TP2_SEL; | |
317 | ||
318 | I915_WRITE(EDP_PSR_CTL, val); | |
3fcb0ca1 | 319 | } |
50db1390 | 320 | |
3fcb0ca1 NV |
321 | static void intel_enable_source_psr2(struct intel_dp *intel_dp) |
322 | { | |
323 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
324 | struct drm_device *dev = dig_port->base.base.dev; | |
325 | struct drm_i915_private *dev_priv = to_i915(dev); | |
326 | /* | |
327 | * Let's respect VBT in case VBT asks a higher idle_frame value. | |
328 | * Let's use 6 as the minimum to cover all known cases including | |
329 | * the off-by-one issue that HW has in some cases. Also there are | |
330 | * cases where sink should be able to train | |
331 | * with the 5 or 6 idle patterns. | |
332 | */ | |
333 | uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames); | |
334 | uint32_t val; | |
335 | ||
336 | val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT; | |
50db1390 DV |
337 | |
338 | /* FIXME: selective update is probably totally broken because it doesn't | |
339 | * mesh at all with our frontbuffer tracking. And the hw alone isn't | |
340 | * good enough. */ | |
6433226b NV |
341 | val |= EDP_PSR2_ENABLE | |
342 | EDP_SU_TRACK_ENABLE | | |
343 | EDP_FRAMES_BEFORE_SU_ENTRY; | |
50db1390 DV |
344 | |
345 | if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) | |
346 | val |= EDP_PSR2_TP2_TIME_2500; | |
347 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1) | |
348 | val |= EDP_PSR2_TP2_TIME_500; | |
349 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0) | |
350 | val |= EDP_PSR2_TP2_TIME_100; | |
351 | else | |
352 | val |= EDP_PSR2_TP2_TIME_50; | |
474d1ec4 | 353 | |
50db1390 | 354 | I915_WRITE(EDP_PSR2_CTL, val); |
0bc12bcb RV |
355 | } |
356 | ||
3fcb0ca1 NV |
357 | static void hsw_psr_enable_source(struct intel_dp *intel_dp) |
358 | { | |
359 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
360 | struct drm_device *dev = dig_port->base.base.dev; | |
361 | struct drm_i915_private *dev_priv = to_i915(dev); | |
362 | ||
363 | /* psr1 and psr2 are mutually exclusive.*/ | |
364 | if (dev_priv->psr.psr2_support) | |
365 | intel_enable_source_psr2(intel_dp); | |
366 | else | |
367 | intel_enable_source_psr1(intel_dp); | |
368 | } | |
369 | ||
0bc12bcb RV |
370 | static bool intel_psr_match_conditions(struct intel_dp *intel_dp) |
371 | { | |
372 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
373 | struct drm_device *dev = dig_port->base.base.dev; | |
fac5e23e | 374 | struct drm_i915_private *dev_priv = to_i915(dev); |
0bc12bcb RV |
375 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
376 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dfd2e9ab VS |
377 | const struct drm_display_mode *adjusted_mode = |
378 | &intel_crtc->config->base.adjusted_mode; | |
379 | int psr_setup_time; | |
0bc12bcb RV |
380 | |
381 | lockdep_assert_held(&dev_priv->psr.lock); | |
382 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); | |
383 | WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); | |
384 | ||
385 | dev_priv->psr.source_ok = false; | |
386 | ||
dc9b5a0c RV |
387 | /* |
388 | * HSW spec explicitly says PSR is tied to port A. | |
389 | * BDW+ platforms with DDI implementation of PSR have different | |
390 | * PSR registers per transcoder and we only implement transcoder EDP | |
391 | * ones. Since by Display design transcoder EDP is tied to port A | |
392 | * we can safely escape based on the port A. | |
393 | */ | |
4f8036a2 | 394 | if (HAS_DDI(dev_priv) && dig_port->port != PORT_A) { |
dc9b5a0c | 395 | DRM_DEBUG_KMS("PSR condition failed: Port not supported\n"); |
0bc12bcb RV |
396 | return false; |
397 | } | |
398 | ||
399 | if (!i915.enable_psr) { | |
400 | DRM_DEBUG_KMS("PSR disable by flag\n"); | |
401 | return false; | |
402 | } | |
403 | ||
920a14b2 | 404 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
65f61b42 RV |
405 | !dev_priv->psr.link_standby) { |
406 | DRM_ERROR("PSR condition failed: Link off requested but not supported on this platform\n"); | |
407 | return false; | |
408 | } | |
409 | ||
772c2a51 | 410 | if (IS_HASWELL(dev_priv) && |
6e3c9717 | 411 | I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) & |
c8e68b7e | 412 | S3D_ENABLE) { |
0bc12bcb RV |
413 | DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); |
414 | return false; | |
415 | } | |
416 | ||
772c2a51 | 417 | if (IS_HASWELL(dev_priv) && |
dfd2e9ab | 418 | adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
0bc12bcb RV |
419 | DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); |
420 | return false; | |
421 | } | |
422 | ||
dfd2e9ab VS |
423 | psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); |
424 | if (psr_setup_time < 0) { | |
425 | DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n", | |
426 | intel_dp->psr_dpcd[1]); | |
427 | return false; | |
428 | } | |
429 | ||
430 | if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > | |
431 | adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { | |
432 | DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n", | |
433 | psr_setup_time); | |
434 | return false; | |
435 | } | |
436 | ||
acf45d11 | 437 | /* PSR2 is restricted to work with panel resolutions upto 3200x2000 */ |
bef8c056 NV |
438 | if (dev_priv->psr.psr2_support && |
439 | (intel_crtc->config->pipe_src_w > 3200 || | |
440 | intel_crtc->config->pipe_src_h > 2000)) { | |
acf45d11 NV |
441 | dev_priv->psr.psr2_support = false; |
442 | return false; | |
443 | } | |
18b9bf3e NV |
444 | |
445 | /* | |
446 | * FIXME:enable psr2 only for y-cordinate psr2 panels | |
447 | * After gtc implementation , remove this restriction. | |
448 | */ | |
449 | if (!dev_priv->psr.y_cord_support && dev_priv->psr.psr2_support) { | |
450 | DRM_DEBUG_KMS("PSR2 disabled, panel does not support Y coordinate\n"); | |
451 | return false; | |
452 | } | |
acf45d11 | 453 | |
0bc12bcb RV |
454 | dev_priv->psr.source_ok = true; |
455 | return true; | |
456 | } | |
457 | ||
e2bbc343 | 458 | static void intel_psr_activate(struct intel_dp *intel_dp) |
0bc12bcb RV |
459 | { |
460 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
461 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 462 | struct drm_i915_private *dev_priv = to_i915(dev); |
0bc12bcb | 463 | |
3fcb0ca1 NV |
464 | if (dev_priv->psr.psr2_support) |
465 | WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE); | |
466 | else | |
467 | WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE); | |
0bc12bcb RV |
468 | WARN_ON(dev_priv->psr.active); |
469 | lockdep_assert_held(&dev_priv->psr.lock); | |
470 | ||
995d3047 | 471 | /* Enable/Re-enable PSR on the host */ |
4f8036a2 | 472 | if (HAS_DDI(dev_priv)) |
995d3047 RV |
473 | /* On HSW+ after we enable PSR on source it will activate it |
474 | * as soon as it match configure idle_frame count. So | |
475 | * we just actually enable it here on activation time. | |
476 | */ | |
477 | hsw_psr_enable_source(intel_dp); | |
478 | else | |
479 | vlv_psr_activate(intel_dp); | |
480 | ||
0bc12bcb RV |
481 | dev_priv->psr.active = true; |
482 | } | |
483 | ||
b2b89f55 RV |
484 | /** |
485 | * intel_psr_enable - Enable PSR | |
486 | * @intel_dp: Intel DP | |
487 | * | |
488 | * This function can only be called after the pipe is fully trained and enabled. | |
489 | */ | |
0bc12bcb RV |
490 | void intel_psr_enable(struct intel_dp *intel_dp) |
491 | { | |
492 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
493 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 494 | struct drm_i915_private *dev_priv = to_i915(dev); |
d86f0482 NV |
495 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
496 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; | |
497 | u32 chicken; | |
0bc12bcb | 498 | |
56b857a5 | 499 | if (!HAS_PSR(dev_priv)) { |
0bc12bcb RV |
500 | DRM_DEBUG_KMS("PSR not supported on this platform\n"); |
501 | return; | |
502 | } | |
503 | ||
504 | if (!is_edp_psr(intel_dp)) { | |
505 | DRM_DEBUG_KMS("PSR not supported by this panel\n"); | |
506 | return; | |
507 | } | |
508 | ||
509 | mutex_lock(&dev_priv->psr.lock); | |
510 | if (dev_priv->psr.enabled) { | |
511 | DRM_DEBUG_KMS("PSR already in use\n"); | |
512 | goto unlock; | |
513 | } | |
514 | ||
515 | if (!intel_psr_match_conditions(intel_dp)) | |
516 | goto unlock; | |
517 | ||
518 | dev_priv->psr.busy_frontbuffer_bits = 0; | |
519 | ||
4f8036a2 | 520 | if (HAS_DDI(dev_priv)) { |
474d1ec4 | 521 | if (dev_priv->psr.psr2_support) { |
acf45d11 | 522 | skl_psr_setup_su_vsc(intel_dp); |
d86f0482 NV |
523 | chicken = PSR2_VSC_ENABLE_PROG_HEADER; |
524 | if (dev_priv->psr.y_cord_support) | |
525 | chicken |= PSR2_ADD_VERTICAL_LINE_COUNT; | |
526 | I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken); | |
6433226b NV |
527 | I915_WRITE(EDP_PSR_DEBUG_CTL, |
528 | EDP_PSR_DEBUG_MASK_MEMUP | | |
529 | EDP_PSR_DEBUG_MASK_HPD | | |
530 | EDP_PSR_DEBUG_MASK_LPSP | | |
531 | EDP_PSR_DEBUG_MASK_MAX_SLEEP | | |
532 | EDP_PSR_DEBUG_MASK_DISP_REG_WRITE); | |
3fcb0ca1 NV |
533 | } else { |
534 | /* set up vsc header for psr1 */ | |
535 | hsw_psr_setup_vsc(intel_dp); | |
6433226b NV |
536 | /* |
537 | * Per Spec: Avoid continuous PSR exit by masking MEMUP | |
538 | * and HPD. also mask LPSP to avoid dependency on other | |
539 | * drivers that might block runtime_pm besides | |
540 | * preventing other hw tracking issues now we can rely | |
541 | * on frontbuffer tracking. | |
542 | */ | |
543 | I915_WRITE(EDP_PSR_DEBUG_CTL, | |
544 | EDP_PSR_DEBUG_MASK_MEMUP | | |
545 | EDP_PSR_DEBUG_MASK_HPD | | |
546 | EDP_PSR_DEBUG_MASK_LPSP); | |
474d1ec4 SJ |
547 | } |
548 | ||
e2bbc343 RV |
549 | /* Enable PSR on the panel */ |
550 | hsw_psr_enable_sink(intel_dp); | |
e3d99845 | 551 | |
66478475 | 552 | if (INTEL_GEN(dev_priv) >= 9) |
e3d99845 | 553 | intel_psr_activate(intel_dp); |
e2bbc343 RV |
554 | } else { |
555 | vlv_psr_setup_vsc(intel_dp); | |
556 | ||
557 | /* Enable PSR on the panel */ | |
558 | vlv_psr_enable_sink(intel_dp); | |
559 | ||
560 | /* On HSW+ enable_source also means go to PSR entry/active | |
561 | * state as soon as idle_frame achieved and here would be | |
562 | * to soon. However on VLV enable_source just enable PSR | |
563 | * but let it on inactive state. So we might do this prior | |
564 | * to active transition, i.e. here. | |
565 | */ | |
566 | vlv_psr_enable_source(intel_dp); | |
567 | } | |
0bc12bcb | 568 | |
d0ac896a RV |
569 | /* |
570 | * FIXME: Activation should happen immediately since this function | |
571 | * is just called after pipe is fully trained and enabled. | |
572 | * However on every platform we face issues when first activation | |
573 | * follows a modeset so quickly. | |
574 | * - On VLV/CHV we get bank screen on first activation | |
575 | * - On HSW/BDW we get a recoverable frozen screen until next | |
576 | * exit-activate sequence. | |
577 | */ | |
66478475 | 578 | if (INTEL_GEN(dev_priv) < 9) |
d0ac896a RV |
579 | schedule_delayed_work(&dev_priv->psr.work, |
580 | msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); | |
581 | ||
0bc12bcb RV |
582 | dev_priv->psr.enabled = intel_dp; |
583 | unlock: | |
584 | mutex_unlock(&dev_priv->psr.lock); | |
585 | } | |
586 | ||
e2bbc343 | 587 | static void vlv_psr_disable(struct intel_dp *intel_dp) |
0bc12bcb RV |
588 | { |
589 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
590 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 591 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2bbc343 RV |
592 | struct intel_crtc *intel_crtc = |
593 | to_intel_crtc(intel_dig_port->base.base.crtc); | |
594 | uint32_t val; | |
0bc12bcb | 595 | |
e2bbc343 RV |
596 | if (dev_priv->psr.active) { |
597 | /* Put VLV PSR back to PSR_state 0 that is PSR Disabled. */ | |
eb0241c1 CW |
598 | if (intel_wait_for_register(dev_priv, |
599 | VLV_PSRSTAT(intel_crtc->pipe), | |
600 | VLV_EDP_PSR_IN_TRANS, | |
601 | 0, | |
602 | 1)) | |
e2bbc343 RV |
603 | WARN(1, "PSR transition took longer than expected\n"); |
604 | ||
605 | val = I915_READ(VLV_PSRCTL(intel_crtc->pipe)); | |
606 | val &= ~VLV_EDP_PSR_ACTIVE_ENTRY; | |
607 | val &= ~VLV_EDP_PSR_ENABLE; | |
608 | val &= ~VLV_EDP_PSR_MODE_MASK; | |
609 | I915_WRITE(VLV_PSRCTL(intel_crtc->pipe), val); | |
610 | ||
611 | dev_priv->psr.active = false; | |
612 | } else { | |
613 | WARN_ON(vlv_is_psr_active_on_pipe(dev, intel_crtc->pipe)); | |
0bc12bcb | 614 | } |
e2bbc343 RV |
615 | } |
616 | ||
617 | static void hsw_psr_disable(struct intel_dp *intel_dp) | |
618 | { | |
619 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
620 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 621 | struct drm_i915_private *dev_priv = to_i915(dev); |
0bc12bcb RV |
622 | |
623 | if (dev_priv->psr.active) { | |
77affa31 CW |
624 | i915_reg_t psr_ctl; |
625 | u32 psr_status_mask; | |
626 | ||
f40c484b NV |
627 | if (dev_priv->psr.aux_frame_sync) |
628 | drm_dp_dpcd_writeb(&intel_dp->aux, | |
629 | DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF, | |
630 | 0); | |
631 | ||
3fcb0ca1 | 632 | if (dev_priv->psr.psr2_support) { |
77affa31 CW |
633 | psr_ctl = EDP_PSR2_CTL; |
634 | psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; | |
635 | ||
636 | I915_WRITE(psr_ctl, | |
637 | I915_READ(psr_ctl) & | |
638 | ~(EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE)); | |
639 | ||
3fcb0ca1 | 640 | } else { |
77affa31 CW |
641 | psr_ctl = EDP_PSR_STATUS_CTL; |
642 | psr_status_mask = EDP_PSR_STATUS_STATE_MASK; | |
643 | ||
644 | I915_WRITE(psr_ctl, | |
645 | I915_READ(psr_ctl) & ~EDP_PSR_ENABLE); | |
3fcb0ca1 | 646 | } |
77affa31 CW |
647 | |
648 | /* Wait till PSR is idle */ | |
649 | if (intel_wait_for_register(dev_priv, | |
650 | psr_ctl, psr_status_mask, 0, | |
651 | 2000)) | |
652 | DRM_ERROR("Timed out waiting for PSR Idle State\n"); | |
653 | ||
0bc12bcb RV |
654 | dev_priv->psr.active = false; |
655 | } else { | |
3fcb0ca1 NV |
656 | if (dev_priv->psr.psr2_support) |
657 | WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE); | |
658 | else | |
659 | WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE); | |
0bc12bcb | 660 | } |
e2bbc343 RV |
661 | } |
662 | ||
663 | /** | |
664 | * intel_psr_disable - Disable PSR | |
665 | * @intel_dp: Intel DP | |
666 | * | |
667 | * This function needs to be called before disabling pipe. | |
668 | */ | |
669 | void intel_psr_disable(struct intel_dp *intel_dp) | |
670 | { | |
671 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
672 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 673 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2bbc343 RV |
674 | |
675 | mutex_lock(&dev_priv->psr.lock); | |
676 | if (!dev_priv->psr.enabled) { | |
677 | mutex_unlock(&dev_priv->psr.lock); | |
678 | return; | |
679 | } | |
680 | ||
b6e4d534 | 681 | /* Disable PSR on Source */ |
4f8036a2 | 682 | if (HAS_DDI(dev_priv)) |
e2bbc343 RV |
683 | hsw_psr_disable(intel_dp); |
684 | else | |
685 | vlv_psr_disable(intel_dp); | |
0bc12bcb | 686 | |
b6e4d534 RV |
687 | /* Disable PSR on Sink */ |
688 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); | |
689 | ||
0bc12bcb RV |
690 | dev_priv->psr.enabled = NULL; |
691 | mutex_unlock(&dev_priv->psr.lock); | |
692 | ||
693 | cancel_delayed_work_sync(&dev_priv->psr.work); | |
694 | } | |
695 | ||
696 | static void intel_psr_work(struct work_struct *work) | |
697 | { | |
698 | struct drm_i915_private *dev_priv = | |
699 | container_of(work, typeof(*dev_priv), psr.work.work); | |
700 | struct intel_dp *intel_dp = dev_priv->psr.enabled; | |
995d3047 RV |
701 | struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc; |
702 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
0bc12bcb RV |
703 | |
704 | /* We have to make sure PSR is ready for re-enable | |
705 | * otherwise it keeps disabled until next full enable/disable cycle. | |
706 | * PSR might take some time to get fully disabled | |
707 | * and be ready for re-enable. | |
708 | */ | |
2d1fe073 | 709 | if (HAS_DDI(dev_priv)) { |
3fcb0ca1 NV |
710 | if (dev_priv->psr.psr2_support) { |
711 | if (intel_wait_for_register(dev_priv, | |
712 | EDP_PSR2_STATUS_CTL, | |
713 | EDP_PSR2_STATUS_STATE_MASK, | |
714 | 0, | |
715 | 50)) { | |
716 | DRM_ERROR("Timed out waiting for PSR2 Idle for re-enable\n"); | |
717 | return; | |
718 | } | |
719 | } else { | |
720 | if (intel_wait_for_register(dev_priv, | |
721 | EDP_PSR_STATUS_CTL, | |
722 | EDP_PSR_STATUS_STATE_MASK, | |
723 | 0, | |
724 | 50)) { | |
725 | DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n"); | |
726 | return; | |
727 | } | |
995d3047 RV |
728 | } |
729 | } else { | |
12bb6319 CW |
730 | if (intel_wait_for_register(dev_priv, |
731 | VLV_PSRSTAT(pipe), | |
732 | VLV_EDP_PSR_IN_TRANS, | |
733 | 0, | |
734 | 1)) { | |
995d3047 RV |
735 | DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n"); |
736 | return; | |
737 | } | |
0bc12bcb | 738 | } |
0bc12bcb RV |
739 | mutex_lock(&dev_priv->psr.lock); |
740 | intel_dp = dev_priv->psr.enabled; | |
741 | ||
742 | if (!intel_dp) | |
743 | goto unlock; | |
744 | ||
745 | /* | |
746 | * The delayed work can race with an invalidate hence we need to | |
747 | * recheck. Since psr_flush first clears this and then reschedules we | |
748 | * won't ever miss a flush when bailing out here. | |
749 | */ | |
750 | if (dev_priv->psr.busy_frontbuffer_bits) | |
751 | goto unlock; | |
752 | ||
e2bbc343 | 753 | intel_psr_activate(intel_dp); |
0bc12bcb RV |
754 | unlock: |
755 | mutex_unlock(&dev_priv->psr.lock); | |
756 | } | |
757 | ||
5748b6a1 | 758 | static void intel_psr_exit(struct drm_i915_private *dev_priv) |
0bc12bcb | 759 | { |
995d3047 RV |
760 | struct intel_dp *intel_dp = dev_priv->psr.enabled; |
761 | struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc; | |
762 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
763 | u32 val; | |
0bc12bcb | 764 | |
995d3047 RV |
765 | if (!dev_priv->psr.active) |
766 | return; | |
767 | ||
5748b6a1 | 768 | if (HAS_DDI(dev_priv)) { |
f40c484b NV |
769 | if (dev_priv->psr.aux_frame_sync) |
770 | drm_dp_dpcd_writeb(&intel_dp->aux, | |
771 | DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF, | |
772 | 0); | |
3fcb0ca1 NV |
773 | if (dev_priv->psr.psr2_support) { |
774 | val = I915_READ(EDP_PSR2_CTL); | |
775 | WARN_ON(!(val & EDP_PSR2_ENABLE)); | |
776 | I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE); | |
777 | } else { | |
778 | val = I915_READ(EDP_PSR_CTL); | |
779 | WARN_ON(!(val & EDP_PSR_ENABLE)); | |
780 | I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE); | |
781 | } | |
995d3047 RV |
782 | } else { |
783 | val = I915_READ(VLV_PSRCTL(pipe)); | |
784 | ||
785 | /* Here we do the transition from PSR_state 3 to PSR_state 5 | |
786 | * directly once PSR State 4 that is active with single frame | |
787 | * update can be skipped. PSR_state 5 that is PSR exit then | |
788 | * Hardware is responsible to transition back to PSR_state 1 | |
789 | * that is PSR inactive. Same state after | |
790 | * vlv_edp_psr_enable_source. | |
791 | */ | |
792 | val &= ~VLV_EDP_PSR_ACTIVE_ENTRY; | |
793 | I915_WRITE(VLV_PSRCTL(pipe), val); | |
794 | ||
795 | /* Send AUX wake up - Spec says after transitioning to PSR | |
796 | * active we have to send AUX wake up by writing 01h in DPCD | |
797 | * 600h of sink device. | |
798 | * XXX: This might slow down the transition, but without this | |
799 | * HW doesn't complete the transition to PSR_state 1 and we | |
800 | * never get the screen updated. | |
801 | */ | |
802 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, | |
803 | DP_SET_POWER_D0); | |
0bc12bcb RV |
804 | } |
805 | ||
995d3047 | 806 | dev_priv->psr.active = false; |
0bc12bcb RV |
807 | } |
808 | ||
c7240c3b RV |
809 | /** |
810 | * intel_psr_single_frame_update - Single Frame Update | |
5748b6a1 | 811 | * @dev_priv: i915 device |
20c8838b | 812 | * @frontbuffer_bits: frontbuffer plane tracking bits |
c7240c3b RV |
813 | * |
814 | * Some platforms support a single frame update feature that is used to | |
815 | * send and update only one frame on Remote Frame Buffer. | |
816 | * So far it is only implemented for Valleyview and Cherryview because | |
817 | * hardware requires this to be done before a page flip. | |
818 | */ | |
5748b6a1 | 819 | void intel_psr_single_frame_update(struct drm_i915_private *dev_priv, |
20c8838b | 820 | unsigned frontbuffer_bits) |
c7240c3b | 821 | { |
c7240c3b RV |
822 | struct drm_crtc *crtc; |
823 | enum pipe pipe; | |
824 | u32 val; | |
825 | ||
826 | /* | |
827 | * Single frame update is already supported on BDW+ but it requires | |
828 | * many W/A and it isn't really needed. | |
829 | */ | |
5748b6a1 | 830 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
c7240c3b RV |
831 | return; |
832 | ||
833 | mutex_lock(&dev_priv->psr.lock); | |
834 | if (!dev_priv->psr.enabled) { | |
835 | mutex_unlock(&dev_priv->psr.lock); | |
836 | return; | |
837 | } | |
838 | ||
839 | crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; | |
840 | pipe = to_intel_crtc(crtc)->pipe; | |
c7240c3b | 841 | |
20c8838b DV |
842 | if (frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)) { |
843 | val = I915_READ(VLV_PSRCTL(pipe)); | |
c7240c3b | 844 | |
20c8838b DV |
845 | /* |
846 | * We need to set this bit before writing registers for a flip. | |
847 | * This bit will be self-clear when it gets to the PSR active state. | |
848 | */ | |
849 | I915_WRITE(VLV_PSRCTL(pipe), val | VLV_EDP_PSR_SINGLE_FRAME_UPDATE); | |
850 | } | |
c7240c3b RV |
851 | mutex_unlock(&dev_priv->psr.lock); |
852 | } | |
853 | ||
b2b89f55 RV |
854 | /** |
855 | * intel_psr_invalidate - Invalidade PSR | |
5748b6a1 | 856 | * @dev_priv: i915 device |
b2b89f55 RV |
857 | * @frontbuffer_bits: frontbuffer plane tracking bits |
858 | * | |
859 | * Since the hardware frontbuffer tracking has gaps we need to integrate | |
860 | * with the software frontbuffer tracking. This function gets called every | |
861 | * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be | |
862 | * disabled if the frontbuffer mask contains a buffer relevant to PSR. | |
863 | * | |
864 | * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." | |
865 | */ | |
5748b6a1 | 866 | void intel_psr_invalidate(struct drm_i915_private *dev_priv, |
20c8838b | 867 | unsigned frontbuffer_bits) |
0bc12bcb | 868 | { |
0bc12bcb RV |
869 | struct drm_crtc *crtc; |
870 | enum pipe pipe; | |
871 | ||
872 | mutex_lock(&dev_priv->psr.lock); | |
873 | if (!dev_priv->psr.enabled) { | |
874 | mutex_unlock(&dev_priv->psr.lock); | |
875 | return; | |
876 | } | |
877 | ||
878 | crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; | |
879 | pipe = to_intel_crtc(crtc)->pipe; | |
880 | ||
0bc12bcb | 881 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
0bc12bcb | 882 | dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits; |
ec76d629 DV |
883 | |
884 | if (frontbuffer_bits) | |
5748b6a1 | 885 | intel_psr_exit(dev_priv); |
ec76d629 | 886 | |
0bc12bcb RV |
887 | mutex_unlock(&dev_priv->psr.lock); |
888 | } | |
889 | ||
b2b89f55 RV |
890 | /** |
891 | * intel_psr_flush - Flush PSR | |
5748b6a1 | 892 | * @dev_priv: i915 device |
b2b89f55 | 893 | * @frontbuffer_bits: frontbuffer plane tracking bits |
169de131 | 894 | * @origin: which operation caused the flush |
b2b89f55 RV |
895 | * |
896 | * Since the hardware frontbuffer tracking has gaps we need to integrate | |
897 | * with the software frontbuffer tracking. This function gets called every | |
898 | * time frontbuffer rendering has completed and flushed out to memory. PSR | |
899 | * can be enabled again if no other frontbuffer relevant to PSR is dirty. | |
900 | * | |
901 | * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. | |
902 | */ | |
5748b6a1 | 903 | void intel_psr_flush(struct drm_i915_private *dev_priv, |
169de131 | 904 | unsigned frontbuffer_bits, enum fb_op_origin origin) |
0bc12bcb | 905 | { |
0bc12bcb RV |
906 | struct drm_crtc *crtc; |
907 | enum pipe pipe; | |
908 | ||
909 | mutex_lock(&dev_priv->psr.lock); | |
910 | if (!dev_priv->psr.enabled) { | |
911 | mutex_unlock(&dev_priv->psr.lock); | |
912 | return; | |
913 | } | |
914 | ||
915 | crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; | |
916 | pipe = to_intel_crtc(crtc)->pipe; | |
ec76d629 DV |
917 | |
918 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); | |
0bc12bcb RV |
919 | dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits; |
920 | ||
921ec285 RV |
921 | /* By definition flush = invalidate + flush */ |
922 | if (frontbuffer_bits) | |
5748b6a1 | 923 | intel_psr_exit(dev_priv); |
995d3047 | 924 | |
0bc12bcb | 925 | if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) |
d0ac896a RV |
926 | if (!work_busy(&dev_priv->psr.work.work)) |
927 | schedule_delayed_work(&dev_priv->psr.work, | |
20bb97fe | 928 | msecs_to_jiffies(100)); |
0bc12bcb RV |
929 | mutex_unlock(&dev_priv->psr.lock); |
930 | } | |
931 | ||
b2b89f55 RV |
932 | /** |
933 | * intel_psr_init - Init basic PSR work and mutex. | |
93de056b | 934 | * @dev_priv: i915 device private |
b2b89f55 RV |
935 | * |
936 | * This function is called only once at driver load to initialize basic | |
937 | * PSR stuff. | |
938 | */ | |
c39055b0 | 939 | void intel_psr_init(struct drm_i915_private *dev_priv) |
0bc12bcb | 940 | { |
443a389f VS |
941 | dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ? |
942 | HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE; | |
943 | ||
2ee7dc49 PZ |
944 | /* Per platform default: all disabled. */ |
945 | if (i915.enable_psr == -1) | |
946 | i915.enable_psr = 0; | |
d94d6e87 | 947 | |
65f61b42 | 948 | /* Set link_standby x link_off defaults */ |
8652744b | 949 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
60e5ffe3 RV |
950 | /* HSW and BDW require workarounds that we don't implement. */ |
951 | dev_priv->psr.link_standby = false; | |
920a14b2 | 952 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
60e5ffe3 RV |
953 | /* On VLV and CHV only standby mode is supported. */ |
954 | dev_priv->psr.link_standby = true; | |
955 | else | |
956 | /* For new platforms let's respect VBT back again */ | |
957 | dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link; | |
958 | ||
65f61b42 RV |
959 | /* Override link_standby x link_off defaults */ |
960 | if (i915.enable_psr == 2 && !dev_priv->psr.link_standby) { | |
961 | DRM_DEBUG_KMS("PSR: Forcing link standby\n"); | |
962 | dev_priv->psr.link_standby = true; | |
963 | } | |
964 | if (i915.enable_psr == 3 && dev_priv->psr.link_standby) { | |
965 | DRM_DEBUG_KMS("PSR: Forcing main link off\n"); | |
966 | dev_priv->psr.link_standby = false; | |
967 | } | |
968 | ||
0bc12bcb RV |
969 | INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work); |
970 | mutex_init(&dev_priv->psr.lock); | |
971 | } |