[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_pm.h

/* SPDX-License-Identifier: MIT */
/*
 * Copyright © 2019 Intel Corporation
 */

#ifndef __INTEL_PM_H__
#define __INTEL_PM_H__

#include <linux/types.h>

#include "display/intel_display.h"
#include "display/intel_global_state.h"

#include "i915_drv.h"

struct drm_device;
struct drm_i915_private;
struct i915_request;
struct intel_atomic_state;
struct intel_bw_state;
struct intel_crtc;
struct intel_crtc_state;
struct intel_plane;
struct skl_ddb_entry;
struct skl_pipe_wm;
struct skl_wm_level;

void intel_init_clock_gating(struct drm_i915_private *dev_priv);
void intel_suspend_hw(struct drm_i915_private *dev_priv);
int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
void intel_init_pm(struct drm_i915_private *dev_priv);
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
void intel_pm_setup(struct drm_i915_private *dev_priv);
void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
void intel_wm_state_verify(struct intel_crtc *crtc,
			   struct intel_crtc_state *new_crtc_state);
u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv);
void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv);
u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,
			    const struct skl_ddb_entry *entry);
void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
void skl_wm_sanitize(struct drm_i915_private *dev_priv);
bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
			   const struct intel_bw_state *bw_state);
void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
void intel_sagv_post_plane_update(struct intel_atomic_state *state);
bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
				 const struct skl_ddb_entry *entries,
				 int num_entries, int ignore_idx);
void skl_write_plane_wm(struct intel_plane *plane,
			const struct intel_crtc_state *crtc_state);
void skl_write_cursor_wm(struct intel_plane *plane,
			 const struct intel_crtc_state *crtc_state);
bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv);
void intel_init_ipc(struct drm_i915_private *dev_priv);
void intel_enable_ipc(struct drm_i915_private *dev_priv);

bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable);

struct intel_dbuf_state {
	struct intel_global_state base;

	struct skl_ddb_entry ddb[I915_MAX_PIPES];
	unsigned int weight[I915_MAX_PIPES];
	u8 slices[I915_MAX_PIPES];
	u8 enabled_slices;
	u8 active_pipes;
	bool joined_mbus;
};

struct intel_dbuf_state *
intel_atomic_get_dbuf_state(struct intel_atomic_state *state);

#define to_intel_dbuf_state(x) container_of((x), struct intel_dbuf_state, base)
#define intel_atomic_get_old_dbuf_state(state) \
	to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->dbuf.obj))
#define intel_atomic_get_new_dbuf_state(state) \
	to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->dbuf.obj))

int intel_dbuf_init(struct drm_i915_private *dev_priv);
void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
void intel_dbuf_post_plane_update(struct intel_atomic_state *state);
void intel_mbus_dbox_update(struct intel_atomic_state *state);

#endif /* __INTEL_PM_H__ */
Commit	Line	Data
696173b0 JN	1	/* SPDX-License-Identifier: MIT */
	2	/*
	3	* Copyright © 2019 Intel Corporation
	4	*/
	5
	6	#ifndef __INTEL_PM_H__
	7	#define __INTEL_PM_H__
	8
	9	#include <linux/types.h>
	10
47a14955	11	#include "display/intel_display.h"
3cf43cdc VS	12	#include "display/intel_global_state.h"
3cf43cdc VS	13
47a14955	14	#include "i915_drv.h"
ecbb5fb7	15
696173b0 JN	16	struct drm_device;
	17	struct drm_i915_private;
	18	struct i915_request;
855e0d68	19	struct intel_atomic_state;
8e6b13a7	20	struct intel_bw_state;
696173b0 JN	21	struct intel_crtc;
	22	struct intel_crtc_state;
	23	struct intel_plane;
696173b0 JN	24	struct skl_ddb_entry;
	25	struct skl_pipe_wm;
	26	struct skl_wm_level;
	27
	28	void intel_init_clock_gating(struct drm_i915_private *dev_priv);
	29	void intel_suspend_hw(struct drm_i915_private *dev_priv);
	30	int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
696173b0 JN	31	void intel_init_pm(struct drm_i915_private *dev_priv);
	32	void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
	33	void intel_pm_setup(struct drm_i915_private *dev_priv);
696173b0 JN	34	void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
	35	void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
	36	void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
	37	void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
88436dec JN	38	void intel_wm_state_verify(struct intel_crtc *crtc,
88436dec JN	39	struct intel_crtc_state *new_crtc_state);
0f0f9aee	40	u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv);
cd191546	41	void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv);
cd191546 SL	42	u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,
cd191546 SL	43	const struct skl_ddb_entry *entry);
696173b0 JN	44	void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
696173b0 JN	45	void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
15512021	46	void skl_wm_sanitize(struct drm_i915_private *dev_priv);
d8d5afe3 SL	47	bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
d8d5afe3 SL	48	const struct intel_bw_state *bw_state);
680e1af7 SL	49	void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
680e1af7 SL	50	void intel_sagv_post_plane_update(struct intel_atomic_state *state);
696173b0 JN	51	bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
	52	const struct skl_ddb_entry *entries,
	53	int num_entries, int ignore_idx);
	54	void skl_write_plane_wm(struct intel_plane *plane,
	55	const struct intel_crtc_state *crtc_state);
	56	void skl_write_cursor_wm(struct intel_plane *plane,
	57	const struct intel_crtc_state *crtc_state);
60aca574	58	bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv);
696173b0 JN	59	void intel_init_ipc(struct drm_i915_private *dev_priv);
	60	void intel_enable_ipc(struct drm_i915_private *dev_priv);
	61
d13616db	62	bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable);
ecbb5fb7	63
3cf43cdc VS	64	struct intel_dbuf_state {
	65	struct intel_global_state base;
	66
47a14955	67	struct skl_ddb_entry ddb[I915_MAX_PIPES];
ef79d62b VS	68	unsigned int weight[I915_MAX_PIPES];
ef79d62b VS	69	u8 slices[I915_MAX_PIPES];
3cf43cdc VS	70	u8 enabled_slices;
3cf43cdc VS	71	u8 active_pipes;
f4dc0086	72	bool joined_mbus;
3cf43cdc VS	73	};
3cf43cdc VS	74
3cf43cdc VS	75	struct intel_dbuf_state *
	76	intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
	77
	78	#define to_intel_dbuf_state(x) container_of((x), struct intel_dbuf_state, base)
	79	#define intel_atomic_get_old_dbuf_state(state) \
	80	to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->dbuf.obj))
	81	#define intel_atomic_get_new_dbuf_state(state) \
	82	to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->dbuf.obj))
	83
	84	int intel_dbuf_init(struct drm_i915_private *dev_priv);
c7c0e7eb VS	85	void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
c7c0e7eb VS	86	void intel_dbuf_post_plane_update(struct intel_atomic_state *state);
47e794d6	87	void intel_mbus_dbox_update(struct intel_atomic_state *state);
3cf43cdc	88
696173b0	89	#endif /* __INTEL_PM_H__ */