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drm/i915: Fold in intel_mst_port_dp_detect
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
dc39fff7
BW		 34/**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51#define INTEL_RC6_ENABLE (1<<0)
52#define INTEL_RC6p_ENABLE (1<<1)
53#define INTEL_RC6pp_ENABLE (1<<2)
54
f6750b3c
ED		 55/* FBC, or Frame Buffer Compression, is a technique employed to compress the
56 * framebuffer contents in-memory, aiming at reducing the required bandwidth
57 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 58 *
f6750b3c
ED		 59 * The benefits of FBC are mostly visible with solid backgrounds and
60 * variation-less patterns.
85208be0 61 *
f6750b3c
ED		 62 * FBC-related functionality can be enabled by the means of the
63 * i915.i915_enable_fbc parameter
85208be0
ED		 64 */
65
da2078cd
DL		 66static void gen9_init_clock_gating(struct drm_device *dev)
67{
acd5c346
DL		 68 struct drm_i915_private *dev_priv = dev->dev_private;
69
70 /*
71 * WaDisableSDEUnitClockGating:skl
72 * This seems to be a pre-production w/a.
73 */
74 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
75 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
91e41d16 76
3ca5da43
DL		 77 /*
78 * WaDisableDgMirrorFixInHalfSliceChicken5:skl
79 * This is a pre-production w/a.
80 */
81 I915_WRITE(GEN9_HALF_SLICE_CHICKEN5,
82 I915_READ(GEN9_HALF_SLICE_CHICKEN5) &
83 ~GEN9_DG_MIRROR_FIX_ENABLE);
84
91e41d16
DL		 85 /* Wa4x4STCOptimizationDisable:skl */
86 I915_WRITE(CACHE_MODE_1,
87 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
da2078cd
DL		 88}
89
1fa61106 90static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 91{
92 struct drm_i915_private *dev_priv = dev->dev_private;
93 u32 fbc_ctl;
94
9adccc60
PZ		 95 dev_priv->fbc.enabled = false;
96
85208be0
ED		 97 /* Disable compression */
98 fbc_ctl = I915_READ(FBC_CONTROL);
99 if ((fbc_ctl & FBC_CTL_EN) == 0)
100 return;
101
102 fbc_ctl &= ~FBC_CTL_EN;
103 I915_WRITE(FBC_CONTROL, fbc_ctl);
104
105 /* Wait for compressing bit to clear */
106 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
107 DRM_DEBUG_KMS("FBC idle timed out\n");
108 return;
109 }
110
111 DRM_DEBUG_KMS("disabled FBC\n");
112}
113
993495ae 114static void i8xx_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 115{
116 struct drm_device *dev = crtc->dev;
117 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 118 struct drm_framebuffer *fb = crtc->primary->fb;
2ff8fde1 119 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
85208be0
ED		 120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
121 int cfb_pitch;
7f2cf220 122 int i;
159f9875 123 u32 fbc_ctl;
85208be0 124
9adccc60
PZ		 125 dev_priv->fbc.enabled = true;
126
5c3fe8b0 127 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
85208be0
ED		 128 if (fb->pitches[0] < cfb_pitch)
129 cfb_pitch = fb->pitches[0];
130
42a430f5
VS		 131 /* FBC_CTL wants 32B or 64B units */
132 if (IS_GEN2(dev))
133 cfb_pitch = (cfb_pitch / 32) - 1;
134 else
135 cfb_pitch = (cfb_pitch / 64) - 1;
85208be0
ED		 136
137 /* Clear old tags */
138 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
139 I915_WRITE(FBC_TAG + (i * 4), 0);
140
159f9875
VS		 141 if (IS_GEN4(dev)) {
142 u32 fbc_ctl2;
143
144 /* Set it up... */
145 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
7f2cf220 146 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
159f9875
VS		 147 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
148 I915_WRITE(FBC_FENCE_OFF, crtc->y);
149 }
85208be0
ED		 150
151 /* enable it... */
993495ae
VS		 152 fbc_ctl = I915_READ(FBC_CONTROL);
153 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
154 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
85208be0
ED		 155 if (IS_I945GM(dev))
156 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
157 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
85208be0
ED		 158 fbc_ctl |= obj->fence_reg;
159 I915_WRITE(FBC_CONTROL, fbc_ctl);
160
5cd5410e 161 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
84f44ce7 162 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 163}
164
1fa61106 165static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 166{
167 struct drm_i915_private *dev_priv = dev->dev_private;
168
169 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
170}
171
993495ae 172static void g4x_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 173{
174 struct drm_device *dev = crtc->dev;
175 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 176 struct drm_framebuffer *fb = crtc->primary->fb;
2ff8fde1 177 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
85208be0 178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85208be0
ED		 179 u32 dpfc_ctl;
180
9adccc60
PZ		 181 dev_priv->fbc.enabled = true;
182
3fa2e0ee
VS		 183 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
184 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
185 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
186 else
187 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
85208be0 188 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
85208be0 189
85208be0
ED		 190 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
191
192 /* enable it... */
fe74c1a5 193 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
85208be0 194
84f44ce7 195 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 196}
197
1fa61106 198static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 199{
200 struct drm_i915_private *dev_priv = dev->dev_private;
201 u32 dpfc_ctl;
202
9adccc60
PZ		 203 dev_priv->fbc.enabled = false;
204
85208be0
ED		 205 /* Disable compression */
206 dpfc_ctl = I915_READ(DPFC_CONTROL);
207 if (dpfc_ctl & DPFC_CTL_EN) {
208 dpfc_ctl &= ~DPFC_CTL_EN;
209 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
210
211 DRM_DEBUG_KMS("disabled FBC\n");
212 }
213}
214
1fa61106 215static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 216{
217 struct drm_i915_private *dev_priv = dev->dev_private;
218
219 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
220}
221
222static void sandybridge_blit_fbc_update(struct drm_device *dev)
223{
224 struct drm_i915_private *dev_priv = dev->dev_private;
225 u32 blt_ecoskpd;
226
227 /* Make sure blitter notifies FBC of writes */
940aece4
D		 228
229 /* Blitter is part of Media powerwell on VLV. No impact of
230 * his param in other platforms for now */
231 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
c8d9a590 232
85208be0
ED		 233 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
234 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
235 GEN6_BLITTER_LOCK_SHIFT;
236 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
237 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
238 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
239 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
240 GEN6_BLITTER_LOCK_SHIFT);
241 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
242 POSTING_READ(GEN6_BLITTER_ECOSKPD);
c8d9a590 243
940aece4 244 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
85208be0
ED		 245}
246
993495ae 247static void ironlake_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 248{
249 struct drm_device *dev = crtc->dev;
250 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 251 struct drm_framebuffer *fb = crtc->primary->fb;
2ff8fde1 252 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
85208be0 253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85208be0
ED		 254 u32 dpfc_ctl;
255
9adccc60
PZ		 256 dev_priv->fbc.enabled = true;
257
46f3dab9 258 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
3fa2e0ee 259 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
5e59f717
BW		 260 dev_priv->fbc.threshold++;
261
262 switch (dev_priv->fbc.threshold) {
263 case 4:
264 case 3:
265 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
266 break;
267 case 2:
3fa2e0ee 268 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
5e59f717
BW		 269 break;
270 case 1:
3fa2e0ee 271 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
5e59f717
BW		 272 break;
273 }
d629336b
VS		 274 dpfc_ctl |= DPFC_CTL_FENCE_EN;
275 if (IS_GEN5(dev))
276 dpfc_ctl |= obj->fence_reg;
85208be0 277
85208be0 278 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
f343c5f6 279 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
85208be0
ED		 280 /* enable it... */
281 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
282
283 if (IS_GEN6(dev)) {
284 I915_WRITE(SNB_DPFC_CTL_SA,
285 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
286 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
287 sandybridge_blit_fbc_update(dev);
288 }
289
84f44ce7 290 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 291}
292
1fa61106 293static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 294{
295 struct drm_i915_private *dev_priv = dev->dev_private;
296 u32 dpfc_ctl;
297
9adccc60
PZ		 298 dev_priv->fbc.enabled = false;
299
85208be0
ED		 300 /* Disable compression */
301 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
302 if (dpfc_ctl & DPFC_CTL_EN) {
303 dpfc_ctl &= ~DPFC_CTL_EN;
304 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
305
306 DRM_DEBUG_KMS("disabled FBC\n");
307 }
308}
309
1fa61106 310static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 311{
312 struct drm_i915_private *dev_priv = dev->dev_private;
313
314 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
315}
316
993495ae 317static void gen7_enable_fbc(struct drm_crtc *crtc)
abe959c7
RV		 318{
319 struct drm_device *dev = crtc->dev;
320 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 321 struct drm_framebuffer *fb = crtc->primary->fb;
2ff8fde1 322 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
abe959c7 323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3fa2e0ee 324 u32 dpfc_ctl;
abe959c7 325
9adccc60
PZ		 326 dev_priv->fbc.enabled = true;
327
3fa2e0ee
VS		 328 dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
329 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
5e59f717
BW		 330 dev_priv->fbc.threshold++;
331
332 switch (dev_priv->fbc.threshold) {
333 case 4:
334 case 3:
335 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
336 break;
337 case 2:
3fa2e0ee 338 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
5e59f717
BW		 339 break;
340 case 1:
3fa2e0ee 341 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
5e59f717
BW		 342 break;
343 }
344
3fa2e0ee
VS		 345 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
346
da46f936
RV		 347 if (dev_priv->fbc.false_color)
348 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
349
3fa2e0ee 350 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
abe959c7 351
891348b2 352 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 353 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
2adb6db8
VS		 354 I915_WRITE(ILK_DISPLAY_CHICKEN1,
355 I915_READ(ILK_DISPLAY_CHICKEN1) |
356 ILK_FBCQ_DIS);
28554164 357 } else {
2adb6db8 358 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
8f670bb1
VS		 359 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
360 I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
361 HSW_FBCQ_DIS);
891348b2 362 }
b74ea102 363
abe959c7
RV		 364 I915_WRITE(SNB_DPFC_CTL_SA,
365 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
366 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
367
368 sandybridge_blit_fbc_update(dev);
369
b19870ee 370 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
abe959c7
RV		 371}
372
85208be0
ED		 373bool intel_fbc_enabled(struct drm_device *dev)
374{
375 struct drm_i915_private *dev_priv = dev->dev_private;
376
9adccc60 377 return dev_priv->fbc.enabled;
85208be0
ED		 378}
379
1d73c2a8 380void bdw_fbc_sw_flush(struct drm_device *dev, u32 value)
c5ad011d
RV		 381{
382 struct drm_i915_private *dev_priv = dev->dev_private;
383
384 if (!IS_GEN8(dev))
385 return;
386
01d06e9f
RV		 387 if (!intel_fbc_enabled(dev))
388 return;
389
c5ad011d
RV		 390 I915_WRITE(MSG_FBC_REND_STATE, value);
391}
392
85208be0
ED		 393static void intel_fbc_work_fn(struct work_struct *__work)
394{
395 struct intel_fbc_work *work =
396 container_of(to_delayed_work(__work),
397 struct intel_fbc_work, work);
398 struct drm_device *dev = work->crtc->dev;
399 struct drm_i915_private *dev_priv = dev->dev_private;
400
401 mutex_lock(&dev->struct_mutex);
5c3fe8b0 402 if (work == dev_priv->fbc.fbc_work) {
85208be0
ED		 403 /* Double check that we haven't switched fb without cancelling
404 * the prior work.
405 */
f4510a27 406 if (work->crtc->primary->fb == work->fb) {
993495ae 407 dev_priv->display.enable_fbc(work->crtc);
85208be0 408
5c3fe8b0 409 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
f4510a27 410 dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
5c3fe8b0 411 dev_priv->fbc.y = work->crtc->y;
85208be0
ED		 412 }
413
5c3fe8b0 414 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 415 }
416 mutex_unlock(&dev->struct_mutex);
417
418 kfree(work);
419}
420
421static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
422{
5c3fe8b0 423 if (dev_priv->fbc.fbc_work == NULL)
85208be0
ED		 424 return;
425
426 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
427
428 /* Synchronisation is provided by struct_mutex and checking of
5c3fe8b0 429 * dev_priv->fbc.fbc_work, so we can perform the cancellation
85208be0
ED		 430 * entirely asynchronously.
431 */
5c3fe8b0 432 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
85208be0 433 /* tasklet was killed before being run, clean up */
5c3fe8b0 434 kfree(dev_priv->fbc.fbc_work);
85208be0
ED		 435
436 /* Mark the work as no longer wanted so that if it does
437 * wake-up (because the work was already running and waiting
438 * for our mutex), it will discover that is no longer
439 * necessary to run.
440 */
5c3fe8b0 441 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 442}
443
993495ae 444static void intel_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 445{
446 struct intel_fbc_work *work;
447 struct drm_device *dev = crtc->dev;
448 struct drm_i915_private *dev_priv = dev->dev_private;
449
450 if (!dev_priv->display.enable_fbc)
451 return;
452
453 intel_cancel_fbc_work(dev_priv);
454
b14c5679 455 work = kzalloc(sizeof(*work), GFP_KERNEL);
85208be0 456 if (work == NULL) {
6cdcb5e7 457 DRM_ERROR("Failed to allocate FBC work structure\n");
993495ae 458 dev_priv->display.enable_fbc(crtc);
85208be0
ED		 459 return;
460 }
461
462 work->crtc = crtc;
f4510a27 463 work->fb = crtc->primary->fb;
85208be0
ED		 464 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
465
5c3fe8b0 466 dev_priv->fbc.fbc_work = work;
85208be0 467
85208be0
ED		 468 /* Delay the actual enabling to let pageflipping cease and the
469 * display to settle before starting the compression. Note that
470 * this delay also serves a second purpose: it allows for a
471 * vblank to pass after disabling the FBC before we attempt
472 * to modify the control registers.
473 *
474 * A more complicated solution would involve tracking vblanks
475 * following the termination of the page-flipping sequence
476 * and indeed performing the enable as a co-routine and not
477 * waiting synchronously upon the vblank.
7457d617
DL		 478 *
479 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
85208be0
ED		 480 */
481 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
482}
483
484void intel_disable_fbc(struct drm_device *dev)
485{
486 struct drm_i915_private *dev_priv = dev->dev_private;
487
488 intel_cancel_fbc_work(dev_priv);
489
490 if (!dev_priv->display.disable_fbc)
491 return;
492
493 dev_priv->display.disable_fbc(dev);
5c3fe8b0 494 dev_priv->fbc.plane = -1;
85208be0
ED		 495}
496
29ebf90f
CW		 497static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
498 enum no_fbc_reason reason)
499{
500 if (dev_priv->fbc.no_fbc_reason == reason)
501 return false;
502
503 dev_priv->fbc.no_fbc_reason = reason;
504 return true;
505}
506
85208be0
ED		 507/**
508 * intel_update_fbc - enable/disable FBC as needed
509 * @dev: the drm_device
510 *
511 * Set up the framebuffer compression hardware at mode set time. We
512 * enable it if possible:
513 * - plane A only (on pre-965)
514 * - no pixel mulitply/line duplication
515 * - no alpha buffer discard
516 * - no dual wide
f85da868 517 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
85208be0
ED		 518 *
519 * We can't assume that any compression will take place (worst case),
520 * so the compressed buffer has to be the same size as the uncompressed
521 * one. It also must reside (along with the line length buffer) in
522 * stolen memory.
523 *
524 * We need to enable/disable FBC on a global basis.
525 */
526void intel_update_fbc(struct drm_device *dev)
527{
528 struct drm_i915_private *dev_priv = dev->dev_private;
529 struct drm_crtc *crtc = NULL, *tmp_crtc;
530 struct intel_crtc *intel_crtc;
531 struct drm_framebuffer *fb;
85208be0 532 struct drm_i915_gem_object *obj;
ef644fda 533 const struct drm_display_mode *adjusted_mode;
37327abd 534 unsigned int max_width, max_height;
85208be0 535
3a77c4c4 536 if (!HAS_FBC(dev)) {
29ebf90f 537 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
85208be0 538 return;
29ebf90f 539 }
85208be0 540
d330a953 541 if (!i915.powersave) {
29ebf90f
CW		 542 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
543 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0 544 return;
29ebf90f 545 }
85208be0
ED		 546
547 /*
548 * If FBC is already on, we just have to verify that we can
549 * keep it that way...
550 * Need to disable if:
551 * - more than one pipe is active
552 * - changing FBC params (stride, fence, mode)
553 * - new fb is too large to fit in compressed buffer
554 * - going to an unsupported config (interlace, pixel multiply, etc.)
555 */
70e1e0ec 556 for_each_crtc(dev, tmp_crtc) {
3490ea5d 557 if (intel_crtc_active(tmp_crtc) &&
4c445e0e 558 to_intel_crtc(tmp_crtc)->primary_enabled) {
85208be0 559 if (crtc) {
29ebf90f
CW		 560 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
561 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
85208be0
ED		 562 goto out_disable;
563 }
564 crtc = tmp_crtc;
565 }
566 }
567
f4510a27 568 if (!crtc || crtc->primary->fb == NULL) {
29ebf90f
CW		 569 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
570 DRM_DEBUG_KMS("no output, disabling\n");
85208be0
ED		 571 goto out_disable;
572 }
573
574 intel_crtc = to_intel_crtc(crtc);
f4510a27 575 fb = crtc->primary->fb;
2ff8fde1 576 obj = intel_fb_obj(fb);
ef644fda 577 adjusted_mode = &intel_crtc->config.adjusted_mode;
85208be0 578
0368920e 579 if (i915.enable_fbc < 0) {
29ebf90f
CW		 580 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
581 DRM_DEBUG_KMS("disabled per chip default\n");
8a5729a3 582 goto out_disable;
85208be0 583 }
d330a953 584 if (!i915.enable_fbc) {
29ebf90f
CW		 585 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
586 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0
ED		 587 goto out_disable;
588 }
ef644fda
VS		 589 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
590 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
29ebf90f
CW		 591 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
592 DRM_DEBUG_KMS("mode incompatible with compression, "
593 "disabling\n");
85208be0
ED		 594 goto out_disable;
595 }
f85da868 596
032843a5
DS		 597 if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) {
598 max_width = 4096;
599 max_height = 4096;
600 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
37327abd
VS		 601 max_width = 4096;
602 max_height = 2048;
f85da868 603 } else {
37327abd
VS		 604 max_width = 2048;
605 max_height = 1536;
f85da868 606 }
37327abd
VS		 607 if (intel_crtc->config.pipe_src_w > max_width ||
608 intel_crtc->config.pipe_src_h > max_height) {
29ebf90f
CW		 609 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
610 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
85208be0
ED		 611 goto out_disable;
612 }
8f94d24b 613 if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
c5a44aa0 614 intel_crtc->plane != PLANE_A) {
29ebf90f 615 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
c5a44aa0 616 DRM_DEBUG_KMS("plane not A, disabling compression\n");
85208be0
ED		 617 goto out_disable;
618 }
619
620 /* The use of a CPU fence is mandatory in order to detect writes
621 * by the CPU to the scanout and trigger updates to the FBC.
622 */
623 if (obj->tiling_mode != I915_TILING_X ||
624 obj->fence_reg == I915_FENCE_REG_NONE) {
29ebf90f
CW		 625 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
626 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
85208be0
ED		 627 goto out_disable;
628 }
48404c1e
SJ		 629 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
630 to_intel_plane(crtc->primary)->rotation != BIT(DRM_ROTATE_0)) {
631 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
632 DRM_DEBUG_KMS("Rotation unsupported, disabling\n");
633 goto out_disable;
634 }
85208be0
ED		 635
636 /* If the kernel debugger is active, always disable compression */
637 if (in_dbg_master())
638 goto out_disable;
639
2ff8fde1 640 if (i915_gem_stolen_setup_compression(dev, obj->base.size,
5e59f717 641 drm_format_plane_cpp(fb->pixel_format, 0))) {
29ebf90f
CW		 642 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
643 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
11be49eb
CW		 644 goto out_disable;
645 }
646
85208be0
ED		 647 /* If the scanout has not changed, don't modify the FBC settings.
648 * Note that we make the fundamental assumption that the fb->obj
649 * cannot be unpinned (and have its GTT offset and fence revoked)
650 * without first being decoupled from the scanout and FBC disabled.
651 */
5c3fe8b0
BW		 652 if (dev_priv->fbc.plane == intel_crtc->plane &&
653 dev_priv->fbc.fb_id == fb->base.id &&
654 dev_priv->fbc.y == crtc->y)
85208be0
ED		 655 return;
656
657 if (intel_fbc_enabled(dev)) {
658 /* We update FBC along two paths, after changing fb/crtc
659 * configuration (modeswitching) and after page-flipping
660 * finishes. For the latter, we know that not only did
661 * we disable the FBC at the start of the page-flip
662 * sequence, but also more than one vblank has passed.
663 *
664 * For the former case of modeswitching, it is possible
665 * to switch between two FBC valid configurations
666 * instantaneously so we do need to disable the FBC
667 * before we can modify its control registers. We also
668 * have to wait for the next vblank for that to take
669 * effect. However, since we delay enabling FBC we can
670 * assume that a vblank has passed since disabling and
671 * that we can safely alter the registers in the deferred
672 * callback.
673 *
674 * In the scenario that we go from a valid to invalid
675 * and then back to valid FBC configuration we have
676 * no strict enforcement that a vblank occurred since
677 * disabling the FBC. However, along all current pipe
678 * disabling paths we do need to wait for a vblank at
679 * some point. And we wait before enabling FBC anyway.
680 */
681 DRM_DEBUG_KMS("disabling active FBC for update\n");
682 intel_disable_fbc(dev);
683 }
684
993495ae 685 intel_enable_fbc(crtc);
29ebf90f 686 dev_priv->fbc.no_fbc_reason = FBC_OK;
85208be0
ED		 687 return;
688
689out_disable:
690 /* Multiple disables should be harmless */
691 if (intel_fbc_enabled(dev)) {
692 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
693 intel_disable_fbc(dev);
694 }
11be49eb 695 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 696}
697
c921aba8
DV		 698static void i915_pineview_get_mem_freq(struct drm_device *dev)
699{
50227e1c 700 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 701 u32 tmp;
702
703 tmp = I915_READ(CLKCFG);
704
705 switch (tmp & CLKCFG_FSB_MASK) {
706 case CLKCFG_FSB_533:
707 dev_priv->fsb_freq = 533; /* 133*4 */
708 break;
709 case CLKCFG_FSB_800:
710 dev_priv->fsb_freq = 800; /* 200*4 */
711 break;
712 case CLKCFG_FSB_667:
713 dev_priv->fsb_freq = 667; /* 167*4 */
714 break;
715 case CLKCFG_FSB_400:
716 dev_priv->fsb_freq = 400; /* 100*4 */
717 break;
718 }
719
720 switch (tmp & CLKCFG_MEM_MASK) {
721 case CLKCFG_MEM_533:
722 dev_priv->mem_freq = 533;
723 break;
724 case CLKCFG_MEM_667:
725 dev_priv->mem_freq = 667;
726 break;
727 case CLKCFG_MEM_800:
728 dev_priv->mem_freq = 800;
729 break;
730 }
731
732 /* detect pineview DDR3 setting */
733 tmp = I915_READ(CSHRDDR3CTL);
734 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
735}
736
737static void i915_ironlake_get_mem_freq(struct drm_device *dev)
738{
50227e1c 739 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 740 u16 ddrpll, csipll;
741
742 ddrpll = I915_READ16(DDRMPLL1);
743 csipll = I915_READ16(CSIPLL0);
744
745 switch (ddrpll & 0xff) {
746 case 0xc:
747 dev_priv->mem_freq = 800;
748 break;
749 case 0x10:
750 dev_priv->mem_freq = 1066;
751 break;
752 case 0x14:
753 dev_priv->mem_freq = 1333;
754 break;
755 case 0x18:
756 dev_priv->mem_freq = 1600;
757 break;
758 default:
759 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
760 ddrpll & 0xff);
761 dev_priv->mem_freq = 0;
762 break;
763 }
764
20e4d407 765 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 766
767 switch (csipll & 0x3ff) {
768 case 0x00c:
769 dev_priv->fsb_freq = 3200;
770 break;
771 case 0x00e:
772 dev_priv->fsb_freq = 3733;
773 break;
774 case 0x010:
775 dev_priv->fsb_freq = 4266;
776 break;
777 case 0x012:
778 dev_priv->fsb_freq = 4800;
779 break;
780 case 0x014:
781 dev_priv->fsb_freq = 5333;
782 break;
783 case 0x016:
784 dev_priv->fsb_freq = 5866;
785 break;
786 case 0x018:
787 dev_priv->fsb_freq = 6400;
788 break;
789 default:
790 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
791 csipll & 0x3ff);
792 dev_priv->fsb_freq = 0;
793 break;
794 }
795
796 if (dev_priv->fsb_freq == 3200) {
20e4d407 797 dev_priv->ips.c_m = 0;
c921aba8 798 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 799 dev_priv->ips.c_m = 1;
c921aba8 800 } else {
20e4d407 801 dev_priv->ips.c_m = 2;
c921aba8
DV		 802 }
803}
804
b445e3b0
ED		 805static const struct cxsr_latency cxsr_latency_table[] = {
806 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
807 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
808 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
809 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
810 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
811
812 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
813 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
814 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
815 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
816 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
817
818 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
819 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
820 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
821 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
822 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
823
824 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
825 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
826 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
827 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
828 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
829
830 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
831 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
832 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
833 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
834 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
835
836 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
837 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
838 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
839 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
840 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
841};
842
63c62275 843static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 844 int is_ddr3,
845 int fsb,
846 int mem)
847{
848 const struct cxsr_latency *latency;
849 int i;
850
851 if (fsb == 0 || mem == 0)
852 return NULL;
853
854 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
855 latency = &cxsr_latency_table[i];
856 if (is_desktop == latency->is_desktop &&
857 is_ddr3 == latency->is_ddr3 &&
858 fsb == latency->fsb_freq && mem == latency->mem_freq)
859 return latency;
860 }
861
862 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
863
864 return NULL;
865}
866
5209b1f4 867void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 868{
5209b1f4
ID		 869 struct drm_device *dev = dev_priv->dev;
870 u32 val;
b445e3b0 871
5209b1f4
ID		 872 if (IS_VALLEYVIEW(dev)) {
873 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
874 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
875 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
876 } else if (IS_PINEVIEW(dev)) {
877 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
878 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
879 I915_WRITE(DSPFW3, val);
880 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
881 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
882 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
883 I915_WRITE(FW_BLC_SELF, val);
884 } else if (IS_I915GM(dev)) {
885 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
886 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
887 I915_WRITE(INSTPM, val);
888 } else {
889 return;
890 }
b445e3b0 891
5209b1f4
ID		 892 DRM_DEBUG_KMS("memory self-refresh is %s\n",
893 enable ? "enabled" : "disabled");
b445e3b0
ED		 894}
895
896/*
897 * Latency for FIFO fetches is dependent on several factors:
898 * - memory configuration (speed, channels)
899 * - chipset
900 * - current MCH state
901 * It can be fairly high in some situations, so here we assume a fairly
902 * pessimal value. It's a tradeoff between extra memory fetches (if we
903 * set this value too high, the FIFO will fetch frequently to stay full)
904 * and power consumption (set it too low to save power and we might see
905 * FIFO underruns and display "flicker").
906 *
907 * A value of 5us seems to be a good balance; safe for very low end
908 * platforms but not overly aggressive on lower latency configs.
909 */
5aef6003 910static const int pessimal_latency_ns = 5000;
b445e3b0 911
1fa61106 912static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 913{
914 struct drm_i915_private *dev_priv = dev->dev_private;
915 uint32_t dsparb = I915_READ(DSPARB);
916 int size;
917
918 size = dsparb & 0x7f;
919 if (plane)
920 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
921
922 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
923 plane ? "B" : "A", size);
924
925 return size;
926}
927
feb56b93 928static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 929{
930 struct drm_i915_private *dev_priv = dev->dev_private;
931 uint32_t dsparb = I915_READ(DSPARB);
932 int size;
933
934 size = dsparb & 0x1ff;
935 if (plane)
936 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
937 size >>= 1; /* Convert to cachelines */
938
939 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
940 plane ? "B" : "A", size);
941
942 return size;
943}
944
1fa61106 945static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 946{
947 struct drm_i915_private *dev_priv = dev->dev_private;
948 uint32_t dsparb = I915_READ(DSPARB);
949 int size;
950
951 size = dsparb & 0x7f;
952 size >>= 2; /* Convert to cachelines */
953
954 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
955 plane ? "B" : "A",
956 size);
957
958 return size;
959}
960
b445e3b0
ED		 961/* Pineview has different values for various configs */
962static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 963 .fifo_size = PINEVIEW_DISPLAY_FIFO,
964 .max_wm = PINEVIEW_MAX_WM,
965 .default_wm = PINEVIEW_DFT_WM,
966 .guard_size = PINEVIEW_GUARD_WM,
967 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 968};
969static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 970 .fifo_size = PINEVIEW_DISPLAY_FIFO,
971 .max_wm = PINEVIEW_MAX_WM,
972 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
973 .guard_size = PINEVIEW_GUARD_WM,
974 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 975};
976static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 977 .fifo_size = PINEVIEW_CURSOR_FIFO,
978 .max_wm = PINEVIEW_CURSOR_MAX_WM,
979 .default_wm = PINEVIEW_CURSOR_DFT_WM,
980 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
981 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 982};
983static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 984 .fifo_size = PINEVIEW_CURSOR_FIFO,
985 .max_wm = PINEVIEW_CURSOR_MAX_WM,
986 .default_wm = PINEVIEW_CURSOR_DFT_WM,
987 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
988 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 989};
990static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 991 .fifo_size = G4X_FIFO_SIZE,
992 .max_wm = G4X_MAX_WM,
993 .default_wm = G4X_MAX_WM,
994 .guard_size = 2,
995 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 996};
997static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 998 .fifo_size = I965_CURSOR_FIFO,
999 .max_wm = I965_CURSOR_MAX_WM,
1000 .default_wm = I965_CURSOR_DFT_WM,
1001 .guard_size = 2,
1002 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 1003};
1004static const struct intel_watermark_params valleyview_wm_info = {
e0f0273e
VS		 1005 .fifo_size = VALLEYVIEW_FIFO_SIZE,
1006 .max_wm = VALLEYVIEW_MAX_WM,
1007 .default_wm = VALLEYVIEW_MAX_WM,
1008 .guard_size = 2,
1009 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 1010};
1011static const struct intel_watermark_params valleyview_cursor_wm_info = {
e0f0273e
VS		 1012 .fifo_size = I965_CURSOR_FIFO,
1013 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
1014 .default_wm = I965_CURSOR_DFT_WM,
1015 .guard_size = 2,
1016 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 1017};
1018static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 1019 .fifo_size = I965_CURSOR_FIFO,
1020 .max_wm = I965_CURSOR_MAX_WM,
1021 .default_wm = I965_CURSOR_DFT_WM,
1022 .guard_size = 2,
1023 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 1024};
1025static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 1026 .fifo_size = I945_FIFO_SIZE,
1027 .max_wm = I915_MAX_WM,
1028 .default_wm = 1,
1029 .guard_size = 2,
1030 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 1031};
1032static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 1033 .fifo_size = I915_FIFO_SIZE,
1034 .max_wm = I915_MAX_WM,
1035 .default_wm = 1,
1036 .guard_size = 2,
1037 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 1038};
9d539105 1039static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 1040 .fifo_size = I855GM_FIFO_SIZE,
1041 .max_wm = I915_MAX_WM,
1042 .default_wm = 1,
1043 .guard_size = 2,
1044 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 1045};
9d539105
VS		 1046static const struct intel_watermark_params i830_bc_wm_info = {
1047 .fifo_size = I855GM_FIFO_SIZE,
1048 .max_wm = I915_MAX_WM/2,
1049 .default_wm = 1,
1050 .guard_size = 2,
1051 .cacheline_size = I830_FIFO_LINE_SIZE,
1052};
feb56b93 1053static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 1054 .fifo_size = I830_FIFO_SIZE,
1055 .max_wm = I915_MAX_WM,
1056 .default_wm = 1,
1057 .guard_size = 2,
1058 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 1059};
1060
b445e3b0
ED		 1061/**
1062 * intel_calculate_wm - calculate watermark level
1063 * @clock_in_khz: pixel clock
1064 * @wm: chip FIFO params
1065 * @pixel_size: display pixel size
1066 * @latency_ns: memory latency for the platform
1067 *
1068 * Calculate the watermark level (the level at which the display plane will
1069 * start fetching from memory again). Each chip has a different display
1070 * FIFO size and allocation, so the caller needs to figure that out and pass
1071 * in the correct intel_watermark_params structure.
1072 *
1073 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1074 * on the pixel size. When it reaches the watermark level, it'll start
1075 * fetching FIFO line sized based chunks from memory until the FIFO fills
1076 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1077 * will occur, and a display engine hang could result.
1078 */
1079static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1080 const struct intel_watermark_params *wm,
1081 int fifo_size,
1082 int pixel_size,
1083 unsigned long latency_ns)
1084{
1085 long entries_required, wm_size;
1086
1087 /*
1088 * Note: we need to make sure we don't overflow for various clock &
1089 * latency values.
1090 * clocks go from a few thousand to several hundred thousand.
1091 * latency is usually a few thousand
1092 */
1093 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1094 1000;
1095 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1096
1097 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1098
1099 wm_size = fifo_size - (entries_required + wm->guard_size);
1100
1101 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1102
1103 /* Don't promote wm_size to unsigned... */
1104 if (wm_size > (long)wm->max_wm)
1105 wm_size = wm->max_wm;
1106 if (wm_size <= 0)
1107 wm_size = wm->default_wm;
d6feb196
VS		 1108
1109 /*
1110 * Bspec seems to indicate that the value shouldn't be lower than
1111 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
1112 * Lets go for 8 which is the burst size since certain platforms
1113 * already use a hardcoded 8 (which is what the spec says should be
1114 * done).
1115 */
1116 if (wm_size <= 8)
1117 wm_size = 8;
1118
b445e3b0
ED		 1119 return wm_size;
1120}
1121
1122static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1123{
1124 struct drm_crtc *crtc, *enabled = NULL;
1125
70e1e0ec 1126 for_each_crtc(dev, crtc) {
3490ea5d 1127 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1128 if (enabled)
1129 return NULL;
1130 enabled = crtc;
1131 }
1132 }
1133
1134 return enabled;
1135}
1136
46ba614c 1137static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1138{
46ba614c 1139 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1140 struct drm_i915_private *dev_priv = dev->dev_private;
1141 struct drm_crtc *crtc;
1142 const struct cxsr_latency *latency;
1143 u32 reg;
1144 unsigned long wm;
1145
1146 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1147 dev_priv->fsb_freq, dev_priv->mem_freq);
1148 if (!latency) {
1149 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 1150 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1151 return;
1152 }
1153
1154 crtc = single_enabled_crtc(dev);
1155 if (crtc) {
241bfc38 1156 const struct drm_display_mode *adjusted_mode;
f4510a27 1157 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
241bfc38
DL		 1158 int clock;
1159
1160 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1161 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 1162
1163 /* Display SR */
1164 wm = intel_calculate_wm(clock, &pineview_display_wm,
1165 pineview_display_wm.fifo_size,
1166 pixel_size, latency->display_sr);
1167 reg = I915_READ(DSPFW1);
1168 reg &= ~DSPFW_SR_MASK;
1169 reg |= wm << DSPFW_SR_SHIFT;
1170 I915_WRITE(DSPFW1, reg);
1171 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1172
1173 /* cursor SR */
1174 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1175 pineview_display_wm.fifo_size,
1176 pixel_size, latency->cursor_sr);
1177 reg = I915_READ(DSPFW3);
1178 reg &= ~DSPFW_CURSOR_SR_MASK;
1179 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1180 I915_WRITE(DSPFW3, reg);
1181
1182 /* Display HPLL off SR */
1183 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1184 pineview_display_hplloff_wm.fifo_size,
1185 pixel_size, latency->display_hpll_disable);
1186 reg = I915_READ(DSPFW3);
1187 reg &= ~DSPFW_HPLL_SR_MASK;
1188 reg |= wm & DSPFW_HPLL_SR_MASK;
1189 I915_WRITE(DSPFW3, reg);
1190
1191 /* cursor HPLL off SR */
1192 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1193 pineview_display_hplloff_wm.fifo_size,
1194 pixel_size, latency->cursor_hpll_disable);
1195 reg = I915_READ(DSPFW3);
1196 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1197 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1198 I915_WRITE(DSPFW3, reg);
1199 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1200
5209b1f4 1201 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 1202 } else {
5209b1f4 1203 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1204 }
1205}
1206
1207static bool g4x_compute_wm0(struct drm_device *dev,
1208 int plane,
1209 const struct intel_watermark_params *display,
1210 int display_latency_ns,
1211 const struct intel_watermark_params *cursor,
1212 int cursor_latency_ns,
1213 int *plane_wm,
1214 int *cursor_wm)
1215{
1216 struct drm_crtc *crtc;
4fe8590a 1217 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1218 int htotal, hdisplay, clock, pixel_size;
1219 int line_time_us, line_count;
1220 int entries, tlb_miss;
1221
1222 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1223 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1224 *cursor_wm = cursor->guard_size;
1225 *plane_wm = display->guard_size;
1226 return false;
1227 }
1228
4fe8590a 1229 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1230 clock = adjusted_mode->crtc_clock;
fec8cba3 1231 htotal = adjusted_mode->crtc_htotal;
37327abd 1232 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1233 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1234
1235 /* Use the small buffer method to calculate plane watermark */
1236 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1237 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1238 if (tlb_miss > 0)
1239 entries += tlb_miss;
1240 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1241 *plane_wm = entries + display->guard_size;
1242 if (*plane_wm > (int)display->max_wm)
1243 *plane_wm = display->max_wm;
1244
1245 /* Use the large buffer method to calculate cursor watermark */
922044c9 1246 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 1247 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
7bb836dd 1248 entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
b445e3b0
ED		 1249 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1250 if (tlb_miss > 0)
1251 entries += tlb_miss;
1252 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1253 *cursor_wm = entries + cursor->guard_size;
1254 if (*cursor_wm > (int)cursor->max_wm)
1255 *cursor_wm = (int)cursor->max_wm;
1256
1257 return true;
1258}
1259
1260/*
1261 * Check the wm result.
1262 *
1263 * If any calculated watermark values is larger than the maximum value that
1264 * can be programmed into the associated watermark register, that watermark
1265 * must be disabled.
1266 */
1267static bool g4x_check_srwm(struct drm_device *dev,
1268 int display_wm, int cursor_wm,
1269 const struct intel_watermark_params *display,
1270 const struct intel_watermark_params *cursor)
1271{
1272 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1273 display_wm, cursor_wm);
1274
1275 if (display_wm > display->max_wm) {
1276 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1277 display_wm, display->max_wm);
1278 return false;
1279 }
1280
1281 if (cursor_wm > cursor->max_wm) {
1282 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1283 cursor_wm, cursor->max_wm);
1284 return false;
1285 }
1286
1287 if (!(display_wm || cursor_wm)) {
1288 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1289 return false;
1290 }
1291
1292 return true;
1293}
1294
1295static bool g4x_compute_srwm(struct drm_device *dev,
1296 int plane,
1297 int latency_ns,
1298 const struct intel_watermark_params *display,
1299 const struct intel_watermark_params *cursor,
1300 int *display_wm, int *cursor_wm)
1301{
1302 struct drm_crtc *crtc;
4fe8590a 1303 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1304 int hdisplay, htotal, pixel_size, clock;
1305 unsigned long line_time_us;
1306 int line_count, line_size;
1307 int small, large;
1308 int entries;
1309
1310 if (!latency_ns) {
1311 *display_wm = *cursor_wm = 0;
1312 return false;
1313 }
1314
1315 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a 1316 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1317 clock = adjusted_mode->crtc_clock;
fec8cba3 1318 htotal = adjusted_mode->crtc_htotal;
37327abd 1319 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1320 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0 1321
922044c9 1322 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1323 line_count = (latency_ns / line_time_us + 1000) / 1000;
1324 line_size = hdisplay * pixel_size;
1325
1326 /* Use the minimum of the small and large buffer method for primary */
1327 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1328 large = line_count * line_size;
1329
1330 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1331 *display_wm = entries + display->guard_size;
1332
1333 /* calculate the self-refresh watermark for display cursor */
7bb836dd 1334 entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
b445e3b0
ED		 1335 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1336 *cursor_wm = entries + cursor->guard_size;
1337
1338 return g4x_check_srwm(dev,
1339 *display_wm, *cursor_wm,
1340 display, cursor);
1341}
1342
0948c265
GB		 1343static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
1344 int pixel_size,
1345 int *prec_mult,
1346 int *drain_latency)
b445e3b0 1347{
b445e3b0 1348 int entries;
0948c265 1349 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
b445e3b0 1350
0948c265 1351 if (WARN(clock == 0, "Pixel clock is zero!\n"))
b445e3b0
ED		 1352 return false;
1353
0948c265
GB		 1354 if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
1355 return false;
b445e3b0 1356
a398e9c7 1357 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
0948c265
GB		 1358 *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 :
1359 DRAIN_LATENCY_PRECISION_32;
1360 *drain_latency = (64 * (*prec_mult) * 4) / entries;
b445e3b0 1361
a398e9c7
GB		 1362 if (*drain_latency > DRAIN_LATENCY_MASK)
1363 *drain_latency = DRAIN_LATENCY_MASK;
b445e3b0
ED		 1364
1365 return true;
1366}
1367
1368/*
1369 * Update drain latency registers of memory arbiter
1370 *
1371 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1372 * to be programmed. Each plane has a drain latency multiplier and a drain
1373 * latency value.
1374 */
1375
41aad816 1376static void vlv_update_drain_latency(struct drm_crtc *crtc)
b445e3b0 1377{
0948c265
GB		 1378 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1379 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1380 int pixel_size;
1381 int drain_latency;
1382 enum pipe pipe = intel_crtc->pipe;
1383 int plane_prec, prec_mult, plane_dl;
b445e3b0 1384
0948c265
GB		 1385 plane_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_64 |
1386 DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_64 |
1387 (DRAIN_LATENCY_MASK << DDL_CURSOR_SHIFT));
1388
1389 if (!intel_crtc_active(crtc)) {
1390 I915_WRITE(VLV_DDL(pipe), plane_dl);
1391 return;
1392 }
b445e3b0 1393
0948c265
GB		 1394 /* Primary plane Drain Latency */
1395 pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
1396 if (vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
1397 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1398 DDL_PLANE_PRECISION_64 :
1399 DDL_PLANE_PRECISION_32;
1400 plane_dl |= plane_prec | drain_latency;
b445e3b0
ED		 1401 }
1402
0948c265
GB		 1403 /* Cursor Drain Latency
1404 * BPP is always 4 for cursor
1405 */
1406 pixel_size = 4;
b445e3b0 1407
0948c265
GB		 1408 /* Program cursor DL only if it is enabled */
1409 if (intel_crtc->cursor_base &&
1410 vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
1411 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1412 DDL_CURSOR_PRECISION_64 :
1413 DDL_CURSOR_PRECISION_32;
1414 plane_dl |= plane_prec | (drain_latency << DDL_CURSOR_SHIFT);
b445e3b0 1415 }
0948c265
GB		 1416
1417 I915_WRITE(VLV_DDL(pipe), plane_dl);
b445e3b0
ED		 1418}
1419
1420#define single_plane_enabled(mask) is_power_of_2(mask)
1421
46ba614c 1422static void valleyview_update_wm(struct drm_crtc *crtc)
b445e3b0 1423{
46ba614c 1424 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1425 static const int sr_latency_ns = 12000;
1426 struct drm_i915_private *dev_priv = dev->dev_private;
1427 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1428 int plane_sr, cursor_sr;
af6c4575 1429 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0 1430 unsigned int enabled = 0;
9858425c 1431 bool cxsr_enabled;
b445e3b0 1432
41aad816 1433 vlv_update_drain_latency(crtc);
b445e3b0 1434
51cea1f4 1435 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1436 &valleyview_wm_info, pessimal_latency_ns,
1437 &valleyview_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1438 &planea_wm, &cursora_wm))
51cea1f4 1439 enabled |= 1 << PIPE_A;
b445e3b0 1440
51cea1f4 1441 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1442 &valleyview_wm_info, pessimal_latency_ns,
1443 &valleyview_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1444 &planeb_wm, &cursorb_wm))
51cea1f4 1445 enabled |= 1 << PIPE_B;
b445e3b0 1446
b445e3b0
ED		 1447 if (single_plane_enabled(enabled) &&
1448 g4x_compute_srwm(dev, ffs(enabled) - 1,
1449 sr_latency_ns,
1450 &valleyview_wm_info,
1451 &valleyview_cursor_wm_info,
af6c4575
CW		 1452 &plane_sr, &ignore_cursor_sr) &&
1453 g4x_compute_srwm(dev, ffs(enabled) - 1,
1454 2*sr_latency_ns,
1455 &valleyview_wm_info,
1456 &valleyview_cursor_wm_info,
52bd02d8 1457 &ignore_plane_sr, &cursor_sr)) {
9858425c 1458 cxsr_enabled = true;
52bd02d8 1459 } else {
9858425c 1460 cxsr_enabled = false;
5209b1f4 1461 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1462 plane_sr = cursor_sr = 0;
1463 }
b445e3b0 1464
a5043453
VS		 1465 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1466 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1467 planea_wm, cursora_wm,
1468 planeb_wm, cursorb_wm,
1469 plane_sr, cursor_sr);
1470
1471 I915_WRITE(DSPFW1,
1472 (plane_sr << DSPFW_SR_SHIFT) |
1473 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1474 (planeb_wm << DSPFW_PLANEB_SHIFT) |
0a560674 1475 (planea_wm << DSPFW_PLANEA_SHIFT));
b445e3b0 1476 I915_WRITE(DSPFW2,
8c919b28 1477 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1478 (cursora_wm << DSPFW_CURSORA_SHIFT));
1479 I915_WRITE(DSPFW3,
8c919b28
CW		 1480 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1481 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
9858425c
ID		 1482
1483 if (cxsr_enabled)
1484 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1485}
1486
3c2777fd
VS		 1487static void cherryview_update_wm(struct drm_crtc *crtc)
1488{
1489 struct drm_device *dev = crtc->dev;
1490 static const int sr_latency_ns = 12000;
1491 struct drm_i915_private *dev_priv = dev->dev_private;
1492 int planea_wm, planeb_wm, planec_wm;
1493 int cursora_wm, cursorb_wm, cursorc_wm;
1494 int plane_sr, cursor_sr;
1495 int ignore_plane_sr, ignore_cursor_sr;
1496 unsigned int enabled = 0;
1497 bool cxsr_enabled;
1498
1499 vlv_update_drain_latency(crtc);
1500
1501 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1502 &valleyview_wm_info, pessimal_latency_ns,
1503 &valleyview_cursor_wm_info, pessimal_latency_ns,
3c2777fd
VS		 1504 &planea_wm, &cursora_wm))
1505 enabled |= 1 << PIPE_A;
1506
1507 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1508 &valleyview_wm_info, pessimal_latency_ns,
1509 &valleyview_cursor_wm_info, pessimal_latency_ns,
3c2777fd
VS		 1510 &planeb_wm, &cursorb_wm))
1511 enabled |= 1 << PIPE_B;
1512
1513 if (g4x_compute_wm0(dev, PIPE_C,
5aef6003
CW		 1514 &valleyview_wm_info, pessimal_latency_ns,
1515 &valleyview_cursor_wm_info, pessimal_latency_ns,
3c2777fd
VS		 1516 &planec_wm, &cursorc_wm))
1517 enabled |= 1 << PIPE_C;
1518
1519 if (single_plane_enabled(enabled) &&
1520 g4x_compute_srwm(dev, ffs(enabled) - 1,
1521 sr_latency_ns,
1522 &valleyview_wm_info,
1523 &valleyview_cursor_wm_info,
1524 &plane_sr, &ignore_cursor_sr) &&
1525 g4x_compute_srwm(dev, ffs(enabled) - 1,
1526 2*sr_latency_ns,
1527 &valleyview_wm_info,
1528 &valleyview_cursor_wm_info,
1529 &ignore_plane_sr, &cursor_sr)) {
1530 cxsr_enabled = true;
1531 } else {
1532 cxsr_enabled = false;
1533 intel_set_memory_cxsr(dev_priv, false);
1534 plane_sr = cursor_sr = 0;
1535 }
1536
1537 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1538 "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, "
1539 "SR: plane=%d, cursor=%d\n",
1540 planea_wm, cursora_wm,
1541 planeb_wm, cursorb_wm,
1542 planec_wm, cursorc_wm,
1543 plane_sr, cursor_sr);
1544
1545 I915_WRITE(DSPFW1,
1546 (plane_sr << DSPFW_SR_SHIFT) |
1547 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1548 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1549 (planea_wm << DSPFW_PLANEA_SHIFT));
1550 I915_WRITE(DSPFW2,
1551 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1552 (cursora_wm << DSPFW_CURSORA_SHIFT));
1553 I915_WRITE(DSPFW3,
1554 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1555 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1556 I915_WRITE(DSPFW9_CHV,
1557 (I915_READ(DSPFW9_CHV) & ~(DSPFW_PLANEC_MASK |
1558 DSPFW_CURSORC_MASK)) |
1559 (planec_wm << DSPFW_PLANEC_SHIFT) |
1560 (cursorc_wm << DSPFW_CURSORC_SHIFT));
1561
1562 if (cxsr_enabled)
1563 intel_set_memory_cxsr(dev_priv, true);
1564}
1565
01e184cc
GB		 1566static void valleyview_update_sprite_wm(struct drm_plane *plane,
1567 struct drm_crtc *crtc,
1568 uint32_t sprite_width,
1569 uint32_t sprite_height,
1570 int pixel_size,
1571 bool enabled, bool scaled)
1572{
1573 struct drm_device *dev = crtc->dev;
1574 struct drm_i915_private *dev_priv = dev->dev_private;
1575 int pipe = to_intel_plane(plane)->pipe;
1576 int sprite = to_intel_plane(plane)->plane;
1577 int drain_latency;
1578 int plane_prec;
1579 int sprite_dl;
1580 int prec_mult;
1581
1582 sprite_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_SPRITE_PRECISION_64(sprite) |
1583 (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite)));
1584
1585 if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult,
1586 &drain_latency)) {
1587 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1588 DDL_SPRITE_PRECISION_64(sprite) :
1589 DDL_SPRITE_PRECISION_32(sprite);
1590 sprite_dl |= plane_prec |
1591 (drain_latency << DDL_SPRITE_SHIFT(sprite));
1592 }
1593
1594 I915_WRITE(VLV_DDL(pipe), sprite_dl);
1595}
1596
46ba614c 1597static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1598{
46ba614c 1599 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1600 static const int sr_latency_ns = 12000;
1601 struct drm_i915_private *dev_priv = dev->dev_private;
1602 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1603 int plane_sr, cursor_sr;
1604 unsigned int enabled = 0;
9858425c 1605 bool cxsr_enabled;
b445e3b0 1606
51cea1f4 1607 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1608 &g4x_wm_info, pessimal_latency_ns,
1609 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1610 &planea_wm, &cursora_wm))
51cea1f4 1611 enabled |= 1 << PIPE_A;
b445e3b0 1612
51cea1f4 1613 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1614 &g4x_wm_info, pessimal_latency_ns,
1615 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1616 &planeb_wm, &cursorb_wm))
51cea1f4 1617 enabled |= 1 << PIPE_B;
b445e3b0 1618
b445e3b0
ED		 1619 if (single_plane_enabled(enabled) &&
1620 g4x_compute_srwm(dev, ffs(enabled) - 1,
1621 sr_latency_ns,
1622 &g4x_wm_info,
1623 &g4x_cursor_wm_info,
52bd02d8 1624 &plane_sr, &cursor_sr)) {
9858425c 1625 cxsr_enabled = true;
52bd02d8 1626 } else {
9858425c 1627 cxsr_enabled = false;
5209b1f4 1628 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1629 plane_sr = cursor_sr = 0;
1630 }
b445e3b0 1631
a5043453
VS		 1632 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1633 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1634 planea_wm, cursora_wm,
1635 planeb_wm, cursorb_wm,
1636 plane_sr, cursor_sr);
1637
1638 I915_WRITE(DSPFW1,
1639 (plane_sr << DSPFW_SR_SHIFT) |
1640 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1641 (planeb_wm << DSPFW_PLANEB_SHIFT) |
0a560674 1642 (planea_wm << DSPFW_PLANEA_SHIFT));
b445e3b0 1643 I915_WRITE(DSPFW2,
8c919b28 1644 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1645 (cursora_wm << DSPFW_CURSORA_SHIFT));
1646 /* HPLL off in SR has some issues on G4x... disable it */
1647 I915_WRITE(DSPFW3,
8c919b28 1648 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0 1649 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
9858425c
ID		 1650
1651 if (cxsr_enabled)
1652 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1653}
1654
46ba614c 1655static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1656{
46ba614c 1657 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1658 struct drm_i915_private *dev_priv = dev->dev_private;
1659 struct drm_crtc *crtc;
1660 int srwm = 1;
1661 int cursor_sr = 16;
9858425c 1662 bool cxsr_enabled;
b445e3b0
ED		 1663
1664 /* Calc sr entries for one plane configs */
1665 crtc = single_enabled_crtc(dev);
1666 if (crtc) {
1667 /* self-refresh has much higher latency */
1668 static const int sr_latency_ns = 12000;
4fe8590a
VS		 1669 const struct drm_display_mode *adjusted_mode =
1670 &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1671 int clock = adjusted_mode->crtc_clock;
fec8cba3 1672 int htotal = adjusted_mode->crtc_htotal;
37327abd 1673 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1674 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1675 unsigned long line_time_us;
1676 int entries;
1677
922044c9 1678 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1679
1680 /* Use ns/us then divide to preserve precision */
1681 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1682 pixel_size * hdisplay;
1683 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1684 srwm = I965_FIFO_SIZE - entries;
1685 if (srwm < 0)
1686 srwm = 1;
1687 srwm &= 0x1ff;
1688 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1689 entries, srwm);
1690
1691 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
7bb836dd 1692 pixel_size * to_intel_crtc(crtc)->cursor_width;
b445e3b0
ED		 1693 entries = DIV_ROUND_UP(entries,
1694 i965_cursor_wm_info.cacheline_size);
1695 cursor_sr = i965_cursor_wm_info.fifo_size -
1696 (entries + i965_cursor_wm_info.guard_size);
1697
1698 if (cursor_sr > i965_cursor_wm_info.max_wm)
1699 cursor_sr = i965_cursor_wm_info.max_wm;
1700
1701 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1702 "cursor %d\n", srwm, cursor_sr);
1703
9858425c 1704 cxsr_enabled = true;
b445e3b0 1705 } else {
9858425c 1706 cxsr_enabled = false;
b445e3b0 1707 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1708 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1709 }
1710
1711 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1712 srwm);
1713
1714 /* 965 has limitations... */
1715 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
0a560674
VS		 1716 (8 << DSPFW_CURSORB_SHIFT) |
1717 (8 << DSPFW_PLANEB_SHIFT) |
1718 (8 << DSPFW_PLANEA_SHIFT));
1719 I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) |
1720 (8 << DSPFW_PLANEC_SHIFT_OLD));
b445e3b0
ED		 1721 /* update cursor SR watermark */
1722 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
9858425c
ID		 1723
1724 if (cxsr_enabled)
1725 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1726}
1727
46ba614c 1728static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1729{
46ba614c 1730 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1731 struct drm_i915_private *dev_priv = dev->dev_private;
1732 const struct intel_watermark_params *wm_info;
1733 uint32_t fwater_lo;
1734 uint32_t fwater_hi;
1735 int cwm, srwm = 1;
1736 int fifo_size;
1737 int planea_wm, planeb_wm;
1738 struct drm_crtc *crtc, *enabled = NULL;
1739
1740 if (IS_I945GM(dev))
1741 wm_info = &i945_wm_info;
1742 else if (!IS_GEN2(dev))
1743 wm_info = &i915_wm_info;
1744 else
9d539105 1745 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1746
1747 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1748 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1749 if (intel_crtc_active(crtc)) {
241bfc38 1750 const struct drm_display_mode *adjusted_mode;
f4510a27 1751 int cpp = crtc->primary->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1752 if (IS_GEN2(dev))
1753 cpp = 4;
1754
241bfc38
DL		 1755 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1756 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1757 wm_info, fifo_size, cpp,
5aef6003 1758 pessimal_latency_ns);
b445e3b0 1759 enabled = crtc;
9d539105 1760 } else {
b445e3b0 1761 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1762 if (planea_wm > (long)wm_info->max_wm)
1763 planea_wm = wm_info->max_wm;
1764 }
1765
1766 if (IS_GEN2(dev))
1767 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1768
1769 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1770 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1771 if (intel_crtc_active(crtc)) {
241bfc38 1772 const struct drm_display_mode *adjusted_mode;
f4510a27 1773 int cpp = crtc->primary->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1774 if (IS_GEN2(dev))
1775 cpp = 4;
1776
241bfc38
DL		 1777 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1778 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1779 wm_info, fifo_size, cpp,
5aef6003 1780 pessimal_latency_ns);
b445e3b0
ED		 1781 if (enabled == NULL)
1782 enabled = crtc;
1783 else
1784 enabled = NULL;
9d539105 1785 } else {
b445e3b0 1786 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1787 if (planeb_wm > (long)wm_info->max_wm)
1788 planeb_wm = wm_info->max_wm;
1789 }
b445e3b0
ED		 1790
1791 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1792
2ab1bc9d 1793 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1794 struct drm_i915_gem_object *obj;
2ab1bc9d 1795
2ff8fde1 1796 obj = intel_fb_obj(enabled->primary->fb);
2ab1bc9d
DV		 1797
1798 /* self-refresh seems busted with untiled */
2ff8fde1 1799 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1800 enabled = NULL;
1801 }
1802
b445e3b0
ED		 1803 /*
1804 * Overlay gets an aggressive default since video jitter is bad.
1805 */
1806 cwm = 2;
1807
1808 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1809 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1810
1811 /* Calc sr entries for one plane configs */
1812 if (HAS_FW_BLC(dev) && enabled) {
1813 /* self-refresh has much higher latency */
1814 static const int sr_latency_ns = 6000;
4fe8590a
VS		 1815 const struct drm_display_mode *adjusted_mode =
1816 &to_intel_crtc(enabled)->config.adjusted_mode;
241bfc38 1817 int clock = adjusted_mode->crtc_clock;
fec8cba3 1818 int htotal = adjusted_mode->crtc_htotal;
f727b490 1819 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
f4510a27 1820 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1821 unsigned long line_time_us;
1822 int entries;
1823
922044c9 1824 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1825
1826 /* Use ns/us then divide to preserve precision */
1827 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1828 pixel_size * hdisplay;
1829 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1830 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1831 srwm = wm_info->fifo_size - entries;
1832 if (srwm < 0)
1833 srwm = 1;
1834
1835 if (IS_I945G(dev) || IS_I945GM(dev))
1836 I915_WRITE(FW_BLC_SELF,
1837 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1838 else if (IS_I915GM(dev))
1839 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1840 }
1841
1842 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1843 planea_wm, planeb_wm, cwm, srwm);
1844
1845 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1846 fwater_hi = (cwm & 0x1f);
1847
1848 /* Set request length to 8 cachelines per fetch */
1849 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1850 fwater_hi = fwater_hi | (1 << 8);
1851
1852 I915_WRITE(FW_BLC, fwater_lo);
1853 I915_WRITE(FW_BLC2, fwater_hi);
1854
5209b1f4
ID		 1855 if (enabled)
1856 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1857}
1858
feb56b93 1859static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1860{
46ba614c 1861 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1862 struct drm_i915_private *dev_priv = dev->dev_private;
1863 struct drm_crtc *crtc;
241bfc38 1864 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1865 uint32_t fwater_lo;
1866 int planea_wm;
1867
1868 crtc = single_enabled_crtc(dev);
1869 if (crtc == NULL)
1870 return;
1871
241bfc38
DL		 1872 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1873 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1874 &i845_wm_info,
b445e3b0 1875 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1876 4, pessimal_latency_ns);
b445e3b0
ED		 1877 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1878 fwater_lo |= (3<<8) | planea_wm;
1879
1880 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1881
1882 I915_WRITE(FW_BLC, fwater_lo);
1883}
1884
3658729a
VS		 1885static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1886 struct drm_crtc *crtc)
801bcfff
PZ		 1887{
1888 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fd4daa9c 1889 uint32_t pixel_rate;
801bcfff 1890
241bfc38 1891 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
801bcfff
PZ		 1892
1893 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1894 * adjust the pixel_rate here. */
1895
fd4daa9c 1896 if (intel_crtc->config.pch_pfit.enabled) {
801bcfff 1897 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
fd4daa9c 1898 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
801bcfff 1899
37327abd
VS		 1900 pipe_w = intel_crtc->config.pipe_src_w;
1901 pipe_h = intel_crtc->config.pipe_src_h;
801bcfff
PZ		 1902 pfit_w = (pfit_size >> 16) & 0xFFFF;
1903 pfit_h = pfit_size & 0xFFFF;
1904 if (pipe_w < pfit_w)
1905 pipe_w = pfit_w;
1906 if (pipe_h < pfit_h)
1907 pipe_h = pfit_h;
1908
1909 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1910 pfit_w * pfit_h);
1911 }
1912
1913 return pixel_rate;
1914}
1915
37126462 1916/* latency must be in 0.1us units. */
23297044 1917static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1918 uint32_t latency)
1919{
1920 uint64_t ret;
1921
3312ba65
VS		 1922 if (WARN(latency == 0, "Latency value missing\n"))
1923 return UINT_MAX;
1924
801bcfff
PZ		 1925 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1926 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1927
1928 return ret;
1929}
1930
37126462 1931/* latency must be in 0.1us units. */
23297044 1932static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1933 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1934 uint32_t latency)
1935{
1936 uint32_t ret;
1937
3312ba65
VS		 1938 if (WARN(latency == 0, "Latency value missing\n"))
1939 return UINT_MAX;
1940
801bcfff
PZ		 1941 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1942 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1943 ret = DIV_ROUND_UP(ret, 64) + 2;
1944 return ret;
1945}
1946
23297044 1947static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1948 uint8_t bytes_per_pixel)
1949{
1950 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1951}
1952
820c1980 1953struct ilk_pipe_wm_parameters {
801bcfff 1954 bool active;
801bcfff
PZ		 1955 uint32_t pipe_htotal;
1956 uint32_t pixel_rate;
c35426d2
VS		 1957 struct intel_plane_wm_parameters pri;
1958 struct intel_plane_wm_parameters spr;
1959 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 1960};
1961
820c1980 1962struct ilk_wm_maximums {
cca32e9a
PZ		 1963 uint16_t pri;
1964 uint16_t spr;
1965 uint16_t cur;
1966 uint16_t fbc;
1967};
1968
240264f4
VS		 1969/* used in computing the new watermarks state */
1970struct intel_wm_config {
1971 unsigned int num_pipes_active;
1972 bool sprites_enabled;
1973 bool sprites_scaled;
240264f4
VS		 1974};
1975
37126462
VS		 1976/*
1977 * For both WM_PIPE and WM_LP.
1978 * mem_value must be in 0.1us units.
1979 */
820c1980 1980static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
cca32e9a
PZ		 1981 uint32_t mem_value,
1982 bool is_lp)
801bcfff 1983{
cca32e9a
PZ		 1984 uint32_t method1, method2;
1985
c35426d2 1986 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 1987 return 0;
1988
23297044 1989 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1990 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1991 mem_value);
1992
1993 if (!is_lp)
1994 return method1;
1995
23297044 1996 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 1997 params->pipe_htotal,
c35426d2
VS		 1998 params->pri.horiz_pixels,
1999 params->pri.bytes_per_pixel,
cca32e9a
PZ		 2000 mem_value);
2001
2002 return min(method1, method2);
801bcfff
PZ		 2003}
2004
37126462
VS		 2005/*
2006 * For both WM_PIPE and WM_LP.
2007 * mem_value must be in 0.1us units.
2008 */
820c1980 2009static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 2010 uint32_t mem_value)
2011{
2012 uint32_t method1, method2;
2013
c35426d2 2014 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 2015 return 0;
2016
23297044 2017 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 2018 params->spr.bytes_per_pixel,
801bcfff 2019 mem_value);
23297044 2020 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 2021 params->pipe_htotal,
c35426d2
VS		 2022 params->spr.horiz_pixels,
2023 params->spr.bytes_per_pixel,
801bcfff
PZ		 2024 mem_value);
2025 return min(method1, method2);
2026}
2027
37126462
VS		 2028/*
2029 * For both WM_PIPE and WM_LP.
2030 * mem_value must be in 0.1us units.
2031 */
820c1980 2032static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 2033 uint32_t mem_value)
2034{
c35426d2 2035 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 2036 return 0;
2037
23297044 2038 return ilk_wm_method2(params->pixel_rate,
801bcfff 2039 params->pipe_htotal,
c35426d2
VS		 2040 params->cur.horiz_pixels,
2041 params->cur.bytes_per_pixel,
801bcfff
PZ		 2042 mem_value);
2043}
2044
cca32e9a 2045/* Only for WM_LP. */
820c1980 2046static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1fda9882 2047 uint32_t pri_val)
cca32e9a 2048{
c35426d2 2049 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 2050 return 0;
2051
23297044 2052 return ilk_wm_fbc(pri_val,
c35426d2
VS		 2053 params->pri.horiz_pixels,
2054 params->pri.bytes_per_pixel);
cca32e9a
PZ		 2055}
2056
158ae64f
VS		 2057static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
2058{
416f4727
VS		 2059 if (INTEL_INFO(dev)->gen >= 8)
2060 return 3072;
2061 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 2062 return 768;
2063 else
2064 return 512;
2065}
2066
4e975081
VS		 2067static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
2068 int level, bool is_sprite)
2069{
2070 if (INTEL_INFO(dev)->gen >= 8)
2071 /* BDW primary/sprite plane watermarks */
2072 return level == 0 ? 255 : 2047;
2073 else if (INTEL_INFO(dev)->gen >= 7)
2074 /* IVB/HSW primary/sprite plane watermarks */
2075 return level == 0 ? 127 : 1023;
2076 else if (!is_sprite)
2077 /* ILK/SNB primary plane watermarks */
2078 return level == 0 ? 127 : 511;
2079 else
2080 /* ILK/SNB sprite plane watermarks */
2081 return level == 0 ? 63 : 255;
2082}
2083
2084static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
2085 int level)
2086{
2087 if (INTEL_INFO(dev)->gen >= 7)
2088 return level == 0 ? 63 : 255;
2089 else
2090 return level == 0 ? 31 : 63;
2091}
2092
2093static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
2094{
2095 if (INTEL_INFO(dev)->gen >= 8)
2096 return 31;
2097 else
2098 return 15;
2099}
2100
158ae64f
VS		 2101/* Calculate the maximum primary/sprite plane watermark */
2102static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2103 int level,
240264f4 2104 const struct intel_wm_config *config,
158ae64f
VS		 2105 enum intel_ddb_partitioning ddb_partitioning,
2106 bool is_sprite)
2107{
2108 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 2109
2110 /* if sprites aren't enabled, sprites get nothing */
240264f4 2111 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 2112 return 0;
2113
2114 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 2115 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 2116 fifo_size /= INTEL_INFO(dev)->num_pipes;
2117
2118 /*
2119 * For some reason the non self refresh
2120 * FIFO size is only half of the self
2121 * refresh FIFO size on ILK/SNB.
2122 */
2123 if (INTEL_INFO(dev)->gen <= 6)
2124 fifo_size /= 2;
2125 }
2126
240264f4 2127 if (config->sprites_enabled) {
158ae64f
VS		 2128 /* level 0 is always calculated with 1:1 split */
2129 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2130 if (is_sprite)
2131 fifo_size *= 5;
2132 fifo_size /= 6;
2133 } else {
2134 fifo_size /= 2;
2135 }
2136 }
2137
2138 /* clamp to max that the registers can hold */
4e975081 2139 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 2140}
2141
2142/* Calculate the maximum cursor plane watermark */
2143static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 2144 int level,
2145 const struct intel_wm_config *config)
158ae64f
VS		 2146{
2147 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 2148 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 2149 return 64;
2150
2151 /* otherwise just report max that registers can hold */
4e975081 2152 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 2153}
2154
d34ff9c6 2155static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 2156 int level,
2157 const struct intel_wm_config *config,
2158 enum intel_ddb_partitioning ddb_partitioning,
820c1980 2159 struct ilk_wm_maximums *max)
158ae64f 2160{
240264f4
VS		 2161 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2162 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2163 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 2164 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 2165}
2166
a3cb4048
VS		 2167static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
2168 int level,
2169 struct ilk_wm_maximums *max)
2170{
2171 max->pri = ilk_plane_wm_reg_max(dev, level, false);
2172 max->spr = ilk_plane_wm_reg_max(dev, level, true);
2173 max->cur = ilk_cursor_wm_reg_max(dev, level);
2174 max->fbc = ilk_fbc_wm_reg_max(dev);
2175}
2176
d9395655 2177static bool ilk_validate_wm_level(int level,
820c1980 2178 const struct ilk_wm_maximums *max,
d9395655 2179 struct intel_wm_level *result)
a9786a11
VS		 2180{
2181 bool ret;
2182
2183 /* already determined to be invalid? */
2184 if (!result->enable)
2185 return false;
2186
2187 result->enable = result->pri_val <= max->pri &&
2188 result->spr_val <= max->spr &&
2189 result->cur_val <= max->cur;
2190
2191 ret = result->enable;
2192
2193 /*
2194 * HACK until we can pre-compute everything,
2195 * and thus fail gracefully if LP0 watermarks
2196 * are exceeded...
2197 */
2198 if (level == 0 && !result->enable) {
2199 if (result->pri_val > max->pri)
2200 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2201 level, result->pri_val, max->pri);
2202 if (result->spr_val > max->spr)
2203 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2204 level, result->spr_val, max->spr);
2205 if (result->cur_val > max->cur)
2206 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2207 level, result->cur_val, max->cur);
2208
2209 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2210 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2211 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2212 result->enable = true;
2213 }
2214
a9786a11
VS		 2215 return ret;
2216}
2217
d34ff9c6 2218static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
6f5ddd17 2219 int level,
820c1980 2220 const struct ilk_pipe_wm_parameters *p,
1fd527cc 2221 struct intel_wm_level *result)
6f5ddd17
VS		 2222{
2223 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2224 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2225 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2226
2227 /* WM1+ latency values stored in 0.5us units */
2228 if (level > 0) {
2229 pri_latency *= 5;
2230 spr_latency *= 5;
2231 cur_latency *= 5;
2232 }
2233
2234 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2235 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2236 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2237 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2238 result->enable = true;
2239}
2240
801bcfff
PZ		 2241static uint32_t
2242hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2243{
2244 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2245 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 2246 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 2247 u32 linetime, ips_linetime;
1f8eeabf 2248
801bcfff
PZ		 2249 if (!intel_crtc_active(crtc))
2250 return 0;
1011d8c4 2251
1f8eeabf
ED		 2252 /* The WM are computed with base on how long it takes to fill a single
2253 * row at the given clock rate, multiplied by 8.
2254 * */
fec8cba3
JB		 2255 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2256 mode->crtc_clock);
2257 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
85a02deb 2258 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 2259
801bcfff
PZ		 2260 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2261 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2262}
2263
12b134df
VS		 2264static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2265{
2266 struct drm_i915_private *dev_priv = dev->dev_private;
2267
a42a5719 2268 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2269 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2270
2271 wm[0] = (sskpd >> 56) & 0xFF;
2272 if (wm[0] == 0)
2273 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2274 wm[1] = (sskpd >> 4) & 0xFF;
2275 wm[2] = (sskpd >> 12) & 0xFF;
2276 wm[3] = (sskpd >> 20) & 0x1FF;
2277 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2278 } else if (INTEL_INFO(dev)->gen >= 6) {
2279 uint32_t sskpd = I915_READ(MCH_SSKPD);
2280
2281 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2282 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2283 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2284 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2285 } else if (INTEL_INFO(dev)->gen >= 5) {
2286 uint32_t mltr = I915_READ(MLTR_ILK);
2287
2288 /* ILK primary LP0 latency is 700 ns */
2289 wm[0] = 7;
2290 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2291 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2292 }
2293}
2294
53615a5e
VS		 2295static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2296{
2297 /* ILK sprite LP0 latency is 1300 ns */
2298 if (INTEL_INFO(dev)->gen == 5)
2299 wm[0] = 13;
2300}
2301
2302static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2303{
2304 /* ILK cursor LP0 latency is 1300 ns */
2305 if (INTEL_INFO(dev)->gen == 5)
2306 wm[0] = 13;
2307
2308 /* WaDoubleCursorLP3Latency:ivb */
2309 if (IS_IVYBRIDGE(dev))
2310 wm[3] *= 2;
2311}
2312
546c81fd 2313int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2314{
26ec971e 2315 /* how many WM levels are we expecting */
a42a5719 2316 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2317 return 4;
26ec971e 2318 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2319 return 3;
26ec971e 2320 else
ad0d6dc4
VS		 2321 return 2;
2322}
7526ed79 2323
ad0d6dc4
VS		 2324static void intel_print_wm_latency(struct drm_device *dev,
2325 const char *name,
2326 const uint16_t wm[5])
2327{
2328 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2329
2330 for (level = 0; level <= max_level; level++) {
2331 unsigned int latency = wm[level];
2332
2333 if (latency == 0) {
2334 DRM_ERROR("%s WM%d latency not provided\n",
2335 name, level);
2336 continue;
2337 }
2338
2339 /* WM1+ latency values in 0.5us units */
2340 if (level > 0)
2341 latency *= 5;
2342
2343 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2344 name, level, wm[level],
2345 latency / 10, latency % 10);
2346 }
2347}
2348
e95a2f75
VS		 2349static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2350 uint16_t wm[5], uint16_t min)
2351{
2352 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2353
2354 if (wm[0] >= min)
2355 return false;
2356
2357 wm[0] = max(wm[0], min);
2358 for (level = 1; level <= max_level; level++)
2359 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2360
2361 return true;
2362}
2363
2364static void snb_wm_latency_quirk(struct drm_device *dev)
2365{
2366 struct drm_i915_private *dev_priv = dev->dev_private;
2367 bool changed;
2368
2369 /*
2370 * The BIOS provided WM memory latency values are often
2371 * inadequate for high resolution displays. Adjust them.
2372 */
2373 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2374 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2375 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2376
2377 if (!changed)
2378 return;
2379
2380 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2381 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2382 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2383 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2384}
2385
fa50ad61 2386static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2387{
2388 struct drm_i915_private *dev_priv = dev->dev_private;
2389
2390 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2391
2392 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2393 sizeof(dev_priv->wm.pri_latency));
2394 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2395 sizeof(dev_priv->wm.pri_latency));
2396
2397 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2398 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2399
2400 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2401 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2402 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2403
2404 if (IS_GEN6(dev))
2405 snb_wm_latency_quirk(dev);
53615a5e
VS		 2406}
2407
820c1980 2408static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2a44b76b 2409 struct ilk_pipe_wm_parameters *p)
1011d8c4 2410{
7c4a395f
VS		 2411 struct drm_device *dev = crtc->dev;
2412 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2413 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2414 struct drm_plane *plane;
1011d8c4 2415
2a44b76b
VS		 2416 if (!intel_crtc_active(crtc))
2417 return;
801bcfff 2418
2a44b76b
VS		 2419 p->active = true;
2420 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2421 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2422 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2423 p->cur.bytes_per_pixel = 4;
2424 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2425 p->cur.horiz_pixels = intel_crtc->cursor_width;
2426 /* TODO: for now, assume primary and cursor planes are always enabled. */
2427 p->pri.enabled = true;
2428 p->cur.enabled = true;
7c4a395f 2429
af2b653b 2430 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
801bcfff 2431 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2432
2a44b76b 2433 if (intel_plane->pipe == pipe) {
7c4a395f 2434 p->spr = intel_plane->wm;
2a44b76b
VS		 2435 break;
2436 }
2437 }
2438}
2439
2440static void ilk_compute_wm_config(struct drm_device *dev,
2441 struct intel_wm_config *config)
2442{
2443 struct intel_crtc *intel_crtc;
2444
2445 /* Compute the currently _active_ config */
d3fcc808 2446 for_each_intel_crtc(dev, intel_crtc) {
2a44b76b 2447 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
cca32e9a 2448
2a44b76b
VS		 2449 if (!wm->pipe_enabled)
2450 continue;
cca32e9a 2451
2a44b76b
VS		 2452 config->sprites_enabled |= wm->sprites_enabled;
2453 config->sprites_scaled |= wm->sprites_scaled;
2454 config->num_pipes_active++;
cca32e9a 2455 }
801bcfff
PZ		 2456}
2457
0b2ae6d7
VS		 2458/* Compute new watermarks for the pipe */
2459static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
820c1980 2460 const struct ilk_pipe_wm_parameters *params,
0b2ae6d7
VS		 2461 struct intel_pipe_wm *pipe_wm)
2462{
2463 struct drm_device *dev = crtc->dev;
d34ff9c6 2464 const struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7
VS		 2465 int level, max_level = ilk_wm_max_level(dev);
2466 /* LP0 watermark maximums depend on this pipe alone */
2467 struct intel_wm_config config = {
2468 .num_pipes_active = 1,
2469 .sprites_enabled = params->spr.enabled,
2470 .sprites_scaled = params->spr.scaled,
2471 };
820c1980 2472 struct ilk_wm_maximums max;
0b2ae6d7 2473
2a44b76b
VS		 2474 pipe_wm->pipe_enabled = params->active;
2475 pipe_wm->sprites_enabled = params->spr.enabled;
2476 pipe_wm->sprites_scaled = params->spr.scaled;
2477
7b39a0b7
VS		 2478 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2479 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2480 max_level = 1;
2481
2482 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2483 if (params->spr.scaled)
2484 max_level = 0;
2485
a3cb4048 2486 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
0b2ae6d7 2487
a42a5719 2488 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2489 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7 2490
a3cb4048
VS		 2491 /* LP0 watermarks always use 1/2 DDB partitioning */
2492 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2493
0b2ae6d7 2494 /* At least LP0 must be valid */
a3cb4048
VS		 2495 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2496 return false;
2497
2498 ilk_compute_wm_reg_maximums(dev, 1, &max);
2499
2500 for (level = 1; level <= max_level; level++) {
2501 struct intel_wm_level wm = {};
2502
2503 ilk_compute_wm_level(dev_priv, level, params, &wm);
2504
2505 /*
2506 * Disable any watermark level that exceeds the
2507 * register maximums since such watermarks are
2508 * always invalid.
2509 */
2510 if (!ilk_validate_wm_level(level, &max, &wm))
2511 break;
2512
2513 pipe_wm->wm[level] = wm;
2514 }
2515
2516 return true;
0b2ae6d7
VS		 2517}
2518
2519/*
2520 * Merge the watermarks from all active pipes for a specific level.
2521 */
2522static void ilk_merge_wm_level(struct drm_device *dev,
2523 int level,
2524 struct intel_wm_level *ret_wm)
2525{
2526 const struct intel_crtc *intel_crtc;
2527
d52fea5b
VS		 2528 ret_wm->enable = true;
2529
d3fcc808 2530 for_each_intel_crtc(dev, intel_crtc) {
fe392efd
VS		 2531 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2532 const struct intel_wm_level *wm = &active->wm[level];
2533
2534 if (!active->pipe_enabled)
2535 continue;
0b2ae6d7 2536
d52fea5b
VS		 2537 /*
2538 * The watermark values may have been used in the past,
2539 * so we must maintain them in the registers for some
2540 * time even if the level is now disabled.
2541 */
0b2ae6d7 2542 if (!wm->enable)
d52fea5b 2543 ret_wm->enable = false;
0b2ae6d7
VS		 2544
2545 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2546 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2547 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2548 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2549 }
0b2ae6d7
VS		 2550}
2551
2552/*
2553 * Merge all low power watermarks for all active pipes.
2554 */
2555static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2556 const struct intel_wm_config *config,
820c1980 2557 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2558 struct intel_pipe_wm *merged)
2559{
2560 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2561 int last_enabled_level = max_level;
0b2ae6d7 2562
0ba22e26
VS		 2563 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2564 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2565 config->num_pipes_active > 1)
2566 return;
2567
6c8b6c28
VS		 2568 /* ILK: FBC WM must be disabled always */
2569 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2570
2571 /* merge each WM1+ level */
2572 for (level = 1; level <= max_level; level++) {
2573 struct intel_wm_level *wm = &merged->wm[level];
2574
2575 ilk_merge_wm_level(dev, level, wm);
2576
d52fea5b
VS		 2577 if (level > last_enabled_level)
2578 wm->enable = false;
2579 else if (!ilk_validate_wm_level(level, max, wm))
2580 /* make sure all following levels get disabled */
2581 last_enabled_level = level - 1;
0b2ae6d7
VS		 2582
2583 /*
2584 * The spec says it is preferred to disable
2585 * FBC WMs instead of disabling a WM level.
2586 */
2587 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2588 if (wm->enable)
2589 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2590 wm->fbc_val = 0;
2591 }
2592 }
6c8b6c28
VS		 2593
2594 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2595 /*
2596 * FIXME this is racy. FBC might get enabled later.
2597 * What we should check here is whether FBC can be
2598 * enabled sometime later.
2599 */
2600 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2601 for (level = 2; level <= max_level; level++) {
2602 struct intel_wm_level *wm = &merged->wm[level];
2603
2604 wm->enable = false;
2605 }
2606 }
0b2ae6d7
VS		 2607}
2608
b380ca3c
VS		 2609static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2610{
2611 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2612 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2613}
2614
a68d68ee
VS		 2615/* The value we need to program into the WM_LPx latency field */
2616static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2617{
2618 struct drm_i915_private *dev_priv = dev->dev_private;
2619
a42a5719 2620 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2621 return 2 * level;
2622 else
2623 return dev_priv->wm.pri_latency[level];
2624}
2625
820c1980 2626static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2627 const struct intel_pipe_wm *merged,
609cedef 2628 enum intel_ddb_partitioning partitioning,
820c1980 2629 struct ilk_wm_values *results)
801bcfff 2630{
0b2ae6d7
VS		 2631 struct intel_crtc *intel_crtc;
2632 int level, wm_lp;
cca32e9a 2633
0362c781 2634 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2635 results->partitioning = partitioning;
cca32e9a 2636
0b2ae6d7 2637 /* LP1+ register values */
cca32e9a 2638 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2639 const struct intel_wm_level *r;
801bcfff 2640
b380ca3c 2641 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2642
0362c781 2643 r = &merged->wm[level];
cca32e9a 2644
d52fea5b
VS		 2645 /*
2646 * Maintain the watermark values even if the level is
2647 * disabled. Doing otherwise could cause underruns.
2648 */
2649 results->wm_lp[wm_lp - 1] =
a68d68ee 2650 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2651 (r->pri_val << WM1_LP_SR_SHIFT) |
2652 r->cur_val;
2653
d52fea5b
VS		 2654 if (r->enable)
2655 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2656
416f4727
VS		 2657 if (INTEL_INFO(dev)->gen >= 8)
2658 results->wm_lp[wm_lp - 1] |=
2659 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2660 else
2661 results->wm_lp[wm_lp - 1] |=
2662 r->fbc_val << WM1_LP_FBC_SHIFT;
2663
d52fea5b
VS		 2664 /*
2665 * Always set WM1S_LP_EN when spr_val != 0, even if the
2666 * level is disabled. Doing otherwise could cause underruns.
2667 */
6cef2b8a
VS		 2668 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2669 WARN_ON(wm_lp != 1);
2670 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2671 } else
2672 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2673 }
801bcfff 2674
0b2ae6d7 2675 /* LP0 register values */
d3fcc808 2676 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7
VS		 2677 enum pipe pipe = intel_crtc->pipe;
2678 const struct intel_wm_level *r =
2679 &intel_crtc->wm.active.wm[0];
2680
2681 if (WARN_ON(!r->enable))
2682 continue;
2683
2684 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2685
0b2ae6d7
VS		 2686 results->wm_pipe[pipe] =
2687 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2688 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2689 r->cur_val;
801bcfff
PZ		 2690 }
2691}
2692
861f3389
PZ		 2693/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2694 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2695static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2696 struct intel_pipe_wm *r1,
2697 struct intel_pipe_wm *r2)
861f3389 2698{
198a1e9b
VS		 2699 int level, max_level = ilk_wm_max_level(dev);
2700 int level1 = 0, level2 = 0;
861f3389 2701
198a1e9b
VS		 2702 for (level = 1; level <= max_level; level++) {
2703 if (r1->wm[level].enable)
2704 level1 = level;
2705 if (r2->wm[level].enable)
2706 level2 = level;
861f3389
PZ		 2707 }
2708
198a1e9b
VS		 2709 if (level1 == level2) {
2710 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2711 return r2;
2712 else
2713 return r1;
198a1e9b 2714 } else if (level1 > level2) {
861f3389
PZ		 2715 return r1;
2716 } else {
2717 return r2;
2718 }
2719}
2720
49a687c4
VS		 2721/* dirty bits used to track which watermarks need changes */
2722#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2723#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2724#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2725#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2726#define WM_DIRTY_FBC (1 << 24)
2727#define WM_DIRTY_DDB (1 << 25)
2728
055e393f 2729static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2730 const struct ilk_wm_values *old,
2731 const struct ilk_wm_values *new)
49a687c4
VS		 2732{
2733 unsigned int dirty = 0;
2734 enum pipe pipe;
2735 int wm_lp;
2736
055e393f 2737 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2738 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2739 dirty |= WM_DIRTY_LINETIME(pipe);
2740 /* Must disable LP1+ watermarks too */
2741 dirty |= WM_DIRTY_LP_ALL;
2742 }
2743
2744 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2745 dirty |= WM_DIRTY_PIPE(pipe);
2746 /* Must disable LP1+ watermarks too */
2747 dirty |= WM_DIRTY_LP_ALL;
2748 }
2749 }
2750
2751 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2752 dirty |= WM_DIRTY_FBC;
2753 /* Must disable LP1+ watermarks too */
2754 dirty |= WM_DIRTY_LP_ALL;
2755 }
2756
2757 if (old->partitioning != new->partitioning) {
2758 dirty |= WM_DIRTY_DDB;
2759 /* Must disable LP1+ watermarks too */
2760 dirty |= WM_DIRTY_LP_ALL;
2761 }
2762
2763 /* LP1+ watermarks already deemed dirty, no need to continue */
2764 if (dirty & WM_DIRTY_LP_ALL)
2765 return dirty;
2766
2767 /* Find the lowest numbered LP1+ watermark in need of an update... */
2768 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2769 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2770 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2771 break;
2772 }
2773
2774 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2775 for (; wm_lp <= 3; wm_lp++)
2776 dirty |= WM_DIRTY_LP(wm_lp);
2777
2778 return dirty;
2779}
2780
8553c18e
VS		 2781static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2782 unsigned int dirty)
801bcfff 2783{
820c1980 2784 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2785 bool changed = false;
801bcfff 2786
facd619b
VS		 2787 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2788 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2789 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2790 changed = true;
facd619b
VS		 2791 }
2792 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2793 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2794 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2795 changed = true;
facd619b
VS		 2796 }
2797 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2798 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2799 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2800 changed = true;
facd619b 2801 }
801bcfff 2802
facd619b
VS		 2803 /*
2804 * Don't touch WM1S_LP_EN here.
2805 * Doing so could cause underruns.
2806 */
6cef2b8a 2807
8553c18e
VS		 2808 return changed;
2809}
2810
2811/*
2812 * The spec says we shouldn't write when we don't need, because every write
2813 * causes WMs to be re-evaluated, expending some power.
2814 */
820c1980
ID		 2815static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2816 struct ilk_wm_values *results)
8553c18e
VS		 2817{
2818 struct drm_device *dev = dev_priv->dev;
820c1980 2819 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2820 unsigned int dirty;
2821 uint32_t val;
2822
055e393f 2823 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2824 if (!dirty)
2825 return;
2826
2827 _ilk_disable_lp_wm(dev_priv, dirty);
2828
49a687c4 2829 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2830 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2831 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2832 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2833 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2834 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2835
49a687c4 2836 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2837 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2838 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2839 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2840 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2841 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2842
49a687c4 2843 if (dirty & WM_DIRTY_DDB) {
a42a5719 2844 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2845 val = I915_READ(WM_MISC);
2846 if (results->partitioning == INTEL_DDB_PART_1_2)
2847 val &= ~WM_MISC_DATA_PARTITION_5_6;
2848 else
2849 val |= WM_MISC_DATA_PARTITION_5_6;
2850 I915_WRITE(WM_MISC, val);
2851 } else {
2852 val = I915_READ(DISP_ARB_CTL2);
2853 if (results->partitioning == INTEL_DDB_PART_1_2)
2854 val &= ~DISP_DATA_PARTITION_5_6;
2855 else
2856 val |= DISP_DATA_PARTITION_5_6;
2857 I915_WRITE(DISP_ARB_CTL2, val);
2858 }
1011d8c4
PZ		 2859 }
2860
49a687c4 2861 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2862 val = I915_READ(DISP_ARB_CTL);
2863 if (results->enable_fbc_wm)
2864 val &= ~DISP_FBC_WM_DIS;
2865 else
2866 val |= DISP_FBC_WM_DIS;
2867 I915_WRITE(DISP_ARB_CTL, val);
2868 }
2869
954911eb
ID		 2870 if (dirty & WM_DIRTY_LP(1) &&
2871 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2872 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2873
2874 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2875 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2876 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2877 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2878 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2879 }
801bcfff 2880
facd619b 2881 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2882 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2883 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2884 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2885 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2886 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2887
2888 dev_priv->wm.hw = *results;
801bcfff
PZ		 2889}
2890
8553c18e
VS		 2891static bool ilk_disable_lp_wm(struct drm_device *dev)
2892{
2893 struct drm_i915_private *dev_priv = dev->dev_private;
2894
2895 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2896}
2897
820c1980 2898static void ilk_update_wm(struct drm_crtc *crtc)
801bcfff 2899{
7c4a395f 2900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 2901 struct drm_device *dev = crtc->dev;
801bcfff 2902 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980
ID		 2903 struct ilk_wm_maximums max;
2904 struct ilk_pipe_wm_parameters params = {};
2905 struct ilk_wm_values results = {};
77c122bc 2906 enum intel_ddb_partitioning partitioning;
7c4a395f 2907 struct intel_pipe_wm pipe_wm = {};
198a1e9b 2908 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 2909 struct intel_wm_config config = {};
7c4a395f 2910
2a44b76b 2911 ilk_compute_wm_parameters(crtc, &params);
7c4a395f
VS		 2912
2913 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2914
2915 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2916 return;
861f3389 2917
7c4a395f 2918 intel_crtc->wm.active = pipe_wm;
861f3389 2919
2a44b76b
VS		 2920 ilk_compute_wm_config(dev, &config);
2921
34982fe1 2922 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
0ba22e26 2923 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 2924
2925 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 2926 if (INTEL_INFO(dev)->gen >= 7 &&
2927 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 2928 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
0ba22e26 2929 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 2930
820c1980 2931 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 2932 } else {
198a1e9b 2933 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 2934 }
2935
198a1e9b 2936 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 2937 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 2938
820c1980 2939 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 2940
820c1980 2941 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 2942}
2943
ed57cb8a
DL		 2944static void
2945ilk_update_sprite_wm(struct drm_plane *plane,
2946 struct drm_crtc *crtc,
2947 uint32_t sprite_width, uint32_t sprite_height,
2948 int pixel_size, bool enabled, bool scaled)
526682e9 2949{
8553c18e 2950 struct drm_device *dev = plane->dev;
adf3d35e 2951 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 2952
adf3d35e
VS		 2953 intel_plane->wm.enabled = enabled;
2954 intel_plane->wm.scaled = scaled;
2955 intel_plane->wm.horiz_pixels = sprite_width;
ed57cb8a 2956 intel_plane->wm.vert_pixels = sprite_width;
adf3d35e 2957 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 2958
8553c18e
VS		 2959 /*
2960 * IVB workaround: must disable low power watermarks for at least
2961 * one frame before enabling scaling. LP watermarks can be re-enabled
2962 * when scaling is disabled.
2963 *
2964 * WaCxSRDisabledForSpriteScaling:ivb
2965 */
2966 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2967 intel_wait_for_vblank(dev, intel_plane->pipe);
2968
820c1980 2969 ilk_update_wm(crtc);
526682e9
PZ		 2970}
2971
243e6a44
VS		 2972static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2973{
2974 struct drm_device *dev = crtc->dev;
2975 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 2976 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 2977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2978 struct intel_pipe_wm *active = &intel_crtc->wm.active;
2979 enum pipe pipe = intel_crtc->pipe;
2980 static const unsigned int wm0_pipe_reg[] = {
2981 [PIPE_A] = WM0_PIPEA_ILK,
2982 [PIPE_B] = WM0_PIPEB_ILK,
2983 [PIPE_C] = WM0_PIPEC_IVB,
2984 };
2985
2986 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 2987 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2988 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 2989
2a44b76b
VS		 2990 active->pipe_enabled = intel_crtc_active(crtc);
2991
2992 if (active->pipe_enabled) {
243e6a44
VS		 2993 u32 tmp = hw->wm_pipe[pipe];
2994
2995 /*
2996 * For active pipes LP0 watermark is marked as
2997 * enabled, and LP1+ watermaks as disabled since
2998 * we can't really reverse compute them in case
2999 * multiple pipes are active.
3000 */
3001 active->wm[0].enable = true;
3002 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3003 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3004 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3005 active->linetime = hw->wm_linetime[pipe];
3006 } else {
3007 int level, max_level = ilk_wm_max_level(dev);
3008
3009 /*
3010 * For inactive pipes, all watermark levels
3011 * should be marked as enabled but zeroed,
3012 * which is what we'd compute them to.
3013 */
3014 for (level = 0; level <= max_level; level++)
3015 active->wm[level].enable = true;
3016 }
3017}
3018
3019void ilk_wm_get_hw_state(struct drm_device *dev)
3020{
3021 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3022 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 3023 struct drm_crtc *crtc;
3024
70e1e0ec 3025 for_each_crtc(dev, crtc)
243e6a44
VS		 3026 ilk_pipe_wm_get_hw_state(crtc);
3027
3028 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3029 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3030 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3031
3032 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 3033 if (INTEL_INFO(dev)->gen >= 7) {
3034 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3035 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3036 }
243e6a44 3037
a42a5719 3038 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 3039 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3040 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3041 else if (IS_IVYBRIDGE(dev))
3042 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
3043 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 3044
3045 hw->enable_fbc_wm =
3046 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3047}
3048
b445e3b0
ED		 3049/**
3050 * intel_update_watermarks - update FIFO watermark values based on current modes
3051 *
3052 * Calculate watermark values for the various WM regs based on current mode
3053 * and plane configuration.
3054 *
3055 * There are several cases to deal with here:
3056 * - normal (i.e. non-self-refresh)
3057 * - self-refresh (SR) mode
3058 * - lines are large relative to FIFO size (buffer can hold up to 2)
3059 * - lines are small relative to FIFO size (buffer can hold more than 2
3060 * lines), so need to account for TLB latency
3061 *
3062 * The normal calculation is:
3063 * watermark = dotclock * bytes per pixel * latency
3064 * where latency is platform & configuration dependent (we assume pessimal
3065 * values here).
3066 *
3067 * The SR calculation is:
3068 * watermark = (trunc(latency/line time)+1) * surface width *
3069 * bytes per pixel
3070 * where
3071 * line time = htotal / dotclock
3072 * surface width = hdisplay for normal plane and 64 for cursor
3073 * and latency is assumed to be high, as above.
3074 *
3075 * The final value programmed to the register should always be rounded up,
3076 * and include an extra 2 entries to account for clock crossings.
3077 *
3078 * We don't use the sprite, so we can ignore that. And on Crestline we have
3079 * to set the non-SR watermarks to 8.
3080 */
46ba614c 3081void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 3082{
46ba614c 3083 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 3084
3085 if (dev_priv->display.update_wm)
46ba614c 3086 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 3087}
3088
adf3d35e
VS		 3089void intel_update_sprite_watermarks(struct drm_plane *plane,
3090 struct drm_crtc *crtc,
ed57cb8a
DL		 3091 uint32_t sprite_width,
3092 uint32_t sprite_height,
3093 int pixel_size,
39db4a4d 3094 bool enabled, bool scaled)
b445e3b0 3095{
adf3d35e 3096 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 3097
3098 if (dev_priv->display.update_sprite_wm)
ed57cb8a
DL		 3099 dev_priv->display.update_sprite_wm(plane, crtc,
3100 sprite_width, sprite_height,
39db4a4d 3101 pixel_size, enabled, scaled);
b445e3b0
ED		 3102}
3103
2b4e57bd
ED		 3104static struct drm_i915_gem_object *
3105intel_alloc_context_page(struct drm_device *dev)
3106{
3107 struct drm_i915_gem_object *ctx;
3108 int ret;
3109
3110 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3111
3112 ctx = i915_gem_alloc_object(dev, 4096);
3113 if (!ctx) {
3114 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3115 return NULL;
3116 }
3117
c69766f2 3118 ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
2b4e57bd
ED		 3119 if (ret) {
3120 DRM_ERROR("failed to pin power context: %d\n", ret);
3121 goto err_unref;
3122 }
3123
3124 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3125 if (ret) {
3126 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3127 goto err_unpin;
3128 }
3129
3130 return ctx;
3131
3132err_unpin:
d7f46fc4 3133 i915_gem_object_ggtt_unpin(ctx);
2b4e57bd
ED		 3134err_unref:
3135 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 3136 return NULL;
3137}
3138
9270388e
DV		 3139/**
3140 * Lock protecting IPS related data structures
9270388e
DV		 3141 */
3142DEFINE_SPINLOCK(mchdev_lock);
3143
3144/* Global for IPS driver to get at the current i915 device. Protected by
3145 * mchdev_lock. */
3146static struct drm_i915_private *i915_mch_dev;
3147
2b4e57bd
ED		 3148bool ironlake_set_drps(struct drm_device *dev, u8 val)
3149{
3150 struct drm_i915_private *dev_priv = dev->dev_private;
3151 u16 rgvswctl;
3152
9270388e
DV		 3153 assert_spin_locked(&mchdev_lock);
3154
2b4e57bd
ED		 3155 rgvswctl = I915_READ16(MEMSWCTL);
3156 if (rgvswctl & MEMCTL_CMD_STS) {
3157 DRM_DEBUG("gpu busy, RCS change rejected\n");
3158 return false; /* still busy with another command */
3159 }
3160
3161 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3162 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3163 I915_WRITE16(MEMSWCTL, rgvswctl);
3164 POSTING_READ16(MEMSWCTL);
3165
3166 rgvswctl |= MEMCTL_CMD_STS;
3167 I915_WRITE16(MEMSWCTL, rgvswctl);
3168
3169 return true;
3170}
3171
8090c6b9 3172static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 3173{
3174 struct drm_i915_private *dev_priv = dev->dev_private;
3175 u32 rgvmodectl = I915_READ(MEMMODECTL);
3176 u8 fmax, fmin, fstart, vstart;
3177
9270388e
DV		 3178 spin_lock_irq(&mchdev_lock);
3179
2b4e57bd
ED		 3180 /* Enable temp reporting */
3181 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3182 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3183
3184 /* 100ms RC evaluation intervals */
3185 I915_WRITE(RCUPEI, 100000);
3186 I915_WRITE(RCDNEI, 100000);
3187
3188 /* Set max/min thresholds to 90ms and 80ms respectively */
3189 I915_WRITE(RCBMAXAVG, 90000);
3190 I915_WRITE(RCBMINAVG, 80000);
3191
3192 I915_WRITE(MEMIHYST, 1);
3193
3194 /* Set up min, max, and cur for interrupt handling */
3195 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3196 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3197 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3198 MEMMODE_FSTART_SHIFT;
3199
3200 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3201 PXVFREQ_PX_SHIFT;
3202
20e4d407
DV		 3203 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3204 dev_priv->ips.fstart = fstart;
2b4e57bd 3205
20e4d407
DV		 3206 dev_priv->ips.max_delay = fstart;
3207 dev_priv->ips.min_delay = fmin;
3208 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 3209
3210 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3211 fmax, fmin, fstart);
3212
3213 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3214
3215 /*
3216 * Interrupts will be enabled in ironlake_irq_postinstall
3217 */
3218
3219 I915_WRITE(VIDSTART, vstart);
3220 POSTING_READ(VIDSTART);
3221
3222 rgvmodectl |= MEMMODE_SWMODE_EN;
3223 I915_WRITE(MEMMODECTL, rgvmodectl);
3224
9270388e 3225 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 3226 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 3227 mdelay(1);
2b4e57bd
ED		 3228
3229 ironlake_set_drps(dev, fstart);
3230
20e4d407 3231 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 3232 I915_READ(0x112e0);
20e4d407
DV		 3233 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3234 dev_priv->ips.last_count2 = I915_READ(0x112f4);
5ed0bdf2 3235 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 3236
3237 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3238}
3239
8090c6b9 3240static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 3241{
3242 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 3243 u16 rgvswctl;
3244
3245 spin_lock_irq(&mchdev_lock);
3246
3247 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 3248
3249 /* Ack interrupts, disable EFC interrupt */
3250 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3251 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3252 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3253 I915_WRITE(DEIIR, DE_PCU_EVENT);
3254 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3255
3256 /* Go back to the starting frequency */
20e4d407 3257 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 3258 mdelay(1);
2b4e57bd
ED		 3259 rgvswctl |= MEMCTL_CMD_STS;
3260 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 3261 mdelay(1);
2b4e57bd 3262
9270388e 3263 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3264}
3265
acbe9475
DV		 3266/* There's a funny hw issue where the hw returns all 0 when reading from
3267 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3268 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3269 * all limits and the gpu stuck at whatever frequency it is at atm).
3270 */
6917c7b9 3271static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 3272{
7b9e0ae6 3273 u32 limits;
2b4e57bd 3274
20b46e59
DV		 3275 /* Only set the down limit when we've reached the lowest level to avoid
3276 * getting more interrupts, otherwise leave this clear. This prevents a
3277 * race in the hw when coming out of rc6: There's a tiny window where
3278 * the hw runs at the minimal clock before selecting the desired
3279 * frequency, if the down threshold expires in that window we will not
3280 * receive a down interrupt. */
b39fb297
BW		 3281 limits = dev_priv->rps.max_freq_softlimit << 24;
3282 if (val <= dev_priv->rps.min_freq_softlimit)
3283 limits |= dev_priv->rps.min_freq_softlimit << 16;
20b46e59
DV		 3284
3285 return limits;
3286}
3287
dd75fdc8
CW		 3288static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3289{
3290 int new_power;
3291
3292 new_power = dev_priv->rps.power;
3293 switch (dev_priv->rps.power) {
3294 case LOW_POWER:
b39fb297 3295 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3296 new_power = BETWEEN;
3297 break;
3298
3299 case BETWEEN:
b39fb297 3300 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 3301 new_power = LOW_POWER;
b39fb297 3302 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3303 new_power = HIGH_POWER;
3304 break;
3305
3306 case HIGH_POWER:
b39fb297 3307 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 3308 new_power = BETWEEN;
3309 break;
3310 }
3311 /* Max/min bins are special */
b39fb297 3312 if (val == dev_priv->rps.min_freq_softlimit)
dd75fdc8 3313 new_power = LOW_POWER;
b39fb297 3314 if (val == dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 3315 new_power = HIGH_POWER;
3316 if (new_power == dev_priv->rps.power)
3317 return;
3318
3319 /* Note the units here are not exactly 1us, but 1280ns. */
3320 switch (new_power) {
3321 case LOW_POWER:
3322 /* Upclock if more than 95% busy over 16ms */
3323 I915_WRITE(GEN6_RP_UP_EI, 12500);
3324 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3325
3326 /* Downclock if less than 85% busy over 32ms */
3327 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3328 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3329
3330 I915_WRITE(GEN6_RP_CONTROL,
3331 GEN6_RP_MEDIA_TURBO |
3332 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3333 GEN6_RP_MEDIA_IS_GFX |
3334 GEN6_RP_ENABLE |
3335 GEN6_RP_UP_BUSY_AVG |
3336 GEN6_RP_DOWN_IDLE_AVG);
3337 break;
3338
3339 case BETWEEN:
3340 /* Upclock if more than 90% busy over 13ms */
3341 I915_WRITE(GEN6_RP_UP_EI, 10250);
3342 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3343
3344 /* Downclock if less than 75% busy over 32ms */
3345 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3346 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3347
3348 I915_WRITE(GEN6_RP_CONTROL,
3349 GEN6_RP_MEDIA_TURBO |
3350 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3351 GEN6_RP_MEDIA_IS_GFX |
3352 GEN6_RP_ENABLE |
3353 GEN6_RP_UP_BUSY_AVG |
3354 GEN6_RP_DOWN_IDLE_AVG);
3355 break;
3356
3357 case HIGH_POWER:
3358 /* Upclock if more than 85% busy over 10ms */
3359 I915_WRITE(GEN6_RP_UP_EI, 8000);
3360 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3361
3362 /* Downclock if less than 60% busy over 32ms */
3363 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3364 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3365
3366 I915_WRITE(GEN6_RP_CONTROL,
3367 GEN6_RP_MEDIA_TURBO |
3368 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3369 GEN6_RP_MEDIA_IS_GFX |
3370 GEN6_RP_ENABLE |
3371 GEN6_RP_UP_BUSY_AVG |
3372 GEN6_RP_DOWN_IDLE_AVG);
3373 break;
3374 }
3375
3376 dev_priv->rps.power = new_power;
3377 dev_priv->rps.last_adj = 0;
3378}
3379
2876ce73
CW		 3380static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3381{
3382 u32 mask = 0;
3383
3384 if (val > dev_priv->rps.min_freq_softlimit)
3385 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3386 if (val < dev_priv->rps.max_freq_softlimit)
3387 mask |= GEN6_PM_RP_UP_THRESHOLD;
3388
7b3c29f6
CW		 3389 mask |= dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED);
3390 mask &= dev_priv->pm_rps_events;
3391
2876ce73
CW		 3392 /* IVB and SNB hard hangs on looping batchbuffer
3393 * if GEN6_PM_UP_EI_EXPIRED is masked.
3394 */
3395 if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3396 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3397
baccd458
D		 3398 if (IS_GEN8(dev_priv->dev))
3399 mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
3400
2876ce73
CW		 3401 return ~mask;
3402}
3403
b8a5ff8d
JM		 3404/* gen6_set_rps is called to update the frequency request, but should also be
3405 * called when the range (min_delay and max_delay) is modified so that we can
3406 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
20b46e59
DV		 3407void gen6_set_rps(struct drm_device *dev, u8 val)
3408{
3409 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 3410
4fc688ce 3411 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
b39fb297
BW		 3412 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3413 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
004777cb 3414
eb64cad1
CW		 3415 /* min/max delay may still have been modified so be sure to
3416 * write the limits value.
3417 */
3418 if (val != dev_priv->rps.cur_freq) {
3419 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 3420
50e6a2a7 3421 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 3422 I915_WRITE(GEN6_RPNSWREQ,
3423 HSW_FREQUENCY(val));
3424 else
3425 I915_WRITE(GEN6_RPNSWREQ,
3426 GEN6_FREQUENCY(val) |
3427 GEN6_OFFSET(0) |
3428 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 3429 }
7b9e0ae6 3430
7b9e0ae6
CW		 3431 /* Make sure we continue to get interrupts
3432 * until we hit the minimum or maximum frequencies.
3433 */
eb64cad1 3434 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
2876ce73 3435 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 3436
d5570a72
BW		 3437 POSTING_READ(GEN6_RPNSWREQ);
3438
b39fb297 3439 dev_priv->rps.cur_freq = val;
be2cde9a 3440 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3441}
3442
76c3552f
D		 3443/* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3444 *
3445 * * If Gfx is Idle, then
3446 * 1. Mask Turbo interrupts
3447 * 2. Bring up Gfx clock
3448 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3449 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3450 * 5. Unmask Turbo interrupts
3451*/
3452static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3453{
5549d25f
D		 3454 struct drm_device *dev = dev_priv->dev;
3455
3456 /* Latest VLV doesn't need to force the gfx clock */
3457 if (dev->pdev->revision >= 0xd) {
3458 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3459 return;
3460 }
3461
76c3552f
D		 3462 /*
3463 * When we are idle. Drop to min voltage state.
3464 */
3465
b39fb297 3466 if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
76c3552f
D		 3467 return;
3468
3469 /* Mask turbo interrupt so that they will not come in between */
3470 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3471
650ad970 3472 vlv_force_gfx_clock(dev_priv, true);
76c3552f 3473
b39fb297 3474 dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
76c3552f
D		 3475
3476 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
b39fb297 3477 dev_priv->rps.min_freq_softlimit);
76c3552f
D		 3478
3479 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3480 & GENFREQSTATUS) == 0, 5))
3481 DRM_ERROR("timed out waiting for Punit\n");
3482
650ad970 3483 vlv_force_gfx_clock(dev_priv, false);
76c3552f 3484
2876ce73
CW		 3485 I915_WRITE(GEN6_PMINTRMSK,
3486 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
76c3552f
D		 3487}
3488
b29c19b6
CW		 3489void gen6_rps_idle(struct drm_i915_private *dev_priv)
3490{
691bb717
DL		 3491 struct drm_device *dev = dev_priv->dev;
3492
b29c19b6 3493 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3494 if (dev_priv->rps.enabled) {
34638118
D		 3495 if (IS_CHERRYVIEW(dev))
3496 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3497 else if (IS_VALLEYVIEW(dev))
76c3552f 3498 vlv_set_rps_idle(dev_priv);
7526ed79 3499 else
b39fb297 3500 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
c0951f0c
CW		 3501 dev_priv->rps.last_adj = 0;
3502 }
b29c19b6
CW		 3503 mutex_unlock(&dev_priv->rps.hw_lock);
3504}
3505
3506void gen6_rps_boost(struct drm_i915_private *dev_priv)
3507{
691bb717
DL		 3508 struct drm_device *dev = dev_priv->dev;
3509
b29c19b6 3510 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3511 if (dev_priv->rps.enabled) {
691bb717 3512 if (IS_VALLEYVIEW(dev))
b39fb297 3513 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
7526ed79 3514 else
b39fb297 3515 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
c0951f0c
CW		 3516 dev_priv->rps.last_adj = 0;
3517 }
b29c19b6
CW		 3518 mutex_unlock(&dev_priv->rps.hw_lock);
3519}
3520
0a073b84
JB		 3521void valleyview_set_rps(struct drm_device *dev, u8 val)
3522{
3523 struct drm_i915_private *dev_priv = dev->dev_private;
7a67092a 3524
0a073b84 3525 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
b39fb297
BW		 3526 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3527 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
0a073b84 3528
1c14762d
VS		 3529 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
3530 "Odd GPU freq value\n"))
3531 val &= ~1;
3532
67956867
VS		 3533 if (val != dev_priv->rps.cur_freq) {
3534 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3535 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3536 dev_priv->rps.cur_freq,
3537 vlv_gpu_freq(dev_priv, val), val);
3538
2876ce73 3539 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
67956867 3540 }
0a073b84 3541
09c87db8 3542 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
0a073b84 3543
b39fb297 3544 dev_priv->rps.cur_freq = val;
2ec3815f 3545 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
0a073b84
JB		 3546}
3547
0961021a
BW		 3548static void gen8_disable_rps_interrupts(struct drm_device *dev)
3549{
3550 struct drm_i915_private *dev_priv = dev->dev_private;
7526ed79
DV		 3551
3552 I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
3553 I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
3554 ~dev_priv->pm_rps_events);
3555 /* Complete PM interrupt masking here doesn't race with the rps work
3556 * item again unmasking PM interrupts because that is using a different
3557 * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
3558 * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
3559 * gen8_enable_rps will clean up. */
3560
3561 spin_lock_irq(&dev_priv->irq_lock);
3562 dev_priv->rps.pm_iir = 0;
3563 spin_unlock_irq(&dev_priv->irq_lock);
3564
3565 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
0961021a
BW		 3566}
3567
44fc7d5c 3568static void gen6_disable_rps_interrupts(struct drm_device *dev)
2b4e57bd
ED		 3569{
3570 struct drm_i915_private *dev_priv = dev->dev_private;
3571
2b4e57bd 3572 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
a6706b45
D		 3573 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3574 ~dev_priv->pm_rps_events);
2b4e57bd
ED		 3575 /* Complete PM interrupt masking here doesn't race with the rps work
3576 * item again unmasking PM interrupts because that is using a different
3577 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3578 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3579
59cdb63d 3580 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3 3581 dev_priv->rps.pm_iir = 0;
59cdb63d 3582 spin_unlock_irq(&dev_priv->irq_lock);
2b4e57bd 3583
a6706b45 3584 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
2b4e57bd
ED		 3585}
3586
44fc7d5c 3587static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 3588{
3589 struct drm_i915_private *dev_priv = dev->dev_private;
3590
3591 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 3592 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
d20d4f0c 3593
0961021a
BW		 3594 if (IS_BROADWELL(dev))
3595 gen8_disable_rps_interrupts(dev);
3596 else
3597 gen6_disable_rps_interrupts(dev);
44fc7d5c
DV		 3598}
3599
38807746
D		 3600static void cherryview_disable_rps(struct drm_device *dev)
3601{
3602 struct drm_i915_private *dev_priv = dev->dev_private;
3603
3604 I915_WRITE(GEN6_RC_CONTROL, 0);
3497a562
D		 3605
3606 gen8_disable_rps_interrupts(dev);
38807746
D		 3607}
3608
44fc7d5c
DV		 3609static void valleyview_disable_rps(struct drm_device *dev)
3610{
3611 struct drm_i915_private *dev_priv = dev->dev_private;
3612
98a2e5f9
D		 3613 /* we're doing forcewake before Disabling RC6,
3614 * This what the BIOS expects when going into suspend */
3615 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3616
44fc7d5c 3617 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 3618
98a2e5f9
D		 3619 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3620
44fc7d5c 3621 gen6_disable_rps_interrupts(dev);
d20d4f0c
JB		 3622}
3623
dc39fff7
BW		 3624static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3625{
91ca689a
ID		 3626 if (IS_VALLEYVIEW(dev)) {
3627 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
3628 mode = GEN6_RC_CTL_RC6_ENABLE;
3629 else
3630 mode = 0;
3631 }
58abf1da
RV		 3632 if (HAS_RC6p(dev))
3633 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
3634 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3635 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3636 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3637
3638 else
3639 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
3640 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
dc39fff7
BW		 3641}
3642
e6069ca8 3643static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 3644{
eb4926e4
DL		 3645 /* No RC6 before Ironlake */
3646 if (INTEL_INFO(dev)->gen < 5)
3647 return 0;
3648
e6069ca8
ID		 3649 /* RC6 is only on Ironlake mobile not on desktop */
3650 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
3651 return 0;
3652
456470eb 3653 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 3654 if (enable_rc6 >= 0) {
3655 int mask;
3656
58abf1da 3657 if (HAS_RC6p(dev))
e6069ca8
ID		 3658 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
3659 INTEL_RC6pp_ENABLE;
3660 else
3661 mask = INTEL_RC6_ENABLE;
3662
3663 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 3664 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3665 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 3666
3667 return enable_rc6 & mask;
3668 }
2b4e57bd 3669
6567d748
CW		 3670 /* Disable RC6 on Ironlake */
3671 if (INTEL_INFO(dev)->gen == 5)
3672 return 0;
2b4e57bd 3673
8bade1ad 3674 if (IS_IVYBRIDGE(dev))
cca84a1f 3675 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 3676
3677 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 3678}
3679
e6069ca8
ID		 3680int intel_enable_rc6(const struct drm_device *dev)
3681{
3682 return i915.enable_rc6;
3683}
3684
0961021a
BW		 3685static void gen8_enable_rps_interrupts(struct drm_device *dev)
3686{
3687 struct drm_i915_private *dev_priv = dev->dev_private;
3688
3689 spin_lock_irq(&dev_priv->irq_lock);
3690 WARN_ON(dev_priv->rps.pm_iir);
480c8033 3691 gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
0961021a
BW		 3692 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3693 spin_unlock_irq(&dev_priv->irq_lock);
3694}
3695
44fc7d5c
DV		 3696static void gen6_enable_rps_interrupts(struct drm_device *dev)
3697{
3698 struct drm_i915_private *dev_priv = dev->dev_private;
3699
3700 spin_lock_irq(&dev_priv->irq_lock);
a0b3335a 3701 WARN_ON(dev_priv->rps.pm_iir);
480c8033 3702 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
a6706b45 3703 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
44fc7d5c 3704 spin_unlock_irq(&dev_priv->irq_lock);
44fc7d5c
DV		 3705}
3706
3280e8b0
BW		 3707static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)
3708{
3709 /* All of these values are in units of 50MHz */
3710 dev_priv->rps.cur_freq = 0;
3711 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3712 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3713 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
3714 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
3715 /* XXX: only BYT has a special efficient freq */
3716 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
3717 /* hw_max = RP0 until we check for overclocking */
3718 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3719
3720 /* Preserve min/max settings in case of re-init */
3721 if (dev_priv->rps.max_freq_softlimit == 0)
3722 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3723
3724 if (dev_priv->rps.min_freq_softlimit == 0)
3725 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3726}
3727
6edee7f3
BW		 3728static void gen8_enable_rps(struct drm_device *dev)
3729{
3730 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 3731 struct intel_engine_cs *ring;
6edee7f3
BW		 3732 uint32_t rc6_mask = 0, rp_state_cap;
3733 int unused;
3734
3735 /* 1a: Software RC state - RC0 */
3736 I915_WRITE(GEN6_RC_STATE, 0);
3737
3738 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3739 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
c8d9a590 3740 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3741
3742 /* 2a: Disable RC states. */
3743 I915_WRITE(GEN6_RC_CONTROL, 0);
3744
3745 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3280e8b0 3746 parse_rp_state_cap(dev_priv, rp_state_cap);
6edee7f3
BW		 3747
3748 /* 2b: Program RC6 thresholds.*/
3749 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3750 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3751 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3752 for_each_ring(ring, dev_priv, unused)
3753 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3754 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 3755 if (IS_BROADWELL(dev))
3756 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
3757 else
3758 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 3759
3760 /* 3: Enable RC6 */
3761 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3762 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 3763 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 3764 if (IS_BROADWELL(dev))
3765 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3766 GEN7_RC_CTL_TO_MODE |
3767 rc6_mask);
3768 else
3769 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3770 GEN6_RC_CTL_EI_MODE(1) |
3771 rc6_mask);
6edee7f3
BW		 3772
3773 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 3774 I915_WRITE(GEN6_RPNSWREQ,
3775 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3776 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3777 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 3778 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3779 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3780
3781 /* Docs recommend 900MHz, and 300 MHz respectively */
3782 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3783 dev_priv->rps.max_freq_softlimit << 24 |
3784 dev_priv->rps.min_freq_softlimit << 16);
3785
3786 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3787 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3788 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3789 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3790
3791 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 3792
3793 /* 5: Enable RPS */
7526ed79
DV		 3794 I915_WRITE(GEN6_RP_CONTROL,
3795 GEN6_RP_MEDIA_TURBO |
3796 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3797 GEN6_RP_MEDIA_IS_GFX |
3798 GEN6_RP_ENABLE |
3799 GEN6_RP_UP_BUSY_AVG |
3800 GEN6_RP_DOWN_IDLE_AVG);
3801
3802 /* 6: Ring frequency + overclocking (our driver does this later */
3803
6edee7f3 3804 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
7526ed79
DV		 3805
3806 gen8_enable_rps_interrupts(dev);
6edee7f3 3807
c8d9a590 3808 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3809}
3810
79f5b2c7 3811static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 3812{
79f5b2c7 3813 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 3814 struct intel_engine_cs *ring;
2a5913a8 3815 u32 rp_state_cap;
d060c169 3816 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 3817 u32 gtfifodbg;
2b4e57bd 3818 int rc6_mode;
42c0526c 3819 int i, ret;
2b4e57bd 3820
4fc688ce 3821 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3822
2b4e57bd
ED		 3823 /* Here begins a magic sequence of register writes to enable
3824 * auto-downclocking.
3825 *
3826 * Perhaps there might be some value in exposing these to
3827 * userspace...
3828 */
3829 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 3830
3831 /* Clear the DBG now so we don't confuse earlier errors */
3832 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3833 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3834 I915_WRITE(GTFIFODBG, gtfifodbg);
3835 }
3836
c8d9a590 3837 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 3838
7b9e0ae6 3839 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7b9e0ae6 3840
3280e8b0 3841 parse_rp_state_cap(dev_priv, rp_state_cap);
dd0a1aa1 3842
2b4e57bd
ED		 3843 /* disable the counters and set deterministic thresholds */
3844 I915_WRITE(GEN6_RC_CONTROL, 0);
3845
3846 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3847 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3848 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3849 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3850 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3851
b4519513
CW		 3852 for_each_ring(ring, dev_priv, i)
3853 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 3854
3855 I915_WRITE(GEN6_RC_SLEEP, 0);
3856 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 3857 if (IS_IVYBRIDGE(dev))
351aa566
SM		 3858 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3859 else
3860 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 3861 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 3862 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3863
5a7dc92a 3864 /* Check if we are enabling RC6 */
2b4e57bd
ED		 3865 rc6_mode = intel_enable_rc6(dev_priv->dev);
3866 if (rc6_mode & INTEL_RC6_ENABLE)
3867 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3868
5a7dc92a
ED		 3869 /* We don't use those on Haswell */
3870 if (!IS_HASWELL(dev)) {
3871 if (rc6_mode & INTEL_RC6p_ENABLE)
3872 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 3873
5a7dc92a
ED		 3874 if (rc6_mode & INTEL_RC6pp_ENABLE)
3875 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3876 }
2b4e57bd 3877
dc39fff7 3878 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 3879
3880 I915_WRITE(GEN6_RC_CONTROL,
3881 rc6_mask |
3882 GEN6_RC_CTL_EI_MODE(1) |
3883 GEN6_RC_CTL_HW_ENABLE);
3884
dd75fdc8
CW		 3885 /* Power down if completely idle for over 50ms */
3886 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 3887 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 3888
42c0526c 3889 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 3890 if (ret)
42c0526c 3891 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 3892
3893 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3894 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3895 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 3896 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 3897 (pcu_mbox & 0xff) * 50);
b39fb297 3898 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 3899 }
3900
dd75fdc8 3901 dev_priv->rps.power = HIGH_POWER; /* force a reset */
b39fb297 3902 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
2b4e57bd 3903
44fc7d5c 3904 gen6_enable_rps_interrupts(dev);
2b4e57bd 3905
31643d54
BW		 3906 rc6vids = 0;
3907 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3908 if (IS_GEN6(dev) && ret) {
3909 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3910 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3911 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3912 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3913 rc6vids &= 0xffff00;
3914 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3915 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3916 if (ret)
3917 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3918 }
3919
c8d9a590 3920 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 3921}
3922
c2bc2fc5 3923static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 3924{
79f5b2c7 3925 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 3926 int min_freq = 15;
3ebecd07
CW		 3927 unsigned int gpu_freq;
3928 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd 3929 int scaling_factor = 180;
eda79642 3930 struct cpufreq_policy *policy;
2b4e57bd 3931
4fc688ce 3932 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3933
eda79642
BW		 3934 policy = cpufreq_cpu_get(0);
3935 if (policy) {
3936 max_ia_freq = policy->cpuinfo.max_freq;
3937 cpufreq_cpu_put(policy);
3938 } else {
3939 /*
3940 * Default to measured freq if none found, PCU will ensure we
3941 * don't go over
3942 */
2b4e57bd 3943 max_ia_freq = tsc_khz;
eda79642 3944 }
2b4e57bd
ED		 3945
3946 /* Convert from kHz to MHz */
3947 max_ia_freq /= 1000;
3948
153b4b95 3949 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 3950 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3951 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 3952
2b4e57bd
ED		 3953 /*
3954 * For each potential GPU frequency, load a ring frequency we'd like
3955 * to use for memory access. We do this by specifying the IA frequency
3956 * the PCU should use as a reference to determine the ring frequency.
3957 */
b39fb297 3958 for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
2b4e57bd 3959 gpu_freq--) {
b39fb297 3960 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
3ebecd07
CW		 3961 unsigned int ia_freq = 0, ring_freq = 0;
3962
46c764d4
BW		 3963 if (INTEL_INFO(dev)->gen >= 8) {
3964 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3965 ring_freq = max(min_ring_freq, gpu_freq);
3966 } else if (IS_HASWELL(dev)) {
f6aca45c 3967 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 3968 ring_freq = max(min_ring_freq, ring_freq);
3969 /* leave ia_freq as the default, chosen by cpufreq */
3970 } else {
3971 /* On older processors, there is no separate ring
3972 * clock domain, so in order to boost the bandwidth
3973 * of the ring, we need to upclock the CPU (ia_freq).
3974 *
3975 * For GPU frequencies less than 750MHz,
3976 * just use the lowest ring freq.
3977 */
3978 if (gpu_freq < min_freq)
3979 ia_freq = 800;
3980 else
3981 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3982 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3983 }
2b4e57bd 3984
42c0526c
BW		 3985 sandybridge_pcode_write(dev_priv,
3986 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 3987 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3988 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3989 gpu_freq);
2b4e57bd 3990 }
2b4e57bd
ED		 3991}
3992
c2bc2fc5
ID		 3993void gen6_update_ring_freq(struct drm_device *dev)
3994{
3995 struct drm_i915_private *dev_priv = dev->dev_private;
3996
3997 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
3998 return;
3999
4000 mutex_lock(&dev_priv->rps.hw_lock);
4001 __gen6_update_ring_freq(dev);
4002 mutex_unlock(&dev_priv->rps.hw_lock);
4003}
4004
03af2045 4005static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 4006{
4007 u32 val, rp0;
4008
4009 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4010 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4011
4012 return rp0;
4013}
4014
4015static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4016{
4017 u32 val, rpe;
4018
4019 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
4020 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
4021
4022 return rpe;
4023}
4024
7707df4a
D		 4025static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
4026{
4027 u32 val, rp1;
4028
4029 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4030 rp1 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4031
4032 return rp1;
4033}
4034
03af2045 4035static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 4036{
4037 u32 val, rpn;
4038
4039 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4040 rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK;
4041 return rpn;
4042}
4043
f8f2b001
D		 4044static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
4045{
4046 u32 val, rp1;
4047
4048 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4049
4050 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
4051
4052 return rp1;
4053}
4054
03af2045 4055static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 4056{
4057 u32 val, rp0;
4058
64936258 4059 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 4060
4061 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
4062 /* Clamp to max */
4063 rp0 = min_t(u32, rp0, 0xea);
4064
4065 return rp0;
4066}
4067
4068static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4069{
4070 u32 val, rpe;
4071
64936258 4072 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 4073 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 4074 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 4075 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4076
4077 return rpe;
4078}
4079
03af2045 4080static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 4081{
64936258 4082 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 4083}
4084
ae48434c
ID		 4085/* Check that the pctx buffer wasn't move under us. */
4086static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
4087{
4088 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4089
4090 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
4091 dev_priv->vlv_pctx->stolen->start);
4092}
4093
38807746
D		 4094
4095/* Check that the pcbr address is not empty. */
4096static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
4097{
4098 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4099
4100 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
4101}
4102
4103static void cherryview_setup_pctx(struct drm_device *dev)
4104{
4105 struct drm_i915_private *dev_priv = dev->dev_private;
4106 unsigned long pctx_paddr, paddr;
4107 struct i915_gtt *gtt = &dev_priv->gtt;
4108 u32 pcbr;
4109 int pctx_size = 32*1024;
4110
4111 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4112
4113 pcbr = I915_READ(VLV_PCBR);
4114 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
4115 paddr = (dev_priv->mm.stolen_base +
4116 (gtt->stolen_size - pctx_size));
4117
4118 pctx_paddr = (paddr & (~4095));
4119 I915_WRITE(VLV_PCBR, pctx_paddr);
4120 }
4121}
4122
c9cddffc
JB		 4123static void valleyview_setup_pctx(struct drm_device *dev)
4124{
4125 struct drm_i915_private *dev_priv = dev->dev_private;
4126 struct drm_i915_gem_object *pctx;
4127 unsigned long pctx_paddr;
4128 u32 pcbr;
4129 int pctx_size = 24*1024;
4130
17b0c1f7
ID		 4131 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4132
c9cddffc
JB		 4133 pcbr = I915_READ(VLV_PCBR);
4134 if (pcbr) {
4135 /* BIOS set it up already, grab the pre-alloc'd space */
4136 int pcbr_offset;
4137
4138 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4139 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4140 pcbr_offset,
190d6cd5 4141 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 4142 pctx_size);
4143 goto out;
4144 }
4145
4146 /*
4147 * From the Gunit register HAS:
4148 * The Gfx driver is expected to program this register and ensure
4149 * proper allocation within Gfx stolen memory. For example, this
4150 * register should be programmed such than the PCBR range does not
4151 * overlap with other ranges, such as the frame buffer, protected
4152 * memory, or any other relevant ranges.
4153 */
4154 pctx = i915_gem_object_create_stolen(dev, pctx_size);
4155 if (!pctx) {
4156 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4157 return;
4158 }
4159
4160 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4161 I915_WRITE(VLV_PCBR, pctx_paddr);
4162
4163out:
4164 dev_priv->vlv_pctx = pctx;
4165}
4166
ae48434c
ID		 4167static void valleyview_cleanup_pctx(struct drm_device *dev)
4168{
4169 struct drm_i915_private *dev_priv = dev->dev_private;
4170
4171 if (WARN_ON(!dev_priv->vlv_pctx))
4172 return;
4173
4174 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
4175 dev_priv->vlv_pctx = NULL;
4176}
4177
4e80519e
ID		 4178static void valleyview_init_gt_powersave(struct drm_device *dev)
4179{
4180 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 4181 u32 val;
4e80519e
ID		 4182
4183 valleyview_setup_pctx(dev);
4184
4185 mutex_lock(&dev_priv->rps.hw_lock);
4186
2bb25c17
VS		 4187 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4188 switch ((val >> 6) & 3) {
4189 case 0:
4190 case 1:
4191 dev_priv->mem_freq = 800;
4192 break;
4193 case 2:
4194 dev_priv->mem_freq = 1066;
4195 break;
4196 case 3:
4197 dev_priv->mem_freq = 1333;
4198 break;
4199 }
4200 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
4201
4e80519e
ID		 4202 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
4203 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4204 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4205 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4206 dev_priv->rps.max_freq);
4207
4208 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
4209 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4210 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4211 dev_priv->rps.efficient_freq);
4212
f8f2b001
D		 4213 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
4214 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
4215 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4216 dev_priv->rps.rp1_freq);
4217
4e80519e
ID		 4218 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
4219 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4220 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4221 dev_priv->rps.min_freq);
4222
4223 /* Preserve min/max settings in case of re-init */
4224 if (dev_priv->rps.max_freq_softlimit == 0)
4225 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4226
4227 if (dev_priv->rps.min_freq_softlimit == 0)
4228 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4229
4230 mutex_unlock(&dev_priv->rps.hw_lock);
4231}
4232
38807746
D		 4233static void cherryview_init_gt_powersave(struct drm_device *dev)
4234{
2b6b3a09 4235 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 4236 u32 val;
2b6b3a09 4237
38807746 4238 cherryview_setup_pctx(dev);
2b6b3a09
D		 4239
4240 mutex_lock(&dev_priv->rps.hw_lock);
4241
2bb25c17
VS		 4242 val = vlv_punit_read(dev_priv, CCK_FUSE_REG);
4243 switch ((val >> 2) & 0x7) {
4244 case 0:
4245 case 1:
4246 dev_priv->rps.cz_freq = 200;
4247 dev_priv->mem_freq = 1600;
4248 break;
4249 case 2:
4250 dev_priv->rps.cz_freq = 267;
4251 dev_priv->mem_freq = 1600;
4252 break;
4253 case 3:
4254 dev_priv->rps.cz_freq = 333;
4255 dev_priv->mem_freq = 2000;
4256 break;
4257 case 4:
4258 dev_priv->rps.cz_freq = 320;
4259 dev_priv->mem_freq = 1600;
4260 break;
4261 case 5:
4262 dev_priv->rps.cz_freq = 400;
4263 dev_priv->mem_freq = 1600;
4264 break;
4265 }
4266 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
4267
2b6b3a09
D		 4268 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
4269 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4270 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4271 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4272 dev_priv->rps.max_freq);
4273
4274 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
4275 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4276 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4277 dev_priv->rps.efficient_freq);
4278
7707df4a
D		 4279 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
4280 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
4281 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4282 dev_priv->rps.rp1_freq);
4283
2b6b3a09
D		 4284 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
4285 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4286 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4287 dev_priv->rps.min_freq);
4288
1c14762d
VS		 4289 WARN_ONCE((dev_priv->rps.max_freq |
4290 dev_priv->rps.efficient_freq |
4291 dev_priv->rps.rp1_freq |
4292 dev_priv->rps.min_freq) & 1,
4293 "Odd GPU freq values\n");
4294
2b6b3a09
D		 4295 /* Preserve min/max settings in case of re-init */
4296 if (dev_priv->rps.max_freq_softlimit == 0)
4297 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4298
4299 if (dev_priv->rps.min_freq_softlimit == 0)
4300 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4301
4302 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 4303}
4304
4e80519e
ID		 4305static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
4306{
4307 valleyview_cleanup_pctx(dev);
4308}
4309
38807746
D		 4310static void cherryview_enable_rps(struct drm_device *dev)
4311{
4312 struct drm_i915_private *dev_priv = dev->dev_private;
4313 struct intel_engine_cs *ring;
2b6b3a09 4314 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 4315 int i;
4316
4317 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4318
4319 gtfifodbg = I915_READ(GTFIFODBG);
4320 if (gtfifodbg) {
4321 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4322 gtfifodbg);
4323 I915_WRITE(GTFIFODBG, gtfifodbg);
4324 }
4325
4326 cherryview_check_pctx(dev_priv);
4327
4328 /* 1a & 1b: Get forcewake during program sequence. Although the driver
4329 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4330 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4331
4332 /* 2a: Program RC6 thresholds.*/
4333 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4334 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4335 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4336
4337 for_each_ring(ring, dev_priv, i)
4338 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4339 I915_WRITE(GEN6_RC_SLEEP, 0);
4340
4341 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4342
4343 /* allows RC6 residency counter to work */
4344 I915_WRITE(VLV_COUNTER_CONTROL,
4345 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4346 VLV_MEDIA_RC6_COUNT_EN |
4347 VLV_RENDER_RC6_COUNT_EN));
4348
4349 /* For now we assume BIOS is allocating and populating the PCBR */
4350 pcbr = I915_READ(VLV_PCBR);
4351
4352 DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr);
4353
4354 /* 3: Enable RC6 */
4355 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
4356 (pcbr >> VLV_PCBR_ADDR_SHIFT))
4357 rc6_mode = GEN6_RC_CTL_EI_MODE(1);
4358
4359 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4360
2b6b3a09
D		 4361 /* 4 Program defaults and thresholds for RPS*/
4362 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4363 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4364 I915_WRITE(GEN6_RP_UP_EI, 66000);
4365 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4366
4367 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4368
7405f42c
TR		 4369 /* WaDisablePwrmtrEvent:chv (pre-production hw) */
4370 I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
4371 I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
4372
2b6b3a09
D		 4373 /* 5: Enable RPS */
4374 I915_WRITE(GEN6_RP_CONTROL,
4375 GEN6_RP_MEDIA_HW_NORMAL_MODE |
7405f42c 4376 GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
2b6b3a09
D		 4377 GEN6_RP_ENABLE |
4378 GEN6_RP_UP_BUSY_AVG |
4379 GEN6_RP_DOWN_IDLE_AVG);
4380
4381 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4382
4383 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4384 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4385
4386 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4387 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4388 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4389 dev_priv->rps.cur_freq);
4390
4391 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4392 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4393 dev_priv->rps.efficient_freq);
4394
4395 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4396
3497a562
D		 4397 gen8_enable_rps_interrupts(dev);
4398
38807746
D		 4399 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4400}
4401
0a073b84
JB		 4402static void valleyview_enable_rps(struct drm_device *dev)
4403{
4404 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4405 struct intel_engine_cs *ring;
2a5913a8 4406 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 4407 int i;
4408
4409 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4410
ae48434c
ID		 4411 valleyview_check_pctx(dev_priv);
4412
0a073b84 4413 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 4414 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4415 gtfifodbg);
0a073b84
JB		 4416 I915_WRITE(GTFIFODBG, gtfifodbg);
4417 }
4418
c8d9a590
D		 4419 /* If VLV, Forcewake all wells, else re-direct to regular path */
4420 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 4421
4422 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4423 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4424 I915_WRITE(GEN6_RP_UP_EI, 66000);
4425 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4426
4427 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
31685c25 4428 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
0a073b84
JB		 4429
4430 I915_WRITE(GEN6_RP_CONTROL,
4431 GEN6_RP_MEDIA_TURBO |
4432 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4433 GEN6_RP_MEDIA_IS_GFX |
4434 GEN6_RP_ENABLE |
4435 GEN6_RP_UP_BUSY_AVG |
4436 GEN6_RP_DOWN_IDLE_CONT);
4437
4438 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4439 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4440 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4441
4442 for_each_ring(ring, dev_priv, i)
4443 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4444
2f0aa304 4445 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 4446
4447 /* allows RC6 residency counter to work */
49798eb2 4448 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 4449 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
4450 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 4451 VLV_MEDIA_RC6_COUNT_EN |
4452 VLV_RENDER_RC6_COUNT_EN));
31685c25 4453
a2b23fe0 4454 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 4455 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 4456
4457 intel_print_rc6_info(dev, rc6_mode);
4458
a2b23fe0 4459 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 4460
64936258 4461 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 4462
4463 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4464 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4465
b39fb297 4466 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 4467 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
b39fb297
BW		 4468 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4469 dev_priv->rps.cur_freq);
0a073b84 4470
73008b98 4471 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
b39fb297
BW		 4472 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4473 dev_priv->rps.efficient_freq);
0a073b84 4474
b39fb297 4475 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 4476
44fc7d5c 4477 gen6_enable_rps_interrupts(dev);
0a073b84 4478
c8d9a590 4479 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 4480}
4481
930ebb46 4482void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 4483{
4484 struct drm_i915_private *dev_priv = dev->dev_private;
4485
3e373948 4486 if (dev_priv->ips.renderctx) {
d7f46fc4 4487 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
3e373948
DV		 4488 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4489 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 4490 }
4491
3e373948 4492 if (dev_priv->ips.pwrctx) {
d7f46fc4 4493 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
3e373948
DV		 4494 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4495 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 4496 }
4497}
4498
930ebb46 4499static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 4500{
4501 struct drm_i915_private *dev_priv = dev->dev_private;
4502
4503 if (I915_READ(PWRCTXA)) {
4504 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4505 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4506 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4507 50);
4508
4509 I915_WRITE(PWRCTXA, 0);
4510 POSTING_READ(PWRCTXA);
4511
4512 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4513 POSTING_READ(RSTDBYCTL);
4514 }
2b4e57bd
ED		 4515}
4516
4517static int ironlake_setup_rc6(struct drm_device *dev)
4518{
4519 struct drm_i915_private *dev_priv = dev->dev_private;
4520
3e373948
DV		 4521 if (dev_priv->ips.renderctx == NULL)
4522 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4523 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 4524 return -ENOMEM;
4525
3e373948
DV		 4526 if (dev_priv->ips.pwrctx == NULL)
4527 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4528 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 4529 ironlake_teardown_rc6(dev);
4530 return -ENOMEM;
4531 }
4532
4533 return 0;
4534}
4535
930ebb46 4536static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 4537{
4538 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4539 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3e960501 4540 bool was_interruptible;
2b4e57bd
ED		 4541 int ret;
4542
4543 /* rc6 disabled by default due to repeated reports of hanging during
4544 * boot and resume.
4545 */
4546 if (!intel_enable_rc6(dev))
4547 return;
4548
79f5b2c7
DV		 4549 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4550
2b4e57bd 4551 ret = ironlake_setup_rc6(dev);
79f5b2c7 4552 if (ret)
2b4e57bd 4553 return;
2b4e57bd 4554
3e960501
CW		 4555 was_interruptible = dev_priv->mm.interruptible;
4556 dev_priv->mm.interruptible = false;
4557
2b4e57bd
ED		 4558 /*
4559 * GPU can automatically power down the render unit if given a page
4560 * to save state.
4561 */
6d90c952 4562 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 4563 if (ret) {
4564 ironlake_teardown_rc6(dev);
3e960501 4565 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 4566 return;
4567 }
4568
6d90c952
DV		 4569 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4570 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 4571 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
6d90c952
DV		 4572 MI_MM_SPACE_GTT |
4573 MI_SAVE_EXT_STATE_EN |
4574 MI_RESTORE_EXT_STATE_EN |
4575 MI_RESTORE_INHIBIT);
4576 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4577 intel_ring_emit(ring, MI_NOOP);
4578 intel_ring_emit(ring, MI_FLUSH);
4579 intel_ring_advance(ring);
2b4e57bd
ED		 4580
4581 /*
4582 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4583 * does an implicit flush, combined with MI_FLUSH above, it should be
4584 * safe to assume that renderctx is valid
4585 */
3e960501
CW		 4586 ret = intel_ring_idle(ring);
4587 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 4588 if (ret) {
def27a58 4589 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 4590 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 4591 return;
4592 }
4593
f343c5f6 4594 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
2b4e57bd 4595 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
dc39fff7 4596
91ca689a 4597 intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
2b4e57bd
ED		 4598}
4599
dde18883
ED		 4600static unsigned long intel_pxfreq(u32 vidfreq)
4601{
4602 unsigned long freq;
4603 int div = (vidfreq & 0x3f0000) >> 16;
4604 int post = (vidfreq & 0x3000) >> 12;
4605 int pre = (vidfreq & 0x7);
4606
4607 if (!pre)
4608 return 0;
4609
4610 freq = ((div * 133333) / ((1<<post) * pre));
4611
4612 return freq;
4613}
4614
eb48eb00
DV		 4615static const struct cparams {
4616 u16 i;
4617 u16 t;
4618 u16 m;
4619 u16 c;
4620} cparams[] = {
4621 { 1, 1333, 301, 28664 },
4622 { 1, 1066, 294, 24460 },
4623 { 1, 800, 294, 25192 },
4624 { 0, 1333, 276, 27605 },
4625 { 0, 1066, 276, 27605 },
4626 { 0, 800, 231, 23784 },
4627};
4628
f531dcb2 4629static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4630{
4631 u64 total_count, diff, ret;
4632 u32 count1, count2, count3, m = 0, c = 0;
4633 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4634 int i;
4635
02d71956
DV		 4636 assert_spin_locked(&mchdev_lock);
4637
20e4d407 4638 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 4639
4640 /* Prevent division-by-zero if we are asking too fast.
4641 * Also, we don't get interesting results if we are polling
4642 * faster than once in 10ms, so just return the saved value
4643 * in such cases.
4644 */
4645 if (diff1 <= 10)
20e4d407 4646 return dev_priv->ips.chipset_power;
eb48eb00
DV		 4647
4648 count1 = I915_READ(DMIEC);
4649 count2 = I915_READ(DDREC);
4650 count3 = I915_READ(CSIEC);
4651
4652 total_count = count1 + count2 + count3;
4653
4654 /* FIXME: handle per-counter overflow */
20e4d407
DV		 4655 if (total_count < dev_priv->ips.last_count1) {
4656 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 4657 diff += total_count;
4658 } else {
20e4d407 4659 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 4660 }
4661
4662 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 4663 if (cparams[i].i == dev_priv->ips.c_m &&
4664 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 4665 m = cparams[i].m;
4666 c = cparams[i].c;
4667 break;
4668 }
4669 }
4670
4671 diff = div_u64(diff, diff1);
4672 ret = ((m * diff) + c);
4673 ret = div_u64(ret, 10);
4674
20e4d407
DV		 4675 dev_priv->ips.last_count1 = total_count;
4676 dev_priv->ips.last_time1 = now;
eb48eb00 4677
20e4d407 4678 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 4679
4680 return ret;
4681}
4682
f531dcb2
CW		 4683unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4684{
3d13ef2e 4685 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 4686 unsigned long val;
4687
3d13ef2e 4688 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 4689 return 0;
4690
4691 spin_lock_irq(&mchdev_lock);
4692
4693 val = __i915_chipset_val(dev_priv);
4694
4695 spin_unlock_irq(&mchdev_lock);
4696
4697 return val;
4698}
4699
eb48eb00
DV		 4700unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4701{
4702 unsigned long m, x, b;
4703 u32 tsfs;
4704
4705 tsfs = I915_READ(TSFS);
4706
4707 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4708 x = I915_READ8(TR1);
4709
4710 b = tsfs & TSFS_INTR_MASK;
4711
4712 return ((m * x) / 127) - b;
4713}
4714
4715static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4716{
3d13ef2e 4717 struct drm_device *dev = dev_priv->dev;
eb48eb00
DV		 4718 static const struct v_table {
4719 u16 vd; /* in .1 mil */
4720 u16 vm; /* in .1 mil */
4721 } v_table[] = {
4722 { 0, 0, },
4723 { 375, 0, },
4724 { 500, 0, },
4725 { 625, 0, },
4726 { 750, 0, },
4727 { 875, 0, },
4728 { 1000, 0, },
4729 { 1125, 0, },
4730 { 4125, 3000, },
4731 { 4125, 3000, },
4732 { 4125, 3000, },
4733 { 4125, 3000, },
4734 { 4125, 3000, },
4735 { 4125, 3000, },
4736 { 4125, 3000, },
4737 { 4125, 3000, },
4738 { 4125, 3000, },
4739 { 4125, 3000, },
4740 { 4125, 3000, },
4741 { 4125, 3000, },
4742 { 4125, 3000, },
4743 { 4125, 3000, },
4744 { 4125, 3000, },
4745 { 4125, 3000, },
4746 { 4125, 3000, },
4747 { 4125, 3000, },
4748 { 4125, 3000, },
4749 { 4125, 3000, },
4750 { 4125, 3000, },
4751 { 4125, 3000, },
4752 { 4125, 3000, },
4753 { 4125, 3000, },
4754 { 4250, 3125, },
4755 { 4375, 3250, },
4756 { 4500, 3375, },
4757 { 4625, 3500, },
4758 { 4750, 3625, },
4759 { 4875, 3750, },
4760 { 5000, 3875, },
4761 { 5125, 4000, },
4762 { 5250, 4125, },
4763 { 5375, 4250, },
4764 { 5500, 4375, },
4765 { 5625, 4500, },
4766 { 5750, 4625, },
4767 { 5875, 4750, },
4768 { 6000, 4875, },
4769 { 6125, 5000, },
4770 { 6250, 5125, },
4771 { 6375, 5250, },
4772 { 6500, 5375, },
4773 { 6625, 5500, },
4774 { 6750, 5625, },
4775 { 6875, 5750, },
4776 { 7000, 5875, },
4777 { 7125, 6000, },
4778 { 7250, 6125, },
4779 { 7375, 6250, },
4780 { 7500, 6375, },
4781 { 7625, 6500, },
4782 { 7750, 6625, },
4783 { 7875, 6750, },
4784 { 8000, 6875, },
4785 { 8125, 7000, },
4786 { 8250, 7125, },
4787 { 8375, 7250, },
4788 { 8500, 7375, },
4789 { 8625, 7500, },
4790 { 8750, 7625, },
4791 { 8875, 7750, },
4792 { 9000, 7875, },
4793 { 9125, 8000, },
4794 { 9250, 8125, },
4795 { 9375, 8250, },
4796 { 9500, 8375, },
4797 { 9625, 8500, },
4798 { 9750, 8625, },
4799 { 9875, 8750, },
4800 { 10000, 8875, },
4801 { 10125, 9000, },
4802 { 10250, 9125, },
4803 { 10375, 9250, },
4804 { 10500, 9375, },
4805 { 10625, 9500, },
4806 { 10750, 9625, },
4807 { 10875, 9750, },
4808 { 11000, 9875, },
4809 { 11125, 10000, },
4810 { 11250, 10125, },
4811 { 11375, 10250, },
4812 { 11500, 10375, },
4813 { 11625, 10500, },
4814 { 11750, 10625, },
4815 { 11875, 10750, },
4816 { 12000, 10875, },
4817 { 12125, 11000, },
4818 { 12250, 11125, },
4819 { 12375, 11250, },
4820 { 12500, 11375, },
4821 { 12625, 11500, },
4822 { 12750, 11625, },
4823 { 12875, 11750, },
4824 { 13000, 11875, },
4825 { 13125, 12000, },
4826 { 13250, 12125, },
4827 { 13375, 12250, },
4828 { 13500, 12375, },
4829 { 13625, 12500, },
4830 { 13750, 12625, },
4831 { 13875, 12750, },
4832 { 14000, 12875, },
4833 { 14125, 13000, },
4834 { 14250, 13125, },
4835 { 14375, 13250, },
4836 { 14500, 13375, },
4837 { 14625, 13500, },
4838 { 14750, 13625, },
4839 { 14875, 13750, },
4840 { 15000, 13875, },
4841 { 15125, 14000, },
4842 { 15250, 14125, },
4843 { 15375, 14250, },
4844 { 15500, 14375, },
4845 { 15625, 14500, },
4846 { 15750, 14625, },
4847 { 15875, 14750, },
4848 { 16000, 14875, },
4849 { 16125, 15000, },
4850 };
3d13ef2e 4851 if (INTEL_INFO(dev)->is_mobile)
eb48eb00
DV		 4852 return v_table[pxvid].vm;
4853 else
4854 return v_table[pxvid].vd;
4855}
4856
02d71956 4857static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 4858{
5ed0bdf2 4859 u64 now, diff, diffms;
eb48eb00
DV		 4860 u32 count;
4861
02d71956 4862 assert_spin_locked(&mchdev_lock);
eb48eb00 4863
5ed0bdf2
TG		 4864 now = ktime_get_raw_ns();
4865 diffms = now - dev_priv->ips.last_time2;
4866 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 4867
4868 /* Don't divide by 0 */
eb48eb00
DV		 4869 if (!diffms)
4870 return;
4871
4872 count = I915_READ(GFXEC);
4873
20e4d407
DV		 4874 if (count < dev_priv->ips.last_count2) {
4875 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 4876 diff += count;
4877 } else {
20e4d407 4878 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 4879 }
4880
20e4d407
DV		 4881 dev_priv->ips.last_count2 = count;
4882 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 4883
4884 /* More magic constants... */
4885 diff = diff * 1181;
4886 diff = div_u64(diff, diffms * 10);
20e4d407 4887 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 4888}
4889
02d71956
DV		 4890void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4891{
3d13ef2e
DL		 4892 struct drm_device *dev = dev_priv->dev;
4893
4894 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 4895 return;
4896
9270388e 4897 spin_lock_irq(&mchdev_lock);
02d71956
DV		 4898
4899 __i915_update_gfx_val(dev_priv);
4900
9270388e 4901 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 4902}
4903
f531dcb2 4904static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4905{
4906 unsigned long t, corr, state1, corr2, state2;
4907 u32 pxvid, ext_v;
4908
02d71956
DV		 4909 assert_spin_locked(&mchdev_lock);
4910
b39fb297 4911 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
eb48eb00
DV		 4912 pxvid = (pxvid >> 24) & 0x7f;
4913 ext_v = pvid_to_extvid(dev_priv, pxvid);
4914
4915 state1 = ext_v;
4916
4917 t = i915_mch_val(dev_priv);
4918
4919 /* Revel in the empirically derived constants */
4920
4921 /* Correction factor in 1/100000 units */
4922 if (t > 80)
4923 corr = ((t * 2349) + 135940);
4924 else if (t >= 50)
4925 corr = ((t * 964) + 29317);
4926 else /* < 50 */
4927 corr = ((t * 301) + 1004);
4928
4929 corr = corr * ((150142 * state1) / 10000 - 78642);
4930 corr /= 100000;
20e4d407 4931 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 4932
4933 state2 = (corr2 * state1) / 10000;
4934 state2 /= 100; /* convert to mW */
4935
02d71956 4936 __i915_update_gfx_val(dev_priv);
eb48eb00 4937
20e4d407 4938 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 4939}
4940
f531dcb2
CW		 4941unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4942{
3d13ef2e 4943 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 4944 unsigned long val;
4945
3d13ef2e 4946 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 4947 return 0;
4948
4949 spin_lock_irq(&mchdev_lock);
4950
4951 val = __i915_gfx_val(dev_priv);
4952
4953 spin_unlock_irq(&mchdev_lock);
4954
4955 return val;
4956}
4957
eb48eb00
DV		 4958/**
4959 * i915_read_mch_val - return value for IPS use
4960 *
4961 * Calculate and return a value for the IPS driver to use when deciding whether
4962 * we have thermal and power headroom to increase CPU or GPU power budget.
4963 */
4964unsigned long i915_read_mch_val(void)
4965{
4966 struct drm_i915_private *dev_priv;
4967 unsigned long chipset_val, graphics_val, ret = 0;
4968
9270388e 4969 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4970 if (!i915_mch_dev)
4971 goto out_unlock;
4972 dev_priv = i915_mch_dev;
4973
f531dcb2
CW		 4974 chipset_val = __i915_chipset_val(dev_priv);
4975 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 4976
4977 ret = chipset_val + graphics_val;
4978
4979out_unlock:
9270388e 4980 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4981
4982 return ret;
4983}
4984EXPORT_SYMBOL_GPL(i915_read_mch_val);
4985
4986/**
4987 * i915_gpu_raise - raise GPU frequency limit
4988 *
4989 * Raise the limit; IPS indicates we have thermal headroom.
4990 */
4991bool i915_gpu_raise(void)
4992{
4993 struct drm_i915_private *dev_priv;
4994 bool ret = true;
4995
9270388e 4996 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4997 if (!i915_mch_dev) {
4998 ret = false;
4999 goto out_unlock;
5000 }
5001 dev_priv = i915_mch_dev;
5002
20e4d407
DV		 5003 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5004 dev_priv->ips.max_delay--;
eb48eb00
DV		 5005
5006out_unlock:
9270388e 5007 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5008
5009 return ret;
5010}
5011EXPORT_SYMBOL_GPL(i915_gpu_raise);
5012
5013/**
5014 * i915_gpu_lower - lower GPU frequency limit
5015 *
5016 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5017 * frequency maximum.
5018 */
5019bool i915_gpu_lower(void)
5020{
5021 struct drm_i915_private *dev_priv;
5022 bool ret = true;
5023
9270388e 5024 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5025 if (!i915_mch_dev) {
5026 ret = false;
5027 goto out_unlock;
5028 }
5029 dev_priv = i915_mch_dev;
5030
20e4d407
DV		 5031 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5032 dev_priv->ips.max_delay++;
eb48eb00
DV		 5033
5034out_unlock:
9270388e 5035 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5036
5037 return ret;
5038}
5039EXPORT_SYMBOL_GPL(i915_gpu_lower);
5040
5041/**
5042 * i915_gpu_busy - indicate GPU business to IPS
5043 *
5044 * Tell the IPS driver whether or not the GPU is busy.
5045 */
5046bool i915_gpu_busy(void)
5047{
5048 struct drm_i915_private *dev_priv;
a4872ba6 5049 struct intel_engine_cs *ring;
eb48eb00 5050 bool ret = false;
f047e395 5051 int i;
eb48eb00 5052
9270388e 5053 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5054 if (!i915_mch_dev)
5055 goto out_unlock;
5056 dev_priv = i915_mch_dev;
5057
f047e395
CW		 5058 for_each_ring(ring, dev_priv, i)
5059 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 5060
5061out_unlock:
9270388e 5062 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5063
5064 return ret;
5065}
5066EXPORT_SYMBOL_GPL(i915_gpu_busy);
5067
5068/**
5069 * i915_gpu_turbo_disable - disable graphics turbo
5070 *
5071 * Disable graphics turbo by resetting the max frequency and setting the
5072 * current frequency to the default.
5073 */
5074bool i915_gpu_turbo_disable(void)
5075{
5076 struct drm_i915_private *dev_priv;
5077 bool ret = true;
5078
9270388e 5079 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5080 if (!i915_mch_dev) {
5081 ret = false;
5082 goto out_unlock;
5083 }
5084 dev_priv = i915_mch_dev;
5085
20e4d407 5086 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 5087
20e4d407 5088 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 5089 ret = false;
5090
5091out_unlock:
9270388e 5092 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5093
5094 return ret;
5095}
5096EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5097
5098/**
5099 * Tells the intel_ips driver that the i915 driver is now loaded, if
5100 * IPS got loaded first.
5101 *
5102 * This awkward dance is so that neither module has to depend on the
5103 * other in order for IPS to do the appropriate communication of
5104 * GPU turbo limits to i915.
5105 */
5106static void
5107ips_ping_for_i915_load(void)
5108{
5109 void (*link)(void);
5110
5111 link = symbol_get(ips_link_to_i915_driver);
5112 if (link) {
5113 link();
5114 symbol_put(ips_link_to_i915_driver);
5115 }
5116}
5117
5118void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5119{
02d71956
DV		 5120 /* We only register the i915 ips part with intel-ips once everything is
5121 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 5122 spin_lock_irq(&mchdev_lock);
eb48eb00 5123 i915_mch_dev = dev_priv;
9270388e 5124 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5125
5126 ips_ping_for_i915_load();
5127}
5128
5129void intel_gpu_ips_teardown(void)
5130{
9270388e 5131 spin_lock_irq(&mchdev_lock);
eb48eb00 5132 i915_mch_dev = NULL;
9270388e 5133 spin_unlock_irq(&mchdev_lock);
eb48eb00 5134}
76c3552f 5135
8090c6b9 5136static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 5137{
5138 struct drm_i915_private *dev_priv = dev->dev_private;
5139 u32 lcfuse;
5140 u8 pxw[16];
5141 int i;
5142
5143 /* Disable to program */
5144 I915_WRITE(ECR, 0);
5145 POSTING_READ(ECR);
5146
5147 /* Program energy weights for various events */
5148 I915_WRITE(SDEW, 0x15040d00);
5149 I915_WRITE(CSIEW0, 0x007f0000);
5150 I915_WRITE(CSIEW1, 0x1e220004);
5151 I915_WRITE(CSIEW2, 0x04000004);
5152
5153 for (i = 0; i < 5; i++)
5154 I915_WRITE(PEW + (i * 4), 0);
5155 for (i = 0; i < 3; i++)
5156 I915_WRITE(DEW + (i * 4), 0);
5157
5158 /* Program P-state weights to account for frequency power adjustment */
5159 for (i = 0; i < 16; i++) {
5160 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5161 unsigned long freq = intel_pxfreq(pxvidfreq);
5162 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5163 PXVFREQ_PX_SHIFT;
5164 unsigned long val;
5165
5166 val = vid * vid;
5167 val *= (freq / 1000);
5168 val *= 255;
5169 val /= (127*127*900);
5170 if (val > 0xff)
5171 DRM_ERROR("bad pxval: %ld\n", val);
5172 pxw[i] = val;
5173 }
5174 /* Render standby states get 0 weight */
5175 pxw[14] = 0;
5176 pxw[15] = 0;
5177
5178 for (i = 0; i < 4; i++) {
5179 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5180 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5181 I915_WRITE(PXW + (i * 4), val);
5182 }
5183
5184 /* Adjust magic regs to magic values (more experimental results) */
5185 I915_WRITE(OGW0, 0);
5186 I915_WRITE(OGW1, 0);
5187 I915_WRITE(EG0, 0x00007f00);
5188 I915_WRITE(EG1, 0x0000000e);
5189 I915_WRITE(EG2, 0x000e0000);
5190 I915_WRITE(EG3, 0x68000300);
5191 I915_WRITE(EG4, 0x42000000);
5192 I915_WRITE(EG5, 0x00140031);
5193 I915_WRITE(EG6, 0);
5194 I915_WRITE(EG7, 0);
5195
5196 for (i = 0; i < 8; i++)
5197 I915_WRITE(PXWL + (i * 4), 0);
5198
5199 /* Enable PMON + select events */
5200 I915_WRITE(ECR, 0x80000019);
5201
5202 lcfuse = I915_READ(LCFUSE02);
5203
20e4d407 5204 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 5205}
5206
ae48434c
ID		 5207void intel_init_gt_powersave(struct drm_device *dev)
5208{
e6069ca8
ID		 5209 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
5210
38807746
D		 5211 if (IS_CHERRYVIEW(dev))
5212 cherryview_init_gt_powersave(dev);
5213 else if (IS_VALLEYVIEW(dev))
4e80519e 5214 valleyview_init_gt_powersave(dev);
ae48434c
ID		 5215}
5216
5217void intel_cleanup_gt_powersave(struct drm_device *dev)
5218{
38807746
D		 5219 if (IS_CHERRYVIEW(dev))
5220 return;
5221 else if (IS_VALLEYVIEW(dev))
4e80519e 5222 valleyview_cleanup_gt_powersave(dev);
ae48434c
ID		 5223}
5224
156c7ca0
JB		 5225/**
5226 * intel_suspend_gt_powersave - suspend PM work and helper threads
5227 * @dev: drm device
5228 *
5229 * We don't want to disable RC6 or other features here, we just want
5230 * to make sure any work we've queued has finished and won't bother
5231 * us while we're suspended.
5232 */
5233void intel_suspend_gt_powersave(struct drm_device *dev)
5234{
5235 struct drm_i915_private *dev_priv = dev->dev_private;
5236
5237 /* Interrupts should be disabled already to avoid re-arming. */
9df7575f 5238 WARN_ON(intel_irqs_enabled(dev_priv));
156c7ca0
JB		 5239
5240 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5241
5242 cancel_work_sync(&dev_priv->rps.work);
b47adc17
D		 5243
5244 /* Force GPU to min freq during suspend */
5245 gen6_rps_idle(dev_priv);
156c7ca0
JB		 5246}
5247
8090c6b9
DV		 5248void intel_disable_gt_powersave(struct drm_device *dev)
5249{
1a01ab3b
JB		 5250 struct drm_i915_private *dev_priv = dev->dev_private;
5251
fd0c0642 5252 /* Interrupts should be disabled already to avoid re-arming. */
9df7575f 5253 WARN_ON(intel_irqs_enabled(dev_priv));
fd0c0642 5254
930ebb46 5255 if (IS_IRONLAKE_M(dev)) {
8090c6b9 5256 ironlake_disable_drps(dev);
930ebb46 5257 ironlake_disable_rc6(dev);
38807746 5258 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 5259 intel_suspend_gt_powersave(dev);
e494837a 5260
4fc688ce 5261 mutex_lock(&dev_priv->rps.hw_lock);
38807746
D		 5262 if (IS_CHERRYVIEW(dev))
5263 cherryview_disable_rps(dev);
5264 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 5265 valleyview_disable_rps(dev);
5266 else
5267 gen6_disable_rps(dev);
c0951f0c 5268 dev_priv->rps.enabled = false;
4fc688ce 5269 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 5270 }
8090c6b9
DV		 5271}
5272
1a01ab3b
JB		 5273static void intel_gen6_powersave_work(struct work_struct *work)
5274{
5275 struct drm_i915_private *dev_priv =
5276 container_of(work, struct drm_i915_private,
5277 rps.delayed_resume_work.work);
5278 struct drm_device *dev = dev_priv->dev;
5279
4fc688ce 5280 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 5281
38807746
D		 5282 if (IS_CHERRYVIEW(dev)) {
5283 cherryview_enable_rps(dev);
5284 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 5285 valleyview_enable_rps(dev);
6edee7f3
BW		 5286 } else if (IS_BROADWELL(dev)) {
5287 gen8_enable_rps(dev);
c2bc2fc5 5288 __gen6_update_ring_freq(dev);
0a073b84
JB		 5289 } else {
5290 gen6_enable_rps(dev);
c2bc2fc5 5291 __gen6_update_ring_freq(dev);
0a073b84 5292 }
c0951f0c 5293 dev_priv->rps.enabled = true;
4fc688ce 5294 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 5295
5296 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 5297}
5298
8090c6b9
DV		 5299void intel_enable_gt_powersave(struct drm_device *dev)
5300{
1a01ab3b
JB		 5301 struct drm_i915_private *dev_priv = dev->dev_private;
5302
8090c6b9 5303 if (IS_IRONLAKE_M(dev)) {
dc1d0136 5304 mutex_lock(&dev->struct_mutex);
8090c6b9
DV		 5305 ironlake_enable_drps(dev);
5306 ironlake_enable_rc6(dev);
5307 intel_init_emon(dev);
dc1d0136 5308 mutex_unlock(&dev->struct_mutex);
38807746 5309 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 5310 /*
5311 * PCU communication is slow and this doesn't need to be
5312 * done at any specific time, so do this out of our fast path
5313 * to make resume and init faster.
c6df39b5
ID		 5314 *
5315 * We depend on the HW RC6 power context save/restore
5316 * mechanism when entering D3 through runtime PM suspend. So
5317 * disable RPM until RPS/RC6 is properly setup. We can only
5318 * get here via the driver load/system resume/runtime resume
5319 * paths, so the _noresume version is enough (and in case of
5320 * runtime resume it's necessary).
1a01ab3b 5321 */
c6df39b5
ID		 5322 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
5323 round_jiffies_up_relative(HZ)))
5324 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 5325 }
5326}
5327
c6df39b5
ID		 5328void intel_reset_gt_powersave(struct drm_device *dev)
5329{
5330 struct drm_i915_private *dev_priv = dev->dev_private;
5331
5332 dev_priv->rps.enabled = false;
5333 intel_enable_gt_powersave(dev);
5334}
5335
3107bd48
DV		 5336static void ibx_init_clock_gating(struct drm_device *dev)
5337{
5338 struct drm_i915_private *dev_priv = dev->dev_private;
5339
5340 /*
5341 * On Ibex Peak and Cougar Point, we need to disable clock
5342 * gating for the panel power sequencer or it will fail to
5343 * start up when no ports are active.
5344 */
5345 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5346}
5347
0e088b8f
VS		 5348static void g4x_disable_trickle_feed(struct drm_device *dev)
5349{
5350 struct drm_i915_private *dev_priv = dev->dev_private;
5351 int pipe;
5352
055e393f 5353 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 5354 I915_WRITE(DSPCNTR(pipe),
5355 I915_READ(DSPCNTR(pipe)) |
5356 DISPPLANE_TRICKLE_FEED_DISABLE);
1dba99f4 5357 intel_flush_primary_plane(dev_priv, pipe);
0e088b8f
VS		 5358 }
5359}
5360
017636cc
VS		 5361static void ilk_init_lp_watermarks(struct drm_device *dev)
5362{
5363 struct drm_i915_private *dev_priv = dev->dev_private;
5364
5365 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5366 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5367 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5368
5369 /*
5370 * Don't touch WM1S_LP_EN here.
5371 * Doing so could cause underruns.
5372 */
5373}
5374
1fa61106 5375static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5376{
5377 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5378 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5379
f1e8fa56
DL		 5380 /*
5381 * Required for FBC
5382 * WaFbcDisableDpfcClockGating:ilk
5383 */
4d47e4f5
DL		 5384 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5385 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5386 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5387
5388 I915_WRITE(PCH_3DCGDIS0,
5389 MARIUNIT_CLOCK_GATE_DISABLE |
5390 SVSMUNIT_CLOCK_GATE_DISABLE);
5391 I915_WRITE(PCH_3DCGDIS1,
5392 VFMUNIT_CLOCK_GATE_DISABLE);
5393
6f1d69b0
ED		 5394 /*
5395 * According to the spec the following bits should be set in
5396 * order to enable memory self-refresh
5397 * The bit 22/21 of 0x42004
5398 * The bit 5 of 0x42020
5399 * The bit 15 of 0x45000
5400 */
5401 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5402 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5403 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 5404 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5405 I915_WRITE(DISP_ARB_CTL,
5406 (I915_READ(DISP_ARB_CTL) |
5407 DISP_FBC_WM_DIS));
017636cc
VS		 5408
5409 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 5410
5411 /*
5412 * Based on the document from hardware guys the following bits
5413 * should be set unconditionally in order to enable FBC.
5414 * The bit 22 of 0x42000
5415 * The bit 22 of 0x42004
5416 * The bit 7,8,9 of 0x42020.
5417 */
5418 if (IS_IRONLAKE_M(dev)) {
4bb35334 5419 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 5420 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5421 I915_READ(ILK_DISPLAY_CHICKEN1) |
5422 ILK_FBCQ_DIS);
5423 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5424 I915_READ(ILK_DISPLAY_CHICKEN2) |
5425 ILK_DPARB_GATE);
6f1d69b0
ED		 5426 }
5427
4d47e4f5
DL		 5428 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5429
6f1d69b0
ED		 5430 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5431 I915_READ(ILK_DISPLAY_CHICKEN2) |
5432 ILK_ELPIN_409_SELECT);
5433 I915_WRITE(_3D_CHICKEN2,
5434 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5435 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 5436
ecdb4eb7 5437 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 5438 I915_WRITE(CACHE_MODE_0,
5439 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 5440
4e04632e
AG		 5441 /* WaDisable_RenderCache_OperationalFlush:ilk */
5442 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5443
0e088b8f 5444 g4x_disable_trickle_feed(dev);
bdad2b2f 5445
3107bd48
DV		 5446 ibx_init_clock_gating(dev);
5447}
5448
5449static void cpt_init_clock_gating(struct drm_device *dev)
5450{
5451 struct drm_i915_private *dev_priv = dev->dev_private;
5452 int pipe;
3f704fa2 5453 uint32_t val;
3107bd48
DV		 5454
5455 /*
5456 * On Ibex Peak and Cougar Point, we need to disable clock
5457 * gating for the panel power sequencer or it will fail to
5458 * start up when no ports are active.
5459 */
cd664078
JB		 5460 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5461 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5462 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 5463 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5464 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 5465 /* The below fixes the weird display corruption, a few pixels shifted
5466 * downward, on (only) LVDS of some HP laptops with IVY.
5467 */
055e393f 5468 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 5469 val = I915_READ(TRANS_CHICKEN2(pipe));
5470 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5471 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 5472 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 5473 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 5474 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5475 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5476 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 5477 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5478 }
3107bd48 5479 /* WADP0ClockGatingDisable */
055e393f 5480 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 5481 I915_WRITE(TRANS_CHICKEN1(pipe),
5482 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5483 }
6f1d69b0
ED		 5484}
5485
1d7aaa0c
DV		 5486static void gen6_check_mch_setup(struct drm_device *dev)
5487{
5488 struct drm_i915_private *dev_priv = dev->dev_private;
5489 uint32_t tmp;
5490
5491 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 5492 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
5493 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
5494 tmp);
1d7aaa0c
DV		 5495}
5496
1fa61106 5497static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5498{
5499 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5500 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5501
231e54f6 5502 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 5503
5504 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5505 I915_READ(ILK_DISPLAY_CHICKEN2) |
5506 ILK_ELPIN_409_SELECT);
5507
ecdb4eb7 5508 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 5509 I915_WRITE(_3D_CHICKEN,
5510 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5511
ecdb4eb7 5512 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 5513 if (IS_SNB_GT1(dev))
5514 I915_WRITE(GEN6_GT_MODE,
5515 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5516
4e04632e
AG		 5517 /* WaDisable_RenderCache_OperationalFlush:snb */
5518 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5519
8d85d272
VS		 5520 /*
5521 * BSpec recoomends 8x4 when MSAA is used,
5522 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5523 *
5524 * Note that PS/WM thread counts depend on the WIZ hashing
5525 * disable bit, which we don't touch here, but it's good
5526 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 5527 */
5528 I915_WRITE(GEN6_GT_MODE,
5529 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5530
017636cc 5531 ilk_init_lp_watermarks(dev);
6f1d69b0 5532
6f1d69b0 5533 I915_WRITE(CACHE_MODE_0,
50743298 5534 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 5535
5536 I915_WRITE(GEN6_UCGCTL1,
5537 I915_READ(GEN6_UCGCTL1) |
5538 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5539 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5540
5541 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5542 * gating disable must be set. Failure to set it results in
5543 * flickering pixels due to Z write ordering failures after
5544 * some amount of runtime in the Mesa "fire" demo, and Unigine
5545 * Sanctuary and Tropics, and apparently anything else with
5546 * alpha test or pixel discard.
5547 *
5548 * According to the spec, bit 11 (RCCUNIT) must also be set,
5549 * but we didn't debug actual testcases to find it out.
0f846f81 5550 *
ef59318c
VS		 5551 * WaDisableRCCUnitClockGating:snb
5552 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 5553 */
5554 I915_WRITE(GEN6_UCGCTL2,
5555 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5556 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5557
5eb146dd 5558 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 5559 I915_WRITE(_3D_CHICKEN3,
5560 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 5561
e927ecde
VS		 5562 /*
5563 * Bspec says:
5564 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
5565 * 3DSTATE_SF number of SF output attributes is more than 16."
5566 */
5567 I915_WRITE(_3D_CHICKEN3,
5568 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
5569
6f1d69b0
ED		 5570 /*
5571 * According to the spec the following bits should be
5572 * set in order to enable memory self-refresh and fbc:
5573 * The bit21 and bit22 of 0x42000
5574 * The bit21 and bit22 of 0x42004
5575 * The bit5 and bit7 of 0x42020
5576 * The bit14 of 0x70180
5577 * The bit14 of 0x71180
4bb35334
DL		 5578 *
5579 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 5580 */
5581 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5582 I915_READ(ILK_DISPLAY_CHICKEN1) |
5583 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5584 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5585 I915_READ(ILK_DISPLAY_CHICKEN2) |
5586 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 5587 I915_WRITE(ILK_DSPCLK_GATE_D,
5588 I915_READ(ILK_DSPCLK_GATE_D) |
5589 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5590 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 5591
0e088b8f 5592 g4x_disable_trickle_feed(dev);
f8f2ac9a 5593
3107bd48 5594 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5595
5596 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5597}
5598
5599static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5600{
5601 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5602
3aad9059 5603 /*
46680e0a 5604 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 5605 *
5606 * This actually overrides the dispatch
5607 * mode for all thread types.
5608 */
6f1d69b0
ED		 5609 reg &= ~GEN7_FF_SCHED_MASK;
5610 reg |= GEN7_FF_TS_SCHED_HW;
5611 reg |= GEN7_FF_VS_SCHED_HW;
5612 reg |= GEN7_FF_DS_SCHED_HW;
5613
5614 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5615}
5616
17a303ec
PZ		 5617static void lpt_init_clock_gating(struct drm_device *dev)
5618{
5619 struct drm_i915_private *dev_priv = dev->dev_private;
5620
5621 /*
5622 * TODO: this bit should only be enabled when really needed, then
5623 * disabled when not needed anymore in order to save power.
5624 */
5625 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5626 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5627 I915_READ(SOUTH_DSPCLK_GATE_D) |
5628 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 5629
5630 /* WADPOClockGatingDisable:hsw */
5631 I915_WRITE(_TRANSA_CHICKEN1,
5632 I915_READ(_TRANSA_CHICKEN1) |
5633 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 5634}
5635
7d708ee4
ID		 5636static void lpt_suspend_hw(struct drm_device *dev)
5637{
5638 struct drm_i915_private *dev_priv = dev->dev_private;
5639
5640 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5641 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5642
5643 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5644 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5645 }
5646}
5647
47c2bd97 5648static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 5649{
5650 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 5651 enum pipe pipe;
1020a5c2
BW		 5652
5653 I915_WRITE(WM3_LP_ILK, 0);
5654 I915_WRITE(WM2_LP_ILK, 0);
5655 I915_WRITE(WM1_LP_ILK, 0);
50ed5fbd 5656
ab57fff1 5657 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 5658 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 5659
ab57fff1 5660 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 5661 I915_WRITE(CHICKEN_PAR1_1,
5662 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5663
ab57fff1 5664 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 5665 for_each_pipe(dev_priv, pipe) {
07d27e20 5666 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 5667 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 5668 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 5669 }
63801f21 5670
ab57fff1
BW		 5671 /* WaVSRefCountFullforceMissDisable:bdw */
5672 /* WaDSRefCountFullforceMissDisable:bdw */
5673 I915_WRITE(GEN7_FF_THREAD_MODE,
5674 I915_READ(GEN7_FF_THREAD_MODE) &
5675 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 5676
295e8bb7
VS		 5677 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5678 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 5679
5680 /* WaDisableSDEUnitClockGating:bdw */
5681 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5682 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 5683
89d6b2b8 5684 lpt_init_clock_gating(dev);
1020a5c2
BW		 5685}
5686
cad2a2d7
ED		 5687static void haswell_init_clock_gating(struct drm_device *dev)
5688{
5689 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 5690
017636cc 5691 ilk_init_lp_watermarks(dev);
cad2a2d7 5692
f3fc4884
FJ		 5693 /* L3 caching of data atomics doesn't work -- disable it. */
5694 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5695 I915_WRITE(HSW_ROW_CHICKEN3,
5696 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5697
ecdb4eb7 5698 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 5699 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5700 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5701 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5702
e36ea7ff
VS		 5703 /* WaVSRefCountFullforceMissDisable:hsw */
5704 I915_WRITE(GEN7_FF_THREAD_MODE,
5705 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 5706
4e04632e
AG		 5707 /* WaDisable_RenderCache_OperationalFlush:hsw */
5708 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5709
fe27c606
CW		 5710 /* enable HiZ Raw Stall Optimization */
5711 I915_WRITE(CACHE_MODE_0_GEN7,
5712 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5713
ecdb4eb7 5714 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 5715 I915_WRITE(CACHE_MODE_1,
5716 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 5717
a12c4967
VS		 5718 /*
5719 * BSpec recommends 8x4 when MSAA is used,
5720 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5721 *
5722 * Note that PS/WM thread counts depend on the WIZ hashing
5723 * disable bit, which we don't touch here, but it's good
5724 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 5725 */
5726 I915_WRITE(GEN7_GT_MODE,
5727 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5728
ecdb4eb7 5729 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 5730 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5731
90a88643
PZ		 5732 /* WaRsPkgCStateDisplayPMReq:hsw */
5733 I915_WRITE(CHICKEN_PAR1_1,
5734 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 5735
17a303ec 5736 lpt_init_clock_gating(dev);
cad2a2d7
ED		 5737}
5738
1fa61106 5739static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5740{
5741 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 5742 uint32_t snpcr;
6f1d69b0 5743
017636cc 5744 ilk_init_lp_watermarks(dev);
6f1d69b0 5745
231e54f6 5746 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5747
ecdb4eb7 5748 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 5749 I915_WRITE(_3D_CHICKEN3,
5750 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5751
ecdb4eb7 5752 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 5753 I915_WRITE(IVB_CHICKEN3,
5754 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5755 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5756
ecdb4eb7 5757 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 5758 if (IS_IVB_GT1(dev))
5759 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5760 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 5761
4e04632e
AG		 5762 /* WaDisable_RenderCache_OperationalFlush:ivb */
5763 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5764
ecdb4eb7 5765 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 5766 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5767 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5768
ecdb4eb7 5769 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 5770 I915_WRITE(GEN7_L3CNTLREG1,
5771 GEN7_WA_FOR_GEN7_L3_CONTROL);
5772 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 5773 GEN7_WA_L3_CHICKEN_MODE);
5774 if (IS_IVB_GT1(dev))
5775 I915_WRITE(GEN7_ROW_CHICKEN2,
5776 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 5777 else {
5778 /* must write both registers */
5779 I915_WRITE(GEN7_ROW_CHICKEN2,
5780 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 5781 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5782 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 5783 }
6f1d69b0 5784
ecdb4eb7 5785 /* WaForceL3Serialization:ivb */
61939d97
JB		 5786 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5787 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5788
1b80a19a 5789 /*
0f846f81 5790 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5791 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 5792 */
5793 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 5794 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 5795
ecdb4eb7 5796 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 5797 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5798 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5799 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5800
0e088b8f 5801 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5802
5803 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 5804
22721343
CW		 5805 if (0) { /* causes HiZ corruption on ivb:gt1 */
5806 /* enable HiZ Raw Stall Optimization */
5807 I915_WRITE(CACHE_MODE_0_GEN7,
5808 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5809 }
116f2b6d 5810
ecdb4eb7 5811 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 5812 I915_WRITE(CACHE_MODE_1,
5813 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 5814
a607c1a4
VS		 5815 /*
5816 * BSpec recommends 8x4 when MSAA is used,
5817 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5818 *
5819 * Note that PS/WM thread counts depend on the WIZ hashing
5820 * disable bit, which we don't touch here, but it's good
5821 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 5822 */
5823 I915_WRITE(GEN7_GT_MODE,
5824 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5825
20848223
BW		 5826 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5827 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5828 snpcr |= GEN6_MBC_SNPCR_MED;
5829 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 5830
ab5c608b
BW		 5831 if (!HAS_PCH_NOP(dev))
5832 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5833
5834 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5835}
5836
1fa61106 5837static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5838{
5839 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 5840
d7fe0cc0 5841 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5842
ecdb4eb7 5843 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 5844 I915_WRITE(_3D_CHICKEN3,
5845 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5846
ecdb4eb7 5847 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 5848 I915_WRITE(IVB_CHICKEN3,
5849 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5850 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5851
fad7d36e 5852 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 5853 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 5854 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 5855 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5856 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 5857
4e04632e
AG		 5858 /* WaDisable_RenderCache_OperationalFlush:vlv */
5859 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5860
ecdb4eb7 5861 /* WaForceL3Serialization:vlv */
61939d97
JB		 5862 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5863 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5864
ecdb4eb7 5865 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 5866 I915_WRITE(GEN7_ROW_CHICKEN2,
5867 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5868
ecdb4eb7 5869 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 5870 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5871 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5872 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5873
46680e0a
VS		 5874 gen7_setup_fixed_func_scheduler(dev_priv);
5875
3c0edaeb 5876 /*
0f846f81 5877 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5878 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 5879 */
5880 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 5881 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 5882
c98f5062
AG		 5883 /* WaDisableL3Bank2xClockGate:vlv
5884 * Disabling L3 clock gating- MMIO 940c[25] = 1
5885 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
5886 I915_WRITE(GEN7_UCGCTL4,
5887 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 5888
e0d8d59b 5889 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 5890
afd58e79
VS		 5891 /*
5892 * BSpec says this must be set, even though
5893 * WaDisable4x2SubspanOptimization isn't listed for VLV.
5894 */
6b26c86d
DV		 5895 I915_WRITE(CACHE_MODE_1,
5896 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 5897
031994ee
VS		 5898 /*
5899 * WaIncreaseL3CreditsForVLVB0:vlv
5900 * This is the hardware default actually.
5901 */
5902 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
5903
2d809570 5904 /*
ecdb4eb7 5905 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 5906 * Disable clock gating on th GCFG unit to prevent a delay
5907 * in the reporting of vblank events.
5908 */
7a0d1eed 5909 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 5910}
5911
a4565da8
VS		 5912static void cherryview_init_clock_gating(struct drm_device *dev)
5913{
5914 struct drm_i915_private *dev_priv = dev->dev_private;
5915
5916 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5917
5918 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
dd811e70 5919
232ce337
VS		 5920 /* WaVSRefCountFullforceMissDisable:chv */
5921 /* WaDSRefCountFullforceMissDisable:chv */
5922 I915_WRITE(GEN7_FF_THREAD_MODE,
5923 I915_READ(GEN7_FF_THREAD_MODE) &
5924 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 5925
5926 /* WaDisableSemaphoreAndSyncFlipWait:chv */
5927 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5928 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 5929
5930 /* WaDisableCSUnitClockGating:chv */
5931 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5932 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 5933
5934 /* WaDisableSDEUnitClockGating:chv */
5935 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5936 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
e0d34ce7 5937
e4443e45
VS		 5938 /* WaDisableGunitClockGating:chv (pre-production hw) */
5939 I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
5940 GINT_DIS);
5941
5942 /* WaDisableFfDopClockGating:chv (pre-production hw) */
5943 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5944 _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
5945
5946 /* WaDisableDopClockGating:chv (pre-production hw) */
e4443e45
VS		 5947 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5948 GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
a4565da8
VS		 5949}
5950
1fa61106 5951static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5952{
5953 struct drm_i915_private *dev_priv = dev->dev_private;
5954 uint32_t dspclk_gate;
5955
5956 I915_WRITE(RENCLK_GATE_D1, 0);
5957 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5958 GS_UNIT_CLOCK_GATE_DISABLE |
5959 CL_UNIT_CLOCK_GATE_DISABLE);
5960 I915_WRITE(RAMCLK_GATE_D, 0);
5961 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5962 OVRUNIT_CLOCK_GATE_DISABLE |
5963 OVCUNIT_CLOCK_GATE_DISABLE;
5964 if (IS_GM45(dev))
5965 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5966 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 5967
5968 /* WaDisableRenderCachePipelinedFlush */
5969 I915_WRITE(CACHE_MODE_0,
5970 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 5971
4e04632e
AG		 5972 /* WaDisable_RenderCache_OperationalFlush:g4x */
5973 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5974
0e088b8f 5975 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5976}
5977
1fa61106 5978static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5979{
5980 struct drm_i915_private *dev_priv = dev->dev_private;
5981
5982 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5983 I915_WRITE(RENCLK_GATE_D2, 0);
5984 I915_WRITE(DSPCLK_GATE_D, 0);
5985 I915_WRITE(RAMCLK_GATE_D, 0);
5986 I915_WRITE16(DEUC, 0);
20f94967
VS		 5987 I915_WRITE(MI_ARB_STATE,
5988 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 5989
5990 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5991 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 5992}
5993
1fa61106 5994static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5995{
5996 struct drm_i915_private *dev_priv = dev->dev_private;
5997
5998 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5999 I965_RCC_CLOCK_GATE_DISABLE |
6000 I965_RCPB_CLOCK_GATE_DISABLE |
6001 I965_ISC_CLOCK_GATE_DISABLE |
6002 I965_FBC_CLOCK_GATE_DISABLE);
6003 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 6004 I915_WRITE(MI_ARB_STATE,
6005 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6006
6007 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6008 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6009}
6010
1fa61106 6011static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6012{
6013 struct drm_i915_private *dev_priv = dev->dev_private;
6014 u32 dstate = I915_READ(D_STATE);
6015
6016 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6017 DSTATE_DOT_CLOCK_GATING;
6018 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 6019
6020 if (IS_PINEVIEW(dev))
6021 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 6022
6023 /* IIR "flip pending" means done if this bit is set */
6024 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 6025
6026 /* interrupts should cause a wake up from C3 */
3299254f 6027 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 6028
6029 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6030 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 6031
6032 I915_WRITE(MI_ARB_STATE,
6033 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6034}
6035
1fa61106 6036static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6037{
6038 struct drm_i915_private *dev_priv = dev->dev_private;
6039
6040 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 6041
6042 /* interrupts should cause a wake up from C3 */
6043 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6044 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 6045
6046 I915_WRITE(MEM_MODE,
6047 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6048}
6049
1fa61106 6050static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6051{
6052 struct drm_i915_private *dev_priv = dev->dev_private;
6053
6054 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 6055
6056 I915_WRITE(MEM_MODE,
6057 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6058 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6059}
6060
6f1d69b0
ED		 6061void intel_init_clock_gating(struct drm_device *dev)
6062{
6063 struct drm_i915_private *dev_priv = dev->dev_private;
6064
6065 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 6066}
6067
7d708ee4
ID		 6068void intel_suspend_hw(struct drm_device *dev)
6069{
6070 if (HAS_PCH_LPT(dev))
6071 lpt_suspend_hw(dev);
6072}
6073
d2dee86c
PZ		 6074static void intel_init_fbc(struct drm_i915_private *dev_priv)
6075{
9adccc60
PZ		 6076 if (!HAS_FBC(dev_priv)) {
6077 dev_priv->fbc.enabled = false;
d2dee86c 6078 return;
9adccc60 6079 }
d2dee86c
PZ		 6080
6081 if (INTEL_INFO(dev_priv)->gen >= 7) {
6082 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6083 dev_priv->display.enable_fbc = gen7_enable_fbc;
6084 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6085 } else if (INTEL_INFO(dev_priv)->gen >= 5) {
6086 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6087 dev_priv->display.enable_fbc = ironlake_enable_fbc;
6088 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6089 } else if (IS_GM45(dev_priv)) {
6090 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6091 dev_priv->display.enable_fbc = g4x_enable_fbc;
6092 dev_priv->display.disable_fbc = g4x_disable_fbc;
6093 } else {
6094 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6095 dev_priv->display.enable_fbc = i8xx_enable_fbc;
6096 dev_priv->display.disable_fbc = i8xx_disable_fbc;
6097
6098 /* This value was pulled out of someone's hat */
6099 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
6100 }
9adccc60
PZ		 6101
6102 dev_priv->fbc.enabled = dev_priv->display.fbc_enabled(dev_priv->dev);
d2dee86c
PZ		 6103}
6104
1fa61106
ED		 6105/* Set up chip specific power management-related functions */
6106void intel_init_pm(struct drm_device *dev)
6107{
6108 struct drm_i915_private *dev_priv = dev->dev_private;
6109
d2dee86c 6110 intel_init_fbc(dev_priv);
1fa61106 6111
c921aba8
DV		 6112 /* For cxsr */
6113 if (IS_PINEVIEW(dev))
6114 i915_pineview_get_mem_freq(dev);
6115 else if (IS_GEN5(dev))
6116 i915_ironlake_get_mem_freq(dev);
6117
1fa61106 6118 /* For FIFO watermark updates */
c83155a6
DL		 6119 if (IS_GEN9(dev)) {
6120 dev_priv->display.init_clock_gating = gen9_init_clock_gating;
6121 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 6122 ilk_setup_wm_latency(dev);
53615a5e 6123
bd602544
VS		 6124 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6125 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6126 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6127 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6128 dev_priv->display.update_wm = ilk_update_wm;
6129 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6130 } else {
6131 DRM_DEBUG_KMS("Failed to read display plane latency. "
6132 "Disable CxSR\n");
6133 }
6134
6135 if (IS_GEN5(dev))
1fa61106 6136 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 6137 else if (IS_GEN6(dev))
1fa61106 6138 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 6139 else if (IS_IVYBRIDGE(dev))
1fa61106 6140 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 6141 else if (IS_HASWELL(dev))
cad2a2d7 6142 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 6143 else if (INTEL_INFO(dev)->gen == 8)
47c2bd97 6144 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
a4565da8 6145 } else if (IS_CHERRYVIEW(dev)) {
3c2777fd 6146 dev_priv->display.update_wm = cherryview_update_wm;
01e184cc 6147 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
a4565da8
VS		 6148 dev_priv->display.init_clock_gating =
6149 cherryview_init_clock_gating;
1fa61106
ED		 6150 } else if (IS_VALLEYVIEW(dev)) {
6151 dev_priv->display.update_wm = valleyview_update_wm;
01e184cc 6152 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
1fa61106
ED		 6153 dev_priv->display.init_clock_gating =
6154 valleyview_init_clock_gating;
1fa61106
ED		 6155 } else if (IS_PINEVIEW(dev)) {
6156 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6157 dev_priv->is_ddr3,
6158 dev_priv->fsb_freq,
6159 dev_priv->mem_freq)) {
6160 DRM_INFO("failed to find known CxSR latency "
6161 "(found ddr%s fsb freq %d, mem freq %d), "
6162 "disabling CxSR\n",
6163 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6164 dev_priv->fsb_freq, dev_priv->mem_freq);
6165 /* Disable CxSR and never update its watermark again */
5209b1f4 6166 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 6167 dev_priv->display.update_wm = NULL;
6168 } else
6169 dev_priv->display.update_wm = pineview_update_wm;
6170 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6171 } else if (IS_G4X(dev)) {
6172 dev_priv->display.update_wm = g4x_update_wm;
6173 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6174 } else if (IS_GEN4(dev)) {
6175 dev_priv->display.update_wm = i965_update_wm;
6176 if (IS_CRESTLINE(dev))
6177 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6178 else if (IS_BROADWATER(dev))
6179 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6180 } else if (IS_GEN3(dev)) {
6181 dev_priv->display.update_wm = i9xx_update_wm;
6182 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6183 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 6184 } else if (IS_GEN2(dev)) {
6185 if (INTEL_INFO(dev)->num_pipes == 1) {
6186 dev_priv->display.update_wm = i845_update_wm;
1fa61106 6187 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 6188 } else {
6189 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 6190 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 6191 }
6192
6193 if (IS_I85X(dev) || IS_I865G(dev))
6194 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6195 else
6196 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6197 } else {
6198 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 6199 }
6200}
6201
42c0526c
BW		 6202int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
6203{
4fc688ce 6204 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6205
6206 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6207 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6208 return -EAGAIN;
6209 }
6210
6211 I915_WRITE(GEN6_PCODE_DATA, *val);
6212 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6213
6214 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6215 500)) {
6216 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6217 return -ETIMEDOUT;
6218 }
6219
6220 *val = I915_READ(GEN6_PCODE_DATA);
6221 I915_WRITE(GEN6_PCODE_DATA, 0);
6222
6223 return 0;
6224}
6225
6226int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
6227{
4fc688ce 6228 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6229
6230 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6231 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6232 return -EAGAIN;
6233 }
6234
6235 I915_WRITE(GEN6_PCODE_DATA, val);
6236 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6237
6238 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6239 500)) {
6240 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6241 return -ETIMEDOUT;
6242 }
6243
6244 I915_WRITE(GEN6_PCODE_DATA, 0);
6245
6246 return 0;
6247}
a0e4e199 6248
b55dd647 6249static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
855ba3be 6250{
07ab118b 6251 int div;
855ba3be 6252
07ab118b 6253 /* 4 x czclk */
2ec3815f 6254 switch (dev_priv->mem_freq) {
855ba3be 6255 case 800:
07ab118b 6256 div = 10;
855ba3be
JB		 6257 break;
6258 case 1066:
07ab118b 6259 div = 12;
855ba3be
JB		 6260 break;
6261 case 1333:
07ab118b 6262 div = 16;
855ba3be
JB		 6263 break;
6264 default:
6265 return -1;
6266 }
6267
2ec3815f 6268 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
855ba3be
JB		 6269}
6270
b55dd647 6271static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 6272{
07ab118b 6273 int mul;
855ba3be 6274
07ab118b 6275 /* 4 x czclk */
2ec3815f 6276 switch (dev_priv->mem_freq) {
855ba3be 6277 case 800:
07ab118b 6278 mul = 10;
855ba3be
JB		 6279 break;
6280 case 1066:
07ab118b 6281 mul = 12;
855ba3be
JB		 6282 break;
6283 case 1333:
07ab118b 6284 mul = 16;
855ba3be
JB		 6285 break;
6286 default:
6287 return -1;
6288 }
6289
2ec3815f 6290 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
855ba3be
JB		 6291}
6292
b55dd647 6293static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8
D		 6294{
6295 int div, freq;
6296
6297 switch (dev_priv->rps.cz_freq) {
6298 case 200:
6299 div = 5;
6300 break;
6301 case 267:
6302 div = 6;
6303 break;
6304 case 320:
6305 case 333:
6306 case 400:
6307 div = 8;
6308 break;
6309 default:
6310 return -1;
6311 }
6312
6313 freq = (DIV_ROUND_CLOSEST((dev_priv->rps.cz_freq * val), 2 * div) / 2);
6314
6315 return freq;
6316}
6317
b55dd647 6318static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8
D		 6319{
6320 int mul, opcode;
6321
6322 switch (dev_priv->rps.cz_freq) {
6323 case 200:
6324 mul = 5;
6325 break;
6326 case 267:
6327 mul = 6;
6328 break;
6329 case 320:
6330 case 333:
6331 case 400:
6332 mul = 8;
6333 break;
6334 default:
6335 return -1;
6336 }
6337
1c14762d 6338 /* CHV needs even values */
22b1b2f8
D		 6339 opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv->rps.cz_freq) * 2);
6340
6341 return opcode;
6342}
6343
6344int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
6345{
6346 int ret = -1;
6347
6348 if (IS_CHERRYVIEW(dev_priv->dev))
6349 ret = chv_gpu_freq(dev_priv, val);
6350 else if (IS_VALLEYVIEW(dev_priv->dev))
6351 ret = byt_gpu_freq(dev_priv, val);
6352
6353 return ret;
6354}
6355
6356int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
6357{
6358 int ret = -1;
6359
6360 if (IS_CHERRYVIEW(dev_priv->dev))
6361 ret = chv_freq_opcode(dev_priv, val);
6362 else if (IS_VALLEYVIEW(dev_priv->dev))
6363 ret = byt_freq_opcode(dev_priv, val);
6364
6365 return ret;
6366}
6367
f742a552 6368void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 6369{
6370 struct drm_i915_private *dev_priv = dev->dev_private;
6371
f742a552
DV		 6372 mutex_init(&dev_priv->rps.hw_lock);
6373
907b28c5
CW		 6374 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6375 intel_gen6_powersave_work);
5d584b2e 6376
33688d95 6377 dev_priv->pm.suspended = false;
907b28c5 6378}
Linux 6.x block layer and io_uring tree(s)