projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: Use the .release hook to drop the stolen drm_mm tracking
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
f9dcb0df 33#include <linux/vgaarb.h>
f4db9321 34#include <drm/i915_powerwell.h>
8a187455 35#include <linux/pm_runtime.h>
85208be0 36
dc39fff7
BW		 37/**
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54#define INTEL_RC6_ENABLE (1<<0)
55#define INTEL_RC6p_ENABLE (1<<1)
56#define INTEL_RC6pp_ENABLE (1<<2)
57
f6750b3c
ED		 58/* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 61 *
f6750b3c
ED		 62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
85208be0 64 *
f6750b3c
ED		 65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
85208be0
ED		 67 */
68
1fa61106 69static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 70{
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 u32 fbc_ctl;
73
74 /* Disable compression */
75 fbc_ctl = I915_READ(FBC_CONTROL);
76 if ((fbc_ctl & FBC_CTL_EN) == 0)
77 return;
78
79 fbc_ctl &= ~FBC_CTL_EN;
80 I915_WRITE(FBC_CONTROL, fbc_ctl);
81
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
85 return;
86 }
87
88 DRM_DEBUG_KMS("disabled FBC\n");
89}
90
993495ae 91static void i8xx_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 92{
93 struct drm_device *dev = crtc->dev;
94 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 95 struct drm_framebuffer *fb = crtc->primary->fb;
85208be0
ED		 96 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
97 struct drm_i915_gem_object *obj = intel_fb->obj;
98 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
99 int cfb_pitch;
7f2cf220 100 int i;
159f9875 101 u32 fbc_ctl;
85208be0 102
5c3fe8b0 103 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
85208be0
ED		 104 if (fb->pitches[0] < cfb_pitch)
105 cfb_pitch = fb->pitches[0];
106
42a430f5
VS		 107 /* FBC_CTL wants 32B or 64B units */
108 if (IS_GEN2(dev))
109 cfb_pitch = (cfb_pitch / 32) - 1;
110 else
111 cfb_pitch = (cfb_pitch / 64) - 1;
85208be0
ED		 112
113 /* Clear old tags */
114 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
115 I915_WRITE(FBC_TAG + (i * 4), 0);
116
159f9875
VS		 117 if (IS_GEN4(dev)) {
118 u32 fbc_ctl2;
119
120 /* Set it up... */
121 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
7f2cf220 122 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
159f9875
VS		 123 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
124 I915_WRITE(FBC_FENCE_OFF, crtc->y);
125 }
85208be0
ED		 126
127 /* enable it... */
993495ae
VS		 128 fbc_ctl = I915_READ(FBC_CONTROL);
129 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
130 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
85208be0
ED		 131 if (IS_I945GM(dev))
132 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
133 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
85208be0
ED		 134 fbc_ctl |= obj->fence_reg;
135 I915_WRITE(FBC_CONTROL, fbc_ctl);
136
5cd5410e 137 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
84f44ce7 138 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 139}
140
1fa61106 141static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 142{
143 struct drm_i915_private *dev_priv = dev->dev_private;
144
145 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
146}
147
993495ae 148static void g4x_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 149{
150 struct drm_device *dev = crtc->dev;
151 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 152 struct drm_framebuffer *fb = crtc->primary->fb;
85208be0
ED		 153 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
154 struct drm_i915_gem_object *obj = intel_fb->obj;
155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85208be0
ED		 156 u32 dpfc_ctl;
157
3fa2e0ee
VS		 158 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
159 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
160 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
161 else
162 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
85208be0 163 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
85208be0 164
85208be0
ED		 165 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
166
167 /* enable it... */
fe74c1a5 168 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
85208be0 169
84f44ce7 170 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 171}
172
1fa61106 173static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 174{
175 struct drm_i915_private *dev_priv = dev->dev_private;
176 u32 dpfc_ctl;
177
178 /* Disable compression */
179 dpfc_ctl = I915_READ(DPFC_CONTROL);
180 if (dpfc_ctl & DPFC_CTL_EN) {
181 dpfc_ctl &= ~DPFC_CTL_EN;
182 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
183
184 DRM_DEBUG_KMS("disabled FBC\n");
185 }
186}
187
1fa61106 188static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 189{
190 struct drm_i915_private *dev_priv = dev->dev_private;
191
192 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
193}
194
195static void sandybridge_blit_fbc_update(struct drm_device *dev)
196{
197 struct drm_i915_private *dev_priv = dev->dev_private;
198 u32 blt_ecoskpd;
199
200 /* Make sure blitter notifies FBC of writes */
940aece4
D		 201
202 /* Blitter is part of Media powerwell on VLV. No impact of
203 * his param in other platforms for now */
204 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
c8d9a590 205
85208be0
ED		 206 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
207 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
208 GEN6_BLITTER_LOCK_SHIFT;
209 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
210 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
211 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
212 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
213 GEN6_BLITTER_LOCK_SHIFT);
214 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
215 POSTING_READ(GEN6_BLITTER_ECOSKPD);
c8d9a590 216
940aece4 217 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
85208be0
ED		 218}
219
993495ae 220static void ironlake_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 221{
222 struct drm_device *dev = crtc->dev;
223 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 224 struct drm_framebuffer *fb = crtc->primary->fb;
85208be0
ED		 225 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
226 struct drm_i915_gem_object *obj = intel_fb->obj;
227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85208be0
ED		 228 u32 dpfc_ctl;
229
46f3dab9 230 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
3fa2e0ee
VS		 231 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
232 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
233 else
234 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
d629336b
VS		 235 dpfc_ctl |= DPFC_CTL_FENCE_EN;
236 if (IS_GEN5(dev))
237 dpfc_ctl |= obj->fence_reg;
85208be0 238
85208be0 239 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
f343c5f6 240 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
85208be0
ED		 241 /* enable it... */
242 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
243
244 if (IS_GEN6(dev)) {
245 I915_WRITE(SNB_DPFC_CTL_SA,
246 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
247 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
248 sandybridge_blit_fbc_update(dev);
249 }
250
84f44ce7 251 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 252}
253
1fa61106 254static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 255{
256 struct drm_i915_private *dev_priv = dev->dev_private;
257 u32 dpfc_ctl;
258
259 /* Disable compression */
260 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
261 if (dpfc_ctl & DPFC_CTL_EN) {
262 dpfc_ctl &= ~DPFC_CTL_EN;
263 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
264
265 DRM_DEBUG_KMS("disabled FBC\n");
266 }
267}
268
1fa61106 269static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 270{
271 struct drm_i915_private *dev_priv = dev->dev_private;
272
273 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
274}
275
993495ae 276static void gen7_enable_fbc(struct drm_crtc *crtc)
abe959c7
RV		 277{
278 struct drm_device *dev = crtc->dev;
279 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 280 struct drm_framebuffer *fb = crtc->primary->fb;
abe959c7
RV		 281 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
282 struct drm_i915_gem_object *obj = intel_fb->obj;
283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3fa2e0ee 284 u32 dpfc_ctl;
abe959c7 285
3fa2e0ee
VS		 286 dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
287 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
288 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
289 else
290 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
291 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
292
293 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
abe959c7 294
891348b2 295 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 296 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
2adb6db8
VS		 297 I915_WRITE(ILK_DISPLAY_CHICKEN1,
298 I915_READ(ILK_DISPLAY_CHICKEN1) |
299 ILK_FBCQ_DIS);
28554164 300 } else {
2adb6db8 301 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
8f670bb1
VS		 302 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
303 I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
304 HSW_FBCQ_DIS);
891348b2 305 }
b74ea102 306
abe959c7
RV		 307 I915_WRITE(SNB_DPFC_CTL_SA,
308 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
309 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
310
311 sandybridge_blit_fbc_update(dev);
312
b19870ee 313 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
abe959c7
RV		 314}
315
85208be0
ED		 316bool intel_fbc_enabled(struct drm_device *dev)
317{
318 struct drm_i915_private *dev_priv = dev->dev_private;
319
320 if (!dev_priv->display.fbc_enabled)
321 return false;
322
323 return dev_priv->display.fbc_enabled(dev);
324}
325
326static void intel_fbc_work_fn(struct work_struct *__work)
327{
328 struct intel_fbc_work *work =
329 container_of(to_delayed_work(__work),
330 struct intel_fbc_work, work);
331 struct drm_device *dev = work->crtc->dev;
332 struct drm_i915_private *dev_priv = dev->dev_private;
333
334 mutex_lock(&dev->struct_mutex);
5c3fe8b0 335 if (work == dev_priv->fbc.fbc_work) {
85208be0
ED		 336 /* Double check that we haven't switched fb without cancelling
337 * the prior work.
338 */
f4510a27 339 if (work->crtc->primary->fb == work->fb) {
993495ae 340 dev_priv->display.enable_fbc(work->crtc);
85208be0 341
5c3fe8b0 342 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
f4510a27 343 dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
5c3fe8b0 344 dev_priv->fbc.y = work->crtc->y;
85208be0
ED		 345 }
346
5c3fe8b0 347 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 348 }
349 mutex_unlock(&dev->struct_mutex);
350
351 kfree(work);
352}
353
354static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
355{
5c3fe8b0 356 if (dev_priv->fbc.fbc_work == NULL)
85208be0
ED		 357 return;
358
359 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
360
361 /* Synchronisation is provided by struct_mutex and checking of
5c3fe8b0 362 * dev_priv->fbc.fbc_work, so we can perform the cancellation
85208be0
ED		 363 * entirely asynchronously.
364 */
5c3fe8b0 365 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
85208be0 366 /* tasklet was killed before being run, clean up */
5c3fe8b0 367 kfree(dev_priv->fbc.fbc_work);
85208be0
ED		 368
369 /* Mark the work as no longer wanted so that if it does
370 * wake-up (because the work was already running and waiting
371 * for our mutex), it will discover that is no longer
372 * necessary to run.
373 */
5c3fe8b0 374 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 375}
376
993495ae 377static void intel_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 378{
379 struct intel_fbc_work *work;
380 struct drm_device *dev = crtc->dev;
381 struct drm_i915_private *dev_priv = dev->dev_private;
382
383 if (!dev_priv->display.enable_fbc)
384 return;
385
386 intel_cancel_fbc_work(dev_priv);
387
b14c5679 388 work = kzalloc(sizeof(*work), GFP_KERNEL);
85208be0 389 if (work == NULL) {
6cdcb5e7 390 DRM_ERROR("Failed to allocate FBC work structure\n");
993495ae 391 dev_priv->display.enable_fbc(crtc);
85208be0
ED		 392 return;
393 }
394
395 work->crtc = crtc;
f4510a27 396 work->fb = crtc->primary->fb;
85208be0
ED		 397 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
398
5c3fe8b0 399 dev_priv->fbc.fbc_work = work;
85208be0 400
85208be0
ED		 401 /* Delay the actual enabling to let pageflipping cease and the
402 * display to settle before starting the compression. Note that
403 * this delay also serves a second purpose: it allows for a
404 * vblank to pass after disabling the FBC before we attempt
405 * to modify the control registers.
406 *
407 * A more complicated solution would involve tracking vblanks
408 * following the termination of the page-flipping sequence
409 * and indeed performing the enable as a co-routine and not
410 * waiting synchronously upon the vblank.
7457d617
DL		 411 *
412 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
85208be0
ED		 413 */
414 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
415}
416
417void intel_disable_fbc(struct drm_device *dev)
418{
419 struct drm_i915_private *dev_priv = dev->dev_private;
420
421 intel_cancel_fbc_work(dev_priv);
422
423 if (!dev_priv->display.disable_fbc)
424 return;
425
426 dev_priv->display.disable_fbc(dev);
5c3fe8b0 427 dev_priv->fbc.plane = -1;
85208be0
ED		 428}
429
29ebf90f
CW		 430static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
431 enum no_fbc_reason reason)
432{
433 if (dev_priv->fbc.no_fbc_reason == reason)
434 return false;
435
436 dev_priv->fbc.no_fbc_reason = reason;
437 return true;
438}
439
85208be0
ED		 440/**
441 * intel_update_fbc - enable/disable FBC as needed
442 * @dev: the drm_device
443 *
444 * Set up the framebuffer compression hardware at mode set time. We
445 * enable it if possible:
446 * - plane A only (on pre-965)
447 * - no pixel mulitply/line duplication
448 * - no alpha buffer discard
449 * - no dual wide
f85da868 450 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
85208be0
ED		 451 *
452 * We can't assume that any compression will take place (worst case),
453 * so the compressed buffer has to be the same size as the uncompressed
454 * one. It also must reside (along with the line length buffer) in
455 * stolen memory.
456 *
457 * We need to enable/disable FBC on a global basis.
458 */
459void intel_update_fbc(struct drm_device *dev)
460{
461 struct drm_i915_private *dev_priv = dev->dev_private;
462 struct drm_crtc *crtc = NULL, *tmp_crtc;
463 struct intel_crtc *intel_crtc;
464 struct drm_framebuffer *fb;
465 struct intel_framebuffer *intel_fb;
466 struct drm_i915_gem_object *obj;
ef644fda 467 const struct drm_display_mode *adjusted_mode;
37327abd 468 unsigned int max_width, max_height;
85208be0 469
3a77c4c4 470 if (!HAS_FBC(dev)) {
29ebf90f 471 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
85208be0 472 return;
29ebf90f 473 }
85208be0 474
d330a953 475 if (!i915.powersave) {
29ebf90f
CW		 476 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
477 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0 478 return;
29ebf90f 479 }
85208be0
ED		 480
481 /*
482 * If FBC is already on, we just have to verify that we can
483 * keep it that way...
484 * Need to disable if:
485 * - more than one pipe is active
486 * - changing FBC params (stride, fence, mode)
487 * - new fb is too large to fit in compressed buffer
488 * - going to an unsupported config (interlace, pixel multiply, etc.)
489 */
70e1e0ec 490 for_each_crtc(dev, tmp_crtc) {
3490ea5d 491 if (intel_crtc_active(tmp_crtc) &&
4c445e0e 492 to_intel_crtc(tmp_crtc)->primary_enabled) {
85208be0 493 if (crtc) {
29ebf90f
CW		 494 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
495 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
85208be0
ED		 496 goto out_disable;
497 }
498 crtc = tmp_crtc;
499 }
500 }
501
f4510a27 502 if (!crtc || crtc->primary->fb == NULL) {
29ebf90f
CW		 503 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
504 DRM_DEBUG_KMS("no output, disabling\n");
85208be0
ED		 505 goto out_disable;
506 }
507
508 intel_crtc = to_intel_crtc(crtc);
f4510a27 509 fb = crtc->primary->fb;
85208be0
ED		 510 intel_fb = to_intel_framebuffer(fb);
511 obj = intel_fb->obj;
ef644fda 512 adjusted_mode = &intel_crtc->config.adjusted_mode;
85208be0 513
d330a953 514 if (i915.enable_fbc < 0 &&
8a5729a3 515 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
29ebf90f
CW		 516 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
517 DRM_DEBUG_KMS("disabled per chip default\n");
8a5729a3 518 goto out_disable;
85208be0 519 }
d330a953 520 if (!i915.enable_fbc) {
29ebf90f
CW		 521 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
522 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0
ED		 523 goto out_disable;
524 }
ef644fda
VS		 525 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
526 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
29ebf90f
CW		 527 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
528 DRM_DEBUG_KMS("mode incompatible with compression, "
529 "disabling\n");
85208be0
ED		 530 goto out_disable;
531 }
f85da868
PZ		 532
533 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
37327abd
VS		 534 max_width = 4096;
535 max_height = 2048;
f85da868 536 } else {
37327abd
VS		 537 max_width = 2048;
538 max_height = 1536;
f85da868 539 }
37327abd
VS		 540 if (intel_crtc->config.pipe_src_w > max_width ||
541 intel_crtc->config.pipe_src_h > max_height) {
29ebf90f
CW		 542 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
543 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
85208be0
ED		 544 goto out_disable;
545 }
8f94d24b 546 if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
c5a44aa0 547 intel_crtc->plane != PLANE_A) {
29ebf90f 548 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
c5a44aa0 549 DRM_DEBUG_KMS("plane not A, disabling compression\n");
85208be0
ED		 550 goto out_disable;
551 }
552
553 /* The use of a CPU fence is mandatory in order to detect writes
554 * by the CPU to the scanout and trigger updates to the FBC.
555 */
556 if (obj->tiling_mode != I915_TILING_X ||
557 obj->fence_reg == I915_FENCE_REG_NONE) {
29ebf90f
CW		 558 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
559 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
85208be0
ED		 560 goto out_disable;
561 }
562
563 /* If the kernel debugger is active, always disable compression */
564 if (in_dbg_master())
565 goto out_disable;
566
11be49eb 567 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
29ebf90f
CW		 568 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
569 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
11be49eb
CW		 570 goto out_disable;
571 }
572
85208be0
ED		 573 /* If the scanout has not changed, don't modify the FBC settings.
574 * Note that we make the fundamental assumption that the fb->obj
575 * cannot be unpinned (and have its GTT offset and fence revoked)
576 * without first being decoupled from the scanout and FBC disabled.
577 */
5c3fe8b0
BW		 578 if (dev_priv->fbc.plane == intel_crtc->plane &&
579 dev_priv->fbc.fb_id == fb->base.id &&
580 dev_priv->fbc.y == crtc->y)
85208be0
ED		 581 return;
582
583 if (intel_fbc_enabled(dev)) {
584 /* We update FBC along two paths, after changing fb/crtc
585 * configuration (modeswitching) and after page-flipping
586 * finishes. For the latter, we know that not only did
587 * we disable the FBC at the start of the page-flip
588 * sequence, but also more than one vblank has passed.
589 *
590 * For the former case of modeswitching, it is possible
591 * to switch between two FBC valid configurations
592 * instantaneously so we do need to disable the FBC
593 * before we can modify its control registers. We also
594 * have to wait for the next vblank for that to take
595 * effect. However, since we delay enabling FBC we can
596 * assume that a vblank has passed since disabling and
597 * that we can safely alter the registers in the deferred
598 * callback.
599 *
600 * In the scenario that we go from a valid to invalid
601 * and then back to valid FBC configuration we have
602 * no strict enforcement that a vblank occurred since
603 * disabling the FBC. However, along all current pipe
604 * disabling paths we do need to wait for a vblank at
605 * some point. And we wait before enabling FBC anyway.
606 */
607 DRM_DEBUG_KMS("disabling active FBC for update\n");
608 intel_disable_fbc(dev);
609 }
610
993495ae 611 intel_enable_fbc(crtc);
29ebf90f 612 dev_priv->fbc.no_fbc_reason = FBC_OK;
85208be0
ED		 613 return;
614
615out_disable:
616 /* Multiple disables should be harmless */
617 if (intel_fbc_enabled(dev)) {
618 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
619 intel_disable_fbc(dev);
620 }
11be49eb 621 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 622}
623
c921aba8
DV		 624static void i915_pineview_get_mem_freq(struct drm_device *dev)
625{
50227e1c 626 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 627 u32 tmp;
628
629 tmp = I915_READ(CLKCFG);
630
631 switch (tmp & CLKCFG_FSB_MASK) {
632 case CLKCFG_FSB_533:
633 dev_priv->fsb_freq = 533; /* 133*4 */
634 break;
635 case CLKCFG_FSB_800:
636 dev_priv->fsb_freq = 800; /* 200*4 */
637 break;
638 case CLKCFG_FSB_667:
639 dev_priv->fsb_freq = 667; /* 167*4 */
640 break;
641 case CLKCFG_FSB_400:
642 dev_priv->fsb_freq = 400; /* 100*4 */
643 break;
644 }
645
646 switch (tmp & CLKCFG_MEM_MASK) {
647 case CLKCFG_MEM_533:
648 dev_priv->mem_freq = 533;
649 break;
650 case CLKCFG_MEM_667:
651 dev_priv->mem_freq = 667;
652 break;
653 case CLKCFG_MEM_800:
654 dev_priv->mem_freq = 800;
655 break;
656 }
657
658 /* detect pineview DDR3 setting */
659 tmp = I915_READ(CSHRDDR3CTL);
660 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
661}
662
663static void i915_ironlake_get_mem_freq(struct drm_device *dev)
664{
50227e1c 665 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 666 u16 ddrpll, csipll;
667
668 ddrpll = I915_READ16(DDRMPLL1);
669 csipll = I915_READ16(CSIPLL0);
670
671 switch (ddrpll & 0xff) {
672 case 0xc:
673 dev_priv->mem_freq = 800;
674 break;
675 case 0x10:
676 dev_priv->mem_freq = 1066;
677 break;
678 case 0x14:
679 dev_priv->mem_freq = 1333;
680 break;
681 case 0x18:
682 dev_priv->mem_freq = 1600;
683 break;
684 default:
685 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
686 ddrpll & 0xff);
687 dev_priv->mem_freq = 0;
688 break;
689 }
690
20e4d407 691 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 692
693 switch (csipll & 0x3ff) {
694 case 0x00c:
695 dev_priv->fsb_freq = 3200;
696 break;
697 case 0x00e:
698 dev_priv->fsb_freq = 3733;
699 break;
700 case 0x010:
701 dev_priv->fsb_freq = 4266;
702 break;
703 case 0x012:
704 dev_priv->fsb_freq = 4800;
705 break;
706 case 0x014:
707 dev_priv->fsb_freq = 5333;
708 break;
709 case 0x016:
710 dev_priv->fsb_freq = 5866;
711 break;
712 case 0x018:
713 dev_priv->fsb_freq = 6400;
714 break;
715 default:
716 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
717 csipll & 0x3ff);
718 dev_priv->fsb_freq = 0;
719 break;
720 }
721
722 if (dev_priv->fsb_freq == 3200) {
20e4d407 723 dev_priv->ips.c_m = 0;
c921aba8 724 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 725 dev_priv->ips.c_m = 1;
c921aba8 726 } else {
20e4d407 727 dev_priv->ips.c_m = 2;
c921aba8
DV		 728 }
729}
730
b445e3b0
ED		 731static const struct cxsr_latency cxsr_latency_table[] = {
732 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
733 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
734 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
735 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
736 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
737
738 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
739 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
740 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
741 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
742 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
743
744 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
745 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
746 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
747 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
748 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
749
750 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
751 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
752 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
753 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
754 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
755
756 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
757 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
758 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
759 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
760 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
761
762 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
763 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
764 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
765 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
766 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
767};
768
63c62275 769static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 770 int is_ddr3,
771 int fsb,
772 int mem)
773{
774 const struct cxsr_latency *latency;
775 int i;
776
777 if (fsb == 0 || mem == 0)
778 return NULL;
779
780 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
781 latency = &cxsr_latency_table[i];
782 if (is_desktop == latency->is_desktop &&
783 is_ddr3 == latency->is_ddr3 &&
784 fsb == latency->fsb_freq && mem == latency->mem_freq)
785 return latency;
786 }
787
788 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
789
790 return NULL;
791}
792
1fa61106 793static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 794{
795 struct drm_i915_private *dev_priv = dev->dev_private;
796
797 /* deactivate cxsr */
798 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
799}
800
801/*
802 * Latency for FIFO fetches is dependent on several factors:
803 * - memory configuration (speed, channels)
804 * - chipset
805 * - current MCH state
806 * It can be fairly high in some situations, so here we assume a fairly
807 * pessimal value. It's a tradeoff between extra memory fetches (if we
808 * set this value too high, the FIFO will fetch frequently to stay full)
809 * and power consumption (set it too low to save power and we might see
810 * FIFO underruns and display "flicker").
811 *
812 * A value of 5us seems to be a good balance; safe for very low end
813 * platforms but not overly aggressive on lower latency configs.
814 */
815static const int latency_ns = 5000;
816
1fa61106 817static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 818{
819 struct drm_i915_private *dev_priv = dev->dev_private;
820 uint32_t dsparb = I915_READ(DSPARB);
821 int size;
822
823 size = dsparb & 0x7f;
824 if (plane)
825 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
826
827 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
828 plane ? "B" : "A", size);
829
830 return size;
831}
832
feb56b93 833static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 834{
835 struct drm_i915_private *dev_priv = dev->dev_private;
836 uint32_t dsparb = I915_READ(DSPARB);
837 int size;
838
839 size = dsparb & 0x1ff;
840 if (plane)
841 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
842 size >>= 1; /* Convert to cachelines */
843
844 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
845 plane ? "B" : "A", size);
846
847 return size;
848}
849
1fa61106 850static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 851{
852 struct drm_i915_private *dev_priv = dev->dev_private;
853 uint32_t dsparb = I915_READ(DSPARB);
854 int size;
855
856 size = dsparb & 0x7f;
857 size >>= 2; /* Convert to cachelines */
858
859 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
860 plane ? "B" : "A",
861 size);
862
863 return size;
864}
865
b445e3b0
ED		 866/* Pineview has different values for various configs */
867static const struct intel_watermark_params pineview_display_wm = {
868 PINEVIEW_DISPLAY_FIFO,
869 PINEVIEW_MAX_WM,
870 PINEVIEW_DFT_WM,
871 PINEVIEW_GUARD_WM,
872 PINEVIEW_FIFO_LINE_SIZE
873};
874static const struct intel_watermark_params pineview_display_hplloff_wm = {
875 PINEVIEW_DISPLAY_FIFO,
876 PINEVIEW_MAX_WM,
877 PINEVIEW_DFT_HPLLOFF_WM,
878 PINEVIEW_GUARD_WM,
879 PINEVIEW_FIFO_LINE_SIZE
880};
881static const struct intel_watermark_params pineview_cursor_wm = {
882 PINEVIEW_CURSOR_FIFO,
883 PINEVIEW_CURSOR_MAX_WM,
884 PINEVIEW_CURSOR_DFT_WM,
885 PINEVIEW_CURSOR_GUARD_WM,
886 PINEVIEW_FIFO_LINE_SIZE,
887};
888static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
889 PINEVIEW_CURSOR_FIFO,
890 PINEVIEW_CURSOR_MAX_WM,
891 PINEVIEW_CURSOR_DFT_WM,
892 PINEVIEW_CURSOR_GUARD_WM,
893 PINEVIEW_FIFO_LINE_SIZE
894};
895static const struct intel_watermark_params g4x_wm_info = {
896 G4X_FIFO_SIZE,
897 G4X_MAX_WM,
898 G4X_MAX_WM,
899 2,
900 G4X_FIFO_LINE_SIZE,
901};
902static const struct intel_watermark_params g4x_cursor_wm_info = {
903 I965_CURSOR_FIFO,
904 I965_CURSOR_MAX_WM,
905 I965_CURSOR_DFT_WM,
906 2,
907 G4X_FIFO_LINE_SIZE,
908};
909static const struct intel_watermark_params valleyview_wm_info = {
910 VALLEYVIEW_FIFO_SIZE,
911 VALLEYVIEW_MAX_WM,
912 VALLEYVIEW_MAX_WM,
913 2,
914 G4X_FIFO_LINE_SIZE,
915};
916static const struct intel_watermark_params valleyview_cursor_wm_info = {
917 I965_CURSOR_FIFO,
918 VALLEYVIEW_CURSOR_MAX_WM,
919 I965_CURSOR_DFT_WM,
920 2,
921 G4X_FIFO_LINE_SIZE,
922};
923static const struct intel_watermark_params i965_cursor_wm_info = {
924 I965_CURSOR_FIFO,
925 I965_CURSOR_MAX_WM,
926 I965_CURSOR_DFT_WM,
927 2,
928 I915_FIFO_LINE_SIZE,
929};
930static const struct intel_watermark_params i945_wm_info = {
931 I945_FIFO_SIZE,
932 I915_MAX_WM,
933 1,
934 2,
935 I915_FIFO_LINE_SIZE
936};
937static const struct intel_watermark_params i915_wm_info = {
938 I915_FIFO_SIZE,
939 I915_MAX_WM,
940 1,
941 2,
942 I915_FIFO_LINE_SIZE
943};
feb56b93 944static const struct intel_watermark_params i830_wm_info = {
b445e3b0
ED		 945 I855GM_FIFO_SIZE,
946 I915_MAX_WM,
947 1,
948 2,
949 I830_FIFO_LINE_SIZE
950};
feb56b93 951static const struct intel_watermark_params i845_wm_info = {
b445e3b0
ED		 952 I830_FIFO_SIZE,
953 I915_MAX_WM,
954 1,
955 2,
956 I830_FIFO_LINE_SIZE
957};
958
b445e3b0
ED		 959/**
960 * intel_calculate_wm - calculate watermark level
961 * @clock_in_khz: pixel clock
962 * @wm: chip FIFO params
963 * @pixel_size: display pixel size
964 * @latency_ns: memory latency for the platform
965 *
966 * Calculate the watermark level (the level at which the display plane will
967 * start fetching from memory again). Each chip has a different display
968 * FIFO size and allocation, so the caller needs to figure that out and pass
969 * in the correct intel_watermark_params structure.
970 *
971 * As the pixel clock runs, the FIFO will be drained at a rate that depends
972 * on the pixel size. When it reaches the watermark level, it'll start
973 * fetching FIFO line sized based chunks from memory until the FIFO fills
974 * past the watermark point. If the FIFO drains completely, a FIFO underrun
975 * will occur, and a display engine hang could result.
976 */
977static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
978 const struct intel_watermark_params *wm,
979 int fifo_size,
980 int pixel_size,
981 unsigned long latency_ns)
982{
983 long entries_required, wm_size;
984
985 /*
986 * Note: we need to make sure we don't overflow for various clock &
987 * latency values.
988 * clocks go from a few thousand to several hundred thousand.
989 * latency is usually a few thousand
990 */
991 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
992 1000;
993 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
994
995 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
996
997 wm_size = fifo_size - (entries_required + wm->guard_size);
998
999 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1000
1001 /* Don't promote wm_size to unsigned... */
1002 if (wm_size > (long)wm->max_wm)
1003 wm_size = wm->max_wm;
1004 if (wm_size <= 0)
1005 wm_size = wm->default_wm;
1006 return wm_size;
1007}
1008
1009static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1010{
1011 struct drm_crtc *crtc, *enabled = NULL;
1012
70e1e0ec 1013 for_each_crtc(dev, crtc) {
3490ea5d 1014 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1015 if (enabled)
1016 return NULL;
1017 enabled = crtc;
1018 }
1019 }
1020
1021 return enabled;
1022}
1023
46ba614c 1024static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1025{
46ba614c 1026 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1027 struct drm_i915_private *dev_priv = dev->dev_private;
1028 struct drm_crtc *crtc;
1029 const struct cxsr_latency *latency;
1030 u32 reg;
1031 unsigned long wm;
1032
1033 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1034 dev_priv->fsb_freq, dev_priv->mem_freq);
1035 if (!latency) {
1036 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1037 pineview_disable_cxsr(dev);
1038 return;
1039 }
1040
1041 crtc = single_enabled_crtc(dev);
1042 if (crtc) {
241bfc38 1043 const struct drm_display_mode *adjusted_mode;
f4510a27 1044 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
241bfc38
DL		 1045 int clock;
1046
1047 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1048 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 1049
1050 /* Display SR */
1051 wm = intel_calculate_wm(clock, &pineview_display_wm,
1052 pineview_display_wm.fifo_size,
1053 pixel_size, latency->display_sr);
1054 reg = I915_READ(DSPFW1);
1055 reg &= ~DSPFW_SR_MASK;
1056 reg |= wm << DSPFW_SR_SHIFT;
1057 I915_WRITE(DSPFW1, reg);
1058 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1059
1060 /* cursor SR */
1061 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1062 pineview_display_wm.fifo_size,
1063 pixel_size, latency->cursor_sr);
1064 reg = I915_READ(DSPFW3);
1065 reg &= ~DSPFW_CURSOR_SR_MASK;
1066 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1067 I915_WRITE(DSPFW3, reg);
1068
1069 /* Display HPLL off SR */
1070 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1071 pineview_display_hplloff_wm.fifo_size,
1072 pixel_size, latency->display_hpll_disable);
1073 reg = I915_READ(DSPFW3);
1074 reg &= ~DSPFW_HPLL_SR_MASK;
1075 reg |= wm & DSPFW_HPLL_SR_MASK;
1076 I915_WRITE(DSPFW3, reg);
1077
1078 /* cursor HPLL off SR */
1079 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1080 pineview_display_hplloff_wm.fifo_size,
1081 pixel_size, latency->cursor_hpll_disable);
1082 reg = I915_READ(DSPFW3);
1083 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1084 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1085 I915_WRITE(DSPFW3, reg);
1086 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1087
1088 /* activate cxsr */
1089 I915_WRITE(DSPFW3,
1090 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1091 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1092 } else {
1093 pineview_disable_cxsr(dev);
1094 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1095 }
1096}
1097
1098static bool g4x_compute_wm0(struct drm_device *dev,
1099 int plane,
1100 const struct intel_watermark_params *display,
1101 int display_latency_ns,
1102 const struct intel_watermark_params *cursor,
1103 int cursor_latency_ns,
1104 int *plane_wm,
1105 int *cursor_wm)
1106{
1107 struct drm_crtc *crtc;
4fe8590a 1108 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1109 int htotal, hdisplay, clock, pixel_size;
1110 int line_time_us, line_count;
1111 int entries, tlb_miss;
1112
1113 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1114 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1115 *cursor_wm = cursor->guard_size;
1116 *plane_wm = display->guard_size;
1117 return false;
1118 }
1119
4fe8590a 1120 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1121 clock = adjusted_mode->crtc_clock;
fec8cba3 1122 htotal = adjusted_mode->crtc_htotal;
37327abd 1123 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1124 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1125
1126 /* Use the small buffer method to calculate plane watermark */
1127 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1128 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1129 if (tlb_miss > 0)
1130 entries += tlb_miss;
1131 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1132 *plane_wm = entries + display->guard_size;
1133 if (*plane_wm > (int)display->max_wm)
1134 *plane_wm = display->max_wm;
1135
1136 /* Use the large buffer method to calculate cursor watermark */
922044c9 1137 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 1138 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
7bb836dd 1139 entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
b445e3b0
ED		 1140 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1141 if (tlb_miss > 0)
1142 entries += tlb_miss;
1143 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1144 *cursor_wm = entries + cursor->guard_size;
1145 if (*cursor_wm > (int)cursor->max_wm)
1146 *cursor_wm = (int)cursor->max_wm;
1147
1148 return true;
1149}
1150
1151/*
1152 * Check the wm result.
1153 *
1154 * If any calculated watermark values is larger than the maximum value that
1155 * can be programmed into the associated watermark register, that watermark
1156 * must be disabled.
1157 */
1158static bool g4x_check_srwm(struct drm_device *dev,
1159 int display_wm, int cursor_wm,
1160 const struct intel_watermark_params *display,
1161 const struct intel_watermark_params *cursor)
1162{
1163 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1164 display_wm, cursor_wm);
1165
1166 if (display_wm > display->max_wm) {
1167 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1168 display_wm, display->max_wm);
1169 return false;
1170 }
1171
1172 if (cursor_wm > cursor->max_wm) {
1173 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1174 cursor_wm, cursor->max_wm);
1175 return false;
1176 }
1177
1178 if (!(display_wm || cursor_wm)) {
1179 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1180 return false;
1181 }
1182
1183 return true;
1184}
1185
1186static bool g4x_compute_srwm(struct drm_device *dev,
1187 int plane,
1188 int latency_ns,
1189 const struct intel_watermark_params *display,
1190 const struct intel_watermark_params *cursor,
1191 int *display_wm, int *cursor_wm)
1192{
1193 struct drm_crtc *crtc;
4fe8590a 1194 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1195 int hdisplay, htotal, pixel_size, clock;
1196 unsigned long line_time_us;
1197 int line_count, line_size;
1198 int small, large;
1199 int entries;
1200
1201 if (!latency_ns) {
1202 *display_wm = *cursor_wm = 0;
1203 return false;
1204 }
1205
1206 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a 1207 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1208 clock = adjusted_mode->crtc_clock;
fec8cba3 1209 htotal = adjusted_mode->crtc_htotal;
37327abd 1210 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1211 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0 1212
922044c9 1213 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1214 line_count = (latency_ns / line_time_us + 1000) / 1000;
1215 line_size = hdisplay * pixel_size;
1216
1217 /* Use the minimum of the small and large buffer method for primary */
1218 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1219 large = line_count * line_size;
1220
1221 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1222 *display_wm = entries + display->guard_size;
1223
1224 /* calculate the self-refresh watermark for display cursor */
7bb836dd 1225 entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
b445e3b0
ED		 1226 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1227 *cursor_wm = entries + cursor->guard_size;
1228
1229 return g4x_check_srwm(dev,
1230 *display_wm, *cursor_wm,
1231 display, cursor);
1232}
1233
1234static bool vlv_compute_drain_latency(struct drm_device *dev,
1235 int plane,
1236 int *plane_prec_mult,
1237 int *plane_dl,
1238 int *cursor_prec_mult,
1239 int *cursor_dl)
1240{
1241 struct drm_crtc *crtc;
1242 int clock, pixel_size;
1243 int entries;
1244
1245 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1246 if (!intel_crtc_active(crtc))
b445e3b0
ED		 1247 return false;
1248
241bfc38 1249 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
f4510a27 1250 pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
b445e3b0
ED		 1251
1252 entries = (clock / 1000) * pixel_size;
1253 *plane_prec_mult = (entries > 256) ?
1254 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1255 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1256 pixel_size);
1257
1258 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1259 *cursor_prec_mult = (entries > 256) ?
1260 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1261 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1262
1263 return true;
1264}
1265
1266/*
1267 * Update drain latency registers of memory arbiter
1268 *
1269 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1270 * to be programmed. Each plane has a drain latency multiplier and a drain
1271 * latency value.
1272 */
1273
1274static void vlv_update_drain_latency(struct drm_device *dev)
1275{
1276 struct drm_i915_private *dev_priv = dev->dev_private;
1277 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1278 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1279 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1280 either 16 or 32 */
1281
1282 /* For plane A, Cursor A */
1283 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1284 &cursor_prec_mult, &cursora_dl)) {
1285 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1286 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1287 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1288 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1289
1290 I915_WRITE(VLV_DDL1, cursora_prec |
1291 (cursora_dl << DDL_CURSORA_SHIFT) |
1292 planea_prec | planea_dl);
1293 }
1294
1295 /* For plane B, Cursor B */
1296 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1297 &cursor_prec_mult, &cursorb_dl)) {
1298 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1299 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1300 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1301 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1302
1303 I915_WRITE(VLV_DDL2, cursorb_prec |
1304 (cursorb_dl << DDL_CURSORB_SHIFT) |
1305 planeb_prec | planeb_dl);
1306 }
1307}
1308
1309#define single_plane_enabled(mask) is_power_of_2(mask)
1310
46ba614c 1311static void valleyview_update_wm(struct drm_crtc *crtc)
b445e3b0 1312{
46ba614c 1313 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1314 static const int sr_latency_ns = 12000;
1315 struct drm_i915_private *dev_priv = dev->dev_private;
1316 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1317 int plane_sr, cursor_sr;
af6c4575 1318 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0
ED		 1319 unsigned int enabled = 0;
1320
1321 vlv_update_drain_latency(dev);
1322
51cea1f4 1323 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1324 &valleyview_wm_info, latency_ns,
1325 &valleyview_cursor_wm_info, latency_ns,
1326 &planea_wm, &cursora_wm))
51cea1f4 1327 enabled |= 1 << PIPE_A;
b445e3b0 1328
51cea1f4 1329 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1330 &valleyview_wm_info, latency_ns,
1331 &valleyview_cursor_wm_info, latency_ns,
1332 &planeb_wm, &cursorb_wm))
51cea1f4 1333 enabled |= 1 << PIPE_B;
b445e3b0 1334
b445e3b0
ED		 1335 if (single_plane_enabled(enabled) &&
1336 g4x_compute_srwm(dev, ffs(enabled) - 1,
1337 sr_latency_ns,
1338 &valleyview_wm_info,
1339 &valleyview_cursor_wm_info,
af6c4575
CW		 1340 &plane_sr, &ignore_cursor_sr) &&
1341 g4x_compute_srwm(dev, ffs(enabled) - 1,
1342 2*sr_latency_ns,
1343 &valleyview_wm_info,
1344 &valleyview_cursor_wm_info,
52bd02d8 1345 &ignore_plane_sr, &cursor_sr)) {
b445e3b0 1346 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
52bd02d8 1347 } else {
b445e3b0
ED		 1348 I915_WRITE(FW_BLC_SELF_VLV,
1349 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
52bd02d8
CW		 1350 plane_sr = cursor_sr = 0;
1351 }
b445e3b0
ED		 1352
1353 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1354 planea_wm, cursora_wm,
1355 planeb_wm, cursorb_wm,
1356 plane_sr, cursor_sr);
1357
1358 I915_WRITE(DSPFW1,
1359 (plane_sr << DSPFW_SR_SHIFT) |
1360 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1361 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1362 planea_wm);
1363 I915_WRITE(DSPFW2,
8c919b28 1364 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1365 (cursora_wm << DSPFW_CURSORA_SHIFT));
1366 I915_WRITE(DSPFW3,
8c919b28
CW		 1367 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1368 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
b445e3b0
ED		 1369}
1370
46ba614c 1371static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1372{
46ba614c 1373 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1374 static const int sr_latency_ns = 12000;
1375 struct drm_i915_private *dev_priv = dev->dev_private;
1376 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1377 int plane_sr, cursor_sr;
1378 unsigned int enabled = 0;
1379
51cea1f4 1380 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1381 &g4x_wm_info, latency_ns,
1382 &g4x_cursor_wm_info, latency_ns,
1383 &planea_wm, &cursora_wm))
51cea1f4 1384 enabled |= 1 << PIPE_A;
b445e3b0 1385
51cea1f4 1386 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1387 &g4x_wm_info, latency_ns,
1388 &g4x_cursor_wm_info, latency_ns,
1389 &planeb_wm, &cursorb_wm))
51cea1f4 1390 enabled |= 1 << PIPE_B;
b445e3b0 1391
b445e3b0
ED		 1392 if (single_plane_enabled(enabled) &&
1393 g4x_compute_srwm(dev, ffs(enabled) - 1,
1394 sr_latency_ns,
1395 &g4x_wm_info,
1396 &g4x_cursor_wm_info,
52bd02d8 1397 &plane_sr, &cursor_sr)) {
b445e3b0 1398 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
52bd02d8 1399 } else {
b445e3b0
ED		 1400 I915_WRITE(FW_BLC_SELF,
1401 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
52bd02d8
CW		 1402 plane_sr = cursor_sr = 0;
1403 }
b445e3b0
ED		 1404
1405 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1406 planea_wm, cursora_wm,
1407 planeb_wm, cursorb_wm,
1408 plane_sr, cursor_sr);
1409
1410 I915_WRITE(DSPFW1,
1411 (plane_sr << DSPFW_SR_SHIFT) |
1412 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1413 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1414 planea_wm);
1415 I915_WRITE(DSPFW2,
8c919b28 1416 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1417 (cursora_wm << DSPFW_CURSORA_SHIFT));
1418 /* HPLL off in SR has some issues on G4x... disable it */
1419 I915_WRITE(DSPFW3,
8c919b28 1420 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0
ED		 1421 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1422}
1423
46ba614c 1424static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1425{
46ba614c 1426 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1427 struct drm_i915_private *dev_priv = dev->dev_private;
1428 struct drm_crtc *crtc;
1429 int srwm = 1;
1430 int cursor_sr = 16;
1431
1432 /* Calc sr entries for one plane configs */
1433 crtc = single_enabled_crtc(dev);
1434 if (crtc) {
1435 /* self-refresh has much higher latency */
1436 static const int sr_latency_ns = 12000;
4fe8590a
VS		 1437 const struct drm_display_mode *adjusted_mode =
1438 &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1439 int clock = adjusted_mode->crtc_clock;
fec8cba3 1440 int htotal = adjusted_mode->crtc_htotal;
37327abd 1441 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1442 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1443 unsigned long line_time_us;
1444 int entries;
1445
922044c9 1446 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1447
1448 /* Use ns/us then divide to preserve precision */
1449 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1450 pixel_size * hdisplay;
1451 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1452 srwm = I965_FIFO_SIZE - entries;
1453 if (srwm < 0)
1454 srwm = 1;
1455 srwm &= 0x1ff;
1456 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1457 entries, srwm);
1458
1459 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
7bb836dd 1460 pixel_size * to_intel_crtc(crtc)->cursor_width;
b445e3b0
ED		 1461 entries = DIV_ROUND_UP(entries,
1462 i965_cursor_wm_info.cacheline_size);
1463 cursor_sr = i965_cursor_wm_info.fifo_size -
1464 (entries + i965_cursor_wm_info.guard_size);
1465
1466 if (cursor_sr > i965_cursor_wm_info.max_wm)
1467 cursor_sr = i965_cursor_wm_info.max_wm;
1468
1469 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1470 "cursor %d\n", srwm, cursor_sr);
1471
1472 if (IS_CRESTLINE(dev))
1473 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1474 } else {
1475 /* Turn off self refresh if both pipes are enabled */
1476 if (IS_CRESTLINE(dev))
1477 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1478 & ~FW_BLC_SELF_EN);
1479 }
1480
1481 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1482 srwm);
1483
1484 /* 965 has limitations... */
1485 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1486 (8 << 16) | (8 << 8) | (8 << 0));
1487 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1488 /* update cursor SR watermark */
1489 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1490}
1491
46ba614c 1492static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1493{
46ba614c 1494 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1495 struct drm_i915_private *dev_priv = dev->dev_private;
1496 const struct intel_watermark_params *wm_info;
1497 uint32_t fwater_lo;
1498 uint32_t fwater_hi;
1499 int cwm, srwm = 1;
1500 int fifo_size;
1501 int planea_wm, planeb_wm;
1502 struct drm_crtc *crtc, *enabled = NULL;
1503
1504 if (IS_I945GM(dev))
1505 wm_info = &i945_wm_info;
1506 else if (!IS_GEN2(dev))
1507 wm_info = &i915_wm_info;
1508 else
feb56b93 1509 wm_info = &i830_wm_info;
b445e3b0
ED		 1510
1511 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1512 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1513 if (intel_crtc_active(crtc)) {
241bfc38 1514 const struct drm_display_mode *adjusted_mode;
f4510a27 1515 int cpp = crtc->primary->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1516 if (IS_GEN2(dev))
1517 cpp = 4;
1518
241bfc38
DL		 1519 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1520 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1521 wm_info, fifo_size, cpp,
b445e3b0
ED		 1522 latency_ns);
1523 enabled = crtc;
1524 } else
1525 planea_wm = fifo_size - wm_info->guard_size;
1526
1527 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1528 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1529 if (intel_crtc_active(crtc)) {
241bfc38 1530 const struct drm_display_mode *adjusted_mode;
f4510a27 1531 int cpp = crtc->primary->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1532 if (IS_GEN2(dev))
1533 cpp = 4;
1534
241bfc38
DL		 1535 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1536 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1537 wm_info, fifo_size, cpp,
b445e3b0
ED		 1538 latency_ns);
1539 if (enabled == NULL)
1540 enabled = crtc;
1541 else
1542 enabled = NULL;
1543 } else
1544 planeb_wm = fifo_size - wm_info->guard_size;
1545
1546 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1547
2ab1bc9d
DV		 1548 if (IS_I915GM(dev) && enabled) {
1549 struct intel_framebuffer *fb;
1550
1551 fb = to_intel_framebuffer(enabled->primary->fb);
1552
1553 /* self-refresh seems busted with untiled */
1554 if (fb->obj->tiling_mode == I915_TILING_NONE)
1555 enabled = NULL;
1556 }
1557
b445e3b0
ED		 1558 /*
1559 * Overlay gets an aggressive default since video jitter is bad.
1560 */
1561 cwm = 2;
1562
1563 /* Play safe and disable self-refresh before adjusting watermarks. */
1564 if (IS_I945G(dev) || IS_I945GM(dev))
1565 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1566 else if (IS_I915GM(dev))
3f2dc5ac 1567 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_SELF_EN));
b445e3b0
ED		 1568
1569 /* Calc sr entries for one plane configs */
1570 if (HAS_FW_BLC(dev) && enabled) {
1571 /* self-refresh has much higher latency */
1572 static const int sr_latency_ns = 6000;
4fe8590a
VS		 1573 const struct drm_display_mode *adjusted_mode =
1574 &to_intel_crtc(enabled)->config.adjusted_mode;
241bfc38 1575 int clock = adjusted_mode->crtc_clock;
fec8cba3 1576 int htotal = adjusted_mode->crtc_htotal;
f727b490 1577 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
f4510a27 1578 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1579 unsigned long line_time_us;
1580 int entries;
1581
922044c9 1582 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1583
1584 /* Use ns/us then divide to preserve precision */
1585 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1586 pixel_size * hdisplay;
1587 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1588 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1589 srwm = wm_info->fifo_size - entries;
1590 if (srwm < 0)
1591 srwm = 1;
1592
1593 if (IS_I945G(dev) || IS_I945GM(dev))
1594 I915_WRITE(FW_BLC_SELF,
1595 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1596 else if (IS_I915GM(dev))
1597 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1598 }
1599
1600 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1601 planea_wm, planeb_wm, cwm, srwm);
1602
1603 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1604 fwater_hi = (cwm & 0x1f);
1605
1606 /* Set request length to 8 cachelines per fetch */
1607 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1608 fwater_hi = fwater_hi | (1 << 8);
1609
1610 I915_WRITE(FW_BLC, fwater_lo);
1611 I915_WRITE(FW_BLC2, fwater_hi);
1612
1613 if (HAS_FW_BLC(dev)) {
1614 if (enabled) {
1615 if (IS_I945G(dev) || IS_I945GM(dev))
1616 I915_WRITE(FW_BLC_SELF,
1617 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1618 else if (IS_I915GM(dev))
3f2dc5ac 1619 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_SELF_EN));
b445e3b0
ED		 1620 DRM_DEBUG_KMS("memory self refresh enabled\n");
1621 } else
1622 DRM_DEBUG_KMS("memory self refresh disabled\n");
1623 }
1624}
1625
feb56b93 1626static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1627{
46ba614c 1628 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1629 struct drm_i915_private *dev_priv = dev->dev_private;
1630 struct drm_crtc *crtc;
241bfc38 1631 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1632 uint32_t fwater_lo;
1633 int planea_wm;
1634
1635 crtc = single_enabled_crtc(dev);
1636 if (crtc == NULL)
1637 return;
1638
241bfc38
DL		 1639 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1640 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1641 &i845_wm_info,
b445e3b0 1642 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1643 4, latency_ns);
b445e3b0
ED		 1644 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1645 fwater_lo |= (3<<8) | planea_wm;
1646
1647 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1648
1649 I915_WRITE(FW_BLC, fwater_lo);
1650}
1651
3658729a
VS		 1652static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1653 struct drm_crtc *crtc)
801bcfff
PZ		 1654{
1655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fd4daa9c 1656 uint32_t pixel_rate;
801bcfff 1657
241bfc38 1658 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
801bcfff
PZ		 1659
1660 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1661 * adjust the pixel_rate here. */
1662
fd4daa9c 1663 if (intel_crtc->config.pch_pfit.enabled) {
801bcfff 1664 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
fd4daa9c 1665 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
801bcfff 1666
37327abd
VS		 1667 pipe_w = intel_crtc->config.pipe_src_w;
1668 pipe_h = intel_crtc->config.pipe_src_h;
801bcfff
PZ		 1669 pfit_w = (pfit_size >> 16) & 0xFFFF;
1670 pfit_h = pfit_size & 0xFFFF;
1671 if (pipe_w < pfit_w)
1672 pipe_w = pfit_w;
1673 if (pipe_h < pfit_h)
1674 pipe_h = pfit_h;
1675
1676 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1677 pfit_w * pfit_h);
1678 }
1679
1680 return pixel_rate;
1681}
1682
37126462 1683/* latency must be in 0.1us units. */
23297044 1684static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1685 uint32_t latency)
1686{
1687 uint64_t ret;
1688
3312ba65
VS		 1689 if (WARN(latency == 0, "Latency value missing\n"))
1690 return UINT_MAX;
1691
801bcfff
PZ		 1692 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1693 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1694
1695 return ret;
1696}
1697
37126462 1698/* latency must be in 0.1us units. */
23297044 1699static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1700 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1701 uint32_t latency)
1702{
1703 uint32_t ret;
1704
3312ba65
VS		 1705 if (WARN(latency == 0, "Latency value missing\n"))
1706 return UINT_MAX;
1707
801bcfff
PZ		 1708 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1709 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1710 ret = DIV_ROUND_UP(ret, 64) + 2;
1711 return ret;
1712}
1713
23297044 1714static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1715 uint8_t bytes_per_pixel)
1716{
1717 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1718}
1719
820c1980 1720struct ilk_pipe_wm_parameters {
801bcfff 1721 bool active;
801bcfff
PZ		 1722 uint32_t pipe_htotal;
1723 uint32_t pixel_rate;
c35426d2
VS		 1724 struct intel_plane_wm_parameters pri;
1725 struct intel_plane_wm_parameters spr;
1726 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 1727};
1728
820c1980 1729struct ilk_wm_maximums {
cca32e9a
PZ		 1730 uint16_t pri;
1731 uint16_t spr;
1732 uint16_t cur;
1733 uint16_t fbc;
1734};
1735
240264f4
VS		 1736/* used in computing the new watermarks state */
1737struct intel_wm_config {
1738 unsigned int num_pipes_active;
1739 bool sprites_enabled;
1740 bool sprites_scaled;
240264f4
VS		 1741};
1742
37126462
VS		 1743/*
1744 * For both WM_PIPE and WM_LP.
1745 * mem_value must be in 0.1us units.
1746 */
820c1980 1747static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
cca32e9a
PZ		 1748 uint32_t mem_value,
1749 bool is_lp)
801bcfff 1750{
cca32e9a
PZ		 1751 uint32_t method1, method2;
1752
c35426d2 1753 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 1754 return 0;
1755
23297044 1756 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1757 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1758 mem_value);
1759
1760 if (!is_lp)
1761 return method1;
1762
23297044 1763 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 1764 params->pipe_htotal,
c35426d2
VS		 1765 params->pri.horiz_pixels,
1766 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1767 mem_value);
1768
1769 return min(method1, method2);
801bcfff
PZ		 1770}
1771
37126462
VS		 1772/*
1773 * For both WM_PIPE and WM_LP.
1774 * mem_value must be in 0.1us units.
1775 */
820c1980 1776static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1777 uint32_t mem_value)
1778{
1779 uint32_t method1, method2;
1780
c35426d2 1781 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 1782 return 0;
1783
23297044 1784 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1785 params->spr.bytes_per_pixel,
801bcfff 1786 mem_value);
23297044 1787 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 1788 params->pipe_htotal,
c35426d2
VS		 1789 params->spr.horiz_pixels,
1790 params->spr.bytes_per_pixel,
801bcfff
PZ		 1791 mem_value);
1792 return min(method1, method2);
1793}
1794
37126462
VS		 1795/*
1796 * For both WM_PIPE and WM_LP.
1797 * mem_value must be in 0.1us units.
1798 */
820c1980 1799static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1800 uint32_t mem_value)
1801{
c35426d2 1802 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 1803 return 0;
1804
23297044 1805 return ilk_wm_method2(params->pixel_rate,
801bcfff 1806 params->pipe_htotal,
c35426d2
VS		 1807 params->cur.horiz_pixels,
1808 params->cur.bytes_per_pixel,
801bcfff
PZ		 1809 mem_value);
1810}
1811
cca32e9a 1812/* Only for WM_LP. */
820c1980 1813static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1fda9882 1814 uint32_t pri_val)
cca32e9a 1815{
c35426d2 1816 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 1817 return 0;
1818
23297044 1819 return ilk_wm_fbc(pri_val,
c35426d2
VS		 1820 params->pri.horiz_pixels,
1821 params->pri.bytes_per_pixel);
cca32e9a
PZ		 1822}
1823
158ae64f
VS		 1824static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1825{
416f4727
VS		 1826 if (INTEL_INFO(dev)->gen >= 8)
1827 return 3072;
1828 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1829 return 768;
1830 else
1831 return 512;
1832}
1833
4e975081
VS		 1834static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1835 int level, bool is_sprite)
1836{
1837 if (INTEL_INFO(dev)->gen >= 8)
1838 /* BDW primary/sprite plane watermarks */
1839 return level == 0 ? 255 : 2047;
1840 else if (INTEL_INFO(dev)->gen >= 7)
1841 /* IVB/HSW primary/sprite plane watermarks */
1842 return level == 0 ? 127 : 1023;
1843 else if (!is_sprite)
1844 /* ILK/SNB primary plane watermarks */
1845 return level == 0 ? 127 : 511;
1846 else
1847 /* ILK/SNB sprite plane watermarks */
1848 return level == 0 ? 63 : 255;
1849}
1850
1851static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1852 int level)
1853{
1854 if (INTEL_INFO(dev)->gen >= 7)
1855 return level == 0 ? 63 : 255;
1856 else
1857 return level == 0 ? 31 : 63;
1858}
1859
1860static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1861{
1862 if (INTEL_INFO(dev)->gen >= 8)
1863 return 31;
1864 else
1865 return 15;
1866}
1867
158ae64f
VS		 1868/* Calculate the maximum primary/sprite plane watermark */
1869static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1870 int level,
240264f4 1871 const struct intel_wm_config *config,
158ae64f
VS		 1872 enum intel_ddb_partitioning ddb_partitioning,
1873 bool is_sprite)
1874{
1875 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1876
1877 /* if sprites aren't enabled, sprites get nothing */
240264f4 1878 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1879 return 0;
1880
1881 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1882 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1883 fifo_size /= INTEL_INFO(dev)->num_pipes;
1884
1885 /*
1886 * For some reason the non self refresh
1887 * FIFO size is only half of the self
1888 * refresh FIFO size on ILK/SNB.
1889 */
1890 if (INTEL_INFO(dev)->gen <= 6)
1891 fifo_size /= 2;
1892 }
1893
240264f4 1894 if (config->sprites_enabled) {
158ae64f
VS		 1895 /* level 0 is always calculated with 1:1 split */
1896 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1897 if (is_sprite)
1898 fifo_size *= 5;
1899 fifo_size /= 6;
1900 } else {
1901 fifo_size /= 2;
1902 }
1903 }
1904
1905 /* clamp to max that the registers can hold */
4e975081 1906 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1907}
1908
1909/* Calculate the maximum cursor plane watermark */
1910static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1911 int level,
1912 const struct intel_wm_config *config)
158ae64f
VS		 1913{
1914 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1915 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1916 return 64;
1917
1918 /* otherwise just report max that registers can hold */
4e975081 1919 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1920}
1921
d34ff9c6 1922static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1923 int level,
1924 const struct intel_wm_config *config,
1925 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1926 struct ilk_wm_maximums *max)
158ae64f 1927{
240264f4
VS		 1928 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1929 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1930 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1931 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1932}
1933
a3cb4048
VS		 1934static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1935 int level,
1936 struct ilk_wm_maximums *max)
1937{
1938 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1939 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1940 max->cur = ilk_cursor_wm_reg_max(dev, level);
1941 max->fbc = ilk_fbc_wm_reg_max(dev);
1942}
1943
d9395655 1944static bool ilk_validate_wm_level(int level,
820c1980 1945 const struct ilk_wm_maximums *max,
d9395655 1946 struct intel_wm_level *result)
a9786a11
VS		 1947{
1948 bool ret;
1949
1950 /* already determined to be invalid? */
1951 if (!result->enable)
1952 return false;
1953
1954 result->enable = result->pri_val <= max->pri &&
1955 result->spr_val <= max->spr &&
1956 result->cur_val <= max->cur;
1957
1958 ret = result->enable;
1959
1960 /*
1961 * HACK until we can pre-compute everything,
1962 * and thus fail gracefully if LP0 watermarks
1963 * are exceeded...
1964 */
1965 if (level == 0 && !result->enable) {
1966 if (result->pri_val > max->pri)
1967 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1968 level, result->pri_val, max->pri);
1969 if (result->spr_val > max->spr)
1970 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1971 level, result->spr_val, max->spr);
1972 if (result->cur_val > max->cur)
1973 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1974 level, result->cur_val, max->cur);
1975
1976 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1977 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1978 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1979 result->enable = true;
1980 }
1981
a9786a11
VS		 1982 return ret;
1983}
1984
d34ff9c6 1985static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
6f5ddd17 1986 int level,
820c1980 1987 const struct ilk_pipe_wm_parameters *p,
1fd527cc 1988 struct intel_wm_level *result)
6f5ddd17
VS		 1989{
1990 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1991 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1992 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1993
1994 /* WM1+ latency values stored in 0.5us units */
1995 if (level > 0) {
1996 pri_latency *= 5;
1997 spr_latency *= 5;
1998 cur_latency *= 5;
1999 }
2000
2001 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2002 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2003 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2004 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2005 result->enable = true;
2006}
2007
801bcfff
PZ		 2008static uint32_t
2009hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2010{
2011 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2012 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 2013 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 2014 u32 linetime, ips_linetime;
1f8eeabf 2015
801bcfff
PZ		 2016 if (!intel_crtc_active(crtc))
2017 return 0;
1011d8c4 2018
1f8eeabf
ED		 2019 /* The WM are computed with base on how long it takes to fill a single
2020 * row at the given clock rate, multiplied by 8.
2021 * */
fec8cba3
JB		 2022 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2023 mode->crtc_clock);
2024 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
85a02deb 2025 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 2026
801bcfff
PZ		 2027 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2028 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2029}
2030
12b134df
VS		 2031static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2032{
2033 struct drm_i915_private *dev_priv = dev->dev_private;
2034
a42a5719 2035 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2036 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2037
2038 wm[0] = (sskpd >> 56) & 0xFF;
2039 if (wm[0] == 0)
2040 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2041 wm[1] = (sskpd >> 4) & 0xFF;
2042 wm[2] = (sskpd >> 12) & 0xFF;
2043 wm[3] = (sskpd >> 20) & 0x1FF;
2044 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2045 } else if (INTEL_INFO(dev)->gen >= 6) {
2046 uint32_t sskpd = I915_READ(MCH_SSKPD);
2047
2048 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2049 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2050 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2051 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2052 } else if (INTEL_INFO(dev)->gen >= 5) {
2053 uint32_t mltr = I915_READ(MLTR_ILK);
2054
2055 /* ILK primary LP0 latency is 700 ns */
2056 wm[0] = 7;
2057 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2058 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2059 }
2060}
2061
53615a5e
VS		 2062static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2063{
2064 /* ILK sprite LP0 latency is 1300 ns */
2065 if (INTEL_INFO(dev)->gen == 5)
2066 wm[0] = 13;
2067}
2068
2069static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2070{
2071 /* ILK cursor LP0 latency is 1300 ns */
2072 if (INTEL_INFO(dev)->gen == 5)
2073 wm[0] = 13;
2074
2075 /* WaDoubleCursorLP3Latency:ivb */
2076 if (IS_IVYBRIDGE(dev))
2077 wm[3] *= 2;
2078}
2079
546c81fd 2080int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2081{
26ec971e 2082 /* how many WM levels are we expecting */
a42a5719 2083 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2084 return 4;
26ec971e 2085 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2086 return 3;
26ec971e 2087 else
ad0d6dc4
VS		 2088 return 2;
2089}
2090
2091static void intel_print_wm_latency(struct drm_device *dev,
2092 const char *name,
2093 const uint16_t wm[5])
2094{
2095 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2096
2097 for (level = 0; level <= max_level; level++) {
2098 unsigned int latency = wm[level];
2099
2100 if (latency == 0) {
2101 DRM_ERROR("%s WM%d latency not provided\n",
2102 name, level);
2103 continue;
2104 }
2105
2106 /* WM1+ latency values in 0.5us units */
2107 if (level > 0)
2108 latency *= 5;
2109
2110 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2111 name, level, wm[level],
2112 latency / 10, latency % 10);
2113 }
2114}
2115
e95a2f75
VS		 2116static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2117 uint16_t wm[5], uint16_t min)
2118{
2119 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2120
2121 if (wm[0] >= min)
2122 return false;
2123
2124 wm[0] = max(wm[0], min);
2125 for (level = 1; level <= max_level; level++)
2126 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2127
2128 return true;
2129}
2130
2131static void snb_wm_latency_quirk(struct drm_device *dev)
2132{
2133 struct drm_i915_private *dev_priv = dev->dev_private;
2134 bool changed;
2135
2136 /*
2137 * The BIOS provided WM memory latency values are often
2138 * inadequate for high resolution displays. Adjust them.
2139 */
2140 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2141 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2142 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2143
2144 if (!changed)
2145 return;
2146
2147 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2148 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2149 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2150 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2151}
2152
fa50ad61 2153static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2154{
2155 struct drm_i915_private *dev_priv = dev->dev_private;
2156
2157 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2158
2159 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2160 sizeof(dev_priv->wm.pri_latency));
2161 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2162 sizeof(dev_priv->wm.pri_latency));
2163
2164 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2165 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2166
2167 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2168 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2169 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2170
2171 if (IS_GEN6(dev))
2172 snb_wm_latency_quirk(dev);
53615a5e
VS		 2173}
2174
820c1980 2175static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2a44b76b 2176 struct ilk_pipe_wm_parameters *p)
1011d8c4 2177{
7c4a395f
VS		 2178 struct drm_device *dev = crtc->dev;
2179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2180 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2181 struct drm_plane *plane;
1011d8c4 2182
2a44b76b
VS		 2183 if (!intel_crtc_active(crtc))
2184 return;
801bcfff 2185
2a44b76b
VS		 2186 p->active = true;
2187 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2188 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2189 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2190 p->cur.bytes_per_pixel = 4;
2191 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2192 p->cur.horiz_pixels = intel_crtc->cursor_width;
2193 /* TODO: for now, assume primary and cursor planes are always enabled. */
2194 p->pri.enabled = true;
2195 p->cur.enabled = true;
7c4a395f 2196
af2b653b 2197 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
801bcfff 2198 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2199
2a44b76b 2200 if (intel_plane->pipe == pipe) {
7c4a395f 2201 p->spr = intel_plane->wm;
2a44b76b
VS		 2202 break;
2203 }
2204 }
2205}
2206
2207static void ilk_compute_wm_config(struct drm_device *dev,
2208 struct intel_wm_config *config)
2209{
2210 struct intel_crtc *intel_crtc;
2211
2212 /* Compute the currently _active_ config */
d3fcc808 2213 for_each_intel_crtc(dev, intel_crtc) {
2a44b76b 2214 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
cca32e9a 2215
2a44b76b
VS		 2216 if (!wm->pipe_enabled)
2217 continue;
cca32e9a 2218
2a44b76b
VS		 2219 config->sprites_enabled |= wm->sprites_enabled;
2220 config->sprites_scaled |= wm->sprites_scaled;
2221 config->num_pipes_active++;
cca32e9a 2222 }
801bcfff
PZ		 2223}
2224
0b2ae6d7
VS		 2225/* Compute new watermarks for the pipe */
2226static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
820c1980 2227 const struct ilk_pipe_wm_parameters *params,
0b2ae6d7
VS		 2228 struct intel_pipe_wm *pipe_wm)
2229{
2230 struct drm_device *dev = crtc->dev;
d34ff9c6 2231 const struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7
VS		 2232 int level, max_level = ilk_wm_max_level(dev);
2233 /* LP0 watermark maximums depend on this pipe alone */
2234 struct intel_wm_config config = {
2235 .num_pipes_active = 1,
2236 .sprites_enabled = params->spr.enabled,
2237 .sprites_scaled = params->spr.scaled,
2238 };
820c1980 2239 struct ilk_wm_maximums max;
0b2ae6d7 2240
2a44b76b
VS		 2241 pipe_wm->pipe_enabled = params->active;
2242 pipe_wm->sprites_enabled = params->spr.enabled;
2243 pipe_wm->sprites_scaled = params->spr.scaled;
2244
7b39a0b7
VS		 2245 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2246 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2247 max_level = 1;
2248
2249 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2250 if (params->spr.scaled)
2251 max_level = 0;
2252
a3cb4048 2253 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
0b2ae6d7 2254
a42a5719 2255 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2256 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7 2257
a3cb4048
VS		 2258 /* LP0 watermarks always use 1/2 DDB partitioning */
2259 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2260
0b2ae6d7 2261 /* At least LP0 must be valid */
a3cb4048
VS		 2262 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2263 return false;
2264
2265 ilk_compute_wm_reg_maximums(dev, 1, &max);
2266
2267 for (level = 1; level <= max_level; level++) {
2268 struct intel_wm_level wm = {};
2269
2270 ilk_compute_wm_level(dev_priv, level, params, &wm);
2271
2272 /*
2273 * Disable any watermark level that exceeds the
2274 * register maximums since such watermarks are
2275 * always invalid.
2276 */
2277 if (!ilk_validate_wm_level(level, &max, &wm))
2278 break;
2279
2280 pipe_wm->wm[level] = wm;
2281 }
2282
2283 return true;
0b2ae6d7
VS		 2284}
2285
2286/*
2287 * Merge the watermarks from all active pipes for a specific level.
2288 */
2289static void ilk_merge_wm_level(struct drm_device *dev,
2290 int level,
2291 struct intel_wm_level *ret_wm)
2292{
2293 const struct intel_crtc *intel_crtc;
2294
d52fea5b
VS		 2295 ret_wm->enable = true;
2296
d3fcc808 2297 for_each_intel_crtc(dev, intel_crtc) {
fe392efd
VS		 2298 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2299 const struct intel_wm_level *wm = &active->wm[level];
2300
2301 if (!active->pipe_enabled)
2302 continue;
0b2ae6d7 2303
d52fea5b
VS		 2304 /*
2305 * The watermark values may have been used in the past,
2306 * so we must maintain them in the registers for some
2307 * time even if the level is now disabled.
2308 */
0b2ae6d7 2309 if (!wm->enable)
d52fea5b 2310 ret_wm->enable = false;
0b2ae6d7
VS		 2311
2312 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2313 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2314 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2315 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2316 }
0b2ae6d7
VS		 2317}
2318
2319/*
2320 * Merge all low power watermarks for all active pipes.
2321 */
2322static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2323 const struct intel_wm_config *config,
820c1980 2324 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2325 struct intel_pipe_wm *merged)
2326{
2327 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2328 int last_enabled_level = max_level;
0b2ae6d7 2329
0ba22e26
VS		 2330 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2331 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2332 config->num_pipes_active > 1)
2333 return;
2334
6c8b6c28
VS		 2335 /* ILK: FBC WM must be disabled always */
2336 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2337
2338 /* merge each WM1+ level */
2339 for (level = 1; level <= max_level; level++) {
2340 struct intel_wm_level *wm = &merged->wm[level];
2341
2342 ilk_merge_wm_level(dev, level, wm);
2343
d52fea5b
VS		 2344 if (level > last_enabled_level)
2345 wm->enable = false;
2346 else if (!ilk_validate_wm_level(level, max, wm))
2347 /* make sure all following levels get disabled */
2348 last_enabled_level = level - 1;
0b2ae6d7
VS		 2349
2350 /*
2351 * The spec says it is preferred to disable
2352 * FBC WMs instead of disabling a WM level.
2353 */
2354 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2355 if (wm->enable)
2356 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2357 wm->fbc_val = 0;
2358 }
2359 }
6c8b6c28
VS		 2360
2361 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2362 /*
2363 * FIXME this is racy. FBC might get enabled later.
2364 * What we should check here is whether FBC can be
2365 * enabled sometime later.
2366 */
2367 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2368 for (level = 2; level <= max_level; level++) {
2369 struct intel_wm_level *wm = &merged->wm[level];
2370
2371 wm->enable = false;
2372 }
2373 }
0b2ae6d7
VS		 2374}
2375
b380ca3c
VS		 2376static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2377{
2378 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2379 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2380}
2381
a68d68ee
VS		 2382/* The value we need to program into the WM_LPx latency field */
2383static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2384{
2385 struct drm_i915_private *dev_priv = dev->dev_private;
2386
a42a5719 2387 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2388 return 2 * level;
2389 else
2390 return dev_priv->wm.pri_latency[level];
2391}
2392
820c1980 2393static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2394 const struct intel_pipe_wm *merged,
609cedef 2395 enum intel_ddb_partitioning partitioning,
820c1980 2396 struct ilk_wm_values *results)
801bcfff 2397{
0b2ae6d7
VS		 2398 struct intel_crtc *intel_crtc;
2399 int level, wm_lp;
cca32e9a 2400
0362c781 2401 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2402 results->partitioning = partitioning;
cca32e9a 2403
0b2ae6d7 2404 /* LP1+ register values */
cca32e9a 2405 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2406 const struct intel_wm_level *r;
801bcfff 2407
b380ca3c 2408 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2409
0362c781 2410 r = &merged->wm[level];
cca32e9a 2411
d52fea5b
VS		 2412 /*
2413 * Maintain the watermark values even if the level is
2414 * disabled. Doing otherwise could cause underruns.
2415 */
2416 results->wm_lp[wm_lp - 1] =
a68d68ee 2417 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2418 (r->pri_val << WM1_LP_SR_SHIFT) |
2419 r->cur_val;
2420
d52fea5b
VS		 2421 if (r->enable)
2422 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2423
416f4727
VS		 2424 if (INTEL_INFO(dev)->gen >= 8)
2425 results->wm_lp[wm_lp - 1] |=
2426 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2427 else
2428 results->wm_lp[wm_lp - 1] |=
2429 r->fbc_val << WM1_LP_FBC_SHIFT;
2430
d52fea5b
VS		 2431 /*
2432 * Always set WM1S_LP_EN when spr_val != 0, even if the
2433 * level is disabled. Doing otherwise could cause underruns.
2434 */
6cef2b8a
VS		 2435 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2436 WARN_ON(wm_lp != 1);
2437 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2438 } else
2439 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2440 }
801bcfff 2441
0b2ae6d7 2442 /* LP0 register values */
d3fcc808 2443 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7
VS		 2444 enum pipe pipe = intel_crtc->pipe;
2445 const struct intel_wm_level *r =
2446 &intel_crtc->wm.active.wm[0];
2447
2448 if (WARN_ON(!r->enable))
2449 continue;
2450
2451 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2452
0b2ae6d7
VS		 2453 results->wm_pipe[pipe] =
2454 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2455 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2456 r->cur_val;
801bcfff
PZ		 2457 }
2458}
2459
861f3389
PZ		 2460/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2461 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2462static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2463 struct intel_pipe_wm *r1,
2464 struct intel_pipe_wm *r2)
861f3389 2465{
198a1e9b
VS		 2466 int level, max_level = ilk_wm_max_level(dev);
2467 int level1 = 0, level2 = 0;
861f3389 2468
198a1e9b
VS		 2469 for (level = 1; level <= max_level; level++) {
2470 if (r1->wm[level].enable)
2471 level1 = level;
2472 if (r2->wm[level].enable)
2473 level2 = level;
861f3389
PZ		 2474 }
2475
198a1e9b
VS		 2476 if (level1 == level2) {
2477 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2478 return r2;
2479 else
2480 return r1;
198a1e9b 2481 } else if (level1 > level2) {
861f3389
PZ		 2482 return r1;
2483 } else {
2484 return r2;
2485 }
2486}
2487
49a687c4
VS		 2488/* dirty bits used to track which watermarks need changes */
2489#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2490#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2491#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2492#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2493#define WM_DIRTY_FBC (1 << 24)
2494#define WM_DIRTY_DDB (1 << 25)
2495
2496static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
820c1980
ID		 2497 const struct ilk_wm_values *old,
2498 const struct ilk_wm_values *new)
49a687c4
VS		 2499{
2500 unsigned int dirty = 0;
2501 enum pipe pipe;
2502 int wm_lp;
2503
2504 for_each_pipe(pipe) {
2505 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2506 dirty |= WM_DIRTY_LINETIME(pipe);
2507 /* Must disable LP1+ watermarks too */
2508 dirty |= WM_DIRTY_LP_ALL;
2509 }
2510
2511 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2512 dirty |= WM_DIRTY_PIPE(pipe);
2513 /* Must disable LP1+ watermarks too */
2514 dirty |= WM_DIRTY_LP_ALL;
2515 }
2516 }
2517
2518 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2519 dirty |= WM_DIRTY_FBC;
2520 /* Must disable LP1+ watermarks too */
2521 dirty |= WM_DIRTY_LP_ALL;
2522 }
2523
2524 if (old->partitioning != new->partitioning) {
2525 dirty |= WM_DIRTY_DDB;
2526 /* Must disable LP1+ watermarks too */
2527 dirty |= WM_DIRTY_LP_ALL;
2528 }
2529
2530 /* LP1+ watermarks already deemed dirty, no need to continue */
2531 if (dirty & WM_DIRTY_LP_ALL)
2532 return dirty;
2533
2534 /* Find the lowest numbered LP1+ watermark in need of an update... */
2535 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2536 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2537 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2538 break;
2539 }
2540
2541 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2542 for (; wm_lp <= 3; wm_lp++)
2543 dirty |= WM_DIRTY_LP(wm_lp);
2544
2545 return dirty;
2546}
2547
8553c18e
VS		 2548static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2549 unsigned int dirty)
801bcfff 2550{
820c1980 2551 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2552 bool changed = false;
801bcfff 2553
facd619b
VS		 2554 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2555 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2556 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2557 changed = true;
facd619b
VS		 2558 }
2559 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2560 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2561 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2562 changed = true;
facd619b
VS		 2563 }
2564 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2565 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2566 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2567 changed = true;
facd619b 2568 }
801bcfff 2569
facd619b
VS		 2570 /*
2571 * Don't touch WM1S_LP_EN here.
2572 * Doing so could cause underruns.
2573 */
6cef2b8a 2574
8553c18e
VS		 2575 return changed;
2576}
2577
2578/*
2579 * The spec says we shouldn't write when we don't need, because every write
2580 * causes WMs to be re-evaluated, expending some power.
2581 */
820c1980
ID		 2582static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2583 struct ilk_wm_values *results)
8553c18e
VS		 2584{
2585 struct drm_device *dev = dev_priv->dev;
820c1980 2586 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2587 unsigned int dirty;
2588 uint32_t val;
2589
2590 dirty = ilk_compute_wm_dirty(dev, previous, results);
2591 if (!dirty)
2592 return;
2593
2594 _ilk_disable_lp_wm(dev_priv, dirty);
2595
49a687c4 2596 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2597 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2598 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2599 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2600 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2601 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2602
49a687c4 2603 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2604 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2605 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2606 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2607 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2608 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2609
49a687c4 2610 if (dirty & WM_DIRTY_DDB) {
a42a5719 2611 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2612 val = I915_READ(WM_MISC);
2613 if (results->partitioning == INTEL_DDB_PART_1_2)
2614 val &= ~WM_MISC_DATA_PARTITION_5_6;
2615 else
2616 val |= WM_MISC_DATA_PARTITION_5_6;
2617 I915_WRITE(WM_MISC, val);
2618 } else {
2619 val = I915_READ(DISP_ARB_CTL2);
2620 if (results->partitioning == INTEL_DDB_PART_1_2)
2621 val &= ~DISP_DATA_PARTITION_5_6;
2622 else
2623 val |= DISP_DATA_PARTITION_5_6;
2624 I915_WRITE(DISP_ARB_CTL2, val);
2625 }
1011d8c4
PZ		 2626 }
2627
49a687c4 2628 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2629 val = I915_READ(DISP_ARB_CTL);
2630 if (results->enable_fbc_wm)
2631 val &= ~DISP_FBC_WM_DIS;
2632 else
2633 val |= DISP_FBC_WM_DIS;
2634 I915_WRITE(DISP_ARB_CTL, val);
2635 }
2636
954911eb
ID		 2637 if (dirty & WM_DIRTY_LP(1) &&
2638 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2639 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2640
2641 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2642 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2643 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2644 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2645 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2646 }
801bcfff 2647
facd619b 2648 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2649 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2650 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2651 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2652 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2653 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2654
2655 dev_priv->wm.hw = *results;
801bcfff
PZ		 2656}
2657
8553c18e
VS		 2658static bool ilk_disable_lp_wm(struct drm_device *dev)
2659{
2660 struct drm_i915_private *dev_priv = dev->dev_private;
2661
2662 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2663}
2664
820c1980 2665static void ilk_update_wm(struct drm_crtc *crtc)
801bcfff 2666{
7c4a395f 2667 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 2668 struct drm_device *dev = crtc->dev;
801bcfff 2669 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980
ID		 2670 struct ilk_wm_maximums max;
2671 struct ilk_pipe_wm_parameters params = {};
2672 struct ilk_wm_values results = {};
77c122bc 2673 enum intel_ddb_partitioning partitioning;
7c4a395f 2674 struct intel_pipe_wm pipe_wm = {};
198a1e9b 2675 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 2676 struct intel_wm_config config = {};
7c4a395f 2677
2a44b76b 2678 ilk_compute_wm_parameters(crtc, &params);
7c4a395f
VS		 2679
2680 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2681
2682 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2683 return;
861f3389 2684
7c4a395f 2685 intel_crtc->wm.active = pipe_wm;
861f3389 2686
2a44b76b
VS		 2687 ilk_compute_wm_config(dev, &config);
2688
34982fe1 2689 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
0ba22e26 2690 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 2691
2692 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 2693 if (INTEL_INFO(dev)->gen >= 7 &&
2694 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 2695 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
0ba22e26 2696 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 2697
820c1980 2698 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 2699 } else {
198a1e9b 2700 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 2701 }
2702
198a1e9b 2703 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 2704 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 2705
820c1980 2706 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 2707
820c1980 2708 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 2709}
2710
820c1980 2711static void ilk_update_sprite_wm(struct drm_plane *plane,
adf3d35e 2712 struct drm_crtc *crtc,
526682e9 2713 uint32_t sprite_width, int pixel_size,
bdd57d03 2714 bool enabled, bool scaled)
526682e9 2715{
8553c18e 2716 struct drm_device *dev = plane->dev;
adf3d35e 2717 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 2718
adf3d35e
VS		 2719 intel_plane->wm.enabled = enabled;
2720 intel_plane->wm.scaled = scaled;
2721 intel_plane->wm.horiz_pixels = sprite_width;
2722 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 2723
8553c18e
VS		 2724 /*
2725 * IVB workaround: must disable low power watermarks for at least
2726 * one frame before enabling scaling. LP watermarks can be re-enabled
2727 * when scaling is disabled.
2728 *
2729 * WaCxSRDisabledForSpriteScaling:ivb
2730 */
2731 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2732 intel_wait_for_vblank(dev, intel_plane->pipe);
2733
820c1980 2734 ilk_update_wm(crtc);
526682e9
PZ		 2735}
2736
243e6a44
VS		 2737static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2738{
2739 struct drm_device *dev = crtc->dev;
2740 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 2741 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 2742 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2743 struct intel_pipe_wm *active = &intel_crtc->wm.active;
2744 enum pipe pipe = intel_crtc->pipe;
2745 static const unsigned int wm0_pipe_reg[] = {
2746 [PIPE_A] = WM0_PIPEA_ILK,
2747 [PIPE_B] = WM0_PIPEB_ILK,
2748 [PIPE_C] = WM0_PIPEC_IVB,
2749 };
2750
2751 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 2752 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2753 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 2754
2a44b76b
VS		 2755 active->pipe_enabled = intel_crtc_active(crtc);
2756
2757 if (active->pipe_enabled) {
243e6a44
VS		 2758 u32 tmp = hw->wm_pipe[pipe];
2759
2760 /*
2761 * For active pipes LP0 watermark is marked as
2762 * enabled, and LP1+ watermaks as disabled since
2763 * we can't really reverse compute them in case
2764 * multiple pipes are active.
2765 */
2766 active->wm[0].enable = true;
2767 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2768 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2769 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2770 active->linetime = hw->wm_linetime[pipe];
2771 } else {
2772 int level, max_level = ilk_wm_max_level(dev);
2773
2774 /*
2775 * For inactive pipes, all watermark levels
2776 * should be marked as enabled but zeroed,
2777 * which is what we'd compute them to.
2778 */
2779 for (level = 0; level <= max_level; level++)
2780 active->wm[level].enable = true;
2781 }
2782}
2783
2784void ilk_wm_get_hw_state(struct drm_device *dev)
2785{
2786 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 2787 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 2788 struct drm_crtc *crtc;
2789
70e1e0ec 2790 for_each_crtc(dev, crtc)
243e6a44
VS		 2791 ilk_pipe_wm_get_hw_state(crtc);
2792
2793 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2794 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2795 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2796
2797 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 2798 if (INTEL_INFO(dev)->gen >= 7) {
2799 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2800 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2801 }
243e6a44 2802
a42a5719 2803 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 2804 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2805 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2806 else if (IS_IVYBRIDGE(dev))
2807 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2808 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 2809
2810 hw->enable_fbc_wm =
2811 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2812}
2813
b445e3b0
ED		 2814/**
2815 * intel_update_watermarks - update FIFO watermark values based on current modes
2816 *
2817 * Calculate watermark values for the various WM regs based on current mode
2818 * and plane configuration.
2819 *
2820 * There are several cases to deal with here:
2821 * - normal (i.e. non-self-refresh)
2822 * - self-refresh (SR) mode
2823 * - lines are large relative to FIFO size (buffer can hold up to 2)
2824 * - lines are small relative to FIFO size (buffer can hold more than 2
2825 * lines), so need to account for TLB latency
2826 *
2827 * The normal calculation is:
2828 * watermark = dotclock * bytes per pixel * latency
2829 * where latency is platform & configuration dependent (we assume pessimal
2830 * values here).
2831 *
2832 * The SR calculation is:
2833 * watermark = (trunc(latency/line time)+1) * surface width *
2834 * bytes per pixel
2835 * where
2836 * line time = htotal / dotclock
2837 * surface width = hdisplay for normal plane and 64 for cursor
2838 * and latency is assumed to be high, as above.
2839 *
2840 * The final value programmed to the register should always be rounded up,
2841 * and include an extra 2 entries to account for clock crossings.
2842 *
2843 * We don't use the sprite, so we can ignore that. And on Crestline we have
2844 * to set the non-SR watermarks to 8.
2845 */
46ba614c 2846void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 2847{
46ba614c 2848 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 2849
2850 if (dev_priv->display.update_wm)
46ba614c 2851 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 2852}
2853
adf3d35e
VS		 2854void intel_update_sprite_watermarks(struct drm_plane *plane,
2855 struct drm_crtc *crtc,
4c4ff43a 2856 uint32_t sprite_width, int pixel_size,
39db4a4d 2857 bool enabled, bool scaled)
b445e3b0 2858{
adf3d35e 2859 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 2860
2861 if (dev_priv->display.update_sprite_wm)
adf3d35e 2862 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
39db4a4d 2863 pixel_size, enabled, scaled);
b445e3b0
ED		 2864}
2865
2b4e57bd
ED		 2866static struct drm_i915_gem_object *
2867intel_alloc_context_page(struct drm_device *dev)
2868{
2869 struct drm_i915_gem_object *ctx;
2870 int ret;
2871
2872 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2873
2874 ctx = i915_gem_alloc_object(dev, 4096);
2875 if (!ctx) {
2876 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2877 return NULL;
2878 }
2879
c69766f2 2880 ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
2b4e57bd
ED		 2881 if (ret) {
2882 DRM_ERROR("failed to pin power context: %d\n", ret);
2883 goto err_unref;
2884 }
2885
2886 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2887 if (ret) {
2888 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2889 goto err_unpin;
2890 }
2891
2892 return ctx;
2893
2894err_unpin:
d7f46fc4 2895 i915_gem_object_ggtt_unpin(ctx);
2b4e57bd
ED		 2896err_unref:
2897 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 2898 return NULL;
2899}
2900
9270388e
DV		 2901/**
2902 * Lock protecting IPS related data structures
9270388e
DV		 2903 */
2904DEFINE_SPINLOCK(mchdev_lock);
2905
2906/* Global for IPS driver to get at the current i915 device. Protected by
2907 * mchdev_lock. */
2908static struct drm_i915_private *i915_mch_dev;
2909
2b4e57bd
ED		 2910bool ironlake_set_drps(struct drm_device *dev, u8 val)
2911{
2912 struct drm_i915_private *dev_priv = dev->dev_private;
2913 u16 rgvswctl;
2914
9270388e
DV		 2915 assert_spin_locked(&mchdev_lock);
2916
2b4e57bd
ED		 2917 rgvswctl = I915_READ16(MEMSWCTL);
2918 if (rgvswctl & MEMCTL_CMD_STS) {
2919 DRM_DEBUG("gpu busy, RCS change rejected\n");
2920 return false; /* still busy with another command */
2921 }
2922
2923 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2924 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2925 I915_WRITE16(MEMSWCTL, rgvswctl);
2926 POSTING_READ16(MEMSWCTL);
2927
2928 rgvswctl |= MEMCTL_CMD_STS;
2929 I915_WRITE16(MEMSWCTL, rgvswctl);
2930
2931 return true;
2932}
2933
8090c6b9 2934static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 2935{
2936 struct drm_i915_private *dev_priv = dev->dev_private;
2937 u32 rgvmodectl = I915_READ(MEMMODECTL);
2938 u8 fmax, fmin, fstart, vstart;
2939
9270388e
DV		 2940 spin_lock_irq(&mchdev_lock);
2941
2b4e57bd
ED		 2942 /* Enable temp reporting */
2943 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2944 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2945
2946 /* 100ms RC evaluation intervals */
2947 I915_WRITE(RCUPEI, 100000);
2948 I915_WRITE(RCDNEI, 100000);
2949
2950 /* Set max/min thresholds to 90ms and 80ms respectively */
2951 I915_WRITE(RCBMAXAVG, 90000);
2952 I915_WRITE(RCBMINAVG, 80000);
2953
2954 I915_WRITE(MEMIHYST, 1);
2955
2956 /* Set up min, max, and cur for interrupt handling */
2957 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2958 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2959 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2960 MEMMODE_FSTART_SHIFT;
2961
2962 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2963 PXVFREQ_PX_SHIFT;
2964
20e4d407
DV		 2965 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2966 dev_priv->ips.fstart = fstart;
2b4e57bd 2967
20e4d407
DV		 2968 dev_priv->ips.max_delay = fstart;
2969 dev_priv->ips.min_delay = fmin;
2970 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 2971
2972 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2973 fmax, fmin, fstart);
2974
2975 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2976
2977 /*
2978 * Interrupts will be enabled in ironlake_irq_postinstall
2979 */
2980
2981 I915_WRITE(VIDSTART, vstart);
2982 POSTING_READ(VIDSTART);
2983
2984 rgvmodectl |= MEMMODE_SWMODE_EN;
2985 I915_WRITE(MEMMODECTL, rgvmodectl);
2986
9270388e 2987 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 2988 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 2989 mdelay(1);
2b4e57bd
ED		 2990
2991 ironlake_set_drps(dev, fstart);
2992
20e4d407 2993 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 2994 I915_READ(0x112e0);
20e4d407
DV		 2995 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2996 dev_priv->ips.last_count2 = I915_READ(0x112f4);
2997 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 2998
2999 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3000}
3001
8090c6b9 3002static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 3003{
3004 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 3005 u16 rgvswctl;
3006
3007 spin_lock_irq(&mchdev_lock);
3008
3009 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 3010
3011 /* Ack interrupts, disable EFC interrupt */
3012 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3013 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3014 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3015 I915_WRITE(DEIIR, DE_PCU_EVENT);
3016 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3017
3018 /* Go back to the starting frequency */
20e4d407 3019 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 3020 mdelay(1);
2b4e57bd
ED		 3021 rgvswctl |= MEMCTL_CMD_STS;
3022 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 3023 mdelay(1);
2b4e57bd 3024
9270388e 3025 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3026}
3027
acbe9475
DV		 3028/* There's a funny hw issue where the hw returns all 0 when reading from
3029 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3030 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3031 * all limits and the gpu stuck at whatever frequency it is at atm).
3032 */
6917c7b9 3033static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 3034{
7b9e0ae6 3035 u32 limits;
2b4e57bd 3036
20b46e59
DV		 3037 /* Only set the down limit when we've reached the lowest level to avoid
3038 * getting more interrupts, otherwise leave this clear. This prevents a
3039 * race in the hw when coming out of rc6: There's a tiny window where
3040 * the hw runs at the minimal clock before selecting the desired
3041 * frequency, if the down threshold expires in that window we will not
3042 * receive a down interrupt. */
b39fb297
BW		 3043 limits = dev_priv->rps.max_freq_softlimit << 24;
3044 if (val <= dev_priv->rps.min_freq_softlimit)
3045 limits |= dev_priv->rps.min_freq_softlimit << 16;
20b46e59
DV		 3046
3047 return limits;
3048}
3049
dd75fdc8
CW		 3050static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3051{
3052 int new_power;
3053
3054 new_power = dev_priv->rps.power;
3055 switch (dev_priv->rps.power) {
3056 case LOW_POWER:
b39fb297 3057 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3058 new_power = BETWEEN;
3059 break;
3060
3061 case BETWEEN:
b39fb297 3062 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 3063 new_power = LOW_POWER;
b39fb297 3064 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3065 new_power = HIGH_POWER;
3066 break;
3067
3068 case HIGH_POWER:
b39fb297 3069 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 3070 new_power = BETWEEN;
3071 break;
3072 }
3073 /* Max/min bins are special */
b39fb297 3074 if (val == dev_priv->rps.min_freq_softlimit)
dd75fdc8 3075 new_power = LOW_POWER;
b39fb297 3076 if (val == dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 3077 new_power = HIGH_POWER;
3078 if (new_power == dev_priv->rps.power)
3079 return;
3080
3081 /* Note the units here are not exactly 1us, but 1280ns. */
3082 switch (new_power) {
3083 case LOW_POWER:
3084 /* Upclock if more than 95% busy over 16ms */
3085 I915_WRITE(GEN6_RP_UP_EI, 12500);
3086 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3087
3088 /* Downclock if less than 85% busy over 32ms */
3089 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3090 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3091
3092 I915_WRITE(GEN6_RP_CONTROL,
3093 GEN6_RP_MEDIA_TURBO |
3094 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3095 GEN6_RP_MEDIA_IS_GFX |
3096 GEN6_RP_ENABLE |
3097 GEN6_RP_UP_BUSY_AVG |
3098 GEN6_RP_DOWN_IDLE_AVG);
3099 break;
3100
3101 case BETWEEN:
3102 /* Upclock if more than 90% busy over 13ms */
3103 I915_WRITE(GEN6_RP_UP_EI, 10250);
3104 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3105
3106 /* Downclock if less than 75% busy over 32ms */
3107 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3108 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3109
3110 I915_WRITE(GEN6_RP_CONTROL,
3111 GEN6_RP_MEDIA_TURBO |
3112 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3113 GEN6_RP_MEDIA_IS_GFX |
3114 GEN6_RP_ENABLE |
3115 GEN6_RP_UP_BUSY_AVG |
3116 GEN6_RP_DOWN_IDLE_AVG);
3117 break;
3118
3119 case HIGH_POWER:
3120 /* Upclock if more than 85% busy over 10ms */
3121 I915_WRITE(GEN6_RP_UP_EI, 8000);
3122 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3123
3124 /* Downclock if less than 60% busy over 32ms */
3125 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3126 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3127
3128 I915_WRITE(GEN6_RP_CONTROL,
3129 GEN6_RP_MEDIA_TURBO |
3130 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3131 GEN6_RP_MEDIA_IS_GFX |
3132 GEN6_RP_ENABLE |
3133 GEN6_RP_UP_BUSY_AVG |
3134 GEN6_RP_DOWN_IDLE_AVG);
3135 break;
3136 }
3137
3138 dev_priv->rps.power = new_power;
3139 dev_priv->rps.last_adj = 0;
3140}
3141
2876ce73
CW		 3142static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3143{
3144 u32 mask = 0;
3145
3146 if (val > dev_priv->rps.min_freq_softlimit)
3147 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3148 if (val < dev_priv->rps.max_freq_softlimit)
3149 mask |= GEN6_PM_RP_UP_THRESHOLD;
3150
3151 /* IVB and SNB hard hangs on looping batchbuffer
3152 * if GEN6_PM_UP_EI_EXPIRED is masked.
3153 */
3154 if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3155 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3156
baccd458
D		 3157 if (IS_GEN8(dev_priv->dev))
3158 mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
3159
2876ce73
CW		 3160 return ~mask;
3161}
3162
b8a5ff8d
JM		 3163/* gen6_set_rps is called to update the frequency request, but should also be
3164 * called when the range (min_delay and max_delay) is modified so that we can
3165 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
20b46e59
DV		 3166void gen6_set_rps(struct drm_device *dev, u8 val)
3167{
3168 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 3169
4fc688ce 3170 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
b39fb297
BW		 3171 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3172 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
004777cb 3173
eb64cad1
CW		 3174 /* min/max delay may still have been modified so be sure to
3175 * write the limits value.
3176 */
3177 if (val != dev_priv->rps.cur_freq) {
3178 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 3179
50e6a2a7 3180 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 3181 I915_WRITE(GEN6_RPNSWREQ,
3182 HSW_FREQUENCY(val));
3183 else
3184 I915_WRITE(GEN6_RPNSWREQ,
3185 GEN6_FREQUENCY(val) |
3186 GEN6_OFFSET(0) |
3187 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 3188 }
7b9e0ae6 3189
7b9e0ae6
CW		 3190 /* Make sure we continue to get interrupts
3191 * until we hit the minimum or maximum frequencies.
3192 */
eb64cad1 3193 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
2876ce73 3194 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 3195
d5570a72
BW		 3196 POSTING_READ(GEN6_RPNSWREQ);
3197
b39fb297 3198 dev_priv->rps.cur_freq = val;
be2cde9a 3199 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3200}
3201
76c3552f
D		 3202/* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3203 *
3204 * * If Gfx is Idle, then
3205 * 1. Mask Turbo interrupts
3206 * 2. Bring up Gfx clock
3207 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3208 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3209 * 5. Unmask Turbo interrupts
3210*/
3211static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3212{
3213 /*
3214 * When we are idle. Drop to min voltage state.
3215 */
3216
b39fb297 3217 if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
76c3552f
D		 3218 return;
3219
3220 /* Mask turbo interrupt so that they will not come in between */
3221 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3222
650ad970 3223 vlv_force_gfx_clock(dev_priv, true);
76c3552f 3224
b39fb297 3225 dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
76c3552f
D		 3226
3227 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
b39fb297 3228 dev_priv->rps.min_freq_softlimit);
76c3552f
D		 3229
3230 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3231 & GENFREQSTATUS) == 0, 5))
3232 DRM_ERROR("timed out waiting for Punit\n");
3233
650ad970 3234 vlv_force_gfx_clock(dev_priv, false);
76c3552f 3235
2876ce73
CW		 3236 I915_WRITE(GEN6_PMINTRMSK,
3237 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
76c3552f
D		 3238}
3239
b29c19b6
CW		 3240void gen6_rps_idle(struct drm_i915_private *dev_priv)
3241{
691bb717
DL		 3242 struct drm_device *dev = dev_priv->dev;
3243
b29c19b6 3244 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3245 if (dev_priv->rps.enabled) {
691bb717 3246 if (IS_VALLEYVIEW(dev))
76c3552f 3247 vlv_set_rps_idle(dev_priv);
c0951f0c 3248 else
b39fb297 3249 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
c0951f0c
CW		 3250 dev_priv->rps.last_adj = 0;
3251 }
b29c19b6
CW		 3252 mutex_unlock(&dev_priv->rps.hw_lock);
3253}
3254
3255void gen6_rps_boost(struct drm_i915_private *dev_priv)
3256{
691bb717
DL		 3257 struct drm_device *dev = dev_priv->dev;
3258
b29c19b6 3259 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3260 if (dev_priv->rps.enabled) {
691bb717 3261 if (IS_VALLEYVIEW(dev))
b39fb297 3262 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
c0951f0c 3263 else
b39fb297 3264 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
c0951f0c
CW		 3265 dev_priv->rps.last_adj = 0;
3266 }
b29c19b6
CW		 3267 mutex_unlock(&dev_priv->rps.hw_lock);
3268}
3269
0a073b84
JB		 3270void valleyview_set_rps(struct drm_device *dev, u8 val)
3271{
3272 struct drm_i915_private *dev_priv = dev->dev_private;
7a67092a 3273
0a073b84 3274 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
b39fb297
BW		 3275 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3276 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
0a073b84 3277
73008b98 3278 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
b39fb297
BW		 3279 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3280 dev_priv->rps.cur_freq,
2ec3815f 3281 vlv_gpu_freq(dev_priv, val), val);
0a073b84 3282
2876ce73
CW		 3283 if (val != dev_priv->rps.cur_freq)
3284 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
0a073b84 3285
09c87db8 3286 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
0a073b84 3287
b39fb297 3288 dev_priv->rps.cur_freq = val;
2ec3815f 3289 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
0a073b84
JB		 3290}
3291
0961021a
BW		 3292static void gen8_disable_rps_interrupts(struct drm_device *dev)
3293{
3294 struct drm_i915_private *dev_priv = dev->dev_private;
3295
992f191f 3296 I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
0961021a
BW		 3297 I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
3298 ~dev_priv->pm_rps_events);
3299 /* Complete PM interrupt masking here doesn't race with the rps work
3300 * item again unmasking PM interrupts because that is using a different
3301 * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
3302 * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
3303 * gen8_enable_rps will clean up. */
3304
3305 spin_lock_irq(&dev_priv->irq_lock);
3306 dev_priv->rps.pm_iir = 0;
3307 spin_unlock_irq(&dev_priv->irq_lock);
3308
3309 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3310}
3311
44fc7d5c 3312static void gen6_disable_rps_interrupts(struct drm_device *dev)
2b4e57bd
ED		 3313{
3314 struct drm_i915_private *dev_priv = dev->dev_private;
3315
2b4e57bd 3316 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
a6706b45
D		 3317 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3318 ~dev_priv->pm_rps_events);
2b4e57bd
ED		 3319 /* Complete PM interrupt masking here doesn't race with the rps work
3320 * item again unmasking PM interrupts because that is using a different
3321 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3322 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3323
59cdb63d 3324 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3 3325 dev_priv->rps.pm_iir = 0;
59cdb63d 3326 spin_unlock_irq(&dev_priv->irq_lock);
2b4e57bd 3327
a6706b45 3328 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
2b4e57bd
ED		 3329}
3330
44fc7d5c 3331static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 3332{
3333 struct drm_i915_private *dev_priv = dev->dev_private;
3334
3335 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 3336 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
d20d4f0c 3337
0961021a
BW		 3338 if (IS_BROADWELL(dev))
3339 gen8_disable_rps_interrupts(dev);
3340 else
3341 gen6_disable_rps_interrupts(dev);
44fc7d5c
DV		 3342}
3343
38807746
D		 3344static void cherryview_disable_rps(struct drm_device *dev)
3345{
3346 struct drm_i915_private *dev_priv = dev->dev_private;
3347
3348 I915_WRITE(GEN6_RC_CONTROL, 0);
3349}
3350
44fc7d5c
DV		 3351static void valleyview_disable_rps(struct drm_device *dev)
3352{
3353 struct drm_i915_private *dev_priv = dev->dev_private;
3354
3355 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 3356
44fc7d5c 3357 gen6_disable_rps_interrupts(dev);
d20d4f0c
JB		 3358}
3359
dc39fff7
BW		 3360static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3361{
91ca689a
ID		 3362 if (IS_VALLEYVIEW(dev)) {
3363 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
3364 mode = GEN6_RC_CTL_RC6_ENABLE;
3365 else
3366 mode = 0;
3367 }
dc39fff7 3368 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
1c79b42f
BW		 3369 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3370 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3371 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
dc39fff7
BW		 3372}
3373
e6069ca8 3374static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 3375{
eb4926e4
DL		 3376 /* No RC6 before Ironlake */
3377 if (INTEL_INFO(dev)->gen < 5)
3378 return 0;
3379
e6069ca8
ID		 3380 /* RC6 is only on Ironlake mobile not on desktop */
3381 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
3382 return 0;
3383
456470eb 3384 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 3385 if (enable_rc6 >= 0) {
3386 int mask;
3387
3388 if (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
3389 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
3390 INTEL_RC6pp_ENABLE;
3391 else
3392 mask = INTEL_RC6_ENABLE;
3393
3394 if ((enable_rc6 & mask) != enable_rc6)
3395 DRM_INFO("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
8fd9c1a9 3396 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 3397
3398 return enable_rc6 & mask;
3399 }
2b4e57bd 3400
6567d748
CW		 3401 /* Disable RC6 on Ironlake */
3402 if (INTEL_INFO(dev)->gen == 5)
3403 return 0;
2b4e57bd 3404
8bade1ad 3405 if (IS_IVYBRIDGE(dev))
cca84a1f 3406 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 3407
3408 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 3409}
3410
e6069ca8
ID		 3411int intel_enable_rc6(const struct drm_device *dev)
3412{
3413 return i915.enable_rc6;
3414}
3415
0961021a
BW		 3416static void gen8_enable_rps_interrupts(struct drm_device *dev)
3417{
3418 struct drm_i915_private *dev_priv = dev->dev_private;
3419
3420 spin_lock_irq(&dev_priv->irq_lock);
3421 WARN_ON(dev_priv->rps.pm_iir);
3422 bdw_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3423 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3424 spin_unlock_irq(&dev_priv->irq_lock);
3425}
3426
44fc7d5c
DV		 3427static void gen6_enable_rps_interrupts(struct drm_device *dev)
3428{
3429 struct drm_i915_private *dev_priv = dev->dev_private;
3430
3431 spin_lock_irq(&dev_priv->irq_lock);
a0b3335a 3432 WARN_ON(dev_priv->rps.pm_iir);
a6706b45
D		 3433 snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3434 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
44fc7d5c 3435 spin_unlock_irq(&dev_priv->irq_lock);
44fc7d5c
DV		 3436}
3437
3280e8b0
BW		 3438static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)
3439{
3440 /* All of these values are in units of 50MHz */
3441 dev_priv->rps.cur_freq = 0;
3442 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3443 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3444 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
3445 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
3446 /* XXX: only BYT has a special efficient freq */
3447 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
3448 /* hw_max = RP0 until we check for overclocking */
3449 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3450
3451 /* Preserve min/max settings in case of re-init */
3452 if (dev_priv->rps.max_freq_softlimit == 0)
3453 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3454
3455 if (dev_priv->rps.min_freq_softlimit == 0)
3456 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3457}
3458
6edee7f3
BW		 3459static void gen8_enable_rps(struct drm_device *dev)
3460{
3461 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 3462 struct intel_engine_cs *ring;
6edee7f3
BW		 3463 uint32_t rc6_mask = 0, rp_state_cap;
3464 int unused;
3465
3466 /* 1a: Software RC state - RC0 */
3467 I915_WRITE(GEN6_RC_STATE, 0);
3468
3469 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3470 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
c8d9a590 3471 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3472
3473 /* 2a: Disable RC states. */
3474 I915_WRITE(GEN6_RC_CONTROL, 0);
3475
3476 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3280e8b0 3477 parse_rp_state_cap(dev_priv, rp_state_cap);
6edee7f3
BW		 3478
3479 /* 2b: Program RC6 thresholds.*/
3480 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3481 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3482 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3483 for_each_ring(ring, dev_priv, unused)
3484 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3485 I915_WRITE(GEN6_RC_SLEEP, 0);
3486 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3487
3488 /* 3: Enable RC6 */
3489 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3490 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 3491 intel_print_rc6_info(dev, rc6_mask);
6edee7f3 3492 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
abbf9d2c
BW		 3493 GEN6_RC_CTL_EI_MODE(1) |
3494 rc6_mask);
6edee7f3
BW		 3495
3496 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 3497 I915_WRITE(GEN6_RPNSWREQ,
3498 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3499 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3500 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
6edee7f3
BW		 3501 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3502 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3503
3504 /* Docs recommend 900MHz, and 300 MHz respectively */
3505 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
b39fb297
BW		 3506 dev_priv->rps.max_freq_softlimit << 24 |
3507 dev_priv->rps.min_freq_softlimit << 16);
6edee7f3
BW		 3508
3509 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3510 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3511 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3512 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3513
3514 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3515
e4443e45
VS		 3516 /* WaDisablePwrmtrEvent:chv (pre-production hw) */
3517 I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
3518 I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
3519
6edee7f3
BW		 3520 /* 5: Enable RPS */
3521 I915_WRITE(GEN6_RP_CONTROL,
3522 GEN6_RP_MEDIA_TURBO |
3523 GEN6_RP_MEDIA_HW_NORMAL_MODE |
e4443e45 3524 GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
6edee7f3
BW		 3525 GEN6_RP_ENABLE |
3526 GEN6_RP_UP_BUSY_AVG |
3527 GEN6_RP_DOWN_IDLE_AVG);
3528
3529 /* 6: Ring frequency + overclocking (our driver does this later */
3530
3531 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3532
0961021a 3533 gen8_enable_rps_interrupts(dev);
6edee7f3 3534
c8d9a590 3535 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3536}
3537
79f5b2c7 3538static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 3539{
79f5b2c7 3540 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 3541 struct intel_engine_cs *ring;
2a5913a8 3542 u32 rp_state_cap;
7b9e0ae6 3543 u32 gt_perf_status;
d060c169 3544 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 3545 u32 gtfifodbg;
2b4e57bd 3546 int rc6_mode;
42c0526c 3547 int i, ret;
2b4e57bd 3548
4fc688ce 3549 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3550
2b4e57bd
ED		 3551 /* Here begins a magic sequence of register writes to enable
3552 * auto-downclocking.
3553 *
3554 * Perhaps there might be some value in exposing these to
3555 * userspace...
3556 */
3557 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 3558
3559 /* Clear the DBG now so we don't confuse earlier errors */
3560 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3561 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3562 I915_WRITE(GTFIFODBG, gtfifodbg);
3563 }
3564
c8d9a590 3565 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 3566
7b9e0ae6
CW		 3567 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3568 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3569
3280e8b0 3570 parse_rp_state_cap(dev_priv, rp_state_cap);
dd0a1aa1 3571
2b4e57bd
ED		 3572 /* disable the counters and set deterministic thresholds */
3573 I915_WRITE(GEN6_RC_CONTROL, 0);
3574
3575 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3576 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3577 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3578 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3579 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3580
b4519513
CW		 3581 for_each_ring(ring, dev_priv, i)
3582 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 3583
3584 I915_WRITE(GEN6_RC_SLEEP, 0);
3585 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 3586 if (IS_IVYBRIDGE(dev))
351aa566
SM		 3587 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3588 else
3589 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 3590 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 3591 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3592
5a7dc92a 3593 /* Check if we are enabling RC6 */
2b4e57bd
ED		 3594 rc6_mode = intel_enable_rc6(dev_priv->dev);
3595 if (rc6_mode & INTEL_RC6_ENABLE)
3596 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3597
5a7dc92a
ED		 3598 /* We don't use those on Haswell */
3599 if (!IS_HASWELL(dev)) {
3600 if (rc6_mode & INTEL_RC6p_ENABLE)
3601 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 3602
5a7dc92a
ED		 3603 if (rc6_mode & INTEL_RC6pp_ENABLE)
3604 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3605 }
2b4e57bd 3606
dc39fff7 3607 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 3608
3609 I915_WRITE(GEN6_RC_CONTROL,
3610 rc6_mask |
3611 GEN6_RC_CTL_EI_MODE(1) |
3612 GEN6_RC_CTL_HW_ENABLE);
3613
dd75fdc8
CW		 3614 /* Power down if completely idle for over 50ms */
3615 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 3616 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 3617
42c0526c 3618 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 3619 if (ret)
42c0526c 3620 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 3621
3622 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3623 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3624 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 3625 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 3626 (pcu_mbox & 0xff) * 50);
b39fb297 3627 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 3628 }
3629
dd75fdc8 3630 dev_priv->rps.power = HIGH_POWER; /* force a reset */
b39fb297 3631 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
2b4e57bd 3632
44fc7d5c 3633 gen6_enable_rps_interrupts(dev);
2b4e57bd 3634
31643d54
BW		 3635 rc6vids = 0;
3636 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3637 if (IS_GEN6(dev) && ret) {
3638 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3639 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3640 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3641 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3642 rc6vids &= 0xffff00;
3643 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3644 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3645 if (ret)
3646 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3647 }
3648
c8d9a590 3649 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 3650}
3651
c2bc2fc5 3652static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 3653{
79f5b2c7 3654 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 3655 int min_freq = 15;
3ebecd07
CW		 3656 unsigned int gpu_freq;
3657 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd 3658 int scaling_factor = 180;
eda79642 3659 struct cpufreq_policy *policy;
2b4e57bd 3660
4fc688ce 3661 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3662
eda79642
BW		 3663 policy = cpufreq_cpu_get(0);
3664 if (policy) {
3665 max_ia_freq = policy->cpuinfo.max_freq;
3666 cpufreq_cpu_put(policy);
3667 } else {
3668 /*
3669 * Default to measured freq if none found, PCU will ensure we
3670 * don't go over
3671 */
2b4e57bd 3672 max_ia_freq = tsc_khz;
eda79642 3673 }
2b4e57bd
ED		 3674
3675 /* Convert from kHz to MHz */
3676 max_ia_freq /= 1000;
3677
153b4b95 3678 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 3679 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3680 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 3681
2b4e57bd
ED		 3682 /*
3683 * For each potential GPU frequency, load a ring frequency we'd like
3684 * to use for memory access. We do this by specifying the IA frequency
3685 * the PCU should use as a reference to determine the ring frequency.
3686 */
b39fb297 3687 for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
2b4e57bd 3688 gpu_freq--) {
b39fb297 3689 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
3ebecd07
CW		 3690 unsigned int ia_freq = 0, ring_freq = 0;
3691
46c764d4
BW		 3692 if (INTEL_INFO(dev)->gen >= 8) {
3693 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3694 ring_freq = max(min_ring_freq, gpu_freq);
3695 } else if (IS_HASWELL(dev)) {
f6aca45c 3696 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 3697 ring_freq = max(min_ring_freq, ring_freq);
3698 /* leave ia_freq as the default, chosen by cpufreq */
3699 } else {
3700 /* On older processors, there is no separate ring
3701 * clock domain, so in order to boost the bandwidth
3702 * of the ring, we need to upclock the CPU (ia_freq).
3703 *
3704 * For GPU frequencies less than 750MHz,
3705 * just use the lowest ring freq.
3706 */
3707 if (gpu_freq < min_freq)
3708 ia_freq = 800;
3709 else
3710 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3711 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3712 }
2b4e57bd 3713
42c0526c
BW		 3714 sandybridge_pcode_write(dev_priv,
3715 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 3716 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3717 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3718 gpu_freq);
2b4e57bd 3719 }
2b4e57bd
ED		 3720}
3721
c2bc2fc5
ID		 3722void gen6_update_ring_freq(struct drm_device *dev)
3723{
3724 struct drm_i915_private *dev_priv = dev->dev_private;
3725
3726 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
3727 return;
3728
3729 mutex_lock(&dev_priv->rps.hw_lock);
3730 __gen6_update_ring_freq(dev);
3731 mutex_unlock(&dev_priv->rps.hw_lock);
3732}
3733
2b6b3a09
D		 3734int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
3735{
3736 u32 val, rp0;
3737
3738 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
3739 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
3740
3741 return rp0;
3742}
3743
3744static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3745{
3746 u32 val, rpe;
3747
3748 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
3749 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
3750
3751 return rpe;
3752}
3753
3754int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
3755{
3756 u32 val, rpn;
3757
3758 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
3759 rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK;
3760 return rpn;
3761}
3762
0a073b84
JB		 3763int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3764{
3765 u32 val, rp0;
3766
64936258 3767 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 3768
3769 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3770 /* Clamp to max */
3771 rp0 = min_t(u32, rp0, 0xea);
3772
3773 return rp0;
3774}
3775
3776static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3777{
3778 u32 val, rpe;
3779
64936258 3780 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 3781 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 3782 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 3783 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3784
3785 return rpe;
3786}
3787
3788int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3789{
64936258 3790 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 3791}
3792
ae48434c
ID		 3793/* Check that the pctx buffer wasn't move under us. */
3794static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
3795{
3796 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
3797
3798 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
3799 dev_priv->vlv_pctx->stolen->start);
3800}
3801
38807746
D		 3802
3803/* Check that the pcbr address is not empty. */
3804static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
3805{
3806 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
3807
3808 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
3809}
3810
3811static void cherryview_setup_pctx(struct drm_device *dev)
3812{
3813 struct drm_i915_private *dev_priv = dev->dev_private;
3814 unsigned long pctx_paddr, paddr;
3815 struct i915_gtt *gtt = &dev_priv->gtt;
3816 u32 pcbr;
3817 int pctx_size = 32*1024;
3818
3819 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3820
3821 pcbr = I915_READ(VLV_PCBR);
3822 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
3823 paddr = (dev_priv->mm.stolen_base +
3824 (gtt->stolen_size - pctx_size));
3825
3826 pctx_paddr = (paddr & (~4095));
3827 I915_WRITE(VLV_PCBR, pctx_paddr);
3828 }
3829}
3830
c9cddffc
JB		 3831static void valleyview_setup_pctx(struct drm_device *dev)
3832{
3833 struct drm_i915_private *dev_priv = dev->dev_private;
3834 struct drm_i915_gem_object *pctx;
3835 unsigned long pctx_paddr;
3836 u32 pcbr;
3837 int pctx_size = 24*1024;
3838
17b0c1f7
ID		 3839 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3840
c9cddffc
JB		 3841 pcbr = I915_READ(VLV_PCBR);
3842 if (pcbr) {
3843 /* BIOS set it up already, grab the pre-alloc'd space */
3844 int pcbr_offset;
3845
3846 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3847 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3848 pcbr_offset,
190d6cd5 3849 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 3850 pctx_size);
3851 goto out;
3852 }
3853
3854 /*
3855 * From the Gunit register HAS:
3856 * The Gfx driver is expected to program this register and ensure
3857 * proper allocation within Gfx stolen memory. For example, this
3858 * register should be programmed such than the PCBR range does not
3859 * overlap with other ranges, such as the frame buffer, protected
3860 * memory, or any other relevant ranges.
3861 */
3862 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3863 if (!pctx) {
3864 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3865 return;
3866 }
3867
3868 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3869 I915_WRITE(VLV_PCBR, pctx_paddr);
3870
3871out:
3872 dev_priv->vlv_pctx = pctx;
3873}
3874
ae48434c
ID		 3875static void valleyview_cleanup_pctx(struct drm_device *dev)
3876{
3877 struct drm_i915_private *dev_priv = dev->dev_private;
3878
3879 if (WARN_ON(!dev_priv->vlv_pctx))
3880 return;
3881
3882 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3883 dev_priv->vlv_pctx = NULL;
3884}
3885
4e80519e
ID		 3886static void valleyview_init_gt_powersave(struct drm_device *dev)
3887{
3888 struct drm_i915_private *dev_priv = dev->dev_private;
3889
3890 valleyview_setup_pctx(dev);
3891
3892 mutex_lock(&dev_priv->rps.hw_lock);
3893
3894 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
3895 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
3896 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3897 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
3898 dev_priv->rps.max_freq);
3899
3900 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
3901 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3902 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3903 dev_priv->rps.efficient_freq);
3904
3905 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
3906 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3907 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
3908 dev_priv->rps.min_freq);
3909
3910 /* Preserve min/max settings in case of re-init */
3911 if (dev_priv->rps.max_freq_softlimit == 0)
3912 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3913
3914 if (dev_priv->rps.min_freq_softlimit == 0)
3915 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3916
3917 mutex_unlock(&dev_priv->rps.hw_lock);
3918}
3919
38807746
D		 3920static void cherryview_init_gt_powersave(struct drm_device *dev)
3921{
2b6b3a09
D		 3922 struct drm_i915_private *dev_priv = dev->dev_private;
3923
38807746 3924 cherryview_setup_pctx(dev);
2b6b3a09
D		 3925
3926 mutex_lock(&dev_priv->rps.hw_lock);
3927
3928 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
3929 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
3930 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3931 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
3932 dev_priv->rps.max_freq);
3933
3934 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
3935 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3936 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3937 dev_priv->rps.efficient_freq);
3938
3939 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
3940 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3941 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
3942 dev_priv->rps.min_freq);
3943
3944 /* Preserve min/max settings in case of re-init */
3945 if (dev_priv->rps.max_freq_softlimit == 0)
3946 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3947
3948 if (dev_priv->rps.min_freq_softlimit == 0)
3949 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3950
3951 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 3952}
3953
4e80519e
ID		 3954static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
3955{
3956 valleyview_cleanup_pctx(dev);
3957}
3958
38807746
D		 3959static void cherryview_enable_rps(struct drm_device *dev)
3960{
3961 struct drm_i915_private *dev_priv = dev->dev_private;
3962 struct intel_engine_cs *ring;
2b6b3a09 3963 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 3964 int i;
3965
3966 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3967
3968 gtfifodbg = I915_READ(GTFIFODBG);
3969 if (gtfifodbg) {
3970 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
3971 gtfifodbg);
3972 I915_WRITE(GTFIFODBG, gtfifodbg);
3973 }
3974
3975 cherryview_check_pctx(dev_priv);
3976
3977 /* 1a & 1b: Get forcewake during program sequence. Although the driver
3978 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3979 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3980
3981 /* 2a: Program RC6 thresholds.*/
3982 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3983 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3984 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3985
3986 for_each_ring(ring, dev_priv, i)
3987 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3988 I915_WRITE(GEN6_RC_SLEEP, 0);
3989
3990 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3991
3992 /* allows RC6 residency counter to work */
3993 I915_WRITE(VLV_COUNTER_CONTROL,
3994 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
3995 VLV_MEDIA_RC6_COUNT_EN |
3996 VLV_RENDER_RC6_COUNT_EN));
3997
3998 /* For now we assume BIOS is allocating and populating the PCBR */
3999 pcbr = I915_READ(VLV_PCBR);
4000
4001 DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr);
4002
4003 /* 3: Enable RC6 */
4004 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
4005 (pcbr >> VLV_PCBR_ADDR_SHIFT))
4006 rc6_mode = GEN6_RC_CTL_EI_MODE(1);
4007
4008 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4009
2b6b3a09
D		 4010 /* 4 Program defaults and thresholds for RPS*/
4011 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4012 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4013 I915_WRITE(GEN6_RP_UP_EI, 66000);
4014 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4015
4016 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4017
4018 /* 5: Enable RPS */
4019 I915_WRITE(GEN6_RP_CONTROL,
4020 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4021 GEN6_RP_MEDIA_IS_GFX |
4022 GEN6_RP_ENABLE |
4023 GEN6_RP_UP_BUSY_AVG |
4024 GEN6_RP_DOWN_IDLE_AVG);
4025
4026 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4027
4028 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4029 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4030
4031 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4032 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4033 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4034 dev_priv->rps.cur_freq);
4035
4036 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4037 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4038 dev_priv->rps.efficient_freq);
4039
4040 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4041
38807746
D		 4042 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4043}
4044
0a073b84
JB		 4045static void valleyview_enable_rps(struct drm_device *dev)
4046{
4047 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4048 struct intel_engine_cs *ring;
2a5913a8 4049 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 4050 int i;
4051
4052 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4053
ae48434c
ID		 4054 valleyview_check_pctx(dev_priv);
4055
0a073b84 4056 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 4057 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4058 gtfifodbg);
0a073b84
JB		 4059 I915_WRITE(GTFIFODBG, gtfifodbg);
4060 }
4061
c8d9a590
D		 4062 /* If VLV, Forcewake all wells, else re-direct to regular path */
4063 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 4064
4065 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4066 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4067 I915_WRITE(GEN6_RP_UP_EI, 66000);
4068 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4069
4070 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4071
4072 I915_WRITE(GEN6_RP_CONTROL,
4073 GEN6_RP_MEDIA_TURBO |
4074 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4075 GEN6_RP_MEDIA_IS_GFX |
4076 GEN6_RP_ENABLE |
4077 GEN6_RP_UP_BUSY_AVG |
4078 GEN6_RP_DOWN_IDLE_CONT);
4079
4080 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4081 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4082 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4083
4084 for_each_ring(ring, dev_priv, i)
4085 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4086
2f0aa304 4087 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 4088
4089 /* allows RC6 residency counter to work */
49798eb2
JB		 4090 I915_WRITE(VLV_COUNTER_CONTROL,
4091 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4092 VLV_MEDIA_RC6_COUNT_EN |
4093 VLV_RENDER_RC6_COUNT_EN));
a2b23fe0 4094 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 4095 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 4096
4097 intel_print_rc6_info(dev, rc6_mode);
4098
a2b23fe0 4099 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 4100
64936258 4101 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 4102
4103 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4104 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4105
b39fb297 4106 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 4107 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
b39fb297
BW		 4108 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4109 dev_priv->rps.cur_freq);
0a073b84 4110
73008b98 4111 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
b39fb297
BW		 4112 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4113 dev_priv->rps.efficient_freq);
0a073b84 4114
b39fb297 4115 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 4116
44fc7d5c 4117 gen6_enable_rps_interrupts(dev);
0a073b84 4118
c8d9a590 4119 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 4120}
4121
930ebb46 4122void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 4123{
4124 struct drm_i915_private *dev_priv = dev->dev_private;
4125
3e373948 4126 if (dev_priv->ips.renderctx) {
d7f46fc4 4127 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
3e373948
DV		 4128 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4129 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 4130 }
4131
3e373948 4132 if (dev_priv->ips.pwrctx) {
d7f46fc4 4133 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
3e373948
DV		 4134 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4135 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 4136 }
4137}
4138
930ebb46 4139static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 4140{
4141 struct drm_i915_private *dev_priv = dev->dev_private;
4142
4143 if (I915_READ(PWRCTXA)) {
4144 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4145 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4146 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4147 50);
4148
4149 I915_WRITE(PWRCTXA, 0);
4150 POSTING_READ(PWRCTXA);
4151
4152 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4153 POSTING_READ(RSTDBYCTL);
4154 }
2b4e57bd
ED		 4155}
4156
4157static int ironlake_setup_rc6(struct drm_device *dev)
4158{
4159 struct drm_i915_private *dev_priv = dev->dev_private;
4160
3e373948
DV		 4161 if (dev_priv->ips.renderctx == NULL)
4162 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4163 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 4164 return -ENOMEM;
4165
3e373948
DV		 4166 if (dev_priv->ips.pwrctx == NULL)
4167 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4168 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 4169 ironlake_teardown_rc6(dev);
4170 return -ENOMEM;
4171 }
4172
4173 return 0;
4174}
4175
930ebb46 4176static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 4177{
4178 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4179 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3e960501 4180 bool was_interruptible;
2b4e57bd
ED		 4181 int ret;
4182
4183 /* rc6 disabled by default due to repeated reports of hanging during
4184 * boot and resume.
4185 */
4186 if (!intel_enable_rc6(dev))
4187 return;
4188
79f5b2c7
DV		 4189 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4190
2b4e57bd 4191 ret = ironlake_setup_rc6(dev);
79f5b2c7 4192 if (ret)
2b4e57bd 4193 return;
2b4e57bd 4194
3e960501
CW		 4195 was_interruptible = dev_priv->mm.interruptible;
4196 dev_priv->mm.interruptible = false;
4197
2b4e57bd
ED		 4198 /*
4199 * GPU can automatically power down the render unit if given a page
4200 * to save state.
4201 */
6d90c952 4202 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 4203 if (ret) {
4204 ironlake_teardown_rc6(dev);
3e960501 4205 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 4206 return;
4207 }
4208
6d90c952
DV		 4209 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4210 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 4211 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
6d90c952
DV		 4212 MI_MM_SPACE_GTT |
4213 MI_SAVE_EXT_STATE_EN |
4214 MI_RESTORE_EXT_STATE_EN |
4215 MI_RESTORE_INHIBIT);
4216 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4217 intel_ring_emit(ring, MI_NOOP);
4218 intel_ring_emit(ring, MI_FLUSH);
4219 intel_ring_advance(ring);
2b4e57bd
ED		 4220
4221 /*
4222 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4223 * does an implicit flush, combined with MI_FLUSH above, it should be
4224 * safe to assume that renderctx is valid
4225 */
3e960501
CW		 4226 ret = intel_ring_idle(ring);
4227 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 4228 if (ret) {
def27a58 4229 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 4230 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 4231 return;
4232 }
4233
f343c5f6 4234 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
2b4e57bd 4235 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
dc39fff7 4236
91ca689a 4237 intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
2b4e57bd
ED		 4238}
4239
dde18883
ED		 4240static unsigned long intel_pxfreq(u32 vidfreq)
4241{
4242 unsigned long freq;
4243 int div = (vidfreq & 0x3f0000) >> 16;
4244 int post = (vidfreq & 0x3000) >> 12;
4245 int pre = (vidfreq & 0x7);
4246
4247 if (!pre)
4248 return 0;
4249
4250 freq = ((div * 133333) / ((1<<post) * pre));
4251
4252 return freq;
4253}
4254
eb48eb00
DV		 4255static const struct cparams {
4256 u16 i;
4257 u16 t;
4258 u16 m;
4259 u16 c;
4260} cparams[] = {
4261 { 1, 1333, 301, 28664 },
4262 { 1, 1066, 294, 24460 },
4263 { 1, 800, 294, 25192 },
4264 { 0, 1333, 276, 27605 },
4265 { 0, 1066, 276, 27605 },
4266 { 0, 800, 231, 23784 },
4267};
4268
f531dcb2 4269static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4270{
4271 u64 total_count, diff, ret;
4272 u32 count1, count2, count3, m = 0, c = 0;
4273 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4274 int i;
4275
02d71956
DV		 4276 assert_spin_locked(&mchdev_lock);
4277
20e4d407 4278 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 4279
4280 /* Prevent division-by-zero if we are asking too fast.
4281 * Also, we don't get interesting results if we are polling
4282 * faster than once in 10ms, so just return the saved value
4283 * in such cases.
4284 */
4285 if (diff1 <= 10)
20e4d407 4286 return dev_priv->ips.chipset_power;
eb48eb00
DV		 4287
4288 count1 = I915_READ(DMIEC);
4289 count2 = I915_READ(DDREC);
4290 count3 = I915_READ(CSIEC);
4291
4292 total_count = count1 + count2 + count3;
4293
4294 /* FIXME: handle per-counter overflow */
20e4d407
DV		 4295 if (total_count < dev_priv->ips.last_count1) {
4296 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 4297 diff += total_count;
4298 } else {
20e4d407 4299 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 4300 }
4301
4302 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 4303 if (cparams[i].i == dev_priv->ips.c_m &&
4304 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 4305 m = cparams[i].m;
4306 c = cparams[i].c;
4307 break;
4308 }
4309 }
4310
4311 diff = div_u64(diff, diff1);
4312 ret = ((m * diff) + c);
4313 ret = div_u64(ret, 10);
4314
20e4d407
DV		 4315 dev_priv->ips.last_count1 = total_count;
4316 dev_priv->ips.last_time1 = now;
eb48eb00 4317
20e4d407 4318 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 4319
4320 return ret;
4321}
4322
f531dcb2
CW		 4323unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4324{
3d13ef2e 4325 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 4326 unsigned long val;
4327
3d13ef2e 4328 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 4329 return 0;
4330
4331 spin_lock_irq(&mchdev_lock);
4332
4333 val = __i915_chipset_val(dev_priv);
4334
4335 spin_unlock_irq(&mchdev_lock);
4336
4337 return val;
4338}
4339
eb48eb00
DV		 4340unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4341{
4342 unsigned long m, x, b;
4343 u32 tsfs;
4344
4345 tsfs = I915_READ(TSFS);
4346
4347 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4348 x = I915_READ8(TR1);
4349
4350 b = tsfs & TSFS_INTR_MASK;
4351
4352 return ((m * x) / 127) - b;
4353}
4354
4355static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4356{
3d13ef2e 4357 struct drm_device *dev = dev_priv->dev;
eb48eb00
DV		 4358 static const struct v_table {
4359 u16 vd; /* in .1 mil */
4360 u16 vm; /* in .1 mil */
4361 } v_table[] = {
4362 { 0, 0, },
4363 { 375, 0, },
4364 { 500, 0, },
4365 { 625, 0, },
4366 { 750, 0, },
4367 { 875, 0, },
4368 { 1000, 0, },
4369 { 1125, 0, },
4370 { 4125, 3000, },
4371 { 4125, 3000, },
4372 { 4125, 3000, },
4373 { 4125, 3000, },
4374 { 4125, 3000, },
4375 { 4125, 3000, },
4376 { 4125, 3000, },
4377 { 4125, 3000, },
4378 { 4125, 3000, },
4379 { 4125, 3000, },
4380 { 4125, 3000, },
4381 { 4125, 3000, },
4382 { 4125, 3000, },
4383 { 4125, 3000, },
4384 { 4125, 3000, },
4385 { 4125, 3000, },
4386 { 4125, 3000, },
4387 { 4125, 3000, },
4388 { 4125, 3000, },
4389 { 4125, 3000, },
4390 { 4125, 3000, },
4391 { 4125, 3000, },
4392 { 4125, 3000, },
4393 { 4125, 3000, },
4394 { 4250, 3125, },
4395 { 4375, 3250, },
4396 { 4500, 3375, },
4397 { 4625, 3500, },
4398 { 4750, 3625, },
4399 { 4875, 3750, },
4400 { 5000, 3875, },
4401 { 5125, 4000, },
4402 { 5250, 4125, },
4403 { 5375, 4250, },
4404 { 5500, 4375, },
4405 { 5625, 4500, },
4406 { 5750, 4625, },
4407 { 5875, 4750, },
4408 { 6000, 4875, },
4409 { 6125, 5000, },
4410 { 6250, 5125, },
4411 { 6375, 5250, },
4412 { 6500, 5375, },
4413 { 6625, 5500, },
4414 { 6750, 5625, },
4415 { 6875, 5750, },
4416 { 7000, 5875, },
4417 { 7125, 6000, },
4418 { 7250, 6125, },
4419 { 7375, 6250, },
4420 { 7500, 6375, },
4421 { 7625, 6500, },
4422 { 7750, 6625, },
4423 { 7875, 6750, },
4424 { 8000, 6875, },
4425 { 8125, 7000, },
4426 { 8250, 7125, },
4427 { 8375, 7250, },
4428 { 8500, 7375, },
4429 { 8625, 7500, },
4430 { 8750, 7625, },
4431 { 8875, 7750, },
4432 { 9000, 7875, },
4433 { 9125, 8000, },
4434 { 9250, 8125, },
4435 { 9375, 8250, },
4436 { 9500, 8375, },
4437 { 9625, 8500, },
4438 { 9750, 8625, },
4439 { 9875, 8750, },
4440 { 10000, 8875, },
4441 { 10125, 9000, },
4442 { 10250, 9125, },
4443 { 10375, 9250, },
4444 { 10500, 9375, },
4445 { 10625, 9500, },
4446 { 10750, 9625, },
4447 { 10875, 9750, },
4448 { 11000, 9875, },
4449 { 11125, 10000, },
4450 { 11250, 10125, },
4451 { 11375, 10250, },
4452 { 11500, 10375, },
4453 { 11625, 10500, },
4454 { 11750, 10625, },
4455 { 11875, 10750, },
4456 { 12000, 10875, },
4457 { 12125, 11000, },
4458 { 12250, 11125, },
4459 { 12375, 11250, },
4460 { 12500, 11375, },
4461 { 12625, 11500, },
4462 { 12750, 11625, },
4463 { 12875, 11750, },
4464 { 13000, 11875, },
4465 { 13125, 12000, },
4466 { 13250, 12125, },
4467 { 13375, 12250, },
4468 { 13500, 12375, },
4469 { 13625, 12500, },
4470 { 13750, 12625, },
4471 { 13875, 12750, },
4472 { 14000, 12875, },
4473 { 14125, 13000, },
4474 { 14250, 13125, },
4475 { 14375, 13250, },
4476 { 14500, 13375, },
4477 { 14625, 13500, },
4478 { 14750, 13625, },
4479 { 14875, 13750, },
4480 { 15000, 13875, },
4481 { 15125, 14000, },
4482 { 15250, 14125, },
4483 { 15375, 14250, },
4484 { 15500, 14375, },
4485 { 15625, 14500, },
4486 { 15750, 14625, },
4487 { 15875, 14750, },
4488 { 16000, 14875, },
4489 { 16125, 15000, },
4490 };
3d13ef2e 4491 if (INTEL_INFO(dev)->is_mobile)
eb48eb00
DV		 4492 return v_table[pxvid].vm;
4493 else
4494 return v_table[pxvid].vd;
4495}
4496
02d71956 4497static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4498{
4499 struct timespec now, diff1;
4500 u64 diff;
4501 unsigned long diffms;
4502 u32 count;
4503
02d71956 4504 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 4505
4506 getrawmonotonic(&now);
20e4d407 4507 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 4508
4509 /* Don't divide by 0 */
4510 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4511 if (!diffms)
4512 return;
4513
4514 count = I915_READ(GFXEC);
4515
20e4d407
DV		 4516 if (count < dev_priv->ips.last_count2) {
4517 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 4518 diff += count;
4519 } else {
20e4d407 4520 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 4521 }
4522
20e4d407
DV		 4523 dev_priv->ips.last_count2 = count;
4524 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 4525
4526 /* More magic constants... */
4527 diff = diff * 1181;
4528 diff = div_u64(diff, diffms * 10);
20e4d407 4529 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 4530}
4531
02d71956
DV		 4532void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4533{
3d13ef2e
DL		 4534 struct drm_device *dev = dev_priv->dev;
4535
4536 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 4537 return;
4538
9270388e 4539 spin_lock_irq(&mchdev_lock);
02d71956
DV		 4540
4541 __i915_update_gfx_val(dev_priv);
4542
9270388e 4543 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 4544}
4545
f531dcb2 4546static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4547{
4548 unsigned long t, corr, state1, corr2, state2;
4549 u32 pxvid, ext_v;
4550
02d71956
DV		 4551 assert_spin_locked(&mchdev_lock);
4552
b39fb297 4553 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
eb48eb00
DV		 4554 pxvid = (pxvid >> 24) & 0x7f;
4555 ext_v = pvid_to_extvid(dev_priv, pxvid);
4556
4557 state1 = ext_v;
4558
4559 t = i915_mch_val(dev_priv);
4560
4561 /* Revel in the empirically derived constants */
4562
4563 /* Correction factor in 1/100000 units */
4564 if (t > 80)
4565 corr = ((t * 2349) + 135940);
4566 else if (t >= 50)
4567 corr = ((t * 964) + 29317);
4568 else /* < 50 */
4569 corr = ((t * 301) + 1004);
4570
4571 corr = corr * ((150142 * state1) / 10000 - 78642);
4572 corr /= 100000;
20e4d407 4573 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 4574
4575 state2 = (corr2 * state1) / 10000;
4576 state2 /= 100; /* convert to mW */
4577
02d71956 4578 __i915_update_gfx_val(dev_priv);
eb48eb00 4579
20e4d407 4580 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 4581}
4582
f531dcb2
CW		 4583unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4584{
3d13ef2e 4585 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 4586 unsigned long val;
4587
3d13ef2e 4588 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 4589 return 0;
4590
4591 spin_lock_irq(&mchdev_lock);
4592
4593 val = __i915_gfx_val(dev_priv);
4594
4595 spin_unlock_irq(&mchdev_lock);
4596
4597 return val;
4598}
4599
eb48eb00
DV		 4600/**
4601 * i915_read_mch_val - return value for IPS use
4602 *
4603 * Calculate and return a value for the IPS driver to use when deciding whether
4604 * we have thermal and power headroom to increase CPU or GPU power budget.
4605 */
4606unsigned long i915_read_mch_val(void)
4607{
4608 struct drm_i915_private *dev_priv;
4609 unsigned long chipset_val, graphics_val, ret = 0;
4610
9270388e 4611 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4612 if (!i915_mch_dev)
4613 goto out_unlock;
4614 dev_priv = i915_mch_dev;
4615
f531dcb2
CW		 4616 chipset_val = __i915_chipset_val(dev_priv);
4617 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 4618
4619 ret = chipset_val + graphics_val;
4620
4621out_unlock:
9270388e 4622 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4623
4624 return ret;
4625}
4626EXPORT_SYMBOL_GPL(i915_read_mch_val);
4627
4628/**
4629 * i915_gpu_raise - raise GPU frequency limit
4630 *
4631 * Raise the limit; IPS indicates we have thermal headroom.
4632 */
4633bool i915_gpu_raise(void)
4634{
4635 struct drm_i915_private *dev_priv;
4636 bool ret = true;
4637
9270388e 4638 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4639 if (!i915_mch_dev) {
4640 ret = false;
4641 goto out_unlock;
4642 }
4643 dev_priv = i915_mch_dev;
4644
20e4d407
DV		 4645 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4646 dev_priv->ips.max_delay--;
eb48eb00
DV		 4647
4648out_unlock:
9270388e 4649 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4650
4651 return ret;
4652}
4653EXPORT_SYMBOL_GPL(i915_gpu_raise);
4654
4655/**
4656 * i915_gpu_lower - lower GPU frequency limit
4657 *
4658 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4659 * frequency maximum.
4660 */
4661bool i915_gpu_lower(void)
4662{
4663 struct drm_i915_private *dev_priv;
4664 bool ret = true;
4665
9270388e 4666 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4667 if (!i915_mch_dev) {
4668 ret = false;
4669 goto out_unlock;
4670 }
4671 dev_priv = i915_mch_dev;
4672
20e4d407
DV		 4673 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4674 dev_priv->ips.max_delay++;
eb48eb00
DV		 4675
4676out_unlock:
9270388e 4677 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4678
4679 return ret;
4680}
4681EXPORT_SYMBOL_GPL(i915_gpu_lower);
4682
4683/**
4684 * i915_gpu_busy - indicate GPU business to IPS
4685 *
4686 * Tell the IPS driver whether or not the GPU is busy.
4687 */
4688bool i915_gpu_busy(void)
4689{
4690 struct drm_i915_private *dev_priv;
a4872ba6 4691 struct intel_engine_cs *ring;
eb48eb00 4692 bool ret = false;
f047e395 4693 int i;
eb48eb00 4694
9270388e 4695 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4696 if (!i915_mch_dev)
4697 goto out_unlock;
4698 dev_priv = i915_mch_dev;
4699
f047e395
CW		 4700 for_each_ring(ring, dev_priv, i)
4701 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 4702
4703out_unlock:
9270388e 4704 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4705
4706 return ret;
4707}
4708EXPORT_SYMBOL_GPL(i915_gpu_busy);
4709
4710/**
4711 * i915_gpu_turbo_disable - disable graphics turbo
4712 *
4713 * Disable graphics turbo by resetting the max frequency and setting the
4714 * current frequency to the default.
4715 */
4716bool i915_gpu_turbo_disable(void)
4717{
4718 struct drm_i915_private *dev_priv;
4719 bool ret = true;
4720
9270388e 4721 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4722 if (!i915_mch_dev) {
4723 ret = false;
4724 goto out_unlock;
4725 }
4726 dev_priv = i915_mch_dev;
4727
20e4d407 4728 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 4729
20e4d407 4730 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 4731 ret = false;
4732
4733out_unlock:
9270388e 4734 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4735
4736 return ret;
4737}
4738EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4739
4740/**
4741 * Tells the intel_ips driver that the i915 driver is now loaded, if
4742 * IPS got loaded first.
4743 *
4744 * This awkward dance is so that neither module has to depend on the
4745 * other in order for IPS to do the appropriate communication of
4746 * GPU turbo limits to i915.
4747 */
4748static void
4749ips_ping_for_i915_load(void)
4750{
4751 void (*link)(void);
4752
4753 link = symbol_get(ips_link_to_i915_driver);
4754 if (link) {
4755 link();
4756 symbol_put(ips_link_to_i915_driver);
4757 }
4758}
4759
4760void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4761{
02d71956
DV		 4762 /* We only register the i915 ips part with intel-ips once everything is
4763 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 4764 spin_lock_irq(&mchdev_lock);
eb48eb00 4765 i915_mch_dev = dev_priv;
9270388e 4766 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4767
4768 ips_ping_for_i915_load();
4769}
4770
4771void intel_gpu_ips_teardown(void)
4772{
9270388e 4773 spin_lock_irq(&mchdev_lock);
eb48eb00 4774 i915_mch_dev = NULL;
9270388e 4775 spin_unlock_irq(&mchdev_lock);
eb48eb00 4776}
76c3552f 4777
8090c6b9 4778static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 4779{
4780 struct drm_i915_private *dev_priv = dev->dev_private;
4781 u32 lcfuse;
4782 u8 pxw[16];
4783 int i;
4784
4785 /* Disable to program */
4786 I915_WRITE(ECR, 0);
4787 POSTING_READ(ECR);
4788
4789 /* Program energy weights for various events */
4790 I915_WRITE(SDEW, 0x15040d00);
4791 I915_WRITE(CSIEW0, 0x007f0000);
4792 I915_WRITE(CSIEW1, 0x1e220004);
4793 I915_WRITE(CSIEW2, 0x04000004);
4794
4795 for (i = 0; i < 5; i++)
4796 I915_WRITE(PEW + (i * 4), 0);
4797 for (i = 0; i < 3; i++)
4798 I915_WRITE(DEW + (i * 4), 0);
4799
4800 /* Program P-state weights to account for frequency power adjustment */
4801 for (i = 0; i < 16; i++) {
4802 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4803 unsigned long freq = intel_pxfreq(pxvidfreq);
4804 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4805 PXVFREQ_PX_SHIFT;
4806 unsigned long val;
4807
4808 val = vid * vid;
4809 val *= (freq / 1000);
4810 val *= 255;
4811 val /= (127*127*900);
4812 if (val > 0xff)
4813 DRM_ERROR("bad pxval: %ld\n", val);
4814 pxw[i] = val;
4815 }
4816 /* Render standby states get 0 weight */
4817 pxw[14] = 0;
4818 pxw[15] = 0;
4819
4820 for (i = 0; i < 4; i++) {
4821 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4822 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4823 I915_WRITE(PXW + (i * 4), val);
4824 }
4825
4826 /* Adjust magic regs to magic values (more experimental results) */
4827 I915_WRITE(OGW0, 0);
4828 I915_WRITE(OGW1, 0);
4829 I915_WRITE(EG0, 0x00007f00);
4830 I915_WRITE(EG1, 0x0000000e);
4831 I915_WRITE(EG2, 0x000e0000);
4832 I915_WRITE(EG3, 0x68000300);
4833 I915_WRITE(EG4, 0x42000000);
4834 I915_WRITE(EG5, 0x00140031);
4835 I915_WRITE(EG6, 0);
4836 I915_WRITE(EG7, 0);
4837
4838 for (i = 0; i < 8; i++)
4839 I915_WRITE(PXWL + (i * 4), 0);
4840
4841 /* Enable PMON + select events */
4842 I915_WRITE(ECR, 0x80000019);
4843
4844 lcfuse = I915_READ(LCFUSE02);
4845
20e4d407 4846 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 4847}
4848
ae48434c
ID		 4849void intel_init_gt_powersave(struct drm_device *dev)
4850{
e6069ca8
ID		 4851 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
4852
38807746
D		 4853 if (IS_CHERRYVIEW(dev))
4854 cherryview_init_gt_powersave(dev);
4855 else if (IS_VALLEYVIEW(dev))
4e80519e 4856 valleyview_init_gt_powersave(dev);
ae48434c
ID		 4857}
4858
4859void intel_cleanup_gt_powersave(struct drm_device *dev)
4860{
38807746
D		 4861 if (IS_CHERRYVIEW(dev))
4862 return;
4863 else if (IS_VALLEYVIEW(dev))
4e80519e 4864 valleyview_cleanup_gt_powersave(dev);
ae48434c
ID		 4865}
4866
8090c6b9
DV		 4867void intel_disable_gt_powersave(struct drm_device *dev)
4868{
1a01ab3b
JB		 4869 struct drm_i915_private *dev_priv = dev->dev_private;
4870
fd0c0642
DV		 4871 /* Interrupts should be disabled already to avoid re-arming. */
4872 WARN_ON(dev->irq_enabled);
4873
930ebb46 4874 if (IS_IRONLAKE_M(dev)) {
8090c6b9 4875 ironlake_disable_drps(dev);
930ebb46 4876 ironlake_disable_rc6(dev);
38807746 4877 } else if (INTEL_INFO(dev)->gen >= 6) {
e494837a
ID		 4878 if (cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work))
4879 intel_runtime_pm_put(dev_priv);
4880
250848ca 4881 cancel_work_sync(&dev_priv->rps.work);
4fc688ce 4882 mutex_lock(&dev_priv->rps.hw_lock);
38807746
D		 4883 if (IS_CHERRYVIEW(dev))
4884 cherryview_disable_rps(dev);
4885 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 4886 valleyview_disable_rps(dev);
4887 else
4888 gen6_disable_rps(dev);
c0951f0c 4889 dev_priv->rps.enabled = false;
4fc688ce 4890 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 4891 }
8090c6b9
DV		 4892}
4893
1a01ab3b
JB		 4894static void intel_gen6_powersave_work(struct work_struct *work)
4895{
4896 struct drm_i915_private *dev_priv =
4897 container_of(work, struct drm_i915_private,
4898 rps.delayed_resume_work.work);
4899 struct drm_device *dev = dev_priv->dev;
4900
4fc688ce 4901 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 4902
38807746
D		 4903 if (IS_CHERRYVIEW(dev)) {
4904 cherryview_enable_rps(dev);
4905 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 4906 valleyview_enable_rps(dev);
6edee7f3
BW		 4907 } else if (IS_BROADWELL(dev)) {
4908 gen8_enable_rps(dev);
c2bc2fc5 4909 __gen6_update_ring_freq(dev);
0a073b84
JB		 4910 } else {
4911 gen6_enable_rps(dev);
c2bc2fc5 4912 __gen6_update_ring_freq(dev);
0a073b84 4913 }
c0951f0c 4914 dev_priv->rps.enabled = true;
4fc688ce 4915 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 4916
4917 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 4918}
4919
8090c6b9
DV		 4920void intel_enable_gt_powersave(struct drm_device *dev)
4921{
1a01ab3b
JB		 4922 struct drm_i915_private *dev_priv = dev->dev_private;
4923
8090c6b9 4924 if (IS_IRONLAKE_M(dev)) {
dc1d0136 4925 mutex_lock(&dev->struct_mutex);
8090c6b9
DV		 4926 ironlake_enable_drps(dev);
4927 ironlake_enable_rc6(dev);
4928 intel_init_emon(dev);
dc1d0136 4929 mutex_unlock(&dev->struct_mutex);
38807746 4930 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 4931 /*
4932 * PCU communication is slow and this doesn't need to be
4933 * done at any specific time, so do this out of our fast path
4934 * to make resume and init faster.
c6df39b5
ID		 4935 *
4936 * We depend on the HW RC6 power context save/restore
4937 * mechanism when entering D3 through runtime PM suspend. So
4938 * disable RPM until RPS/RC6 is properly setup. We can only
4939 * get here via the driver load/system resume/runtime resume
4940 * paths, so the _noresume version is enough (and in case of
4941 * runtime resume it's necessary).
1a01ab3b 4942 */
c6df39b5
ID		 4943 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4944 round_jiffies_up_relative(HZ)))
4945 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 4946 }
4947}
4948
c6df39b5
ID		 4949void intel_reset_gt_powersave(struct drm_device *dev)
4950{
4951 struct drm_i915_private *dev_priv = dev->dev_private;
4952
4953 dev_priv->rps.enabled = false;
4954 intel_enable_gt_powersave(dev);
4955}
4956
3107bd48
DV		 4957static void ibx_init_clock_gating(struct drm_device *dev)
4958{
4959 struct drm_i915_private *dev_priv = dev->dev_private;
4960
4961 /*
4962 * On Ibex Peak and Cougar Point, we need to disable clock
4963 * gating for the panel power sequencer or it will fail to
4964 * start up when no ports are active.
4965 */
4966 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4967}
4968
0e088b8f
VS		 4969static void g4x_disable_trickle_feed(struct drm_device *dev)
4970{
4971 struct drm_i915_private *dev_priv = dev->dev_private;
4972 int pipe;
4973
4974 for_each_pipe(pipe) {
4975 I915_WRITE(DSPCNTR(pipe),
4976 I915_READ(DSPCNTR(pipe)) |
4977 DISPPLANE_TRICKLE_FEED_DISABLE);
1dba99f4 4978 intel_flush_primary_plane(dev_priv, pipe);
0e088b8f
VS		 4979 }
4980}
4981
017636cc
VS		 4982static void ilk_init_lp_watermarks(struct drm_device *dev)
4983{
4984 struct drm_i915_private *dev_priv = dev->dev_private;
4985
4986 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
4987 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
4988 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
4989
4990 /*
4991 * Don't touch WM1S_LP_EN here.
4992 * Doing so could cause underruns.
4993 */
4994}
4995
1fa61106 4996static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4997{
4998 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4999 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5000
f1e8fa56
DL		 5001 /*
5002 * Required for FBC
5003 * WaFbcDisableDpfcClockGating:ilk
5004 */
4d47e4f5
DL		 5005 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5006 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5007 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5008
5009 I915_WRITE(PCH_3DCGDIS0,
5010 MARIUNIT_CLOCK_GATE_DISABLE |
5011 SVSMUNIT_CLOCK_GATE_DISABLE);
5012 I915_WRITE(PCH_3DCGDIS1,
5013 VFMUNIT_CLOCK_GATE_DISABLE);
5014
6f1d69b0
ED		 5015 /*
5016 * According to the spec the following bits should be set in
5017 * order to enable memory self-refresh
5018 * The bit 22/21 of 0x42004
5019 * The bit 5 of 0x42020
5020 * The bit 15 of 0x45000
5021 */
5022 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5023 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5024 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 5025 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5026 I915_WRITE(DISP_ARB_CTL,
5027 (I915_READ(DISP_ARB_CTL) |
5028 DISP_FBC_WM_DIS));
017636cc
VS		 5029
5030 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 5031
5032 /*
5033 * Based on the document from hardware guys the following bits
5034 * should be set unconditionally in order to enable FBC.
5035 * The bit 22 of 0x42000
5036 * The bit 22 of 0x42004
5037 * The bit 7,8,9 of 0x42020.
5038 */
5039 if (IS_IRONLAKE_M(dev)) {
4bb35334 5040 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 5041 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5042 I915_READ(ILK_DISPLAY_CHICKEN1) |
5043 ILK_FBCQ_DIS);
5044 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5045 I915_READ(ILK_DISPLAY_CHICKEN2) |
5046 ILK_DPARB_GATE);
6f1d69b0
ED		 5047 }
5048
4d47e4f5
DL		 5049 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5050
6f1d69b0
ED		 5051 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5052 I915_READ(ILK_DISPLAY_CHICKEN2) |
5053 ILK_ELPIN_409_SELECT);
5054 I915_WRITE(_3D_CHICKEN2,
5055 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5056 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 5057
ecdb4eb7 5058 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 5059 I915_WRITE(CACHE_MODE_0,
5060 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 5061
4e04632e
AG		 5062 /* WaDisable_RenderCache_OperationalFlush:ilk */
5063 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5064
0e088b8f 5065 g4x_disable_trickle_feed(dev);
bdad2b2f 5066
3107bd48
DV		 5067 ibx_init_clock_gating(dev);
5068}
5069
5070static void cpt_init_clock_gating(struct drm_device *dev)
5071{
5072 struct drm_i915_private *dev_priv = dev->dev_private;
5073 int pipe;
3f704fa2 5074 uint32_t val;
3107bd48
DV		 5075
5076 /*
5077 * On Ibex Peak and Cougar Point, we need to disable clock
5078 * gating for the panel power sequencer or it will fail to
5079 * start up when no ports are active.
5080 */
cd664078
JB		 5081 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5082 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5083 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 5084 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5085 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 5086 /* The below fixes the weird display corruption, a few pixels shifted
5087 * downward, on (only) LVDS of some HP laptops with IVY.
5088 */
3f704fa2 5089 for_each_pipe(pipe) {
dc4bd2d1
PZ		 5090 val = I915_READ(TRANS_CHICKEN2(pipe));
5091 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5092 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 5093 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 5094 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 5095 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5096 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5097 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 5098 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5099 }
3107bd48
DV		 5100 /* WADP0ClockGatingDisable */
5101 for_each_pipe(pipe) {
5102 I915_WRITE(TRANS_CHICKEN1(pipe),
5103 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5104 }
6f1d69b0
ED		 5105}
5106
1d7aaa0c
DV		 5107static void gen6_check_mch_setup(struct drm_device *dev)
5108{
5109 struct drm_i915_private *dev_priv = dev->dev_private;
5110 uint32_t tmp;
5111
5112 tmp = I915_READ(MCH_SSKPD);
5113 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
5114 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
5115 DRM_INFO("This can cause pipe underruns and display issues.\n");
5116 DRM_INFO("Please upgrade your BIOS to fix this.\n");
5117 }
5118}
5119
1fa61106 5120static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5121{
5122 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5123 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5124
231e54f6 5125 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 5126
5127 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5128 I915_READ(ILK_DISPLAY_CHICKEN2) |
5129 ILK_ELPIN_409_SELECT);
5130
ecdb4eb7 5131 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 5132 I915_WRITE(_3D_CHICKEN,
5133 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5134
ecdb4eb7 5135 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 5136 if (IS_SNB_GT1(dev))
5137 I915_WRITE(GEN6_GT_MODE,
5138 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5139
4e04632e
AG		 5140 /* WaDisable_RenderCache_OperationalFlush:snb */
5141 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5142
8d85d272
VS		 5143 /*
5144 * BSpec recoomends 8x4 when MSAA is used,
5145 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5146 *
5147 * Note that PS/WM thread counts depend on the WIZ hashing
5148 * disable bit, which we don't touch here, but it's good
5149 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 5150 */
5151 I915_WRITE(GEN6_GT_MODE,
5152 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5153
017636cc 5154 ilk_init_lp_watermarks(dev);
6f1d69b0 5155
6f1d69b0 5156 I915_WRITE(CACHE_MODE_0,
50743298 5157 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 5158
5159 I915_WRITE(GEN6_UCGCTL1,
5160 I915_READ(GEN6_UCGCTL1) |
5161 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5162 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5163
5164 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5165 * gating disable must be set. Failure to set it results in
5166 * flickering pixels due to Z write ordering failures after
5167 * some amount of runtime in the Mesa "fire" demo, and Unigine
5168 * Sanctuary and Tropics, and apparently anything else with
5169 * alpha test or pixel discard.
5170 *
5171 * According to the spec, bit 11 (RCCUNIT) must also be set,
5172 * but we didn't debug actual testcases to find it out.
0f846f81 5173 *
ef59318c
VS		 5174 * WaDisableRCCUnitClockGating:snb
5175 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 5176 */
5177 I915_WRITE(GEN6_UCGCTL2,
5178 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5179 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5180
5eb146dd 5181 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 5182 I915_WRITE(_3D_CHICKEN3,
5183 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 5184
e927ecde
VS		 5185 /*
5186 * Bspec says:
5187 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
5188 * 3DSTATE_SF number of SF output attributes is more than 16."
5189 */
5190 I915_WRITE(_3D_CHICKEN3,
5191 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
5192
6f1d69b0
ED		 5193 /*
5194 * According to the spec the following bits should be
5195 * set in order to enable memory self-refresh and fbc:
5196 * The bit21 and bit22 of 0x42000
5197 * The bit21 and bit22 of 0x42004
5198 * The bit5 and bit7 of 0x42020
5199 * The bit14 of 0x70180
5200 * The bit14 of 0x71180
4bb35334
DL		 5201 *
5202 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 5203 */
5204 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5205 I915_READ(ILK_DISPLAY_CHICKEN1) |
5206 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5207 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5208 I915_READ(ILK_DISPLAY_CHICKEN2) |
5209 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 5210 I915_WRITE(ILK_DSPCLK_GATE_D,
5211 I915_READ(ILK_DSPCLK_GATE_D) |
5212 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5213 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 5214
0e088b8f 5215 g4x_disable_trickle_feed(dev);
f8f2ac9a 5216
3107bd48 5217 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5218
5219 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5220}
5221
5222static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5223{
5224 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5225
3aad9059 5226 /*
46680e0a 5227 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 5228 *
5229 * This actually overrides the dispatch
5230 * mode for all thread types.
5231 */
6f1d69b0
ED		 5232 reg &= ~GEN7_FF_SCHED_MASK;
5233 reg |= GEN7_FF_TS_SCHED_HW;
5234 reg |= GEN7_FF_VS_SCHED_HW;
5235 reg |= GEN7_FF_DS_SCHED_HW;
5236
5237 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5238}
5239
17a303ec
PZ		 5240static void lpt_init_clock_gating(struct drm_device *dev)
5241{
5242 struct drm_i915_private *dev_priv = dev->dev_private;
5243
5244 /*
5245 * TODO: this bit should only be enabled when really needed, then
5246 * disabled when not needed anymore in order to save power.
5247 */
5248 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5249 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5250 I915_READ(SOUTH_DSPCLK_GATE_D) |
5251 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 5252
5253 /* WADPOClockGatingDisable:hsw */
5254 I915_WRITE(_TRANSA_CHICKEN1,
5255 I915_READ(_TRANSA_CHICKEN1) |
5256 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 5257}
5258
7d708ee4
ID		 5259static void lpt_suspend_hw(struct drm_device *dev)
5260{
5261 struct drm_i915_private *dev_priv = dev->dev_private;
5262
5263 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5264 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5265
5266 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5267 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5268 }
5269}
5270
1020a5c2
BW		 5271static void gen8_init_clock_gating(struct drm_device *dev)
5272{
5273 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 5274 enum pipe pipe;
1020a5c2
BW		 5275
5276 I915_WRITE(WM3_LP_ILK, 0);
5277 I915_WRITE(WM2_LP_ILK, 0);
5278 I915_WRITE(WM1_LP_ILK, 0);
50ed5fbd
BW		 5279
5280 /* FIXME(BDW): Check all the w/a, some might only apply to
5281 * pre-production hw. */
5282
c8966e10
KG		 5283 /* WaDisablePartialInstShootdown:bdw */
5284 I915_WRITE(GEN8_ROW_CHICKEN,
5285 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
5286
1411e6a5
KG		 5287 /* WaDisableThreadStallDopClockGating:bdw */
5288 /* FIXME: Unclear whether we really need this on production bdw. */
5289 I915_WRITE(GEN8_ROW_CHICKEN,
5290 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
5291
4167e32c
DL		 5292 /*
5293 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
5294 * pre-production hardware
5295 */
fd392b60
BW		 5296 I915_WRITE(HALF_SLICE_CHICKEN3,
5297 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
bf66347c
BW		 5298 I915_WRITE(HALF_SLICE_CHICKEN3,
5299 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
4afe8d33
BW		 5300 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5301
7f88da0c
BW		 5302 I915_WRITE(_3D_CHICKEN3,
5303 _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
5304
a75f3628
BW		 5305 I915_WRITE(COMMON_SLICE_CHICKEN2,
5306 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
5307
4c2e7a5f
BW		 5308 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5309 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
5310
242a4018
BW		 5311 /* WaDisableDopClockGating:bdw May not be needed for production */
5312 I915_WRITE(GEN7_ROW_CHICKEN2,
5313 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5314
ab57fff1 5315 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 5316 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 5317
ab57fff1 5318 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 5319 I915_WRITE(CHICKEN_PAR1_1,
5320 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5321
ab57fff1 5322 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
07d27e20
DL		 5323 for_each_pipe(pipe) {
5324 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 5325 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 5326 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 5327 }
63801f21
BW		 5328
5329 /* Use Force Non-Coherent whenever executing a 3D context. This is a
5330 * workaround for for a possible hang in the unlikely event a TLB
5331 * invalidation occurs during a PSD flush.
5332 */
5333 I915_WRITE(HDC_CHICKEN0,
5334 I915_READ(HDC_CHICKEN0) |
5335 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
ab57fff1
BW		 5336
5337 /* WaVSRefCountFullforceMissDisable:bdw */
5338 /* WaDSRefCountFullforceMissDisable:bdw */
5339 I915_WRITE(GEN7_FF_THREAD_MODE,
5340 I915_READ(GEN7_FF_THREAD_MODE) &
5341 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c
VS		 5342
5343 /*
5344 * BSpec recommends 8x4 when MSAA is used,
5345 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5346 *
5347 * Note that PS/WM thread counts depend on the WIZ hashing
5348 * disable bit, which we don't touch here, but it's good
5349 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
36075a4c
VS		 5350 */
5351 I915_WRITE(GEN7_GT_MODE,
5352 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
295e8bb7
VS		 5353
5354 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5355 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 5356
5357 /* WaDisableSDEUnitClockGating:bdw */
5358 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5359 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680
DL		 5360
5361 /* Wa4x4STCOptimizationDisable:bdw */
5362 I915_WRITE(CACHE_MODE_1,
5363 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
1020a5c2
BW		 5364}
5365
cad2a2d7
ED		 5366static void haswell_init_clock_gating(struct drm_device *dev)
5367{
5368 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 5369
017636cc 5370 ilk_init_lp_watermarks(dev);
cad2a2d7 5371
f3fc4884
FJ		 5372 /* L3 caching of data atomics doesn't work -- disable it. */
5373 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5374 I915_WRITE(HSW_ROW_CHICKEN3,
5375 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5376
ecdb4eb7 5377 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 5378 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5379 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5380 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5381
e36ea7ff
VS		 5382 /* WaVSRefCountFullforceMissDisable:hsw */
5383 I915_WRITE(GEN7_FF_THREAD_MODE,
5384 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 5385
4e04632e
AG		 5386 /* WaDisable_RenderCache_OperationalFlush:hsw */
5387 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5388
fe27c606
CW		 5389 /* enable HiZ Raw Stall Optimization */
5390 I915_WRITE(CACHE_MODE_0_GEN7,
5391 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5392
ecdb4eb7 5393 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 5394 I915_WRITE(CACHE_MODE_1,
5395 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 5396
a12c4967
VS		 5397 /*
5398 * BSpec recommends 8x4 when MSAA is used,
5399 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5400 *
5401 * Note that PS/WM thread counts depend on the WIZ hashing
5402 * disable bit, which we don't touch here, but it's good
5403 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 5404 */
5405 I915_WRITE(GEN7_GT_MODE,
5406 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5407
ecdb4eb7 5408 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 5409 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5410
90a88643
PZ		 5411 /* WaRsPkgCStateDisplayPMReq:hsw */
5412 I915_WRITE(CHICKEN_PAR1_1,
5413 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 5414
17a303ec 5415 lpt_init_clock_gating(dev);
cad2a2d7
ED		 5416}
5417
1fa61106 5418static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5419{
5420 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 5421 uint32_t snpcr;
6f1d69b0 5422
017636cc 5423 ilk_init_lp_watermarks(dev);
6f1d69b0 5424
231e54f6 5425 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5426
ecdb4eb7 5427 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 5428 I915_WRITE(_3D_CHICKEN3,
5429 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5430
ecdb4eb7 5431 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 5432 I915_WRITE(IVB_CHICKEN3,
5433 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5434 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5435
ecdb4eb7 5436 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 5437 if (IS_IVB_GT1(dev))
5438 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5439 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 5440
4e04632e
AG		 5441 /* WaDisable_RenderCache_OperationalFlush:ivb */
5442 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5443
ecdb4eb7 5444 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 5445 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5446 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5447
ecdb4eb7 5448 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 5449 I915_WRITE(GEN7_L3CNTLREG1,
5450 GEN7_WA_FOR_GEN7_L3_CONTROL);
5451 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 5452 GEN7_WA_L3_CHICKEN_MODE);
5453 if (IS_IVB_GT1(dev))
5454 I915_WRITE(GEN7_ROW_CHICKEN2,
5455 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 5456 else {
5457 /* must write both registers */
5458 I915_WRITE(GEN7_ROW_CHICKEN2,
5459 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 5460 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5461 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 5462 }
6f1d69b0 5463
ecdb4eb7 5464 /* WaForceL3Serialization:ivb */
61939d97
JB		 5465 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5466 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5467
1b80a19a 5468 /*
0f846f81 5469 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5470 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 5471 */
5472 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 5473 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 5474
ecdb4eb7 5475 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 5476 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5477 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5478 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5479
0e088b8f 5480 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5481
5482 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 5483
22721343
CW		 5484 if (0) { /* causes HiZ corruption on ivb:gt1 */
5485 /* enable HiZ Raw Stall Optimization */
5486 I915_WRITE(CACHE_MODE_0_GEN7,
5487 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5488 }
116f2b6d 5489
ecdb4eb7 5490 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 5491 I915_WRITE(CACHE_MODE_1,
5492 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 5493
a607c1a4
VS		 5494 /*
5495 * BSpec recommends 8x4 when MSAA is used,
5496 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5497 *
5498 * Note that PS/WM thread counts depend on the WIZ hashing
5499 * disable bit, which we don't touch here, but it's good
5500 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 5501 */
5502 I915_WRITE(GEN7_GT_MODE,
5503 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5504
20848223
BW		 5505 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5506 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5507 snpcr |= GEN6_MBC_SNPCR_MED;
5508 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 5509
ab5c608b
BW		 5510 if (!HAS_PCH_NOP(dev))
5511 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5512
5513 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5514}
5515
1fa61106 5516static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5517{
5518 struct drm_i915_private *dev_priv = dev->dev_private;
85b1d7b3
JB		 5519 u32 val;
5520
5521 mutex_lock(&dev_priv->rps.hw_lock);
5522 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5523 mutex_unlock(&dev_priv->rps.hw_lock);
5524 switch ((val >> 6) & 3) {
5525 case 0:
f64a28a7 5526 case 1:
f6d51948 5527 dev_priv->mem_freq = 800;
85b1d7b3 5528 break;
f64a28a7 5529 case 2:
f6d51948 5530 dev_priv->mem_freq = 1066;
85b1d7b3 5531 break;
f64a28a7 5532 case 3:
2325991e 5533 dev_priv->mem_freq = 1333;
f64a28a7 5534 break;
85b1d7b3
JB		 5535 }
5536 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
6f1d69b0 5537
d60c4473
ID		 5538 dev_priv->vlv_cdclk_freq = valleyview_cur_cdclk(dev_priv);
5539 DRM_DEBUG_DRIVER("Current CD clock rate: %d MHz",
5540 dev_priv->vlv_cdclk_freq);
5541
d7fe0cc0 5542 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5543
ecdb4eb7 5544 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 5545 I915_WRITE(_3D_CHICKEN3,
5546 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5547
ecdb4eb7 5548 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 5549 I915_WRITE(IVB_CHICKEN3,
5550 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5551 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5552
fad7d36e 5553 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 5554 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 5555 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 5556 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5557 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 5558
4e04632e
AG		 5559 /* WaDisable_RenderCache_OperationalFlush:vlv */
5560 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5561
ecdb4eb7 5562 /* WaForceL3Serialization:vlv */
61939d97
JB		 5563 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5564 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5565
ecdb4eb7 5566 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 5567 I915_WRITE(GEN7_ROW_CHICKEN2,
5568 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5569
ecdb4eb7 5570 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 5571 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5572 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5573 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5574
46680e0a
VS		 5575 gen7_setup_fixed_func_scheduler(dev_priv);
5576
3c0edaeb 5577 /*
0f846f81 5578 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5579 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 5580 */
5581 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 5582 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 5583
c98f5062
AG		 5584 /* WaDisableL3Bank2xClockGate:vlv
5585 * Disabling L3 clock gating- MMIO 940c[25] = 1
5586 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
5587 I915_WRITE(GEN7_UCGCTL4,
5588 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 5589
e0d8d59b 5590 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 5591
afd58e79
VS		 5592 /*
5593 * BSpec says this must be set, even though
5594 * WaDisable4x2SubspanOptimization isn't listed for VLV.
5595 */
6b26c86d
DV		 5596 I915_WRITE(CACHE_MODE_1,
5597 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 5598
031994ee
VS		 5599 /*
5600 * WaIncreaseL3CreditsForVLVB0:vlv
5601 * This is the hardware default actually.
5602 */
5603 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
5604
2d809570 5605 /*
ecdb4eb7 5606 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 5607 * Disable clock gating on th GCFG unit to prevent a delay
5608 * in the reporting of vblank events.
5609 */
7a0d1eed 5610 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 5611}
5612
a4565da8
VS		 5613static void cherryview_init_clock_gating(struct drm_device *dev)
5614{
5615 struct drm_i915_private *dev_priv = dev->dev_private;
5616
5617 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5618
5619 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
dd811e70
VS		 5620
5621 /* WaDisablePartialInstShootdown:chv */
5622 I915_WRITE(GEN8_ROW_CHICKEN,
5623 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
a7068025
VS		 5624
5625 /* WaDisableThreadStallDopClockGating:chv */
5626 I915_WRITE(GEN8_ROW_CHICKEN,
5627 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
232ce337
VS		 5628
5629 /* WaVSRefCountFullforceMissDisable:chv */
5630 /* WaDSRefCountFullforceMissDisable:chv */
5631 I915_WRITE(GEN7_FF_THREAD_MODE,
5632 I915_READ(GEN7_FF_THREAD_MODE) &
5633 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 5634
5635 /* WaDisableSemaphoreAndSyncFlipWait:chv */
5636 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5637 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 5638
5639 /* WaDisableCSUnitClockGating:chv */
5640 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5641 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 5642
5643 /* WaDisableSDEUnitClockGating:chv */
5644 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5645 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
e0d34ce7
RB		 5646
5647 /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
5648 I915_WRITE(HALF_SLICE_CHICKEN3,
5649 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
e4443e45
VS		 5650
5651 /* WaDisableGunitClockGating:chv (pre-production hw) */
5652 I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
5653 GINT_DIS);
5654
5655 /* WaDisableFfDopClockGating:chv (pre-production hw) */
5656 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5657 _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
5658
5659 /* WaDisableDopClockGating:chv (pre-production hw) */
5660 I915_WRITE(GEN7_ROW_CHICKEN2,
5661 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5662 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5663 GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
a4565da8
VS		 5664}
5665
1fa61106 5666static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5667{
5668 struct drm_i915_private *dev_priv = dev->dev_private;
5669 uint32_t dspclk_gate;
5670
5671 I915_WRITE(RENCLK_GATE_D1, 0);
5672 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5673 GS_UNIT_CLOCK_GATE_DISABLE |
5674 CL_UNIT_CLOCK_GATE_DISABLE);
5675 I915_WRITE(RAMCLK_GATE_D, 0);
5676 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5677 OVRUNIT_CLOCK_GATE_DISABLE |
5678 OVCUNIT_CLOCK_GATE_DISABLE;
5679 if (IS_GM45(dev))
5680 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5681 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 5682
5683 /* WaDisableRenderCachePipelinedFlush */
5684 I915_WRITE(CACHE_MODE_0,
5685 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 5686
4e04632e
AG		 5687 /* WaDisable_RenderCache_OperationalFlush:g4x */
5688 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5689
0e088b8f 5690 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5691}
5692
1fa61106 5693static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5694{
5695 struct drm_i915_private *dev_priv = dev->dev_private;
5696
5697 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5698 I915_WRITE(RENCLK_GATE_D2, 0);
5699 I915_WRITE(DSPCLK_GATE_D, 0);
5700 I915_WRITE(RAMCLK_GATE_D, 0);
5701 I915_WRITE16(DEUC, 0);
20f94967
VS		 5702 I915_WRITE(MI_ARB_STATE,
5703 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 5704
5705 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5706 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 5707}
5708
1fa61106 5709static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5710{
5711 struct drm_i915_private *dev_priv = dev->dev_private;
5712
5713 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5714 I965_RCC_CLOCK_GATE_DISABLE |
5715 I965_RCPB_CLOCK_GATE_DISABLE |
5716 I965_ISC_CLOCK_GATE_DISABLE |
5717 I965_FBC_CLOCK_GATE_DISABLE);
5718 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 5719 I915_WRITE(MI_ARB_STATE,
5720 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 5721
5722 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5723 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 5724}
5725
1fa61106 5726static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5727{
5728 struct drm_i915_private *dev_priv = dev->dev_private;
5729 u32 dstate = I915_READ(D_STATE);
5730
5731 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5732 DSTATE_DOT_CLOCK_GATING;
5733 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 5734
5735 if (IS_PINEVIEW(dev))
5736 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 5737
5738 /* IIR "flip pending" means done if this bit is set */
5739 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 5740
5741 /* interrupts should cause a wake up from C3 */
3299254f 5742 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 5743
5744 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
5745 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
6f1d69b0
ED		 5746}
5747
1fa61106 5748static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5749{
5750 struct drm_i915_private *dev_priv = dev->dev_private;
5751
5752 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 5753
5754 /* interrupts should cause a wake up from C3 */
5755 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
5756 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
6f1d69b0
ED		 5757}
5758
1fa61106 5759static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5760{
5761 struct drm_i915_private *dev_priv = dev->dev_private;
5762
5763 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5764}
5765
6f1d69b0
ED		 5766void intel_init_clock_gating(struct drm_device *dev)
5767{
5768 struct drm_i915_private *dev_priv = dev->dev_private;
5769
5770 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 5771}
5772
7d708ee4
ID		 5773void intel_suspend_hw(struct drm_device *dev)
5774{
5775 if (HAS_PCH_LPT(dev))
5776 lpt_suspend_hw(dev);
5777}
5778
c1ca727f
ID		 5779#define for_each_power_well(i, power_well, domain_mask, power_domains) \
5780 for (i = 0; \
5781 i < (power_domains)->power_well_count && \
5782 ((power_well) = &(power_domains)->power_wells[i]); \
5783 i++) \
5784 if ((power_well)->domains & (domain_mask))
5785
5786#define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5787 for (i = (power_domains)->power_well_count - 1; \
5788 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5789 i--) \
5790 if ((power_well)->domains & (domain_mask))
5791
15d199ea
PZ		 5792/**
5793 * We should only use the power well if we explicitly asked the hardware to
5794 * enable it, so check if it's enabled and also check if we've requested it to
5795 * be enabled.
5796 */
da7e29bd 5797static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
c1ca727f
ID		 5798 struct i915_power_well *power_well)
5799{
c1ca727f
ID		 5800 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5801 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5802}
5803
da7e29bd 5804bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
ddf9c536
ID		 5805 enum intel_display_power_domain domain)
5806{
ddf9c536 5807 struct i915_power_domains *power_domains;
b8c000d9
ID		 5808 struct i915_power_well *power_well;
5809 bool is_enabled;
5810 int i;
5811
5812 if (dev_priv->pm.suspended)
5813 return false;
ddf9c536
ID		 5814
5815 power_domains = &dev_priv->power_domains;
b8c000d9
ID		 5816 is_enabled = true;
5817 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5818 if (power_well->always_on)
5819 continue;
ddf9c536 5820
b8c000d9
ID		 5821 if (!power_well->count) {
5822 is_enabled = false;
5823 break;
5824 }
5825 }
5826 return is_enabled;
ddf9c536
ID		 5827}
5828
da7e29bd 5829bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
b97186f0 5830 enum intel_display_power_domain domain)
15d199ea 5831{
c1ca727f
ID		 5832 struct i915_power_domains *power_domains;
5833 struct i915_power_well *power_well;
5834 bool is_enabled;
5835 int i;
15d199ea 5836
882244a3
PZ		 5837 if (dev_priv->pm.suspended)
5838 return false;
5839
c1ca727f
ID		 5840 power_domains = &dev_priv->power_domains;
5841
5842 is_enabled = true;
5843
5844 mutex_lock(&power_domains->lock);
5845 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6f3ef5dd
ID		 5846 if (power_well->always_on)
5847 continue;
5848
c6cb582e 5849 if (!power_well->ops->is_enabled(dev_priv, power_well)) {
c1ca727f
ID		 5850 is_enabled = false;
5851 break;
5852 }
5853 }
5854 mutex_unlock(&power_domains->lock);
5855
5856 return is_enabled;
15d199ea
PZ		 5857}
5858
93c73e8c
ID		 5859/*
5860 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5861 * when not needed anymore. We have 4 registers that can request the power well
5862 * to be enabled, and it will only be disabled if none of the registers is
5863 * requesting it to be enabled.
5864 */
d5e8fdc8
PZ		 5865static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5866{
5867 struct drm_device *dev = dev_priv->dev;
5868 unsigned long irqflags;
5869
f9dcb0df
PZ		 5870 /*
5871 * After we re-enable the power well, if we touch VGA register 0x3d5
5872 * we'll get unclaimed register interrupts. This stops after we write
5873 * anything to the VGA MSR register. The vgacon module uses this
5874 * register all the time, so if we unbind our driver and, as a
5875 * consequence, bind vgacon, we'll get stuck in an infinite loop at
5876 * console_unlock(). So make here we touch the VGA MSR register, making
5877 * sure vgacon can keep working normally without triggering interrupts
5878 * and error messages.
5879 */
5880 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5881 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
5882 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5883
d5e8fdc8
PZ		 5884 if (IS_BROADWELL(dev)) {
5885 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5886 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5887 dev_priv->de_irq_mask[PIPE_B]);
5888 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5889 ~dev_priv->de_irq_mask[PIPE_B] |
5890 GEN8_PIPE_VBLANK);
5891 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5892 dev_priv->de_irq_mask[PIPE_C]);
5893 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5894 ~dev_priv->de_irq_mask[PIPE_C] |
5895 GEN8_PIPE_VBLANK);
5896 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5897 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5898 }
5899}
5900
da7e29bd 5901static void hsw_set_power_well(struct drm_i915_private *dev_priv,
c1ca727f 5902 struct i915_power_well *power_well, bool enable)
d0d3e513 5903{
fa42e23c
PZ		 5904 bool is_enabled, enable_requested;
5905 uint32_t tmp;
d0d3e513 5906
fa42e23c 5907 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
6aedd1f5
PZ		 5908 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5909 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
d0d3e513 5910
fa42e23c
PZ		 5911 if (enable) {
5912 if (!enable_requested)
6aedd1f5
PZ		 5913 I915_WRITE(HSW_PWR_WELL_DRIVER,
5914 HSW_PWR_WELL_ENABLE_REQUEST);
d0d3e513 5915
fa42e23c
PZ		 5916 if (!is_enabled) {
5917 DRM_DEBUG_KMS("Enabling power well\n");
5918 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
6aedd1f5 5919 HSW_PWR_WELL_STATE_ENABLED), 20))
fa42e23c
PZ		 5920 DRM_ERROR("Timeout enabling power well\n");
5921 }
596cc11e 5922
d5e8fdc8 5923 hsw_power_well_post_enable(dev_priv);
fa42e23c
PZ		 5924 } else {
5925 if (enable_requested) {
5926 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
9dbd8feb 5927 POSTING_READ(HSW_PWR_WELL_DRIVER);
fa42e23c 5928 DRM_DEBUG_KMS("Requesting to disable the power well\n");
d0d3e513
ED		 5929 }
5930 }
fa42e23c 5931}
d0d3e513 5932
c6cb582e
ID		 5933static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
5934 struct i915_power_well *power_well)
5935{
5936 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
5937
5938 /*
5939 * We're taking over the BIOS, so clear any requests made by it since
5940 * the driver is in charge now.
5941 */
5942 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5943 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5944}
5945
5946static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
5947 struct i915_power_well *power_well)
5948{
c6cb582e
ID		 5949 hsw_set_power_well(dev_priv, power_well, true);
5950}
5951
5952static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
5953 struct i915_power_well *power_well)
5954{
5955 hsw_set_power_well(dev_priv, power_well, false);
c6cb582e
ID		 5956}
5957
a45f4466
ID		 5958static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
5959 struct i915_power_well *power_well)
5960{
5961}
5962
5963static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
5964 struct i915_power_well *power_well)
5965{
5966 return true;
5967}
5968
57021059
JB		 5969void __vlv_set_power_well(struct drm_i915_private *dev_priv,
5970 enum punit_power_well power_well_id, bool enable)
77961eb9 5971{
4dfbd12c 5972 struct drm_device *dev = dev_priv->dev;
77961eb9
ID		 5973 u32 mask;
5974 u32 state;
5975 u32 ctrl;
4dfbd12c 5976 enum pipe pipe;
77961eb9 5977
f618e38d
JB		 5978 if (power_well_id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
5979 if (enable) {
5980 /*
5981 * Enable the CRI clock source so we can get at the
5982 * display and the reference clock for VGA
5983 * hotplug / manual detection.
5984 */
5985 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
5986 DPLL_REFA_CLK_ENABLE_VLV |
5987 DPLL_INTEGRATED_CRI_CLK_VLV);
5988 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
5989 } else {
4dfbd12c
JB		 5990 for_each_pipe(pipe)
5991 assert_pll_disabled(dev_priv, pipe);
f618e38d
JB		 5992 /* Assert common reset */
5993 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) &
5994 ~DPIO_CMNRST);
5995 }
b00f025c 5996 }
77961eb9
ID		 5997
5998 mask = PUNIT_PWRGT_MASK(power_well_id);
5999 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
6000 PUNIT_PWRGT_PWR_GATE(power_well_id);
6001
6002 mutex_lock(&dev_priv->rps.hw_lock);
6003
6004#define COND \
6005 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
6006
6007 if (COND)
6008 goto out;
6009
6010 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
6011 ctrl &= ~mask;
6012 ctrl |= state;
6013 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
6014
6015 if (wait_for(COND, 100))
6016 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6017 state,
6018 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
6019
6020#undef COND
6021
6022out:
6023 mutex_unlock(&dev_priv->rps.hw_lock);
f618e38d
JB		 6024
6025 /*
6026 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
6027 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
6028 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
6029 * b. The other bits such as sfr settings / modesel may all
6030 * be set to 0.
6031 *
6032 * This should only be done on init and resume from S3 with
6033 * both PLLs disabled, or we risk losing DPIO and PLL
6034 * synchronization.
6035 */
6036 if (power_well_id == PUNIT_POWER_WELL_DPIO_CMN_BC && enable)
6037 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
77961eb9
ID		 6038}
6039
57021059
JB		 6040static void vlv_set_power_well(struct drm_i915_private *dev_priv,
6041 struct i915_power_well *power_well, bool enable)
6042{
6043 enum punit_power_well power_well_id = power_well->data;
6044
6045 __vlv_set_power_well(dev_priv, power_well_id, enable);
77961eb9
ID		 6046}
6047
6048static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
6049 struct i915_power_well *power_well)
6050{
6051 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
6052}
6053
6054static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
6055 struct i915_power_well *power_well)
6056{
6057 vlv_set_power_well(dev_priv, power_well, true);
6058}
6059
6060static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
6061 struct i915_power_well *power_well)
6062{
6063 vlv_set_power_well(dev_priv, power_well, false);
6064}
6065
6066static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
6067 struct i915_power_well *power_well)
6068{
6069 int power_well_id = power_well->data;
6070 bool enabled = false;
6071 u32 mask;
6072 u32 state;
6073 u32 ctrl;
6074
6075 mask = PUNIT_PWRGT_MASK(power_well_id);
6076 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
6077
6078 mutex_lock(&dev_priv->rps.hw_lock);
6079
6080 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
6081 /*
6082 * We only ever set the power-on and power-gate states, anything
6083 * else is unexpected.
6084 */
6085 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
6086 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
6087 if (state == ctrl)
6088 enabled = true;
6089
6090 /*
6091 * A transient state at this point would mean some unexpected party
6092 * is poking at the power controls too.
6093 */
6094 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
6095 WARN_ON(ctrl != state);
6096
6097 mutex_unlock(&dev_priv->rps.hw_lock);
6098
6099 return enabled;
6100}
6101
6102static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
6103 struct i915_power_well *power_well)
6104{
6105 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6106
6107 vlv_set_power_well(dev_priv, power_well, true);
6108
6109 spin_lock_irq(&dev_priv->irq_lock);
6110 valleyview_enable_display_irqs(dev_priv);
6111 spin_unlock_irq(&dev_priv->irq_lock);
6112
6113 /*
0d116a29
ID		 6114 * During driver initialization/resume we can avoid restoring the
6115 * part of the HW/SW state that will be inited anyway explicitly.
77961eb9 6116 */
0d116a29
ID		 6117 if (dev_priv->power_domains.initializing)
6118 return;
6119
6120 intel_hpd_init(dev_priv->dev);
77961eb9
ID		 6121
6122 i915_redisable_vga_power_on(dev_priv->dev);
6123}
6124
6125static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
6126 struct i915_power_well *power_well)
6127{
77961eb9
ID		 6128 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6129
6130 spin_lock_irq(&dev_priv->irq_lock);
77961eb9
ID		 6131 valleyview_disable_display_irqs(dev_priv);
6132 spin_unlock_irq(&dev_priv->irq_lock);
6133
77961eb9
ID		 6134 vlv_set_power_well(dev_priv, power_well, false);
6135}
6136
25eaa003
ID		 6137static void check_power_well_state(struct drm_i915_private *dev_priv,
6138 struct i915_power_well *power_well)
6139{
6140 bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
6141
6142 if (power_well->always_on || !i915.disable_power_well) {
6143 if (!enabled)
6144 goto mismatch;
6145
6146 return;
6147 }
6148
6149 if (enabled != (power_well->count > 0))
6150 goto mismatch;
6151
6152 return;
6153
6154mismatch:
6155 WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
6156 power_well->name, power_well->always_on, enabled,
6157 power_well->count, i915.disable_power_well);
6158}
6159
da7e29bd 6160void intel_display_power_get(struct drm_i915_private *dev_priv,
6765625e
VS		 6161 enum intel_display_power_domain domain)
6162{
83c00f55 6163 struct i915_power_domains *power_domains;
c1ca727f
ID		 6164 struct i915_power_well *power_well;
6165 int i;
6765625e 6166
9e6ea71a
PZ		 6167 intel_runtime_pm_get(dev_priv);
6168
83c00f55
ID		 6169 power_domains = &dev_priv->power_domains;
6170
6171 mutex_lock(&power_domains->lock);
1da51581 6172
25eaa003
ID		 6173 for_each_power_well(i, power_well, BIT(domain), power_domains) {
6174 if (!power_well->count++) {
6175 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
c6cb582e 6176 power_well->ops->enable(dev_priv, power_well);
25eaa003
ID		 6177 }
6178
6179 check_power_well_state(dev_priv, power_well);
6180 }
1da51581 6181
ddf9c536
ID		 6182 power_domains->domain_use_count[domain]++;
6183
83c00f55 6184 mutex_unlock(&power_domains->lock);
6765625e
VS		 6185}
6186
da7e29bd 6187void intel_display_power_put(struct drm_i915_private *dev_priv,
6765625e
VS		 6188 enum intel_display_power_domain domain)
6189{
83c00f55 6190 struct i915_power_domains *power_domains;
c1ca727f
ID		 6191 struct i915_power_well *power_well;
6192 int i;
6765625e 6193
83c00f55
ID		 6194 power_domains = &dev_priv->power_domains;
6195
6196 mutex_lock(&power_domains->lock);
1da51581 6197
1da51581
ID		 6198 WARN_ON(!power_domains->domain_use_count[domain]);
6199 power_domains->domain_use_count[domain]--;
ddf9c536 6200
70bf407c
ID		 6201 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6202 WARN_ON(!power_well->count);
6203
25eaa003
ID		 6204 if (!--power_well->count && i915.disable_power_well) {
6205 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
c6cb582e 6206 power_well->ops->disable(dev_priv, power_well);
25eaa003
ID		 6207 }
6208
6209 check_power_well_state(dev_priv, power_well);
70bf407c 6210 }
1da51581 6211
83c00f55 6212 mutex_unlock(&power_domains->lock);
9e6ea71a
PZ		 6213
6214 intel_runtime_pm_put(dev_priv);
6765625e
VS		 6215}
6216
83c00f55 6217static struct i915_power_domains *hsw_pwr;
a38911a3
WX		 6218
6219/* Display audio driver power well request */
6220void i915_request_power_well(void)
6221{
b4ed4484
ID		 6222 struct drm_i915_private *dev_priv;
6223
a38911a3
WX		 6224 if (WARN_ON(!hsw_pwr))
6225 return;
6226
b4ed4484
ID		 6227 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6228 power_domains);
da7e29bd 6229 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
a38911a3
WX		 6230}
6231EXPORT_SYMBOL_GPL(i915_request_power_well);
6232
6233/* Display audio driver power well release */
6234void i915_release_power_well(void)
6235{
b4ed4484
ID		 6236 struct drm_i915_private *dev_priv;
6237
a38911a3
WX		 6238 if (WARN_ON(!hsw_pwr))
6239 return;
6240
b4ed4484
ID		 6241 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6242 power_domains);
da7e29bd 6243 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
a38911a3
WX		 6244}
6245EXPORT_SYMBOL_GPL(i915_release_power_well);
6246
efcad917
ID		 6247#define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
6248
6249#define HSW_ALWAYS_ON_POWER_DOMAINS ( \
6250 BIT(POWER_DOMAIN_PIPE_A) | \
f5938f36 6251 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
319be8ae
ID		 6252 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
6253 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
6254 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6255 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6256 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6257 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6258 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6259 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6260 BIT(POWER_DOMAIN_PORT_CRT) | \
f5938f36 6261 BIT(POWER_DOMAIN_INIT))
efcad917
ID		 6262#define HSW_DISPLAY_POWER_DOMAINS ( \
6263 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
6264 BIT(POWER_DOMAIN_INIT))
6265
6266#define BDW_ALWAYS_ON_POWER_DOMAINS ( \
6267 HSW_ALWAYS_ON_POWER_DOMAINS | \
6268 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
6269#define BDW_DISPLAY_POWER_DOMAINS ( \
6270 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
6271 BIT(POWER_DOMAIN_INIT))
6272
77961eb9
ID		 6273#define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
6274#define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
6275
6276#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
6277 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6278 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6279 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6280 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6281 BIT(POWER_DOMAIN_PORT_CRT) | \
6282 BIT(POWER_DOMAIN_INIT))
6283
6284#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
6285 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6286 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6287 BIT(POWER_DOMAIN_INIT))
6288
6289#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
6290 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6291 BIT(POWER_DOMAIN_INIT))
6292
6293#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
6294 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6295 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6296 BIT(POWER_DOMAIN_INIT))
6297
6298#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
6299 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6300 BIT(POWER_DOMAIN_INIT))
6301
a45f4466
ID		 6302static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
6303 .sync_hw = i9xx_always_on_power_well_noop,
6304 .enable = i9xx_always_on_power_well_noop,
6305 .disable = i9xx_always_on_power_well_noop,
6306 .is_enabled = i9xx_always_on_power_well_enabled,
6307};
c6cb582e 6308
1c2256df
ID		 6309static struct i915_power_well i9xx_always_on_power_well[] = {
6310 {
6311 .name = "always-on",
6312 .always_on = 1,
6313 .domains = POWER_DOMAIN_MASK,
c6cb582e 6314 .ops = &i9xx_always_on_power_well_ops,
1c2256df
ID		 6315 },
6316};
6317
c6cb582e
ID		 6318static const struct i915_power_well_ops hsw_power_well_ops = {
6319 .sync_hw = hsw_power_well_sync_hw,
6320 .enable = hsw_power_well_enable,
6321 .disable = hsw_power_well_disable,
6322 .is_enabled = hsw_power_well_enabled,
6323};
6324
c1ca727f 6325static struct i915_power_well hsw_power_wells[] = {
6f3ef5dd
ID		 6326 {
6327 .name = "always-on",
6328 .always_on = 1,
6329 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
c6cb582e 6330 .ops = &i9xx_always_on_power_well_ops,
6f3ef5dd 6331 },
c1ca727f
ID		 6332 {
6333 .name = "display",
efcad917 6334 .domains = HSW_DISPLAY_POWER_DOMAINS,
c6cb582e 6335 .ops = &hsw_power_well_ops,
c1ca727f
ID		 6336 },
6337};
6338
6339static struct i915_power_well bdw_power_wells[] = {
6f3ef5dd
ID		 6340 {
6341 .name = "always-on",
6342 .always_on = 1,
6343 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
c6cb582e 6344 .ops = &i9xx_always_on_power_well_ops,
6f3ef5dd 6345 },
c1ca727f
ID		 6346 {
6347 .name = "display",
efcad917 6348 .domains = BDW_DISPLAY_POWER_DOMAINS,
c6cb582e 6349 .ops = &hsw_power_well_ops,
c1ca727f
ID		 6350 },
6351};
6352
77961eb9
ID		 6353static const struct i915_power_well_ops vlv_display_power_well_ops = {
6354 .sync_hw = vlv_power_well_sync_hw,
6355 .enable = vlv_display_power_well_enable,
6356 .disable = vlv_display_power_well_disable,
6357 .is_enabled = vlv_power_well_enabled,
6358};
6359
6360static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
6361 .sync_hw = vlv_power_well_sync_hw,
6362 .enable = vlv_power_well_enable,
6363 .disable = vlv_power_well_disable,
6364 .is_enabled = vlv_power_well_enabled,
6365};
6366
6367static struct i915_power_well vlv_power_wells[] = {
6368 {
6369 .name = "always-on",
6370 .always_on = 1,
6371 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
6372 .ops = &i9xx_always_on_power_well_ops,
6373 },
6374 {
6375 .name = "display",
6376 .domains = VLV_DISPLAY_POWER_DOMAINS,
6377 .data = PUNIT_POWER_WELL_DISP2D,
6378 .ops = &vlv_display_power_well_ops,
6379 },
77961eb9
ID		 6380 {
6381 .name = "dpio-tx-b-01",
6382 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6383 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6384 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6385 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6386 .ops = &vlv_dpio_power_well_ops,
6387 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
6388 },
6389 {
6390 .name = "dpio-tx-b-23",
6391 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6392 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6393 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6394 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6395 .ops = &vlv_dpio_power_well_ops,
6396 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
6397 },
6398 {
6399 .name = "dpio-tx-c-01",
6400 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6401 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6402 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6403 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6404 .ops = &vlv_dpio_power_well_ops,
6405 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
6406 },
6407 {
6408 .name = "dpio-tx-c-23",
6409 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6410 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6411 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6412 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6413 .ops = &vlv_dpio_power_well_ops,
6414 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
6415 },
f099a3c6
JB		 6416 {
6417 .name = "dpio-common",
6418 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
6419 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
6420 .ops = &vlv_dpio_power_well_ops,
6421 },
77961eb9
ID		 6422};
6423
c1ca727f
ID		 6424#define set_power_wells(power_domains, __power_wells) ({ \
6425 (power_domains)->power_wells = (__power_wells); \
6426 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
6427})
6428
da7e29bd 6429int intel_power_domains_init(struct drm_i915_private *dev_priv)
a38911a3 6430{
83c00f55 6431 struct i915_power_domains *power_domains = &dev_priv->power_domains;
c1ca727f 6432
83c00f55 6433 mutex_init(&power_domains->lock);
a38911a3 6434
c1ca727f
ID		 6435 /*
6436 * The enabling order will be from lower to higher indexed wells,
6437 * the disabling order is reversed.
6438 */
da7e29bd 6439 if (IS_HASWELL(dev_priv->dev)) {
c1ca727f
ID		 6440 set_power_wells(power_domains, hsw_power_wells);
6441 hsw_pwr = power_domains;
da7e29bd 6442 } else if (IS_BROADWELL(dev_priv->dev)) {
c1ca727f
ID		 6443 set_power_wells(power_domains, bdw_power_wells);
6444 hsw_pwr = power_domains;
77961eb9
ID		 6445 } else if (IS_VALLEYVIEW(dev_priv->dev)) {
6446 set_power_wells(power_domains, vlv_power_wells);
c1ca727f 6447 } else {
1c2256df 6448 set_power_wells(power_domains, i9xx_always_on_power_well);
c1ca727f 6449 }
a38911a3
WX		 6450
6451 return 0;
6452}
6453
da7e29bd 6454void intel_power_domains_remove(struct drm_i915_private *dev_priv)
a38911a3
WX		 6455{
6456 hsw_pwr = NULL;
6457}
6458
da7e29bd 6459static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
9cdb826c 6460{
83c00f55
ID		 6461 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6462 struct i915_power_well *power_well;
c1ca727f 6463 int i;
9cdb826c 6464
83c00f55 6465 mutex_lock(&power_domains->lock);
a45f4466
ID		 6466 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains)
6467 power_well->ops->sync_hw(dev_priv, power_well);
83c00f55 6468 mutex_unlock(&power_domains->lock);
a38911a3
WX		 6469}
6470
da7e29bd 6471void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
d0d3e513 6472{
0d116a29
ID		 6473 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6474
6475 power_domains->initializing = true;
fa42e23c 6476 /* For now, we need the power well to be always enabled. */
da7e29bd
ID		 6477 intel_display_set_init_power(dev_priv, true);
6478 intel_power_domains_resume(dev_priv);
0d116a29 6479 power_domains->initializing = false;
d0d3e513
ED		 6480}
6481
c67a470b
PZ		 6482void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
6483{
d361ae26 6484 intel_runtime_pm_get(dev_priv);
c67a470b
PZ		 6485}
6486
6487void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
6488{
d361ae26 6489 intel_runtime_pm_put(dev_priv);
c67a470b
PZ		 6490}
6491
8a187455
PZ		 6492void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
6493{
6494 struct drm_device *dev = dev_priv->dev;
6495 struct device *device = &dev->pdev->dev;
6496
6497 if (!HAS_RUNTIME_PM(dev))
6498 return;
6499
6500 pm_runtime_get_sync(device);
6501 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
6502}
6503
c6df39b5
ID		 6504void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
6505{
6506 struct drm_device *dev = dev_priv->dev;
6507 struct device *device = &dev->pdev->dev;
6508
6509 if (!HAS_RUNTIME_PM(dev))
6510 return;
6511
6512 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
6513 pm_runtime_get_noresume(device);
6514}
6515
8a187455
PZ		 6516void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
6517{
6518 struct drm_device *dev = dev_priv->dev;
6519 struct device *device = &dev->pdev->dev;
6520
6521 if (!HAS_RUNTIME_PM(dev))
6522 return;
6523
6524 pm_runtime_mark_last_busy(device);
6525 pm_runtime_put_autosuspend(device);
6526}
6527
6528void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
6529{
6530 struct drm_device *dev = dev_priv->dev;
6531 struct device *device = &dev->pdev->dev;
6532
8a187455
PZ		 6533 if (!HAS_RUNTIME_PM(dev))
6534 return;
6535
6536 pm_runtime_set_active(device);
6537
aeab0b5a
ID		 6538 /*
6539 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6540 * requirement.
6541 */
6542 if (!intel_enable_rc6(dev)) {
6543 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6544 return;
6545 }
6546
8a187455
PZ		 6547 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
6548 pm_runtime_mark_last_busy(device);
6549 pm_runtime_use_autosuspend(device);
ba0239e0
PZ		 6550
6551 pm_runtime_put_autosuspend(device);
8a187455
PZ		 6552}
6553
6554void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
6555{
6556 struct drm_device *dev = dev_priv->dev;
6557 struct device *device = &dev->pdev->dev;
6558
6559 if (!HAS_RUNTIME_PM(dev))
6560 return;
6561
aeab0b5a
ID		 6562 if (!intel_enable_rc6(dev))
6563 return;
6564
8a187455
PZ		 6565 /* Make sure we're not suspended first. */
6566 pm_runtime_get_sync(device);
6567 pm_runtime_disable(device);
6568}
6569
1fa61106
ED		 6570/* Set up chip specific power management-related functions */
6571void intel_init_pm(struct drm_device *dev)
6572{
6573 struct drm_i915_private *dev_priv = dev->dev_private;
6574
3a77c4c4 6575 if (HAS_FBC(dev)) {
40045465 6576 if (INTEL_INFO(dev)->gen >= 7) {
1fa61106 6577 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
40045465
VS		 6578 dev_priv->display.enable_fbc = gen7_enable_fbc;
6579 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6580 } else if (INTEL_INFO(dev)->gen >= 5) {
6581 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6582 dev_priv->display.enable_fbc = ironlake_enable_fbc;
1fa61106
ED		 6583 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6584 } else if (IS_GM45(dev)) {
6585 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6586 dev_priv->display.enable_fbc = g4x_enable_fbc;
6587 dev_priv->display.disable_fbc = g4x_disable_fbc;
40045465 6588 } else {
1fa61106
ED		 6589 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6590 dev_priv->display.enable_fbc = i8xx_enable_fbc;
6591 dev_priv->display.disable_fbc = i8xx_disable_fbc;
993495ae
VS		 6592
6593 /* This value was pulled out of someone's hat */
6594 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
1fa61106 6595 }
1fa61106
ED		 6596 }
6597
c921aba8
DV		 6598 /* For cxsr */
6599 if (IS_PINEVIEW(dev))
6600 i915_pineview_get_mem_freq(dev);
6601 else if (IS_GEN5(dev))
6602 i915_ironlake_get_mem_freq(dev);
6603
1fa61106
ED		 6604 /* For FIFO watermark updates */
6605 if (HAS_PCH_SPLIT(dev)) {
fa50ad61 6606 ilk_setup_wm_latency(dev);
53615a5e 6607
bd602544
VS		 6608 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6609 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6610 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6611 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6612 dev_priv->display.update_wm = ilk_update_wm;
6613 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6614 } else {
6615 DRM_DEBUG_KMS("Failed to read display plane latency. "
6616 "Disable CxSR\n");
6617 }
6618
6619 if (IS_GEN5(dev))
1fa61106 6620 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 6621 else if (IS_GEN6(dev))
1fa61106 6622 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 6623 else if (IS_IVYBRIDGE(dev))
1fa61106 6624 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 6625 else if (IS_HASWELL(dev))
cad2a2d7 6626 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 6627 else if (INTEL_INFO(dev)->gen == 8)
1020a5c2 6628 dev_priv->display.init_clock_gating = gen8_init_clock_gating;
a4565da8
VS		 6629 } else if (IS_CHERRYVIEW(dev)) {
6630 dev_priv->display.update_wm = valleyview_update_wm;
6631 dev_priv->display.init_clock_gating =
6632 cherryview_init_clock_gating;
1fa61106
ED		 6633 } else if (IS_VALLEYVIEW(dev)) {
6634 dev_priv->display.update_wm = valleyview_update_wm;
6635 dev_priv->display.init_clock_gating =
6636 valleyview_init_clock_gating;
1fa61106
ED		 6637 } else if (IS_PINEVIEW(dev)) {
6638 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6639 dev_priv->is_ddr3,
6640 dev_priv->fsb_freq,
6641 dev_priv->mem_freq)) {
6642 DRM_INFO("failed to find known CxSR latency "
6643 "(found ddr%s fsb freq %d, mem freq %d), "
6644 "disabling CxSR\n",
6645 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6646 dev_priv->fsb_freq, dev_priv->mem_freq);
6647 /* Disable CxSR and never update its watermark again */
6648 pineview_disable_cxsr(dev);
6649 dev_priv->display.update_wm = NULL;
6650 } else
6651 dev_priv->display.update_wm = pineview_update_wm;
6652 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6653 } else if (IS_G4X(dev)) {
6654 dev_priv->display.update_wm = g4x_update_wm;
6655 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6656 } else if (IS_GEN4(dev)) {
6657 dev_priv->display.update_wm = i965_update_wm;
6658 if (IS_CRESTLINE(dev))
6659 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6660 else if (IS_BROADWATER(dev))
6661 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6662 } else if (IS_GEN3(dev)) {
6663 dev_priv->display.update_wm = i9xx_update_wm;
6664 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6665 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 6666 } else if (IS_GEN2(dev)) {
6667 if (INTEL_INFO(dev)->num_pipes == 1) {
6668 dev_priv->display.update_wm = i845_update_wm;
1fa61106 6669 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 6670 } else {
6671 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 6672 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 6673 }
6674
6675 if (IS_I85X(dev) || IS_I865G(dev))
6676 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6677 else
6678 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6679 } else {
6680 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 6681 }
6682}
6683
42c0526c
BW		 6684int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
6685{
4fc688ce 6686 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6687
6688 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6689 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6690 return -EAGAIN;
6691 }
6692
6693 I915_WRITE(GEN6_PCODE_DATA, *val);
6694 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6695
6696 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6697 500)) {
6698 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6699 return -ETIMEDOUT;
6700 }
6701
6702 *val = I915_READ(GEN6_PCODE_DATA);
6703 I915_WRITE(GEN6_PCODE_DATA, 0);
6704
6705 return 0;
6706}
6707
6708int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
6709{
4fc688ce 6710 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6711
6712 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6713 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6714 return -EAGAIN;
6715 }
6716
6717 I915_WRITE(GEN6_PCODE_DATA, val);
6718 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6719
6720 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6721 500)) {
6722 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6723 return -ETIMEDOUT;
6724 }
6725
6726 I915_WRITE(GEN6_PCODE_DATA, 0);
6727
6728 return 0;
6729}
a0e4e199 6730
2ec3815f 6731int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
855ba3be 6732{
07ab118b 6733 int div;
855ba3be 6734
07ab118b 6735 /* 4 x czclk */
2ec3815f 6736 switch (dev_priv->mem_freq) {
855ba3be 6737 case 800:
07ab118b 6738 div = 10;
855ba3be
JB		 6739 break;
6740 case 1066:
07ab118b 6741 div = 12;
855ba3be
JB		 6742 break;
6743 case 1333:
07ab118b 6744 div = 16;
855ba3be
JB		 6745 break;
6746 default:
6747 return -1;
6748 }
6749
2ec3815f 6750 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
855ba3be
JB		 6751}
6752
2ec3815f 6753int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 6754{
07ab118b 6755 int mul;
855ba3be 6756
07ab118b 6757 /* 4 x czclk */
2ec3815f 6758 switch (dev_priv->mem_freq) {
855ba3be 6759 case 800:
07ab118b 6760 mul = 10;
855ba3be
JB		 6761 break;
6762 case 1066:
07ab118b 6763 mul = 12;
855ba3be
JB		 6764 break;
6765 case 1333:
07ab118b 6766 mul = 16;
855ba3be
JB		 6767 break;
6768 default:
6769 return -1;
6770 }
6771
2ec3815f 6772 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
855ba3be
JB		 6773}
6774
f742a552 6775void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 6776{
6777 struct drm_i915_private *dev_priv = dev->dev_private;
6778
f742a552
DV		 6779 mutex_init(&dev_priv->rps.hw_lock);
6780
907b28c5
CW		 6781 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6782 intel_gen6_powersave_work);
5d584b2e 6783
33688d95 6784 dev_priv->pm.suspended = false;
5d584b2e 6785 dev_priv->pm.irqs_disabled = false;
907b28c5 6786}
Linux 6.x block layer and io_uring tree(s)