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drm/i915: SWF screatch registers need an offset on VLV
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
057d3860 34#define FORCEWAKE_ACK_TIMEOUT_MS 2
b67a4376 35
f6750b3c
ED		 36/* FBC, or Frame Buffer Compression, is a technique employed to compress the
37 * framebuffer contents in-memory, aiming at reducing the required bandwidth
38 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 39 *
f6750b3c
ED		 40 * The benefits of FBC are mostly visible with solid backgrounds and
41 * variation-less patterns.
85208be0 42 *
f6750b3c
ED		 43 * FBC-related functionality can be enabled by the means of the
44 * i915.i915_enable_fbc parameter
85208be0
ED		 45 */
46
1fa61106 47static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 48{
49 struct drm_i915_private *dev_priv = dev->dev_private;
50 u32 fbc_ctl;
51
52 /* Disable compression */
53 fbc_ctl = I915_READ(FBC_CONTROL);
54 if ((fbc_ctl & FBC_CTL_EN) == 0)
55 return;
56
57 fbc_ctl &= ~FBC_CTL_EN;
58 I915_WRITE(FBC_CONTROL, fbc_ctl);
59
60 /* Wait for compressing bit to clear */
61 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
62 DRM_DEBUG_KMS("FBC idle timed out\n");
63 return;
64 }
65
66 DRM_DEBUG_KMS("disabled FBC\n");
67}
68
1fa61106 69static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 70{
71 struct drm_device *dev = crtc->dev;
72 struct drm_i915_private *dev_priv = dev->dev_private;
73 struct drm_framebuffer *fb = crtc->fb;
74 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
75 struct drm_i915_gem_object *obj = intel_fb->obj;
76 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
77 int cfb_pitch;
78 int plane, i;
79 u32 fbc_ctl, fbc_ctl2;
80
81 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
82 if (fb->pitches[0] < cfb_pitch)
83 cfb_pitch = fb->pitches[0];
84
85 /* FBC_CTL wants 64B units */
86 cfb_pitch = (cfb_pitch / 64) - 1;
87 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
88
89 /* Clear old tags */
90 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
91 I915_WRITE(FBC_TAG + (i * 4), 0);
92
93 /* Set it up... */
94 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
95 fbc_ctl2 |= plane;
96 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
97 I915_WRITE(FBC_FENCE_OFF, crtc->y);
98
99 /* enable it... */
100 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
101 if (IS_I945GM(dev))
102 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
103 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
104 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
105 fbc_ctl |= obj->fence_reg;
106 I915_WRITE(FBC_CONTROL, fbc_ctl);
107
108 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
109 cfb_pitch, crtc->y, intel_crtc->plane);
110}
111
1fa61106 112static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 113{
114 struct drm_i915_private *dev_priv = dev->dev_private;
115
116 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
117}
118
1fa61106 119static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 120{
121 struct drm_device *dev = crtc->dev;
122 struct drm_i915_private *dev_priv = dev->dev_private;
123 struct drm_framebuffer *fb = crtc->fb;
124 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
125 struct drm_i915_gem_object *obj = intel_fb->obj;
126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
127 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
128 unsigned long stall_watermark = 200;
129 u32 dpfc_ctl;
130
131 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
132 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
133 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
134
135 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
136 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
137 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
138 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
139
140 /* enable it... */
141 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
142
143 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
144}
145
1fa61106 146static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 147{
148 struct drm_i915_private *dev_priv = dev->dev_private;
149 u32 dpfc_ctl;
150
151 /* Disable compression */
152 dpfc_ctl = I915_READ(DPFC_CONTROL);
153 if (dpfc_ctl & DPFC_CTL_EN) {
154 dpfc_ctl &= ~DPFC_CTL_EN;
155 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
156
157 DRM_DEBUG_KMS("disabled FBC\n");
158 }
159}
160
1fa61106 161static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 162{
163 struct drm_i915_private *dev_priv = dev->dev_private;
164
165 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
166}
167
168static void sandybridge_blit_fbc_update(struct drm_device *dev)
169{
170 struct drm_i915_private *dev_priv = dev->dev_private;
171 u32 blt_ecoskpd;
172
173 /* Make sure blitter notifies FBC of writes */
174 gen6_gt_force_wake_get(dev_priv);
175 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
176 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
177 GEN6_BLITTER_LOCK_SHIFT;
178 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
179 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
180 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
181 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
182 GEN6_BLITTER_LOCK_SHIFT);
183 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
184 POSTING_READ(GEN6_BLITTER_ECOSKPD);
185 gen6_gt_force_wake_put(dev_priv);
186}
187
1fa61106 188static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 189{
190 struct drm_device *dev = crtc->dev;
191 struct drm_i915_private *dev_priv = dev->dev_private;
192 struct drm_framebuffer *fb = crtc->fb;
193 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
194 struct drm_i915_gem_object *obj = intel_fb->obj;
195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
196 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
197 unsigned long stall_watermark = 200;
198 u32 dpfc_ctl;
199
200 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
201 dpfc_ctl &= DPFC_RESERVED;
202 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
203 /* Set persistent mode for front-buffer rendering, ala X. */
204 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
205 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
206 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
207
208 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
209 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
210 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
211 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
212 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
213 /* enable it... */
214 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
215
216 if (IS_GEN6(dev)) {
217 I915_WRITE(SNB_DPFC_CTL_SA,
218 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
219 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
220 sandybridge_blit_fbc_update(dev);
221 }
222
223 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
224}
225
1fa61106 226static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 227{
228 struct drm_i915_private *dev_priv = dev->dev_private;
229 u32 dpfc_ctl;
230
231 /* Disable compression */
232 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
233 if (dpfc_ctl & DPFC_CTL_EN) {
234 dpfc_ctl &= ~DPFC_CTL_EN;
235 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
236
237 DRM_DEBUG_KMS("disabled FBC\n");
238 }
239}
240
1fa61106 241static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 242{
243 struct drm_i915_private *dev_priv = dev->dev_private;
244
245 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
246}
247
248bool intel_fbc_enabled(struct drm_device *dev)
249{
250 struct drm_i915_private *dev_priv = dev->dev_private;
251
252 if (!dev_priv->display.fbc_enabled)
253 return false;
254
255 return dev_priv->display.fbc_enabled(dev);
256}
257
258static void intel_fbc_work_fn(struct work_struct *__work)
259{
260 struct intel_fbc_work *work =
261 container_of(to_delayed_work(__work),
262 struct intel_fbc_work, work);
263 struct drm_device *dev = work->crtc->dev;
264 struct drm_i915_private *dev_priv = dev->dev_private;
265
266 mutex_lock(&dev->struct_mutex);
267 if (work == dev_priv->fbc_work) {
268 /* Double check that we haven't switched fb without cancelling
269 * the prior work.
270 */
271 if (work->crtc->fb == work->fb) {
272 dev_priv->display.enable_fbc(work->crtc,
273 work->interval);
274
275 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
276 dev_priv->cfb_fb = work->crtc->fb->base.id;
277 dev_priv->cfb_y = work->crtc->y;
278 }
279
280 dev_priv->fbc_work = NULL;
281 }
282 mutex_unlock(&dev->struct_mutex);
283
284 kfree(work);
285}
286
287static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
288{
289 if (dev_priv->fbc_work == NULL)
290 return;
291
292 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
293
294 /* Synchronisation is provided by struct_mutex and checking of
295 * dev_priv->fbc_work, so we can perform the cancellation
296 * entirely asynchronously.
297 */
298 if (cancel_delayed_work(&dev_priv->fbc_work->work))
299 /* tasklet was killed before being run, clean up */
300 kfree(dev_priv->fbc_work);
301
302 /* Mark the work as no longer wanted so that if it does
303 * wake-up (because the work was already running and waiting
304 * for our mutex), it will discover that is no longer
305 * necessary to run.
306 */
307 dev_priv->fbc_work = NULL;
308}
309
310void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
311{
312 struct intel_fbc_work *work;
313 struct drm_device *dev = crtc->dev;
314 struct drm_i915_private *dev_priv = dev->dev_private;
315
316 if (!dev_priv->display.enable_fbc)
317 return;
318
319 intel_cancel_fbc_work(dev_priv);
320
321 work = kzalloc(sizeof *work, GFP_KERNEL);
322 if (work == NULL) {
323 dev_priv->display.enable_fbc(crtc, interval);
324 return;
325 }
326
327 work->crtc = crtc;
328 work->fb = crtc->fb;
329 work->interval = interval;
330 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
331
332 dev_priv->fbc_work = work;
333
334 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
335
336 /* Delay the actual enabling to let pageflipping cease and the
337 * display to settle before starting the compression. Note that
338 * this delay also serves a second purpose: it allows for a
339 * vblank to pass after disabling the FBC before we attempt
340 * to modify the control registers.
341 *
342 * A more complicated solution would involve tracking vblanks
343 * following the termination of the page-flipping sequence
344 * and indeed performing the enable as a co-routine and not
345 * waiting synchronously upon the vblank.
346 */
347 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
348}
349
350void intel_disable_fbc(struct drm_device *dev)
351{
352 struct drm_i915_private *dev_priv = dev->dev_private;
353
354 intel_cancel_fbc_work(dev_priv);
355
356 if (!dev_priv->display.disable_fbc)
357 return;
358
359 dev_priv->display.disable_fbc(dev);
360 dev_priv->cfb_plane = -1;
361}
362
363/**
364 * intel_update_fbc - enable/disable FBC as needed
365 * @dev: the drm_device
366 *
367 * Set up the framebuffer compression hardware at mode set time. We
368 * enable it if possible:
369 * - plane A only (on pre-965)
370 * - no pixel mulitply/line duplication
371 * - no alpha buffer discard
372 * - no dual wide
373 * - framebuffer <= 2048 in width, 1536 in height
374 *
375 * We can't assume that any compression will take place (worst case),
376 * so the compressed buffer has to be the same size as the uncompressed
377 * one. It also must reside (along with the line length buffer) in
378 * stolen memory.
379 *
380 * We need to enable/disable FBC on a global basis.
381 */
382void intel_update_fbc(struct drm_device *dev)
383{
384 struct drm_i915_private *dev_priv = dev->dev_private;
385 struct drm_crtc *crtc = NULL, *tmp_crtc;
386 struct intel_crtc *intel_crtc;
387 struct drm_framebuffer *fb;
388 struct intel_framebuffer *intel_fb;
389 struct drm_i915_gem_object *obj;
390 int enable_fbc;
391
85208be0
ED		 392 if (!i915_powersave)
393 return;
394
395 if (!I915_HAS_FBC(dev))
396 return;
397
398 /*
399 * If FBC is already on, we just have to verify that we can
400 * keep it that way...
401 * Need to disable if:
402 * - more than one pipe is active
403 * - changing FBC params (stride, fence, mode)
404 * - new fb is too large to fit in compressed buffer
405 * - going to an unsupported config (interlace, pixel multiply, etc.)
406 */
407 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
f20e0b08 408 if (to_intel_crtc(tmp_crtc)->active &&
93314b5b
CW		 409 !to_intel_crtc(tmp_crtc)->primary_disabled &&
410 tmp_crtc->fb) {
85208be0
ED		 411 if (crtc) {
412 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
413 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
414 goto out_disable;
415 }
416 crtc = tmp_crtc;
417 }
418 }
419
420 if (!crtc || crtc->fb == NULL) {
421 DRM_DEBUG_KMS("no output, disabling\n");
422 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
423 goto out_disable;
424 }
425
426 intel_crtc = to_intel_crtc(crtc);
427 fb = crtc->fb;
428 intel_fb = to_intel_framebuffer(fb);
429 obj = intel_fb->obj;
430
431 enable_fbc = i915_enable_fbc;
432 if (enable_fbc < 0) {
433 DRM_DEBUG_KMS("fbc set to per-chip default\n");
434 enable_fbc = 1;
435 if (INTEL_INFO(dev)->gen <= 6)
436 enable_fbc = 0;
437 }
438 if (!enable_fbc) {
439 DRM_DEBUG_KMS("fbc disabled per module param\n");
440 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
441 goto out_disable;
442 }
85208be0
ED		 443 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
444 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
445 DRM_DEBUG_KMS("mode incompatible with compression, "
446 "disabling\n");
447 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
448 goto out_disable;
449 }
450 if ((crtc->mode.hdisplay > 2048) ||
451 (crtc->mode.vdisplay > 1536)) {
452 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
453 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
454 goto out_disable;
455 }
456 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
457 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
458 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
459 goto out_disable;
460 }
461
462 /* The use of a CPU fence is mandatory in order to detect writes
463 * by the CPU to the scanout and trigger updates to the FBC.
464 */
465 if (obj->tiling_mode != I915_TILING_X ||
466 obj->fence_reg == I915_FENCE_REG_NONE) {
467 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
468 dev_priv->no_fbc_reason = FBC_NOT_TILED;
469 goto out_disable;
470 }
471
472 /* If the kernel debugger is active, always disable compression */
473 if (in_dbg_master())
474 goto out_disable;
475
11be49eb
CW		 476 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
477 DRM_INFO("not enough stolen space for compressed buffer (need %zd bytes), disabling\n", intel_fb->obj->base.size);
478 DRM_INFO("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
479 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
480 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
481 goto out_disable;
482 }
483
85208be0
ED		 484 /* If the scanout has not changed, don't modify the FBC settings.
485 * Note that we make the fundamental assumption that the fb->obj
486 * cannot be unpinned (and have its GTT offset and fence revoked)
487 * without first being decoupled from the scanout and FBC disabled.
488 */
489 if (dev_priv->cfb_plane == intel_crtc->plane &&
490 dev_priv->cfb_fb == fb->base.id &&
491 dev_priv->cfb_y == crtc->y)
492 return;
493
494 if (intel_fbc_enabled(dev)) {
495 /* We update FBC along two paths, after changing fb/crtc
496 * configuration (modeswitching) and after page-flipping
497 * finishes. For the latter, we know that not only did
498 * we disable the FBC at the start of the page-flip
499 * sequence, but also more than one vblank has passed.
500 *
501 * For the former case of modeswitching, it is possible
502 * to switch between two FBC valid configurations
503 * instantaneously so we do need to disable the FBC
504 * before we can modify its control registers. We also
505 * have to wait for the next vblank for that to take
506 * effect. However, since we delay enabling FBC we can
507 * assume that a vblank has passed since disabling and
508 * that we can safely alter the registers in the deferred
509 * callback.
510 *
511 * In the scenario that we go from a valid to invalid
512 * and then back to valid FBC configuration we have
513 * no strict enforcement that a vblank occurred since
514 * disabling the FBC. However, along all current pipe
515 * disabling paths we do need to wait for a vblank at
516 * some point. And we wait before enabling FBC anyway.
517 */
518 DRM_DEBUG_KMS("disabling active FBC for update\n");
519 intel_disable_fbc(dev);
520 }
521
522 intel_enable_fbc(crtc, 500);
523 return;
524
525out_disable:
526 /* Multiple disables should be harmless */
527 if (intel_fbc_enabled(dev)) {
528 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
529 intel_disable_fbc(dev);
530 }
11be49eb 531 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 532}
533
c921aba8
DV		 534static void i915_pineview_get_mem_freq(struct drm_device *dev)
535{
536 drm_i915_private_t *dev_priv = dev->dev_private;
537 u32 tmp;
538
539 tmp = I915_READ(CLKCFG);
540
541 switch (tmp & CLKCFG_FSB_MASK) {
542 case CLKCFG_FSB_533:
543 dev_priv->fsb_freq = 533; /* 133*4 */
544 break;
545 case CLKCFG_FSB_800:
546 dev_priv->fsb_freq = 800; /* 200*4 */
547 break;
548 case CLKCFG_FSB_667:
549 dev_priv->fsb_freq = 667; /* 167*4 */
550 break;
551 case CLKCFG_FSB_400:
552 dev_priv->fsb_freq = 400; /* 100*4 */
553 break;
554 }
555
556 switch (tmp & CLKCFG_MEM_MASK) {
557 case CLKCFG_MEM_533:
558 dev_priv->mem_freq = 533;
559 break;
560 case CLKCFG_MEM_667:
561 dev_priv->mem_freq = 667;
562 break;
563 case CLKCFG_MEM_800:
564 dev_priv->mem_freq = 800;
565 break;
566 }
567
568 /* detect pineview DDR3 setting */
569 tmp = I915_READ(CSHRDDR3CTL);
570 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
571}
572
573static void i915_ironlake_get_mem_freq(struct drm_device *dev)
574{
575 drm_i915_private_t *dev_priv = dev->dev_private;
576 u16 ddrpll, csipll;
577
578 ddrpll = I915_READ16(DDRMPLL1);
579 csipll = I915_READ16(CSIPLL0);
580
581 switch (ddrpll & 0xff) {
582 case 0xc:
583 dev_priv->mem_freq = 800;
584 break;
585 case 0x10:
586 dev_priv->mem_freq = 1066;
587 break;
588 case 0x14:
589 dev_priv->mem_freq = 1333;
590 break;
591 case 0x18:
592 dev_priv->mem_freq = 1600;
593 break;
594 default:
595 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
596 ddrpll & 0xff);
597 dev_priv->mem_freq = 0;
598 break;
599 }
600
20e4d407 601 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 602
603 switch (csipll & 0x3ff) {
604 case 0x00c:
605 dev_priv->fsb_freq = 3200;
606 break;
607 case 0x00e:
608 dev_priv->fsb_freq = 3733;
609 break;
610 case 0x010:
611 dev_priv->fsb_freq = 4266;
612 break;
613 case 0x012:
614 dev_priv->fsb_freq = 4800;
615 break;
616 case 0x014:
617 dev_priv->fsb_freq = 5333;
618 break;
619 case 0x016:
620 dev_priv->fsb_freq = 5866;
621 break;
622 case 0x018:
623 dev_priv->fsb_freq = 6400;
624 break;
625 default:
626 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
627 csipll & 0x3ff);
628 dev_priv->fsb_freq = 0;
629 break;
630 }
631
632 if (dev_priv->fsb_freq == 3200) {
20e4d407 633 dev_priv->ips.c_m = 0;
c921aba8 634 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 635 dev_priv->ips.c_m = 1;
c921aba8 636 } else {
20e4d407 637 dev_priv->ips.c_m = 2;
c921aba8
DV		 638 }
639}
640
b445e3b0
ED		 641static const struct cxsr_latency cxsr_latency_table[] = {
642 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
643 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
644 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
645 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
646 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
647
648 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
649 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
650 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
651 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
652 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
653
654 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
655 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
656 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
657 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
658 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
659
660 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
661 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
662 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
663 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
664 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
665
666 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
667 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
668 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
669 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
670 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
671
672 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
673 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
674 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
675 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
676 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
677};
678
63c62275 679static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 680 int is_ddr3,
681 int fsb,
682 int mem)
683{
684 const struct cxsr_latency *latency;
685 int i;
686
687 if (fsb == 0 || mem == 0)
688 return NULL;
689
690 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
691 latency = &cxsr_latency_table[i];
692 if (is_desktop == latency->is_desktop &&
693 is_ddr3 == latency->is_ddr3 &&
694 fsb == latency->fsb_freq && mem == latency->mem_freq)
695 return latency;
696 }
697
698 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
699
700 return NULL;
701}
702
1fa61106 703static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 704{
705 struct drm_i915_private *dev_priv = dev->dev_private;
706
707 /* deactivate cxsr */
708 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
709}
710
711/*
712 * Latency for FIFO fetches is dependent on several factors:
713 * - memory configuration (speed, channels)
714 * - chipset
715 * - current MCH state
716 * It can be fairly high in some situations, so here we assume a fairly
717 * pessimal value. It's a tradeoff between extra memory fetches (if we
718 * set this value too high, the FIFO will fetch frequently to stay full)
719 * and power consumption (set it too low to save power and we might see
720 * FIFO underruns and display "flicker").
721 *
722 * A value of 5us seems to be a good balance; safe for very low end
723 * platforms but not overly aggressive on lower latency configs.
724 */
725static const int latency_ns = 5000;
726
1fa61106 727static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 728{
729 struct drm_i915_private *dev_priv = dev->dev_private;
730 uint32_t dsparb = I915_READ(DSPARB);
731 int size;
732
733 size = dsparb & 0x7f;
734 if (plane)
735 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
736
737 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
738 plane ? "B" : "A", size);
739
740 return size;
741}
742
1fa61106 743static int i85x_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 744{
745 struct drm_i915_private *dev_priv = dev->dev_private;
746 uint32_t dsparb = I915_READ(DSPARB);
747 int size;
748
749 size = dsparb & 0x1ff;
750 if (plane)
751 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
752 size >>= 1; /* Convert to cachelines */
753
754 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
755 plane ? "B" : "A", size);
756
757 return size;
758}
759
1fa61106 760static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 761{
762 struct drm_i915_private *dev_priv = dev->dev_private;
763 uint32_t dsparb = I915_READ(DSPARB);
764 int size;
765
766 size = dsparb & 0x7f;
767 size >>= 2; /* Convert to cachelines */
768
769 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
770 plane ? "B" : "A",
771 size);
772
773 return size;
774}
775
1fa61106 776static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 777{
778 struct drm_i915_private *dev_priv = dev->dev_private;
779 uint32_t dsparb = I915_READ(DSPARB);
780 int size;
781
782 size = dsparb & 0x7f;
783 size >>= 1; /* Convert to cachelines */
784
785 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
786 plane ? "B" : "A", size);
787
788 return size;
789}
790
791/* Pineview has different values for various configs */
792static const struct intel_watermark_params pineview_display_wm = {
793 PINEVIEW_DISPLAY_FIFO,
794 PINEVIEW_MAX_WM,
795 PINEVIEW_DFT_WM,
796 PINEVIEW_GUARD_WM,
797 PINEVIEW_FIFO_LINE_SIZE
798};
799static const struct intel_watermark_params pineview_display_hplloff_wm = {
800 PINEVIEW_DISPLAY_FIFO,
801 PINEVIEW_MAX_WM,
802 PINEVIEW_DFT_HPLLOFF_WM,
803 PINEVIEW_GUARD_WM,
804 PINEVIEW_FIFO_LINE_SIZE
805};
806static const struct intel_watermark_params pineview_cursor_wm = {
807 PINEVIEW_CURSOR_FIFO,
808 PINEVIEW_CURSOR_MAX_WM,
809 PINEVIEW_CURSOR_DFT_WM,
810 PINEVIEW_CURSOR_GUARD_WM,
811 PINEVIEW_FIFO_LINE_SIZE,
812};
813static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
814 PINEVIEW_CURSOR_FIFO,
815 PINEVIEW_CURSOR_MAX_WM,
816 PINEVIEW_CURSOR_DFT_WM,
817 PINEVIEW_CURSOR_GUARD_WM,
818 PINEVIEW_FIFO_LINE_SIZE
819};
820static const struct intel_watermark_params g4x_wm_info = {
821 G4X_FIFO_SIZE,
822 G4X_MAX_WM,
823 G4X_MAX_WM,
824 2,
825 G4X_FIFO_LINE_SIZE,
826};
827static const struct intel_watermark_params g4x_cursor_wm_info = {
828 I965_CURSOR_FIFO,
829 I965_CURSOR_MAX_WM,
830 I965_CURSOR_DFT_WM,
831 2,
832 G4X_FIFO_LINE_SIZE,
833};
834static const struct intel_watermark_params valleyview_wm_info = {
835 VALLEYVIEW_FIFO_SIZE,
836 VALLEYVIEW_MAX_WM,
837 VALLEYVIEW_MAX_WM,
838 2,
839 G4X_FIFO_LINE_SIZE,
840};
841static const struct intel_watermark_params valleyview_cursor_wm_info = {
842 I965_CURSOR_FIFO,
843 VALLEYVIEW_CURSOR_MAX_WM,
844 I965_CURSOR_DFT_WM,
845 2,
846 G4X_FIFO_LINE_SIZE,
847};
848static const struct intel_watermark_params i965_cursor_wm_info = {
849 I965_CURSOR_FIFO,
850 I965_CURSOR_MAX_WM,
851 I965_CURSOR_DFT_WM,
852 2,
853 I915_FIFO_LINE_SIZE,
854};
855static const struct intel_watermark_params i945_wm_info = {
856 I945_FIFO_SIZE,
857 I915_MAX_WM,
858 1,
859 2,
860 I915_FIFO_LINE_SIZE
861};
862static const struct intel_watermark_params i915_wm_info = {
863 I915_FIFO_SIZE,
864 I915_MAX_WM,
865 1,
866 2,
867 I915_FIFO_LINE_SIZE
868};
869static const struct intel_watermark_params i855_wm_info = {
870 I855GM_FIFO_SIZE,
871 I915_MAX_WM,
872 1,
873 2,
874 I830_FIFO_LINE_SIZE
875};
876static const struct intel_watermark_params i830_wm_info = {
877 I830_FIFO_SIZE,
878 I915_MAX_WM,
879 1,
880 2,
881 I830_FIFO_LINE_SIZE
882};
883
884static const struct intel_watermark_params ironlake_display_wm_info = {
885 ILK_DISPLAY_FIFO,
886 ILK_DISPLAY_MAXWM,
887 ILK_DISPLAY_DFTWM,
888 2,
889 ILK_FIFO_LINE_SIZE
890};
891static const struct intel_watermark_params ironlake_cursor_wm_info = {
892 ILK_CURSOR_FIFO,
893 ILK_CURSOR_MAXWM,
894 ILK_CURSOR_DFTWM,
895 2,
896 ILK_FIFO_LINE_SIZE
897};
898static const struct intel_watermark_params ironlake_display_srwm_info = {
899 ILK_DISPLAY_SR_FIFO,
900 ILK_DISPLAY_MAX_SRWM,
901 ILK_DISPLAY_DFT_SRWM,
902 2,
903 ILK_FIFO_LINE_SIZE
904};
905static const struct intel_watermark_params ironlake_cursor_srwm_info = {
906 ILK_CURSOR_SR_FIFO,
907 ILK_CURSOR_MAX_SRWM,
908 ILK_CURSOR_DFT_SRWM,
909 2,
910 ILK_FIFO_LINE_SIZE
911};
912
913static const struct intel_watermark_params sandybridge_display_wm_info = {
914 SNB_DISPLAY_FIFO,
915 SNB_DISPLAY_MAXWM,
916 SNB_DISPLAY_DFTWM,
917 2,
918 SNB_FIFO_LINE_SIZE
919};
920static const struct intel_watermark_params sandybridge_cursor_wm_info = {
921 SNB_CURSOR_FIFO,
922 SNB_CURSOR_MAXWM,
923 SNB_CURSOR_DFTWM,
924 2,
925 SNB_FIFO_LINE_SIZE
926};
927static const struct intel_watermark_params sandybridge_display_srwm_info = {
928 SNB_DISPLAY_SR_FIFO,
929 SNB_DISPLAY_MAX_SRWM,
930 SNB_DISPLAY_DFT_SRWM,
931 2,
932 SNB_FIFO_LINE_SIZE
933};
934static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
935 SNB_CURSOR_SR_FIFO,
936 SNB_CURSOR_MAX_SRWM,
937 SNB_CURSOR_DFT_SRWM,
938 2,
939 SNB_FIFO_LINE_SIZE
940};
941
942
943/**
944 * intel_calculate_wm - calculate watermark level
945 * @clock_in_khz: pixel clock
946 * @wm: chip FIFO params
947 * @pixel_size: display pixel size
948 * @latency_ns: memory latency for the platform
949 *
950 * Calculate the watermark level (the level at which the display plane will
951 * start fetching from memory again). Each chip has a different display
952 * FIFO size and allocation, so the caller needs to figure that out and pass
953 * in the correct intel_watermark_params structure.
954 *
955 * As the pixel clock runs, the FIFO will be drained at a rate that depends
956 * on the pixel size. When it reaches the watermark level, it'll start
957 * fetching FIFO line sized based chunks from memory until the FIFO fills
958 * past the watermark point. If the FIFO drains completely, a FIFO underrun
959 * will occur, and a display engine hang could result.
960 */
961static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
962 const struct intel_watermark_params *wm,
963 int fifo_size,
964 int pixel_size,
965 unsigned long latency_ns)
966{
967 long entries_required, wm_size;
968
969 /*
970 * Note: we need to make sure we don't overflow for various clock &
971 * latency values.
972 * clocks go from a few thousand to several hundred thousand.
973 * latency is usually a few thousand
974 */
975 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
976 1000;
977 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
978
979 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
980
981 wm_size = fifo_size - (entries_required + wm->guard_size);
982
983 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
984
985 /* Don't promote wm_size to unsigned... */
986 if (wm_size > (long)wm->max_wm)
987 wm_size = wm->max_wm;
988 if (wm_size <= 0)
989 wm_size = wm->default_wm;
990 return wm_size;
991}
992
993static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
994{
995 struct drm_crtc *crtc, *enabled = NULL;
996
997 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
f20e0b08 998 if (to_intel_crtc(crtc)->active && crtc->fb) {
b445e3b0
ED		 999 if (enabled)
1000 return NULL;
1001 enabled = crtc;
1002 }
1003 }
1004
1005 return enabled;
1006}
1007
1fa61106 1008static void pineview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1009{
1010 struct drm_i915_private *dev_priv = dev->dev_private;
1011 struct drm_crtc *crtc;
1012 const struct cxsr_latency *latency;
1013 u32 reg;
1014 unsigned long wm;
1015
1016 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1017 dev_priv->fsb_freq, dev_priv->mem_freq);
1018 if (!latency) {
1019 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1020 pineview_disable_cxsr(dev);
1021 return;
1022 }
1023
1024 crtc = single_enabled_crtc(dev);
1025 if (crtc) {
1026 int clock = crtc->mode.clock;
1027 int pixel_size = crtc->fb->bits_per_pixel / 8;
1028
1029 /* Display SR */
1030 wm = intel_calculate_wm(clock, &pineview_display_wm,
1031 pineview_display_wm.fifo_size,
1032 pixel_size, latency->display_sr);
1033 reg = I915_READ(DSPFW1);
1034 reg &= ~DSPFW_SR_MASK;
1035 reg |= wm << DSPFW_SR_SHIFT;
1036 I915_WRITE(DSPFW1, reg);
1037 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1038
1039 /* cursor SR */
1040 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1041 pineview_display_wm.fifo_size,
1042 pixel_size, latency->cursor_sr);
1043 reg = I915_READ(DSPFW3);
1044 reg &= ~DSPFW_CURSOR_SR_MASK;
1045 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1046 I915_WRITE(DSPFW3, reg);
1047
1048 /* Display HPLL off SR */
1049 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1050 pineview_display_hplloff_wm.fifo_size,
1051 pixel_size, latency->display_hpll_disable);
1052 reg = I915_READ(DSPFW3);
1053 reg &= ~DSPFW_HPLL_SR_MASK;
1054 reg |= wm & DSPFW_HPLL_SR_MASK;
1055 I915_WRITE(DSPFW3, reg);
1056
1057 /* cursor HPLL off SR */
1058 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1059 pineview_display_hplloff_wm.fifo_size,
1060 pixel_size, latency->cursor_hpll_disable);
1061 reg = I915_READ(DSPFW3);
1062 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1063 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1064 I915_WRITE(DSPFW3, reg);
1065 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1066
1067 /* activate cxsr */
1068 I915_WRITE(DSPFW3,
1069 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1070 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1071 } else {
1072 pineview_disable_cxsr(dev);
1073 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1074 }
1075}
1076
1077static bool g4x_compute_wm0(struct drm_device *dev,
1078 int plane,
1079 const struct intel_watermark_params *display,
1080 int display_latency_ns,
1081 const struct intel_watermark_params *cursor,
1082 int cursor_latency_ns,
1083 int *plane_wm,
1084 int *cursor_wm)
1085{
1086 struct drm_crtc *crtc;
1087 int htotal, hdisplay, clock, pixel_size;
1088 int line_time_us, line_count;
1089 int entries, tlb_miss;
1090
1091 crtc = intel_get_crtc_for_plane(dev, plane);
f20e0b08 1092 if (crtc->fb == NULL || !to_intel_crtc(crtc)->active) {
b445e3b0
ED		 1093 *cursor_wm = cursor->guard_size;
1094 *plane_wm = display->guard_size;
1095 return false;
1096 }
1097
1098 htotal = crtc->mode.htotal;
1099 hdisplay = crtc->mode.hdisplay;
1100 clock = crtc->mode.clock;
1101 pixel_size = crtc->fb->bits_per_pixel / 8;
1102
1103 /* Use the small buffer method to calculate plane watermark */
1104 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1105 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1106 if (tlb_miss > 0)
1107 entries += tlb_miss;
1108 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1109 *plane_wm = entries + display->guard_size;
1110 if (*plane_wm > (int)display->max_wm)
1111 *plane_wm = display->max_wm;
1112
1113 /* Use the large buffer method to calculate cursor watermark */
1114 line_time_us = ((htotal * 1000) / clock);
1115 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1116 entries = line_count * 64 * pixel_size;
1117 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1118 if (tlb_miss > 0)
1119 entries += tlb_miss;
1120 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1121 *cursor_wm = entries + cursor->guard_size;
1122 if (*cursor_wm > (int)cursor->max_wm)
1123 *cursor_wm = (int)cursor->max_wm;
1124
1125 return true;
1126}
1127
1128/*
1129 * Check the wm result.
1130 *
1131 * If any calculated watermark values is larger than the maximum value that
1132 * can be programmed into the associated watermark register, that watermark
1133 * must be disabled.
1134 */
1135static bool g4x_check_srwm(struct drm_device *dev,
1136 int display_wm, int cursor_wm,
1137 const struct intel_watermark_params *display,
1138 const struct intel_watermark_params *cursor)
1139{
1140 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1141 display_wm, cursor_wm);
1142
1143 if (display_wm > display->max_wm) {
1144 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1145 display_wm, display->max_wm);
1146 return false;
1147 }
1148
1149 if (cursor_wm > cursor->max_wm) {
1150 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1151 cursor_wm, cursor->max_wm);
1152 return false;
1153 }
1154
1155 if (!(display_wm || cursor_wm)) {
1156 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1157 return false;
1158 }
1159
1160 return true;
1161}
1162
1163static bool g4x_compute_srwm(struct drm_device *dev,
1164 int plane,
1165 int latency_ns,
1166 const struct intel_watermark_params *display,
1167 const struct intel_watermark_params *cursor,
1168 int *display_wm, int *cursor_wm)
1169{
1170 struct drm_crtc *crtc;
1171 int hdisplay, htotal, pixel_size, clock;
1172 unsigned long line_time_us;
1173 int line_count, line_size;
1174 int small, large;
1175 int entries;
1176
1177 if (!latency_ns) {
1178 *display_wm = *cursor_wm = 0;
1179 return false;
1180 }
1181
1182 crtc = intel_get_crtc_for_plane(dev, plane);
1183 hdisplay = crtc->mode.hdisplay;
1184 htotal = crtc->mode.htotal;
1185 clock = crtc->mode.clock;
1186 pixel_size = crtc->fb->bits_per_pixel / 8;
1187
1188 line_time_us = (htotal * 1000) / clock;
1189 line_count = (latency_ns / line_time_us + 1000) / 1000;
1190 line_size = hdisplay * pixel_size;
1191
1192 /* Use the minimum of the small and large buffer method for primary */
1193 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1194 large = line_count * line_size;
1195
1196 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1197 *display_wm = entries + display->guard_size;
1198
1199 /* calculate the self-refresh watermark for display cursor */
1200 entries = line_count * pixel_size * 64;
1201 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1202 *cursor_wm = entries + cursor->guard_size;
1203
1204 return g4x_check_srwm(dev,
1205 *display_wm, *cursor_wm,
1206 display, cursor);
1207}
1208
1209static bool vlv_compute_drain_latency(struct drm_device *dev,
1210 int plane,
1211 int *plane_prec_mult,
1212 int *plane_dl,
1213 int *cursor_prec_mult,
1214 int *cursor_dl)
1215{
1216 struct drm_crtc *crtc;
1217 int clock, pixel_size;
1218 int entries;
1219
1220 crtc = intel_get_crtc_for_plane(dev, plane);
f20e0b08 1221 if (crtc->fb == NULL || !to_intel_crtc(crtc)->active)
b445e3b0
ED		 1222 return false;
1223
1224 clock = crtc->mode.clock; /* VESA DOT Clock */
1225 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1226
1227 entries = (clock / 1000) * pixel_size;
1228 *plane_prec_mult = (entries > 256) ?
1229 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1230 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1231 pixel_size);
1232
1233 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1234 *cursor_prec_mult = (entries > 256) ?
1235 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1236 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1237
1238 return true;
1239}
1240
1241/*
1242 * Update drain latency registers of memory arbiter
1243 *
1244 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1245 * to be programmed. Each plane has a drain latency multiplier and a drain
1246 * latency value.
1247 */
1248
1249static void vlv_update_drain_latency(struct drm_device *dev)
1250{
1251 struct drm_i915_private *dev_priv = dev->dev_private;
1252 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1253 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1254 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1255 either 16 or 32 */
1256
1257 /* For plane A, Cursor A */
1258 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1259 &cursor_prec_mult, &cursora_dl)) {
1260 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1261 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1262 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1263 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1264
1265 I915_WRITE(VLV_DDL1, cursora_prec |
1266 (cursora_dl << DDL_CURSORA_SHIFT) |
1267 planea_prec | planea_dl);
1268 }
1269
1270 /* For plane B, Cursor B */
1271 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1272 &cursor_prec_mult, &cursorb_dl)) {
1273 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1274 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1275 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1276 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1277
1278 I915_WRITE(VLV_DDL2, cursorb_prec |
1279 (cursorb_dl << DDL_CURSORB_SHIFT) |
1280 planeb_prec | planeb_dl);
1281 }
1282}
1283
1284#define single_plane_enabled(mask) is_power_of_2(mask)
1285
1fa61106 1286static void valleyview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1287{
1288 static const int sr_latency_ns = 12000;
1289 struct drm_i915_private *dev_priv = dev->dev_private;
1290 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1291 int plane_sr, cursor_sr;
af6c4575 1292 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0
ED		 1293 unsigned int enabled = 0;
1294
1295 vlv_update_drain_latency(dev);
1296
1297 if (g4x_compute_wm0(dev, 0,
1298 &valleyview_wm_info, latency_ns,
1299 &valleyview_cursor_wm_info, latency_ns,
1300 &planea_wm, &cursora_wm))
1301 enabled |= 1;
1302
1303 if (g4x_compute_wm0(dev, 1,
1304 &valleyview_wm_info, latency_ns,
1305 &valleyview_cursor_wm_info, latency_ns,
1306 &planeb_wm, &cursorb_wm))
1307 enabled |= 2;
1308
b445e3b0
ED		 1309 if (single_plane_enabled(enabled) &&
1310 g4x_compute_srwm(dev, ffs(enabled) - 1,
1311 sr_latency_ns,
1312 &valleyview_wm_info,
1313 &valleyview_cursor_wm_info,
af6c4575
CW		 1314 &plane_sr, &ignore_cursor_sr) &&
1315 g4x_compute_srwm(dev, ffs(enabled) - 1,
1316 2*sr_latency_ns,
1317 &valleyview_wm_info,
1318 &valleyview_cursor_wm_info,
52bd02d8 1319 &ignore_plane_sr, &cursor_sr)) {
b445e3b0 1320 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
52bd02d8 1321 } else {
b445e3b0
ED		 1322 I915_WRITE(FW_BLC_SELF_VLV,
1323 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
52bd02d8
CW		 1324 plane_sr = cursor_sr = 0;
1325 }
b445e3b0
ED		 1326
1327 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1328 planea_wm, cursora_wm,
1329 planeb_wm, cursorb_wm,
1330 plane_sr, cursor_sr);
1331
1332 I915_WRITE(DSPFW1,
1333 (plane_sr << DSPFW_SR_SHIFT) |
1334 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1335 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1336 planea_wm);
1337 I915_WRITE(DSPFW2,
8c919b28 1338 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1339 (cursora_wm << DSPFW_CURSORA_SHIFT));
1340 I915_WRITE(DSPFW3,
8c919b28
CW		 1341 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1342 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
b445e3b0
ED		 1343}
1344
1fa61106 1345static void g4x_update_wm(struct drm_device *dev)
b445e3b0
ED		 1346{
1347 static const int sr_latency_ns = 12000;
1348 struct drm_i915_private *dev_priv = dev->dev_private;
1349 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1350 int plane_sr, cursor_sr;
1351 unsigned int enabled = 0;
1352
1353 if (g4x_compute_wm0(dev, 0,
1354 &g4x_wm_info, latency_ns,
1355 &g4x_cursor_wm_info, latency_ns,
1356 &planea_wm, &cursora_wm))
1357 enabled |= 1;
1358
1359 if (g4x_compute_wm0(dev, 1,
1360 &g4x_wm_info, latency_ns,
1361 &g4x_cursor_wm_info, latency_ns,
1362 &planeb_wm, &cursorb_wm))
1363 enabled |= 2;
1364
b445e3b0
ED		 1365 if (single_plane_enabled(enabled) &&
1366 g4x_compute_srwm(dev, ffs(enabled) - 1,
1367 sr_latency_ns,
1368 &g4x_wm_info,
1369 &g4x_cursor_wm_info,
52bd02d8 1370 &plane_sr, &cursor_sr)) {
b445e3b0 1371 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
52bd02d8 1372 } else {
b445e3b0
ED		 1373 I915_WRITE(FW_BLC_SELF,
1374 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
52bd02d8
CW		 1375 plane_sr = cursor_sr = 0;
1376 }
b445e3b0
ED		 1377
1378 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1379 planea_wm, cursora_wm,
1380 planeb_wm, cursorb_wm,
1381 plane_sr, cursor_sr);
1382
1383 I915_WRITE(DSPFW1,
1384 (plane_sr << DSPFW_SR_SHIFT) |
1385 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1386 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1387 planea_wm);
1388 I915_WRITE(DSPFW2,
8c919b28 1389 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1390 (cursora_wm << DSPFW_CURSORA_SHIFT));
1391 /* HPLL off in SR has some issues on G4x... disable it */
1392 I915_WRITE(DSPFW3,
8c919b28 1393 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0
ED		 1394 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1395}
1396
1fa61106 1397static void i965_update_wm(struct drm_device *dev)
b445e3b0
ED		 1398{
1399 struct drm_i915_private *dev_priv = dev->dev_private;
1400 struct drm_crtc *crtc;
1401 int srwm = 1;
1402 int cursor_sr = 16;
1403
1404 /* Calc sr entries for one plane configs */
1405 crtc = single_enabled_crtc(dev);
1406 if (crtc) {
1407 /* self-refresh has much higher latency */
1408 static const int sr_latency_ns = 12000;
1409 int clock = crtc->mode.clock;
1410 int htotal = crtc->mode.htotal;
1411 int hdisplay = crtc->mode.hdisplay;
1412 int pixel_size = crtc->fb->bits_per_pixel / 8;
1413 unsigned long line_time_us;
1414 int entries;
1415
1416 line_time_us = ((htotal * 1000) / clock);
1417
1418 /* Use ns/us then divide to preserve precision */
1419 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1420 pixel_size * hdisplay;
1421 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1422 srwm = I965_FIFO_SIZE - entries;
1423 if (srwm < 0)
1424 srwm = 1;
1425 srwm &= 0x1ff;
1426 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1427 entries, srwm);
1428
1429 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1430 pixel_size * 64;
1431 entries = DIV_ROUND_UP(entries,
1432 i965_cursor_wm_info.cacheline_size);
1433 cursor_sr = i965_cursor_wm_info.fifo_size -
1434 (entries + i965_cursor_wm_info.guard_size);
1435
1436 if (cursor_sr > i965_cursor_wm_info.max_wm)
1437 cursor_sr = i965_cursor_wm_info.max_wm;
1438
1439 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1440 "cursor %d\n", srwm, cursor_sr);
1441
1442 if (IS_CRESTLINE(dev))
1443 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1444 } else {
1445 /* Turn off self refresh if both pipes are enabled */
1446 if (IS_CRESTLINE(dev))
1447 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1448 & ~FW_BLC_SELF_EN);
1449 }
1450
1451 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1452 srwm);
1453
1454 /* 965 has limitations... */
1455 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1456 (8 << 16) | (8 << 8) | (8 << 0));
1457 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1458 /* update cursor SR watermark */
1459 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1460}
1461
1fa61106 1462static void i9xx_update_wm(struct drm_device *dev)
b445e3b0
ED		 1463{
1464 struct drm_i915_private *dev_priv = dev->dev_private;
1465 const struct intel_watermark_params *wm_info;
1466 uint32_t fwater_lo;
1467 uint32_t fwater_hi;
1468 int cwm, srwm = 1;
1469 int fifo_size;
1470 int planea_wm, planeb_wm;
1471 struct drm_crtc *crtc, *enabled = NULL;
1472
1473 if (IS_I945GM(dev))
1474 wm_info = &i945_wm_info;
1475 else if (!IS_GEN2(dev))
1476 wm_info = &i915_wm_info;
1477 else
1478 wm_info = &i855_wm_info;
1479
1480 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1481 crtc = intel_get_crtc_for_plane(dev, 0);
f20e0b08 1482 if (to_intel_crtc(crtc)->active && crtc->fb) {
b9e0bda3
CW		 1483 int cpp = crtc->fb->bits_per_pixel / 8;
1484 if (IS_GEN2(dev))
1485 cpp = 4;
1486
b445e3b0 1487 planea_wm = intel_calculate_wm(crtc->mode.clock,
b9e0bda3 1488 wm_info, fifo_size, cpp,
b445e3b0
ED		 1489 latency_ns);
1490 enabled = crtc;
1491 } else
1492 planea_wm = fifo_size - wm_info->guard_size;
1493
1494 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1495 crtc = intel_get_crtc_for_plane(dev, 1);
f20e0b08 1496 if (to_intel_crtc(crtc)->active && crtc->fb) {
b9e0bda3
CW		 1497 int cpp = crtc->fb->bits_per_pixel / 8;
1498 if (IS_GEN2(dev))
1499 cpp = 4;
1500
b445e3b0 1501 planeb_wm = intel_calculate_wm(crtc->mode.clock,
b9e0bda3 1502 wm_info, fifo_size, cpp,
b445e3b0
ED		 1503 latency_ns);
1504 if (enabled == NULL)
1505 enabled = crtc;
1506 else
1507 enabled = NULL;
1508 } else
1509 planeb_wm = fifo_size - wm_info->guard_size;
1510
1511 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1512
1513 /*
1514 * Overlay gets an aggressive default since video jitter is bad.
1515 */
1516 cwm = 2;
1517
1518 /* Play safe and disable self-refresh before adjusting watermarks. */
1519 if (IS_I945G(dev) || IS_I945GM(dev))
1520 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1521 else if (IS_I915GM(dev))
1522 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1523
1524 /* Calc sr entries for one plane configs */
1525 if (HAS_FW_BLC(dev) && enabled) {
1526 /* self-refresh has much higher latency */
1527 static const int sr_latency_ns = 6000;
1528 int clock = enabled->mode.clock;
1529 int htotal = enabled->mode.htotal;
1530 int hdisplay = enabled->mode.hdisplay;
1531 int pixel_size = enabled->fb->bits_per_pixel / 8;
1532 unsigned long line_time_us;
1533 int entries;
1534
1535 line_time_us = (htotal * 1000) / clock;
1536
1537 /* Use ns/us then divide to preserve precision */
1538 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1539 pixel_size * hdisplay;
1540 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1541 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1542 srwm = wm_info->fifo_size - entries;
1543 if (srwm < 0)
1544 srwm = 1;
1545
1546 if (IS_I945G(dev) || IS_I945GM(dev))
1547 I915_WRITE(FW_BLC_SELF,
1548 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1549 else if (IS_I915GM(dev))
1550 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1551 }
1552
1553 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1554 planea_wm, planeb_wm, cwm, srwm);
1555
1556 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1557 fwater_hi = (cwm & 0x1f);
1558
1559 /* Set request length to 8 cachelines per fetch */
1560 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1561 fwater_hi = fwater_hi | (1 << 8);
1562
1563 I915_WRITE(FW_BLC, fwater_lo);
1564 I915_WRITE(FW_BLC2, fwater_hi);
1565
1566 if (HAS_FW_BLC(dev)) {
1567 if (enabled) {
1568 if (IS_I945G(dev) || IS_I945GM(dev))
1569 I915_WRITE(FW_BLC_SELF,
1570 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1571 else if (IS_I915GM(dev))
1572 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1573 DRM_DEBUG_KMS("memory self refresh enabled\n");
1574 } else
1575 DRM_DEBUG_KMS("memory self refresh disabled\n");
1576 }
1577}
1578
1fa61106 1579static void i830_update_wm(struct drm_device *dev)
b445e3b0
ED		 1580{
1581 struct drm_i915_private *dev_priv = dev->dev_private;
1582 struct drm_crtc *crtc;
1583 uint32_t fwater_lo;
1584 int planea_wm;
1585
1586 crtc = single_enabled_crtc(dev);
1587 if (crtc == NULL)
1588 return;
1589
1590 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1591 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1592 4, latency_ns);
b445e3b0
ED		 1593 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1594 fwater_lo |= (3<<8) | planea_wm;
1595
1596 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1597
1598 I915_WRITE(FW_BLC, fwater_lo);
1599}
1600
1601#define ILK_LP0_PLANE_LATENCY 700
1602#define ILK_LP0_CURSOR_LATENCY 1300
1603
1604/*
1605 * Check the wm result.
1606 *
1607 * If any calculated watermark values is larger than the maximum value that
1608 * can be programmed into the associated watermark register, that watermark
1609 * must be disabled.
1610 */
1611static bool ironlake_check_srwm(struct drm_device *dev, int level,
1612 int fbc_wm, int display_wm, int cursor_wm,
1613 const struct intel_watermark_params *display,
1614 const struct intel_watermark_params *cursor)
1615{
1616 struct drm_i915_private *dev_priv = dev->dev_private;
1617
1618 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1619 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1620
1621 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1622 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1623 fbc_wm, SNB_FBC_MAX_SRWM, level);
1624
1625 /* fbc has it's own way to disable FBC WM */
1626 I915_WRITE(DISP_ARB_CTL,
1627 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1628 return false;
1629 }
1630
1631 if (display_wm > display->max_wm) {
1632 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1633 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1634 return false;
1635 }
1636
1637 if (cursor_wm > cursor->max_wm) {
1638 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1639 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1640 return false;
1641 }
1642
1643 if (!(fbc_wm || display_wm || cursor_wm)) {
1644 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1645 return false;
1646 }
1647
1648 return true;
1649}
1650
1651/*
1652 * Compute watermark values of WM[1-3],
1653 */
1654static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1655 int latency_ns,
1656 const struct intel_watermark_params *display,
1657 const struct intel_watermark_params *cursor,
1658 int *fbc_wm, int *display_wm, int *cursor_wm)
1659{
1660 struct drm_crtc *crtc;
1661 unsigned long line_time_us;
1662 int hdisplay, htotal, pixel_size, clock;
1663 int line_count, line_size;
1664 int small, large;
1665 int entries;
1666
1667 if (!latency_ns) {
1668 *fbc_wm = *display_wm = *cursor_wm = 0;
1669 return false;
1670 }
1671
1672 crtc = intel_get_crtc_for_plane(dev, plane);
1673 hdisplay = crtc->mode.hdisplay;
1674 htotal = crtc->mode.htotal;
1675 clock = crtc->mode.clock;
1676 pixel_size = crtc->fb->bits_per_pixel / 8;
1677
1678 line_time_us = (htotal * 1000) / clock;
1679 line_count = (latency_ns / line_time_us + 1000) / 1000;
1680 line_size = hdisplay * pixel_size;
1681
1682 /* Use the minimum of the small and large buffer method for primary */
1683 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1684 large = line_count * line_size;
1685
1686 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1687 *display_wm = entries + display->guard_size;
1688
1689 /*
1690 * Spec says:
1691 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1692 */
1693 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1694
1695 /* calculate the self-refresh watermark for display cursor */
1696 entries = line_count * pixel_size * 64;
1697 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1698 *cursor_wm = entries + cursor->guard_size;
1699
1700 return ironlake_check_srwm(dev, level,
1701 *fbc_wm, *display_wm, *cursor_wm,
1702 display, cursor);
1703}
1704
1fa61106 1705static void ironlake_update_wm(struct drm_device *dev)
b445e3b0
ED		 1706{
1707 struct drm_i915_private *dev_priv = dev->dev_private;
1708 int fbc_wm, plane_wm, cursor_wm;
1709 unsigned int enabled;
1710
1711 enabled = 0;
1712 if (g4x_compute_wm0(dev, 0,
1713 &ironlake_display_wm_info,
1714 ILK_LP0_PLANE_LATENCY,
1715 &ironlake_cursor_wm_info,
1716 ILK_LP0_CURSOR_LATENCY,
1717 &plane_wm, &cursor_wm)) {
1718 I915_WRITE(WM0_PIPEA_ILK,
1719 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1720 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1721 " plane %d, " "cursor: %d\n",
1722 plane_wm, cursor_wm);
1723 enabled |= 1;
1724 }
1725
1726 if (g4x_compute_wm0(dev, 1,
1727 &ironlake_display_wm_info,
1728 ILK_LP0_PLANE_LATENCY,
1729 &ironlake_cursor_wm_info,
1730 ILK_LP0_CURSOR_LATENCY,
1731 &plane_wm, &cursor_wm)) {
1732 I915_WRITE(WM0_PIPEB_ILK,
1733 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1734 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1735 " plane %d, cursor: %d\n",
1736 plane_wm, cursor_wm);
1737 enabled |= 2;
1738 }
1739
1740 /*
1741 * Calculate and update the self-refresh watermark only when one
1742 * display plane is used.
1743 */
1744 I915_WRITE(WM3_LP_ILK, 0);
1745 I915_WRITE(WM2_LP_ILK, 0);
1746 I915_WRITE(WM1_LP_ILK, 0);
1747
1748 if (!single_plane_enabled(enabled))
1749 return;
1750 enabled = ffs(enabled) - 1;
1751
1752 /* WM1 */
1753 if (!ironlake_compute_srwm(dev, 1, enabled,
1754 ILK_READ_WM1_LATENCY() * 500,
1755 &ironlake_display_srwm_info,
1756 &ironlake_cursor_srwm_info,
1757 &fbc_wm, &plane_wm, &cursor_wm))
1758 return;
1759
1760 I915_WRITE(WM1_LP_ILK,
1761 WM1_LP_SR_EN |
1762 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1763 (fbc_wm << WM1_LP_FBC_SHIFT) |
1764 (plane_wm << WM1_LP_SR_SHIFT) |
1765 cursor_wm);
1766
1767 /* WM2 */
1768 if (!ironlake_compute_srwm(dev, 2, enabled,
1769 ILK_READ_WM2_LATENCY() * 500,
1770 &ironlake_display_srwm_info,
1771 &ironlake_cursor_srwm_info,
1772 &fbc_wm, &plane_wm, &cursor_wm))
1773 return;
1774
1775 I915_WRITE(WM2_LP_ILK,
1776 WM2_LP_EN |
1777 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1778 (fbc_wm << WM1_LP_FBC_SHIFT) |
1779 (plane_wm << WM1_LP_SR_SHIFT) |
1780 cursor_wm);
1781
1782 /*
1783 * WM3 is unsupported on ILK, probably because we don't have latency
1784 * data for that power state
1785 */
1786}
1787
1fa61106 1788static void sandybridge_update_wm(struct drm_device *dev)
b445e3b0
ED		 1789{
1790 struct drm_i915_private *dev_priv = dev->dev_private;
1791 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1792 u32 val;
1793 int fbc_wm, plane_wm, cursor_wm;
1794 unsigned int enabled;
1795
1796 enabled = 0;
1797 if (g4x_compute_wm0(dev, 0,
1798 &sandybridge_display_wm_info, latency,
1799 &sandybridge_cursor_wm_info, latency,
1800 &plane_wm, &cursor_wm)) {
1801 val = I915_READ(WM0_PIPEA_ILK);
1802 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1803 I915_WRITE(WM0_PIPEA_ILK, val |
1804 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1805 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1806 " plane %d, " "cursor: %d\n",
1807 plane_wm, cursor_wm);
1808 enabled |= 1;
1809 }
1810
1811 if (g4x_compute_wm0(dev, 1,
1812 &sandybridge_display_wm_info, latency,
1813 &sandybridge_cursor_wm_info, latency,
1814 &plane_wm, &cursor_wm)) {
1815 val = I915_READ(WM0_PIPEB_ILK);
1816 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1817 I915_WRITE(WM0_PIPEB_ILK, val |
1818 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1819 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1820 " plane %d, cursor: %d\n",
1821 plane_wm, cursor_wm);
1822 enabled |= 2;
1823 }
1824
c43d0188
CW		 1825 /*
1826 * Calculate and update the self-refresh watermark only when one
1827 * display plane is used.
1828 *
1829 * SNB support 3 levels of watermark.
1830 *
1831 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1832 * and disabled in the descending order
1833 *
1834 */
1835 I915_WRITE(WM3_LP_ILK, 0);
1836 I915_WRITE(WM2_LP_ILK, 0);
1837 I915_WRITE(WM1_LP_ILK, 0);
1838
1839 if (!single_plane_enabled(enabled) ||
1840 dev_priv->sprite_scaling_enabled)
1841 return;
1842 enabled = ffs(enabled) - 1;
1843
1844 /* WM1 */
1845 if (!ironlake_compute_srwm(dev, 1, enabled,
1846 SNB_READ_WM1_LATENCY() * 500,
1847 &sandybridge_display_srwm_info,
1848 &sandybridge_cursor_srwm_info,
1849 &fbc_wm, &plane_wm, &cursor_wm))
1850 return;
1851
1852 I915_WRITE(WM1_LP_ILK,
1853 WM1_LP_SR_EN |
1854 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1855 (fbc_wm << WM1_LP_FBC_SHIFT) |
1856 (plane_wm << WM1_LP_SR_SHIFT) |
1857 cursor_wm);
1858
1859 /* WM2 */
1860 if (!ironlake_compute_srwm(dev, 2, enabled,
1861 SNB_READ_WM2_LATENCY() * 500,
1862 &sandybridge_display_srwm_info,
1863 &sandybridge_cursor_srwm_info,
1864 &fbc_wm, &plane_wm, &cursor_wm))
1865 return;
1866
1867 I915_WRITE(WM2_LP_ILK,
1868 WM2_LP_EN |
1869 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1870 (fbc_wm << WM1_LP_FBC_SHIFT) |
1871 (plane_wm << WM1_LP_SR_SHIFT) |
1872 cursor_wm);
1873
1874 /* WM3 */
1875 if (!ironlake_compute_srwm(dev, 3, enabled,
1876 SNB_READ_WM3_LATENCY() * 500,
1877 &sandybridge_display_srwm_info,
1878 &sandybridge_cursor_srwm_info,
1879 &fbc_wm, &plane_wm, &cursor_wm))
1880 return;
1881
1882 I915_WRITE(WM3_LP_ILK,
1883 WM3_LP_EN |
1884 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1885 (fbc_wm << WM1_LP_FBC_SHIFT) |
1886 (plane_wm << WM1_LP_SR_SHIFT) |
1887 cursor_wm);
1888}
1889
1890static void ivybridge_update_wm(struct drm_device *dev)
1891{
1892 struct drm_i915_private *dev_priv = dev->dev_private;
1893 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1894 u32 val;
1895 int fbc_wm, plane_wm, cursor_wm;
1896 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
1897 unsigned int enabled;
1898
1899 enabled = 0;
1900 if (g4x_compute_wm0(dev, 0,
1901 &sandybridge_display_wm_info, latency,
1902 &sandybridge_cursor_wm_info, latency,
1903 &plane_wm, &cursor_wm)) {
1904 val = I915_READ(WM0_PIPEA_ILK);
1905 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1906 I915_WRITE(WM0_PIPEA_ILK, val |
1907 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1908 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1909 " plane %d, " "cursor: %d\n",
1910 plane_wm, cursor_wm);
1911 enabled |= 1;
1912 }
1913
1914 if (g4x_compute_wm0(dev, 1,
1915 &sandybridge_display_wm_info, latency,
1916 &sandybridge_cursor_wm_info, latency,
1917 &plane_wm, &cursor_wm)) {
1918 val = I915_READ(WM0_PIPEB_ILK);
1919 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1920 I915_WRITE(WM0_PIPEB_ILK, val |
1921 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1922 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1923 " plane %d, cursor: %d\n",
1924 plane_wm, cursor_wm);
1925 enabled |= 2;
1926 }
1927
1928 if (g4x_compute_wm0(dev, 2,
b445e3b0
ED		 1929 &sandybridge_display_wm_info, latency,
1930 &sandybridge_cursor_wm_info, latency,
1931 &plane_wm, &cursor_wm)) {
1932 val = I915_READ(WM0_PIPEC_IVB);
1933 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1934 I915_WRITE(WM0_PIPEC_IVB, val |
1935 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1936 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
1937 " plane %d, cursor: %d\n",
1938 plane_wm, cursor_wm);
1939 enabled |= 3;
1940 }
1941
1942 /*
1943 * Calculate and update the self-refresh watermark only when one
1944 * display plane is used.
1945 *
1946 * SNB support 3 levels of watermark.
1947 *
1948 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1949 * and disabled in the descending order
1950 *
1951 */
1952 I915_WRITE(WM3_LP_ILK, 0);
1953 I915_WRITE(WM2_LP_ILK, 0);
1954 I915_WRITE(WM1_LP_ILK, 0);
1955
1956 if (!single_plane_enabled(enabled) ||
1957 dev_priv->sprite_scaling_enabled)
1958 return;
1959 enabled = ffs(enabled) - 1;
1960
1961 /* WM1 */
1962 if (!ironlake_compute_srwm(dev, 1, enabled,
1963 SNB_READ_WM1_LATENCY() * 500,
1964 &sandybridge_display_srwm_info,
1965 &sandybridge_cursor_srwm_info,
1966 &fbc_wm, &plane_wm, &cursor_wm))
1967 return;
1968
1969 I915_WRITE(WM1_LP_ILK,
1970 WM1_LP_SR_EN |
1971 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1972 (fbc_wm << WM1_LP_FBC_SHIFT) |
1973 (plane_wm << WM1_LP_SR_SHIFT) |
1974 cursor_wm);
1975
1976 /* WM2 */
1977 if (!ironlake_compute_srwm(dev, 2, enabled,
1978 SNB_READ_WM2_LATENCY() * 500,
1979 &sandybridge_display_srwm_info,
1980 &sandybridge_cursor_srwm_info,
1981 &fbc_wm, &plane_wm, &cursor_wm))
1982 return;
1983
1984 I915_WRITE(WM2_LP_ILK,
1985 WM2_LP_EN |
1986 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1987 (fbc_wm << WM1_LP_FBC_SHIFT) |
1988 (plane_wm << WM1_LP_SR_SHIFT) |
1989 cursor_wm);
1990
c43d0188 1991 /* WM3, note we have to correct the cursor latency */
b445e3b0
ED		 1992 if (!ironlake_compute_srwm(dev, 3, enabled,
1993 SNB_READ_WM3_LATENCY() * 500,
1994 &sandybridge_display_srwm_info,
1995 &sandybridge_cursor_srwm_info,
c43d0188
CW		 1996 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
1997 !ironlake_compute_srwm(dev, 3, enabled,
1998 2 * SNB_READ_WM3_LATENCY() * 500,
1999 &sandybridge_display_srwm_info,
2000 &sandybridge_cursor_srwm_info,
2001 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
b445e3b0
ED		 2002 return;
2003
2004 I915_WRITE(WM3_LP_ILK,
2005 WM3_LP_EN |
2006 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2007 (fbc_wm << WM1_LP_FBC_SHIFT) |
2008 (plane_wm << WM1_LP_SR_SHIFT) |
2009 cursor_wm);
2010}
2011
1f8eeabf
ED		 2012static void
2013haswell_update_linetime_wm(struct drm_device *dev, int pipe,
2014 struct drm_display_mode *mode)
2015{
2016 struct drm_i915_private *dev_priv = dev->dev_private;
2017 u32 temp;
2018
2019 temp = I915_READ(PIPE_WM_LINETIME(pipe));
2020 temp &= ~PIPE_WM_LINETIME_MASK;
2021
2022 /* The WM are computed with base on how long it takes to fill a single
2023 * row at the given clock rate, multiplied by 8.
2024 * */
2025 temp |= PIPE_WM_LINETIME_TIME(
2026 ((mode->crtc_hdisplay * 1000) / mode->clock) * 8);
2027
2028 /* IPS watermarks are only used by pipe A, and are ignored by
2029 * pipes B and C. They are calculated similarly to the common
2030 * linetime values, except that we are using CD clock frequency
2031 * in MHz instead of pixel rate for the division.
2032 *
2033 * This is a placeholder for the IPS watermark calculation code.
2034 */
2035
2036 I915_WRITE(PIPE_WM_LINETIME(pipe), temp);
2037}
2038
b445e3b0
ED		 2039static bool
2040sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2041 uint32_t sprite_width, int pixel_size,
2042 const struct intel_watermark_params *display,
2043 int display_latency_ns, int *sprite_wm)
2044{
2045 struct drm_crtc *crtc;
2046 int clock;
2047 int entries, tlb_miss;
2048
2049 crtc = intel_get_crtc_for_plane(dev, plane);
f20e0b08 2050 if (crtc->fb == NULL || !to_intel_crtc(crtc)->active) {
b445e3b0
ED		 2051 *sprite_wm = display->guard_size;
2052 return false;
2053 }
2054
2055 clock = crtc->mode.clock;
2056
2057 /* Use the small buffer method to calculate the sprite watermark */
2058 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2059 tlb_miss = display->fifo_size*display->cacheline_size -
2060 sprite_width * 8;
2061 if (tlb_miss > 0)
2062 entries += tlb_miss;
2063 entries = DIV_ROUND_UP(entries, display->cacheline_size);
2064 *sprite_wm = entries + display->guard_size;
2065 if (*sprite_wm > (int)display->max_wm)
2066 *sprite_wm = display->max_wm;
2067
2068 return true;
2069}
2070
2071static bool
2072sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2073 uint32_t sprite_width, int pixel_size,
2074 const struct intel_watermark_params *display,
2075 int latency_ns, int *sprite_wm)
2076{
2077 struct drm_crtc *crtc;
2078 unsigned long line_time_us;
2079 int clock;
2080 int line_count, line_size;
2081 int small, large;
2082 int entries;
2083
2084 if (!latency_ns) {
2085 *sprite_wm = 0;
2086 return false;
2087 }
2088
2089 crtc = intel_get_crtc_for_plane(dev, plane);
2090 clock = crtc->mode.clock;
2091 if (!clock) {
2092 *sprite_wm = 0;
2093 return false;
2094 }
2095
2096 line_time_us = (sprite_width * 1000) / clock;
2097 if (!line_time_us) {
2098 *sprite_wm = 0;
2099 return false;
2100 }
2101
2102 line_count = (latency_ns / line_time_us + 1000) / 1000;
2103 line_size = sprite_width * pixel_size;
2104
2105 /* Use the minimum of the small and large buffer method for primary */
2106 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2107 large = line_count * line_size;
2108
2109 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2110 *sprite_wm = entries + display->guard_size;
2111
2112 return *sprite_wm > 0x3ff ? false : true;
2113}
2114
1fa61106 2115static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
b445e3b0
ED		 2116 uint32_t sprite_width, int pixel_size)
2117{
2118 struct drm_i915_private *dev_priv = dev->dev_private;
2119 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
2120 u32 val;
2121 int sprite_wm, reg;
2122 int ret;
2123
2124 switch (pipe) {
2125 case 0:
2126 reg = WM0_PIPEA_ILK;
2127 break;
2128 case 1:
2129 reg = WM0_PIPEB_ILK;
2130 break;
2131 case 2:
2132 reg = WM0_PIPEC_IVB;
2133 break;
2134 default:
2135 return; /* bad pipe */
2136 }
2137
2138 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2139 &sandybridge_display_wm_info,
2140 latency, &sprite_wm);
2141 if (!ret) {
2142 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
2143 pipe);
2144 return;
2145 }
2146
2147 val = I915_READ(reg);
2148 val &= ~WM0_PIPE_SPRITE_MASK;
2149 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
2150 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
2151
2152
2153 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2154 pixel_size,
2155 &sandybridge_display_srwm_info,
2156 SNB_READ_WM1_LATENCY() * 500,
2157 &sprite_wm);
2158 if (!ret) {
2159 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
2160 pipe);
2161 return;
2162 }
2163 I915_WRITE(WM1S_LP_ILK, sprite_wm);
2164
2165 /* Only IVB has two more LP watermarks for sprite */
2166 if (!IS_IVYBRIDGE(dev))
2167 return;
2168
2169 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2170 pixel_size,
2171 &sandybridge_display_srwm_info,
2172 SNB_READ_WM2_LATENCY() * 500,
2173 &sprite_wm);
2174 if (!ret) {
2175 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
2176 pipe);
2177 return;
2178 }
2179 I915_WRITE(WM2S_LP_IVB, sprite_wm);
2180
2181 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2182 pixel_size,
2183 &sandybridge_display_srwm_info,
2184 SNB_READ_WM3_LATENCY() * 500,
2185 &sprite_wm);
2186 if (!ret) {
2187 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
2188 pipe);
2189 return;
2190 }
2191 I915_WRITE(WM3S_LP_IVB, sprite_wm);
2192}
2193
2194/**
2195 * intel_update_watermarks - update FIFO watermark values based on current modes
2196 *
2197 * Calculate watermark values for the various WM regs based on current mode
2198 * and plane configuration.
2199 *
2200 * There are several cases to deal with here:
2201 * - normal (i.e. non-self-refresh)
2202 * - self-refresh (SR) mode
2203 * - lines are large relative to FIFO size (buffer can hold up to 2)
2204 * - lines are small relative to FIFO size (buffer can hold more than 2
2205 * lines), so need to account for TLB latency
2206 *
2207 * The normal calculation is:
2208 * watermark = dotclock * bytes per pixel * latency
2209 * where latency is platform & configuration dependent (we assume pessimal
2210 * values here).
2211 *
2212 * The SR calculation is:
2213 * watermark = (trunc(latency/line time)+1) * surface width *
2214 * bytes per pixel
2215 * where
2216 * line time = htotal / dotclock
2217 * surface width = hdisplay for normal plane and 64 for cursor
2218 * and latency is assumed to be high, as above.
2219 *
2220 * The final value programmed to the register should always be rounded up,
2221 * and include an extra 2 entries to account for clock crossings.
2222 *
2223 * We don't use the sprite, so we can ignore that. And on Crestline we have
2224 * to set the non-SR watermarks to 8.
2225 */
2226void intel_update_watermarks(struct drm_device *dev)
2227{
2228 struct drm_i915_private *dev_priv = dev->dev_private;
2229
2230 if (dev_priv->display.update_wm)
2231 dev_priv->display.update_wm(dev);
2232}
2233
1f8eeabf
ED		 2234void intel_update_linetime_watermarks(struct drm_device *dev,
2235 int pipe, struct drm_display_mode *mode)
2236{
2237 struct drm_i915_private *dev_priv = dev->dev_private;
2238
2239 if (dev_priv->display.update_linetime_wm)
2240 dev_priv->display.update_linetime_wm(dev, pipe, mode);
2241}
2242
b445e3b0
ED		 2243void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
2244 uint32_t sprite_width, int pixel_size)
2245{
2246 struct drm_i915_private *dev_priv = dev->dev_private;
2247
2248 if (dev_priv->display.update_sprite_wm)
2249 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
2250 pixel_size);
2251}
2252
2b4e57bd
ED		 2253static struct drm_i915_gem_object *
2254intel_alloc_context_page(struct drm_device *dev)
2255{
2256 struct drm_i915_gem_object *ctx;
2257 int ret;
2258
2259 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2260
2261 ctx = i915_gem_alloc_object(dev, 4096);
2262 if (!ctx) {
2263 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2264 return NULL;
2265 }
2266
86a1ee26 2267 ret = i915_gem_object_pin(ctx, 4096, true, false);
2b4e57bd
ED		 2268 if (ret) {
2269 DRM_ERROR("failed to pin power context: %d\n", ret);
2270 goto err_unref;
2271 }
2272
2273 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2274 if (ret) {
2275 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2276 goto err_unpin;
2277 }
2278
2279 return ctx;
2280
2281err_unpin:
2282 i915_gem_object_unpin(ctx);
2283err_unref:
2284 drm_gem_object_unreference(&ctx->base);
2285 mutex_unlock(&dev->struct_mutex);
2286 return NULL;
2287}
2288
9270388e
DV		 2289/**
2290 * Lock protecting IPS related data structures
9270388e
DV		 2291 */
2292DEFINE_SPINLOCK(mchdev_lock);
2293
2294/* Global for IPS driver to get at the current i915 device. Protected by
2295 * mchdev_lock. */
2296static struct drm_i915_private *i915_mch_dev;
2297
2b4e57bd
ED		 2298bool ironlake_set_drps(struct drm_device *dev, u8 val)
2299{
2300 struct drm_i915_private *dev_priv = dev->dev_private;
2301 u16 rgvswctl;
2302
9270388e
DV		 2303 assert_spin_locked(&mchdev_lock);
2304
2b4e57bd
ED		 2305 rgvswctl = I915_READ16(MEMSWCTL);
2306 if (rgvswctl & MEMCTL_CMD_STS) {
2307 DRM_DEBUG("gpu busy, RCS change rejected\n");
2308 return false; /* still busy with another command */
2309 }
2310
2311 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2312 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2313 I915_WRITE16(MEMSWCTL, rgvswctl);
2314 POSTING_READ16(MEMSWCTL);
2315
2316 rgvswctl |= MEMCTL_CMD_STS;
2317 I915_WRITE16(MEMSWCTL, rgvswctl);
2318
2319 return true;
2320}
2321
8090c6b9 2322static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 2323{
2324 struct drm_i915_private *dev_priv = dev->dev_private;
2325 u32 rgvmodectl = I915_READ(MEMMODECTL);
2326 u8 fmax, fmin, fstart, vstart;
2327
9270388e
DV		 2328 spin_lock_irq(&mchdev_lock);
2329
2b4e57bd
ED		 2330 /* Enable temp reporting */
2331 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2332 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2333
2334 /* 100ms RC evaluation intervals */
2335 I915_WRITE(RCUPEI, 100000);
2336 I915_WRITE(RCDNEI, 100000);
2337
2338 /* Set max/min thresholds to 90ms and 80ms respectively */
2339 I915_WRITE(RCBMAXAVG, 90000);
2340 I915_WRITE(RCBMINAVG, 80000);
2341
2342 I915_WRITE(MEMIHYST, 1);
2343
2344 /* Set up min, max, and cur for interrupt handling */
2345 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2346 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2347 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2348 MEMMODE_FSTART_SHIFT;
2349
2350 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2351 PXVFREQ_PX_SHIFT;
2352
20e4d407
DV		 2353 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2354 dev_priv->ips.fstart = fstart;
2b4e57bd 2355
20e4d407
DV		 2356 dev_priv->ips.max_delay = fstart;
2357 dev_priv->ips.min_delay = fmin;
2358 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 2359
2360 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2361 fmax, fmin, fstart);
2362
2363 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2364
2365 /*
2366 * Interrupts will be enabled in ironlake_irq_postinstall
2367 */
2368
2369 I915_WRITE(VIDSTART, vstart);
2370 POSTING_READ(VIDSTART);
2371
2372 rgvmodectl |= MEMMODE_SWMODE_EN;
2373 I915_WRITE(MEMMODECTL, rgvmodectl);
2374
9270388e 2375 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 2376 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 2377 mdelay(1);
2b4e57bd
ED		 2378
2379 ironlake_set_drps(dev, fstart);
2380
20e4d407 2381 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 2382 I915_READ(0x112e0);
20e4d407
DV		 2383 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2384 dev_priv->ips.last_count2 = I915_READ(0x112f4);
2385 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 2386
2387 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2388}
2389
8090c6b9 2390static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 2391{
2392 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 2393 u16 rgvswctl;
2394
2395 spin_lock_irq(&mchdev_lock);
2396
2397 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 2398
2399 /* Ack interrupts, disable EFC interrupt */
2400 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2401 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2402 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2403 I915_WRITE(DEIIR, DE_PCU_EVENT);
2404 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2405
2406 /* Go back to the starting frequency */
20e4d407 2407 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 2408 mdelay(1);
2b4e57bd
ED		 2409 rgvswctl |= MEMCTL_CMD_STS;
2410 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 2411 mdelay(1);
2b4e57bd 2412
9270388e 2413 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2414}
2415
acbe9475
DV		 2416/* There's a funny hw issue where the hw returns all 0 when reading from
2417 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2418 * ourselves, instead of doing a rmw cycle (which might result in us clearing
2419 * all limits and the gpu stuck at whatever frequency it is at atm).
2420 */
65bccb5c 2421static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2b4e57bd 2422{
7b9e0ae6 2423 u32 limits;
2b4e57bd 2424
7b9e0ae6 2425 limits = 0;
c6a828d3
DV		 2426
2427 if (*val >= dev_priv->rps.max_delay)
2428 *val = dev_priv->rps.max_delay;
2429 limits |= dev_priv->rps.max_delay << 24;
20b46e59
DV		 2430
2431 /* Only set the down limit when we've reached the lowest level to avoid
2432 * getting more interrupts, otherwise leave this clear. This prevents a
2433 * race in the hw when coming out of rc6: There's a tiny window where
2434 * the hw runs at the minimal clock before selecting the desired
2435 * frequency, if the down threshold expires in that window we will not
2436 * receive a down interrupt. */
c6a828d3
DV		 2437 if (*val <= dev_priv->rps.min_delay) {
2438 *val = dev_priv->rps.min_delay;
2439 limits |= dev_priv->rps.min_delay << 16;
20b46e59
DV		 2440 }
2441
2442 return limits;
2443}
2444
2445void gen6_set_rps(struct drm_device *dev, u8 val)
2446{
2447 struct drm_i915_private *dev_priv = dev->dev_private;
65bccb5c 2448 u32 limits = gen6_rps_limits(dev_priv, &val);
7b9e0ae6 2449
4fc688ce 2450 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79249636
BW		 2451 WARN_ON(val > dev_priv->rps.max_delay);
2452 WARN_ON(val < dev_priv->rps.min_delay);
004777cb 2453
c6a828d3 2454 if (val == dev_priv->rps.cur_delay)
7b9e0ae6
CW		 2455 return;
2456
2457 I915_WRITE(GEN6_RPNSWREQ,
2458 GEN6_FREQUENCY(val) |
2459 GEN6_OFFSET(0) |
2460 GEN6_AGGRESSIVE_TURBO);
2461
2462 /* Make sure we continue to get interrupts
2463 * until we hit the minimum or maximum frequencies.
2464 */
2465 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2466
d5570a72
BW		 2467 POSTING_READ(GEN6_RPNSWREQ);
2468
c6a828d3 2469 dev_priv->rps.cur_delay = val;
be2cde9a
DV		 2470
2471 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 2472}
2473
8090c6b9 2474static void gen6_disable_rps(struct drm_device *dev)
2b4e57bd
ED		 2475{
2476 struct drm_i915_private *dev_priv = dev->dev_private;
2477
88509484 2478 I915_WRITE(GEN6_RC_CONTROL, 0);
2b4e57bd
ED		 2479 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2480 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2481 I915_WRITE(GEN6_PMIER, 0);
2482 /* Complete PM interrupt masking here doesn't race with the rps work
2483 * item again unmasking PM interrupts because that is using a different
2484 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2485 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2486
c6a828d3
DV		 2487 spin_lock_irq(&dev_priv->rps.lock);
2488 dev_priv->rps.pm_iir = 0;
2489 spin_unlock_irq(&dev_priv->rps.lock);
2b4e57bd
ED		 2490
2491 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2492}
2493
2494int intel_enable_rc6(const struct drm_device *dev)
2495{
456470eb 2496 /* Respect the kernel parameter if it is set */
2b4e57bd
ED		 2497 if (i915_enable_rc6 >= 0)
2498 return i915_enable_rc6;
2499
6567d748
CW		 2500 /* Disable RC6 on Ironlake */
2501 if (INTEL_INFO(dev)->gen == 5)
2502 return 0;
2b4e57bd 2503
456470eb
DV		 2504 if (IS_HASWELL(dev)) {
2505 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
4a637c2c 2506 return INTEL_RC6_ENABLE;
456470eb 2507 }
2b4e57bd 2508
456470eb 2509 /* snb/ivb have more than one rc6 state. */
2b4e57bd
ED		 2510 if (INTEL_INFO(dev)->gen == 6) {
2511 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
2512 return INTEL_RC6_ENABLE;
2513 }
456470eb 2514
2b4e57bd
ED		 2515 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
2516 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
2517}
2518
79f5b2c7 2519static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 2520{
79f5b2c7 2521 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 2522 struct intel_ring_buffer *ring;
7b9e0ae6
CW		 2523 u32 rp_state_cap;
2524 u32 gt_perf_status;
31643d54 2525 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2b4e57bd 2526 u32 gtfifodbg;
2b4e57bd 2527 int rc6_mode;
42c0526c 2528 int i, ret;
2b4e57bd 2529
4fc688ce 2530 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 2531
2b4e57bd
ED		 2532 /* Here begins a magic sequence of register writes to enable
2533 * auto-downclocking.
2534 *
2535 * Perhaps there might be some value in exposing these to
2536 * userspace...
2537 */
2538 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 2539
2540 /* Clear the DBG now so we don't confuse earlier errors */
2541 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
2542 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
2543 I915_WRITE(GTFIFODBG, gtfifodbg);
2544 }
2545
2546 gen6_gt_force_wake_get(dev_priv);
2547
7b9e0ae6
CW		 2548 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
2549 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
2550
2551 /* In units of 100MHz */
c6a828d3
DV		 2552 dev_priv->rps.max_delay = rp_state_cap & 0xff;
2553 dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
2554 dev_priv->rps.cur_delay = 0;
7b9e0ae6 2555
2b4e57bd
ED		 2556 /* disable the counters and set deterministic thresholds */
2557 I915_WRITE(GEN6_RC_CONTROL, 0);
2558
2559 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
2560 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
2561 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
2562 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
2563 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
2564
b4519513
CW		 2565 for_each_ring(ring, dev_priv, i)
2566 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 2567
2568 I915_WRITE(GEN6_RC_SLEEP, 0);
2569 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
2570 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
2571 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
2572 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
2573
5a7dc92a 2574 /* Check if we are enabling RC6 */
2b4e57bd
ED		 2575 rc6_mode = intel_enable_rc6(dev_priv->dev);
2576 if (rc6_mode & INTEL_RC6_ENABLE)
2577 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
2578
5a7dc92a
ED		 2579 /* We don't use those on Haswell */
2580 if (!IS_HASWELL(dev)) {
2581 if (rc6_mode & INTEL_RC6p_ENABLE)
2582 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 2583
5a7dc92a
ED		 2584 if (rc6_mode & INTEL_RC6pp_ENABLE)
2585 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
2586 }
2b4e57bd
ED		 2587
2588 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
5a7dc92a
ED		 2589 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
2590 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
2591 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2b4e57bd
ED		 2592
2593 I915_WRITE(GEN6_RC_CONTROL,
2594 rc6_mask |
2595 GEN6_RC_CTL_EI_MODE(1) |
2596 GEN6_RC_CTL_HW_ENABLE);
2597
2598 I915_WRITE(GEN6_RPNSWREQ,
2599 GEN6_FREQUENCY(10) |
2600 GEN6_OFFSET(0) |
2601 GEN6_AGGRESSIVE_TURBO);
2602 I915_WRITE(GEN6_RC_VIDEO_FREQ,
2603 GEN6_FREQUENCY(12));
2604
2605 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2606 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
c6a828d3
DV		 2607 dev_priv->rps.max_delay << 24 |
2608 dev_priv->rps.min_delay << 16);
5a7dc92a 2609
1ee9ae32
DV		 2610 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
2611 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
2612 I915_WRITE(GEN6_RP_UP_EI, 66000);
2613 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5a7dc92a 2614
2b4e57bd
ED		 2615 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2616 I915_WRITE(GEN6_RP_CONTROL,
2617 GEN6_RP_MEDIA_TURBO |
89ba829e 2618 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2b4e57bd
ED		 2619 GEN6_RP_MEDIA_IS_GFX |
2620 GEN6_RP_ENABLE |
2621 GEN6_RP_UP_BUSY_AVG |
5a7dc92a 2622 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2b4e57bd 2623
42c0526c
BW		 2624 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
2625 if (!ret) {
2626 pcu_mbox = 0;
2627 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
2628 if (ret && pcu_mbox & (1<<31)) { /* OC supported */
2629 dev_priv->rps.max_delay = pcu_mbox & 0xff;
2630 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
2631 }
2632 } else {
2633 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2b4e57bd
ED		 2634 }
2635
7b9e0ae6 2636 gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2b4e57bd
ED		 2637
2638 /* requires MSI enabled */
ff928261 2639 I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
c6a828d3
DV		 2640 spin_lock_irq(&dev_priv->rps.lock);
2641 WARN_ON(dev_priv->rps.pm_iir != 0);
2b4e57bd 2642 I915_WRITE(GEN6_PMIMR, 0);
c6a828d3 2643 spin_unlock_irq(&dev_priv->rps.lock);
2b4e57bd
ED		 2644 /* enable all PM interrupts */
2645 I915_WRITE(GEN6_PMINTRMSK, 0);
2646
31643d54
BW		 2647 rc6vids = 0;
2648 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
2649 if (IS_GEN6(dev) && ret) {
2650 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
2651 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
2652 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
2653 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
2654 rc6vids &= 0xffff00;
2655 rc6vids |= GEN6_ENCODE_RC6_VID(450);
2656 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
2657 if (ret)
2658 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
2659 }
2660
2b4e57bd 2661 gen6_gt_force_wake_put(dev_priv);
2b4e57bd
ED		 2662}
2663
79f5b2c7 2664static void gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 2665{
79f5b2c7 2666 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 2667 int min_freq = 15;
e3fef09d
JD		 2668 int gpu_freq;
2669 unsigned int ia_freq, max_ia_freq;
2b4e57bd
ED		 2670 int scaling_factor = 180;
2671
4fc688ce 2672 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 2673
2b4e57bd
ED		 2674 max_ia_freq = cpufreq_quick_get_max(0);
2675 /*
2676 * Default to measured freq if none found, PCU will ensure we don't go
2677 * over
2678 */
2679 if (!max_ia_freq)
2680 max_ia_freq = tsc_khz;
2681
2682 /* Convert from kHz to MHz */
2683 max_ia_freq /= 1000;
2684
2b4e57bd
ED		 2685 /*
2686 * For each potential GPU frequency, load a ring frequency we'd like
2687 * to use for memory access. We do this by specifying the IA frequency
2688 * the PCU should use as a reference to determine the ring frequency.
2689 */
c6a828d3 2690 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2b4e57bd 2691 gpu_freq--) {
c6a828d3 2692 int diff = dev_priv->rps.max_delay - gpu_freq;
2b4e57bd
ED		 2693
2694 /*
2695 * For GPU frequencies less than 750MHz, just use the lowest
2696 * ring freq.
2697 */
2698 if (gpu_freq < min_freq)
2699 ia_freq = 800;
2700 else
2701 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
2702 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
42c0526c 2703 ia_freq <<= GEN6_PCODE_FREQ_IA_RATIO_SHIFT;
2b4e57bd 2704
42c0526c
BW		 2705 sandybridge_pcode_write(dev_priv,
2706 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
2707 ia_freq | gpu_freq);
2b4e57bd 2708 }
2b4e57bd
ED		 2709}
2710
930ebb46 2711void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 2712{
2713 struct drm_i915_private *dev_priv = dev->dev_private;
2714
3e373948
DV		 2715 if (dev_priv->ips.renderctx) {
2716 i915_gem_object_unpin(dev_priv->ips.renderctx);
2717 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
2718 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 2719 }
2720
3e373948
DV		 2721 if (dev_priv->ips.pwrctx) {
2722 i915_gem_object_unpin(dev_priv->ips.pwrctx);
2723 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
2724 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 2725 }
2726}
2727
930ebb46 2728static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 2729{
2730 struct drm_i915_private *dev_priv = dev->dev_private;
2731
2732 if (I915_READ(PWRCTXA)) {
2733 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
2734 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
2735 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
2736 50);
2737
2738 I915_WRITE(PWRCTXA, 0);
2739 POSTING_READ(PWRCTXA);
2740
2741 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2742 POSTING_READ(RSTDBYCTL);
2743 }
2b4e57bd
ED		 2744}
2745
2746static int ironlake_setup_rc6(struct drm_device *dev)
2747{
2748 struct drm_i915_private *dev_priv = dev->dev_private;
2749
3e373948
DV		 2750 if (dev_priv->ips.renderctx == NULL)
2751 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
2752 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 2753 return -ENOMEM;
2754
3e373948
DV		 2755 if (dev_priv->ips.pwrctx == NULL)
2756 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
2757 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 2758 ironlake_teardown_rc6(dev);
2759 return -ENOMEM;
2760 }
2761
2762 return 0;
2763}
2764
930ebb46 2765static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 2766{
2767 struct drm_i915_private *dev_priv = dev->dev_private;
6d90c952 2768 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3e960501 2769 bool was_interruptible;
2b4e57bd
ED		 2770 int ret;
2771
2772 /* rc6 disabled by default due to repeated reports of hanging during
2773 * boot and resume.
2774 */
2775 if (!intel_enable_rc6(dev))
2776 return;
2777
79f5b2c7
DV		 2778 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2779
2b4e57bd 2780 ret = ironlake_setup_rc6(dev);
79f5b2c7 2781 if (ret)
2b4e57bd 2782 return;
2b4e57bd 2783
3e960501
CW		 2784 was_interruptible = dev_priv->mm.interruptible;
2785 dev_priv->mm.interruptible = false;
2786
2b4e57bd
ED		 2787 /*
2788 * GPU can automatically power down the render unit if given a page
2789 * to save state.
2790 */
6d90c952 2791 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 2792 if (ret) {
2793 ironlake_teardown_rc6(dev);
3e960501 2794 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 2795 return;
2796 }
2797
6d90c952
DV		 2798 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
2799 intel_ring_emit(ring, MI_SET_CONTEXT);
3e373948 2800 intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset |
6d90c952
DV		 2801 MI_MM_SPACE_GTT |
2802 MI_SAVE_EXT_STATE_EN |
2803 MI_RESTORE_EXT_STATE_EN |
2804 MI_RESTORE_INHIBIT);
2805 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
2806 intel_ring_emit(ring, MI_NOOP);
2807 intel_ring_emit(ring, MI_FLUSH);
2808 intel_ring_advance(ring);
2b4e57bd
ED		 2809
2810 /*
2811 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
2812 * does an implicit flush, combined with MI_FLUSH above, it should be
2813 * safe to assume that renderctx is valid
2814 */
3e960501
CW		 2815 ret = intel_ring_idle(ring);
2816 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 2817 if (ret) {
2818 DRM_ERROR("failed to enable ironlake power power savings\n");
2819 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 2820 return;
2821 }
2822
3e373948 2823 I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN);
2b4e57bd 2824 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2b4e57bd
ED		 2825}
2826
dde18883
ED		 2827static unsigned long intel_pxfreq(u32 vidfreq)
2828{
2829 unsigned long freq;
2830 int div = (vidfreq & 0x3f0000) >> 16;
2831 int post = (vidfreq & 0x3000) >> 12;
2832 int pre = (vidfreq & 0x7);
2833
2834 if (!pre)
2835 return 0;
2836
2837 freq = ((div * 133333) / ((1<<post) * pre));
2838
2839 return freq;
2840}
2841
eb48eb00
DV		 2842static const struct cparams {
2843 u16 i;
2844 u16 t;
2845 u16 m;
2846 u16 c;
2847} cparams[] = {
2848 { 1, 1333, 301, 28664 },
2849 { 1, 1066, 294, 24460 },
2850 { 1, 800, 294, 25192 },
2851 { 0, 1333, 276, 27605 },
2852 { 0, 1066, 276, 27605 },
2853 { 0, 800, 231, 23784 },
2854};
2855
f531dcb2 2856static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 2857{
2858 u64 total_count, diff, ret;
2859 u32 count1, count2, count3, m = 0, c = 0;
2860 unsigned long now = jiffies_to_msecs(jiffies), diff1;
2861 int i;
2862
02d71956
DV		 2863 assert_spin_locked(&mchdev_lock);
2864
20e4d407 2865 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 2866
2867 /* Prevent division-by-zero if we are asking too fast.
2868 * Also, we don't get interesting results if we are polling
2869 * faster than once in 10ms, so just return the saved value
2870 * in such cases.
2871 */
2872 if (diff1 <= 10)
20e4d407 2873 return dev_priv->ips.chipset_power;
eb48eb00
DV		 2874
2875 count1 = I915_READ(DMIEC);
2876 count2 = I915_READ(DDREC);
2877 count3 = I915_READ(CSIEC);
2878
2879 total_count = count1 + count2 + count3;
2880
2881 /* FIXME: handle per-counter overflow */
20e4d407
DV		 2882 if (total_count < dev_priv->ips.last_count1) {
2883 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 2884 diff += total_count;
2885 } else {
20e4d407 2886 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 2887 }
2888
2889 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 2890 if (cparams[i].i == dev_priv->ips.c_m &&
2891 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 2892 m = cparams[i].m;
2893 c = cparams[i].c;
2894 break;
2895 }
2896 }
2897
2898 diff = div_u64(diff, diff1);
2899 ret = ((m * diff) + c);
2900 ret = div_u64(ret, 10);
2901
20e4d407
DV		 2902 dev_priv->ips.last_count1 = total_count;
2903 dev_priv->ips.last_time1 = now;
eb48eb00 2904
20e4d407 2905 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 2906
2907 return ret;
2908}
2909
f531dcb2
CW		 2910unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
2911{
2912 unsigned long val;
2913
2914 if (dev_priv->info->gen != 5)
2915 return 0;
2916
2917 spin_lock_irq(&mchdev_lock);
2918
2919 val = __i915_chipset_val(dev_priv);
2920
2921 spin_unlock_irq(&mchdev_lock);
2922
2923 return val;
2924}
2925
eb48eb00
DV		 2926unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
2927{
2928 unsigned long m, x, b;
2929 u32 tsfs;
2930
2931 tsfs = I915_READ(TSFS);
2932
2933 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
2934 x = I915_READ8(TR1);
2935
2936 b = tsfs & TSFS_INTR_MASK;
2937
2938 return ((m * x) / 127) - b;
2939}
2940
2941static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
2942{
2943 static const struct v_table {
2944 u16 vd; /* in .1 mil */
2945 u16 vm; /* in .1 mil */
2946 } v_table[] = {
2947 { 0, 0, },
2948 { 375, 0, },
2949 { 500, 0, },
2950 { 625, 0, },
2951 { 750, 0, },
2952 { 875, 0, },
2953 { 1000, 0, },
2954 { 1125, 0, },
2955 { 4125, 3000, },
2956 { 4125, 3000, },
2957 { 4125, 3000, },
2958 { 4125, 3000, },
2959 { 4125, 3000, },
2960 { 4125, 3000, },
2961 { 4125, 3000, },
2962 { 4125, 3000, },
2963 { 4125, 3000, },
2964 { 4125, 3000, },
2965 { 4125, 3000, },
2966 { 4125, 3000, },
2967 { 4125, 3000, },
2968 { 4125, 3000, },
2969 { 4125, 3000, },
2970 { 4125, 3000, },
2971 { 4125, 3000, },
2972 { 4125, 3000, },
2973 { 4125, 3000, },
2974 { 4125, 3000, },
2975 { 4125, 3000, },
2976 { 4125, 3000, },
2977 { 4125, 3000, },
2978 { 4125, 3000, },
2979 { 4250, 3125, },
2980 { 4375, 3250, },
2981 { 4500, 3375, },
2982 { 4625, 3500, },
2983 { 4750, 3625, },
2984 { 4875, 3750, },
2985 { 5000, 3875, },
2986 { 5125, 4000, },
2987 { 5250, 4125, },
2988 { 5375, 4250, },
2989 { 5500, 4375, },
2990 { 5625, 4500, },
2991 { 5750, 4625, },
2992 { 5875, 4750, },
2993 { 6000, 4875, },
2994 { 6125, 5000, },
2995 { 6250, 5125, },
2996 { 6375, 5250, },
2997 { 6500, 5375, },
2998 { 6625, 5500, },
2999 { 6750, 5625, },
3000 { 6875, 5750, },
3001 { 7000, 5875, },
3002 { 7125, 6000, },
3003 { 7250, 6125, },
3004 { 7375, 6250, },
3005 { 7500, 6375, },
3006 { 7625, 6500, },
3007 { 7750, 6625, },
3008 { 7875, 6750, },
3009 { 8000, 6875, },
3010 { 8125, 7000, },
3011 { 8250, 7125, },
3012 { 8375, 7250, },
3013 { 8500, 7375, },
3014 { 8625, 7500, },
3015 { 8750, 7625, },
3016 { 8875, 7750, },
3017 { 9000, 7875, },
3018 { 9125, 8000, },
3019 { 9250, 8125, },
3020 { 9375, 8250, },
3021 { 9500, 8375, },
3022 { 9625, 8500, },
3023 { 9750, 8625, },
3024 { 9875, 8750, },
3025 { 10000, 8875, },
3026 { 10125, 9000, },
3027 { 10250, 9125, },
3028 { 10375, 9250, },
3029 { 10500, 9375, },
3030 { 10625, 9500, },
3031 { 10750, 9625, },
3032 { 10875, 9750, },
3033 { 11000, 9875, },
3034 { 11125, 10000, },
3035 { 11250, 10125, },
3036 { 11375, 10250, },
3037 { 11500, 10375, },
3038 { 11625, 10500, },
3039 { 11750, 10625, },
3040 { 11875, 10750, },
3041 { 12000, 10875, },
3042 { 12125, 11000, },
3043 { 12250, 11125, },
3044 { 12375, 11250, },
3045 { 12500, 11375, },
3046 { 12625, 11500, },
3047 { 12750, 11625, },
3048 { 12875, 11750, },
3049 { 13000, 11875, },
3050 { 13125, 12000, },
3051 { 13250, 12125, },
3052 { 13375, 12250, },
3053 { 13500, 12375, },
3054 { 13625, 12500, },
3055 { 13750, 12625, },
3056 { 13875, 12750, },
3057 { 14000, 12875, },
3058 { 14125, 13000, },
3059 { 14250, 13125, },
3060 { 14375, 13250, },
3061 { 14500, 13375, },
3062 { 14625, 13500, },
3063 { 14750, 13625, },
3064 { 14875, 13750, },
3065 { 15000, 13875, },
3066 { 15125, 14000, },
3067 { 15250, 14125, },
3068 { 15375, 14250, },
3069 { 15500, 14375, },
3070 { 15625, 14500, },
3071 { 15750, 14625, },
3072 { 15875, 14750, },
3073 { 16000, 14875, },
3074 { 16125, 15000, },
3075 };
3076 if (dev_priv->info->is_mobile)
3077 return v_table[pxvid].vm;
3078 else
3079 return v_table[pxvid].vd;
3080}
3081
02d71956 3082static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 3083{
3084 struct timespec now, diff1;
3085 u64 diff;
3086 unsigned long diffms;
3087 u32 count;
3088
02d71956 3089 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 3090
3091 getrawmonotonic(&now);
20e4d407 3092 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 3093
3094 /* Don't divide by 0 */
3095 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
3096 if (!diffms)
3097 return;
3098
3099 count = I915_READ(GFXEC);
3100
20e4d407
DV		 3101 if (count < dev_priv->ips.last_count2) {
3102 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 3103 diff += count;
3104 } else {
20e4d407 3105 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 3106 }
3107
20e4d407
DV		 3108 dev_priv->ips.last_count2 = count;
3109 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 3110
3111 /* More magic constants... */
3112 diff = diff * 1181;
3113 diff = div_u64(diff, diffms * 10);
20e4d407 3114 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 3115}
3116
02d71956
DV		 3117void i915_update_gfx_val(struct drm_i915_private *dev_priv)
3118{
3119 if (dev_priv->info->gen != 5)
3120 return;
3121
9270388e 3122 spin_lock_irq(&mchdev_lock);
02d71956
DV		 3123
3124 __i915_update_gfx_val(dev_priv);
3125
9270388e 3126 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 3127}
3128
f531dcb2 3129static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 3130{
3131 unsigned long t, corr, state1, corr2, state2;
3132 u32 pxvid, ext_v;
3133
02d71956
DV		 3134 assert_spin_locked(&mchdev_lock);
3135
c6a828d3 3136 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
eb48eb00
DV		 3137 pxvid = (pxvid >> 24) & 0x7f;
3138 ext_v = pvid_to_extvid(dev_priv, pxvid);
3139
3140 state1 = ext_v;
3141
3142 t = i915_mch_val(dev_priv);
3143
3144 /* Revel in the empirically derived constants */
3145
3146 /* Correction factor in 1/100000 units */
3147 if (t > 80)
3148 corr = ((t * 2349) + 135940);
3149 else if (t >= 50)
3150 corr = ((t * 964) + 29317);
3151 else /* < 50 */
3152 corr = ((t * 301) + 1004);
3153
3154 corr = corr * ((150142 * state1) / 10000 - 78642);
3155 corr /= 100000;
20e4d407 3156 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 3157
3158 state2 = (corr2 * state1) / 10000;
3159 state2 /= 100; /* convert to mW */
3160
02d71956 3161 __i915_update_gfx_val(dev_priv);
eb48eb00 3162
20e4d407 3163 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 3164}
3165
f531dcb2
CW		 3166unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
3167{
3168 unsigned long val;
3169
3170 if (dev_priv->info->gen != 5)
3171 return 0;
3172
3173 spin_lock_irq(&mchdev_lock);
3174
3175 val = __i915_gfx_val(dev_priv);
3176
3177 spin_unlock_irq(&mchdev_lock);
3178
3179 return val;
3180}
3181
eb48eb00
DV		 3182/**
3183 * i915_read_mch_val - return value for IPS use
3184 *
3185 * Calculate and return a value for the IPS driver to use when deciding whether
3186 * we have thermal and power headroom to increase CPU or GPU power budget.
3187 */
3188unsigned long i915_read_mch_val(void)
3189{
3190 struct drm_i915_private *dev_priv;
3191 unsigned long chipset_val, graphics_val, ret = 0;
3192
9270388e 3193 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3194 if (!i915_mch_dev)
3195 goto out_unlock;
3196 dev_priv = i915_mch_dev;
3197
f531dcb2
CW		 3198 chipset_val = __i915_chipset_val(dev_priv);
3199 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 3200
3201 ret = chipset_val + graphics_val;
3202
3203out_unlock:
9270388e 3204 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3205
3206 return ret;
3207}
3208EXPORT_SYMBOL_GPL(i915_read_mch_val);
3209
3210/**
3211 * i915_gpu_raise - raise GPU frequency limit
3212 *
3213 * Raise the limit; IPS indicates we have thermal headroom.
3214 */
3215bool i915_gpu_raise(void)
3216{
3217 struct drm_i915_private *dev_priv;
3218 bool ret = true;
3219
9270388e 3220 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3221 if (!i915_mch_dev) {
3222 ret = false;
3223 goto out_unlock;
3224 }
3225 dev_priv = i915_mch_dev;
3226
20e4d407
DV		 3227 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
3228 dev_priv->ips.max_delay--;
eb48eb00
DV		 3229
3230out_unlock:
9270388e 3231 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3232
3233 return ret;
3234}
3235EXPORT_SYMBOL_GPL(i915_gpu_raise);
3236
3237/**
3238 * i915_gpu_lower - lower GPU frequency limit
3239 *
3240 * IPS indicates we're close to a thermal limit, so throttle back the GPU
3241 * frequency maximum.
3242 */
3243bool i915_gpu_lower(void)
3244{
3245 struct drm_i915_private *dev_priv;
3246 bool ret = true;
3247
9270388e 3248 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3249 if (!i915_mch_dev) {
3250 ret = false;
3251 goto out_unlock;
3252 }
3253 dev_priv = i915_mch_dev;
3254
20e4d407
DV		 3255 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
3256 dev_priv->ips.max_delay++;
eb48eb00
DV		 3257
3258out_unlock:
9270388e 3259 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3260
3261 return ret;
3262}
3263EXPORT_SYMBOL_GPL(i915_gpu_lower);
3264
3265/**
3266 * i915_gpu_busy - indicate GPU business to IPS
3267 *
3268 * Tell the IPS driver whether or not the GPU is busy.
3269 */
3270bool i915_gpu_busy(void)
3271{
3272 struct drm_i915_private *dev_priv;
f047e395 3273 struct intel_ring_buffer *ring;
eb48eb00 3274 bool ret = false;
f047e395 3275 int i;
eb48eb00 3276
9270388e 3277 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3278 if (!i915_mch_dev)
3279 goto out_unlock;
3280 dev_priv = i915_mch_dev;
3281
f047e395
CW		 3282 for_each_ring(ring, dev_priv, i)
3283 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 3284
3285out_unlock:
9270388e 3286 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3287
3288 return ret;
3289}
3290EXPORT_SYMBOL_GPL(i915_gpu_busy);
3291
3292/**
3293 * i915_gpu_turbo_disable - disable graphics turbo
3294 *
3295 * Disable graphics turbo by resetting the max frequency and setting the
3296 * current frequency to the default.
3297 */
3298bool i915_gpu_turbo_disable(void)
3299{
3300 struct drm_i915_private *dev_priv;
3301 bool ret = true;
3302
9270388e 3303 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3304 if (!i915_mch_dev) {
3305 ret = false;
3306 goto out_unlock;
3307 }
3308 dev_priv = i915_mch_dev;
3309
20e4d407 3310 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 3311
20e4d407 3312 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 3313 ret = false;
3314
3315out_unlock:
9270388e 3316 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3317
3318 return ret;
3319}
3320EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
3321
3322/**
3323 * Tells the intel_ips driver that the i915 driver is now loaded, if
3324 * IPS got loaded first.
3325 *
3326 * This awkward dance is so that neither module has to depend on the
3327 * other in order for IPS to do the appropriate communication of
3328 * GPU turbo limits to i915.
3329 */
3330static void
3331ips_ping_for_i915_load(void)
3332{
3333 void (*link)(void);
3334
3335 link = symbol_get(ips_link_to_i915_driver);
3336 if (link) {
3337 link();
3338 symbol_put(ips_link_to_i915_driver);
3339 }
3340}
3341
3342void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
3343{
02d71956
DV		 3344 /* We only register the i915 ips part with intel-ips once everything is
3345 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 3346 spin_lock_irq(&mchdev_lock);
eb48eb00 3347 i915_mch_dev = dev_priv;
9270388e 3348 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3349
3350 ips_ping_for_i915_load();
3351}
3352
3353void intel_gpu_ips_teardown(void)
3354{
9270388e 3355 spin_lock_irq(&mchdev_lock);
eb48eb00 3356 i915_mch_dev = NULL;
9270388e 3357 spin_unlock_irq(&mchdev_lock);
eb48eb00 3358}
8090c6b9 3359static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 3360{
3361 struct drm_i915_private *dev_priv = dev->dev_private;
3362 u32 lcfuse;
3363 u8 pxw[16];
3364 int i;
3365
3366 /* Disable to program */
3367 I915_WRITE(ECR, 0);
3368 POSTING_READ(ECR);
3369
3370 /* Program energy weights for various events */
3371 I915_WRITE(SDEW, 0x15040d00);
3372 I915_WRITE(CSIEW0, 0x007f0000);
3373 I915_WRITE(CSIEW1, 0x1e220004);
3374 I915_WRITE(CSIEW2, 0x04000004);
3375
3376 for (i = 0; i < 5; i++)
3377 I915_WRITE(PEW + (i * 4), 0);
3378 for (i = 0; i < 3; i++)
3379 I915_WRITE(DEW + (i * 4), 0);
3380
3381 /* Program P-state weights to account for frequency power adjustment */
3382 for (i = 0; i < 16; i++) {
3383 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
3384 unsigned long freq = intel_pxfreq(pxvidfreq);
3385 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
3386 PXVFREQ_PX_SHIFT;
3387 unsigned long val;
3388
3389 val = vid * vid;
3390 val *= (freq / 1000);
3391 val *= 255;
3392 val /= (127*127*900);
3393 if (val > 0xff)
3394 DRM_ERROR("bad pxval: %ld\n", val);
3395 pxw[i] = val;
3396 }
3397 /* Render standby states get 0 weight */
3398 pxw[14] = 0;
3399 pxw[15] = 0;
3400
3401 for (i = 0; i < 4; i++) {
3402 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
3403 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
3404 I915_WRITE(PXW + (i * 4), val);
3405 }
3406
3407 /* Adjust magic regs to magic values (more experimental results) */
3408 I915_WRITE(OGW0, 0);
3409 I915_WRITE(OGW1, 0);
3410 I915_WRITE(EG0, 0x00007f00);
3411 I915_WRITE(EG1, 0x0000000e);
3412 I915_WRITE(EG2, 0x000e0000);
3413 I915_WRITE(EG3, 0x68000300);
3414 I915_WRITE(EG4, 0x42000000);
3415 I915_WRITE(EG5, 0x00140031);
3416 I915_WRITE(EG6, 0);
3417 I915_WRITE(EG7, 0);
3418
3419 for (i = 0; i < 8; i++)
3420 I915_WRITE(PXWL + (i * 4), 0);
3421
3422 /* Enable PMON + select events */
3423 I915_WRITE(ECR, 0x80000019);
3424
3425 lcfuse = I915_READ(LCFUSE02);
3426
20e4d407 3427 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 3428}
3429
8090c6b9
DV		 3430void intel_disable_gt_powersave(struct drm_device *dev)
3431{
1a01ab3b
JB		 3432 struct drm_i915_private *dev_priv = dev->dev_private;
3433
930ebb46 3434 if (IS_IRONLAKE_M(dev)) {
8090c6b9 3435 ironlake_disable_drps(dev);
930ebb46
DV		 3436 ironlake_disable_rc6(dev);
3437 } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) {
1a01ab3b 3438 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
4fc688ce 3439 mutex_lock(&dev_priv->rps.hw_lock);
8090c6b9 3440 gen6_disable_rps(dev);
4fc688ce 3441 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 3442 }
8090c6b9
DV		 3443}
3444
1a01ab3b
JB		 3445static void intel_gen6_powersave_work(struct work_struct *work)
3446{
3447 struct drm_i915_private *dev_priv =
3448 container_of(work, struct drm_i915_private,
3449 rps.delayed_resume_work.work);
3450 struct drm_device *dev = dev_priv->dev;
3451
4fc688ce 3452 mutex_lock(&dev_priv->rps.hw_lock);
1a01ab3b
JB		 3453 gen6_enable_rps(dev);
3454 gen6_update_ring_freq(dev);
4fc688ce 3455 mutex_unlock(&dev_priv->rps.hw_lock);
1a01ab3b
JB		 3456}
3457
8090c6b9
DV		 3458void intel_enable_gt_powersave(struct drm_device *dev)
3459{
1a01ab3b
JB		 3460 struct drm_i915_private *dev_priv = dev->dev_private;
3461
8090c6b9
DV		 3462 if (IS_IRONLAKE_M(dev)) {
3463 ironlake_enable_drps(dev);
3464 ironlake_enable_rc6(dev);
3465 intel_init_emon(dev);
7cf50fc8 3466 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
1a01ab3b
JB		 3467 /*
3468 * PCU communication is slow and this doesn't need to be
3469 * done at any specific time, so do this out of our fast path
3470 * to make resume and init faster.
3471 */
3472 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
3473 round_jiffies_up_relative(HZ));
8090c6b9
DV		 3474 }
3475}
3476
3107bd48
DV		 3477static void ibx_init_clock_gating(struct drm_device *dev)
3478{
3479 struct drm_i915_private *dev_priv = dev->dev_private;
3480
3481 /*
3482 * On Ibex Peak and Cougar Point, we need to disable clock
3483 * gating for the panel power sequencer or it will fail to
3484 * start up when no ports are active.
3485 */
3486 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3487}
3488
1fa61106 3489static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3490{
3491 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 3492 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0
ED		 3493
3494 /* Required for FBC */
4d47e4f5
DL		 3495 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
3496 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
3497 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 3498
3499 I915_WRITE(PCH_3DCGDIS0,
3500 MARIUNIT_CLOCK_GATE_DISABLE |
3501 SVSMUNIT_CLOCK_GATE_DISABLE);
3502 I915_WRITE(PCH_3DCGDIS1,
3503 VFMUNIT_CLOCK_GATE_DISABLE);
3504
6f1d69b0
ED		 3505 /*
3506 * According to the spec the following bits should be set in
3507 * order to enable memory self-refresh
3508 * The bit 22/21 of 0x42004
3509 * The bit 5 of 0x42020
3510 * The bit 15 of 0x45000
3511 */
3512 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3513 (I915_READ(ILK_DISPLAY_CHICKEN2) |
3514 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 3515 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 3516 I915_WRITE(DISP_ARB_CTL,
3517 (I915_READ(DISP_ARB_CTL) |
3518 DISP_FBC_WM_DIS));
3519 I915_WRITE(WM3_LP_ILK, 0);
3520 I915_WRITE(WM2_LP_ILK, 0);
3521 I915_WRITE(WM1_LP_ILK, 0);
3522
3523 /*
3524 * Based on the document from hardware guys the following bits
3525 * should be set unconditionally in order to enable FBC.
3526 * The bit 22 of 0x42000
3527 * The bit 22 of 0x42004
3528 * The bit 7,8,9 of 0x42020.
3529 */
3530 if (IS_IRONLAKE_M(dev)) {
3531 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3532 I915_READ(ILK_DISPLAY_CHICKEN1) |
3533 ILK_FBCQ_DIS);
3534 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3535 I915_READ(ILK_DISPLAY_CHICKEN2) |
3536 ILK_DPARB_GATE);
6f1d69b0
ED		 3537 }
3538
4d47e4f5
DL		 3539 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3540
6f1d69b0
ED		 3541 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3542 I915_READ(ILK_DISPLAY_CHICKEN2) |
3543 ILK_ELPIN_409_SELECT);
3544 I915_WRITE(_3D_CHICKEN2,
3545 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
3546 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374
DV		 3547
3548 /* WaDisableRenderCachePipelinedFlush */
3549 I915_WRITE(CACHE_MODE_0,
3550 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48
DV		 3551
3552 ibx_init_clock_gating(dev);
3553}
3554
3555static void cpt_init_clock_gating(struct drm_device *dev)
3556{
3557 struct drm_i915_private *dev_priv = dev->dev_private;
3558 int pipe;
3559
3560 /*
3561 * On Ibex Peak and Cougar Point, we need to disable clock
3562 * gating for the panel power sequencer or it will fail to
3563 * start up when no ports are active.
3564 */
3565 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3566 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
3567 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 3568 /* The below fixes the weird display corruption, a few pixels shifted
3569 * downward, on (only) LVDS of some HP laptops with IVY.
3570 */
3571 for_each_pipe(pipe)
3572 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_CHICKEN2_TIMING_OVERRIDE);
3107bd48
DV		 3573 /* WADP0ClockGatingDisable */
3574 for_each_pipe(pipe) {
3575 I915_WRITE(TRANS_CHICKEN1(pipe),
3576 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
3577 }
6f1d69b0
ED		 3578}
3579
1fa61106 3580static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3581{
3582 struct drm_i915_private *dev_priv = dev->dev_private;
3583 int pipe;
231e54f6 3584 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 3585
231e54f6 3586 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 3587
3588 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3589 I915_READ(ILK_DISPLAY_CHICKEN2) |
3590 ILK_ELPIN_409_SELECT);
3591
4283908e
DV		 3592 /* WaDisableHiZPlanesWhenMSAAEnabled */
3593 I915_WRITE(_3D_CHICKEN,
3594 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
3595
6547fbdb
DV		 3596 /* WaSetupGtModeTdRowDispatch */
3597 if (IS_SNB_GT1(dev))
3598 I915_WRITE(GEN6_GT_MODE,
3599 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
3600
6f1d69b0
ED		 3601 I915_WRITE(WM3_LP_ILK, 0);
3602 I915_WRITE(WM2_LP_ILK, 0);
3603 I915_WRITE(WM1_LP_ILK, 0);
3604
6f1d69b0 3605 I915_WRITE(CACHE_MODE_0,
50743298 3606 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 3607
3608 I915_WRITE(GEN6_UCGCTL1,
3609 I915_READ(GEN6_UCGCTL1) |
3610 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
3611 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
3612
3613 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3614 * gating disable must be set. Failure to set it results in
3615 * flickering pixels due to Z write ordering failures after
3616 * some amount of runtime in the Mesa "fire" demo, and Unigine
3617 * Sanctuary and Tropics, and apparently anything else with
3618 * alpha test or pixel discard.
3619 *
3620 * According to the spec, bit 11 (RCCUNIT) must also be set,
3621 * but we didn't debug actual testcases to find it out.
0f846f81
JB		 3622 *
3623 * Also apply WaDisableVDSUnitClockGating and
3624 * WaDisableRCPBUnitClockGating.
6f1d69b0
ED		 3625 */
3626 I915_WRITE(GEN6_UCGCTL2,
0f846f81 3627 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6f1d69b0
ED		 3628 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3629 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3630
3631 /* Bspec says we need to always set all mask bits. */
26b6e44a
KG		 3632 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
3633 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
6f1d69b0
ED		 3634
3635 /*
3636 * According to the spec the following bits should be
3637 * set in order to enable memory self-refresh and fbc:
3638 * The bit21 and bit22 of 0x42000
3639 * The bit21 and bit22 of 0x42004
3640 * The bit5 and bit7 of 0x42020
3641 * The bit14 of 0x70180
3642 * The bit14 of 0x71180
3643 */
3644 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3645 I915_READ(ILK_DISPLAY_CHICKEN1) |
3646 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
3647 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3648 I915_READ(ILK_DISPLAY_CHICKEN2) |
3649 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 3650 I915_WRITE(ILK_DSPCLK_GATE_D,
3651 I915_READ(ILK_DSPCLK_GATE_D) |
3652 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
3653 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 3654
b3bf0766 3655 /* WaMbcDriverBootEnable */
b4ae3f22
JB		 3656 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3657 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3658
6f1d69b0
ED		 3659 for_each_pipe(pipe) {
3660 I915_WRITE(DSPCNTR(pipe),
3661 I915_READ(DSPCNTR(pipe)) |
3662 DISPPLANE_TRICKLE_FEED_DISABLE);
3663 intel_flush_display_plane(dev_priv, pipe);
3664 }
f8f2ac9a
BW		 3665
3666 /* The default value should be 0x200 according to docs, but the two
3667 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
3668 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
3669 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3107bd48
DV		 3670
3671 cpt_init_clock_gating(dev);
6f1d69b0
ED		 3672}
3673
3674static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
3675{
3676 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
3677
3678 reg &= ~GEN7_FF_SCHED_MASK;
3679 reg |= GEN7_FF_TS_SCHED_HW;
3680 reg |= GEN7_FF_VS_SCHED_HW;
3681 reg |= GEN7_FF_DS_SCHED_HW;
3682
3683 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
3684}
3685
17a303ec
PZ		 3686static void lpt_init_clock_gating(struct drm_device *dev)
3687{
3688 struct drm_i915_private *dev_priv = dev->dev_private;
3689
3690 /*
3691 * TODO: this bit should only be enabled when really needed, then
3692 * disabled when not needed anymore in order to save power.
3693 */
3694 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
3695 I915_WRITE(SOUTH_DSPCLK_GATE_D,
3696 I915_READ(SOUTH_DSPCLK_GATE_D) |
3697 PCH_LP_PARTITION_LEVEL_DISABLE);
3698}
3699
cad2a2d7
ED		 3700static void haswell_init_clock_gating(struct drm_device *dev)
3701{
3702 struct drm_i915_private *dev_priv = dev->dev_private;
3703 int pipe;
cad2a2d7
ED		 3704
3705 I915_WRITE(WM3_LP_ILK, 0);
3706 I915_WRITE(WM2_LP_ILK, 0);
3707 I915_WRITE(WM1_LP_ILK, 0);
3708
3709 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3710 * This implements the WaDisableRCZUnitClockGating workaround.
3711 */
3712 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
3713
cad2a2d7
ED		 3714 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3715 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3716 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3717
3718 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3719 I915_WRITE(GEN7_L3CNTLREG1,
3720 GEN7_WA_FOR_GEN7_L3_CONTROL);
3721 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
3722 GEN7_WA_L3_CHICKEN_MODE);
3723
3724 /* This is required by WaCatErrorRejectionIssue */
3725 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3726 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3727 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3728
3729 for_each_pipe(pipe) {
3730 I915_WRITE(DSPCNTR(pipe),
3731 I915_READ(DSPCNTR(pipe)) |
3732 DISPPLANE_TRICKLE_FEED_DISABLE);
3733 intel_flush_display_plane(dev_priv, pipe);
3734 }
3735
3736 gen7_setup_fixed_func_scheduler(dev_priv);
3737
3738 /* WaDisable4x2SubspanOptimization */
3739 I915_WRITE(CACHE_MODE_1,
3740 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 3741
b3bf0766
PZ		 3742 /* WaMbcDriverBootEnable */
3743 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3744 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3745
1544d9d5
ED		 3746 /* XXX: This is a workaround for early silicon revisions and should be
3747 * removed later.
3748 */
3749 I915_WRITE(WM_DBG,
3750 I915_READ(WM_DBG) |
3751 WM_DBG_DISALLOW_MULTIPLE_LP |
3752 WM_DBG_DISALLOW_SPRITE |
3753 WM_DBG_DISALLOW_MAXFIFO);
3754
17a303ec 3755 lpt_init_clock_gating(dev);
cad2a2d7
ED		 3756}
3757
1fa61106 3758static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3759{
3760 struct drm_i915_private *dev_priv = dev->dev_private;
3761 int pipe;
20848223 3762 uint32_t snpcr;
6f1d69b0 3763
6f1d69b0
ED		 3764 I915_WRITE(WM3_LP_ILK, 0);
3765 I915_WRITE(WM2_LP_ILK, 0);
3766 I915_WRITE(WM1_LP_ILK, 0);
3767
231e54f6 3768 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 3769
87f8020e
JB		 3770 /* WaDisableEarlyCull */
3771 I915_WRITE(_3D_CHICKEN3,
3772 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
3773
62cb944f 3774 /* WaDisableBackToBackFlipFix */
6f1d69b0
ED		 3775 I915_WRITE(IVB_CHICKEN3,
3776 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3777 CHICKEN3_DGMG_DONE_FIX_DISABLE);
3778
12f3382b
JB		 3779 /* WaDisablePSDDualDispatchEnable */
3780 if (IS_IVB_GT1(dev))
3781 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
3782 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3783 else
3784 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
3785 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3786
6f1d69b0
ED		 3787 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3788 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3789 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3790
3791 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3792 I915_WRITE(GEN7_L3CNTLREG1,
3793 GEN7_WA_FOR_GEN7_L3_CONTROL);
3794 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 3795 GEN7_WA_L3_CHICKEN_MODE);
3796 if (IS_IVB_GT1(dev))
3797 I915_WRITE(GEN7_ROW_CHICKEN2,
3798 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3799 else
3800 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
3801 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3802
6f1d69b0 3803
61939d97
JB		 3804 /* WaForceL3Serialization */
3805 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3806 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3807
0f846f81
JB		 3808 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3809 * gating disable must be set. Failure to set it results in
3810 * flickering pixels due to Z write ordering failures after
3811 * some amount of runtime in the Mesa "fire" demo, and Unigine
3812 * Sanctuary and Tropics, and apparently anything else with
3813 * alpha test or pixel discard.
3814 *
3815 * According to the spec, bit 11 (RCCUNIT) must also be set,
3816 * but we didn't debug actual testcases to find it out.
3817 *
3818 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3819 * This implements the WaDisableRCZUnitClockGating workaround.
3820 */
3821 I915_WRITE(GEN6_UCGCTL2,
3822 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
3823 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3824
6f1d69b0
ED		 3825 /* This is required by WaCatErrorRejectionIssue */
3826 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3827 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3828 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3829
3830 for_each_pipe(pipe) {
3831 I915_WRITE(DSPCNTR(pipe),
3832 I915_READ(DSPCNTR(pipe)) |
3833 DISPPLANE_TRICKLE_FEED_DISABLE);
3834 intel_flush_display_plane(dev_priv, pipe);
3835 }
3836
b3bf0766 3837 /* WaMbcDriverBootEnable */
b4ae3f22
JB		 3838 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3839 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3840
6f1d69b0 3841 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f
DV		 3842
3843 /* WaDisable4x2SubspanOptimization */
3844 I915_WRITE(CACHE_MODE_1,
3845 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223
BW		 3846
3847 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3848 snpcr &= ~GEN6_MBC_SNPCR_MASK;
3849 snpcr |= GEN6_MBC_SNPCR_MED;
3850 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48
DV		 3851
3852 cpt_init_clock_gating(dev);
6f1d69b0
ED		 3853}
3854
1fa61106 3855static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3856{
3857 struct drm_i915_private *dev_priv = dev->dev_private;
3858 int pipe;
6f1d69b0
ED		 3859
3860 I915_WRITE(WM3_LP_ILK, 0);
3861 I915_WRITE(WM2_LP_ILK, 0);
3862 I915_WRITE(WM1_LP_ILK, 0);
3863
231e54f6 3864 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 3865
87f8020e
JB		 3866 /* WaDisableEarlyCull */
3867 I915_WRITE(_3D_CHICKEN3,
3868 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
3869
62cb944f 3870 /* WaDisableBackToBackFlipFix */
6f1d69b0
ED		 3871 I915_WRITE(IVB_CHICKEN3,
3872 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3873 CHICKEN3_DGMG_DONE_FIX_DISABLE);
3874
12f3382b
JB		 3875 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
3876 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3877
6f1d69b0
ED		 3878 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3879 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3880 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3881
3882 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
d0cf5ead 3883 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
6f1d69b0
ED		 3884 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
3885
61939d97
JB		 3886 /* WaForceL3Serialization */
3887 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3888 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3889
8ab43976
JB		 3890 /* WaDisableDopClockGating */
3891 I915_WRITE(GEN7_ROW_CHICKEN2,
3892 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3893
5c9664d7
JB		 3894 /* WaForceL3Serialization */
3895 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3896 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3897
6f1d69b0
ED		 3898 /* This is required by WaCatErrorRejectionIssue */
3899 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3900 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3901 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3902
b3bf0766 3903 /* WaMbcDriverBootEnable */
b4ae3f22
JB		 3904 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3905 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3906
0f846f81
JB		 3907
3908 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3909 * gating disable must be set. Failure to set it results in
3910 * flickering pixels due to Z write ordering failures after
3911 * some amount of runtime in the Mesa "fire" demo, and Unigine
3912 * Sanctuary and Tropics, and apparently anything else with
3913 * alpha test or pixel discard.
3914 *
3915 * According to the spec, bit 11 (RCCUNIT) must also be set,
3916 * but we didn't debug actual testcases to find it out.
3917 *
3918 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3919 * This implements the WaDisableRCZUnitClockGating workaround.
3920 *
3921 * Also apply WaDisableVDSUnitClockGating and
3922 * WaDisableRCPBUnitClockGating.
3923 */
3924 I915_WRITE(GEN6_UCGCTL2,
3925 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6edaa7fc 3926 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
0f846f81
JB		 3927 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
3928 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3929 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3930
e3f33d46
JB		 3931 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
3932
6f1d69b0
ED		 3933 for_each_pipe(pipe) {
3934 I915_WRITE(DSPCNTR(pipe),
3935 I915_READ(DSPCNTR(pipe)) |
3936 DISPPLANE_TRICKLE_FEED_DISABLE);
3937 intel_flush_display_plane(dev_priv, pipe);
3938 }
3939
6b26c86d
DV		 3940 I915_WRITE(CACHE_MODE_1,
3941 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f
JB		 3942
3943 /*
3944 * On ValleyView, the GUnit needs to signal the GT
3945 * when flip and other events complete. So enable
3946 * all the GUnit->GT interrupts here
3947 */
3948 I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN |
3949 PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN |
3950 SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN |
3951 PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN |
3952 PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN |
3953 SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN |
3954 PLANEA_FLIPDONE_INT_EN);
2d809570
JB		 3955
3956 /*
3957 * WaDisableVLVClockGating_VBIIssue
3958 * Disable clock gating on th GCFG unit to prevent a delay
3959 * in the reporting of vblank events.
3960 */
3961 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 3962}
3963
1fa61106 3964static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3965{
3966 struct drm_i915_private *dev_priv = dev->dev_private;
3967 uint32_t dspclk_gate;
3968
3969 I915_WRITE(RENCLK_GATE_D1, 0);
3970 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
3971 GS_UNIT_CLOCK_GATE_DISABLE |
3972 CL_UNIT_CLOCK_GATE_DISABLE);
3973 I915_WRITE(RAMCLK_GATE_D, 0);
3974 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
3975 OVRUNIT_CLOCK_GATE_DISABLE |
3976 OVCUNIT_CLOCK_GATE_DISABLE;
3977 if (IS_GM45(dev))
3978 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
3979 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 3980
3981 /* WaDisableRenderCachePipelinedFlush */
3982 I915_WRITE(CACHE_MODE_0,
3983 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6f1d69b0
ED		 3984}
3985
1fa61106 3986static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3987{
3988 struct drm_i915_private *dev_priv = dev->dev_private;
3989
3990 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
3991 I915_WRITE(RENCLK_GATE_D2, 0);
3992 I915_WRITE(DSPCLK_GATE_D, 0);
3993 I915_WRITE(RAMCLK_GATE_D, 0);
3994 I915_WRITE16(DEUC, 0);
3995}
3996
1fa61106 3997static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3998{
3999 struct drm_i915_private *dev_priv = dev->dev_private;
4000
4001 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4002 I965_RCC_CLOCK_GATE_DISABLE |
4003 I965_RCPB_CLOCK_GATE_DISABLE |
4004 I965_ISC_CLOCK_GATE_DISABLE |
4005 I965_FBC_CLOCK_GATE_DISABLE);
4006 I915_WRITE(RENCLK_GATE_D2, 0);
4007}
4008
1fa61106 4009static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4010{
4011 struct drm_i915_private *dev_priv = dev->dev_private;
4012 u32 dstate = I915_READ(D_STATE);
4013
4014 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4015 DSTATE_DOT_CLOCK_GATING;
4016 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 4017
4018 if (IS_PINEVIEW(dev))
4019 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 4020
4021 /* IIR "flip pending" means done if this bit is set */
4022 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6f1d69b0
ED		 4023}
4024
1fa61106 4025static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4026{
4027 struct drm_i915_private *dev_priv = dev->dev_private;
4028
4029 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4030}
4031
1fa61106 4032static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4033{
4034 struct drm_i915_private *dev_priv = dev->dev_private;
4035
4036 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4037}
4038
6f1d69b0
ED		 4039void intel_init_clock_gating(struct drm_device *dev)
4040{
4041 struct drm_i915_private *dev_priv = dev->dev_private;
4042
4043 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 4044}
4045
d0d3e513
ED		 4046/* Starting with Haswell, we have different power wells for
4047 * different parts of the GPU. This attempts to enable them all.
4048 */
4049void intel_init_power_wells(struct drm_device *dev)
4050{
4051 struct drm_i915_private *dev_priv = dev->dev_private;
4052 unsigned long power_wells[] = {
4053 HSW_PWR_WELL_CTL1,
4054 HSW_PWR_WELL_CTL2,
4055 HSW_PWR_WELL_CTL4
4056 };
4057 int i;
4058
4059 if (!IS_HASWELL(dev))
4060 return;
4061
4062 mutex_lock(&dev->struct_mutex);
4063
4064 for (i = 0; i < ARRAY_SIZE(power_wells); i++) {
4065 int well = I915_READ(power_wells[i]);
4066
4067 if ((well & HSW_PWR_WELL_STATE) == 0) {
4068 I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE);
263b30d4 4069 if (wait_for((I915_READ(power_wells[i]) & HSW_PWR_WELL_STATE), 20))
d0d3e513
ED		 4070 DRM_ERROR("Error enabling power well %lx\n", power_wells[i]);
4071 }
4072 }
4073
4074 mutex_unlock(&dev->struct_mutex);
4075}
4076
1fa61106
ED		 4077/* Set up chip specific power management-related functions */
4078void intel_init_pm(struct drm_device *dev)
4079{
4080 struct drm_i915_private *dev_priv = dev->dev_private;
4081
4082 if (I915_HAS_FBC(dev)) {
4083 if (HAS_PCH_SPLIT(dev)) {
4084 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
4085 dev_priv->display.enable_fbc = ironlake_enable_fbc;
4086 dev_priv->display.disable_fbc = ironlake_disable_fbc;
4087 } else if (IS_GM45(dev)) {
4088 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4089 dev_priv->display.enable_fbc = g4x_enable_fbc;
4090 dev_priv->display.disable_fbc = g4x_disable_fbc;
4091 } else if (IS_CRESTLINE(dev)) {
4092 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4093 dev_priv->display.enable_fbc = i8xx_enable_fbc;
4094 dev_priv->display.disable_fbc = i8xx_disable_fbc;
4095 }
4096 /* 855GM needs testing */
4097 }
4098
c921aba8
DV		 4099 /* For cxsr */
4100 if (IS_PINEVIEW(dev))
4101 i915_pineview_get_mem_freq(dev);
4102 else if (IS_GEN5(dev))
4103 i915_ironlake_get_mem_freq(dev);
4104
1fa61106
ED		 4105 /* For FIFO watermark updates */
4106 if (HAS_PCH_SPLIT(dev)) {
1fa61106
ED		 4107 if (IS_GEN5(dev)) {
4108 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
4109 dev_priv->display.update_wm = ironlake_update_wm;
4110 else {
4111 DRM_DEBUG_KMS("Failed to get proper latency. "
4112 "Disable CxSR\n");
4113 dev_priv->display.update_wm = NULL;
4114 }
4115 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
4116 } else if (IS_GEN6(dev)) {
4117 if (SNB_READ_WM0_LATENCY()) {
4118 dev_priv->display.update_wm = sandybridge_update_wm;
4119 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4120 } else {
4121 DRM_DEBUG_KMS("Failed to read display plane latency. "
4122 "Disable CxSR\n");
4123 dev_priv->display.update_wm = NULL;
4124 }
4125 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
4126 } else if (IS_IVYBRIDGE(dev)) {
4127 /* FIXME: detect B0+ stepping and use auto training */
4128 if (SNB_READ_WM0_LATENCY()) {
c43d0188 4129 dev_priv->display.update_wm = ivybridge_update_wm;
1fa61106
ED		 4130 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4131 } else {
4132 DRM_DEBUG_KMS("Failed to read display plane latency. "
4133 "Disable CxSR\n");
4134 dev_priv->display.update_wm = NULL;
4135 }
4136 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6b8a5eeb
ED		 4137 } else if (IS_HASWELL(dev)) {
4138 if (SNB_READ_WM0_LATENCY()) {
4139 dev_priv->display.update_wm = sandybridge_update_wm;
4140 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
1f8eeabf 4141 dev_priv->display.update_linetime_wm = haswell_update_linetime_wm;
6b8a5eeb
ED		 4142 } else {
4143 DRM_DEBUG_KMS("Failed to read display plane latency. "
4144 "Disable CxSR\n");
4145 dev_priv->display.update_wm = NULL;
4146 }
cad2a2d7 4147 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
1fa61106
ED		 4148 } else
4149 dev_priv->display.update_wm = NULL;
4150 } else if (IS_VALLEYVIEW(dev)) {
4151 dev_priv->display.update_wm = valleyview_update_wm;
4152 dev_priv->display.init_clock_gating =
4153 valleyview_init_clock_gating;
1fa61106
ED		 4154 } else if (IS_PINEVIEW(dev)) {
4155 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4156 dev_priv->is_ddr3,
4157 dev_priv->fsb_freq,
4158 dev_priv->mem_freq)) {
4159 DRM_INFO("failed to find known CxSR latency "
4160 "(found ddr%s fsb freq %d, mem freq %d), "
4161 "disabling CxSR\n",
4162 (dev_priv->is_ddr3 == 1) ? "3" : "2",
4163 dev_priv->fsb_freq, dev_priv->mem_freq);
4164 /* Disable CxSR and never update its watermark again */
4165 pineview_disable_cxsr(dev);
4166 dev_priv->display.update_wm = NULL;
4167 } else
4168 dev_priv->display.update_wm = pineview_update_wm;
4169 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4170 } else if (IS_G4X(dev)) {
4171 dev_priv->display.update_wm = g4x_update_wm;
4172 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
4173 } else if (IS_GEN4(dev)) {
4174 dev_priv->display.update_wm = i965_update_wm;
4175 if (IS_CRESTLINE(dev))
4176 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
4177 else if (IS_BROADWATER(dev))
4178 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
4179 } else if (IS_GEN3(dev)) {
4180 dev_priv->display.update_wm = i9xx_update_wm;
4181 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4182 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4183 } else if (IS_I865G(dev)) {
4184 dev_priv->display.update_wm = i830_update_wm;
4185 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4186 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4187 } else if (IS_I85X(dev)) {
4188 dev_priv->display.update_wm = i9xx_update_wm;
4189 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4190 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4191 } else {
4192 dev_priv->display.update_wm = i830_update_wm;
4193 dev_priv->display.init_clock_gating = i830_init_clock_gating;
4194 if (IS_845G(dev))
4195 dev_priv->display.get_fifo_size = i845_get_fifo_size;
4196 else
4197 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4198 }
4199}
4200
6590190d
ED		 4201static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
4202{
4203 u32 gt_thread_status_mask;
4204
4205 if (IS_HASWELL(dev_priv->dev))
4206 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
4207 else
4208 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
4209
4210 /* w/a for a sporadic read returning 0 by waiting for the GT
4211 * thread to wake up.
4212 */
4213 if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
4214 DRM_ERROR("GT thread status wait timed out\n");
4215}
4216
16995a9f
CW		 4217static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
4218{
4219 I915_WRITE_NOTRACE(FORCEWAKE, 0);
4220 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4221}
4222
6590190d
ED		 4223static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4224{
4225 u32 forcewake_ack;
4226
4227 if (IS_HASWELL(dev_priv->dev))
4228 forcewake_ack = FORCEWAKE_ACK_HSW;
4229 else
4230 forcewake_ack = FORCEWAKE_ACK;
4231
057d3860
BW		 4232 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0,
4233 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4234 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
6590190d 4235
c5836c27 4236 I915_WRITE_NOTRACE(FORCEWAKE, FORCEWAKE_KERNEL);
8dee3eea 4237 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
6590190d 4238
057d3860
BW		 4239 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1),
4240 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4241 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
6590190d
ED		 4242
4243 __gen6_gt_wait_for_thread_c0(dev_priv);
4244}
4245
16995a9f
CW		 4246static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
4247{
4248 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
4249 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4250}
4251
6590190d
ED		 4252static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
4253{
4254 u32 forcewake_ack;
4255
4256 if (IS_HASWELL(dev_priv->dev))
4257 forcewake_ack = FORCEWAKE_ACK_HSW;
4258 else
4259 forcewake_ack = FORCEWAKE_MT_ACK;
4260
057d3860
BW		 4261 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0,
4262 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4263 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
6590190d 4264
c5836c27 4265 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
8dee3eea 4266 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
6590190d 4267
057d3860
BW		 4268 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1),
4269 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4270 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
6590190d
ED		 4271
4272 __gen6_gt_wait_for_thread_c0(dev_priv);
4273}
4274
4275/*
4276 * Generally this is called implicitly by the register read function. However,
4277 * if some sequence requires the GT to not power down then this function should
4278 * be called at the beginning of the sequence followed by a call to
4279 * gen6_gt_force_wake_put() at the end of the sequence.
4280 */
4281void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4282{
4283 unsigned long irqflags;
4284
4285 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4286 if (dev_priv->forcewake_count++ == 0)
4287 dev_priv->gt.force_wake_get(dev_priv);
4288 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4289}
4290
4291void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
4292{
4293 u32 gtfifodbg;
4294 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
4295 if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
4296 "MMIO read or write has been dropped %x\n", gtfifodbg))
4297 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
4298}
4299
4300static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4301{
4302 I915_WRITE_NOTRACE(FORCEWAKE, 0);
8dee3eea 4303 /* gen6_gt_check_fifodbg doubles as the POSTING_READ */
6590190d
ED		 4304 gen6_gt_check_fifodbg(dev_priv);
4305}
4306
4307static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
4308{
c5836c27 4309 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
8dee3eea 4310 /* gen6_gt_check_fifodbg doubles as the POSTING_READ */
6590190d
ED		 4311 gen6_gt_check_fifodbg(dev_priv);
4312}
4313
4314/*
4315 * see gen6_gt_force_wake_get()
4316 */
4317void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4318{
4319 unsigned long irqflags;
4320
4321 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4322 if (--dev_priv->forcewake_count == 0)
4323 dev_priv->gt.force_wake_put(dev_priv);
4324 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4325}
4326
4327int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
4328{
4329 int ret = 0;
4330
4331 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
4332 int loop = 500;
4333 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4334 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
4335 udelay(10);
4336 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4337 }
4338 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
4339 ++ret;
4340 dev_priv->gt_fifo_count = fifo;
4341 }
4342 dev_priv->gt_fifo_count--;
4343
4344 return ret;
4345}
4346
16995a9f
CW		 4347static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
4348{
4349 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff));
4350}
4351
6590190d
ED		 4352static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
4353{
057d3860
BW		 4354 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0,
4355 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4356 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
6590190d 4357
c5836c27 4358 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
6590190d 4359
057d3860
BW		 4360 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1),
4361 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4362 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
6590190d
ED		 4363
4364 __gen6_gt_wait_for_thread_c0(dev_priv);
4365}
4366
4367static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
4368{
c5836c27 4369 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
5ab140a4
DV		 4370 /* The below doubles as a POSTING_READ */
4371 gen6_gt_check_fifodbg(dev_priv);
6590190d
ED		 4372}
4373
16995a9f
CW		 4374void intel_gt_reset(struct drm_device *dev)
4375{
4376 struct drm_i915_private *dev_priv = dev->dev_private;
4377
4378 if (IS_VALLEYVIEW(dev)) {
4379 vlv_force_wake_reset(dev_priv);
4380 } else if (INTEL_INFO(dev)->gen >= 6) {
4381 __gen6_gt_force_wake_reset(dev_priv);
4382 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4383 __gen6_gt_force_wake_mt_reset(dev_priv);
4384 }
4385}
4386
6590190d
ED		 4387void intel_gt_init(struct drm_device *dev)
4388{
4389 struct drm_i915_private *dev_priv = dev->dev_private;
4390
4391 spin_lock_init(&dev_priv->gt_lock);
4392
16995a9f
CW		 4393 intel_gt_reset(dev);
4394
6590190d
ED		 4395 if (IS_VALLEYVIEW(dev)) {
4396 dev_priv->gt.force_wake_get = vlv_force_wake_get;
4397 dev_priv->gt.force_wake_put = vlv_force_wake_put;
36ec8f87
DV		 4398 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4399 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get;
4400 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put;
4401 } else if (IS_GEN6(dev)) {
6590190d
ED		 4402 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
4403 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
6590190d 4404 }
1a01ab3b
JB		 4405 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
4406 intel_gen6_powersave_work);
6590190d
ED		 4407}
4408
42c0526c
BW		 4409int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
4410{
4fc688ce 4411 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 4412
4413 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4414 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
4415 return -EAGAIN;
4416 }
4417
4418 I915_WRITE(GEN6_PCODE_DATA, *val);
4419 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4420
4421 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4422 500)) {
4423 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
4424 return -ETIMEDOUT;
4425 }
4426
4427 *val = I915_READ(GEN6_PCODE_DATA);
4428 I915_WRITE(GEN6_PCODE_DATA, 0);
4429
4430 return 0;
4431}
4432
4433int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
4434{
4fc688ce 4435 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 4436
4437 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4438 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
4439 return -EAGAIN;
4440 }
4441
4442 I915_WRITE(GEN6_PCODE_DATA, val);
4443 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4444
4445 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4446 500)) {
4447 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
4448 return -ETIMEDOUT;
4449 }
4450
4451 I915_WRITE(GEN6_PCODE_DATA, 0);
4452
4453 return 0;
4454}
Linux 6.x block layer and io_uring tree(s)