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drm/i915: drop DRM_ERROR in intel_fbdev init
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
f4db9321 33#include <drm/i915_powerwell.h>
85208be0 34
dc39fff7
BW		 35/**
36 * RC6 is a special power stage which allows the GPU to enter an very
37 * low-voltage mode when idle, using down to 0V while at this stage. This
38 * stage is entered automatically when the GPU is idle when RC6 support is
39 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
40 *
41 * There are different RC6 modes available in Intel GPU, which differentiate
42 * among each other with the latency required to enter and leave RC6 and
43 * voltage consumed by the GPU in different states.
44 *
45 * The combination of the following flags define which states GPU is allowed
46 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
47 * RC6pp is deepest RC6. Their support by hardware varies according to the
48 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
49 * which brings the most power savings; deeper states save more power, but
50 * require higher latency to switch to and wake up.
51 */
52#define INTEL_RC6_ENABLE (1<<0)
53#define INTEL_RC6p_ENABLE (1<<1)
54#define INTEL_RC6pp_ENABLE (1<<2)
55
f6750b3c
ED		 56/* FBC, or Frame Buffer Compression, is a technique employed to compress the
57 * framebuffer contents in-memory, aiming at reducing the required bandwidth
58 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 59 *
f6750b3c
ED		 60 * The benefits of FBC are mostly visible with solid backgrounds and
61 * variation-less patterns.
85208be0 62 *
f6750b3c
ED		 63 * FBC-related functionality can be enabled by the means of the
64 * i915.i915_enable_fbc parameter
85208be0
ED		 65 */
66
1fa61106 67static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 68{
69 struct drm_i915_private *dev_priv = dev->dev_private;
70 u32 fbc_ctl;
71
72 /* Disable compression */
73 fbc_ctl = I915_READ(FBC_CONTROL);
74 if ((fbc_ctl & FBC_CTL_EN) == 0)
75 return;
76
77 fbc_ctl &= ~FBC_CTL_EN;
78 I915_WRITE(FBC_CONTROL, fbc_ctl);
79
80 /* Wait for compressing bit to clear */
81 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
82 DRM_DEBUG_KMS("FBC idle timed out\n");
83 return;
84 }
85
86 DRM_DEBUG_KMS("disabled FBC\n");
87}
88
1fa61106 89static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 90{
91 struct drm_device *dev = crtc->dev;
92 struct drm_i915_private *dev_priv = dev->dev_private;
93 struct drm_framebuffer *fb = crtc->fb;
94 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
95 struct drm_i915_gem_object *obj = intel_fb->obj;
96 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
97 int cfb_pitch;
98 int plane, i;
99 u32 fbc_ctl, fbc_ctl2;
100
5c3fe8b0 101 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
85208be0
ED		 102 if (fb->pitches[0] < cfb_pitch)
103 cfb_pitch = fb->pitches[0];
104
105 /* FBC_CTL wants 64B units */
106 cfb_pitch = (cfb_pitch / 64) - 1;
107 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
108
109 /* Clear old tags */
110 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
111 I915_WRITE(FBC_TAG + (i * 4), 0);
112
113 /* Set it up... */
114 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
115 fbc_ctl2 |= plane;
116 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
117 I915_WRITE(FBC_FENCE_OFF, crtc->y);
118
119 /* enable it... */
120 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
121 if (IS_I945GM(dev))
122 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
123 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
124 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
125 fbc_ctl |= obj->fence_reg;
126 I915_WRITE(FBC_CONTROL, fbc_ctl);
127
84f44ce7
VS		 128 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
129 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 130}
131
1fa61106 132static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 133{
134 struct drm_i915_private *dev_priv = dev->dev_private;
135
136 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
137}
138
1fa61106 139static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 140{
141 struct drm_device *dev = crtc->dev;
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 struct drm_framebuffer *fb = crtc->fb;
144 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
145 struct drm_i915_gem_object *obj = intel_fb->obj;
146 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
147 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
148 unsigned long stall_watermark = 200;
149 u32 dpfc_ctl;
150
151 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
152 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
153 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
154
155 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
156 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
157 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
158 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
159
160 /* enable it... */
161 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
162
84f44ce7 163 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 164}
165
1fa61106 166static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 167{
168 struct drm_i915_private *dev_priv = dev->dev_private;
169 u32 dpfc_ctl;
170
171 /* Disable compression */
172 dpfc_ctl = I915_READ(DPFC_CONTROL);
173 if (dpfc_ctl & DPFC_CTL_EN) {
174 dpfc_ctl &= ~DPFC_CTL_EN;
175 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
176
177 DRM_DEBUG_KMS("disabled FBC\n");
178 }
179}
180
1fa61106 181static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 182{
183 struct drm_i915_private *dev_priv = dev->dev_private;
184
185 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
186}
187
188static void sandybridge_blit_fbc_update(struct drm_device *dev)
189{
190 struct drm_i915_private *dev_priv = dev->dev_private;
191 u32 blt_ecoskpd;
192
193 /* Make sure blitter notifies FBC of writes */
940aece4
D		 194
195 /* Blitter is part of Media powerwell on VLV. No impact of
196 * his param in other platforms for now */
197 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
c8d9a590 198
85208be0
ED		 199 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
200 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
201 GEN6_BLITTER_LOCK_SHIFT;
202 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
203 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
204 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
205 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
206 GEN6_BLITTER_LOCK_SHIFT);
207 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
208 POSTING_READ(GEN6_BLITTER_ECOSKPD);
c8d9a590 209
940aece4 210 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
85208be0
ED		 211}
212
1fa61106 213static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 214{
215 struct drm_device *dev = crtc->dev;
216 struct drm_i915_private *dev_priv = dev->dev_private;
217 struct drm_framebuffer *fb = crtc->fb;
218 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
219 struct drm_i915_gem_object *obj = intel_fb->obj;
220 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
221 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
222 unsigned long stall_watermark = 200;
223 u32 dpfc_ctl;
224
225 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
226 dpfc_ctl &= DPFC_RESERVED;
227 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
228 /* Set persistent mode for front-buffer rendering, ala X. */
229 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
d629336b
VS		 230 dpfc_ctl |= DPFC_CTL_FENCE_EN;
231 if (IS_GEN5(dev))
232 dpfc_ctl |= obj->fence_reg;
85208be0
ED		 233 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
234
235 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
236 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
237 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
238 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
f343c5f6 239 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
85208be0
ED		 240 /* enable it... */
241 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
242
243 if (IS_GEN6(dev)) {
244 I915_WRITE(SNB_DPFC_CTL_SA,
245 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
246 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
247 sandybridge_blit_fbc_update(dev);
248 }
249
84f44ce7 250 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 251}
252
1fa61106 253static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 254{
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 u32 dpfc_ctl;
257
258 /* Disable compression */
259 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
260 if (dpfc_ctl & DPFC_CTL_EN) {
261 dpfc_ctl &= ~DPFC_CTL_EN;
262 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
263
264 DRM_DEBUG_KMS("disabled FBC\n");
265 }
266}
267
1fa61106 268static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 269{
270 struct drm_i915_private *dev_priv = dev->dev_private;
271
272 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
273}
274
abe959c7
RV		 275static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
276{
277 struct drm_device *dev = crtc->dev;
278 struct drm_i915_private *dev_priv = dev->dev_private;
279 struct drm_framebuffer *fb = crtc->fb;
280 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
281 struct drm_i915_gem_object *obj = intel_fb->obj;
282 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
283
f343c5f6 284 I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
abe959c7
RV		 285
286 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
287 IVB_DPFC_CTL_FENCE_EN |
288 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
289
891348b2 290 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 291 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
891348b2 292 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
28554164 293 } else {
7dd23ba0 294 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
28554164
RV		 295 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
296 HSW_BYPASS_FBC_QUEUE);
891348b2 297 }
b74ea102 298
abe959c7
RV		 299 I915_WRITE(SNB_DPFC_CTL_SA,
300 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
301 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
302
303 sandybridge_blit_fbc_update(dev);
304
b19870ee 305 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
abe959c7
RV		 306}
307
85208be0
ED		 308bool intel_fbc_enabled(struct drm_device *dev)
309{
310 struct drm_i915_private *dev_priv = dev->dev_private;
311
312 if (!dev_priv->display.fbc_enabled)
313 return false;
314
315 return dev_priv->display.fbc_enabled(dev);
316}
317
318static void intel_fbc_work_fn(struct work_struct *__work)
319{
320 struct intel_fbc_work *work =
321 container_of(to_delayed_work(__work),
322 struct intel_fbc_work, work);
323 struct drm_device *dev = work->crtc->dev;
324 struct drm_i915_private *dev_priv = dev->dev_private;
325
326 mutex_lock(&dev->struct_mutex);
5c3fe8b0 327 if (work == dev_priv->fbc.fbc_work) {
85208be0
ED		 328 /* Double check that we haven't switched fb without cancelling
329 * the prior work.
330 */
331 if (work->crtc->fb == work->fb) {
332 dev_priv->display.enable_fbc(work->crtc,
333 work->interval);
334
5c3fe8b0
BW		 335 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
336 dev_priv->fbc.fb_id = work->crtc->fb->base.id;
337 dev_priv->fbc.y = work->crtc->y;
85208be0
ED		 338 }
339
5c3fe8b0 340 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 341 }
342 mutex_unlock(&dev->struct_mutex);
343
344 kfree(work);
345}
346
347static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
348{
5c3fe8b0 349 if (dev_priv->fbc.fbc_work == NULL)
85208be0
ED		 350 return;
351
352 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
353
354 /* Synchronisation is provided by struct_mutex and checking of
5c3fe8b0 355 * dev_priv->fbc.fbc_work, so we can perform the cancellation
85208be0
ED		 356 * entirely asynchronously.
357 */
5c3fe8b0 358 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
85208be0 359 /* tasklet was killed before being run, clean up */
5c3fe8b0 360 kfree(dev_priv->fbc.fbc_work);
85208be0
ED		 361
362 /* Mark the work as no longer wanted so that if it does
363 * wake-up (because the work was already running and waiting
364 * for our mutex), it will discover that is no longer
365 * necessary to run.
366 */
5c3fe8b0 367 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 368}
369
b63fb44c 370static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 371{
372 struct intel_fbc_work *work;
373 struct drm_device *dev = crtc->dev;
374 struct drm_i915_private *dev_priv = dev->dev_private;
375
376 if (!dev_priv->display.enable_fbc)
377 return;
378
379 intel_cancel_fbc_work(dev_priv);
380
b14c5679 381 work = kzalloc(sizeof(*work), GFP_KERNEL);
85208be0 382 if (work == NULL) {
6cdcb5e7 383 DRM_ERROR("Failed to allocate FBC work structure\n");
85208be0
ED		 384 dev_priv->display.enable_fbc(crtc, interval);
385 return;
386 }
387
388 work->crtc = crtc;
389 work->fb = crtc->fb;
390 work->interval = interval;
391 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
392
5c3fe8b0 393 dev_priv->fbc.fbc_work = work;
85208be0 394
85208be0
ED		 395 /* Delay the actual enabling to let pageflipping cease and the
396 * display to settle before starting the compression. Note that
397 * this delay also serves a second purpose: it allows for a
398 * vblank to pass after disabling the FBC before we attempt
399 * to modify the control registers.
400 *
401 * A more complicated solution would involve tracking vblanks
402 * following the termination of the page-flipping sequence
403 * and indeed performing the enable as a co-routine and not
404 * waiting synchronously upon the vblank.
7457d617
DL		 405 *
406 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
85208be0
ED		 407 */
408 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
409}
410
411void intel_disable_fbc(struct drm_device *dev)
412{
413 struct drm_i915_private *dev_priv = dev->dev_private;
414
415 intel_cancel_fbc_work(dev_priv);
416
417 if (!dev_priv->display.disable_fbc)
418 return;
419
420 dev_priv->display.disable_fbc(dev);
5c3fe8b0 421 dev_priv->fbc.plane = -1;
85208be0
ED		 422}
423
29ebf90f
CW		 424static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
425 enum no_fbc_reason reason)
426{
427 if (dev_priv->fbc.no_fbc_reason == reason)
428 return false;
429
430 dev_priv->fbc.no_fbc_reason = reason;
431 return true;
432}
433
85208be0
ED		 434/**
435 * intel_update_fbc - enable/disable FBC as needed
436 * @dev: the drm_device
437 *
438 * Set up the framebuffer compression hardware at mode set time. We
439 * enable it if possible:
440 * - plane A only (on pre-965)
441 * - no pixel mulitply/line duplication
442 * - no alpha buffer discard
443 * - no dual wide
f85da868 444 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
85208be0
ED		 445 *
446 * We can't assume that any compression will take place (worst case),
447 * so the compressed buffer has to be the same size as the uncompressed
448 * one. It also must reside (along with the line length buffer) in
449 * stolen memory.
450 *
451 * We need to enable/disable FBC on a global basis.
452 */
453void intel_update_fbc(struct drm_device *dev)
454{
455 struct drm_i915_private *dev_priv = dev->dev_private;
456 struct drm_crtc *crtc = NULL, *tmp_crtc;
457 struct intel_crtc *intel_crtc;
458 struct drm_framebuffer *fb;
459 struct intel_framebuffer *intel_fb;
460 struct drm_i915_gem_object *obj;
ef644fda 461 const struct drm_display_mode *adjusted_mode;
37327abd 462 unsigned int max_width, max_height;
85208be0 463
29ebf90f
CW		 464 if (!I915_HAS_FBC(dev)) {
465 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
85208be0 466 return;
29ebf90f 467 }
85208be0 468
29ebf90f
CW		 469 if (!i915_powersave) {
470 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
471 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0 472 return;
29ebf90f 473 }
85208be0
ED		 474
475 /*
476 * If FBC is already on, we just have to verify that we can
477 * keep it that way...
478 * Need to disable if:
479 * - more than one pipe is active
480 * - changing FBC params (stride, fence, mode)
481 * - new fb is too large to fit in compressed buffer
482 * - going to an unsupported config (interlace, pixel multiply, etc.)
483 */
484 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 485 if (intel_crtc_active(tmp_crtc) &&
4c445e0e 486 to_intel_crtc(tmp_crtc)->primary_enabled) {
85208be0 487 if (crtc) {
29ebf90f
CW		 488 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
489 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
85208be0
ED		 490 goto out_disable;
491 }
492 crtc = tmp_crtc;
493 }
494 }
495
496 if (!crtc || crtc->fb == NULL) {
29ebf90f
CW		 497 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
498 DRM_DEBUG_KMS("no output, disabling\n");
85208be0
ED		 499 goto out_disable;
500 }
501
502 intel_crtc = to_intel_crtc(crtc);
503 fb = crtc->fb;
504 intel_fb = to_intel_framebuffer(fb);
505 obj = intel_fb->obj;
ef644fda 506 adjusted_mode = &intel_crtc->config.adjusted_mode;
85208be0 507
8a5729a3
DL		 508 if (i915_enable_fbc < 0 &&
509 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
29ebf90f
CW		 510 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
511 DRM_DEBUG_KMS("disabled per chip default\n");
8a5729a3 512 goto out_disable;
85208be0 513 }
8a5729a3 514 if (!i915_enable_fbc) {
29ebf90f
CW		 515 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
516 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0
ED		 517 goto out_disable;
518 }
ef644fda
VS		 519 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
520 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
29ebf90f
CW		 521 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
522 DRM_DEBUG_KMS("mode incompatible with compression, "
523 "disabling\n");
85208be0
ED		 524 goto out_disable;
525 }
f85da868
PZ		 526
527 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
37327abd
VS		 528 max_width = 4096;
529 max_height = 2048;
f85da868 530 } else {
37327abd
VS		 531 max_width = 2048;
532 max_height = 1536;
f85da868 533 }
37327abd
VS		 534 if (intel_crtc->config.pipe_src_w > max_width ||
535 intel_crtc->config.pipe_src_h > max_height) {
29ebf90f
CW		 536 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
537 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
85208be0
ED		 538 goto out_disable;
539 }
891348b2
RV		 540 if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
541 intel_crtc->plane != 0) {
29ebf90f
CW		 542 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
543 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
85208be0
ED		 544 goto out_disable;
545 }
546
547 /* The use of a CPU fence is mandatory in order to detect writes
548 * by the CPU to the scanout and trigger updates to the FBC.
549 */
550 if (obj->tiling_mode != I915_TILING_X ||
551 obj->fence_reg == I915_FENCE_REG_NONE) {
29ebf90f
CW		 552 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
553 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
85208be0
ED		 554 goto out_disable;
555 }
556
557 /* If the kernel debugger is active, always disable compression */
558 if (in_dbg_master())
559 goto out_disable;
560
11be49eb 561 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
29ebf90f
CW		 562 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
563 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
11be49eb
CW		 564 goto out_disable;
565 }
566
85208be0
ED		 567 /* If the scanout has not changed, don't modify the FBC settings.
568 * Note that we make the fundamental assumption that the fb->obj
569 * cannot be unpinned (and have its GTT offset and fence revoked)
570 * without first being decoupled from the scanout and FBC disabled.
571 */
5c3fe8b0
BW		 572 if (dev_priv->fbc.plane == intel_crtc->plane &&
573 dev_priv->fbc.fb_id == fb->base.id &&
574 dev_priv->fbc.y == crtc->y)
85208be0
ED		 575 return;
576
577 if (intel_fbc_enabled(dev)) {
578 /* We update FBC along two paths, after changing fb/crtc
579 * configuration (modeswitching) and after page-flipping
580 * finishes. For the latter, we know that not only did
581 * we disable the FBC at the start of the page-flip
582 * sequence, but also more than one vblank has passed.
583 *
584 * For the former case of modeswitching, it is possible
585 * to switch between two FBC valid configurations
586 * instantaneously so we do need to disable the FBC
587 * before we can modify its control registers. We also
588 * have to wait for the next vblank for that to take
589 * effect. However, since we delay enabling FBC we can
590 * assume that a vblank has passed since disabling and
591 * that we can safely alter the registers in the deferred
592 * callback.
593 *
594 * In the scenario that we go from a valid to invalid
595 * and then back to valid FBC configuration we have
596 * no strict enforcement that a vblank occurred since
597 * disabling the FBC. However, along all current pipe
598 * disabling paths we do need to wait for a vblank at
599 * some point. And we wait before enabling FBC anyway.
600 */
601 DRM_DEBUG_KMS("disabling active FBC for update\n");
602 intel_disable_fbc(dev);
603 }
604
605 intel_enable_fbc(crtc, 500);
29ebf90f 606 dev_priv->fbc.no_fbc_reason = FBC_OK;
85208be0
ED		 607 return;
608
609out_disable:
610 /* Multiple disables should be harmless */
611 if (intel_fbc_enabled(dev)) {
612 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
613 intel_disable_fbc(dev);
614 }
11be49eb 615 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 616}
617
c921aba8
DV		 618static void i915_pineview_get_mem_freq(struct drm_device *dev)
619{
620 drm_i915_private_t *dev_priv = dev->dev_private;
621 u32 tmp;
622
623 tmp = I915_READ(CLKCFG);
624
625 switch (tmp & CLKCFG_FSB_MASK) {
626 case CLKCFG_FSB_533:
627 dev_priv->fsb_freq = 533; /* 133*4 */
628 break;
629 case CLKCFG_FSB_800:
630 dev_priv->fsb_freq = 800; /* 200*4 */
631 break;
632 case CLKCFG_FSB_667:
633 dev_priv->fsb_freq = 667; /* 167*4 */
634 break;
635 case CLKCFG_FSB_400:
636 dev_priv->fsb_freq = 400; /* 100*4 */
637 break;
638 }
639
640 switch (tmp & CLKCFG_MEM_MASK) {
641 case CLKCFG_MEM_533:
642 dev_priv->mem_freq = 533;
643 break;
644 case CLKCFG_MEM_667:
645 dev_priv->mem_freq = 667;
646 break;
647 case CLKCFG_MEM_800:
648 dev_priv->mem_freq = 800;
649 break;
650 }
651
652 /* detect pineview DDR3 setting */
653 tmp = I915_READ(CSHRDDR3CTL);
654 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
655}
656
657static void i915_ironlake_get_mem_freq(struct drm_device *dev)
658{
659 drm_i915_private_t *dev_priv = dev->dev_private;
660 u16 ddrpll, csipll;
661
662 ddrpll = I915_READ16(DDRMPLL1);
663 csipll = I915_READ16(CSIPLL0);
664
665 switch (ddrpll & 0xff) {
666 case 0xc:
667 dev_priv->mem_freq = 800;
668 break;
669 case 0x10:
670 dev_priv->mem_freq = 1066;
671 break;
672 case 0x14:
673 dev_priv->mem_freq = 1333;
674 break;
675 case 0x18:
676 dev_priv->mem_freq = 1600;
677 break;
678 default:
679 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
680 ddrpll & 0xff);
681 dev_priv->mem_freq = 0;
682 break;
683 }
684
20e4d407 685 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 686
687 switch (csipll & 0x3ff) {
688 case 0x00c:
689 dev_priv->fsb_freq = 3200;
690 break;
691 case 0x00e:
692 dev_priv->fsb_freq = 3733;
693 break;
694 case 0x010:
695 dev_priv->fsb_freq = 4266;
696 break;
697 case 0x012:
698 dev_priv->fsb_freq = 4800;
699 break;
700 case 0x014:
701 dev_priv->fsb_freq = 5333;
702 break;
703 case 0x016:
704 dev_priv->fsb_freq = 5866;
705 break;
706 case 0x018:
707 dev_priv->fsb_freq = 6400;
708 break;
709 default:
710 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
711 csipll & 0x3ff);
712 dev_priv->fsb_freq = 0;
713 break;
714 }
715
716 if (dev_priv->fsb_freq == 3200) {
20e4d407 717 dev_priv->ips.c_m = 0;
c921aba8 718 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 719 dev_priv->ips.c_m = 1;
c921aba8 720 } else {
20e4d407 721 dev_priv->ips.c_m = 2;
c921aba8
DV		 722 }
723}
724
b445e3b0
ED		 725static const struct cxsr_latency cxsr_latency_table[] = {
726 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
727 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
728 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
729 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
730 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
731
732 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
733 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
734 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
735 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
736 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
737
738 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
739 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
740 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
741 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
742 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
743
744 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
745 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
746 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
747 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
748 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
749
750 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
751 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
752 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
753 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
754 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
755
756 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
757 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
758 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
759 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
760 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
761};
762
63c62275 763static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 764 int is_ddr3,
765 int fsb,
766 int mem)
767{
768 const struct cxsr_latency *latency;
769 int i;
770
771 if (fsb == 0 || mem == 0)
772 return NULL;
773
774 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
775 latency = &cxsr_latency_table[i];
776 if (is_desktop == latency->is_desktop &&
777 is_ddr3 == latency->is_ddr3 &&
778 fsb == latency->fsb_freq && mem == latency->mem_freq)
779 return latency;
780 }
781
782 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
783
784 return NULL;
785}
786
1fa61106 787static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 788{
789 struct drm_i915_private *dev_priv = dev->dev_private;
790
791 /* deactivate cxsr */
792 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
793}
794
795/*
796 * Latency for FIFO fetches is dependent on several factors:
797 * - memory configuration (speed, channels)
798 * - chipset
799 * - current MCH state
800 * It can be fairly high in some situations, so here we assume a fairly
801 * pessimal value. It's a tradeoff between extra memory fetches (if we
802 * set this value too high, the FIFO will fetch frequently to stay full)
803 * and power consumption (set it too low to save power and we might see
804 * FIFO underruns and display "flicker").
805 *
806 * A value of 5us seems to be a good balance; safe for very low end
807 * platforms but not overly aggressive on lower latency configs.
808 */
809static const int latency_ns = 5000;
810
1fa61106 811static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 812{
813 struct drm_i915_private *dev_priv = dev->dev_private;
814 uint32_t dsparb = I915_READ(DSPARB);
815 int size;
816
817 size = dsparb & 0x7f;
818 if (plane)
819 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
820
821 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
822 plane ? "B" : "A", size);
823
824 return size;
825}
826
1fa61106 827static int i85x_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 828{
829 struct drm_i915_private *dev_priv = dev->dev_private;
830 uint32_t dsparb = I915_READ(DSPARB);
831 int size;
832
833 size = dsparb & 0x1ff;
834 if (plane)
835 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
836 size >>= 1; /* Convert to cachelines */
837
838 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
839 plane ? "B" : "A", size);
840
841 return size;
842}
843
1fa61106 844static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 845{
846 struct drm_i915_private *dev_priv = dev->dev_private;
847 uint32_t dsparb = I915_READ(DSPARB);
848 int size;
849
850 size = dsparb & 0x7f;
851 size >>= 2; /* Convert to cachelines */
852
853 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
854 plane ? "B" : "A",
855 size);
856
857 return size;
858}
859
1fa61106 860static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 861{
862 struct drm_i915_private *dev_priv = dev->dev_private;
863 uint32_t dsparb = I915_READ(DSPARB);
864 int size;
865
866 size = dsparb & 0x7f;
867 size >>= 1; /* Convert to cachelines */
868
869 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
870 plane ? "B" : "A", size);
871
872 return size;
873}
874
875/* Pineview has different values for various configs */
876static const struct intel_watermark_params pineview_display_wm = {
877 PINEVIEW_DISPLAY_FIFO,
878 PINEVIEW_MAX_WM,
879 PINEVIEW_DFT_WM,
880 PINEVIEW_GUARD_WM,
881 PINEVIEW_FIFO_LINE_SIZE
882};
883static const struct intel_watermark_params pineview_display_hplloff_wm = {
884 PINEVIEW_DISPLAY_FIFO,
885 PINEVIEW_MAX_WM,
886 PINEVIEW_DFT_HPLLOFF_WM,
887 PINEVIEW_GUARD_WM,
888 PINEVIEW_FIFO_LINE_SIZE
889};
890static const struct intel_watermark_params pineview_cursor_wm = {
891 PINEVIEW_CURSOR_FIFO,
892 PINEVIEW_CURSOR_MAX_WM,
893 PINEVIEW_CURSOR_DFT_WM,
894 PINEVIEW_CURSOR_GUARD_WM,
895 PINEVIEW_FIFO_LINE_SIZE,
896};
897static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
898 PINEVIEW_CURSOR_FIFO,
899 PINEVIEW_CURSOR_MAX_WM,
900 PINEVIEW_CURSOR_DFT_WM,
901 PINEVIEW_CURSOR_GUARD_WM,
902 PINEVIEW_FIFO_LINE_SIZE
903};
904static const struct intel_watermark_params g4x_wm_info = {
905 G4X_FIFO_SIZE,
906 G4X_MAX_WM,
907 G4X_MAX_WM,
908 2,
909 G4X_FIFO_LINE_SIZE,
910};
911static const struct intel_watermark_params g4x_cursor_wm_info = {
912 I965_CURSOR_FIFO,
913 I965_CURSOR_MAX_WM,
914 I965_CURSOR_DFT_WM,
915 2,
916 G4X_FIFO_LINE_SIZE,
917};
918static const struct intel_watermark_params valleyview_wm_info = {
919 VALLEYVIEW_FIFO_SIZE,
920 VALLEYVIEW_MAX_WM,
921 VALLEYVIEW_MAX_WM,
922 2,
923 G4X_FIFO_LINE_SIZE,
924};
925static const struct intel_watermark_params valleyview_cursor_wm_info = {
926 I965_CURSOR_FIFO,
927 VALLEYVIEW_CURSOR_MAX_WM,
928 I965_CURSOR_DFT_WM,
929 2,
930 G4X_FIFO_LINE_SIZE,
931};
932static const struct intel_watermark_params i965_cursor_wm_info = {
933 I965_CURSOR_FIFO,
934 I965_CURSOR_MAX_WM,
935 I965_CURSOR_DFT_WM,
936 2,
937 I915_FIFO_LINE_SIZE,
938};
939static const struct intel_watermark_params i945_wm_info = {
940 I945_FIFO_SIZE,
941 I915_MAX_WM,
942 1,
943 2,
944 I915_FIFO_LINE_SIZE
945};
946static const struct intel_watermark_params i915_wm_info = {
947 I915_FIFO_SIZE,
948 I915_MAX_WM,
949 1,
950 2,
951 I915_FIFO_LINE_SIZE
952};
953static const struct intel_watermark_params i855_wm_info = {
954 I855GM_FIFO_SIZE,
955 I915_MAX_WM,
956 1,
957 2,
958 I830_FIFO_LINE_SIZE
959};
960static const struct intel_watermark_params i830_wm_info = {
961 I830_FIFO_SIZE,
962 I915_MAX_WM,
963 1,
964 2,
965 I830_FIFO_LINE_SIZE
966};
967
968static const struct intel_watermark_params ironlake_display_wm_info = {
969 ILK_DISPLAY_FIFO,
970 ILK_DISPLAY_MAXWM,
971 ILK_DISPLAY_DFTWM,
972 2,
973 ILK_FIFO_LINE_SIZE
974};
975static const struct intel_watermark_params ironlake_cursor_wm_info = {
976 ILK_CURSOR_FIFO,
977 ILK_CURSOR_MAXWM,
978 ILK_CURSOR_DFTWM,
979 2,
980 ILK_FIFO_LINE_SIZE
981};
982static const struct intel_watermark_params ironlake_display_srwm_info = {
983 ILK_DISPLAY_SR_FIFO,
984 ILK_DISPLAY_MAX_SRWM,
985 ILK_DISPLAY_DFT_SRWM,
986 2,
987 ILK_FIFO_LINE_SIZE
988};
989static const struct intel_watermark_params ironlake_cursor_srwm_info = {
990 ILK_CURSOR_SR_FIFO,
991 ILK_CURSOR_MAX_SRWM,
992 ILK_CURSOR_DFT_SRWM,
993 2,
994 ILK_FIFO_LINE_SIZE
995};
996
997static const struct intel_watermark_params sandybridge_display_wm_info = {
998 SNB_DISPLAY_FIFO,
999 SNB_DISPLAY_MAXWM,
1000 SNB_DISPLAY_DFTWM,
1001 2,
1002 SNB_FIFO_LINE_SIZE
1003};
1004static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1005 SNB_CURSOR_FIFO,
1006 SNB_CURSOR_MAXWM,
1007 SNB_CURSOR_DFTWM,
1008 2,
1009 SNB_FIFO_LINE_SIZE
1010};
1011static const struct intel_watermark_params sandybridge_display_srwm_info = {
1012 SNB_DISPLAY_SR_FIFO,
1013 SNB_DISPLAY_MAX_SRWM,
1014 SNB_DISPLAY_DFT_SRWM,
1015 2,
1016 SNB_FIFO_LINE_SIZE
1017};
1018static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1019 SNB_CURSOR_SR_FIFO,
1020 SNB_CURSOR_MAX_SRWM,
1021 SNB_CURSOR_DFT_SRWM,
1022 2,
1023 SNB_FIFO_LINE_SIZE
1024};
1025
1026
1027/**
1028 * intel_calculate_wm - calculate watermark level
1029 * @clock_in_khz: pixel clock
1030 * @wm: chip FIFO params
1031 * @pixel_size: display pixel size
1032 * @latency_ns: memory latency for the platform
1033 *
1034 * Calculate the watermark level (the level at which the display plane will
1035 * start fetching from memory again). Each chip has a different display
1036 * FIFO size and allocation, so the caller needs to figure that out and pass
1037 * in the correct intel_watermark_params structure.
1038 *
1039 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1040 * on the pixel size. When it reaches the watermark level, it'll start
1041 * fetching FIFO line sized based chunks from memory until the FIFO fills
1042 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1043 * will occur, and a display engine hang could result.
1044 */
1045static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1046 const struct intel_watermark_params *wm,
1047 int fifo_size,
1048 int pixel_size,
1049 unsigned long latency_ns)
1050{
1051 long entries_required, wm_size;
1052
1053 /*
1054 * Note: we need to make sure we don't overflow for various clock &
1055 * latency values.
1056 * clocks go from a few thousand to several hundred thousand.
1057 * latency is usually a few thousand
1058 */
1059 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1060 1000;
1061 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1062
1063 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1064
1065 wm_size = fifo_size - (entries_required + wm->guard_size);
1066
1067 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1068
1069 /* Don't promote wm_size to unsigned... */
1070 if (wm_size > (long)wm->max_wm)
1071 wm_size = wm->max_wm;
1072 if (wm_size <= 0)
1073 wm_size = wm->default_wm;
1074 return wm_size;
1075}
1076
1077static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1078{
1079 struct drm_crtc *crtc, *enabled = NULL;
1080
1081 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 1082 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1083 if (enabled)
1084 return NULL;
1085 enabled = crtc;
1086 }
1087 }
1088
1089 return enabled;
1090}
1091
46ba614c 1092static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1093{
46ba614c 1094 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1095 struct drm_i915_private *dev_priv = dev->dev_private;
1096 struct drm_crtc *crtc;
1097 const struct cxsr_latency *latency;
1098 u32 reg;
1099 unsigned long wm;
1100
1101 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1102 dev_priv->fsb_freq, dev_priv->mem_freq);
1103 if (!latency) {
1104 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1105 pineview_disable_cxsr(dev);
1106 return;
1107 }
1108
1109 crtc = single_enabled_crtc(dev);
1110 if (crtc) {
241bfc38 1111 const struct drm_display_mode *adjusted_mode;
b445e3b0 1112 int pixel_size = crtc->fb->bits_per_pixel / 8;
241bfc38
DL		 1113 int clock;
1114
1115 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1116 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 1117
1118 /* Display SR */
1119 wm = intel_calculate_wm(clock, &pineview_display_wm,
1120 pineview_display_wm.fifo_size,
1121 pixel_size, latency->display_sr);
1122 reg = I915_READ(DSPFW1);
1123 reg &= ~DSPFW_SR_MASK;
1124 reg |= wm << DSPFW_SR_SHIFT;
1125 I915_WRITE(DSPFW1, reg);
1126 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1127
1128 /* cursor SR */
1129 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1130 pineview_display_wm.fifo_size,
1131 pixel_size, latency->cursor_sr);
1132 reg = I915_READ(DSPFW3);
1133 reg &= ~DSPFW_CURSOR_SR_MASK;
1134 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1135 I915_WRITE(DSPFW3, reg);
1136
1137 /* Display HPLL off SR */
1138 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1139 pineview_display_hplloff_wm.fifo_size,
1140 pixel_size, latency->display_hpll_disable);
1141 reg = I915_READ(DSPFW3);
1142 reg &= ~DSPFW_HPLL_SR_MASK;
1143 reg |= wm & DSPFW_HPLL_SR_MASK;
1144 I915_WRITE(DSPFW3, reg);
1145
1146 /* cursor HPLL off SR */
1147 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1148 pineview_display_hplloff_wm.fifo_size,
1149 pixel_size, latency->cursor_hpll_disable);
1150 reg = I915_READ(DSPFW3);
1151 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1152 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1153 I915_WRITE(DSPFW3, reg);
1154 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1155
1156 /* activate cxsr */
1157 I915_WRITE(DSPFW3,
1158 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1159 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1160 } else {
1161 pineview_disable_cxsr(dev);
1162 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1163 }
1164}
1165
1166static bool g4x_compute_wm0(struct drm_device *dev,
1167 int plane,
1168 const struct intel_watermark_params *display,
1169 int display_latency_ns,
1170 const struct intel_watermark_params *cursor,
1171 int cursor_latency_ns,
1172 int *plane_wm,
1173 int *cursor_wm)
1174{
1175 struct drm_crtc *crtc;
4fe8590a 1176 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1177 int htotal, hdisplay, clock, pixel_size;
1178 int line_time_us, line_count;
1179 int entries, tlb_miss;
1180
1181 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1182 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1183 *cursor_wm = cursor->guard_size;
1184 *plane_wm = display->guard_size;
1185 return false;
1186 }
1187
4fe8590a 1188 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1189 clock = adjusted_mode->crtc_clock;
4fe8590a 1190 htotal = adjusted_mode->htotal;
37327abd 1191 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1192 pixel_size = crtc->fb->bits_per_pixel / 8;
1193
1194 /* Use the small buffer method to calculate plane watermark */
1195 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1196 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1197 if (tlb_miss > 0)
1198 entries += tlb_miss;
1199 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1200 *plane_wm = entries + display->guard_size;
1201 if (*plane_wm > (int)display->max_wm)
1202 *plane_wm = display->max_wm;
1203
1204 /* Use the large buffer method to calculate cursor watermark */
1205 line_time_us = ((htotal * 1000) / clock);
1206 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1207 entries = line_count * 64 * pixel_size;
1208 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1209 if (tlb_miss > 0)
1210 entries += tlb_miss;
1211 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1212 *cursor_wm = entries + cursor->guard_size;
1213 if (*cursor_wm > (int)cursor->max_wm)
1214 *cursor_wm = (int)cursor->max_wm;
1215
1216 return true;
1217}
1218
1219/*
1220 * Check the wm result.
1221 *
1222 * If any calculated watermark values is larger than the maximum value that
1223 * can be programmed into the associated watermark register, that watermark
1224 * must be disabled.
1225 */
1226static bool g4x_check_srwm(struct drm_device *dev,
1227 int display_wm, int cursor_wm,
1228 const struct intel_watermark_params *display,
1229 const struct intel_watermark_params *cursor)
1230{
1231 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1232 display_wm, cursor_wm);
1233
1234 if (display_wm > display->max_wm) {
1235 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1236 display_wm, display->max_wm);
1237 return false;
1238 }
1239
1240 if (cursor_wm > cursor->max_wm) {
1241 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1242 cursor_wm, cursor->max_wm);
1243 return false;
1244 }
1245
1246 if (!(display_wm || cursor_wm)) {
1247 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1248 return false;
1249 }
1250
1251 return true;
1252}
1253
1254static bool g4x_compute_srwm(struct drm_device *dev,
1255 int plane,
1256 int latency_ns,
1257 const struct intel_watermark_params *display,
1258 const struct intel_watermark_params *cursor,
1259 int *display_wm, int *cursor_wm)
1260{
1261 struct drm_crtc *crtc;
4fe8590a 1262 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1263 int hdisplay, htotal, pixel_size, clock;
1264 unsigned long line_time_us;
1265 int line_count, line_size;
1266 int small, large;
1267 int entries;
1268
1269 if (!latency_ns) {
1270 *display_wm = *cursor_wm = 0;
1271 return false;
1272 }
1273
1274 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a 1275 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1276 clock = adjusted_mode->crtc_clock;
4fe8590a 1277 htotal = adjusted_mode->htotal;
37327abd 1278 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1279 pixel_size = crtc->fb->bits_per_pixel / 8;
1280
1281 line_time_us = (htotal * 1000) / clock;
1282 line_count = (latency_ns / line_time_us + 1000) / 1000;
1283 line_size = hdisplay * pixel_size;
1284
1285 /* Use the minimum of the small and large buffer method for primary */
1286 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1287 large = line_count * line_size;
1288
1289 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1290 *display_wm = entries + display->guard_size;
1291
1292 /* calculate the self-refresh watermark for display cursor */
1293 entries = line_count * pixel_size * 64;
1294 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1295 *cursor_wm = entries + cursor->guard_size;
1296
1297 return g4x_check_srwm(dev,
1298 *display_wm, *cursor_wm,
1299 display, cursor);
1300}
1301
1302static bool vlv_compute_drain_latency(struct drm_device *dev,
1303 int plane,
1304 int *plane_prec_mult,
1305 int *plane_dl,
1306 int *cursor_prec_mult,
1307 int *cursor_dl)
1308{
1309 struct drm_crtc *crtc;
1310 int clock, pixel_size;
1311 int entries;
1312
1313 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1314 if (!intel_crtc_active(crtc))
b445e3b0
ED		 1315 return false;
1316
241bfc38 1317 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
b445e3b0
ED		 1318 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1319
1320 entries = (clock / 1000) * pixel_size;
1321 *plane_prec_mult = (entries > 256) ?
1322 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1323 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1324 pixel_size);
1325
1326 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1327 *cursor_prec_mult = (entries > 256) ?
1328 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1329 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1330
1331 return true;
1332}
1333
1334/*
1335 * Update drain latency registers of memory arbiter
1336 *
1337 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1338 * to be programmed. Each plane has a drain latency multiplier and a drain
1339 * latency value.
1340 */
1341
1342static void vlv_update_drain_latency(struct drm_device *dev)
1343{
1344 struct drm_i915_private *dev_priv = dev->dev_private;
1345 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1346 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1347 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1348 either 16 or 32 */
1349
1350 /* For plane A, Cursor A */
1351 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1352 &cursor_prec_mult, &cursora_dl)) {
1353 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1354 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1355 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1356 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1357
1358 I915_WRITE(VLV_DDL1, cursora_prec |
1359 (cursora_dl << DDL_CURSORA_SHIFT) |
1360 planea_prec | planea_dl);
1361 }
1362
1363 /* For plane B, Cursor B */
1364 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1365 &cursor_prec_mult, &cursorb_dl)) {
1366 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1367 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1368 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1369 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1370
1371 I915_WRITE(VLV_DDL2, cursorb_prec |
1372 (cursorb_dl << DDL_CURSORB_SHIFT) |
1373 planeb_prec | planeb_dl);
1374 }
1375}
1376
1377#define single_plane_enabled(mask) is_power_of_2(mask)
1378
46ba614c 1379static void valleyview_update_wm(struct drm_crtc *crtc)
b445e3b0 1380{
46ba614c 1381 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1382 static const int sr_latency_ns = 12000;
1383 struct drm_i915_private *dev_priv = dev->dev_private;
1384 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1385 int plane_sr, cursor_sr;
af6c4575 1386 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0
ED		 1387 unsigned int enabled = 0;
1388
1389 vlv_update_drain_latency(dev);
1390
51cea1f4 1391 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1392 &valleyview_wm_info, latency_ns,
1393 &valleyview_cursor_wm_info, latency_ns,
1394 &planea_wm, &cursora_wm))
51cea1f4 1395 enabled |= 1 << PIPE_A;
b445e3b0 1396
51cea1f4 1397 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1398 &valleyview_wm_info, latency_ns,
1399 &valleyview_cursor_wm_info, latency_ns,
1400 &planeb_wm, &cursorb_wm))
51cea1f4 1401 enabled |= 1 << PIPE_B;
b445e3b0 1402
b445e3b0
ED		 1403 if (single_plane_enabled(enabled) &&
1404 g4x_compute_srwm(dev, ffs(enabled) - 1,
1405 sr_latency_ns,
1406 &valleyview_wm_info,
1407 &valleyview_cursor_wm_info,
af6c4575
CW		 1408 &plane_sr, &ignore_cursor_sr) &&
1409 g4x_compute_srwm(dev, ffs(enabled) - 1,
1410 2*sr_latency_ns,
1411 &valleyview_wm_info,
1412 &valleyview_cursor_wm_info,
52bd02d8 1413 &ignore_plane_sr, &cursor_sr)) {
b445e3b0 1414 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
52bd02d8 1415 } else {
b445e3b0
ED		 1416 I915_WRITE(FW_BLC_SELF_VLV,
1417 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
52bd02d8
CW		 1418 plane_sr = cursor_sr = 0;
1419 }
b445e3b0
ED		 1420
1421 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1422 planea_wm, cursora_wm,
1423 planeb_wm, cursorb_wm,
1424 plane_sr, cursor_sr);
1425
1426 I915_WRITE(DSPFW1,
1427 (plane_sr << DSPFW_SR_SHIFT) |
1428 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1429 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1430 planea_wm);
1431 I915_WRITE(DSPFW2,
8c919b28 1432 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1433 (cursora_wm << DSPFW_CURSORA_SHIFT));
1434 I915_WRITE(DSPFW3,
8c919b28
CW		 1435 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1436 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
b445e3b0
ED		 1437}
1438
46ba614c 1439static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1440{
46ba614c 1441 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1442 static const int sr_latency_ns = 12000;
1443 struct drm_i915_private *dev_priv = dev->dev_private;
1444 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1445 int plane_sr, cursor_sr;
1446 unsigned int enabled = 0;
1447
51cea1f4 1448 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1449 &g4x_wm_info, latency_ns,
1450 &g4x_cursor_wm_info, latency_ns,
1451 &planea_wm, &cursora_wm))
51cea1f4 1452 enabled |= 1 << PIPE_A;
b445e3b0 1453
51cea1f4 1454 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1455 &g4x_wm_info, latency_ns,
1456 &g4x_cursor_wm_info, latency_ns,
1457 &planeb_wm, &cursorb_wm))
51cea1f4 1458 enabled |= 1 << PIPE_B;
b445e3b0 1459
b445e3b0
ED		 1460 if (single_plane_enabled(enabled) &&
1461 g4x_compute_srwm(dev, ffs(enabled) - 1,
1462 sr_latency_ns,
1463 &g4x_wm_info,
1464 &g4x_cursor_wm_info,
52bd02d8 1465 &plane_sr, &cursor_sr)) {
b445e3b0 1466 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
52bd02d8 1467 } else {
b445e3b0
ED		 1468 I915_WRITE(FW_BLC_SELF,
1469 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
52bd02d8
CW		 1470 plane_sr = cursor_sr = 0;
1471 }
b445e3b0
ED		 1472
1473 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1474 planea_wm, cursora_wm,
1475 planeb_wm, cursorb_wm,
1476 plane_sr, cursor_sr);
1477
1478 I915_WRITE(DSPFW1,
1479 (plane_sr << DSPFW_SR_SHIFT) |
1480 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1481 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1482 planea_wm);
1483 I915_WRITE(DSPFW2,
8c919b28 1484 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1485 (cursora_wm << DSPFW_CURSORA_SHIFT));
1486 /* HPLL off in SR has some issues on G4x... disable it */
1487 I915_WRITE(DSPFW3,
8c919b28 1488 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0
ED		 1489 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1490}
1491
46ba614c 1492static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1493{
46ba614c 1494 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1495 struct drm_i915_private *dev_priv = dev->dev_private;
1496 struct drm_crtc *crtc;
1497 int srwm = 1;
1498 int cursor_sr = 16;
1499
1500 /* Calc sr entries for one plane configs */
1501 crtc = single_enabled_crtc(dev);
1502 if (crtc) {
1503 /* self-refresh has much higher latency */
1504 static const int sr_latency_ns = 12000;
4fe8590a
VS		 1505 const struct drm_display_mode *adjusted_mode =
1506 &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1507 int clock = adjusted_mode->crtc_clock;
4fe8590a 1508 int htotal = adjusted_mode->htotal;
37327abd 1509 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1510 int pixel_size = crtc->fb->bits_per_pixel / 8;
1511 unsigned long line_time_us;
1512 int entries;
1513
1514 line_time_us = ((htotal * 1000) / clock);
1515
1516 /* Use ns/us then divide to preserve precision */
1517 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1518 pixel_size * hdisplay;
1519 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1520 srwm = I965_FIFO_SIZE - entries;
1521 if (srwm < 0)
1522 srwm = 1;
1523 srwm &= 0x1ff;
1524 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1525 entries, srwm);
1526
1527 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1528 pixel_size * 64;
1529 entries = DIV_ROUND_UP(entries,
1530 i965_cursor_wm_info.cacheline_size);
1531 cursor_sr = i965_cursor_wm_info.fifo_size -
1532 (entries + i965_cursor_wm_info.guard_size);
1533
1534 if (cursor_sr > i965_cursor_wm_info.max_wm)
1535 cursor_sr = i965_cursor_wm_info.max_wm;
1536
1537 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1538 "cursor %d\n", srwm, cursor_sr);
1539
1540 if (IS_CRESTLINE(dev))
1541 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1542 } else {
1543 /* Turn off self refresh if both pipes are enabled */
1544 if (IS_CRESTLINE(dev))
1545 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1546 & ~FW_BLC_SELF_EN);
1547 }
1548
1549 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1550 srwm);
1551
1552 /* 965 has limitations... */
1553 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1554 (8 << 16) | (8 << 8) | (8 << 0));
1555 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1556 /* update cursor SR watermark */
1557 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1558}
1559
46ba614c 1560static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1561{
46ba614c 1562 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1563 struct drm_i915_private *dev_priv = dev->dev_private;
1564 const struct intel_watermark_params *wm_info;
1565 uint32_t fwater_lo;
1566 uint32_t fwater_hi;
1567 int cwm, srwm = 1;
1568 int fifo_size;
1569 int planea_wm, planeb_wm;
1570 struct drm_crtc *crtc, *enabled = NULL;
1571
1572 if (IS_I945GM(dev))
1573 wm_info = &i945_wm_info;
1574 else if (!IS_GEN2(dev))
1575 wm_info = &i915_wm_info;
1576 else
1577 wm_info = &i855_wm_info;
1578
1579 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1580 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1581 if (intel_crtc_active(crtc)) {
241bfc38 1582 const struct drm_display_mode *adjusted_mode;
b9e0bda3
CW		 1583 int cpp = crtc->fb->bits_per_pixel / 8;
1584 if (IS_GEN2(dev))
1585 cpp = 4;
1586
241bfc38
DL		 1587 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1588 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1589 wm_info, fifo_size, cpp,
b445e3b0
ED		 1590 latency_ns);
1591 enabled = crtc;
1592 } else
1593 planea_wm = fifo_size - wm_info->guard_size;
1594
1595 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1596 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1597 if (intel_crtc_active(crtc)) {
241bfc38 1598 const struct drm_display_mode *adjusted_mode;
b9e0bda3
CW		 1599 int cpp = crtc->fb->bits_per_pixel / 8;
1600 if (IS_GEN2(dev))
1601 cpp = 4;
1602
241bfc38
DL		 1603 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1604 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1605 wm_info, fifo_size, cpp,
b445e3b0
ED		 1606 latency_ns);
1607 if (enabled == NULL)
1608 enabled = crtc;
1609 else
1610 enabled = NULL;
1611 } else
1612 planeb_wm = fifo_size - wm_info->guard_size;
1613
1614 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1615
1616 /*
1617 * Overlay gets an aggressive default since video jitter is bad.
1618 */
1619 cwm = 2;
1620
1621 /* Play safe and disable self-refresh before adjusting watermarks. */
1622 if (IS_I945G(dev) || IS_I945GM(dev))
1623 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1624 else if (IS_I915GM(dev))
1625 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1626
1627 /* Calc sr entries for one plane configs */
1628 if (HAS_FW_BLC(dev) && enabled) {
1629 /* self-refresh has much higher latency */
1630 static const int sr_latency_ns = 6000;
4fe8590a
VS		 1631 const struct drm_display_mode *adjusted_mode =
1632 &to_intel_crtc(enabled)->config.adjusted_mode;
241bfc38 1633 int clock = adjusted_mode->crtc_clock;
4fe8590a 1634 int htotal = adjusted_mode->htotal;
37327abd 1635 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1636 int pixel_size = enabled->fb->bits_per_pixel / 8;
1637 unsigned long line_time_us;
1638 int entries;
1639
1640 line_time_us = (htotal * 1000) / clock;
1641
1642 /* Use ns/us then divide to preserve precision */
1643 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1644 pixel_size * hdisplay;
1645 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1646 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1647 srwm = wm_info->fifo_size - entries;
1648 if (srwm < 0)
1649 srwm = 1;
1650
1651 if (IS_I945G(dev) || IS_I945GM(dev))
1652 I915_WRITE(FW_BLC_SELF,
1653 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1654 else if (IS_I915GM(dev))
1655 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1656 }
1657
1658 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1659 planea_wm, planeb_wm, cwm, srwm);
1660
1661 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1662 fwater_hi = (cwm & 0x1f);
1663
1664 /* Set request length to 8 cachelines per fetch */
1665 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1666 fwater_hi = fwater_hi | (1 << 8);
1667
1668 I915_WRITE(FW_BLC, fwater_lo);
1669 I915_WRITE(FW_BLC2, fwater_hi);
1670
1671 if (HAS_FW_BLC(dev)) {
1672 if (enabled) {
1673 if (IS_I945G(dev) || IS_I945GM(dev))
1674 I915_WRITE(FW_BLC_SELF,
1675 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1676 else if (IS_I915GM(dev))
1677 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1678 DRM_DEBUG_KMS("memory self refresh enabled\n");
1679 } else
1680 DRM_DEBUG_KMS("memory self refresh disabled\n");
1681 }
1682}
1683
46ba614c 1684static void i830_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1685{
46ba614c 1686 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1687 struct drm_i915_private *dev_priv = dev->dev_private;
1688 struct drm_crtc *crtc;
241bfc38 1689 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1690 uint32_t fwater_lo;
1691 int planea_wm;
1692
1693 crtc = single_enabled_crtc(dev);
1694 if (crtc == NULL)
1695 return;
1696
241bfc38
DL		 1697 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1698 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
4fe8590a 1699 &i830_wm_info,
b445e3b0 1700 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1701 4, latency_ns);
b445e3b0
ED		 1702 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1703 fwater_lo |= (3<<8) | planea_wm;
1704
1705 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1706
1707 I915_WRITE(FW_BLC, fwater_lo);
1708}
1709
b445e3b0
ED		 1710/*
1711 * Check the wm result.
1712 *
1713 * If any calculated watermark values is larger than the maximum value that
1714 * can be programmed into the associated watermark register, that watermark
1715 * must be disabled.
1716 */
1717static bool ironlake_check_srwm(struct drm_device *dev, int level,
1718 int fbc_wm, int display_wm, int cursor_wm,
1719 const struct intel_watermark_params *display,
1720 const struct intel_watermark_params *cursor)
1721{
1722 struct drm_i915_private *dev_priv = dev->dev_private;
1723
1724 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1725 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1726
1727 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1728 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1729 fbc_wm, SNB_FBC_MAX_SRWM, level);
1730
1731 /* fbc has it's own way to disable FBC WM */
1732 I915_WRITE(DISP_ARB_CTL,
1733 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1734 return false;
615aaa5f
VS		 1735 } else if (INTEL_INFO(dev)->gen >= 6) {
1736 /* enable FBC WM (except on ILK, where it must remain off) */
1737 I915_WRITE(DISP_ARB_CTL,
1738 I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
b445e3b0
ED		 1739 }
1740
1741 if (display_wm > display->max_wm) {
1742 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1743 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1744 return false;
1745 }
1746
1747 if (cursor_wm > cursor->max_wm) {
1748 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1749 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1750 return false;
1751 }
1752
1753 if (!(fbc_wm || display_wm || cursor_wm)) {
1754 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1755 return false;
1756 }
1757
1758 return true;
1759}
1760
1761/*
1762 * Compute watermark values of WM[1-3],
1763 */
1764static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1765 int latency_ns,
1766 const struct intel_watermark_params *display,
1767 const struct intel_watermark_params *cursor,
1768 int *fbc_wm, int *display_wm, int *cursor_wm)
1769{
1770 struct drm_crtc *crtc;
4fe8590a 1771 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1772 unsigned long line_time_us;
1773 int hdisplay, htotal, pixel_size, clock;
1774 int line_count, line_size;
1775 int small, large;
1776 int entries;
1777
1778 if (!latency_ns) {
1779 *fbc_wm = *display_wm = *cursor_wm = 0;
1780 return false;
1781 }
1782
1783 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a 1784 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1785 clock = adjusted_mode->crtc_clock;
4fe8590a 1786 htotal = adjusted_mode->htotal;
37327abd 1787 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1788 pixel_size = crtc->fb->bits_per_pixel / 8;
1789
1790 line_time_us = (htotal * 1000) / clock;
1791 line_count = (latency_ns / line_time_us + 1000) / 1000;
1792 line_size = hdisplay * pixel_size;
1793
1794 /* Use the minimum of the small and large buffer method for primary */
1795 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1796 large = line_count * line_size;
1797
1798 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1799 *display_wm = entries + display->guard_size;
1800
1801 /*
1802 * Spec says:
1803 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1804 */
1805 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1806
1807 /* calculate the self-refresh watermark for display cursor */
1808 entries = line_count * pixel_size * 64;
1809 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1810 *cursor_wm = entries + cursor->guard_size;
1811
1812 return ironlake_check_srwm(dev, level,
1813 *fbc_wm, *display_wm, *cursor_wm,
1814 display, cursor);
1815}
1816
46ba614c 1817static void ironlake_update_wm(struct drm_crtc *crtc)
b445e3b0 1818{
46ba614c 1819 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1820 struct drm_i915_private *dev_priv = dev->dev_private;
1821 int fbc_wm, plane_wm, cursor_wm;
1822 unsigned int enabled;
1823
1824 enabled = 0;
51cea1f4 1825 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0 1826 &ironlake_display_wm_info,
b0aea5dc 1827 dev_priv->wm.pri_latency[0] * 100,
b445e3b0 1828 &ironlake_cursor_wm_info,
b0aea5dc 1829 dev_priv->wm.cur_latency[0] * 100,
b445e3b0
ED		 1830 &plane_wm, &cursor_wm)) {
1831 I915_WRITE(WM0_PIPEA_ILK,
1832 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1833 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1834 " plane %d, " "cursor: %d\n",
1835 plane_wm, cursor_wm);
51cea1f4 1836 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1837 }
1838
51cea1f4 1839 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0 1840 &ironlake_display_wm_info,
b0aea5dc 1841 dev_priv->wm.pri_latency[0] * 100,
b445e3b0 1842 &ironlake_cursor_wm_info,
b0aea5dc 1843 dev_priv->wm.cur_latency[0] * 100,
b445e3b0
ED		 1844 &plane_wm, &cursor_wm)) {
1845 I915_WRITE(WM0_PIPEB_ILK,
1846 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1847 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1848 " plane %d, cursor: %d\n",
1849 plane_wm, cursor_wm);
51cea1f4 1850 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1851 }
1852
1853 /*
1854 * Calculate and update the self-refresh watermark only when one
1855 * display plane is used.
1856 */
1857 I915_WRITE(WM3_LP_ILK, 0);
1858 I915_WRITE(WM2_LP_ILK, 0);
1859 I915_WRITE(WM1_LP_ILK, 0);
1860
1861 if (!single_plane_enabled(enabled))
1862 return;
1863 enabled = ffs(enabled) - 1;
1864
1865 /* WM1 */
1866 if (!ironlake_compute_srwm(dev, 1, enabled,
b0aea5dc 1867 dev_priv->wm.pri_latency[1] * 500,
b445e3b0
ED		 1868 &ironlake_display_srwm_info,
1869 &ironlake_cursor_srwm_info,
1870 &fbc_wm, &plane_wm, &cursor_wm))
1871 return;
1872
1873 I915_WRITE(WM1_LP_ILK,
1874 WM1_LP_SR_EN |
b0aea5dc 1875 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 1876 (fbc_wm << WM1_LP_FBC_SHIFT) |
1877 (plane_wm << WM1_LP_SR_SHIFT) |
1878 cursor_wm);
1879
1880 /* WM2 */
1881 if (!ironlake_compute_srwm(dev, 2, enabled,
b0aea5dc 1882 dev_priv->wm.pri_latency[2] * 500,
b445e3b0
ED		 1883 &ironlake_display_srwm_info,
1884 &ironlake_cursor_srwm_info,
1885 &fbc_wm, &plane_wm, &cursor_wm))
1886 return;
1887
1888 I915_WRITE(WM2_LP_ILK,
1889 WM2_LP_EN |
b0aea5dc 1890 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 1891 (fbc_wm << WM1_LP_FBC_SHIFT) |
1892 (plane_wm << WM1_LP_SR_SHIFT) |
1893 cursor_wm);
1894
1895 /*
1896 * WM3 is unsupported on ILK, probably because we don't have latency
1897 * data for that power state
1898 */
1899}
1900
46ba614c 1901static void sandybridge_update_wm(struct drm_crtc *crtc)
b445e3b0 1902{
46ba614c 1903 struct drm_device *dev = crtc->dev;
b445e3b0 1904 struct drm_i915_private *dev_priv = dev->dev_private;
b0aea5dc 1905 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
b445e3b0
ED		 1906 u32 val;
1907 int fbc_wm, plane_wm, cursor_wm;
1908 unsigned int enabled;
1909
1910 enabled = 0;
51cea1f4 1911 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1912 &sandybridge_display_wm_info, latency,
1913 &sandybridge_cursor_wm_info, latency,
1914 &plane_wm, &cursor_wm)) {
1915 val = I915_READ(WM0_PIPEA_ILK);
1916 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1917 I915_WRITE(WM0_PIPEA_ILK, val |
1918 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1919 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1920 " plane %d, " "cursor: %d\n",
1921 plane_wm, cursor_wm);
51cea1f4 1922 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1923 }
1924
51cea1f4 1925 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1926 &sandybridge_display_wm_info, latency,
1927 &sandybridge_cursor_wm_info, latency,
1928 &plane_wm, &cursor_wm)) {
1929 val = I915_READ(WM0_PIPEB_ILK);
1930 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1931 I915_WRITE(WM0_PIPEB_ILK, val |
1932 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1933 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1934 " plane %d, cursor: %d\n",
1935 plane_wm, cursor_wm);
51cea1f4 1936 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1937 }
1938
c43d0188
CW		 1939 /*
1940 * Calculate and update the self-refresh watermark only when one
1941 * display plane is used.
1942 *
1943 * SNB support 3 levels of watermark.
1944 *
1945 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1946 * and disabled in the descending order
1947 *
1948 */
1949 I915_WRITE(WM3_LP_ILK, 0);
1950 I915_WRITE(WM2_LP_ILK, 0);
1951 I915_WRITE(WM1_LP_ILK, 0);
1952
1953 if (!single_plane_enabled(enabled) ||
1954 dev_priv->sprite_scaling_enabled)
1955 return;
1956 enabled = ffs(enabled) - 1;
1957
1958 /* WM1 */
1959 if (!ironlake_compute_srwm(dev, 1, enabled,
b0aea5dc 1960 dev_priv->wm.pri_latency[1] * 500,
c43d0188
CW		 1961 &sandybridge_display_srwm_info,
1962 &sandybridge_cursor_srwm_info,
1963 &fbc_wm, &plane_wm, &cursor_wm))
1964 return;
1965
1966 I915_WRITE(WM1_LP_ILK,
1967 WM1_LP_SR_EN |
b0aea5dc 1968 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
c43d0188
CW		 1969 (fbc_wm << WM1_LP_FBC_SHIFT) |
1970 (plane_wm << WM1_LP_SR_SHIFT) |
1971 cursor_wm);
1972
1973 /* WM2 */
1974 if (!ironlake_compute_srwm(dev, 2, enabled,
b0aea5dc 1975 dev_priv->wm.pri_latency[2] * 500,
c43d0188
CW		 1976 &sandybridge_display_srwm_info,
1977 &sandybridge_cursor_srwm_info,
1978 &fbc_wm, &plane_wm, &cursor_wm))
1979 return;
1980
1981 I915_WRITE(WM2_LP_ILK,
1982 WM2_LP_EN |
b0aea5dc 1983 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
c43d0188
CW		 1984 (fbc_wm << WM1_LP_FBC_SHIFT) |
1985 (plane_wm << WM1_LP_SR_SHIFT) |
1986 cursor_wm);
1987
1988 /* WM3 */
1989 if (!ironlake_compute_srwm(dev, 3, enabled,
b0aea5dc 1990 dev_priv->wm.pri_latency[3] * 500,
c43d0188
CW		 1991 &sandybridge_display_srwm_info,
1992 &sandybridge_cursor_srwm_info,
1993 &fbc_wm, &plane_wm, &cursor_wm))
1994 return;
1995
1996 I915_WRITE(WM3_LP_ILK,
1997 WM3_LP_EN |
b0aea5dc 1998 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
c43d0188
CW		 1999 (fbc_wm << WM1_LP_FBC_SHIFT) |
2000 (plane_wm << WM1_LP_SR_SHIFT) |
2001 cursor_wm);
2002}
2003
46ba614c 2004static void ivybridge_update_wm(struct drm_crtc *crtc)
c43d0188 2005{
46ba614c 2006 struct drm_device *dev = crtc->dev;
c43d0188 2007 struct drm_i915_private *dev_priv = dev->dev_private;
b0aea5dc 2008 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
c43d0188
CW		 2009 u32 val;
2010 int fbc_wm, plane_wm, cursor_wm;
2011 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
2012 unsigned int enabled;
2013
2014 enabled = 0;
51cea1f4 2015 if (g4x_compute_wm0(dev, PIPE_A,
c43d0188
CW		 2016 &sandybridge_display_wm_info, latency,
2017 &sandybridge_cursor_wm_info, latency,
2018 &plane_wm, &cursor_wm)) {
2019 val = I915_READ(WM0_PIPEA_ILK);
2020 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2021 I915_WRITE(WM0_PIPEA_ILK, val |
2022 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2023 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
2024 " plane %d, " "cursor: %d\n",
2025 plane_wm, cursor_wm);
51cea1f4 2026 enabled |= 1 << PIPE_A;
c43d0188
CW		 2027 }
2028
51cea1f4 2029 if (g4x_compute_wm0(dev, PIPE_B,
c43d0188
CW		 2030 &sandybridge_display_wm_info, latency,
2031 &sandybridge_cursor_wm_info, latency,
2032 &plane_wm, &cursor_wm)) {
2033 val = I915_READ(WM0_PIPEB_ILK);
2034 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2035 I915_WRITE(WM0_PIPEB_ILK, val |
2036 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2037 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
2038 " plane %d, cursor: %d\n",
2039 plane_wm, cursor_wm);
51cea1f4 2040 enabled |= 1 << PIPE_B;
c43d0188
CW		 2041 }
2042
51cea1f4 2043 if (g4x_compute_wm0(dev, PIPE_C,
b445e3b0
ED		 2044 &sandybridge_display_wm_info, latency,
2045 &sandybridge_cursor_wm_info, latency,
2046 &plane_wm, &cursor_wm)) {
2047 val = I915_READ(WM0_PIPEC_IVB);
2048 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2049 I915_WRITE(WM0_PIPEC_IVB, val |
2050 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2051 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2052 " plane %d, cursor: %d\n",
2053 plane_wm, cursor_wm);
51cea1f4 2054 enabled |= 1 << PIPE_C;
b445e3b0
ED		 2055 }
2056
2057 /*
2058 * Calculate and update the self-refresh watermark only when one
2059 * display plane is used.
2060 *
2061 * SNB support 3 levels of watermark.
2062 *
2063 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2064 * and disabled in the descending order
2065 *
2066 */
2067 I915_WRITE(WM3_LP_ILK, 0);
2068 I915_WRITE(WM2_LP_ILK, 0);
2069 I915_WRITE(WM1_LP_ILK, 0);
2070
2071 if (!single_plane_enabled(enabled) ||
2072 dev_priv->sprite_scaling_enabled)
2073 return;
2074 enabled = ffs(enabled) - 1;
2075
2076 /* WM1 */
2077 if (!ironlake_compute_srwm(dev, 1, enabled,
b0aea5dc 2078 dev_priv->wm.pri_latency[1] * 500,
b445e3b0
ED		 2079 &sandybridge_display_srwm_info,
2080 &sandybridge_cursor_srwm_info,
2081 &fbc_wm, &plane_wm, &cursor_wm))
2082 return;
2083
2084 I915_WRITE(WM1_LP_ILK,
2085 WM1_LP_SR_EN |
b0aea5dc 2086 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 2087 (fbc_wm << WM1_LP_FBC_SHIFT) |
2088 (plane_wm << WM1_LP_SR_SHIFT) |
2089 cursor_wm);
2090
2091 /* WM2 */
2092 if (!ironlake_compute_srwm(dev, 2, enabled,
b0aea5dc 2093 dev_priv->wm.pri_latency[2] * 500,
b445e3b0
ED		 2094 &sandybridge_display_srwm_info,
2095 &sandybridge_cursor_srwm_info,
2096 &fbc_wm, &plane_wm, &cursor_wm))
2097 return;
2098
2099 I915_WRITE(WM2_LP_ILK,
2100 WM2_LP_EN |
b0aea5dc 2101 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 2102 (fbc_wm << WM1_LP_FBC_SHIFT) |
2103 (plane_wm << WM1_LP_SR_SHIFT) |
2104 cursor_wm);
2105
c43d0188 2106 /* WM3, note we have to correct the cursor latency */
b445e3b0 2107 if (!ironlake_compute_srwm(dev, 3, enabled,
b0aea5dc 2108 dev_priv->wm.pri_latency[3] * 500,
b445e3b0
ED		 2109 &sandybridge_display_srwm_info,
2110 &sandybridge_cursor_srwm_info,
c43d0188
CW		 2111 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2112 !ironlake_compute_srwm(dev, 3, enabled,
b0aea5dc 2113 dev_priv->wm.cur_latency[3] * 500,
c43d0188
CW		 2114 &sandybridge_display_srwm_info,
2115 &sandybridge_cursor_srwm_info,
2116 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
b445e3b0
ED		 2117 return;
2118
2119 I915_WRITE(WM3_LP_ILK,
2120 WM3_LP_EN |
b0aea5dc 2121 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 2122 (fbc_wm << WM1_LP_FBC_SHIFT) |
2123 (plane_wm << WM1_LP_SR_SHIFT) |
2124 cursor_wm);
2125}
2126
3658729a
VS		 2127static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
2128 struct drm_crtc *crtc)
801bcfff
PZ		 2129{
2130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fd4daa9c 2131 uint32_t pixel_rate;
801bcfff 2132
241bfc38 2133 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
801bcfff
PZ		 2134
2135 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2136 * adjust the pixel_rate here. */
2137
fd4daa9c 2138 if (intel_crtc->config.pch_pfit.enabled) {
801bcfff 2139 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
fd4daa9c 2140 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
801bcfff 2141
37327abd
VS		 2142 pipe_w = intel_crtc->config.pipe_src_w;
2143 pipe_h = intel_crtc->config.pipe_src_h;
801bcfff
PZ		 2144 pfit_w = (pfit_size >> 16) & 0xFFFF;
2145 pfit_h = pfit_size & 0xFFFF;
2146 if (pipe_w < pfit_w)
2147 pipe_w = pfit_w;
2148 if (pipe_h < pfit_h)
2149 pipe_h = pfit_h;
2150
2151 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2152 pfit_w * pfit_h);
2153 }
2154
2155 return pixel_rate;
2156}
2157
37126462 2158/* latency must be in 0.1us units. */
23297044 2159static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 2160 uint32_t latency)
2161{
2162 uint64_t ret;
2163
3312ba65
VS		 2164 if (WARN(latency == 0, "Latency value missing\n"))
2165 return UINT_MAX;
2166
801bcfff
PZ		 2167 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2168 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2169
2170 return ret;
2171}
2172
37126462 2173/* latency must be in 0.1us units. */
23297044 2174static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 2175 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2176 uint32_t latency)
2177{
2178 uint32_t ret;
2179
3312ba65
VS		 2180 if (WARN(latency == 0, "Latency value missing\n"))
2181 return UINT_MAX;
2182
801bcfff
PZ		 2183 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2184 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2185 ret = DIV_ROUND_UP(ret, 64) + 2;
2186 return ret;
2187}
2188
23297044 2189static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 2190 uint8_t bytes_per_pixel)
2191{
2192 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
2193}
2194
801bcfff
PZ		 2195struct hsw_pipe_wm_parameters {
2196 bool active;
801bcfff
PZ		 2197 uint32_t pipe_htotal;
2198 uint32_t pixel_rate;
c35426d2
VS		 2199 struct intel_plane_wm_parameters pri;
2200 struct intel_plane_wm_parameters spr;
2201 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 2202};
2203
cca32e9a
PZ		 2204struct hsw_wm_maximums {
2205 uint16_t pri;
2206 uint16_t spr;
2207 uint16_t cur;
2208 uint16_t fbc;
2209};
2210
240264f4
VS		 2211/* used in computing the new watermarks state */
2212struct intel_wm_config {
2213 unsigned int num_pipes_active;
2214 bool sprites_enabled;
2215 bool sprites_scaled;
240264f4
VS		 2216};
2217
37126462
VS		 2218/*
2219 * For both WM_PIPE and WM_LP.
2220 * mem_value must be in 0.1us units.
2221 */
ac830fe1 2222static uint32_t ilk_compute_pri_wm(const struct hsw_pipe_wm_parameters *params,
cca32e9a
PZ		 2223 uint32_t mem_value,
2224 bool is_lp)
801bcfff 2225{
cca32e9a
PZ		 2226 uint32_t method1, method2;
2227
c35426d2 2228 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 2229 return 0;
2230
23297044 2231 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 2232 params->pri.bytes_per_pixel,
cca32e9a
PZ		 2233 mem_value);
2234
2235 if (!is_lp)
2236 return method1;
2237
23297044 2238 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 2239 params->pipe_htotal,
c35426d2
VS		 2240 params->pri.horiz_pixels,
2241 params->pri.bytes_per_pixel,
cca32e9a
PZ		 2242 mem_value);
2243
2244 return min(method1, method2);
801bcfff
PZ		 2245}
2246
37126462
VS		 2247/*
2248 * For both WM_PIPE and WM_LP.
2249 * mem_value must be in 0.1us units.
2250 */
ac830fe1 2251static uint32_t ilk_compute_spr_wm(const struct hsw_pipe_wm_parameters *params,
801bcfff
PZ		 2252 uint32_t mem_value)
2253{
2254 uint32_t method1, method2;
2255
c35426d2 2256 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 2257 return 0;
2258
23297044 2259 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 2260 params->spr.bytes_per_pixel,
801bcfff 2261 mem_value);
23297044 2262 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 2263 params->pipe_htotal,
c35426d2
VS		 2264 params->spr.horiz_pixels,
2265 params->spr.bytes_per_pixel,
801bcfff
PZ		 2266 mem_value);
2267 return min(method1, method2);
2268}
2269
37126462
VS		 2270/*
2271 * For both WM_PIPE and WM_LP.
2272 * mem_value must be in 0.1us units.
2273 */
ac830fe1 2274static uint32_t ilk_compute_cur_wm(const struct hsw_pipe_wm_parameters *params,
801bcfff
PZ		 2275 uint32_t mem_value)
2276{
c35426d2 2277 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 2278 return 0;
2279
23297044 2280 return ilk_wm_method2(params->pixel_rate,
801bcfff 2281 params->pipe_htotal,
c35426d2
VS		 2282 params->cur.horiz_pixels,
2283 params->cur.bytes_per_pixel,
801bcfff
PZ		 2284 mem_value);
2285}
2286
cca32e9a 2287/* Only for WM_LP. */
ac830fe1 2288static uint32_t ilk_compute_fbc_wm(const struct hsw_pipe_wm_parameters *params,
1fda9882 2289 uint32_t pri_val)
cca32e9a 2290{
c35426d2 2291 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 2292 return 0;
2293
23297044 2294 return ilk_wm_fbc(pri_val,
c35426d2
VS		 2295 params->pri.horiz_pixels,
2296 params->pri.bytes_per_pixel);
cca32e9a
PZ		 2297}
2298
158ae64f
VS		 2299static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
2300{
416f4727
VS		 2301 if (INTEL_INFO(dev)->gen >= 8)
2302 return 3072;
2303 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 2304 return 768;
2305 else
2306 return 512;
2307}
2308
2309/* Calculate the maximum primary/sprite plane watermark */
2310static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2311 int level,
240264f4 2312 const struct intel_wm_config *config,
158ae64f
VS		 2313 enum intel_ddb_partitioning ddb_partitioning,
2314 bool is_sprite)
2315{
2316 unsigned int fifo_size = ilk_display_fifo_size(dev);
2317 unsigned int max;
2318
2319 /* if sprites aren't enabled, sprites get nothing */
240264f4 2320 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 2321 return 0;
2322
2323 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 2324 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 2325 fifo_size /= INTEL_INFO(dev)->num_pipes;
2326
2327 /*
2328 * For some reason the non self refresh
2329 * FIFO size is only half of the self
2330 * refresh FIFO size on ILK/SNB.
2331 */
2332 if (INTEL_INFO(dev)->gen <= 6)
2333 fifo_size /= 2;
2334 }
2335
240264f4 2336 if (config->sprites_enabled) {
158ae64f
VS		 2337 /* level 0 is always calculated with 1:1 split */
2338 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2339 if (is_sprite)
2340 fifo_size *= 5;
2341 fifo_size /= 6;
2342 } else {
2343 fifo_size /= 2;
2344 }
2345 }
2346
2347 /* clamp to max that the registers can hold */
416f4727
VS		 2348 if (INTEL_INFO(dev)->gen >= 8)
2349 max = level == 0 ? 255 : 2047;
2350 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 2351 /* IVB/HSW primary/sprite plane watermarks */
2352 max = level == 0 ? 127 : 1023;
2353 else if (!is_sprite)
2354 /* ILK/SNB primary plane watermarks */
2355 max = level == 0 ? 127 : 511;
2356 else
2357 /* ILK/SNB sprite plane watermarks */
2358 max = level == 0 ? 63 : 255;
2359
2360 return min(fifo_size, max);
2361}
2362
2363/* Calculate the maximum cursor plane watermark */
2364static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 2365 int level,
2366 const struct intel_wm_config *config)
158ae64f
VS		 2367{
2368 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 2369 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 2370 return 64;
2371
2372 /* otherwise just report max that registers can hold */
2373 if (INTEL_INFO(dev)->gen >= 7)
2374 return level == 0 ? 63 : 255;
2375 else
2376 return level == 0 ? 31 : 63;
2377}
2378
2379/* Calculate the maximum FBC watermark */
416f4727 2380static unsigned int ilk_fbc_wm_max(struct drm_device *dev)
158ae64f
VS		 2381{
2382 /* max that registers can hold */
416f4727
VS		 2383 if (INTEL_INFO(dev)->gen >= 8)
2384 return 31;
2385 else
2386 return 15;
158ae64f
VS		 2387}
2388
34982fe1
VS		 2389static void ilk_compute_wm_maximums(struct drm_device *dev,
2390 int level,
2391 const struct intel_wm_config *config,
2392 enum intel_ddb_partitioning ddb_partitioning,
2393 struct hsw_wm_maximums *max)
158ae64f 2394{
240264f4
VS		 2395 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2396 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2397 max->cur = ilk_cursor_wm_max(dev, level, config);
416f4727 2398 max->fbc = ilk_fbc_wm_max(dev);
158ae64f
VS		 2399}
2400
d9395655
VS		 2401static bool ilk_validate_wm_level(int level,
2402 const struct hsw_wm_maximums *max,
2403 struct intel_wm_level *result)
a9786a11
VS		 2404{
2405 bool ret;
2406
2407 /* already determined to be invalid? */
2408 if (!result->enable)
2409 return false;
2410
2411 result->enable = result->pri_val <= max->pri &&
2412 result->spr_val <= max->spr &&
2413 result->cur_val <= max->cur;
2414
2415 ret = result->enable;
2416
2417 /*
2418 * HACK until we can pre-compute everything,
2419 * and thus fail gracefully if LP0 watermarks
2420 * are exceeded...
2421 */
2422 if (level == 0 && !result->enable) {
2423 if (result->pri_val > max->pri)
2424 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2425 level, result->pri_val, max->pri);
2426 if (result->spr_val > max->spr)
2427 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2428 level, result->spr_val, max->spr);
2429 if (result->cur_val > max->cur)
2430 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2431 level, result->cur_val, max->cur);
2432
2433 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2434 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2435 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2436 result->enable = true;
2437 }
2438
a9786a11
VS		 2439 return ret;
2440}
2441
6f5ddd17
VS		 2442static void ilk_compute_wm_level(struct drm_i915_private *dev_priv,
2443 int level,
ac830fe1 2444 const struct hsw_pipe_wm_parameters *p,
1fd527cc 2445 struct intel_wm_level *result)
6f5ddd17
VS		 2446{
2447 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2448 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2449 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2450
2451 /* WM1+ latency values stored in 0.5us units */
2452 if (level > 0) {
2453 pri_latency *= 5;
2454 spr_latency *= 5;
2455 cur_latency *= 5;
2456 }
2457
2458 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2459 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2460 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2461 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2462 result->enable = true;
2463}
2464
801bcfff
PZ		 2465static uint32_t
2466hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2467{
2468 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 2470 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 2471 u32 linetime, ips_linetime;
1f8eeabf 2472
801bcfff
PZ		 2473 if (!intel_crtc_active(crtc))
2474 return 0;
1011d8c4 2475
1f8eeabf
ED		 2476 /* The WM are computed with base on how long it takes to fill a single
2477 * row at the given clock rate, multiplied by 8.
2478 * */
85a02deb
PZ		 2479 linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2480 ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2481 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 2482
801bcfff
PZ		 2483 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2484 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2485}
2486
12b134df
VS		 2487static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2488{
2489 struct drm_i915_private *dev_priv = dev->dev_private;
2490
2491 if (IS_HASWELL(dev)) {
2492 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2493
2494 wm[0] = (sskpd >> 56) & 0xFF;
2495 if (wm[0] == 0)
2496 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2497 wm[1] = (sskpd >> 4) & 0xFF;
2498 wm[2] = (sskpd >> 12) & 0xFF;
2499 wm[3] = (sskpd >> 20) & 0x1FF;
2500 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2501 } else if (INTEL_INFO(dev)->gen >= 6) {
2502 uint32_t sskpd = I915_READ(MCH_SSKPD);
2503
2504 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2505 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2506 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2507 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2508 } else if (INTEL_INFO(dev)->gen >= 5) {
2509 uint32_t mltr = I915_READ(MLTR_ILK);
2510
2511 /* ILK primary LP0 latency is 700 ns */
2512 wm[0] = 7;
2513 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2514 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2515 }
2516}
2517
53615a5e
VS		 2518static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2519{
2520 /* ILK sprite LP0 latency is 1300 ns */
2521 if (INTEL_INFO(dev)->gen == 5)
2522 wm[0] = 13;
2523}
2524
2525static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2526{
2527 /* ILK cursor LP0 latency is 1300 ns */
2528 if (INTEL_INFO(dev)->gen == 5)
2529 wm[0] = 13;
2530
2531 /* WaDoubleCursorLP3Latency:ivb */
2532 if (IS_IVYBRIDGE(dev))
2533 wm[3] *= 2;
2534}
2535
ad0d6dc4 2536static int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2537{
26ec971e
VS		 2538 /* how many WM levels are we expecting */
2539 if (IS_HASWELL(dev))
ad0d6dc4 2540 return 4;
26ec971e 2541 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2542 return 3;
26ec971e 2543 else
ad0d6dc4
VS		 2544 return 2;
2545}
2546
2547static void intel_print_wm_latency(struct drm_device *dev,
2548 const char *name,
2549 const uint16_t wm[5])
2550{
2551 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2552
2553 for (level = 0; level <= max_level; level++) {
2554 unsigned int latency = wm[level];
2555
2556 if (latency == 0) {
2557 DRM_ERROR("%s WM%d latency not provided\n",
2558 name, level);
2559 continue;
2560 }
2561
2562 /* WM1+ latency values in 0.5us units */
2563 if (level > 0)
2564 latency *= 5;
2565
2566 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2567 name, level, wm[level],
2568 latency / 10, latency % 10);
2569 }
2570}
2571
53615a5e
VS		 2572static void intel_setup_wm_latency(struct drm_device *dev)
2573{
2574 struct drm_i915_private *dev_priv = dev->dev_private;
2575
2576 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2577
2578 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2579 sizeof(dev_priv->wm.pri_latency));
2580 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2581 sizeof(dev_priv->wm.pri_latency));
2582
2583 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2584 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2585
2586 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2587 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2588 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
53615a5e
VS		 2589}
2590
7c4a395f
VS		 2591static void hsw_compute_wm_parameters(struct drm_crtc *crtc,
2592 struct hsw_pipe_wm_parameters *p,
a485bfb8 2593 struct intel_wm_config *config)
1011d8c4 2594{
7c4a395f
VS		 2595 struct drm_device *dev = crtc->dev;
2596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2597 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2598 struct drm_plane *plane;
1011d8c4 2599
7c4a395f
VS		 2600 p->active = intel_crtc_active(crtc);
2601 if (p->active) {
801bcfff 2602 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
3658729a 2603 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
c35426d2
VS		 2604 p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2605 p->cur.bytes_per_pixel = 4;
37327abd 2606 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
c35426d2
VS		 2607 p->cur.horiz_pixels = 64;
2608 /* TODO: for now, assume primary and cursor planes are always enabled. */
2609 p->pri.enabled = true;
2610 p->cur.enabled = true;
801bcfff
PZ		 2611 }
2612
7c4a395f 2613 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
a485bfb8 2614 config->num_pipes_active += intel_crtc_active(crtc);
7c4a395f 2615
801bcfff
PZ		 2616 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2617 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2618
7c4a395f
VS		 2619 if (intel_plane->pipe == pipe)
2620 p->spr = intel_plane->wm;
cca32e9a 2621
a485bfb8
VS		 2622 config->sprites_enabled |= intel_plane->wm.enabled;
2623 config->sprites_scaled |= intel_plane->wm.scaled;
cca32e9a 2624 }
801bcfff
PZ		 2625}
2626
0b2ae6d7
VS		 2627/* Compute new watermarks for the pipe */
2628static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2629 const struct hsw_pipe_wm_parameters *params,
2630 struct intel_pipe_wm *pipe_wm)
2631{
2632 struct drm_device *dev = crtc->dev;
2633 struct drm_i915_private *dev_priv = dev->dev_private;
2634 int level, max_level = ilk_wm_max_level(dev);
2635 /* LP0 watermark maximums depend on this pipe alone */
2636 struct intel_wm_config config = {
2637 .num_pipes_active = 1,
2638 .sprites_enabled = params->spr.enabled,
2639 .sprites_scaled = params->spr.scaled,
2640 };
2641 struct hsw_wm_maximums max;
2642
0b2ae6d7 2643 /* LP0 watermarks always use 1/2 DDB partitioning */
34982fe1 2644 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
0b2ae6d7
VS		 2645
2646 for (level = 0; level <= max_level; level++)
2647 ilk_compute_wm_level(dev_priv, level, params,
2648 &pipe_wm->wm[level]);
2649
2650 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2651
2652 /* At least LP0 must be valid */
d9395655 2653 return ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]);
0b2ae6d7
VS		 2654}
2655
2656/*
2657 * Merge the watermarks from all active pipes for a specific level.
2658 */
2659static void ilk_merge_wm_level(struct drm_device *dev,
2660 int level,
2661 struct intel_wm_level *ret_wm)
2662{
2663 const struct intel_crtc *intel_crtc;
2664
2665 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2666 const struct intel_wm_level *wm =
2667 &intel_crtc->wm.active.wm[level];
2668
2669 if (!wm->enable)
2670 return;
2671
2672 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2673 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2674 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2675 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2676 }
2677
2678 ret_wm->enable = true;
2679}
2680
2681/*
2682 * Merge all low power watermarks for all active pipes.
2683 */
2684static void ilk_wm_merge(struct drm_device *dev,
2685 const struct hsw_wm_maximums *max,
2686 struct intel_pipe_wm *merged)
2687{
2688 int level, max_level = ilk_wm_max_level(dev);
2689
2690 merged->fbc_wm_enabled = true;
2691
2692 /* merge each WM1+ level */
2693 for (level = 1; level <= max_level; level++) {
2694 struct intel_wm_level *wm = &merged->wm[level];
2695
2696 ilk_merge_wm_level(dev, level, wm);
2697
d9395655 2698 if (!ilk_validate_wm_level(level, max, wm))
0b2ae6d7
VS		 2699 break;
2700
2701 /*
2702 * The spec says it is preferred to disable
2703 * FBC WMs instead of disabling a WM level.
2704 */
2705 if (wm->fbc_val > max->fbc) {
2706 merged->fbc_wm_enabled = false;
2707 wm->fbc_val = 0;
2708 }
2709 }
2710}
2711
b380ca3c
VS		 2712static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2713{
2714 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2715 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2716}
2717
801bcfff 2718static void hsw_compute_wm_results(struct drm_device *dev,
0362c781 2719 const struct intel_pipe_wm *merged,
609cedef 2720 enum intel_ddb_partitioning partitioning,
801bcfff
PZ		 2721 struct hsw_wm_values *results)
2722{
0b2ae6d7
VS		 2723 struct intel_crtc *intel_crtc;
2724 int level, wm_lp;
cca32e9a 2725
0362c781 2726 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2727 results->partitioning = partitioning;
cca32e9a 2728
0b2ae6d7 2729 /* LP1+ register values */
cca32e9a 2730 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2731 const struct intel_wm_level *r;
801bcfff 2732
b380ca3c 2733 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2734
0362c781 2735 r = &merged->wm[level];
0b2ae6d7 2736 if (!r->enable)
cca32e9a
PZ		 2737 break;
2738
416f4727
VS		 2739 results->wm_lp[wm_lp - 1] = WM3_LP_EN |
2740 ((level * 2) << WM1_LP_LATENCY_SHIFT) |
2741 (r->pri_val << WM1_LP_SR_SHIFT) |
2742 r->cur_val;
2743
2744 if (INTEL_INFO(dev)->gen >= 8)
2745 results->wm_lp[wm_lp - 1] |=
2746 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2747 else
2748 results->wm_lp[wm_lp - 1] |=
2749 r->fbc_val << WM1_LP_FBC_SHIFT;
2750
cca32e9a
PZ		 2751 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2752 }
801bcfff 2753
0b2ae6d7
VS		 2754 /* LP0 register values */
2755 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2756 enum pipe pipe = intel_crtc->pipe;
2757 const struct intel_wm_level *r =
2758 &intel_crtc->wm.active.wm[0];
2759
2760 if (WARN_ON(!r->enable))
2761 continue;
2762
2763 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2764
0b2ae6d7
VS		 2765 results->wm_pipe[pipe] =
2766 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2767 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2768 r->cur_val;
801bcfff
PZ		 2769 }
2770}
2771
861f3389
PZ		 2772/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2773 * case both are at the same level. Prefer r1 in case they're the same. */
198a1e9b
VS		 2774static struct intel_pipe_wm *hsw_find_best_result(struct drm_device *dev,
2775 struct intel_pipe_wm *r1,
2776 struct intel_pipe_wm *r2)
861f3389 2777{
198a1e9b
VS		 2778 int level, max_level = ilk_wm_max_level(dev);
2779 int level1 = 0, level2 = 0;
861f3389 2780
198a1e9b
VS		 2781 for (level = 1; level <= max_level; level++) {
2782 if (r1->wm[level].enable)
2783 level1 = level;
2784 if (r2->wm[level].enable)
2785 level2 = level;
861f3389
PZ		 2786 }
2787
198a1e9b
VS		 2788 if (level1 == level2) {
2789 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2790 return r2;
2791 else
2792 return r1;
198a1e9b 2793 } else if (level1 > level2) {
861f3389
PZ		 2794 return r1;
2795 } else {
2796 return r2;
2797 }
2798}
2799
49a687c4
VS		 2800/* dirty bits used to track which watermarks need changes */
2801#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2802#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2803#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2804#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2805#define WM_DIRTY_FBC (1 << 24)
2806#define WM_DIRTY_DDB (1 << 25)
2807
2808static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2809 const struct hsw_wm_values *old,
2810 const struct hsw_wm_values *new)
2811{
2812 unsigned int dirty = 0;
2813 enum pipe pipe;
2814 int wm_lp;
2815
2816 for_each_pipe(pipe) {
2817 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2818 dirty |= WM_DIRTY_LINETIME(pipe);
2819 /* Must disable LP1+ watermarks too */
2820 dirty |= WM_DIRTY_LP_ALL;
2821 }
2822
2823 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2824 dirty |= WM_DIRTY_PIPE(pipe);
2825 /* Must disable LP1+ watermarks too */
2826 dirty |= WM_DIRTY_LP_ALL;
2827 }
2828 }
2829
2830 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2831 dirty |= WM_DIRTY_FBC;
2832 /* Must disable LP1+ watermarks too */
2833 dirty |= WM_DIRTY_LP_ALL;
2834 }
2835
2836 if (old->partitioning != new->partitioning) {
2837 dirty |= WM_DIRTY_DDB;
2838 /* Must disable LP1+ watermarks too */
2839 dirty |= WM_DIRTY_LP_ALL;
2840 }
2841
2842 /* LP1+ watermarks already deemed dirty, no need to continue */
2843 if (dirty & WM_DIRTY_LP_ALL)
2844 return dirty;
2845
2846 /* Find the lowest numbered LP1+ watermark in need of an update... */
2847 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2848 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2849 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2850 break;
2851 }
2852
2853 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2854 for (; wm_lp <= 3; wm_lp++)
2855 dirty |= WM_DIRTY_LP(wm_lp);
2856
2857 return dirty;
2858}
2859
801bcfff
PZ		 2860/*
2861 * The spec says we shouldn't write when we don't need, because every write
2862 * causes WMs to be re-evaluated, expending some power.
2863 */
2864static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
609cedef 2865 struct hsw_wm_values *results)
801bcfff 2866{
243e6a44 2867 struct hsw_wm_values *previous = &dev_priv->wm.hw;
49a687c4 2868 unsigned int dirty;
801bcfff 2869 uint32_t val;
801bcfff 2870
243e6a44 2871 dirty = ilk_compute_wm_dirty(dev_priv->dev, previous, results);
49a687c4 2872 if (!dirty)
801bcfff
PZ		 2873 return;
2874
243e6a44 2875 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != 0)
801bcfff 2876 I915_WRITE(WM3_LP_ILK, 0);
243e6a44 2877 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != 0)
801bcfff 2878 I915_WRITE(WM2_LP_ILK, 0);
243e6a44 2879 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != 0)
801bcfff
PZ		 2880 I915_WRITE(WM1_LP_ILK, 0);
2881
49a687c4 2882 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2883 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2884 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2885 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2886 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2887 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2888
49a687c4 2889 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2890 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2891 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2892 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2893 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2894 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2895
49a687c4 2896 if (dirty & WM_DIRTY_DDB) {
801bcfff 2897 val = I915_READ(WM_MISC);
609cedef 2898 if (results->partitioning == INTEL_DDB_PART_1_2)
801bcfff
PZ		 2899 val &= ~WM_MISC_DATA_PARTITION_5_6;
2900 else
2901 val |= WM_MISC_DATA_PARTITION_5_6;
2902 I915_WRITE(WM_MISC, val);
1011d8c4
PZ		 2903 }
2904
49a687c4 2905 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2906 val = I915_READ(DISP_ARB_CTL);
2907 if (results->enable_fbc_wm)
2908 val &= ~DISP_FBC_WM_DIS;
2909 else
2910 val |= DISP_FBC_WM_DIS;
2911 I915_WRITE(DISP_ARB_CTL, val);
2912 }
2913
243e6a44 2914 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp_spr[0] != results->wm_lp_spr[0])
801bcfff 2915 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
243e6a44 2916 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
801bcfff 2917 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
243e6a44 2918 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
801bcfff
PZ		 2919 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2920
49a687c4 2921 if (dirty & WM_DIRTY_LP(1) && results->wm_lp[0] != 0)
801bcfff 2922 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
49a687c4 2923 if (dirty & WM_DIRTY_LP(2) && results->wm_lp[1] != 0)
801bcfff 2924 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
49a687c4 2925 if (dirty & WM_DIRTY_LP(3) && results->wm_lp[2] != 0)
801bcfff 2926 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2927
2928 dev_priv->wm.hw = *results;
801bcfff
PZ		 2929}
2930
46ba614c 2931static void haswell_update_wm(struct drm_crtc *crtc)
801bcfff 2932{
7c4a395f 2933 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 2934 struct drm_device *dev = crtc->dev;
801bcfff 2935 struct drm_i915_private *dev_priv = dev->dev_private;
a485bfb8 2936 struct hsw_wm_maximums max;
7c4a395f 2937 struct hsw_pipe_wm_parameters params = {};
198a1e9b 2938 struct hsw_wm_values results = {};
77c122bc 2939 enum intel_ddb_partitioning partitioning;
7c4a395f 2940 struct intel_pipe_wm pipe_wm = {};
198a1e9b 2941 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 2942 struct intel_wm_config config = {};
7c4a395f 2943
a485bfb8 2944 hsw_compute_wm_parameters(crtc, &params, &config);
7c4a395f
VS		 2945
2946 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2947
2948 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2949 return;
861f3389 2950
7c4a395f 2951 intel_crtc->wm.active = pipe_wm;
861f3389 2952
34982fe1 2953 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
a485bfb8
VS		 2954 ilk_wm_merge(dev, &max, &lp_wm_1_2);
2955
2956 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 2957 if (INTEL_INFO(dev)->gen >= 7 &&
2958 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 2959 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
a485bfb8 2960 ilk_wm_merge(dev, &max, &lp_wm_5_6);
0362c781 2961
198a1e9b 2962 best_lp_wm = hsw_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 2963 } else {
198a1e9b 2964 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 2965 }
2966
198a1e9b 2967 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 2968 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 2969
609cedef
VS		 2970 hsw_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2971
2972 hsw_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 2973}
2974
adf3d35e
VS		 2975static void haswell_update_sprite_wm(struct drm_plane *plane,
2976 struct drm_crtc *crtc,
526682e9 2977 uint32_t sprite_width, int pixel_size,
bdd57d03 2978 bool enabled, bool scaled)
526682e9 2979{
adf3d35e 2980 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 2981
adf3d35e
VS		 2982 intel_plane->wm.enabled = enabled;
2983 intel_plane->wm.scaled = scaled;
2984 intel_plane->wm.horiz_pixels = sprite_width;
2985 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 2986
46ba614c 2987 haswell_update_wm(crtc);
526682e9
PZ		 2988}
2989
b445e3b0
ED		 2990static bool
2991sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2992 uint32_t sprite_width, int pixel_size,
2993 const struct intel_watermark_params *display,
2994 int display_latency_ns, int *sprite_wm)
2995{
2996 struct drm_crtc *crtc;
2997 int clock;
2998 int entries, tlb_miss;
2999
3000 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 3001 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 3002 *sprite_wm = display->guard_size;
3003 return false;
3004 }
3005
241bfc38 3006 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
b445e3b0
ED		 3007
3008 /* Use the small buffer method to calculate the sprite watermark */
3009 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3010 tlb_miss = display->fifo_size*display->cacheline_size -
3011 sprite_width * 8;
3012 if (tlb_miss > 0)
3013 entries += tlb_miss;
3014 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3015 *sprite_wm = entries + display->guard_size;
3016 if (*sprite_wm > (int)display->max_wm)
3017 *sprite_wm = display->max_wm;
3018
3019 return true;
3020}
3021
3022static bool
3023sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
3024 uint32_t sprite_width, int pixel_size,
3025 const struct intel_watermark_params *display,
3026 int latency_ns, int *sprite_wm)
3027{
3028 struct drm_crtc *crtc;
3029 unsigned long line_time_us;
3030 int clock;
3031 int line_count, line_size;
3032 int small, large;
3033 int entries;
3034
3035 if (!latency_ns) {
3036 *sprite_wm = 0;
3037 return false;
3038 }
3039
3040 crtc = intel_get_crtc_for_plane(dev, plane);
241bfc38 3041 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
b445e3b0
ED		 3042 if (!clock) {
3043 *sprite_wm = 0;
3044 return false;
3045 }
3046
3047 line_time_us = (sprite_width * 1000) / clock;
3048 if (!line_time_us) {
3049 *sprite_wm = 0;
3050 return false;
3051 }
3052
3053 line_count = (latency_ns / line_time_us + 1000) / 1000;
3054 line_size = sprite_width * pixel_size;
3055
3056 /* Use the minimum of the small and large buffer method for primary */
3057 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3058 large = line_count * line_size;
3059
3060 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3061 *sprite_wm = entries + display->guard_size;
3062
3063 return *sprite_wm > 0x3ff ? false : true;
3064}
3065
adf3d35e
VS		 3066static void sandybridge_update_sprite_wm(struct drm_plane *plane,
3067 struct drm_crtc *crtc,
4c4ff43a 3068 uint32_t sprite_width, int pixel_size,
39db4a4d 3069 bool enabled, bool scaled)
b445e3b0 3070{
adf3d35e 3071 struct drm_device *dev = plane->dev;
b445e3b0 3072 struct drm_i915_private *dev_priv = dev->dev_private;
adf3d35e 3073 int pipe = to_intel_plane(plane)->pipe;
b0aea5dc 3074 int latency = dev_priv->wm.spr_latency[0] * 100; /* In unit 0.1us */
b445e3b0
ED		 3075 u32 val;
3076 int sprite_wm, reg;
3077 int ret;
3078
39db4a4d 3079 if (!enabled)
4c4ff43a
PZ		 3080 return;
3081
b445e3b0
ED		 3082 switch (pipe) {
3083 case 0:
3084 reg = WM0_PIPEA_ILK;
3085 break;
3086 case 1:
3087 reg = WM0_PIPEB_ILK;
3088 break;
3089 case 2:
3090 reg = WM0_PIPEC_IVB;
3091 break;
3092 default:
3093 return; /* bad pipe */
3094 }
3095
3096 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
3097 &sandybridge_display_wm_info,
3098 latency, &sprite_wm);
3099 if (!ret) {
84f44ce7
VS		 3100 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
3101 pipe_name(pipe));
b445e3b0
ED		 3102 return;
3103 }
3104
3105 val = I915_READ(reg);
3106 val &= ~WM0_PIPE_SPRITE_MASK;
3107 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
84f44ce7 3108 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
b445e3b0
ED		 3109
3110
3111 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3112 pixel_size,
3113 &sandybridge_display_srwm_info,
b0aea5dc 3114 dev_priv->wm.spr_latency[1] * 500,
b445e3b0
ED		 3115 &sprite_wm);
3116 if (!ret) {
84f44ce7
VS		 3117 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
3118 pipe_name(pipe));
b445e3b0
ED		 3119 return;
3120 }
3121 I915_WRITE(WM1S_LP_ILK, sprite_wm);
3122
3123 /* Only IVB has two more LP watermarks for sprite */
3124 if (!IS_IVYBRIDGE(dev))
3125 return;
3126
3127 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3128 pixel_size,
3129 &sandybridge_display_srwm_info,
b0aea5dc 3130 dev_priv->wm.spr_latency[2] * 500,
b445e3b0
ED		 3131 &sprite_wm);
3132 if (!ret) {
84f44ce7
VS		 3133 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
3134 pipe_name(pipe));
b445e3b0
ED		 3135 return;
3136 }
3137 I915_WRITE(WM2S_LP_IVB, sprite_wm);
3138
3139 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3140 pixel_size,
3141 &sandybridge_display_srwm_info,
b0aea5dc 3142 dev_priv->wm.spr_latency[3] * 500,
b445e3b0
ED		 3143 &sprite_wm);
3144 if (!ret) {
84f44ce7
VS		 3145 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
3146 pipe_name(pipe));
b445e3b0
ED		 3147 return;
3148 }
3149 I915_WRITE(WM3S_LP_IVB, sprite_wm);
3150}
3151
243e6a44
VS		 3152static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3153{
3154 struct drm_device *dev = crtc->dev;
3155 struct drm_i915_private *dev_priv = dev->dev_private;
3156 struct hsw_wm_values *hw = &dev_priv->wm.hw;
3157 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3158 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3159 enum pipe pipe = intel_crtc->pipe;
3160 static const unsigned int wm0_pipe_reg[] = {
3161 [PIPE_A] = WM0_PIPEA_ILK,
3162 [PIPE_B] = WM0_PIPEB_ILK,
3163 [PIPE_C] = WM0_PIPEC_IVB,
3164 };
3165
3166 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3167 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3168
3169 if (intel_crtc_active(crtc)) {
3170 u32 tmp = hw->wm_pipe[pipe];
3171
3172 /*
3173 * For active pipes LP0 watermark is marked as
3174 * enabled, and LP1+ watermaks as disabled since
3175 * we can't really reverse compute them in case
3176 * multiple pipes are active.
3177 */
3178 active->wm[0].enable = true;
3179 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3180 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3181 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3182 active->linetime = hw->wm_linetime[pipe];
3183 } else {
3184 int level, max_level = ilk_wm_max_level(dev);
3185
3186 /*
3187 * For inactive pipes, all watermark levels
3188 * should be marked as enabled but zeroed,
3189 * which is what we'd compute them to.
3190 */
3191 for (level = 0; level <= max_level; level++)
3192 active->wm[level].enable = true;
3193 }
3194}
3195
3196void ilk_wm_get_hw_state(struct drm_device *dev)
3197{
3198 struct drm_i915_private *dev_priv = dev->dev_private;
3199 struct hsw_wm_values *hw = &dev_priv->wm.hw;
3200 struct drm_crtc *crtc;
3201
3202 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3203 ilk_pipe_wm_get_hw_state(crtc);
3204
3205 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3206 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3207 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3208
3209 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
3210 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3211 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3212
3213 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3214 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3215
3216 hw->enable_fbc_wm =
3217 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3218}
3219
b445e3b0
ED		 3220/**
3221 * intel_update_watermarks - update FIFO watermark values based on current modes
3222 *
3223 * Calculate watermark values for the various WM regs based on current mode
3224 * and plane configuration.
3225 *
3226 * There are several cases to deal with here:
3227 * - normal (i.e. non-self-refresh)
3228 * - self-refresh (SR) mode
3229 * - lines are large relative to FIFO size (buffer can hold up to 2)
3230 * - lines are small relative to FIFO size (buffer can hold more than 2
3231 * lines), so need to account for TLB latency
3232 *
3233 * The normal calculation is:
3234 * watermark = dotclock * bytes per pixel * latency
3235 * where latency is platform & configuration dependent (we assume pessimal
3236 * values here).
3237 *
3238 * The SR calculation is:
3239 * watermark = (trunc(latency/line time)+1) * surface width *
3240 * bytes per pixel
3241 * where
3242 * line time = htotal / dotclock
3243 * surface width = hdisplay for normal plane and 64 for cursor
3244 * and latency is assumed to be high, as above.
3245 *
3246 * The final value programmed to the register should always be rounded up,
3247 * and include an extra 2 entries to account for clock crossings.
3248 *
3249 * We don't use the sprite, so we can ignore that. And on Crestline we have
3250 * to set the non-SR watermarks to 8.
3251 */
46ba614c 3252void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 3253{
46ba614c 3254 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 3255
3256 if (dev_priv->display.update_wm)
46ba614c 3257 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 3258}
3259
adf3d35e
VS		 3260void intel_update_sprite_watermarks(struct drm_plane *plane,
3261 struct drm_crtc *crtc,
4c4ff43a 3262 uint32_t sprite_width, int pixel_size,
39db4a4d 3263 bool enabled, bool scaled)
b445e3b0 3264{
adf3d35e 3265 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 3266
3267 if (dev_priv->display.update_sprite_wm)
adf3d35e 3268 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
39db4a4d 3269 pixel_size, enabled, scaled);
b445e3b0
ED		 3270}
3271
2b4e57bd
ED		 3272static struct drm_i915_gem_object *
3273intel_alloc_context_page(struct drm_device *dev)
3274{
3275 struct drm_i915_gem_object *ctx;
3276 int ret;
3277
3278 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3279
3280 ctx = i915_gem_alloc_object(dev, 4096);
3281 if (!ctx) {
3282 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3283 return NULL;
3284 }
3285
c37e2204 3286 ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
2b4e57bd
ED		 3287 if (ret) {
3288 DRM_ERROR("failed to pin power context: %d\n", ret);
3289 goto err_unref;
3290 }
3291
3292 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3293 if (ret) {
3294 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3295 goto err_unpin;
3296 }
3297
3298 return ctx;
3299
3300err_unpin:
3301 i915_gem_object_unpin(ctx);
3302err_unref:
3303 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 3304 return NULL;
3305}
3306
9270388e
DV		 3307/**
3308 * Lock protecting IPS related data structures
9270388e
DV		 3309 */
3310DEFINE_SPINLOCK(mchdev_lock);
3311
3312/* Global for IPS driver to get at the current i915 device. Protected by
3313 * mchdev_lock. */
3314static struct drm_i915_private *i915_mch_dev;
3315
2b4e57bd
ED		 3316bool ironlake_set_drps(struct drm_device *dev, u8 val)
3317{
3318 struct drm_i915_private *dev_priv = dev->dev_private;
3319 u16 rgvswctl;
3320
9270388e
DV		 3321 assert_spin_locked(&mchdev_lock);
3322
2b4e57bd
ED		 3323 rgvswctl = I915_READ16(MEMSWCTL);
3324 if (rgvswctl & MEMCTL_CMD_STS) {
3325 DRM_DEBUG("gpu busy, RCS change rejected\n");
3326 return false; /* still busy with another command */
3327 }
3328
3329 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3330 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3331 I915_WRITE16(MEMSWCTL, rgvswctl);
3332 POSTING_READ16(MEMSWCTL);
3333
3334 rgvswctl |= MEMCTL_CMD_STS;
3335 I915_WRITE16(MEMSWCTL, rgvswctl);
3336
3337 return true;
3338}
3339
8090c6b9 3340static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 3341{
3342 struct drm_i915_private *dev_priv = dev->dev_private;
3343 u32 rgvmodectl = I915_READ(MEMMODECTL);
3344 u8 fmax, fmin, fstart, vstart;
3345
9270388e
DV		 3346 spin_lock_irq(&mchdev_lock);
3347
2b4e57bd
ED		 3348 /* Enable temp reporting */
3349 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3350 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3351
3352 /* 100ms RC evaluation intervals */
3353 I915_WRITE(RCUPEI, 100000);
3354 I915_WRITE(RCDNEI, 100000);
3355
3356 /* Set max/min thresholds to 90ms and 80ms respectively */
3357 I915_WRITE(RCBMAXAVG, 90000);
3358 I915_WRITE(RCBMINAVG, 80000);
3359
3360 I915_WRITE(MEMIHYST, 1);
3361
3362 /* Set up min, max, and cur for interrupt handling */
3363 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3364 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3365 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3366 MEMMODE_FSTART_SHIFT;
3367
3368 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3369 PXVFREQ_PX_SHIFT;
3370
20e4d407
DV		 3371 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3372 dev_priv->ips.fstart = fstart;
2b4e57bd 3373
20e4d407
DV		 3374 dev_priv->ips.max_delay = fstart;
3375 dev_priv->ips.min_delay = fmin;
3376 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 3377
3378 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3379 fmax, fmin, fstart);
3380
3381 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3382
3383 /*
3384 * Interrupts will be enabled in ironlake_irq_postinstall
3385 */
3386
3387 I915_WRITE(VIDSTART, vstart);
3388 POSTING_READ(VIDSTART);
3389
3390 rgvmodectl |= MEMMODE_SWMODE_EN;
3391 I915_WRITE(MEMMODECTL, rgvmodectl);
3392
9270388e 3393 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 3394 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 3395 mdelay(1);
2b4e57bd
ED		 3396
3397 ironlake_set_drps(dev, fstart);
3398
20e4d407 3399 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 3400 I915_READ(0x112e0);
20e4d407
DV		 3401 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3402 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3403 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 3404
3405 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3406}
3407
8090c6b9 3408static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 3409{
3410 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 3411 u16 rgvswctl;
3412
3413 spin_lock_irq(&mchdev_lock);
3414
3415 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 3416
3417 /* Ack interrupts, disable EFC interrupt */
3418 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3419 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3420 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3421 I915_WRITE(DEIIR, DE_PCU_EVENT);
3422 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3423
3424 /* Go back to the starting frequency */
20e4d407 3425 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 3426 mdelay(1);
2b4e57bd
ED		 3427 rgvswctl |= MEMCTL_CMD_STS;
3428 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 3429 mdelay(1);
2b4e57bd 3430
9270388e 3431 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3432}
3433
acbe9475
DV		 3434/* There's a funny hw issue where the hw returns all 0 when reading from
3435 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3436 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3437 * all limits and the gpu stuck at whatever frequency it is at atm).
3438 */
6917c7b9 3439static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 3440{
7b9e0ae6 3441 u32 limits;
2b4e57bd 3442
20b46e59
DV		 3443 /* Only set the down limit when we've reached the lowest level to avoid
3444 * getting more interrupts, otherwise leave this clear. This prevents a
3445 * race in the hw when coming out of rc6: There's a tiny window where
3446 * the hw runs at the minimal clock before selecting the desired
3447 * frequency, if the down threshold expires in that window we will not
3448 * receive a down interrupt. */
6917c7b9
CW		 3449 limits = dev_priv->rps.max_delay << 24;
3450 if (val <= dev_priv->rps.min_delay)
c6a828d3 3451 limits |= dev_priv->rps.min_delay << 16;
20b46e59
DV		 3452
3453 return limits;
3454}
3455
dd75fdc8
CW		 3456static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3457{
3458 int new_power;
3459
3460 new_power = dev_priv->rps.power;
3461 switch (dev_priv->rps.power) {
3462 case LOW_POWER:
3463 if (val > dev_priv->rps.rpe_delay + 1 && val > dev_priv->rps.cur_delay)
3464 new_power = BETWEEN;
3465 break;
3466
3467 case BETWEEN:
3468 if (val <= dev_priv->rps.rpe_delay && val < dev_priv->rps.cur_delay)
3469 new_power = LOW_POWER;
3470 else if (val >= dev_priv->rps.rp0_delay && val > dev_priv->rps.cur_delay)
3471 new_power = HIGH_POWER;
3472 break;
3473
3474 case HIGH_POWER:
3475 if (val < (dev_priv->rps.rp1_delay + dev_priv->rps.rp0_delay) >> 1 && val < dev_priv->rps.cur_delay)
3476 new_power = BETWEEN;
3477 break;
3478 }
3479 /* Max/min bins are special */
3480 if (val == dev_priv->rps.min_delay)
3481 new_power = LOW_POWER;
3482 if (val == dev_priv->rps.max_delay)
3483 new_power = HIGH_POWER;
3484 if (new_power == dev_priv->rps.power)
3485 return;
3486
3487 /* Note the units here are not exactly 1us, but 1280ns. */
3488 switch (new_power) {
3489 case LOW_POWER:
3490 /* Upclock if more than 95% busy over 16ms */
3491 I915_WRITE(GEN6_RP_UP_EI, 12500);
3492 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3493
3494 /* Downclock if less than 85% busy over 32ms */
3495 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3496 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3497
3498 I915_WRITE(GEN6_RP_CONTROL,
3499 GEN6_RP_MEDIA_TURBO |
3500 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3501 GEN6_RP_MEDIA_IS_GFX |
3502 GEN6_RP_ENABLE |
3503 GEN6_RP_UP_BUSY_AVG |
3504 GEN6_RP_DOWN_IDLE_AVG);
3505 break;
3506
3507 case BETWEEN:
3508 /* Upclock if more than 90% busy over 13ms */
3509 I915_WRITE(GEN6_RP_UP_EI, 10250);
3510 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3511
3512 /* Downclock if less than 75% busy over 32ms */
3513 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3514 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3515
3516 I915_WRITE(GEN6_RP_CONTROL,
3517 GEN6_RP_MEDIA_TURBO |
3518 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3519 GEN6_RP_MEDIA_IS_GFX |
3520 GEN6_RP_ENABLE |
3521 GEN6_RP_UP_BUSY_AVG |
3522 GEN6_RP_DOWN_IDLE_AVG);
3523 break;
3524
3525 case HIGH_POWER:
3526 /* Upclock if more than 85% busy over 10ms */
3527 I915_WRITE(GEN6_RP_UP_EI, 8000);
3528 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3529
3530 /* Downclock if less than 60% busy over 32ms */
3531 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3532 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3533
3534 I915_WRITE(GEN6_RP_CONTROL,
3535 GEN6_RP_MEDIA_TURBO |
3536 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3537 GEN6_RP_MEDIA_IS_GFX |
3538 GEN6_RP_ENABLE |
3539 GEN6_RP_UP_BUSY_AVG |
3540 GEN6_RP_DOWN_IDLE_AVG);
3541 break;
3542 }
3543
3544 dev_priv->rps.power = new_power;
3545 dev_priv->rps.last_adj = 0;
3546}
3547
20b46e59
DV		 3548void gen6_set_rps(struct drm_device *dev, u8 val)
3549{
3550 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 3551
4fc688ce 3552 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79249636
BW		 3553 WARN_ON(val > dev_priv->rps.max_delay);
3554 WARN_ON(val < dev_priv->rps.min_delay);
004777cb 3555
c6a828d3 3556 if (val == dev_priv->rps.cur_delay)
7b9e0ae6
CW		 3557 return;
3558
dd75fdc8
CW		 3559 gen6_set_rps_thresholds(dev_priv, val);
3560
92bd1bf0
RV		 3561 if (IS_HASWELL(dev))
3562 I915_WRITE(GEN6_RPNSWREQ,
3563 HSW_FREQUENCY(val));
3564 else
3565 I915_WRITE(GEN6_RPNSWREQ,
3566 GEN6_FREQUENCY(val) |
3567 GEN6_OFFSET(0) |
3568 GEN6_AGGRESSIVE_TURBO);
7b9e0ae6
CW		 3569
3570 /* Make sure we continue to get interrupts
3571 * until we hit the minimum or maximum frequencies.
3572 */
6917c7b9
CW		 3573 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3574 gen6_rps_limits(dev_priv, val));
7b9e0ae6 3575
d5570a72
BW		 3576 POSTING_READ(GEN6_RPNSWREQ);
3577
c6a828d3 3578 dev_priv->rps.cur_delay = val;
be2cde9a
DV		 3579
3580 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3581}
3582
b29c19b6
CW		 3583void gen6_rps_idle(struct drm_i915_private *dev_priv)
3584{
3585 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c
CW		 3586 if (dev_priv->rps.enabled) {
3587 if (dev_priv->info->is_valleyview)
3588 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3589 else
3590 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3591 dev_priv->rps.last_adj = 0;
3592 }
b29c19b6
CW		 3593 mutex_unlock(&dev_priv->rps.hw_lock);
3594}
3595
3596void gen6_rps_boost(struct drm_i915_private *dev_priv)
3597{
3598 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c
CW		 3599 if (dev_priv->rps.enabled) {
3600 if (dev_priv->info->is_valleyview)
3601 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3602 else
3603 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3604 dev_priv->rps.last_adj = 0;
3605 }
b29c19b6
CW		 3606 mutex_unlock(&dev_priv->rps.hw_lock);
3607}
3608
0a073b84
JB		 3609void valleyview_set_rps(struct drm_device *dev, u8 val)
3610{
3611 struct drm_i915_private *dev_priv = dev->dev_private;
7a67092a 3612
0a073b84
JB		 3613 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3614 WARN_ON(val > dev_priv->rps.max_delay);
3615 WARN_ON(val < dev_priv->rps.min_delay);
3616
73008b98 3617 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
2ec3815f 3618 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
73008b98 3619 dev_priv->rps.cur_delay,
2ec3815f 3620 vlv_gpu_freq(dev_priv, val), val);
0a073b84
JB		 3621
3622 if (val == dev_priv->rps.cur_delay)
3623 return;
3624
ae99258f 3625 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
0a073b84 3626
80814ae4 3627 dev_priv->rps.cur_delay = val;
0a073b84 3628
2ec3815f 3629 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
0a073b84
JB		 3630}
3631
44fc7d5c 3632static void gen6_disable_rps_interrupts(struct drm_device *dev)
2b4e57bd
ED		 3633{
3634 struct drm_i915_private *dev_priv = dev->dev_private;
3635
2b4e57bd 3636 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4848405c 3637 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3638 /* Complete PM interrupt masking here doesn't race with the rps work
3639 * item again unmasking PM interrupts because that is using a different
3640 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3641 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3642
59cdb63d 3643 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3 3644 dev_priv->rps.pm_iir = 0;
59cdb63d 3645 spin_unlock_irq(&dev_priv->irq_lock);
2b4e57bd 3646
4848405c 3647 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3648}
3649
44fc7d5c 3650static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 3651{
3652 struct drm_i915_private *dev_priv = dev->dev_private;
3653
3654 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 3655 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
d20d4f0c 3656
44fc7d5c
DV		 3657 gen6_disable_rps_interrupts(dev);
3658}
3659
3660static void valleyview_disable_rps(struct drm_device *dev)
3661{
3662 struct drm_i915_private *dev_priv = dev->dev_private;
3663
3664 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 3665
44fc7d5c 3666 gen6_disable_rps_interrupts(dev);
c9cddffc
JB		 3667
3668 if (dev_priv->vlv_pctx) {
3669 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3670 dev_priv->vlv_pctx = NULL;
3671 }
d20d4f0c
JB		 3672}
3673
dc39fff7
BW		 3674static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3675{
3676 if (IS_GEN6(dev))
3677 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3678
3679 if (IS_HASWELL(dev))
3680 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3681
3682 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3683 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3684 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3685 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3686}
3687
2b4e57bd
ED		 3688int intel_enable_rc6(const struct drm_device *dev)
3689{
eb4926e4
DL		 3690 /* No RC6 before Ironlake */
3691 if (INTEL_INFO(dev)->gen < 5)
3692 return 0;
3693
456470eb 3694 /* Respect the kernel parameter if it is set */
2b4e57bd
ED		 3695 if (i915_enable_rc6 >= 0)
3696 return i915_enable_rc6;
3697
6567d748
CW		 3698 /* Disable RC6 on Ironlake */
3699 if (INTEL_INFO(dev)->gen == 5)
3700 return 0;
2b4e57bd 3701
dc39fff7 3702 if (IS_HASWELL(dev))
4a637c2c 3703 return INTEL_RC6_ENABLE;
2b4e57bd 3704
456470eb 3705 /* snb/ivb have more than one rc6 state. */
dc39fff7 3706 if (INTEL_INFO(dev)->gen == 6)
2b4e57bd 3707 return INTEL_RC6_ENABLE;
456470eb 3708
2b4e57bd
ED		 3709 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3710}
3711
44fc7d5c
DV		 3712static void gen6_enable_rps_interrupts(struct drm_device *dev)
3713{
3714 struct drm_i915_private *dev_priv = dev->dev_private;
a9c1f90c 3715 u32 enabled_intrs;
44fc7d5c
DV		 3716
3717 spin_lock_irq(&dev_priv->irq_lock);
a0b3335a 3718 WARN_ON(dev_priv->rps.pm_iir);
edbfdb45 3719 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
44fc7d5c
DV		 3720 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3721 spin_unlock_irq(&dev_priv->irq_lock);
a9c1f90c 3722
fd547d25 3723 /* only unmask PM interrupts we need. Mask all others. */
a9c1f90c
MK		 3724 enabled_intrs = GEN6_PM_RPS_EVENTS;
3725
3726 /* IVB and SNB hard hangs on looping batchbuffer
3727 * if GEN6_PM_UP_EI_EXPIRED is masked.
3728 */
3729 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3730 enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
3731
3732 I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
44fc7d5c
DV		 3733}
3734
6edee7f3
BW		 3735static void gen8_enable_rps(struct drm_device *dev)
3736{
3737 struct drm_i915_private *dev_priv = dev->dev_private;
3738 struct intel_ring_buffer *ring;
3739 uint32_t rc6_mask = 0, rp_state_cap;
3740 int unused;
3741
3742 /* 1a: Software RC state - RC0 */
3743 I915_WRITE(GEN6_RC_STATE, 0);
3744
3745 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3746 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
c8d9a590 3747 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3748
3749 /* 2a: Disable RC states. */
3750 I915_WRITE(GEN6_RC_CONTROL, 0);
3751
3752 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3753
3754 /* 2b: Program RC6 thresholds.*/
3755 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3756 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3757 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3758 for_each_ring(ring, dev_priv, unused)
3759 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3760 I915_WRITE(GEN6_RC_SLEEP, 0);
3761 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3762
3763 /* 3: Enable RC6 */
3764 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3765 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3766 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
3767 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3768 GEN6_RC_CTL_EI_MODE(1) |
3769 rc6_mask);
3770
3771 /* 4 Program defaults and thresholds for RPS*/
3772 I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */
3773 I915_WRITE(GEN6_RC_VIDEO_FREQ, HSW_FREQUENCY(12)); /* Request 600 MHz */
3774 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3775 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3776
3777 /* Docs recommend 900MHz, and 300 MHz respectively */
3778 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3779 dev_priv->rps.max_delay << 24 |
3780 dev_priv->rps.min_delay << 16);
3781
3782 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3783 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3784 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3785 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3786
3787 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3788
3789 /* 5: Enable RPS */
3790 I915_WRITE(GEN6_RP_CONTROL,
3791 GEN6_RP_MEDIA_TURBO |
3792 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3793 GEN6_RP_MEDIA_IS_GFX |
3794 GEN6_RP_ENABLE |
3795 GEN6_RP_UP_BUSY_AVG |
3796 GEN6_RP_DOWN_IDLE_AVG);
3797
3798 /* 6: Ring frequency + overclocking (our driver does this later */
3799
3800 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3801
3802 gen6_enable_rps_interrupts(dev);
3803
c8d9a590 3804 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3805}
3806
79f5b2c7 3807static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 3808{
79f5b2c7 3809 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 3810 struct intel_ring_buffer *ring;
7b9e0ae6
CW		 3811 u32 rp_state_cap;
3812 u32 gt_perf_status;
31643d54 3813 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2b4e57bd 3814 u32 gtfifodbg;
2b4e57bd 3815 int rc6_mode;
42c0526c 3816 int i, ret;
2b4e57bd 3817
4fc688ce 3818 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3819
2b4e57bd
ED		 3820 /* Here begins a magic sequence of register writes to enable
3821 * auto-downclocking.
3822 *
3823 * Perhaps there might be some value in exposing these to
3824 * userspace...
3825 */
3826 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 3827
3828 /* Clear the DBG now so we don't confuse earlier errors */
3829 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3830 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3831 I915_WRITE(GTFIFODBG, gtfifodbg);
3832 }
3833
c8d9a590 3834 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 3835
7b9e0ae6
CW		 3836 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3837 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3838
31c77388
BW		 3839 /* In units of 50MHz */
3840 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
dd75fdc8
CW		 3841 dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff;
3842 dev_priv->rps.rp1_delay = (rp_state_cap >> 8) & 0xff;
3843 dev_priv->rps.rp0_delay = (rp_state_cap >> 0) & 0xff;
3844 dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
c6a828d3 3845 dev_priv->rps.cur_delay = 0;
7b9e0ae6 3846
2b4e57bd
ED		 3847 /* disable the counters and set deterministic thresholds */
3848 I915_WRITE(GEN6_RC_CONTROL, 0);
3849
3850 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3851 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3852 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3853 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3854 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3855
b4519513
CW		 3856 for_each_ring(ring, dev_priv, i)
3857 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 3858
3859 I915_WRITE(GEN6_RC_SLEEP, 0);
3860 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
351aa566
SM		 3861 if (INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev))
3862 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3863 else
3864 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 3865 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 3866 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3867
5a7dc92a 3868 /* Check if we are enabling RC6 */
2b4e57bd
ED		 3869 rc6_mode = intel_enable_rc6(dev_priv->dev);
3870 if (rc6_mode & INTEL_RC6_ENABLE)
3871 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3872
5a7dc92a
ED		 3873 /* We don't use those on Haswell */
3874 if (!IS_HASWELL(dev)) {
3875 if (rc6_mode & INTEL_RC6p_ENABLE)
3876 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 3877
5a7dc92a
ED		 3878 if (rc6_mode & INTEL_RC6pp_ENABLE)
3879 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3880 }
2b4e57bd 3881
dc39fff7 3882 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 3883
3884 I915_WRITE(GEN6_RC_CONTROL,
3885 rc6_mask |
3886 GEN6_RC_CTL_EI_MODE(1) |
3887 GEN6_RC_CTL_HW_ENABLE);
3888
dd75fdc8
CW		 3889 /* Power down if completely idle for over 50ms */
3890 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 3891 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 3892
42c0526c 3893 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
988b36e5 3894 if (!ret) {
42c0526c
BW		 3895 pcu_mbox = 0;
3896 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
a2b3fc01 3897 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
10e08497 3898 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
a2b3fc01
BW		 3899 (dev_priv->rps.max_delay & 0xff) * 50,
3900 (pcu_mbox & 0xff) * 50);
31c77388 3901 dev_priv->rps.hw_max = pcu_mbox & 0xff;
42c0526c
BW		 3902 }
3903 } else {
3904 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2b4e57bd
ED		 3905 }
3906
dd75fdc8
CW		 3907 dev_priv->rps.power = HIGH_POWER; /* force a reset */
3908 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
2b4e57bd 3909
44fc7d5c 3910 gen6_enable_rps_interrupts(dev);
2b4e57bd 3911
31643d54
BW		 3912 rc6vids = 0;
3913 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3914 if (IS_GEN6(dev) && ret) {
3915 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3916 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3917 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3918 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3919 rc6vids &= 0xffff00;
3920 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3921 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3922 if (ret)
3923 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3924 }
3925
c8d9a590 3926 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 3927}
3928
c67a470b 3929void gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 3930{
79f5b2c7 3931 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 3932 int min_freq = 15;
3ebecd07
CW		 3933 unsigned int gpu_freq;
3934 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd 3935 int scaling_factor = 180;
eda79642 3936 struct cpufreq_policy *policy;
2b4e57bd 3937
4fc688ce 3938 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3939
eda79642
BW		 3940 policy = cpufreq_cpu_get(0);
3941 if (policy) {
3942 max_ia_freq = policy->cpuinfo.max_freq;
3943 cpufreq_cpu_put(policy);
3944 } else {
3945 /*
3946 * Default to measured freq if none found, PCU will ensure we
3947 * don't go over
3948 */
2b4e57bd 3949 max_ia_freq = tsc_khz;
eda79642 3950 }
2b4e57bd
ED		 3951
3952 /* Convert from kHz to MHz */
3953 max_ia_freq /= 1000;
3954
153b4b95 3955 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 3956 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3957 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 3958
2b4e57bd
ED		 3959 /*
3960 * For each potential GPU frequency, load a ring frequency we'd like
3961 * to use for memory access. We do this by specifying the IA frequency
3962 * the PCU should use as a reference to determine the ring frequency.
3963 */
c6a828d3 3964 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2b4e57bd 3965 gpu_freq--) {
c6a828d3 3966 int diff = dev_priv->rps.max_delay - gpu_freq;
3ebecd07
CW		 3967 unsigned int ia_freq = 0, ring_freq = 0;
3968
46c764d4
BW		 3969 if (INTEL_INFO(dev)->gen >= 8) {
3970 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3971 ring_freq = max(min_ring_freq, gpu_freq);
3972 } else if (IS_HASWELL(dev)) {
f6aca45c 3973 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 3974 ring_freq = max(min_ring_freq, ring_freq);
3975 /* leave ia_freq as the default, chosen by cpufreq */
3976 } else {
3977 /* On older processors, there is no separate ring
3978 * clock domain, so in order to boost the bandwidth
3979 * of the ring, we need to upclock the CPU (ia_freq).
3980 *
3981 * For GPU frequencies less than 750MHz,
3982 * just use the lowest ring freq.
3983 */
3984 if (gpu_freq < min_freq)
3985 ia_freq = 800;
3986 else
3987 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3988 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3989 }
2b4e57bd 3990
42c0526c
BW		 3991 sandybridge_pcode_write(dev_priv,
3992 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 3993 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3994 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3995 gpu_freq);
2b4e57bd 3996 }
2b4e57bd
ED		 3997}
3998
0a073b84
JB		 3999int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
4000{
4001 u32 val, rp0;
4002
64936258 4003 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 4004
4005 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
4006 /* Clamp to max */
4007 rp0 = min_t(u32, rp0, 0xea);
4008
4009 return rp0;
4010}
4011
4012static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4013{
4014 u32 val, rpe;
4015
64936258 4016 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 4017 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 4018 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 4019 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4020
4021 return rpe;
4022}
4023
4024int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
4025{
64936258 4026 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 4027}
4028
c9cddffc
JB		 4029static void valleyview_setup_pctx(struct drm_device *dev)
4030{
4031 struct drm_i915_private *dev_priv = dev->dev_private;
4032 struct drm_i915_gem_object *pctx;
4033 unsigned long pctx_paddr;
4034 u32 pcbr;
4035 int pctx_size = 24*1024;
4036
4037 pcbr = I915_READ(VLV_PCBR);
4038 if (pcbr) {
4039 /* BIOS set it up already, grab the pre-alloc'd space */
4040 int pcbr_offset;
4041
4042 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4043 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4044 pcbr_offset,
190d6cd5 4045 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 4046 pctx_size);
4047 goto out;
4048 }
4049
4050 /*
4051 * From the Gunit register HAS:
4052 * The Gfx driver is expected to program this register and ensure
4053 * proper allocation within Gfx stolen memory. For example, this
4054 * register should be programmed such than the PCBR range does not
4055 * overlap with other ranges, such as the frame buffer, protected
4056 * memory, or any other relevant ranges.
4057 */
4058 pctx = i915_gem_object_create_stolen(dev, pctx_size);
4059 if (!pctx) {
4060 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4061 return;
4062 }
4063
4064 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4065 I915_WRITE(VLV_PCBR, pctx_paddr);
4066
4067out:
4068 dev_priv->vlv_pctx = pctx;
4069}
4070
0a073b84
JB		 4071static void valleyview_enable_rps(struct drm_device *dev)
4072{
4073 struct drm_i915_private *dev_priv = dev->dev_private;
4074 struct intel_ring_buffer *ring;
a2b23fe0 4075 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 4076 int i;
4077
4078 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4079
4080 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 4081 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4082 gtfifodbg);
0a073b84
JB		 4083 I915_WRITE(GTFIFODBG, gtfifodbg);
4084 }
4085
c9cddffc
JB		 4086 valleyview_setup_pctx(dev);
4087
c8d9a590
D		 4088 /* If VLV, Forcewake all wells, else re-direct to regular path */
4089 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 4090
4091 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4092 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4093 I915_WRITE(GEN6_RP_UP_EI, 66000);
4094 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4095
4096 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4097
4098 I915_WRITE(GEN6_RP_CONTROL,
4099 GEN6_RP_MEDIA_TURBO |
4100 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4101 GEN6_RP_MEDIA_IS_GFX |
4102 GEN6_RP_ENABLE |
4103 GEN6_RP_UP_BUSY_AVG |
4104 GEN6_RP_DOWN_IDLE_CONT);
4105
4106 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4107 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4108 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4109
4110 for_each_ring(ring, dev_priv, i)
4111 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4112
2f0aa304 4113 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 4114
4115 /* allows RC6 residency counter to work */
49798eb2
JB		 4116 I915_WRITE(VLV_COUNTER_CONTROL,
4117 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4118 VLV_MEDIA_RC6_COUNT_EN |
4119 VLV_RENDER_RC6_COUNT_EN));
a2b23fe0 4120 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 4121 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 4122
4123 intel_print_rc6_info(dev, rc6_mode);
4124
a2b23fe0 4125 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 4126
64936258 4127 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 4128
4129 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4130 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4131
0a073b84 4132 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
73008b98 4133 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
2ec3815f 4134 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
73008b98 4135 dev_priv->rps.cur_delay);
0a073b84
JB		 4136
4137 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
4138 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
73008b98 4139 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
2ec3815f 4140 vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay),
73008b98 4141 dev_priv->rps.max_delay);
0a073b84 4142
73008b98
VS		 4143 dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
4144 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
2ec3815f 4145 vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
73008b98 4146 dev_priv->rps.rpe_delay);
0a073b84 4147
73008b98
VS		 4148 dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
4149 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
2ec3815f 4150 vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay),
73008b98 4151 dev_priv->rps.min_delay);
0a073b84 4152
73008b98 4153 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
2ec3815f 4154 vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
73008b98 4155 dev_priv->rps.rpe_delay);
0a073b84 4156
73008b98 4157 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
0a073b84 4158
44fc7d5c 4159 gen6_enable_rps_interrupts(dev);
0a073b84 4160
c8d9a590 4161 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 4162}
4163
930ebb46 4164void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 4165{
4166 struct drm_i915_private *dev_priv = dev->dev_private;
4167
3e373948
DV		 4168 if (dev_priv->ips.renderctx) {
4169 i915_gem_object_unpin(dev_priv->ips.renderctx);
4170 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4171 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 4172 }
4173
3e373948
DV		 4174 if (dev_priv->ips.pwrctx) {
4175 i915_gem_object_unpin(dev_priv->ips.pwrctx);
4176 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4177 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 4178 }
4179}
4180
930ebb46 4181static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 4182{
4183 struct drm_i915_private *dev_priv = dev->dev_private;
4184
4185 if (I915_READ(PWRCTXA)) {
4186 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4187 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4188 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4189 50);
4190
4191 I915_WRITE(PWRCTXA, 0);
4192 POSTING_READ(PWRCTXA);
4193
4194 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4195 POSTING_READ(RSTDBYCTL);
4196 }
2b4e57bd
ED		 4197}
4198
4199static int ironlake_setup_rc6(struct drm_device *dev)
4200{
4201 struct drm_i915_private *dev_priv = dev->dev_private;
4202
3e373948
DV		 4203 if (dev_priv->ips.renderctx == NULL)
4204 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4205 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 4206 return -ENOMEM;
4207
3e373948
DV		 4208 if (dev_priv->ips.pwrctx == NULL)
4209 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4210 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 4211 ironlake_teardown_rc6(dev);
4212 return -ENOMEM;
4213 }
4214
4215 return 0;
4216}
4217
930ebb46 4218static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 4219{
4220 struct drm_i915_private *dev_priv = dev->dev_private;
6d90c952 4221 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3e960501 4222 bool was_interruptible;
2b4e57bd
ED		 4223 int ret;
4224
4225 /* rc6 disabled by default due to repeated reports of hanging during
4226 * boot and resume.
4227 */
4228 if (!intel_enable_rc6(dev))
4229 return;
4230
79f5b2c7
DV		 4231 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4232
2b4e57bd 4233 ret = ironlake_setup_rc6(dev);
79f5b2c7 4234 if (ret)
2b4e57bd 4235 return;
2b4e57bd 4236
3e960501
CW		 4237 was_interruptible = dev_priv->mm.interruptible;
4238 dev_priv->mm.interruptible = false;
4239
2b4e57bd
ED		 4240 /*
4241 * GPU can automatically power down the render unit if given a page
4242 * to save state.
4243 */
6d90c952 4244 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 4245 if (ret) {
4246 ironlake_teardown_rc6(dev);
3e960501 4247 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 4248 return;
4249 }
4250
6d90c952
DV		 4251 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4252 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 4253 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
6d90c952
DV		 4254 MI_MM_SPACE_GTT |
4255 MI_SAVE_EXT_STATE_EN |
4256 MI_RESTORE_EXT_STATE_EN |
4257 MI_RESTORE_INHIBIT);
4258 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4259 intel_ring_emit(ring, MI_NOOP);
4260 intel_ring_emit(ring, MI_FLUSH);
4261 intel_ring_advance(ring);
2b4e57bd
ED		 4262
4263 /*
4264 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4265 * does an implicit flush, combined with MI_FLUSH above, it should be
4266 * safe to assume that renderctx is valid
4267 */
3e960501
CW		 4268 ret = intel_ring_idle(ring);
4269 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 4270 if (ret) {
def27a58 4271 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 4272 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 4273 return;
4274 }
4275
f343c5f6 4276 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
2b4e57bd 4277 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
dc39fff7
BW		 4278
4279 intel_print_rc6_info(dev, INTEL_RC6_ENABLE);
2b4e57bd
ED		 4280}
4281
dde18883
ED		 4282static unsigned long intel_pxfreq(u32 vidfreq)
4283{
4284 unsigned long freq;
4285 int div = (vidfreq & 0x3f0000) >> 16;
4286 int post = (vidfreq & 0x3000) >> 12;
4287 int pre = (vidfreq & 0x7);
4288
4289 if (!pre)
4290 return 0;
4291
4292 freq = ((div * 133333) / ((1<<post) * pre));
4293
4294 return freq;
4295}
4296
eb48eb00
DV		 4297static const struct cparams {
4298 u16 i;
4299 u16 t;
4300 u16 m;
4301 u16 c;
4302} cparams[] = {
4303 { 1, 1333, 301, 28664 },
4304 { 1, 1066, 294, 24460 },
4305 { 1, 800, 294, 25192 },
4306 { 0, 1333, 276, 27605 },
4307 { 0, 1066, 276, 27605 },
4308 { 0, 800, 231, 23784 },
4309};
4310
f531dcb2 4311static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4312{
4313 u64 total_count, diff, ret;
4314 u32 count1, count2, count3, m = 0, c = 0;
4315 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4316 int i;
4317
02d71956
DV		 4318 assert_spin_locked(&mchdev_lock);
4319
20e4d407 4320 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 4321
4322 /* Prevent division-by-zero if we are asking too fast.
4323 * Also, we don't get interesting results if we are polling
4324 * faster than once in 10ms, so just return the saved value
4325 * in such cases.
4326 */
4327 if (diff1 <= 10)
20e4d407 4328 return dev_priv->ips.chipset_power;
eb48eb00
DV		 4329
4330 count1 = I915_READ(DMIEC);
4331 count2 = I915_READ(DDREC);
4332 count3 = I915_READ(CSIEC);
4333
4334 total_count = count1 + count2 + count3;
4335
4336 /* FIXME: handle per-counter overflow */
20e4d407
DV		 4337 if (total_count < dev_priv->ips.last_count1) {
4338 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 4339 diff += total_count;
4340 } else {
20e4d407 4341 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 4342 }
4343
4344 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 4345 if (cparams[i].i == dev_priv->ips.c_m &&
4346 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 4347 m = cparams[i].m;
4348 c = cparams[i].c;
4349 break;
4350 }
4351 }
4352
4353 diff = div_u64(diff, diff1);
4354 ret = ((m * diff) + c);
4355 ret = div_u64(ret, 10);
4356
20e4d407
DV		 4357 dev_priv->ips.last_count1 = total_count;
4358 dev_priv->ips.last_time1 = now;
eb48eb00 4359
20e4d407 4360 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 4361
4362 return ret;
4363}
4364
f531dcb2
CW		 4365unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4366{
4367 unsigned long val;
4368
4369 if (dev_priv->info->gen != 5)
4370 return 0;
4371
4372 spin_lock_irq(&mchdev_lock);
4373
4374 val = __i915_chipset_val(dev_priv);
4375
4376 spin_unlock_irq(&mchdev_lock);
4377
4378 return val;
4379}
4380
eb48eb00
DV		 4381unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4382{
4383 unsigned long m, x, b;
4384 u32 tsfs;
4385
4386 tsfs = I915_READ(TSFS);
4387
4388 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4389 x = I915_READ8(TR1);
4390
4391 b = tsfs & TSFS_INTR_MASK;
4392
4393 return ((m * x) / 127) - b;
4394}
4395
4396static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4397{
4398 static const struct v_table {
4399 u16 vd; /* in .1 mil */
4400 u16 vm; /* in .1 mil */
4401 } v_table[] = {
4402 { 0, 0, },
4403 { 375, 0, },
4404 { 500, 0, },
4405 { 625, 0, },
4406 { 750, 0, },
4407 { 875, 0, },
4408 { 1000, 0, },
4409 { 1125, 0, },
4410 { 4125, 3000, },
4411 { 4125, 3000, },
4412 { 4125, 3000, },
4413 { 4125, 3000, },
4414 { 4125, 3000, },
4415 { 4125, 3000, },
4416 { 4125, 3000, },
4417 { 4125, 3000, },
4418 { 4125, 3000, },
4419 { 4125, 3000, },
4420 { 4125, 3000, },
4421 { 4125, 3000, },
4422 { 4125, 3000, },
4423 { 4125, 3000, },
4424 { 4125, 3000, },
4425 { 4125, 3000, },
4426 { 4125, 3000, },
4427 { 4125, 3000, },
4428 { 4125, 3000, },
4429 { 4125, 3000, },
4430 { 4125, 3000, },
4431 { 4125, 3000, },
4432 { 4125, 3000, },
4433 { 4125, 3000, },
4434 { 4250, 3125, },
4435 { 4375, 3250, },
4436 { 4500, 3375, },
4437 { 4625, 3500, },
4438 { 4750, 3625, },
4439 { 4875, 3750, },
4440 { 5000, 3875, },
4441 { 5125, 4000, },
4442 { 5250, 4125, },
4443 { 5375, 4250, },
4444 { 5500, 4375, },
4445 { 5625, 4500, },
4446 { 5750, 4625, },
4447 { 5875, 4750, },
4448 { 6000, 4875, },
4449 { 6125, 5000, },
4450 { 6250, 5125, },
4451 { 6375, 5250, },
4452 { 6500, 5375, },
4453 { 6625, 5500, },
4454 { 6750, 5625, },
4455 { 6875, 5750, },
4456 { 7000, 5875, },
4457 { 7125, 6000, },
4458 { 7250, 6125, },
4459 { 7375, 6250, },
4460 { 7500, 6375, },
4461 { 7625, 6500, },
4462 { 7750, 6625, },
4463 { 7875, 6750, },
4464 { 8000, 6875, },
4465 { 8125, 7000, },
4466 { 8250, 7125, },
4467 { 8375, 7250, },
4468 { 8500, 7375, },
4469 { 8625, 7500, },
4470 { 8750, 7625, },
4471 { 8875, 7750, },
4472 { 9000, 7875, },
4473 { 9125, 8000, },
4474 { 9250, 8125, },
4475 { 9375, 8250, },
4476 { 9500, 8375, },
4477 { 9625, 8500, },
4478 { 9750, 8625, },
4479 { 9875, 8750, },
4480 { 10000, 8875, },
4481 { 10125, 9000, },
4482 { 10250, 9125, },
4483 { 10375, 9250, },
4484 { 10500, 9375, },
4485 { 10625, 9500, },
4486 { 10750, 9625, },
4487 { 10875, 9750, },
4488 { 11000, 9875, },
4489 { 11125, 10000, },
4490 { 11250, 10125, },
4491 { 11375, 10250, },
4492 { 11500, 10375, },
4493 { 11625, 10500, },
4494 { 11750, 10625, },
4495 { 11875, 10750, },
4496 { 12000, 10875, },
4497 { 12125, 11000, },
4498 { 12250, 11125, },
4499 { 12375, 11250, },
4500 { 12500, 11375, },
4501 { 12625, 11500, },
4502 { 12750, 11625, },
4503 { 12875, 11750, },
4504 { 13000, 11875, },
4505 { 13125, 12000, },
4506 { 13250, 12125, },
4507 { 13375, 12250, },
4508 { 13500, 12375, },
4509 { 13625, 12500, },
4510 { 13750, 12625, },
4511 { 13875, 12750, },
4512 { 14000, 12875, },
4513 { 14125, 13000, },
4514 { 14250, 13125, },
4515 { 14375, 13250, },
4516 { 14500, 13375, },
4517 { 14625, 13500, },
4518 { 14750, 13625, },
4519 { 14875, 13750, },
4520 { 15000, 13875, },
4521 { 15125, 14000, },
4522 { 15250, 14125, },
4523 { 15375, 14250, },
4524 { 15500, 14375, },
4525 { 15625, 14500, },
4526 { 15750, 14625, },
4527 { 15875, 14750, },
4528 { 16000, 14875, },
4529 { 16125, 15000, },
4530 };
4531 if (dev_priv->info->is_mobile)
4532 return v_table[pxvid].vm;
4533 else
4534 return v_table[pxvid].vd;
4535}
4536
02d71956 4537static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4538{
4539 struct timespec now, diff1;
4540 u64 diff;
4541 unsigned long diffms;
4542 u32 count;
4543
02d71956 4544 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 4545
4546 getrawmonotonic(&now);
20e4d407 4547 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 4548
4549 /* Don't divide by 0 */
4550 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4551 if (!diffms)
4552 return;
4553
4554 count = I915_READ(GFXEC);
4555
20e4d407
DV		 4556 if (count < dev_priv->ips.last_count2) {
4557 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 4558 diff += count;
4559 } else {
20e4d407 4560 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 4561 }
4562
20e4d407
DV		 4563 dev_priv->ips.last_count2 = count;
4564 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 4565
4566 /* More magic constants... */
4567 diff = diff * 1181;
4568 diff = div_u64(diff, diffms * 10);
20e4d407 4569 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 4570}
4571
02d71956
DV		 4572void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4573{
4574 if (dev_priv->info->gen != 5)
4575 return;
4576
9270388e 4577 spin_lock_irq(&mchdev_lock);
02d71956
DV		 4578
4579 __i915_update_gfx_val(dev_priv);
4580
9270388e 4581 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 4582}
4583
f531dcb2 4584static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4585{
4586 unsigned long t, corr, state1, corr2, state2;
4587 u32 pxvid, ext_v;
4588
02d71956
DV		 4589 assert_spin_locked(&mchdev_lock);
4590
c6a828d3 4591 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
eb48eb00
DV		 4592 pxvid = (pxvid >> 24) & 0x7f;
4593 ext_v = pvid_to_extvid(dev_priv, pxvid);
4594
4595 state1 = ext_v;
4596
4597 t = i915_mch_val(dev_priv);
4598
4599 /* Revel in the empirically derived constants */
4600
4601 /* Correction factor in 1/100000 units */
4602 if (t > 80)
4603 corr = ((t * 2349) + 135940);
4604 else if (t >= 50)
4605 corr = ((t * 964) + 29317);
4606 else /* < 50 */
4607 corr = ((t * 301) + 1004);
4608
4609 corr = corr * ((150142 * state1) / 10000 - 78642);
4610 corr /= 100000;
20e4d407 4611 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 4612
4613 state2 = (corr2 * state1) / 10000;
4614 state2 /= 100; /* convert to mW */
4615
02d71956 4616 __i915_update_gfx_val(dev_priv);
eb48eb00 4617
20e4d407 4618 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 4619}
4620
f531dcb2
CW		 4621unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4622{
4623 unsigned long val;
4624
4625 if (dev_priv->info->gen != 5)
4626 return 0;
4627
4628 spin_lock_irq(&mchdev_lock);
4629
4630 val = __i915_gfx_val(dev_priv);
4631
4632 spin_unlock_irq(&mchdev_lock);
4633
4634 return val;
4635}
4636
eb48eb00
DV		 4637/**
4638 * i915_read_mch_val - return value for IPS use
4639 *
4640 * Calculate and return a value for the IPS driver to use when deciding whether
4641 * we have thermal and power headroom to increase CPU or GPU power budget.
4642 */
4643unsigned long i915_read_mch_val(void)
4644{
4645 struct drm_i915_private *dev_priv;
4646 unsigned long chipset_val, graphics_val, ret = 0;
4647
9270388e 4648 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4649 if (!i915_mch_dev)
4650 goto out_unlock;
4651 dev_priv = i915_mch_dev;
4652
f531dcb2
CW		 4653 chipset_val = __i915_chipset_val(dev_priv);
4654 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 4655
4656 ret = chipset_val + graphics_val;
4657
4658out_unlock:
9270388e 4659 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4660
4661 return ret;
4662}
4663EXPORT_SYMBOL_GPL(i915_read_mch_val);
4664
4665/**
4666 * i915_gpu_raise - raise GPU frequency limit
4667 *
4668 * Raise the limit; IPS indicates we have thermal headroom.
4669 */
4670bool i915_gpu_raise(void)
4671{
4672 struct drm_i915_private *dev_priv;
4673 bool ret = true;
4674
9270388e 4675 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4676 if (!i915_mch_dev) {
4677 ret = false;
4678 goto out_unlock;
4679 }
4680 dev_priv = i915_mch_dev;
4681
20e4d407
DV		 4682 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4683 dev_priv->ips.max_delay--;
eb48eb00
DV		 4684
4685out_unlock:
9270388e 4686 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4687
4688 return ret;
4689}
4690EXPORT_SYMBOL_GPL(i915_gpu_raise);
4691
4692/**
4693 * i915_gpu_lower - lower GPU frequency limit
4694 *
4695 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4696 * frequency maximum.
4697 */
4698bool i915_gpu_lower(void)
4699{
4700 struct drm_i915_private *dev_priv;
4701 bool ret = true;
4702
9270388e 4703 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4704 if (!i915_mch_dev) {
4705 ret = false;
4706 goto out_unlock;
4707 }
4708 dev_priv = i915_mch_dev;
4709
20e4d407
DV		 4710 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4711 dev_priv->ips.max_delay++;
eb48eb00
DV		 4712
4713out_unlock:
9270388e 4714 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4715
4716 return ret;
4717}
4718EXPORT_SYMBOL_GPL(i915_gpu_lower);
4719
4720/**
4721 * i915_gpu_busy - indicate GPU business to IPS
4722 *
4723 * Tell the IPS driver whether or not the GPU is busy.
4724 */
4725bool i915_gpu_busy(void)
4726{
4727 struct drm_i915_private *dev_priv;
f047e395 4728 struct intel_ring_buffer *ring;
eb48eb00 4729 bool ret = false;
f047e395 4730 int i;
eb48eb00 4731
9270388e 4732 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4733 if (!i915_mch_dev)
4734 goto out_unlock;
4735 dev_priv = i915_mch_dev;
4736
f047e395
CW		 4737 for_each_ring(ring, dev_priv, i)
4738 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 4739
4740out_unlock:
9270388e 4741 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4742
4743 return ret;
4744}
4745EXPORT_SYMBOL_GPL(i915_gpu_busy);
4746
4747/**
4748 * i915_gpu_turbo_disable - disable graphics turbo
4749 *
4750 * Disable graphics turbo by resetting the max frequency and setting the
4751 * current frequency to the default.
4752 */
4753bool i915_gpu_turbo_disable(void)
4754{
4755 struct drm_i915_private *dev_priv;
4756 bool ret = true;
4757
9270388e 4758 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4759 if (!i915_mch_dev) {
4760 ret = false;
4761 goto out_unlock;
4762 }
4763 dev_priv = i915_mch_dev;
4764
20e4d407 4765 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 4766
20e4d407 4767 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 4768 ret = false;
4769
4770out_unlock:
9270388e 4771 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4772
4773 return ret;
4774}
4775EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4776
4777/**
4778 * Tells the intel_ips driver that the i915 driver is now loaded, if
4779 * IPS got loaded first.
4780 *
4781 * This awkward dance is so that neither module has to depend on the
4782 * other in order for IPS to do the appropriate communication of
4783 * GPU turbo limits to i915.
4784 */
4785static void
4786ips_ping_for_i915_load(void)
4787{
4788 void (*link)(void);
4789
4790 link = symbol_get(ips_link_to_i915_driver);
4791 if (link) {
4792 link();
4793 symbol_put(ips_link_to_i915_driver);
4794 }
4795}
4796
4797void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4798{
02d71956
DV		 4799 /* We only register the i915 ips part with intel-ips once everything is
4800 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 4801 spin_lock_irq(&mchdev_lock);
eb48eb00 4802 i915_mch_dev = dev_priv;
9270388e 4803 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4804
4805 ips_ping_for_i915_load();
4806}
4807
4808void intel_gpu_ips_teardown(void)
4809{
9270388e 4810 spin_lock_irq(&mchdev_lock);
eb48eb00 4811 i915_mch_dev = NULL;
9270388e 4812 spin_unlock_irq(&mchdev_lock);
eb48eb00 4813}
8090c6b9 4814static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 4815{
4816 struct drm_i915_private *dev_priv = dev->dev_private;
4817 u32 lcfuse;
4818 u8 pxw[16];
4819 int i;
4820
4821 /* Disable to program */
4822 I915_WRITE(ECR, 0);
4823 POSTING_READ(ECR);
4824
4825 /* Program energy weights for various events */
4826 I915_WRITE(SDEW, 0x15040d00);
4827 I915_WRITE(CSIEW0, 0x007f0000);
4828 I915_WRITE(CSIEW1, 0x1e220004);
4829 I915_WRITE(CSIEW2, 0x04000004);
4830
4831 for (i = 0; i < 5; i++)
4832 I915_WRITE(PEW + (i * 4), 0);
4833 for (i = 0; i < 3; i++)
4834 I915_WRITE(DEW + (i * 4), 0);
4835
4836 /* Program P-state weights to account for frequency power adjustment */
4837 for (i = 0; i < 16; i++) {
4838 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4839 unsigned long freq = intel_pxfreq(pxvidfreq);
4840 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4841 PXVFREQ_PX_SHIFT;
4842 unsigned long val;
4843
4844 val = vid * vid;
4845 val *= (freq / 1000);
4846 val *= 255;
4847 val /= (127*127*900);
4848 if (val > 0xff)
4849 DRM_ERROR("bad pxval: %ld\n", val);
4850 pxw[i] = val;
4851 }
4852 /* Render standby states get 0 weight */
4853 pxw[14] = 0;
4854 pxw[15] = 0;
4855
4856 for (i = 0; i < 4; i++) {
4857 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4858 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4859 I915_WRITE(PXW + (i * 4), val);
4860 }
4861
4862 /* Adjust magic regs to magic values (more experimental results) */
4863 I915_WRITE(OGW0, 0);
4864 I915_WRITE(OGW1, 0);
4865 I915_WRITE(EG0, 0x00007f00);
4866 I915_WRITE(EG1, 0x0000000e);
4867 I915_WRITE(EG2, 0x000e0000);
4868 I915_WRITE(EG3, 0x68000300);
4869 I915_WRITE(EG4, 0x42000000);
4870 I915_WRITE(EG5, 0x00140031);
4871 I915_WRITE(EG6, 0);
4872 I915_WRITE(EG7, 0);
4873
4874 for (i = 0; i < 8; i++)
4875 I915_WRITE(PXWL + (i * 4), 0);
4876
4877 /* Enable PMON + select events */
4878 I915_WRITE(ECR, 0x80000019);
4879
4880 lcfuse = I915_READ(LCFUSE02);
4881
20e4d407 4882 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 4883}
4884
8090c6b9
DV		 4885void intel_disable_gt_powersave(struct drm_device *dev)
4886{
1a01ab3b
JB		 4887 struct drm_i915_private *dev_priv = dev->dev_private;
4888
fd0c0642
DV		 4889 /* Interrupts should be disabled already to avoid re-arming. */
4890 WARN_ON(dev->irq_enabled);
4891
930ebb46 4892 if (IS_IRONLAKE_M(dev)) {
8090c6b9 4893 ironlake_disable_drps(dev);
930ebb46 4894 ironlake_disable_rc6(dev);
0a073b84 4895 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b 4896 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
250848ca 4897 cancel_work_sync(&dev_priv->rps.work);
4fc688ce 4898 mutex_lock(&dev_priv->rps.hw_lock);
d20d4f0c
JB		 4899 if (IS_VALLEYVIEW(dev))
4900 valleyview_disable_rps(dev);
4901 else
4902 gen6_disable_rps(dev);
c0951f0c 4903 dev_priv->rps.enabled = false;
4fc688ce 4904 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 4905 }
8090c6b9
DV		 4906}
4907
1a01ab3b
JB		 4908static void intel_gen6_powersave_work(struct work_struct *work)
4909{
4910 struct drm_i915_private *dev_priv =
4911 container_of(work, struct drm_i915_private,
4912 rps.delayed_resume_work.work);
4913 struct drm_device *dev = dev_priv->dev;
4914
4fc688ce 4915 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84
JB		 4916
4917 if (IS_VALLEYVIEW(dev)) {
4918 valleyview_enable_rps(dev);
6edee7f3
BW		 4919 } else if (IS_BROADWELL(dev)) {
4920 gen8_enable_rps(dev);
4921 gen6_update_ring_freq(dev);
0a073b84
JB		 4922 } else {
4923 gen6_enable_rps(dev);
4924 gen6_update_ring_freq(dev);
4925 }
c0951f0c 4926 dev_priv->rps.enabled = true;
4fc688ce 4927 mutex_unlock(&dev_priv->rps.hw_lock);
1a01ab3b
JB		 4928}
4929
8090c6b9
DV		 4930void intel_enable_gt_powersave(struct drm_device *dev)
4931{
1a01ab3b
JB		 4932 struct drm_i915_private *dev_priv = dev->dev_private;
4933
8090c6b9
DV		 4934 if (IS_IRONLAKE_M(dev)) {
4935 ironlake_enable_drps(dev);
4936 ironlake_enable_rc6(dev);
4937 intel_init_emon(dev);
0a073b84 4938 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1a01ab3b
JB		 4939 /*
4940 * PCU communication is slow and this doesn't need to be
4941 * done at any specific time, so do this out of our fast path
4942 * to make resume and init faster.
4943 */
4944 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4945 round_jiffies_up_relative(HZ));
8090c6b9
DV		 4946 }
4947}
4948
3107bd48
DV		 4949static void ibx_init_clock_gating(struct drm_device *dev)
4950{
4951 struct drm_i915_private *dev_priv = dev->dev_private;
4952
4953 /*
4954 * On Ibex Peak and Cougar Point, we need to disable clock
4955 * gating for the panel power sequencer or it will fail to
4956 * start up when no ports are active.
4957 */
4958 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4959}
4960
0e088b8f
VS		 4961static void g4x_disable_trickle_feed(struct drm_device *dev)
4962{
4963 struct drm_i915_private *dev_priv = dev->dev_private;
4964 int pipe;
4965
4966 for_each_pipe(pipe) {
4967 I915_WRITE(DSPCNTR(pipe),
4968 I915_READ(DSPCNTR(pipe)) |
4969 DISPPLANE_TRICKLE_FEED_DISABLE);
1dba99f4 4970 intel_flush_primary_plane(dev_priv, pipe);
0e088b8f
VS		 4971 }
4972}
4973
1fa61106 4974static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4975{
4976 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4977 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4978
f1e8fa56
DL		 4979 /*
4980 * Required for FBC
4981 * WaFbcDisableDpfcClockGating:ilk
4982 */
4d47e4f5
DL		 4983 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4984 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4985 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4986
4987 I915_WRITE(PCH_3DCGDIS0,
4988 MARIUNIT_CLOCK_GATE_DISABLE |
4989 SVSMUNIT_CLOCK_GATE_DISABLE);
4990 I915_WRITE(PCH_3DCGDIS1,
4991 VFMUNIT_CLOCK_GATE_DISABLE);
4992
6f1d69b0
ED		 4993 /*
4994 * According to the spec the following bits should be set in
4995 * order to enable memory self-refresh
4996 * The bit 22/21 of 0x42004
4997 * The bit 5 of 0x42020
4998 * The bit 15 of 0x45000
4999 */
5000 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5001 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5002 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 5003 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5004 I915_WRITE(DISP_ARB_CTL,
5005 (I915_READ(DISP_ARB_CTL) |
5006 DISP_FBC_WM_DIS));
5007 I915_WRITE(WM3_LP_ILK, 0);
5008 I915_WRITE(WM2_LP_ILK, 0);
5009 I915_WRITE(WM1_LP_ILK, 0);
5010
5011 /*
5012 * Based on the document from hardware guys the following bits
5013 * should be set unconditionally in order to enable FBC.
5014 * The bit 22 of 0x42000
5015 * The bit 22 of 0x42004
5016 * The bit 7,8,9 of 0x42020.
5017 */
5018 if (IS_IRONLAKE_M(dev)) {
4bb35334 5019 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 5020 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5021 I915_READ(ILK_DISPLAY_CHICKEN1) |
5022 ILK_FBCQ_DIS);
5023 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5024 I915_READ(ILK_DISPLAY_CHICKEN2) |
5025 ILK_DPARB_GATE);
6f1d69b0
ED		 5026 }
5027
4d47e4f5
DL		 5028 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5029
6f1d69b0
ED		 5030 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5031 I915_READ(ILK_DISPLAY_CHICKEN2) |
5032 ILK_ELPIN_409_SELECT);
5033 I915_WRITE(_3D_CHICKEN2,
5034 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5035 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 5036
ecdb4eb7 5037 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 5038 I915_WRITE(CACHE_MODE_0,
5039 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 5040
0e088b8f 5041 g4x_disable_trickle_feed(dev);
bdad2b2f 5042
3107bd48
DV		 5043 ibx_init_clock_gating(dev);
5044}
5045
5046static void cpt_init_clock_gating(struct drm_device *dev)
5047{
5048 struct drm_i915_private *dev_priv = dev->dev_private;
5049 int pipe;
3f704fa2 5050 uint32_t val;
3107bd48
DV		 5051
5052 /*
5053 * On Ibex Peak and Cougar Point, we need to disable clock
5054 * gating for the panel power sequencer or it will fail to
5055 * start up when no ports are active.
5056 */
cd664078
JB		 5057 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5058 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5059 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 5060 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5061 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 5062 /* The below fixes the weird display corruption, a few pixels shifted
5063 * downward, on (only) LVDS of some HP laptops with IVY.
5064 */
3f704fa2 5065 for_each_pipe(pipe) {
dc4bd2d1
PZ		 5066 val = I915_READ(TRANS_CHICKEN2(pipe));
5067 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5068 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 5069 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 5070 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 5071 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5072 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5073 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 5074 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5075 }
3107bd48
DV		 5076 /* WADP0ClockGatingDisable */
5077 for_each_pipe(pipe) {
5078 I915_WRITE(TRANS_CHICKEN1(pipe),
5079 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5080 }
6f1d69b0
ED		 5081}
5082
1d7aaa0c
DV		 5083static void gen6_check_mch_setup(struct drm_device *dev)
5084{
5085 struct drm_i915_private *dev_priv = dev->dev_private;
5086 uint32_t tmp;
5087
5088 tmp = I915_READ(MCH_SSKPD);
5089 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
5090 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
5091 DRM_INFO("This can cause pipe underruns and display issues.\n");
5092 DRM_INFO("Please upgrade your BIOS to fix this.\n");
5093 }
5094}
5095
1fa61106 5096static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5097{
5098 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5099 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5100
231e54f6 5101 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 5102
5103 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5104 I915_READ(ILK_DISPLAY_CHICKEN2) |
5105 ILK_ELPIN_409_SELECT);
5106
ecdb4eb7 5107 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 5108 I915_WRITE(_3D_CHICKEN,
5109 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5110
ecdb4eb7 5111 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 5112 if (IS_SNB_GT1(dev))
5113 I915_WRITE(GEN6_GT_MODE,
5114 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5115
6f1d69b0
ED		 5116 I915_WRITE(WM3_LP_ILK, 0);
5117 I915_WRITE(WM2_LP_ILK, 0);
5118 I915_WRITE(WM1_LP_ILK, 0);
5119
6f1d69b0 5120 I915_WRITE(CACHE_MODE_0,
50743298 5121 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 5122
5123 I915_WRITE(GEN6_UCGCTL1,
5124 I915_READ(GEN6_UCGCTL1) |
5125 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5126 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5127
5128 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5129 * gating disable must be set. Failure to set it results in
5130 * flickering pixels due to Z write ordering failures after
5131 * some amount of runtime in the Mesa "fire" demo, and Unigine
5132 * Sanctuary and Tropics, and apparently anything else with
5133 * alpha test or pixel discard.
5134 *
5135 * According to the spec, bit 11 (RCCUNIT) must also be set,
5136 * but we didn't debug actual testcases to find it out.
0f846f81 5137 *
ecdb4eb7
DL		 5138 * Also apply WaDisableVDSUnitClockGating:snb and
5139 * WaDisableRCPBUnitClockGating:snb.
6f1d69b0
ED		 5140 */
5141 I915_WRITE(GEN6_UCGCTL2,
0f846f81 5142 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6f1d69b0
ED		 5143 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5144 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5145
5146 /* Bspec says we need to always set all mask bits. */
26b6e44a
KG		 5147 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
5148 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
6f1d69b0
ED		 5149
5150 /*
5151 * According to the spec the following bits should be
5152 * set in order to enable memory self-refresh and fbc:
5153 * The bit21 and bit22 of 0x42000
5154 * The bit21 and bit22 of 0x42004
5155 * The bit5 and bit7 of 0x42020
5156 * The bit14 of 0x70180
5157 * The bit14 of 0x71180
4bb35334
DL		 5158 *
5159 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 5160 */
5161 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5162 I915_READ(ILK_DISPLAY_CHICKEN1) |
5163 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5164 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5165 I915_READ(ILK_DISPLAY_CHICKEN2) |
5166 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 5167 I915_WRITE(ILK_DSPCLK_GATE_D,
5168 I915_READ(ILK_DSPCLK_GATE_D) |
5169 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5170 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 5171
0e088b8f 5172 g4x_disable_trickle_feed(dev);
f8f2ac9a
BW		 5173
5174 /* The default value should be 0x200 according to docs, but the two
5175 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
5176 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
5177 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3107bd48
DV		 5178
5179 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5180
5181 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5182}
5183
5184static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5185{
5186 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5187
5188 reg &= ~GEN7_FF_SCHED_MASK;
5189 reg |= GEN7_FF_TS_SCHED_HW;
5190 reg |= GEN7_FF_VS_SCHED_HW;
5191 reg |= GEN7_FF_DS_SCHED_HW;
5192
41c0b3a8
BW		 5193 if (IS_HASWELL(dev_priv->dev))
5194 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
5195
6f1d69b0
ED		 5196 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5197}
5198
17a303ec
PZ		 5199static void lpt_init_clock_gating(struct drm_device *dev)
5200{
5201 struct drm_i915_private *dev_priv = dev->dev_private;
5202
5203 /*
5204 * TODO: this bit should only be enabled when really needed, then
5205 * disabled when not needed anymore in order to save power.
5206 */
5207 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5208 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5209 I915_READ(SOUTH_DSPCLK_GATE_D) |
5210 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 5211
5212 /* WADPOClockGatingDisable:hsw */
5213 I915_WRITE(_TRANSA_CHICKEN1,
5214 I915_READ(_TRANSA_CHICKEN1) |
5215 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 5216}
5217
7d708ee4
ID		 5218static void lpt_suspend_hw(struct drm_device *dev)
5219{
5220 struct drm_i915_private *dev_priv = dev->dev_private;
5221
5222 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5223 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5224
5225 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5226 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5227 }
5228}
5229
1020a5c2
BW		 5230static void gen8_init_clock_gating(struct drm_device *dev)
5231{
5232 struct drm_i915_private *dev_priv = dev->dev_private;
fe4ab3ce 5233 enum pipe i;
1020a5c2
BW		 5234
5235 I915_WRITE(WM3_LP_ILK, 0);
5236 I915_WRITE(WM2_LP_ILK, 0);
5237 I915_WRITE(WM1_LP_ILK, 0);
50ed5fbd
BW		 5238
5239 /* FIXME(BDW): Check all the w/a, some might only apply to
5240 * pre-production hw. */
5241
fd392b60
BW		 5242 WARN(!i915_preliminary_hw_support,
5243 "GEN8_CENTROID_PIXEL_OPT_DIS not be needed for production\n");
5244 I915_WRITE(HALF_SLICE_CHICKEN3,
5245 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
bf66347c
BW		 5246 I915_WRITE(HALF_SLICE_CHICKEN3,
5247 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
4afe8d33
BW		 5248 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5249
7f88da0c
BW		 5250 I915_WRITE(_3D_CHICKEN3,
5251 _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
5252
a75f3628
BW		 5253 I915_WRITE(COMMON_SLICE_CHICKEN2,
5254 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
5255
4c2e7a5f
BW		 5256 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5257 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
5258
50ed5fbd
BW		 5259 /* WaSwitchSolVfFArbitrationPriority */
5260 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce
BW		 5261
5262 /* WaPsrDPAMaskVBlankInSRD */
5263 I915_WRITE(CHICKEN_PAR1_1,
5264 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5265
5266 /* WaPsrDPRSUnmaskVBlankInSRD */
5267 for_each_pipe(i) {
5268 I915_WRITE(CHICKEN_PIPESL_1(i),
5269 I915_READ(CHICKEN_PIPESL_1(i) |
5270 DPRS_MASK_VBLANK_SRD));
5271 }
1020a5c2
BW		 5272}
5273
cad2a2d7
ED		 5274static void haswell_init_clock_gating(struct drm_device *dev)
5275{
5276 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7
ED		 5277
5278 I915_WRITE(WM3_LP_ILK, 0);
5279 I915_WRITE(WM2_LP_ILK, 0);
5280 I915_WRITE(WM1_LP_ILK, 0);
5281
5282 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5283 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
cad2a2d7
ED		 5284 */
5285 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5286
ecdb4eb7 5287 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
cad2a2d7
ED		 5288 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5289 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5290
ecdb4eb7 5291 /* WaApplyL3ControlAndL3ChickenMode:hsw */
cad2a2d7
ED		 5292 I915_WRITE(GEN7_L3CNTLREG1,
5293 GEN7_WA_FOR_GEN7_L3_CONTROL);
5294 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5295 GEN7_WA_L3_CHICKEN_MODE);
5296
f3fc4884
FJ		 5297 /* L3 caching of data atomics doesn't work -- disable it. */
5298 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5299 I915_WRITE(HSW_ROW_CHICKEN3,
5300 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5301
ecdb4eb7 5302 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 5303 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5304 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5305 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5306
ecdb4eb7 5307 /* WaVSRefCountFullforceMissDisable:hsw */
cad2a2d7
ED		 5308 gen7_setup_fixed_func_scheduler(dev_priv);
5309
ecdb4eb7 5310 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 5311 I915_WRITE(CACHE_MODE_1,
5312 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 5313
ecdb4eb7 5314 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 5315 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5316
90a88643
PZ		 5317 /* WaRsPkgCStateDisplayPMReq:hsw */
5318 I915_WRITE(CHICKEN_PAR1_1,
5319 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 5320
17a303ec 5321 lpt_init_clock_gating(dev);
cad2a2d7
ED		 5322}
5323
1fa61106 5324static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5325{
5326 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 5327 uint32_t snpcr;
6f1d69b0 5328
6f1d69b0
ED		 5329 I915_WRITE(WM3_LP_ILK, 0);
5330 I915_WRITE(WM2_LP_ILK, 0);
5331 I915_WRITE(WM1_LP_ILK, 0);
5332
231e54f6 5333 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5334
ecdb4eb7 5335 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 5336 I915_WRITE(_3D_CHICKEN3,
5337 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5338
ecdb4eb7 5339 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 5340 I915_WRITE(IVB_CHICKEN3,
5341 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5342 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5343
ecdb4eb7 5344 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 5345 if (IS_IVB_GT1(dev))
5346 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5347 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5348 else
5349 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
5350 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5351
ecdb4eb7 5352 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 5353 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5354 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5355
ecdb4eb7 5356 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 5357 I915_WRITE(GEN7_L3CNTLREG1,
5358 GEN7_WA_FOR_GEN7_L3_CONTROL);
5359 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 5360 GEN7_WA_L3_CHICKEN_MODE);
5361 if (IS_IVB_GT1(dev))
5362 I915_WRITE(GEN7_ROW_CHICKEN2,
5363 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5364 else
5365 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5366 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5367
6f1d69b0 5368
ecdb4eb7 5369 /* WaForceL3Serialization:ivb */
61939d97
JB		 5370 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5371 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5372
0f846f81
JB		 5373 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5374 * gating disable must be set. Failure to set it results in
5375 * flickering pixels due to Z write ordering failures after
5376 * some amount of runtime in the Mesa "fire" demo, and Unigine
5377 * Sanctuary and Tropics, and apparently anything else with
5378 * alpha test or pixel discard.
5379 *
5380 * According to the spec, bit 11 (RCCUNIT) must also be set,
5381 * but we didn't debug actual testcases to find it out.
5382 *
5383 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5384 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 5385 */
5386 I915_WRITE(GEN6_UCGCTL2,
5387 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5388 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5389
ecdb4eb7 5390 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 5391 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5392 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5393 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5394
0e088b8f 5395 g4x_disable_trickle_feed(dev);
6f1d69b0 5396
ecdb4eb7 5397 /* WaVSRefCountFullforceMissDisable:ivb */
6f1d69b0 5398 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 5399
ecdb4eb7 5400 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 5401 I915_WRITE(CACHE_MODE_1,
5402 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223
BW		 5403
5404 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5405 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5406 snpcr |= GEN6_MBC_SNPCR_MED;
5407 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 5408
ab5c608b
BW		 5409 if (!HAS_PCH_NOP(dev))
5410 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5411
5412 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5413}
5414
1fa61106 5415static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5416{
5417 struct drm_i915_private *dev_priv = dev->dev_private;
85b1d7b3
JB		 5418 u32 val;
5419
5420 mutex_lock(&dev_priv->rps.hw_lock);
5421 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5422 mutex_unlock(&dev_priv->rps.hw_lock);
5423 switch ((val >> 6) & 3) {
5424 case 0:
85b1d7b3
JB		 5425 dev_priv->mem_freq = 800;
5426 break;
f64a28a7 5427 case 1:
85b1d7b3
JB		 5428 dev_priv->mem_freq = 1066;
5429 break;
f64a28a7 5430 case 2:
85b1d7b3
JB		 5431 dev_priv->mem_freq = 1333;
5432 break;
f64a28a7 5433 case 3:
2325991e 5434 dev_priv->mem_freq = 1333;
f64a28a7 5435 break;
85b1d7b3
JB		 5436 }
5437 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
6f1d69b0 5438
d7fe0cc0 5439 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5440
ecdb4eb7 5441 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 5442 I915_WRITE(_3D_CHICKEN3,
5443 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5444
ecdb4eb7 5445 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 5446 I915_WRITE(IVB_CHICKEN3,
5447 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5448 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5449
ecdb4eb7 5450 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 5451 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 5452 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5453 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 5454
ecdb4eb7 5455 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
6f1d69b0
ED		 5456 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5457 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5458
ecdb4eb7 5459 /* WaApplyL3ControlAndL3ChickenMode:vlv */
d0cf5ead 5460 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
6f1d69b0
ED		 5461 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
5462
ecdb4eb7 5463 /* WaForceL3Serialization:vlv */
61939d97
JB		 5464 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5465 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5466
ecdb4eb7 5467 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 5468 I915_WRITE(GEN7_ROW_CHICKEN2,
5469 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5470
ecdb4eb7 5471 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 5472 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5473 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5474 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5475
0f846f81
JB		 5476 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5477 * gating disable must be set. Failure to set it results in
5478 * flickering pixels due to Z write ordering failures after
5479 * some amount of runtime in the Mesa "fire" demo, and Unigine
5480 * Sanctuary and Tropics, and apparently anything else with
5481 * alpha test or pixel discard.
5482 *
5483 * According to the spec, bit 11 (RCCUNIT) must also be set,
5484 * but we didn't debug actual testcases to find it out.
5485 *
5486 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5487 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81 5488 *
ecdb4eb7
DL		 5489 * Also apply WaDisableVDSUnitClockGating:vlv and
5490 * WaDisableRCPBUnitClockGating:vlv.
0f846f81
JB		 5491 */
5492 I915_WRITE(GEN6_UCGCTL2,
5493 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6edaa7fc 5494 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
0f846f81
JB		 5495 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5496 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5497 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5498
e3f33d46
JB		 5499 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5500
e0d8d59b 5501 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 5502
6b26c86d
DV		 5503 I915_WRITE(CACHE_MODE_1,
5504 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 5505
2d809570 5506 /*
ecdb4eb7 5507 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 5508 * Disable clock gating on th GCFG unit to prevent a delay
5509 * in the reporting of vblank events.
5510 */
4e8c84a5
JB		 5511 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
5512
5513 /* Conservative clock gating settings for now */
5514 I915_WRITE(0x9400, 0xffffffff);
5515 I915_WRITE(0x9404, 0xffffffff);
5516 I915_WRITE(0x9408, 0xffffffff);
5517 I915_WRITE(0x940c, 0xffffffff);
5518 I915_WRITE(0x9410, 0xffffffff);
5519 I915_WRITE(0x9414, 0xffffffff);
5520 I915_WRITE(0x9418, 0xffffffff);
6f1d69b0
ED		 5521}
5522
1fa61106 5523static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5524{
5525 struct drm_i915_private *dev_priv = dev->dev_private;
5526 uint32_t dspclk_gate;
5527
5528 I915_WRITE(RENCLK_GATE_D1, 0);
5529 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5530 GS_UNIT_CLOCK_GATE_DISABLE |
5531 CL_UNIT_CLOCK_GATE_DISABLE);
5532 I915_WRITE(RAMCLK_GATE_D, 0);
5533 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5534 OVRUNIT_CLOCK_GATE_DISABLE |
5535 OVCUNIT_CLOCK_GATE_DISABLE;
5536 if (IS_GM45(dev))
5537 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5538 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 5539
5540 /* WaDisableRenderCachePipelinedFlush */
5541 I915_WRITE(CACHE_MODE_0,
5542 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 5543
0e088b8f 5544 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5545}
5546
1fa61106 5547static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5548{
5549 struct drm_i915_private *dev_priv = dev->dev_private;
5550
5551 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5552 I915_WRITE(RENCLK_GATE_D2, 0);
5553 I915_WRITE(DSPCLK_GATE_D, 0);
5554 I915_WRITE(RAMCLK_GATE_D, 0);
5555 I915_WRITE16(DEUC, 0);
20f94967
VS		 5556 I915_WRITE(MI_ARB_STATE,
5557 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 5558}
5559
1fa61106 5560static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5561{
5562 struct drm_i915_private *dev_priv = dev->dev_private;
5563
5564 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5565 I965_RCC_CLOCK_GATE_DISABLE |
5566 I965_RCPB_CLOCK_GATE_DISABLE |
5567 I965_ISC_CLOCK_GATE_DISABLE |
5568 I965_FBC_CLOCK_GATE_DISABLE);
5569 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 5570 I915_WRITE(MI_ARB_STATE,
5571 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 5572}
5573
1fa61106 5574static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5575{
5576 struct drm_i915_private *dev_priv = dev->dev_private;
5577 u32 dstate = I915_READ(D_STATE);
5578
5579 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5580 DSTATE_DOT_CLOCK_GATING;
5581 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 5582
5583 if (IS_PINEVIEW(dev))
5584 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 5585
5586 /* IIR "flip pending" means done if this bit is set */
5587 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6f1d69b0
ED		 5588}
5589
1fa61106 5590static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5591{
5592 struct drm_i915_private *dev_priv = dev->dev_private;
5593
5594 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5595}
5596
1fa61106 5597static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5598{
5599 struct drm_i915_private *dev_priv = dev->dev_private;
5600
5601 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5602}
5603
6f1d69b0
ED		 5604void intel_init_clock_gating(struct drm_device *dev)
5605{
5606 struct drm_i915_private *dev_priv = dev->dev_private;
5607
5608 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 5609}
5610
7d708ee4
ID		 5611void intel_suspend_hw(struct drm_device *dev)
5612{
5613 if (HAS_PCH_LPT(dev))
5614 lpt_suspend_hw(dev);
5615}
5616
c1ca727f
ID		 5617#define for_each_power_well(i, power_well, domain_mask, power_domains) \
5618 for (i = 0; \
5619 i < (power_domains)->power_well_count && \
5620 ((power_well) = &(power_domains)->power_wells[i]); \
5621 i++) \
5622 if ((power_well)->domains & (domain_mask))
5623
5624#define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5625 for (i = (power_domains)->power_well_count - 1; \
5626 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5627 i--) \
5628 if ((power_well)->domains & (domain_mask))
5629
15d199ea
PZ		 5630/**
5631 * We should only use the power well if we explicitly asked the hardware to
5632 * enable it, so check if it's enabled and also check if we've requested it to
5633 * be enabled.
5634 */
c1ca727f
ID		 5635static bool hsw_power_well_enabled(struct drm_device *dev,
5636 struct i915_power_well *power_well)
5637{
5638 struct drm_i915_private *dev_priv = dev->dev_private;
5639
5640 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5641 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5642}
5643
b97186f0
PZ		 5644bool intel_display_power_enabled(struct drm_device *dev,
5645 enum intel_display_power_domain domain)
15d199ea
PZ		 5646{
5647 struct drm_i915_private *dev_priv = dev->dev_private;
c1ca727f
ID		 5648 struct i915_power_domains *power_domains;
5649 struct i915_power_well *power_well;
5650 bool is_enabled;
5651 int i;
15d199ea 5652
c1ca727f
ID		 5653 power_domains = &dev_priv->power_domains;
5654
5655 is_enabled = true;
5656
5657 mutex_lock(&power_domains->lock);
5658 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6f3ef5dd
ID		 5659 if (power_well->always_on)
5660 continue;
5661
c1ca727f
ID		 5662 if (!power_well->is_enabled(dev, power_well)) {
5663 is_enabled = false;
5664 break;
5665 }
5666 }
5667 mutex_unlock(&power_domains->lock);
5668
5669 return is_enabled;
15d199ea
PZ		 5670}
5671
c1ca727f
ID		 5672static void hsw_set_power_well(struct drm_device *dev,
5673 struct i915_power_well *power_well, bool enable)
d0d3e513
ED		 5674{
5675 struct drm_i915_private *dev_priv = dev->dev_private;
fa42e23c 5676 bool is_enabled, enable_requested;
596cc11e 5677 unsigned long irqflags;
fa42e23c 5678 uint32_t tmp;
d0d3e513 5679
fa42e23c 5680 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
6aedd1f5
PZ		 5681 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5682 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
d0d3e513 5683
fa42e23c
PZ		 5684 if (enable) {
5685 if (!enable_requested)
6aedd1f5
PZ		 5686 I915_WRITE(HSW_PWR_WELL_DRIVER,
5687 HSW_PWR_WELL_ENABLE_REQUEST);
d0d3e513 5688
fa42e23c
PZ		 5689 if (!is_enabled) {
5690 DRM_DEBUG_KMS("Enabling power well\n");
5691 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
6aedd1f5 5692 HSW_PWR_WELL_STATE_ENABLED), 20))
fa42e23c
PZ		 5693 DRM_ERROR("Timeout enabling power well\n");
5694 }
596cc11e
BW		 5695
5696 if (IS_BROADWELL(dev)) {
5697 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5698 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5699 dev_priv->de_irq_mask[PIPE_B]);
5700 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5701 ~dev_priv->de_irq_mask[PIPE_B] |
5702 GEN8_PIPE_VBLANK);
5703 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5704 dev_priv->de_irq_mask[PIPE_C]);
5705 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5706 ~dev_priv->de_irq_mask[PIPE_C] |
5707 GEN8_PIPE_VBLANK);
5708 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5709 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5710 }
fa42e23c
PZ		 5711 } else {
5712 if (enable_requested) {
9dbd8feb
PZ		 5713 enum pipe p;
5714
fa42e23c 5715 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
9dbd8feb 5716 POSTING_READ(HSW_PWR_WELL_DRIVER);
fa42e23c 5717 DRM_DEBUG_KMS("Requesting to disable the power well\n");
9dbd8feb
PZ		 5718
5719 /*
5720 * After this, the registers on the pipes that are part
5721 * of the power well will become zero, so we have to
5722 * adjust our counters according to that.
5723 *
5724 * FIXME: Should we do this in general in
5725 * drm_vblank_post_modeset?
5726 */
5727 spin_lock_irqsave(&dev->vbl_lock, irqflags);
5728 for_each_pipe(p)
5729 if (p != PIPE_A)
5380e929 5730 dev->vblank[p].last = 0;
9dbd8feb 5731 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
d0d3e513
ED		 5732 }
5733 }
fa42e23c 5734}
d0d3e513 5735
b4ed4484
ID		 5736static void __intel_power_well_get(struct drm_device *dev,
5737 struct i915_power_well *power_well)
2d66aef5 5738{
c1ca727f
ID		 5739 if (!power_well->count++ && power_well->set)
5740 power_well->set(dev, power_well, true);
2d66aef5
VS		 5741}
5742
b4ed4484
ID		 5743static void __intel_power_well_put(struct drm_device *dev,
5744 struct i915_power_well *power_well)
2d66aef5
VS		 5745{
5746 WARN_ON(!power_well->count);
c1ca727f
ID		 5747
5748 if (!--power_well->count && power_well->set && i915_disable_power_well)
5749 power_well->set(dev, power_well, false);
2d66aef5
VS		 5750}
5751
6765625e
VS		 5752void intel_display_power_get(struct drm_device *dev,
5753 enum intel_display_power_domain domain)
5754{
5755 struct drm_i915_private *dev_priv = dev->dev_private;
83c00f55 5756 struct i915_power_domains *power_domains;
c1ca727f
ID		 5757 struct i915_power_well *power_well;
5758 int i;
6765625e 5759
83c00f55
ID		 5760 power_domains = &dev_priv->power_domains;
5761
5762 mutex_lock(&power_domains->lock);
1da51581
ID		 5763
5764#if IS_ENABLED(CONFIG_DEBUG_FS)
5765 power_domains->domain_use_count[domain]++;
5766#endif
c1ca727f
ID		 5767 for_each_power_well(i, power_well, BIT(domain), power_domains)
5768 __intel_power_well_get(dev, power_well);
1da51581 5769
83c00f55 5770 mutex_unlock(&power_domains->lock);
6765625e
VS		 5771}
5772
5773void intel_display_power_put(struct drm_device *dev,
5774 enum intel_display_power_domain domain)
5775{
5776 struct drm_i915_private *dev_priv = dev->dev_private;
83c00f55 5777 struct i915_power_domains *power_domains;
c1ca727f
ID		 5778 struct i915_power_well *power_well;
5779 int i;
6765625e 5780
83c00f55
ID		 5781 power_domains = &dev_priv->power_domains;
5782
5783 mutex_lock(&power_domains->lock);
1da51581 5784
c1ca727f
ID		 5785 for_each_power_well_rev(i, power_well, BIT(domain), power_domains)
5786 __intel_power_well_put(dev, power_well);
1da51581
ID		 5787
5788#if IS_ENABLED(CONFIG_DEBUG_FS)
5789 WARN_ON(!power_domains->domain_use_count[domain]);
5790 power_domains->domain_use_count[domain]--;
5791#endif
5792
83c00f55 5793 mutex_unlock(&power_domains->lock);
6765625e
VS		 5794}
5795
83c00f55 5796static struct i915_power_domains *hsw_pwr;
a38911a3
WX		 5797
5798/* Display audio driver power well request */
5799void i915_request_power_well(void)
5800{
b4ed4484
ID		 5801 struct drm_i915_private *dev_priv;
5802
a38911a3
WX		 5803 if (WARN_ON(!hsw_pwr))
5804 return;
5805
b4ed4484
ID		 5806 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5807 power_domains);
fbeeaa23 5808 intel_display_power_get(dev_priv->dev, POWER_DOMAIN_AUDIO);
a38911a3
WX		 5809}
5810EXPORT_SYMBOL_GPL(i915_request_power_well);
5811
5812/* Display audio driver power well release */
5813void i915_release_power_well(void)
5814{
b4ed4484
ID		 5815 struct drm_i915_private *dev_priv;
5816
a38911a3
WX		 5817 if (WARN_ON(!hsw_pwr))
5818 return;
5819
b4ed4484
ID		 5820 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5821 power_domains);
fbeeaa23 5822 intel_display_power_put(dev_priv->dev, POWER_DOMAIN_AUDIO);
a38911a3
WX		 5823}
5824EXPORT_SYMBOL_GPL(i915_release_power_well);
5825
1c2256df
ID		 5826static struct i915_power_well i9xx_always_on_power_well[] = {
5827 {
5828 .name = "always-on",
5829 .always_on = 1,
5830 .domains = POWER_DOMAIN_MASK,
5831 },
5832};
5833
c1ca727f 5834static struct i915_power_well hsw_power_wells[] = {
6f3ef5dd
ID		 5835 {
5836 .name = "always-on",
5837 .always_on = 1,
5838 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
5839 },
c1ca727f
ID		 5840 {
5841 .name = "display",
5842 .domains = POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS,
5843 .is_enabled = hsw_power_well_enabled,
5844 .set = hsw_set_power_well,
5845 },
5846};
5847
5848static struct i915_power_well bdw_power_wells[] = {
6f3ef5dd
ID		 5849 {
5850 .name = "always-on",
5851 .always_on = 1,
5852 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
5853 },
c1ca727f
ID		 5854 {
5855 .name = "display",
5856 .domains = POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS,
5857 .is_enabled = hsw_power_well_enabled,
5858 .set = hsw_set_power_well,
5859 },
5860};
5861
5862#define set_power_wells(power_domains, __power_wells) ({ \
5863 (power_domains)->power_wells = (__power_wells); \
5864 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
5865})
5866
ddb642fb 5867int intel_power_domains_init(struct drm_device *dev)
a38911a3
WX		 5868{
5869 struct drm_i915_private *dev_priv = dev->dev_private;
83c00f55 5870 struct i915_power_domains *power_domains = &dev_priv->power_domains;
c1ca727f 5871
83c00f55 5872 mutex_init(&power_domains->lock);
a38911a3 5873
c1ca727f
ID		 5874 /*
5875 * The enabling order will be from lower to higher indexed wells,
5876 * the disabling order is reversed.
5877 */
5878 if (IS_HASWELL(dev)) {
5879 set_power_wells(power_domains, hsw_power_wells);
5880 hsw_pwr = power_domains;
5881 } else if (IS_BROADWELL(dev)) {
5882 set_power_wells(power_domains, bdw_power_wells);
5883 hsw_pwr = power_domains;
5884 } else {
1c2256df 5885 set_power_wells(power_domains, i9xx_always_on_power_well);
c1ca727f 5886 }
a38911a3
WX		 5887
5888 return 0;
5889}
5890
ddb642fb 5891void intel_power_domains_remove(struct drm_device *dev)
a38911a3
WX		 5892{
5893 hsw_pwr = NULL;
5894}
5895
ddb642fb 5896static void intel_power_domains_resume(struct drm_device *dev)
9cdb826c
VS		 5897{
5898 struct drm_i915_private *dev_priv = dev->dev_private;
83c00f55
ID		 5899 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5900 struct i915_power_well *power_well;
c1ca727f 5901 int i;
9cdb826c 5902
83c00f55 5903 mutex_lock(&power_domains->lock);
c1ca727f
ID		 5904 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
5905 if (power_well->set)
5906 power_well->set(dev, power_well, power_well->count > 0);
5907 }
83c00f55 5908 mutex_unlock(&power_domains->lock);
a38911a3
WX		 5909}
5910
fa42e23c
PZ		 5911/*
5912 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5913 * when not needed anymore. We have 4 registers that can request the power well
5914 * to be enabled, and it will only be disabled if none of the registers is
5915 * requesting it to be enabled.
d0d3e513 5916 */
ddb642fb 5917void intel_power_domains_init_hw(struct drm_device *dev)
d0d3e513
ED		 5918{
5919 struct drm_i915_private *dev_priv = dev->dev_private;
d0d3e513 5920
fa42e23c 5921 /* For now, we need the power well to be always enabled. */
baa70707 5922 intel_display_set_init_power(dev, true);
ddb642fb 5923 intel_power_domains_resume(dev);
d0d3e513 5924
f7243ac9
ID		 5925 if (!(IS_HASWELL(dev) || IS_BROADWELL(dev)))
5926 return;
5927
fa42e23c
PZ		 5928 /* We're taking over the BIOS, so clear any requests made by it since
5929 * the driver is in charge now. */
6aedd1f5 5930 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
fa42e23c 5931 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
d0d3e513
ED		 5932}
5933
c67a470b
PZ		 5934/* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
5935void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
5936{
5937 hsw_disable_package_c8(dev_priv);
5938}
5939
5940void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
5941{
5942 hsw_enable_package_c8(dev_priv);
5943}
5944
1fa61106
ED		 5945/* Set up chip specific power management-related functions */
5946void intel_init_pm(struct drm_device *dev)
5947{
5948 struct drm_i915_private *dev_priv = dev->dev_private;
5949
5950 if (I915_HAS_FBC(dev)) {
5951 if (HAS_PCH_SPLIT(dev)) {
5952 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
891348b2 5953 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
abe959c7
RV		 5954 dev_priv->display.enable_fbc =
5955 gen7_enable_fbc;
5956 else
5957 dev_priv->display.enable_fbc =
5958 ironlake_enable_fbc;
1fa61106
ED		 5959 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5960 } else if (IS_GM45(dev)) {
5961 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5962 dev_priv->display.enable_fbc = g4x_enable_fbc;
5963 dev_priv->display.disable_fbc = g4x_disable_fbc;
5964 } else if (IS_CRESTLINE(dev)) {
5965 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5966 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5967 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5968 }
5969 /* 855GM needs testing */
5970 }
5971
c921aba8
DV		 5972 /* For cxsr */
5973 if (IS_PINEVIEW(dev))
5974 i915_pineview_get_mem_freq(dev);
5975 else if (IS_GEN5(dev))
5976 i915_ironlake_get_mem_freq(dev);
5977
1fa61106
ED		 5978 /* For FIFO watermark updates */
5979 if (HAS_PCH_SPLIT(dev)) {
53615a5e
VS		 5980 intel_setup_wm_latency(dev);
5981
1fa61106 5982 if (IS_GEN5(dev)) {
53615a5e
VS		 5983 if (dev_priv->wm.pri_latency[1] &&
5984 dev_priv->wm.spr_latency[1] &&
5985 dev_priv->wm.cur_latency[1])
1fa61106
ED		 5986 dev_priv->display.update_wm = ironlake_update_wm;
5987 else {
5988 DRM_DEBUG_KMS("Failed to get proper latency. "
5989 "Disable CxSR\n");
5990 dev_priv->display.update_wm = NULL;
5991 }
5992 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5993 } else if (IS_GEN6(dev)) {
53615a5e
VS		 5994 if (dev_priv->wm.pri_latency[0] &&
5995 dev_priv->wm.spr_latency[0] &&
5996 dev_priv->wm.cur_latency[0]) {
1fa61106
ED		 5997 dev_priv->display.update_wm = sandybridge_update_wm;
5998 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5999 } else {
6000 DRM_DEBUG_KMS("Failed to read display plane latency. "
6001 "Disable CxSR\n");
6002 dev_priv->display.update_wm = NULL;
6003 }
6004 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
6005 } else if (IS_IVYBRIDGE(dev)) {
53615a5e
VS		 6006 if (dev_priv->wm.pri_latency[0] &&
6007 dev_priv->wm.spr_latency[0] &&
6008 dev_priv->wm.cur_latency[0]) {
c43d0188 6009 dev_priv->display.update_wm = ivybridge_update_wm;
1fa61106
ED		 6010 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
6011 } else {
6012 DRM_DEBUG_KMS("Failed to read display plane latency. "
6013 "Disable CxSR\n");
6014 dev_priv->display.update_wm = NULL;
6015 }
6016 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6b8a5eeb 6017 } else if (IS_HASWELL(dev)) {
53615a5e
VS		 6018 if (dev_priv->wm.pri_latency[0] &&
6019 dev_priv->wm.spr_latency[0] &&
6020 dev_priv->wm.cur_latency[0]) {
1011d8c4 6021 dev_priv->display.update_wm = haswell_update_wm;
526682e9
PZ		 6022 dev_priv->display.update_sprite_wm =
6023 haswell_update_sprite_wm;
6b8a5eeb
ED		 6024 } else {
6025 DRM_DEBUG_KMS("Failed to read display plane latency. "
6026 "Disable CxSR\n");
6027 dev_priv->display.update_wm = NULL;
6028 }
cad2a2d7 6029 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
1020a5c2
BW		 6030 } else if (INTEL_INFO(dev)->gen == 8) {
6031 dev_priv->display.init_clock_gating = gen8_init_clock_gating;
1fa61106
ED		 6032 } else
6033 dev_priv->display.update_wm = NULL;
6034 } else if (IS_VALLEYVIEW(dev)) {
6035 dev_priv->display.update_wm = valleyview_update_wm;
6036 dev_priv->display.init_clock_gating =
6037 valleyview_init_clock_gating;
1fa61106
ED		 6038 } else if (IS_PINEVIEW(dev)) {
6039 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6040 dev_priv->is_ddr3,
6041 dev_priv->fsb_freq,
6042 dev_priv->mem_freq)) {
6043 DRM_INFO("failed to find known CxSR latency "
6044 "(found ddr%s fsb freq %d, mem freq %d), "
6045 "disabling CxSR\n",
6046 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6047 dev_priv->fsb_freq, dev_priv->mem_freq);
6048 /* Disable CxSR and never update its watermark again */
6049 pineview_disable_cxsr(dev);
6050 dev_priv->display.update_wm = NULL;
6051 } else
6052 dev_priv->display.update_wm = pineview_update_wm;
6053 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6054 } else if (IS_G4X(dev)) {
6055 dev_priv->display.update_wm = g4x_update_wm;
6056 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6057 } else if (IS_GEN4(dev)) {
6058 dev_priv->display.update_wm = i965_update_wm;
6059 if (IS_CRESTLINE(dev))
6060 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6061 else if (IS_BROADWATER(dev))
6062 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6063 } else if (IS_GEN3(dev)) {
6064 dev_priv->display.update_wm = i9xx_update_wm;
6065 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6066 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6067 } else if (IS_I865G(dev)) {
6068 dev_priv->display.update_wm = i830_update_wm;
6069 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6070 dev_priv->display.get_fifo_size = i830_get_fifo_size;
6071 } else if (IS_I85X(dev)) {
6072 dev_priv->display.update_wm = i9xx_update_wm;
6073 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6074 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6075 } else {
6076 dev_priv->display.update_wm = i830_update_wm;
6077 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6078 if (IS_845G(dev))
6079 dev_priv->display.get_fifo_size = i845_get_fifo_size;
6080 else
6081 dev_priv->display.get_fifo_size = i830_get_fifo_size;
6082 }
6083}
6084
42c0526c
BW		 6085int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
6086{
4fc688ce 6087 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6088
6089 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6090 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6091 return -EAGAIN;
6092 }
6093
6094 I915_WRITE(GEN6_PCODE_DATA, *val);
6095 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6096
6097 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6098 500)) {
6099 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6100 return -ETIMEDOUT;
6101 }
6102
6103 *val = I915_READ(GEN6_PCODE_DATA);
6104 I915_WRITE(GEN6_PCODE_DATA, 0);
6105
6106 return 0;
6107}
6108
6109int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
6110{
4fc688ce 6111 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6112
6113 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6114 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6115 return -EAGAIN;
6116 }
6117
6118 I915_WRITE(GEN6_PCODE_DATA, val);
6119 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6120
6121 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6122 500)) {
6123 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6124 return -ETIMEDOUT;
6125 }
6126
6127 I915_WRITE(GEN6_PCODE_DATA, 0);
6128
6129 return 0;
6130}
a0e4e199 6131
2ec3815f 6132int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
855ba3be 6133{
07ab118b 6134 int div;
855ba3be 6135
07ab118b 6136 /* 4 x czclk */
2ec3815f 6137 switch (dev_priv->mem_freq) {
855ba3be 6138 case 800:
07ab118b 6139 div = 10;
855ba3be
JB		 6140 break;
6141 case 1066:
07ab118b 6142 div = 12;
855ba3be
JB		 6143 break;
6144 case 1333:
07ab118b 6145 div = 16;
855ba3be
JB		 6146 break;
6147 default:
6148 return -1;
6149 }
6150
2ec3815f 6151 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
855ba3be
JB		 6152}
6153
2ec3815f 6154int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 6155{
07ab118b 6156 int mul;
855ba3be 6157
07ab118b 6158 /* 4 x czclk */
2ec3815f 6159 switch (dev_priv->mem_freq) {
855ba3be 6160 case 800:
07ab118b 6161 mul = 10;
855ba3be
JB		 6162 break;
6163 case 1066:
07ab118b 6164 mul = 12;
855ba3be
JB		 6165 break;
6166 case 1333:
07ab118b 6167 mul = 16;
855ba3be
JB		 6168 break;
6169 default:
6170 return -1;
6171 }
6172
2ec3815f 6173 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
855ba3be
JB		 6174}
6175
907b28c5
CW		 6176void intel_pm_init(struct drm_device *dev)
6177{
6178 struct drm_i915_private *dev_priv = dev->dev_private;
6179
6180 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6181 intel_gen6_powersave_work);
6182}
Linux 6.x block layer and io_uring tree(s)