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drm/i915: shut up gen8+ SDE irq dmesg noise, again
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
dc39fff7
BW		 34/**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51#define INTEL_RC6_ENABLE (1<<0)
52#define INTEL_RC6p_ENABLE (1<<1)
53#define INTEL_RC6pp_ENABLE (1<<2)
54
a82abe43
ID		 55static void bxt_init_clock_gating(struct drm_device *dev)
56{
32608ca2
ID		 57 struct drm_i915_private *dev_priv = dev->dev_private;
58
a7546159
NH		 59 /* WaDisableSDEUnitClockGating:bxt */
60 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
61 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
62
32608ca2
ID		 63 /*
64 * FIXME:
868434c5 65 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 66 */
32608ca2 67 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 68 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
d965e7ac
ID		 69
70 /*
71 * Wa: Backlight PWM may stop in the asserted state, causing backlight
72 * to stay fully on.
73 */
74 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
75 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
76 PWM1_GATING_DIS | PWM2_GATING_DIS);
a82abe43
ID		 77}
78
c921aba8
DV		 79static void i915_pineview_get_mem_freq(struct drm_device *dev)
80{
50227e1c 81 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 82 u32 tmp;
83
84 tmp = I915_READ(CLKCFG);
85
86 switch (tmp & CLKCFG_FSB_MASK) {
87 case CLKCFG_FSB_533:
88 dev_priv->fsb_freq = 533; /* 133*4 */
89 break;
90 case CLKCFG_FSB_800:
91 dev_priv->fsb_freq = 800; /* 200*4 */
92 break;
93 case CLKCFG_FSB_667:
94 dev_priv->fsb_freq = 667; /* 167*4 */
95 break;
96 case CLKCFG_FSB_400:
97 dev_priv->fsb_freq = 400; /* 100*4 */
98 break;
99 }
100
101 switch (tmp & CLKCFG_MEM_MASK) {
102 case CLKCFG_MEM_533:
103 dev_priv->mem_freq = 533;
104 break;
105 case CLKCFG_MEM_667:
106 dev_priv->mem_freq = 667;
107 break;
108 case CLKCFG_MEM_800:
109 dev_priv->mem_freq = 800;
110 break;
111 }
112
113 /* detect pineview DDR3 setting */
114 tmp = I915_READ(CSHRDDR3CTL);
115 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
116}
117
118static void i915_ironlake_get_mem_freq(struct drm_device *dev)
119{
50227e1c 120 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 121 u16 ddrpll, csipll;
122
123 ddrpll = I915_READ16(DDRMPLL1);
124 csipll = I915_READ16(CSIPLL0);
125
126 switch (ddrpll & 0xff) {
127 case 0xc:
128 dev_priv->mem_freq = 800;
129 break;
130 case 0x10:
131 dev_priv->mem_freq = 1066;
132 break;
133 case 0x14:
134 dev_priv->mem_freq = 1333;
135 break;
136 case 0x18:
137 dev_priv->mem_freq = 1600;
138 break;
139 default:
140 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
141 ddrpll & 0xff);
142 dev_priv->mem_freq = 0;
143 break;
144 }
145
20e4d407 146 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 147
148 switch (csipll & 0x3ff) {
149 case 0x00c:
150 dev_priv->fsb_freq = 3200;
151 break;
152 case 0x00e:
153 dev_priv->fsb_freq = 3733;
154 break;
155 case 0x010:
156 dev_priv->fsb_freq = 4266;
157 break;
158 case 0x012:
159 dev_priv->fsb_freq = 4800;
160 break;
161 case 0x014:
162 dev_priv->fsb_freq = 5333;
163 break;
164 case 0x016:
165 dev_priv->fsb_freq = 5866;
166 break;
167 case 0x018:
168 dev_priv->fsb_freq = 6400;
169 break;
170 default:
171 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
172 csipll & 0x3ff);
173 dev_priv->fsb_freq = 0;
174 break;
175 }
176
177 if (dev_priv->fsb_freq == 3200) {
20e4d407 178 dev_priv->ips.c_m = 0;
c921aba8 179 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 180 dev_priv->ips.c_m = 1;
c921aba8 181 } else {
20e4d407 182 dev_priv->ips.c_m = 2;
c921aba8
DV		 183 }
184}
185
b445e3b0
ED		 186static const struct cxsr_latency cxsr_latency_table[] = {
187 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
188 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
189 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
190 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
191 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
192
193 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
194 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
195 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
196 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
197 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
198
199 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
200 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
201 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
202 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
203 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
204
205 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
206 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
207 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
208 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
209 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
210
211 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
212 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
213 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
214 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
215 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
216
217 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
218 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
219 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
220 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
221 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
222};
223
63c62275 224static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 225 int is_ddr3,
226 int fsb,
227 int mem)
228{
229 const struct cxsr_latency *latency;
230 int i;
231
232 if (fsb == 0 || mem == 0)
233 return NULL;
234
235 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
236 latency = &cxsr_latency_table[i];
237 if (is_desktop == latency->is_desktop &&
238 is_ddr3 == latency->is_ddr3 &&
239 fsb == latency->fsb_freq && mem == latency->mem_freq)
240 return latency;
241 }
242
243 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
244
245 return NULL;
246}
247
fc1ac8de
VS		 248static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
249{
250 u32 val;
251
252 mutex_lock(&dev_priv->rps.hw_lock);
253
254 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
255 if (enable)
256 val &= ~FORCE_DDR_HIGH_FREQ;
257 else
258 val |= FORCE_DDR_HIGH_FREQ;
259 val &= ~FORCE_DDR_LOW_FREQ;
260 val |= FORCE_DDR_FREQ_REQ_ACK;
261 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
262
263 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
264 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
265 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
266
267 mutex_unlock(&dev_priv->rps.hw_lock);
268}
269
cfb41411
VS		 270static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
271{
272 u32 val;
273
274 mutex_lock(&dev_priv->rps.hw_lock);
275
276 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
277 if (enable)
278 val |= DSP_MAXFIFO_PM5_ENABLE;
279 else
280 val &= ~DSP_MAXFIFO_PM5_ENABLE;
281 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
282
283 mutex_unlock(&dev_priv->rps.hw_lock);
284}
285
f4998963
VS		 286#define FW_WM(value, plane) \
287 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
288
5209b1f4 289void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 290{
5209b1f4
ID		 291 struct drm_device *dev = dev_priv->dev;
292 u32 val;
b445e3b0 293
666a4537 294 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5209b1f4 295 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 296 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 297 dev_priv->wm.vlv.cxsr = enable;
5209b1f4
ID		 298 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
299 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 300 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 301 } else if (IS_PINEVIEW(dev)) {
302 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
303 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
304 I915_WRITE(DSPFW3, val);
a7a6c498 305 POSTING_READ(DSPFW3);
5209b1f4
ID		 306 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
307 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
308 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
309 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 310 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 311 } else if (IS_I915GM(dev)) {
312 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
313 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
314 I915_WRITE(INSTPM, val);
a7a6c498 315 POSTING_READ(INSTPM);
5209b1f4
ID		 316 } else {
317 return;
318 }
b445e3b0 319
5209b1f4
ID		 320 DRM_DEBUG_KMS("memory self-refresh is %s\n",
321 enable ? "enabled" : "disabled");
b445e3b0
ED		 322}
323
fc1ac8de 324
b445e3b0
ED		 325/*
326 * Latency for FIFO fetches is dependent on several factors:
327 * - memory configuration (speed, channels)
328 * - chipset
329 * - current MCH state
330 * It can be fairly high in some situations, so here we assume a fairly
331 * pessimal value. It's a tradeoff between extra memory fetches (if we
332 * set this value too high, the FIFO will fetch frequently to stay full)
333 * and power consumption (set it too low to save power and we might see
334 * FIFO underruns and display "flicker").
335 *
336 * A value of 5us seems to be a good balance; safe for very low end
337 * platforms but not overly aggressive on lower latency configs.
338 */
5aef6003 339static const int pessimal_latency_ns = 5000;
b445e3b0 340
b5004720
VS		 341#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
342 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
343
344static int vlv_get_fifo_size(struct drm_device *dev,
345 enum pipe pipe, int plane)
346{
347 struct drm_i915_private *dev_priv = dev->dev_private;
348 int sprite0_start, sprite1_start, size;
349
350 switch (pipe) {
351 uint32_t dsparb, dsparb2, dsparb3;
352 case PIPE_A:
353 dsparb = I915_READ(DSPARB);
354 dsparb2 = I915_READ(DSPARB2);
355 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
356 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
357 break;
358 case PIPE_B:
359 dsparb = I915_READ(DSPARB);
360 dsparb2 = I915_READ(DSPARB2);
361 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
362 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
363 break;
364 case PIPE_C:
365 dsparb2 = I915_READ(DSPARB2);
366 dsparb3 = I915_READ(DSPARB3);
367 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
368 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
369 break;
370 default:
371 return 0;
372 }
373
374 switch (plane) {
375 case 0:
376 size = sprite0_start;
377 break;
378 case 1:
379 size = sprite1_start - sprite0_start;
380 break;
381 case 2:
382 size = 512 - 1 - sprite1_start;
383 break;
384 default:
385 return 0;
386 }
387
388 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
389 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
390 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
391 size);
392
393 return size;
394}
395
1fa61106 396static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 397{
398 struct drm_i915_private *dev_priv = dev->dev_private;
399 uint32_t dsparb = I915_READ(DSPARB);
400 int size;
401
402 size = dsparb & 0x7f;
403 if (plane)
404 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
405
406 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
407 plane ? "B" : "A", size);
408
409 return size;
410}
411
feb56b93 412static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 413{
414 struct drm_i915_private *dev_priv = dev->dev_private;
415 uint32_t dsparb = I915_READ(DSPARB);
416 int size;
417
418 size = dsparb & 0x1ff;
419 if (plane)
420 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
421 size >>= 1; /* Convert to cachelines */
422
423 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
424 plane ? "B" : "A", size);
425
426 return size;
427}
428
1fa61106 429static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 430{
431 struct drm_i915_private *dev_priv = dev->dev_private;
432 uint32_t dsparb = I915_READ(DSPARB);
433 int size;
434
435 size = dsparb & 0x7f;
436 size >>= 2; /* Convert to cachelines */
437
438 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
439 plane ? "B" : "A",
440 size);
441
442 return size;
443}
444
b445e3b0
ED		 445/* Pineview has different values for various configs */
446static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 447 .fifo_size = PINEVIEW_DISPLAY_FIFO,
448 .max_wm = PINEVIEW_MAX_WM,
449 .default_wm = PINEVIEW_DFT_WM,
450 .guard_size = PINEVIEW_GUARD_WM,
451 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 452};
453static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 454 .fifo_size = PINEVIEW_DISPLAY_FIFO,
455 .max_wm = PINEVIEW_MAX_WM,
456 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
457 .guard_size = PINEVIEW_GUARD_WM,
458 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 459};
460static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 461 .fifo_size = PINEVIEW_CURSOR_FIFO,
462 .max_wm = PINEVIEW_CURSOR_MAX_WM,
463 .default_wm = PINEVIEW_CURSOR_DFT_WM,
464 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
465 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 466};
467static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 468 .fifo_size = PINEVIEW_CURSOR_FIFO,
469 .max_wm = PINEVIEW_CURSOR_MAX_WM,
470 .default_wm = PINEVIEW_CURSOR_DFT_WM,
471 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
472 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 473};
474static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 475 .fifo_size = G4X_FIFO_SIZE,
476 .max_wm = G4X_MAX_WM,
477 .default_wm = G4X_MAX_WM,
478 .guard_size = 2,
479 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 480};
481static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 482 .fifo_size = I965_CURSOR_FIFO,
483 .max_wm = I965_CURSOR_MAX_WM,
484 .default_wm = I965_CURSOR_DFT_WM,
485 .guard_size = 2,
486 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 487};
488static const struct intel_watermark_params valleyview_wm_info = {
e0f0273e
VS		 489 .fifo_size = VALLEYVIEW_FIFO_SIZE,
490 .max_wm = VALLEYVIEW_MAX_WM,
491 .default_wm = VALLEYVIEW_MAX_WM,
492 .guard_size = 2,
493 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 494};
495static const struct intel_watermark_params valleyview_cursor_wm_info = {
e0f0273e
VS		 496 .fifo_size = I965_CURSOR_FIFO,
497 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
498 .default_wm = I965_CURSOR_DFT_WM,
499 .guard_size = 2,
500 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 501};
502static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 503 .fifo_size = I965_CURSOR_FIFO,
504 .max_wm = I965_CURSOR_MAX_WM,
505 .default_wm = I965_CURSOR_DFT_WM,
506 .guard_size = 2,
507 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 508};
509static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 510 .fifo_size = I945_FIFO_SIZE,
511 .max_wm = I915_MAX_WM,
512 .default_wm = 1,
513 .guard_size = 2,
514 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 515};
516static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 517 .fifo_size = I915_FIFO_SIZE,
518 .max_wm = I915_MAX_WM,
519 .default_wm = 1,
520 .guard_size = 2,
521 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 522};
9d539105 523static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 524 .fifo_size = I855GM_FIFO_SIZE,
525 .max_wm = I915_MAX_WM,
526 .default_wm = 1,
527 .guard_size = 2,
528 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 529};
9d539105
VS		 530static const struct intel_watermark_params i830_bc_wm_info = {
531 .fifo_size = I855GM_FIFO_SIZE,
532 .max_wm = I915_MAX_WM/2,
533 .default_wm = 1,
534 .guard_size = 2,
535 .cacheline_size = I830_FIFO_LINE_SIZE,
536};
feb56b93 537static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 538 .fifo_size = I830_FIFO_SIZE,
539 .max_wm = I915_MAX_WM,
540 .default_wm = 1,
541 .guard_size = 2,
542 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 543};
544
b445e3b0
ED		 545/**
546 * intel_calculate_wm - calculate watermark level
547 * @clock_in_khz: pixel clock
548 * @wm: chip FIFO params
549 * @pixel_size: display pixel size
550 * @latency_ns: memory latency for the platform
551 *
552 * Calculate the watermark level (the level at which the display plane will
553 * start fetching from memory again). Each chip has a different display
554 * FIFO size and allocation, so the caller needs to figure that out and pass
555 * in the correct intel_watermark_params structure.
556 *
557 * As the pixel clock runs, the FIFO will be drained at a rate that depends
558 * on the pixel size. When it reaches the watermark level, it'll start
559 * fetching FIFO line sized based chunks from memory until the FIFO fills
560 * past the watermark point. If the FIFO drains completely, a FIFO underrun
561 * will occur, and a display engine hang could result.
562 */
563static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
564 const struct intel_watermark_params *wm,
565 int fifo_size,
566 int pixel_size,
567 unsigned long latency_ns)
568{
569 long entries_required, wm_size;
570
571 /*
572 * Note: we need to make sure we don't overflow for various clock &
573 * latency values.
574 * clocks go from a few thousand to several hundred thousand.
575 * latency is usually a few thousand
576 */
577 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
578 1000;
579 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
580
581 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
582
583 wm_size = fifo_size - (entries_required + wm->guard_size);
584
585 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
586
587 /* Don't promote wm_size to unsigned... */
588 if (wm_size > (long)wm->max_wm)
589 wm_size = wm->max_wm;
590 if (wm_size <= 0)
591 wm_size = wm->default_wm;
d6feb196
VS		 592
593 /*
594 * Bspec seems to indicate that the value shouldn't be lower than
595 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
596 * Lets go for 8 which is the burst size since certain platforms
597 * already use a hardcoded 8 (which is what the spec says should be
598 * done).
599 */
600 if (wm_size <= 8)
601 wm_size = 8;
602
b445e3b0
ED		 603 return wm_size;
604}
605
606static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
607{
608 struct drm_crtc *crtc, *enabled = NULL;
609
70e1e0ec 610 for_each_crtc(dev, crtc) {
3490ea5d 611 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 612 if (enabled)
613 return NULL;
614 enabled = crtc;
615 }
616 }
617
618 return enabled;
619}
620
46ba614c 621static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 622{
46ba614c 623 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 624 struct drm_i915_private *dev_priv = dev->dev_private;
625 struct drm_crtc *crtc;
626 const struct cxsr_latency *latency;
627 u32 reg;
628 unsigned long wm;
629
630 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
631 dev_priv->fsb_freq, dev_priv->mem_freq);
632 if (!latency) {
633 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 634 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 635 return;
636 }
637
638 crtc = single_enabled_crtc(dev);
639 if (crtc) {
7c5f93b0 640 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
59bea882 641 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
7c5f93b0 642 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 643
644 /* Display SR */
645 wm = intel_calculate_wm(clock, &pineview_display_wm,
646 pineview_display_wm.fifo_size,
647 pixel_size, latency->display_sr);
648 reg = I915_READ(DSPFW1);
649 reg &= ~DSPFW_SR_MASK;
f4998963 650 reg |= FW_WM(wm, SR);
b445e3b0
ED		 651 I915_WRITE(DSPFW1, reg);
652 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
653
654 /* cursor SR */
655 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
656 pineview_display_wm.fifo_size,
657 pixel_size, latency->cursor_sr);
658 reg = I915_READ(DSPFW3);
659 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 660 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 661 I915_WRITE(DSPFW3, reg);
662
663 /* Display HPLL off SR */
664 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
665 pineview_display_hplloff_wm.fifo_size,
666 pixel_size, latency->display_hpll_disable);
667 reg = I915_READ(DSPFW3);
668 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 669 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 670 I915_WRITE(DSPFW3, reg);
671
672 /* cursor HPLL off SR */
673 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
674 pineview_display_hplloff_wm.fifo_size,
675 pixel_size, latency->cursor_hpll_disable);
676 reg = I915_READ(DSPFW3);
677 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 678 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 679 I915_WRITE(DSPFW3, reg);
680 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
681
5209b1f4 682 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 683 } else {
5209b1f4 684 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 685 }
686}
687
688static bool g4x_compute_wm0(struct drm_device *dev,
689 int plane,
690 const struct intel_watermark_params *display,
691 int display_latency_ns,
692 const struct intel_watermark_params *cursor,
693 int cursor_latency_ns,
694 int *plane_wm,
695 int *cursor_wm)
696{
697 struct drm_crtc *crtc;
4fe8590a 698 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 699 int htotal, hdisplay, clock, pixel_size;
700 int line_time_us, line_count;
701 int entries, tlb_miss;
702
703 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 704 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 705 *cursor_wm = cursor->guard_size;
706 *plane_wm = display->guard_size;
707 return false;
708 }
709
6e3c9717 710 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 711 clock = adjusted_mode->crtc_clock;
fec8cba3 712 htotal = adjusted_mode->crtc_htotal;
6e3c9717 713 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 714 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 715
716 /* Use the small buffer method to calculate plane watermark */
717 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
718 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
719 if (tlb_miss > 0)
720 entries += tlb_miss;
721 entries = DIV_ROUND_UP(entries, display->cacheline_size);
722 *plane_wm = entries + display->guard_size;
723 if (*plane_wm > (int)display->max_wm)
724 *plane_wm = display->max_wm;
725
726 /* Use the large buffer method to calculate cursor watermark */
922044c9 727 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 728 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3dd512fb 729 entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
b445e3b0
ED		 730 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
731 if (tlb_miss > 0)
732 entries += tlb_miss;
733 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
734 *cursor_wm = entries + cursor->guard_size;
735 if (*cursor_wm > (int)cursor->max_wm)
736 *cursor_wm = (int)cursor->max_wm;
737
738 return true;
739}
740
741/*
742 * Check the wm result.
743 *
744 * If any calculated watermark values is larger than the maximum value that
745 * can be programmed into the associated watermark register, that watermark
746 * must be disabled.
747 */
748static bool g4x_check_srwm(struct drm_device *dev,
749 int display_wm, int cursor_wm,
750 const struct intel_watermark_params *display,
751 const struct intel_watermark_params *cursor)
752{
753 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
754 display_wm, cursor_wm);
755
756 if (display_wm > display->max_wm) {
757 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
758 display_wm, display->max_wm);
759 return false;
760 }
761
762 if (cursor_wm > cursor->max_wm) {
763 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
764 cursor_wm, cursor->max_wm);
765 return false;
766 }
767
768 if (!(display_wm || cursor_wm)) {
769 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
770 return false;
771 }
772
773 return true;
774}
775
776static bool g4x_compute_srwm(struct drm_device *dev,
777 int plane,
778 int latency_ns,
779 const struct intel_watermark_params *display,
780 const struct intel_watermark_params *cursor,
781 int *display_wm, int *cursor_wm)
782{
783 struct drm_crtc *crtc;
4fe8590a 784 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 785 int hdisplay, htotal, pixel_size, clock;
786 unsigned long line_time_us;
787 int line_count, line_size;
788 int small, large;
789 int entries;
790
791 if (!latency_ns) {
792 *display_wm = *cursor_wm = 0;
793 return false;
794 }
795
796 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 797 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 798 clock = adjusted_mode->crtc_clock;
fec8cba3 799 htotal = adjusted_mode->crtc_htotal;
6e3c9717 800 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 801 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0 802
922044c9 803 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 804 line_count = (latency_ns / line_time_us + 1000) / 1000;
805 line_size = hdisplay * pixel_size;
806
807 /* Use the minimum of the small and large buffer method for primary */
808 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
809 large = line_count * line_size;
810
811 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
812 *display_wm = entries + display->guard_size;
813
814 /* calculate the self-refresh watermark for display cursor */
3dd512fb 815 entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 816 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
817 *cursor_wm = entries + cursor->guard_size;
818
819 return g4x_check_srwm(dev,
820 *display_wm, *cursor_wm,
821 display, cursor);
822}
823
15665979
VS		 824#define FW_WM_VLV(value, plane) \
825 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
826
0018fda1
VS		 827static void vlv_write_wm_values(struct intel_crtc *crtc,
828 const struct vlv_wm_values *wm)
829{
830 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
831 enum pipe pipe = crtc->pipe;
832
833 I915_WRITE(VLV_DDL(pipe),
834 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
835 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
836 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
837 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
838
ae80152d 839 I915_WRITE(DSPFW1,
15665979
VS		 840 FW_WM(wm->sr.plane, SR) |
841 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
842 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
843 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 844 I915_WRITE(DSPFW2,
15665979
VS		 845 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
846 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
847 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 848 I915_WRITE(DSPFW3,
15665979 849 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 850
851 if (IS_CHERRYVIEW(dev_priv)) {
852 I915_WRITE(DSPFW7_CHV,
15665979
VS		 853 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
854 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 855 I915_WRITE(DSPFW8_CHV,
15665979
VS		 856 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
857 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 858 I915_WRITE(DSPFW9_CHV,
15665979
VS		 859 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
860 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 861 I915_WRITE(DSPHOWM,
15665979
VS		 862 FW_WM(wm->sr.plane >> 9, SR_HI) |
863 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
864 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
865 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
866 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
867 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
868 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
869 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
870 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
871 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 872 } else {
873 I915_WRITE(DSPFW7,
15665979
VS		 874 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
875 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 876 I915_WRITE(DSPHOWM,
15665979
VS		 877 FW_WM(wm->sr.plane >> 9, SR_HI) |
878 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
879 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
880 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
881 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
882 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
883 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 884 }
885
2cb389b7
VS		 886 /* zero (unused) WM1 watermarks */
887 I915_WRITE(DSPFW4, 0);
888 I915_WRITE(DSPFW5, 0);
889 I915_WRITE(DSPFW6, 0);
890 I915_WRITE(DSPHOWM1, 0);
891
ae80152d 892 POSTING_READ(DSPFW1);
0018fda1
VS		 893}
894
15665979
VS		 895#undef FW_WM_VLV
896
6eb1a681
VS		 897enum vlv_wm_level {
898 VLV_WM_LEVEL_PM2,
899 VLV_WM_LEVEL_PM5,
900 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 901};
902
262cd2e1
VS		 903/* latency must be in 0.1us units. */
904static unsigned int vlv_wm_method2(unsigned int pixel_rate,
905 unsigned int pipe_htotal,
906 unsigned int horiz_pixels,
907 unsigned int bytes_per_pixel,
908 unsigned int latency)
909{
910 unsigned int ret;
911
912 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
913 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
914 ret = DIV_ROUND_UP(ret, 64);
915
916 return ret;
917}
918
919static void vlv_setup_wm_latency(struct drm_device *dev)
920{
921 struct drm_i915_private *dev_priv = dev->dev_private;
922
923 /* all latencies in usec */
924 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
925
58590c14
VS		 926 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
927
262cd2e1
VS		 928 if (IS_CHERRYVIEW(dev_priv)) {
929 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
930 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 931
932 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 933 }
934}
935
936static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
937 struct intel_crtc *crtc,
938 const struct intel_plane_state *state,
939 int level)
940{
941 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
942 int clock, htotal, pixel_size, width, wm;
943
944 if (dev_priv->wm.pri_latency[level] == 0)
945 return USHRT_MAX;
946
947 if (!state->visible)
948 return 0;
949
950 pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
951 clock = crtc->config->base.adjusted_mode.crtc_clock;
952 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
953 width = crtc->config->pipe_src_w;
954 if (WARN_ON(htotal == 0))
955 htotal = 1;
956
957 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
958 /*
959 * FIXME the formula gives values that are
960 * too big for the cursor FIFO, and hence we
961 * would never be able to use cursors. For
962 * now just hardcode the watermark.
963 */
964 wm = 63;
965 } else {
966 wm = vlv_wm_method2(clock, htotal, width, pixel_size,
967 dev_priv->wm.pri_latency[level] * 10);
968 }
969
970 return min_t(int, wm, USHRT_MAX);
971}
972
54f1b6e1
VS		 973static void vlv_compute_fifo(struct intel_crtc *crtc)
974{
975 struct drm_device *dev = crtc->base.dev;
976 struct vlv_wm_state *wm_state = &crtc->wm_state;
977 struct intel_plane *plane;
978 unsigned int total_rate = 0;
979 const int fifo_size = 512 - 1;
980 int fifo_extra, fifo_left = fifo_size;
981
982 for_each_intel_plane_on_crtc(dev, crtc, plane) {
983 struct intel_plane_state *state =
984 to_intel_plane_state(plane->base.state);
985
986 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
987 continue;
988
989 if (state->visible) {
990 wm_state->num_active_planes++;
991 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
992 }
993 }
994
995 for_each_intel_plane_on_crtc(dev, crtc, plane) {
996 struct intel_plane_state *state =
997 to_intel_plane_state(plane->base.state);
998 unsigned int rate;
999
1000 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1001 plane->wm.fifo_size = 63;
1002 continue;
1003 }
1004
1005 if (!state->visible) {
1006 plane->wm.fifo_size = 0;
1007 continue;
1008 }
1009
1010 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1011 plane->wm.fifo_size = fifo_size * rate / total_rate;
1012 fifo_left -= plane->wm.fifo_size;
1013 }
1014
1015 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1016
1017 /* spread the remainder evenly */
1018 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1019 int plane_extra;
1020
1021 if (fifo_left == 0)
1022 break;
1023
1024 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1025 continue;
1026
1027 /* give it all to the first plane if none are active */
1028 if (plane->wm.fifo_size == 0 &&
1029 wm_state->num_active_planes)
1030 continue;
1031
1032 plane_extra = min(fifo_extra, fifo_left);
1033 plane->wm.fifo_size += plane_extra;
1034 fifo_left -= plane_extra;
1035 }
1036
1037 WARN_ON(fifo_left != 0);
1038}
1039
262cd2e1
VS		 1040static void vlv_invert_wms(struct intel_crtc *crtc)
1041{
1042 struct vlv_wm_state *wm_state = &crtc->wm_state;
1043 int level;
1044
1045 for (level = 0; level < wm_state->num_levels; level++) {
1046 struct drm_device *dev = crtc->base.dev;
1047 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1048 struct intel_plane *plane;
1049
1050 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1051 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1052
1053 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1054 switch (plane->base.type) {
1055 int sprite;
1056 case DRM_PLANE_TYPE_CURSOR:
1057 wm_state->wm[level].cursor = plane->wm.fifo_size -
1058 wm_state->wm[level].cursor;
1059 break;
1060 case DRM_PLANE_TYPE_PRIMARY:
1061 wm_state->wm[level].primary = plane->wm.fifo_size -
1062 wm_state->wm[level].primary;
1063 break;
1064 case DRM_PLANE_TYPE_OVERLAY:
1065 sprite = plane->plane;
1066 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1067 wm_state->wm[level].sprite[sprite];
1068 break;
1069 }
1070 }
1071 }
1072}
1073
26e1fe4f 1074static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1075{
1076 struct drm_device *dev = crtc->base.dev;
1077 struct vlv_wm_state *wm_state = &crtc->wm_state;
1078 struct intel_plane *plane;
1079 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1080 int level;
1081
1082 memset(wm_state, 0, sizeof(*wm_state));
1083
852eb00d 1084 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1085 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1086
1087 wm_state->num_active_planes = 0;
262cd2e1 1088
54f1b6e1 1089 vlv_compute_fifo(crtc);
262cd2e1
VS		 1090
1091 if (wm_state->num_active_planes != 1)
1092 wm_state->cxsr = false;
1093
1094 if (wm_state->cxsr) {
1095 for (level = 0; level < wm_state->num_levels; level++) {
1096 wm_state->sr[level].plane = sr_fifo_size;
1097 wm_state->sr[level].cursor = 63;
1098 }
1099 }
1100
1101 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1102 struct intel_plane_state *state =
1103 to_intel_plane_state(plane->base.state);
1104
1105 if (!state->visible)
1106 continue;
1107
1108 /* normal watermarks */
1109 for (level = 0; level < wm_state->num_levels; level++) {
1110 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1111 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1112
1113 /* hack */
1114 if (WARN_ON(level == 0 && wm > max_wm))
1115 wm = max_wm;
1116
1117 if (wm > plane->wm.fifo_size)
1118 break;
1119
1120 switch (plane->base.type) {
1121 int sprite;
1122 case DRM_PLANE_TYPE_CURSOR:
1123 wm_state->wm[level].cursor = wm;
1124 break;
1125 case DRM_PLANE_TYPE_PRIMARY:
1126 wm_state->wm[level].primary = wm;
1127 break;
1128 case DRM_PLANE_TYPE_OVERLAY:
1129 sprite = plane->plane;
1130 wm_state->wm[level].sprite[sprite] = wm;
1131 break;
1132 }
1133 }
1134
1135 wm_state->num_levels = level;
1136
1137 if (!wm_state->cxsr)
1138 continue;
1139
1140 /* maxfifo watermarks */
1141 switch (plane->base.type) {
1142 int sprite, level;
1143 case DRM_PLANE_TYPE_CURSOR:
1144 for (level = 0; level < wm_state->num_levels; level++)
1145 wm_state->sr[level].cursor =
5a37ed0a 1146 wm_state->wm[level].cursor;
262cd2e1
VS		 1147 break;
1148 case DRM_PLANE_TYPE_PRIMARY:
1149 for (level = 0; level < wm_state->num_levels; level++)
1150 wm_state->sr[level].plane =
1151 min(wm_state->sr[level].plane,
1152 wm_state->wm[level].primary);
1153 break;
1154 case DRM_PLANE_TYPE_OVERLAY:
1155 sprite = plane->plane;
1156 for (level = 0; level < wm_state->num_levels; level++)
1157 wm_state->sr[level].plane =
1158 min(wm_state->sr[level].plane,
1159 wm_state->wm[level].sprite[sprite]);
1160 break;
1161 }
1162 }
1163
1164 /* clear any (partially) filled invalid levels */
58590c14 1165 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1166 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1167 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1168 }
1169
1170 vlv_invert_wms(crtc);
1171}
1172
54f1b6e1
VS		 1173#define VLV_FIFO(plane, value) \
1174 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1175
1176static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1177{
1178 struct drm_device *dev = crtc->base.dev;
1179 struct drm_i915_private *dev_priv = to_i915(dev);
1180 struct intel_plane *plane;
1181 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1182
1183 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1184 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1185 WARN_ON(plane->wm.fifo_size != 63);
1186 continue;
1187 }
1188
1189 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1190 sprite0_start = plane->wm.fifo_size;
1191 else if (plane->plane == 0)
1192 sprite1_start = sprite0_start + plane->wm.fifo_size;
1193 else
1194 fifo_size = sprite1_start + plane->wm.fifo_size;
1195 }
1196
1197 WARN_ON(fifo_size != 512 - 1);
1198
1199 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1200 pipe_name(crtc->pipe), sprite0_start,
1201 sprite1_start, fifo_size);
1202
1203 switch (crtc->pipe) {
1204 uint32_t dsparb, dsparb2, dsparb3;
1205 case PIPE_A:
1206 dsparb = I915_READ(DSPARB);
1207 dsparb2 = I915_READ(DSPARB2);
1208
1209 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1210 VLV_FIFO(SPRITEB, 0xff));
1211 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1212 VLV_FIFO(SPRITEB, sprite1_start));
1213
1214 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1215 VLV_FIFO(SPRITEB_HI, 0x1));
1216 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1217 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1218
1219 I915_WRITE(DSPARB, dsparb);
1220 I915_WRITE(DSPARB2, dsparb2);
1221 break;
1222 case PIPE_B:
1223 dsparb = I915_READ(DSPARB);
1224 dsparb2 = I915_READ(DSPARB2);
1225
1226 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1227 VLV_FIFO(SPRITED, 0xff));
1228 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1229 VLV_FIFO(SPRITED, sprite1_start));
1230
1231 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1232 VLV_FIFO(SPRITED_HI, 0xff));
1233 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1234 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1235
1236 I915_WRITE(DSPARB, dsparb);
1237 I915_WRITE(DSPARB2, dsparb2);
1238 break;
1239 case PIPE_C:
1240 dsparb3 = I915_READ(DSPARB3);
1241 dsparb2 = I915_READ(DSPARB2);
1242
1243 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1244 VLV_FIFO(SPRITEF, 0xff));
1245 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1246 VLV_FIFO(SPRITEF, sprite1_start));
1247
1248 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1249 VLV_FIFO(SPRITEF_HI, 0xff));
1250 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1251 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1252
1253 I915_WRITE(DSPARB3, dsparb3);
1254 I915_WRITE(DSPARB2, dsparb2);
1255 break;
1256 default:
1257 break;
1258 }
1259}
1260
1261#undef VLV_FIFO
1262
262cd2e1
VS		 1263static void vlv_merge_wm(struct drm_device *dev,
1264 struct vlv_wm_values *wm)
1265{
1266 struct intel_crtc *crtc;
1267 int num_active_crtcs = 0;
1268
58590c14 1269 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1270 wm->cxsr = true;
1271
1272 for_each_intel_crtc(dev, crtc) {
1273 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1274
1275 if (!crtc->active)
1276 continue;
1277
1278 if (!wm_state->cxsr)
1279 wm->cxsr = false;
1280
1281 num_active_crtcs++;
1282 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1283 }
1284
1285 if (num_active_crtcs != 1)
1286 wm->cxsr = false;
1287
6f9c784b
VS		 1288 if (num_active_crtcs > 1)
1289 wm->level = VLV_WM_LEVEL_PM2;
1290
262cd2e1
VS		 1291 for_each_intel_crtc(dev, crtc) {
1292 struct vlv_wm_state *wm_state = &crtc->wm_state;
1293 enum pipe pipe = crtc->pipe;
1294
1295 if (!crtc->active)
1296 continue;
1297
1298 wm->pipe[pipe] = wm_state->wm[wm->level];
1299 if (wm->cxsr)
1300 wm->sr = wm_state->sr[wm->level];
1301
1302 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1303 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1304 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1305 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1306 }
1307}
1308
1309static void vlv_update_wm(struct drm_crtc *crtc)
1310{
1311 struct drm_device *dev = crtc->dev;
1312 struct drm_i915_private *dev_priv = dev->dev_private;
1313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1314 enum pipe pipe = intel_crtc->pipe;
1315 struct vlv_wm_values wm = {};
1316
26e1fe4f 1317 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1318 vlv_merge_wm(dev, &wm);
1319
54f1b6e1
VS		 1320 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1321 /* FIXME should be part of crtc atomic commit */
1322 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1323 return;
54f1b6e1 1324 }
262cd2e1
VS		 1325
1326 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1327 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1328 chv_set_memory_dvfs(dev_priv, false);
1329
1330 if (wm.level < VLV_WM_LEVEL_PM5 &&
1331 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1332 chv_set_memory_pm5(dev_priv, false);
1333
852eb00d 1334 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1335 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1336
54f1b6e1
VS		 1337 /* FIXME should be part of crtc atomic commit */
1338 vlv_pipe_set_fifo_size(intel_crtc);
1339
262cd2e1
VS		 1340 vlv_write_wm_values(intel_crtc, &wm);
1341
1342 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1343 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1344 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1345 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1346 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1347
852eb00d 1348 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1349 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1350
1351 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1352 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1353 chv_set_memory_pm5(dev_priv, true);
1354
1355 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1356 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1357 chv_set_memory_dvfs(dev_priv, true);
1358
1359 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1360}
1361
ae80152d
VS		 1362#define single_plane_enabled(mask) is_power_of_2(mask)
1363
46ba614c 1364static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1365{
46ba614c 1366 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1367 static const int sr_latency_ns = 12000;
1368 struct drm_i915_private *dev_priv = dev->dev_private;
1369 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1370 int plane_sr, cursor_sr;
1371 unsigned int enabled = 0;
9858425c 1372 bool cxsr_enabled;
b445e3b0 1373
51cea1f4 1374 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1375 &g4x_wm_info, pessimal_latency_ns,
1376 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1377 &planea_wm, &cursora_wm))
51cea1f4 1378 enabled |= 1 << PIPE_A;
b445e3b0 1379
51cea1f4 1380 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1381 &g4x_wm_info, pessimal_latency_ns,
1382 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1383 &planeb_wm, &cursorb_wm))
51cea1f4 1384 enabled |= 1 << PIPE_B;
b445e3b0 1385
b445e3b0
ED		 1386 if (single_plane_enabled(enabled) &&
1387 g4x_compute_srwm(dev, ffs(enabled) - 1,
1388 sr_latency_ns,
1389 &g4x_wm_info,
1390 &g4x_cursor_wm_info,
52bd02d8 1391 &plane_sr, &cursor_sr)) {
9858425c 1392 cxsr_enabled = true;
52bd02d8 1393 } else {
9858425c 1394 cxsr_enabled = false;
5209b1f4 1395 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1396 plane_sr = cursor_sr = 0;
1397 }
b445e3b0 1398
a5043453
VS		 1399 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1400 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1401 planea_wm, cursora_wm,
1402 planeb_wm, cursorb_wm,
1403 plane_sr, cursor_sr);
1404
1405 I915_WRITE(DSPFW1,
f4998963
VS		 1406 FW_WM(plane_sr, SR) |
1407 FW_WM(cursorb_wm, CURSORB) |
1408 FW_WM(planeb_wm, PLANEB) |
1409 FW_WM(planea_wm, PLANEA));
b445e3b0 1410 I915_WRITE(DSPFW2,
8c919b28 1411 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1412 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1413 /* HPLL off in SR has some issues on G4x... disable it */
1414 I915_WRITE(DSPFW3,
8c919b28 1415 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1416 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1417
1418 if (cxsr_enabled)
1419 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1420}
1421
46ba614c 1422static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1423{
46ba614c 1424 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1425 struct drm_i915_private *dev_priv = dev->dev_private;
1426 struct drm_crtc *crtc;
1427 int srwm = 1;
1428 int cursor_sr = 16;
9858425c 1429 bool cxsr_enabled;
b445e3b0
ED		 1430
1431 /* Calc sr entries for one plane configs */
1432 crtc = single_enabled_crtc(dev);
1433 if (crtc) {
1434 /* self-refresh has much higher latency */
1435 static const int sr_latency_ns = 12000;
124abe07 1436 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1437 int clock = adjusted_mode->crtc_clock;
fec8cba3 1438 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1439 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 1440 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1441 unsigned long line_time_us;
1442 int entries;
1443
922044c9 1444 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1445
1446 /* Use ns/us then divide to preserve precision */
1447 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1448 pixel_size * hdisplay;
1449 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1450 srwm = I965_FIFO_SIZE - entries;
1451 if (srwm < 0)
1452 srwm = 1;
1453 srwm &= 0x1ff;
1454 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1455 entries, srwm);
1456
1457 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3dd512fb 1458 pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1459 entries = DIV_ROUND_UP(entries,
1460 i965_cursor_wm_info.cacheline_size);
1461 cursor_sr = i965_cursor_wm_info.fifo_size -
1462 (entries + i965_cursor_wm_info.guard_size);
1463
1464 if (cursor_sr > i965_cursor_wm_info.max_wm)
1465 cursor_sr = i965_cursor_wm_info.max_wm;
1466
1467 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1468 "cursor %d\n", srwm, cursor_sr);
1469
9858425c 1470 cxsr_enabled = true;
b445e3b0 1471 } else {
9858425c 1472 cxsr_enabled = false;
b445e3b0 1473 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1474 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1475 }
1476
1477 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1478 srwm);
1479
1480 /* 965 has limitations... */
f4998963
VS		 1481 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1482 FW_WM(8, CURSORB) |
1483 FW_WM(8, PLANEB) |
1484 FW_WM(8, PLANEA));
1485 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1486 FW_WM(8, PLANEC_OLD));
b445e3b0 1487 /* update cursor SR watermark */
f4998963 1488 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1489
1490 if (cxsr_enabled)
1491 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1492}
1493
f4998963
VS		 1494#undef FW_WM
1495
46ba614c 1496static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1497{
46ba614c 1498 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1499 struct drm_i915_private *dev_priv = dev->dev_private;
1500 const struct intel_watermark_params *wm_info;
1501 uint32_t fwater_lo;
1502 uint32_t fwater_hi;
1503 int cwm, srwm = 1;
1504 int fifo_size;
1505 int planea_wm, planeb_wm;
1506 struct drm_crtc *crtc, *enabled = NULL;
1507
1508 if (IS_I945GM(dev))
1509 wm_info = &i945_wm_info;
1510 else if (!IS_GEN2(dev))
1511 wm_info = &i915_wm_info;
1512 else
9d539105 1513 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1514
1515 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1516 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1517 if (intel_crtc_active(crtc)) {
241bfc38 1518 const struct drm_display_mode *adjusted_mode;
59bea882 1519 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1520 if (IS_GEN2(dev))
1521 cpp = 4;
1522
6e3c9717 1523 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1524 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1525 wm_info, fifo_size, cpp,
5aef6003 1526 pessimal_latency_ns);
b445e3b0 1527 enabled = crtc;
9d539105 1528 } else {
b445e3b0 1529 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1530 if (planea_wm > (long)wm_info->max_wm)
1531 planea_wm = wm_info->max_wm;
1532 }
1533
1534 if (IS_GEN2(dev))
1535 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1536
1537 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1538 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1539 if (intel_crtc_active(crtc)) {
241bfc38 1540 const struct drm_display_mode *adjusted_mode;
59bea882 1541 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1542 if (IS_GEN2(dev))
1543 cpp = 4;
1544
6e3c9717 1545 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1546 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1547 wm_info, fifo_size, cpp,
5aef6003 1548 pessimal_latency_ns);
b445e3b0
ED		 1549 if (enabled == NULL)
1550 enabled = crtc;
1551 else
1552 enabled = NULL;
9d539105 1553 } else {
b445e3b0 1554 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1555 if (planeb_wm > (long)wm_info->max_wm)
1556 planeb_wm = wm_info->max_wm;
1557 }
b445e3b0
ED		 1558
1559 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1560
2ab1bc9d 1561 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1562 struct drm_i915_gem_object *obj;
2ab1bc9d 1563
59bea882 1564 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1565
1566 /* self-refresh seems busted with untiled */
2ff8fde1 1567 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1568 enabled = NULL;
1569 }
1570
b445e3b0
ED		 1571 /*
1572 * Overlay gets an aggressive default since video jitter is bad.
1573 */
1574 cwm = 2;
1575
1576 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1577 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1578
1579 /* Calc sr entries for one plane configs */
1580 if (HAS_FW_BLC(dev) && enabled) {
1581 /* self-refresh has much higher latency */
1582 static const int sr_latency_ns = 6000;
124abe07 1583 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1584 int clock = adjusted_mode->crtc_clock;
fec8cba3 1585 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1586 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
59bea882 1587 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1588 unsigned long line_time_us;
1589 int entries;
1590
922044c9 1591 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1592
1593 /* Use ns/us then divide to preserve precision */
1594 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1595 pixel_size * hdisplay;
1596 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1597 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1598 srwm = wm_info->fifo_size - entries;
1599 if (srwm < 0)
1600 srwm = 1;
1601
1602 if (IS_I945G(dev) || IS_I945GM(dev))
1603 I915_WRITE(FW_BLC_SELF,
1604 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1605 else if (IS_I915GM(dev))
1606 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1607 }
1608
1609 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1610 planea_wm, planeb_wm, cwm, srwm);
1611
1612 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1613 fwater_hi = (cwm & 0x1f);
1614
1615 /* Set request length to 8 cachelines per fetch */
1616 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1617 fwater_hi = fwater_hi | (1 << 8);
1618
1619 I915_WRITE(FW_BLC, fwater_lo);
1620 I915_WRITE(FW_BLC2, fwater_hi);
1621
5209b1f4
ID		 1622 if (enabled)
1623 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1624}
1625
feb56b93 1626static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1627{
46ba614c 1628 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1629 struct drm_i915_private *dev_priv = dev->dev_private;
1630 struct drm_crtc *crtc;
241bfc38 1631 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1632 uint32_t fwater_lo;
1633 int planea_wm;
1634
1635 crtc = single_enabled_crtc(dev);
1636 if (crtc == NULL)
1637 return;
1638
6e3c9717 1639 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1640 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1641 &i845_wm_info,
b445e3b0 1642 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1643 4, pessimal_latency_ns);
b445e3b0
ED		 1644 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1645 fwater_lo |= (3<<8) | planea_wm;
1646
1647 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1648
1649 I915_WRITE(FW_BLC, fwater_lo);
1650}
1651
8cfb3407 1652uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1653{
fd4daa9c 1654 uint32_t pixel_rate;
801bcfff 1655
8cfb3407 1656 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1657
1658 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1659 * adjust the pixel_rate here. */
1660
8cfb3407 1661 if (pipe_config->pch_pfit.enabled) {
801bcfff 1662 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1663 uint32_t pfit_size = pipe_config->pch_pfit.size;
1664
1665 pipe_w = pipe_config->pipe_src_w;
1666 pipe_h = pipe_config->pipe_src_h;
801bcfff 1667
801bcfff
PZ		 1668 pfit_w = (pfit_size >> 16) & 0xFFFF;
1669 pfit_h = pfit_size & 0xFFFF;
1670 if (pipe_w < pfit_w)
1671 pipe_w = pfit_w;
1672 if (pipe_h < pfit_h)
1673 pipe_h = pfit_h;
1674
15126882
MR		 1675 if (WARN_ON(!pfit_w || !pfit_h))
1676 return pixel_rate;
1677
801bcfff
PZ		 1678 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1679 pfit_w * pfit_h);
1680 }
1681
1682 return pixel_rate;
1683}
1684
37126462 1685/* latency must be in 0.1us units. */
23297044 1686static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1687 uint32_t latency)
1688{
1689 uint64_t ret;
1690
3312ba65
VS		 1691 if (WARN(latency == 0, "Latency value missing\n"))
1692 return UINT_MAX;
1693
801bcfff
PZ		 1694 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1695 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1696
1697 return ret;
1698}
1699
37126462 1700/* latency must be in 0.1us units. */
23297044 1701static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1702 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1703 uint32_t latency)
1704{
1705 uint32_t ret;
1706
3312ba65
VS		 1707 if (WARN(latency == 0, "Latency value missing\n"))
1708 return UINT_MAX;
15126882
MR		 1709 if (WARN_ON(!pipe_htotal))
1710 return UINT_MAX;
3312ba65 1711
801bcfff
PZ		 1712 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1713 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1714 ret = DIV_ROUND_UP(ret, 64) + 2;
1715 return ret;
1716}
1717
23297044 1718static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1719 uint8_t bytes_per_pixel)
1720{
15126882
MR		 1721 /*
1722 * Neither of these should be possible since this function shouldn't be
1723 * called if the CRTC is off or the plane is invisible. But let's be
1724 * extra paranoid to avoid a potential divide-by-zero if we screw up
1725 * elsewhere in the driver.
1726 */
1727 if (WARN_ON(!bytes_per_pixel))
1728 return 0;
1729 if (WARN_ON(!horiz_pixels))
1730 return 0;
1731
cca32e9a
PZ		 1732 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1733}
1734
820c1980 1735struct ilk_wm_maximums {
cca32e9a
PZ		 1736 uint16_t pri;
1737 uint16_t spr;
1738 uint16_t cur;
1739 uint16_t fbc;
1740};
1741
37126462
VS		 1742/*
1743 * For both WM_PIPE and WM_LP.
1744 * mem_value must be in 0.1us units.
1745 */
7221fc33 1746static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1747 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1748 uint32_t mem_value,
1749 bool is_lp)
801bcfff 1750{
43d59eda 1751 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
cca32e9a
PZ		 1752 uint32_t method1, method2;
1753
7221fc33 1754 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1755 return 0;
1756
7221fc33 1757 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
cca32e9a
PZ		 1758
1759 if (!is_lp)
1760 return method1;
1761
7221fc33
MR		 1762 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1763 cstate->base.adjusted_mode.crtc_htotal,
43d59eda
MR		 1764 drm_rect_width(&pstate->dst),
1765 bpp,
cca32e9a
PZ		 1766 mem_value);
1767
1768 return min(method1, method2);
801bcfff
PZ		 1769}
1770
37126462
VS		 1771/*
1772 * For both WM_PIPE and WM_LP.
1773 * mem_value must be in 0.1us units.
1774 */
7221fc33 1775static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1776 const struct intel_plane_state *pstate,
801bcfff
PZ		 1777 uint32_t mem_value)
1778{
43d59eda 1779 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
801bcfff
PZ		 1780 uint32_t method1, method2;
1781
7221fc33 1782 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1783 return 0;
1784
7221fc33
MR		 1785 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
1786 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1787 cstate->base.adjusted_mode.crtc_htotal,
43d59eda
MR		 1788 drm_rect_width(&pstate->dst),
1789 bpp,
801bcfff
PZ		 1790 mem_value);
1791 return min(method1, method2);
1792}
1793
37126462
VS		 1794/*
1795 * For both WM_PIPE and WM_LP.
1796 * mem_value must be in 0.1us units.
1797 */
7221fc33 1798static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1799 const struct intel_plane_state *pstate,
801bcfff
PZ		 1800 uint32_t mem_value)
1801{
43d59eda
MR		 1802 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1803
7221fc33 1804 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1805 return 0;
1806
7221fc33
MR		 1807 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1808 cstate->base.adjusted_mode.crtc_htotal,
43d59eda
MR		 1809 drm_rect_width(&pstate->dst),
1810 bpp,
801bcfff
PZ		 1811 mem_value);
1812}
1813
cca32e9a 1814/* Only for WM_LP. */
7221fc33 1815static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1816 const struct intel_plane_state *pstate,
1fda9882 1817 uint32_t pri_val)
cca32e9a 1818{
43d59eda
MR		 1819 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1820
7221fc33 1821 if (!cstate->base.active || !pstate->visible)
cca32e9a
PZ		 1822 return 0;
1823
43d59eda 1824 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp);
cca32e9a
PZ		 1825}
1826
158ae64f
VS		 1827static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1828{
416f4727
VS		 1829 if (INTEL_INFO(dev)->gen >= 8)
1830 return 3072;
1831 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1832 return 768;
1833 else
1834 return 512;
1835}
1836
4e975081
VS		 1837static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1838 int level, bool is_sprite)
1839{
1840 if (INTEL_INFO(dev)->gen >= 8)
1841 /* BDW primary/sprite plane watermarks */
1842 return level == 0 ? 255 : 2047;
1843 else if (INTEL_INFO(dev)->gen >= 7)
1844 /* IVB/HSW primary/sprite plane watermarks */
1845 return level == 0 ? 127 : 1023;
1846 else if (!is_sprite)
1847 /* ILK/SNB primary plane watermarks */
1848 return level == 0 ? 127 : 511;
1849 else
1850 /* ILK/SNB sprite plane watermarks */
1851 return level == 0 ? 63 : 255;
1852}
1853
1854static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1855 int level)
1856{
1857 if (INTEL_INFO(dev)->gen >= 7)
1858 return level == 0 ? 63 : 255;
1859 else
1860 return level == 0 ? 31 : 63;
1861}
1862
1863static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1864{
1865 if (INTEL_INFO(dev)->gen >= 8)
1866 return 31;
1867 else
1868 return 15;
1869}
1870
158ae64f
VS		 1871/* Calculate the maximum primary/sprite plane watermark */
1872static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1873 int level,
240264f4 1874 const struct intel_wm_config *config,
158ae64f
VS		 1875 enum intel_ddb_partitioning ddb_partitioning,
1876 bool is_sprite)
1877{
1878 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1879
1880 /* if sprites aren't enabled, sprites get nothing */
240264f4 1881 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1882 return 0;
1883
1884 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1885 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1886 fifo_size /= INTEL_INFO(dev)->num_pipes;
1887
1888 /*
1889 * For some reason the non self refresh
1890 * FIFO size is only half of the self
1891 * refresh FIFO size on ILK/SNB.
1892 */
1893 if (INTEL_INFO(dev)->gen <= 6)
1894 fifo_size /= 2;
1895 }
1896
240264f4 1897 if (config->sprites_enabled) {
158ae64f
VS		 1898 /* level 0 is always calculated with 1:1 split */
1899 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1900 if (is_sprite)
1901 fifo_size *= 5;
1902 fifo_size /= 6;
1903 } else {
1904 fifo_size /= 2;
1905 }
1906 }
1907
1908 /* clamp to max that the registers can hold */
4e975081 1909 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1910}
1911
1912/* Calculate the maximum cursor plane watermark */
1913static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1914 int level,
1915 const struct intel_wm_config *config)
158ae64f
VS		 1916{
1917 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1918 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1919 return 64;
1920
1921 /* otherwise just report max that registers can hold */
4e975081 1922 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1923}
1924
d34ff9c6 1925static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1926 int level,
1927 const struct intel_wm_config *config,
1928 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1929 struct ilk_wm_maximums *max)
158ae64f 1930{
240264f4
VS		 1931 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1932 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1933 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1934 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1935}
1936
a3cb4048
VS		 1937static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1938 int level,
1939 struct ilk_wm_maximums *max)
1940{
1941 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1942 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1943 max->cur = ilk_cursor_wm_reg_max(dev, level);
1944 max->fbc = ilk_fbc_wm_reg_max(dev);
1945}
1946
d9395655 1947static bool ilk_validate_wm_level(int level,
820c1980 1948 const struct ilk_wm_maximums *max,
d9395655 1949 struct intel_wm_level *result)
a9786a11
VS		 1950{
1951 bool ret;
1952
1953 /* already determined to be invalid? */
1954 if (!result->enable)
1955 return false;
1956
1957 result->enable = result->pri_val <= max->pri &&
1958 result->spr_val <= max->spr &&
1959 result->cur_val <= max->cur;
1960
1961 ret = result->enable;
1962
1963 /*
1964 * HACK until we can pre-compute everything,
1965 * and thus fail gracefully if LP0 watermarks
1966 * are exceeded...
1967 */
1968 if (level == 0 && !result->enable) {
1969 if (result->pri_val > max->pri)
1970 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1971 level, result->pri_val, max->pri);
1972 if (result->spr_val > max->spr)
1973 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1974 level, result->spr_val, max->spr);
1975 if (result->cur_val > max->cur)
1976 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1977 level, result->cur_val, max->cur);
1978
1979 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1980 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1981 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1982 result->enable = true;
1983 }
1984
a9786a11
VS		 1985 return ret;
1986}
1987
d34ff9c6 1988static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 1989 const struct intel_crtc *intel_crtc,
6f5ddd17 1990 int level,
7221fc33 1991 struct intel_crtc_state *cstate,
86c8bbbe
MR		 1992 struct intel_plane_state *pristate,
1993 struct intel_plane_state *sprstate,
1994 struct intel_plane_state *curstate,
1fd527cc 1995 struct intel_wm_level *result)
6f5ddd17
VS		 1996{
1997 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1998 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1999 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2000
2001 /* WM1+ latency values stored in 0.5us units */
2002 if (level > 0) {
2003 pri_latency *= 5;
2004 spr_latency *= 5;
2005 cur_latency *= 5;
2006 }
2007
86c8bbbe
MR		 2008 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2009 pri_latency, level);
2010 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2011 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2012 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
6f5ddd17
VS		 2013 result->enable = true;
2014}
2015
801bcfff 2016static uint32_t
ee91a159
MR		 2017hsw_compute_linetime_wm(struct drm_device *dev,
2018 struct intel_crtc_state *cstate)
1f8eeabf
ED		 2019{
2020 struct drm_i915_private *dev_priv = dev->dev_private;
ee91a159
MR		 2021 const struct drm_display_mode *adjusted_mode =
2022 &cstate->base.adjusted_mode;
85a02deb 2023 u32 linetime, ips_linetime;
1f8eeabf 2024
ee91a159
MR		 2025 if (!cstate->base.active)
2026 return 0;
2027 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2028 return 0;
2029 if (WARN_ON(dev_priv->cdclk_freq == 0))
801bcfff 2030 return 0;
1011d8c4 2031
1f8eeabf
ED		 2032 /* The WM are computed with base on how long it takes to fill a single
2033 * row at the given clock rate, multiplied by 8.
2034 * */
124abe07
VS		 2035 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2036 adjusted_mode->crtc_clock);
2037 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
05024da3 2038 dev_priv->cdclk_freq);
1f8eeabf 2039
801bcfff
PZ		 2040 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2041 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2042}
2043
2af30a5c 2044static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS		 2045{
2046 struct drm_i915_private *dev_priv = dev->dev_private;
2047
2af30a5c
PB		 2048 if (IS_GEN9(dev)) {
2049 uint32_t val;
4f947386 2050 int ret, i;
367294be 2051 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2052
2053 /* read the first set of memory latencies[0:3] */
2054 val = 0; /* data0 to be programmed to 0 for first set */
2055 mutex_lock(&dev_priv->rps.hw_lock);
2056 ret = sandybridge_pcode_read(dev_priv,
2057 GEN9_PCODE_READ_MEM_LATENCY,
2058 &val);
2059 mutex_unlock(&dev_priv->rps.hw_lock);
2060
2061 if (ret) {
2062 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2063 return;
2064 }
2065
2066 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2067 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2068 GEN9_MEM_LATENCY_LEVEL_MASK;
2069 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2070 GEN9_MEM_LATENCY_LEVEL_MASK;
2071 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2072 GEN9_MEM_LATENCY_LEVEL_MASK;
2073
2074 /* read the second set of memory latencies[4:7] */
2075 val = 1; /* data0 to be programmed to 1 for second set */
2076 mutex_lock(&dev_priv->rps.hw_lock);
2077 ret = sandybridge_pcode_read(dev_priv,
2078 GEN9_PCODE_READ_MEM_LATENCY,
2079 &val);
2080 mutex_unlock(&dev_priv->rps.hw_lock);
2081 if (ret) {
2082 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2083 return;
2084 }
2085
2086 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2087 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2088 GEN9_MEM_LATENCY_LEVEL_MASK;
2089 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2090 GEN9_MEM_LATENCY_LEVEL_MASK;
2091 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2092 GEN9_MEM_LATENCY_LEVEL_MASK;
2093
367294be 2094 /*
6f97235b
DL		 2095 * WaWmMemoryReadLatency:skl
2096 *
367294be
VK		 2097 * punit doesn't take into account the read latency so we need
2098 * to add 2us to the various latency levels we retrieve from
2099 * the punit.
2100 * - W0 is a bit special in that it's the only level that
2101 * can't be disabled if we want to have display working, so
2102 * we always add 2us there.
2103 * - For levels >=1, punit returns 0us latency when they are
2104 * disabled, so we respect that and don't add 2us then
4f947386
VK		 2105 *
2106 * Additionally, if a level n (n > 1) has a 0us latency, all
2107 * levels m (m >= n) need to be disabled. We make sure to
2108 * sanitize the values out of the punit to satisfy this
2109 * requirement.
367294be
VK		 2110 */
2111 wm[0] += 2;
2112 for (level = 1; level <= max_level; level++)
2113 if (wm[level] != 0)
2114 wm[level] += 2;
4f947386
VK		 2115 else {
2116 for (i = level + 1; i <= max_level; i++)
2117 wm[i] = 0;
367294be 2118
4f947386
VK		 2119 break;
2120 }
2af30a5c 2121 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2122 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2123
2124 wm[0] = (sskpd >> 56) & 0xFF;
2125 if (wm[0] == 0)
2126 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2127 wm[1] = (sskpd >> 4) & 0xFF;
2128 wm[2] = (sskpd >> 12) & 0xFF;
2129 wm[3] = (sskpd >> 20) & 0x1FF;
2130 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2131 } else if (INTEL_INFO(dev)->gen >= 6) {
2132 uint32_t sskpd = I915_READ(MCH_SSKPD);
2133
2134 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2135 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2136 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2137 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2138 } else if (INTEL_INFO(dev)->gen >= 5) {
2139 uint32_t mltr = I915_READ(MLTR_ILK);
2140
2141 /* ILK primary LP0 latency is 700 ns */
2142 wm[0] = 7;
2143 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2144 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2145 }
2146}
2147
53615a5e
VS		 2148static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2149{
2150 /* ILK sprite LP0 latency is 1300 ns */
2151 if (INTEL_INFO(dev)->gen == 5)
2152 wm[0] = 13;
2153}
2154
2155static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2156{
2157 /* ILK cursor LP0 latency is 1300 ns */
2158 if (INTEL_INFO(dev)->gen == 5)
2159 wm[0] = 13;
2160
2161 /* WaDoubleCursorLP3Latency:ivb */
2162 if (IS_IVYBRIDGE(dev))
2163 wm[3] *= 2;
2164}
2165
546c81fd 2166int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2167{
26ec971e 2168 /* how many WM levels are we expecting */
b6e742f6 2169 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB		 2170 return 7;
2171 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2172 return 4;
26ec971e 2173 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2174 return 3;
26ec971e 2175 else
ad0d6dc4
VS		 2176 return 2;
2177}
7526ed79 2178
ad0d6dc4
VS		 2179static void intel_print_wm_latency(struct drm_device *dev,
2180 const char *name,
2af30a5c 2181 const uint16_t wm[8])
ad0d6dc4
VS		 2182{
2183 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2184
2185 for (level = 0; level <= max_level; level++) {
2186 unsigned int latency = wm[level];
2187
2188 if (latency == 0) {
2189 DRM_ERROR("%s WM%d latency not provided\n",
2190 name, level);
2191 continue;
2192 }
2193
2af30a5c
PB		 2194 /*
2195 * - latencies are in us on gen9.
2196 * - before then, WM1+ latency values are in 0.5us units
2197 */
2198 if (IS_GEN9(dev))
2199 latency *= 10;
2200 else if (level > 0)
26ec971e
VS		 2201 latency *= 5;
2202
2203 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2204 name, level, wm[level],
2205 latency / 10, latency % 10);
2206 }
2207}
2208
e95a2f75
VS		 2209static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2210 uint16_t wm[5], uint16_t min)
2211{
2212 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2213
2214 if (wm[0] >= min)
2215 return false;
2216
2217 wm[0] = max(wm[0], min);
2218 for (level = 1; level <= max_level; level++)
2219 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2220
2221 return true;
2222}
2223
2224static void snb_wm_latency_quirk(struct drm_device *dev)
2225{
2226 struct drm_i915_private *dev_priv = dev->dev_private;
2227 bool changed;
2228
2229 /*
2230 * The BIOS provided WM memory latency values are often
2231 * inadequate for high resolution displays. Adjust them.
2232 */
2233 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2234 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2235 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2236
2237 if (!changed)
2238 return;
2239
2240 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2241 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2242 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2243 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2244}
2245
fa50ad61 2246static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2247{
2248 struct drm_i915_private *dev_priv = dev->dev_private;
2249
2250 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2251
2252 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2253 sizeof(dev_priv->wm.pri_latency));
2254 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2255 sizeof(dev_priv->wm.pri_latency));
2256
2257 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2258 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2259
2260 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2261 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2262 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2263
2264 if (IS_GEN6(dev))
2265 snb_wm_latency_quirk(dev);
53615a5e
VS		 2266}
2267
2af30a5c
PB		 2268static void skl_setup_wm_latency(struct drm_device *dev)
2269{
2270 struct drm_i915_private *dev_priv = dev->dev_private;
2271
2272 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2273 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2274}
2275
0b2ae6d7 2276/* Compute new watermarks for the pipe */
86c8bbbe
MR		 2277static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc,
2278 struct drm_atomic_state *state)
0b2ae6d7 2279{
86c8bbbe
MR		 2280 struct intel_pipe_wm *pipe_wm;
2281 struct drm_device *dev = intel_crtc->base.dev;
d34ff9c6 2282 const struct drm_i915_private *dev_priv = dev->dev_private;
86c8bbbe 2283 struct intel_crtc_state *cstate = NULL;
43d59eda 2284 struct intel_plane *intel_plane;
86c8bbbe
MR		 2285 struct drm_plane_state *ps;
2286 struct intel_plane_state *pristate = NULL;
43d59eda 2287 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2288 struct intel_plane_state *curstate = NULL;
0b2ae6d7
VS		 2289 int level, max_level = ilk_wm_max_level(dev);
2290 /* LP0 watermark maximums depend on this pipe alone */
2291 struct intel_wm_config config = {
2292 .num_pipes_active = 1,
0b2ae6d7 2293 };
820c1980 2294 struct ilk_wm_maximums max;
0b2ae6d7 2295
86c8bbbe
MR		 2296 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
2297 if (IS_ERR(cstate))
2298 return PTR_ERR(cstate);
2299
2300 pipe_wm = &cstate->wm.optimal.ilk;
2301
43d59eda 2302 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
86c8bbbe
MR		 2303 ps = drm_atomic_get_plane_state(state,
2304 &intel_plane->base);
2305 if (IS_ERR(ps))
2306 return PTR_ERR(ps);
2307
2308 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2309 pristate = to_intel_plane_state(ps);
2310 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2311 sprstate = to_intel_plane_state(ps);
2312 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2313 curstate = to_intel_plane_state(ps);
43d59eda
MR		 2314 }
2315
2316 config.sprites_enabled = sprstate->visible;
2317 config.sprites_scaled = sprstate->visible &&
2318 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2319 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2320
7221fc33 2321 pipe_wm->pipe_enabled = cstate->base.active;
86c8bbbe 2322 pipe_wm->sprites_enabled = config.sprites_enabled;
43d59eda 2323 pipe_wm->sprites_scaled = config.sprites_scaled;
2a44b76b 2324
7b39a0b7 2325 /* ILK/SNB: LP2+ watermarks only w/o sprites */
43d59eda 2326 if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible)
7b39a0b7
VS		 2327 max_level = 1;
2328
2329 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
43d59eda 2330 if (config.sprites_scaled)
7b39a0b7
VS		 2331 max_level = 0;
2332
86c8bbbe
MR		 2333 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2334 pristate, sprstate, curstate, &pipe_wm->wm[0]);
0b2ae6d7 2335
a42a5719 2336 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ee91a159 2337 pipe_wm->linetime = hsw_compute_linetime_wm(dev, cstate);
0b2ae6d7 2338
a3cb4048
VS		 2339 /* LP0 watermarks always use 1/2 DDB partitioning */
2340 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2341
0b2ae6d7 2342 /* At least LP0 must be valid */
a3cb4048 2343 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
86c8bbbe 2344 return -EINVAL;
a3cb4048
VS		 2345
2346 ilk_compute_wm_reg_maximums(dev, 1, &max);
2347
2348 for (level = 1; level <= max_level; level++) {
2349 struct intel_wm_level wm = {};
2350
86c8bbbe
MR		 2351 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2352 pristate, sprstate, curstate, &wm);
a3cb4048
VS		 2353
2354 /*
2355 * Disable any watermark level that exceeds the
2356 * register maximums since such watermarks are
2357 * always invalid.
2358 */
2359 if (!ilk_validate_wm_level(level, &max, &wm))
2360 break;
2361
2362 pipe_wm->wm[level] = wm;
2363 }
2364
86c8bbbe 2365 return 0;
0b2ae6d7
VS		 2366}
2367
2368/*
2369 * Merge the watermarks from all active pipes for a specific level.
2370 */
2371static void ilk_merge_wm_level(struct drm_device *dev,
2372 int level,
2373 struct intel_wm_level *ret_wm)
2374{
2375 const struct intel_crtc *intel_crtc;
2376
d52fea5b
VS		 2377 ret_wm->enable = true;
2378
d3fcc808 2379 for_each_intel_crtc(dev, intel_crtc) {
4e0963c7
MR		 2380 const struct intel_crtc_state *cstate =
2381 to_intel_crtc_state(intel_crtc->base.state);
2382 const struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
fe392efd
VS		 2383 const struct intel_wm_level *wm = &active->wm[level];
2384
2385 if (!active->pipe_enabled)
2386 continue;
0b2ae6d7 2387
d52fea5b
VS		 2388 /*
2389 * The watermark values may have been used in the past,
2390 * so we must maintain them in the registers for some
2391 * time even if the level is now disabled.
2392 */
0b2ae6d7 2393 if (!wm->enable)
d52fea5b 2394 ret_wm->enable = false;
0b2ae6d7
VS		 2395
2396 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2397 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2398 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2399 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2400 }
0b2ae6d7
VS		 2401}
2402
2403/*
2404 * Merge all low power watermarks for all active pipes.
2405 */
2406static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2407 const struct intel_wm_config *config,
820c1980 2408 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2409 struct intel_pipe_wm *merged)
2410{
7733b49b 2411 struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7 2412 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2413 int last_enabled_level = max_level;
0b2ae6d7 2414
0ba22e26
VS		 2415 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2416 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2417 config->num_pipes_active > 1)
2418 return;
2419
6c8b6c28
VS		 2420 /* ILK: FBC WM must be disabled always */
2421 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2422
2423 /* merge each WM1+ level */
2424 for (level = 1; level <= max_level; level++) {
2425 struct intel_wm_level *wm = &merged->wm[level];
2426
2427 ilk_merge_wm_level(dev, level, wm);
2428
d52fea5b
VS		 2429 if (level > last_enabled_level)
2430 wm->enable = false;
2431 else if (!ilk_validate_wm_level(level, max, wm))
2432 /* make sure all following levels get disabled */
2433 last_enabled_level = level - 1;
0b2ae6d7
VS		 2434
2435 /*
2436 * The spec says it is preferred to disable
2437 * FBC WMs instead of disabling a WM level.
2438 */
2439 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2440 if (wm->enable)
2441 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2442 wm->fbc_val = 0;
2443 }
2444 }
6c8b6c28
VS		 2445
2446 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2447 /*
2448 * FIXME this is racy. FBC might get enabled later.
2449 * What we should check here is whether FBC can be
2450 * enabled sometime later.
2451 */
7733b49b 2452 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
0e631adc 2453 intel_fbc_is_active(dev_priv)) {
6c8b6c28
VS		 2454 for (level = 2; level <= max_level; level++) {
2455 struct intel_wm_level *wm = &merged->wm[level];
2456
2457 wm->enable = false;
2458 }
2459 }
0b2ae6d7
VS		 2460}
2461
b380ca3c
VS		 2462static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2463{
2464 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2465 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2466}
2467
a68d68ee
VS		 2468/* The value we need to program into the WM_LPx latency field */
2469static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2470{
2471 struct drm_i915_private *dev_priv = dev->dev_private;
2472
a42a5719 2473 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2474 return 2 * level;
2475 else
2476 return dev_priv->wm.pri_latency[level];
2477}
2478
820c1980 2479static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2480 const struct intel_pipe_wm *merged,
609cedef 2481 enum intel_ddb_partitioning partitioning,
820c1980 2482 struct ilk_wm_values *results)
801bcfff 2483{
0b2ae6d7
VS		 2484 struct intel_crtc *intel_crtc;
2485 int level, wm_lp;
cca32e9a 2486
0362c781 2487 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2488 results->partitioning = partitioning;
cca32e9a 2489
0b2ae6d7 2490 /* LP1+ register values */
cca32e9a 2491 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2492 const struct intel_wm_level *r;
801bcfff 2493
b380ca3c 2494 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2495
0362c781 2496 r = &merged->wm[level];
cca32e9a 2497
d52fea5b
VS		 2498 /*
2499 * Maintain the watermark values even if the level is
2500 * disabled. Doing otherwise could cause underruns.
2501 */
2502 results->wm_lp[wm_lp - 1] =
a68d68ee 2503 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2504 (r->pri_val << WM1_LP_SR_SHIFT) |
2505 r->cur_val;
2506
d52fea5b
VS		 2507 if (r->enable)
2508 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2509
416f4727
VS		 2510 if (INTEL_INFO(dev)->gen >= 8)
2511 results->wm_lp[wm_lp - 1] |=
2512 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2513 else
2514 results->wm_lp[wm_lp - 1] |=
2515 r->fbc_val << WM1_LP_FBC_SHIFT;
2516
d52fea5b
VS		 2517 /*
2518 * Always set WM1S_LP_EN when spr_val != 0, even if the
2519 * level is disabled. Doing otherwise could cause underruns.
2520 */
6cef2b8a
VS		 2521 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2522 WARN_ON(wm_lp != 1);
2523 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2524 } else
2525 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2526 }
801bcfff 2527
0b2ae6d7 2528 /* LP0 register values */
d3fcc808 2529 for_each_intel_crtc(dev, intel_crtc) {
4e0963c7
MR		 2530 const struct intel_crtc_state *cstate =
2531 to_intel_crtc_state(intel_crtc->base.state);
0b2ae6d7 2532 enum pipe pipe = intel_crtc->pipe;
4e0963c7 2533 const struct intel_wm_level *r = &cstate->wm.optimal.ilk.wm[0];
0b2ae6d7
VS		 2534
2535 if (WARN_ON(!r->enable))
2536 continue;
2537
4e0963c7 2538 results->wm_linetime[pipe] = cstate->wm.optimal.ilk.linetime;
1011d8c4 2539
0b2ae6d7
VS		 2540 results->wm_pipe[pipe] =
2541 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2542 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2543 r->cur_val;
801bcfff
PZ		 2544 }
2545}
2546
861f3389
PZ		 2547/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2548 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2549static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2550 struct intel_pipe_wm *r1,
2551 struct intel_pipe_wm *r2)
861f3389 2552{
198a1e9b
VS		 2553 int level, max_level = ilk_wm_max_level(dev);
2554 int level1 = 0, level2 = 0;
861f3389 2555
198a1e9b
VS		 2556 for (level = 1; level <= max_level; level++) {
2557 if (r1->wm[level].enable)
2558 level1 = level;
2559 if (r2->wm[level].enable)
2560 level2 = level;
861f3389
PZ		 2561 }
2562
198a1e9b
VS		 2563 if (level1 == level2) {
2564 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2565 return r2;
2566 else
2567 return r1;
198a1e9b 2568 } else if (level1 > level2) {
861f3389
PZ		 2569 return r1;
2570 } else {
2571 return r2;
2572 }
2573}
2574
49a687c4
VS		 2575/* dirty bits used to track which watermarks need changes */
2576#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2577#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2578#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2579#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2580#define WM_DIRTY_FBC (1 << 24)
2581#define WM_DIRTY_DDB (1 << 25)
2582
055e393f 2583static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2584 const struct ilk_wm_values *old,
2585 const struct ilk_wm_values *new)
49a687c4
VS		 2586{
2587 unsigned int dirty = 0;
2588 enum pipe pipe;
2589 int wm_lp;
2590
055e393f 2591 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2592 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2593 dirty |= WM_DIRTY_LINETIME(pipe);
2594 /* Must disable LP1+ watermarks too */
2595 dirty |= WM_DIRTY_LP_ALL;
2596 }
2597
2598 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2599 dirty |= WM_DIRTY_PIPE(pipe);
2600 /* Must disable LP1+ watermarks too */
2601 dirty |= WM_DIRTY_LP_ALL;
2602 }
2603 }
2604
2605 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2606 dirty |= WM_DIRTY_FBC;
2607 /* Must disable LP1+ watermarks too */
2608 dirty |= WM_DIRTY_LP_ALL;
2609 }
2610
2611 if (old->partitioning != new->partitioning) {
2612 dirty |= WM_DIRTY_DDB;
2613 /* Must disable LP1+ watermarks too */
2614 dirty |= WM_DIRTY_LP_ALL;
2615 }
2616
2617 /* LP1+ watermarks already deemed dirty, no need to continue */
2618 if (dirty & WM_DIRTY_LP_ALL)
2619 return dirty;
2620
2621 /* Find the lowest numbered LP1+ watermark in need of an update... */
2622 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2623 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2624 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2625 break;
2626 }
2627
2628 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2629 for (; wm_lp <= 3; wm_lp++)
2630 dirty |= WM_DIRTY_LP(wm_lp);
2631
2632 return dirty;
2633}
2634
8553c18e
VS		 2635static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2636 unsigned int dirty)
801bcfff 2637{
820c1980 2638 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2639 bool changed = false;
801bcfff 2640
facd619b
VS		 2641 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2642 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2643 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2644 changed = true;
facd619b
VS		 2645 }
2646 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2647 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2648 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2649 changed = true;
facd619b
VS		 2650 }
2651 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2652 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2653 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2654 changed = true;
facd619b 2655 }
801bcfff 2656
facd619b
VS		 2657 /*
2658 * Don't touch WM1S_LP_EN here.
2659 * Doing so could cause underruns.
2660 */
6cef2b8a 2661
8553c18e
VS		 2662 return changed;
2663}
2664
2665/*
2666 * The spec says we shouldn't write when we don't need, because every write
2667 * causes WMs to be re-evaluated, expending some power.
2668 */
820c1980
ID		 2669static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2670 struct ilk_wm_values *results)
8553c18e
VS		 2671{
2672 struct drm_device *dev = dev_priv->dev;
820c1980 2673 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2674 unsigned int dirty;
2675 uint32_t val;
2676
055e393f 2677 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2678 if (!dirty)
2679 return;
2680
2681 _ilk_disable_lp_wm(dev_priv, dirty);
2682
49a687c4 2683 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2684 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2685 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2686 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2687 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2688 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2689
49a687c4 2690 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2691 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2692 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2693 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2694 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2695 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2696
49a687c4 2697 if (dirty & WM_DIRTY_DDB) {
a42a5719 2698 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2699 val = I915_READ(WM_MISC);
2700 if (results->partitioning == INTEL_DDB_PART_1_2)
2701 val &= ~WM_MISC_DATA_PARTITION_5_6;
2702 else
2703 val |= WM_MISC_DATA_PARTITION_5_6;
2704 I915_WRITE(WM_MISC, val);
2705 } else {
2706 val = I915_READ(DISP_ARB_CTL2);
2707 if (results->partitioning == INTEL_DDB_PART_1_2)
2708 val &= ~DISP_DATA_PARTITION_5_6;
2709 else
2710 val |= DISP_DATA_PARTITION_5_6;
2711 I915_WRITE(DISP_ARB_CTL2, val);
2712 }
1011d8c4
PZ		 2713 }
2714
49a687c4 2715 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2716 val = I915_READ(DISP_ARB_CTL);
2717 if (results->enable_fbc_wm)
2718 val &= ~DISP_FBC_WM_DIS;
2719 else
2720 val |= DISP_FBC_WM_DIS;
2721 I915_WRITE(DISP_ARB_CTL, val);
2722 }
2723
954911eb
ID		 2724 if (dirty & WM_DIRTY_LP(1) &&
2725 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2726 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2727
2728 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2729 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2730 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2731 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2732 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2733 }
801bcfff 2734
facd619b 2735 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2736 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2737 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2738 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2739 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2740 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2741
2742 dev_priv->wm.hw = *results;
801bcfff
PZ		 2743}
2744
8553c18e
VS		 2745static bool ilk_disable_lp_wm(struct drm_device *dev)
2746{
2747 struct drm_i915_private *dev_priv = dev->dev_private;
2748
2749 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2750}
2751
b9cec075
DL		 2752/*
2753 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2754 * different active planes.
2755 */
2756
2757#define SKL_DDB_SIZE 896 /* in blocks */
43d735a6 2758#define BXT_DDB_SIZE 512
b9cec075 2759
024c9045
MR		 2760/*
2761 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2762 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2763 * other universal planes are in indices 1..n. Note that this may leave unused
2764 * indices between the top "sprite" plane and the cursor.
2765 */
2766static int
2767skl_wm_plane_id(const struct intel_plane *plane)
2768{
2769 switch (plane->base.type) {
2770 case DRM_PLANE_TYPE_PRIMARY:
2771 return 0;
2772 case DRM_PLANE_TYPE_CURSOR:
2773 return PLANE_CURSOR;
2774 case DRM_PLANE_TYPE_OVERLAY:
2775 return plane->plane + 1;
2776 default:
2777 MISSING_CASE(plane->base.type);
2778 return plane->plane;
2779 }
2780}
2781
b9cec075
DL		 2782static void
2783skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 2784 const struct intel_crtc_state *cstate,
b9cec075 2785 const struct intel_wm_config *config,
b9cec075
DL		 2786 struct skl_ddb_entry *alloc /* out */)
2787{
024c9045 2788 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 2789 struct drm_crtc *crtc;
2790 unsigned int pipe_size, ddb_size;
2791 int nth_active_pipe;
2792
024c9045 2793 if (!cstate->base.active) {
b9cec075
DL		 2794 alloc->start = 0;
2795 alloc->end = 0;
2796 return;
2797 }
2798
43d735a6
DL		 2799 if (IS_BROXTON(dev))
2800 ddb_size = BXT_DDB_SIZE;
2801 else
2802 ddb_size = SKL_DDB_SIZE;
b9cec075
DL		 2803
2804 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2805
2806 nth_active_pipe = 0;
2807 for_each_crtc(dev, crtc) {
3ef00284 2808 if (!to_intel_crtc(crtc)->active)
b9cec075
DL		 2809 continue;
2810
2811 if (crtc == for_crtc)
2812 break;
2813
2814 nth_active_pipe++;
2815 }
2816
2817 pipe_size = ddb_size / config->num_pipes_active;
2818 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
16160e3d 2819 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 2820}
2821
2822static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2823{
2824 if (config->num_pipes_active == 1)
2825 return 32;
2826
2827 return 8;
2828}
2829
a269c583
DL		 2830static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2831{
2832 entry->start = reg & 0x3ff;
2833 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2834 if (entry->end)
2835 entry->end += 1;
a269c583
DL		 2836}
2837
08db6652
DL		 2838void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2839 struct skl_ddb_allocation *ddb /* out */)
a269c583 2840{
a269c583
DL		 2841 enum pipe pipe;
2842 int plane;
2843 u32 val;
2844
b10f1b20
ML		 2845 memset(ddb, 0, sizeof(*ddb));
2846
a269c583 2847 for_each_pipe(dev_priv, pipe) {
b10f1b20
ML		 2848 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe)))
2849 continue;
2850
dd740780 2851 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 2852 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2853 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2854 val);
2855 }
2856
2857 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 2858 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2859 val);
a269c583
DL		 2860 }
2861}
2862
b9cec075 2863static unsigned int
024c9045
MR		 2864skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2865 const struct drm_plane_state *pstate,
2866 int y)
b9cec075 2867{
024c9045
MR		 2868 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2869 struct drm_framebuffer *fb = pstate->fb;
2cd601c6
CK		 2870
2871 /* for planar format */
024c9045 2872 if (fb->pixel_format == DRM_FORMAT_NV12) {
2cd601c6 2873 if (y) /* y-plane data rate */
024c9045
MR		 2874 return intel_crtc->config->pipe_src_w *
2875 intel_crtc->config->pipe_src_h *
2876 drm_format_plane_cpp(fb->pixel_format, 0);
2cd601c6 2877 else /* uv-plane data rate */
024c9045
MR		 2878 return (intel_crtc->config->pipe_src_w/2) *
2879 (intel_crtc->config->pipe_src_h/2) *
2880 drm_format_plane_cpp(fb->pixel_format, 1);
2cd601c6
CK		 2881 }
2882
2883 /* for packed formats */
024c9045
MR		 2884 return intel_crtc->config->pipe_src_w *
2885 intel_crtc->config->pipe_src_h *
2886 drm_format_plane_cpp(fb->pixel_format, 0);
b9cec075
DL		 2887}
2888
2889/*
2890 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2891 * a 8192x4096@32bpp framebuffer:
2892 * 3 * 4096 * 8192 * 4 < 2^32
2893 */
2894static unsigned int
024c9045 2895skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
b9cec075 2896{
024c9045
MR		 2897 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2898 struct drm_device *dev = intel_crtc->base.dev;
2899 const struct intel_plane *intel_plane;
b9cec075 2900 unsigned int total_data_rate = 0;
b9cec075 2901
024c9045
MR		 2902 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2903 const struct drm_plane_state *pstate = intel_plane->base.state;
b9cec075 2904
024c9045 2905 if (pstate->fb == NULL)
b9cec075
DL		 2906 continue;
2907
024c9045
MR		 2908 if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2909 continue;
2910
2911 /* packed/uv */
2912 total_data_rate += skl_plane_relative_data_rate(cstate,
2913 pstate,
2914 0);
2915
2916 if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
2917 /* y-plane */
2918 total_data_rate += skl_plane_relative_data_rate(cstate,
2919 pstate,
2920 1);
b9cec075
DL		 2921 }
2922
2923 return total_data_rate;
2924}
2925
2926static void
024c9045 2927skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 2928 struct skl_ddb_allocation *ddb /* out */)
2929{
024c9045 2930 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075 2931 struct drm_device *dev = crtc->dev;
aa363136
MR		 2932 struct drm_i915_private *dev_priv = to_i915(dev);
2933 struct intel_wm_config *config = &dev_priv->wm.config;
b9cec075 2934 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 2935 struct intel_plane *intel_plane;
b9cec075 2936 enum pipe pipe = intel_crtc->pipe;
34bb56af 2937 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 2938 uint16_t alloc_size, start, cursor_blocks;
80958155 2939 uint16_t minimum[I915_MAX_PLANES];
2cd601c6 2940 uint16_t y_minimum[I915_MAX_PLANES];
b9cec075 2941 unsigned int total_data_rate;
b9cec075 2942
024c9045 2943 skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc);
34bb56af 2944 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 2945 if (alloc_size == 0) {
2946 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
4969d33e
MR		 2947 memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
2948 sizeof(ddb->plane[pipe][PLANE_CURSOR]));
b9cec075
DL		 2949 return;
2950 }
2951
2952 cursor_blocks = skl_cursor_allocation(config);
4969d33e
MR		 2953 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
2954 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
b9cec075
DL		 2955
2956 alloc_size -= cursor_blocks;
34bb56af 2957 alloc->end -= cursor_blocks;
b9cec075 2958
80958155 2959 /* 1. Allocate the mininum required blocks for each active plane */
024c9045
MR		 2960 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2961 struct drm_plane *plane = &intel_plane->base;
2962 struct drm_framebuffer *fb = plane->state->fb;
2963 int id = skl_wm_plane_id(intel_plane);
80958155 2964
024c9045
MR		 2965 if (fb == NULL)
2966 continue;
2967 if (plane->type == DRM_PLANE_TYPE_CURSOR)
80958155
DL		 2968 continue;
2969
024c9045
MR		 2970 minimum[id] = 8;
2971 alloc_size -= minimum[id];
2972 y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
2973 alloc_size -= y_minimum[id];
80958155
DL		 2974 }
2975
b9cec075 2976 /*
80958155
DL		 2977 * 2. Distribute the remaining space in proportion to the amount of
2978 * data each plane needs to fetch from memory.
b9cec075
DL		 2979 *
2980 * FIXME: we may not allocate every single block here.
2981 */
024c9045 2982 total_data_rate = skl_get_total_relative_data_rate(cstate);
b9cec075 2983
34bb56af 2984 start = alloc->start;
024c9045
MR		 2985 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2986 struct drm_plane *plane = &intel_plane->base;
2987 struct drm_plane_state *pstate = intel_plane->base.state;
2cd601c6
CK		 2988 unsigned int data_rate, y_data_rate;
2989 uint16_t plane_blocks, y_plane_blocks = 0;
024c9045 2990 int id = skl_wm_plane_id(intel_plane);
b9cec075 2991
024c9045
MR		 2992 if (pstate->fb == NULL)
2993 continue;
2994 if (plane->type == DRM_PLANE_TYPE_CURSOR)
b9cec075
DL		 2995 continue;
2996
024c9045 2997 data_rate = skl_plane_relative_data_rate(cstate, pstate, 0);
b9cec075
DL		 2998
2999 /*
2cd601c6 3000 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3001 * promote the expression to 64 bits to avoid overflowing, the
3002 * result is < available as data_rate / total_data_rate < 1
3003 */
024c9045 3004 plane_blocks = minimum[id];
80958155
DL		 3005 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3006 total_data_rate);
b9cec075 3007
024c9045
MR		 3008 ddb->plane[pipe][id].start = start;
3009 ddb->plane[pipe][id].end = start + plane_blocks;
b9cec075
DL		 3010
3011 start += plane_blocks;
2cd601c6
CK		 3012
3013 /*
3014 * allocation for y_plane part of planar format:
3015 */
024c9045
MR		 3016 if (pstate->fb->pixel_format == DRM_FORMAT_NV12) {
3017 y_data_rate = skl_plane_relative_data_rate(cstate,
3018 pstate,
3019 1);
3020 y_plane_blocks = y_minimum[id];
2cd601c6
CK		 3021 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3022 total_data_rate);
3023
024c9045
MR		 3024 ddb->y_plane[pipe][id].start = start;
3025 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
2cd601c6
CK		 3026
3027 start += y_plane_blocks;
3028 }
3029
b9cec075
DL		 3030 }
3031
3032}
3033
5cec258b 3034static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3035{
3036 /* TODO: Take into account the scalers once we support them */
2d112de7 3037 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3038}
3039
3040/*
3041 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3042 * for the read latency) and bytes_per_pixel should always be <= 8, so that
3043 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3044 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3045*/
3046static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
3047 uint32_t latency)
3048{
3049 uint32_t wm_intermediate_val, ret;
3050
3051 if (latency == 0)
3052 return UINT_MAX;
3053
d4c2aa60 3054 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
2d41c0b5
PB		 3055 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3056
3057 return ret;
3058}
3059
3060static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3061 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
0fda6568 3062 uint64_t tiling, uint32_t latency)
2d41c0b5 3063{
d4c2aa60
TU		 3064 uint32_t ret;
3065 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3066 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3067
3068 if (latency == 0)
3069 return UINT_MAX;
3070
3071 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
0fda6568
TU		 3072
3073 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3074 tiling == I915_FORMAT_MOD_Yf_TILED) {
3075 plane_bytes_per_line *= 4;
3076 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3077 plane_blocks_per_line /= 4;
3078 } else {
3079 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3080 }
3081
2d41c0b5
PB		 3082 wm_intermediate_val = latency * pixel_rate;
3083 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3084 plane_blocks_per_line;
2d41c0b5
PB		 3085
3086 return ret;
3087}
3088
2d41c0b5
PB		 3089static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3090 const struct intel_crtc *intel_crtc)
3091{
3092 struct drm_device *dev = intel_crtc->base.dev;
3093 struct drm_i915_private *dev_priv = dev->dev_private;
3094 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
2d41c0b5 3095
e6d90023
KM		 3096 /*
3097 * If ddb allocation of pipes changed, it may require recalculation of
3098 * watermarks
3099 */
3100 if (memcmp(new_ddb->pipe, cur_ddb->pipe, sizeof(new_ddb->pipe)))
2d41c0b5
PB		 3101 return true;
3102
3103 return false;
3104}
3105
d4c2aa60 3106static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
024c9045
MR		 3107 struct intel_crtc_state *cstate,
3108 struct intel_plane *intel_plane,
afb024aa 3109 uint16_t ddb_allocation,
d4c2aa60 3110 int level,
afb024aa
DL		 3111 uint16_t *out_blocks, /* out */
3112 uint8_t *out_lines /* out */)
2d41c0b5 3113{
024c9045
MR		 3114 struct drm_plane *plane = &intel_plane->base;
3115 struct drm_framebuffer *fb = plane->state->fb;
d4c2aa60
TU		 3116 uint32_t latency = dev_priv->wm.skl_latency[level];
3117 uint32_t method1, method2;
3118 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3119 uint32_t res_blocks, res_lines;
3120 uint32_t selected_result;
2cd601c6 3121 uint8_t bytes_per_pixel;
2d41c0b5 3122
024c9045 3123 if (latency == 0 || !cstate->base.active || !fb)
2d41c0b5
PB		 3124 return false;
3125
024c9045
MR		 3126 bytes_per_pixel = drm_format_plane_cpp(fb->pixel_format, 0);
3127 method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
2cd601c6 3128 bytes_per_pixel,
d4c2aa60 3129 latency);
024c9045
MR		 3130 method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
3131 cstate->base.adjusted_mode.crtc_htotal,
3132 cstate->pipe_src_w,
2cd601c6 3133 bytes_per_pixel,
024c9045 3134 fb->modifier[0],
d4c2aa60 3135 latency);
2d41c0b5 3136
024c9045 3137 plane_bytes_per_line = cstate->pipe_src_w * bytes_per_pixel;
d4c2aa60 3138 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 3139
024c9045
MR		 3140 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3141 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 3142 uint32_t min_scanlines = 4;
3143 uint32_t y_tile_minimum;
024c9045
MR		 3144 if (intel_rotation_90_or_270(plane->state->rotation)) {
3145 int bpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3146 drm_format_plane_cpp(fb->pixel_format, 1) :
3147 drm_format_plane_cpp(fb->pixel_format, 0);
3148
3149 switch (bpp) {
1fc0a8f7
TU		 3150 case 1:
3151 min_scanlines = 16;
3152 break;
3153 case 2:
3154 min_scanlines = 8;
3155 break;
3156 case 8:
3157 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 3158 }
1fc0a8f7
TU		 3159 }
3160 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 3161 selected_result = max(method2, y_tile_minimum);
3162 } else {
3163 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3164 selected_result = min(method1, method2);
3165 else
3166 selected_result = method1;
3167 }
2d41c0b5 3168
d4c2aa60
TU		 3169 res_blocks = selected_result + 1;
3170 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3171
0fda6568 3172 if (level >= 1 && level <= 7) {
024c9045
MR		 3173 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3174 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
0fda6568
TU		 3175 res_lines += 4;
3176 else
3177 res_blocks++;
3178 }
e6d66171 3179
d4c2aa60 3180 if (res_blocks >= ddb_allocation || res_lines > 31)
e6d66171
DL		 3181 return false;
3182
3183 *out_blocks = res_blocks;
3184 *out_lines = res_lines;
2d41c0b5
PB		 3185
3186 return true;
3187}
3188
3189static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3190 struct skl_ddb_allocation *ddb,
024c9045 3191 struct intel_crtc_state *cstate,
2d41c0b5 3192 int level,
2d41c0b5
PB		 3193 struct skl_wm_level *result)
3194{
024c9045
MR		 3195 struct drm_device *dev = dev_priv->dev;
3196 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3197 struct intel_plane *intel_plane;
2d41c0b5 3198 uint16_t ddb_blocks;
024c9045
MR		 3199 enum pipe pipe = intel_crtc->pipe;
3200
3201 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3202 int i = skl_wm_plane_id(intel_plane);
2d41c0b5 3203
2d41c0b5
PB		 3204 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3205
d4c2aa60 3206 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
024c9045
MR		 3207 cstate,
3208 intel_plane,
2d41c0b5 3209 ddb_blocks,
d4c2aa60 3210 level,
2d41c0b5
PB		 3211 &result->plane_res_b[i],
3212 &result->plane_res_l[i]);
3213 }
2d41c0b5
PB		 3214}
3215
407b50f3 3216static uint32_t
024c9045 3217skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3218{
024c9045 3219 if (!cstate->base.active)
407b50f3
DL		 3220 return 0;
3221
024c9045 3222 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
661abfc0 3223 return 0;
407b50f3 3224
024c9045
MR		 3225 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3226 skl_pipe_pixel_rate(cstate));
407b50f3
DL		 3227}
3228
024c9045 3229static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3230 struct skl_wm_level *trans_wm /* out */)
407b50f3 3231{
024c9045 3232 struct drm_crtc *crtc = cstate->base.crtc;
9414f563 3233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3234 struct intel_plane *intel_plane;
9414f563 3235
024c9045 3236 if (!cstate->base.active)
407b50f3 3237 return;
9414f563
DL		 3238
3239 /* Until we know more, just disable transition WMs */
024c9045
MR		 3240 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3241 int i = skl_wm_plane_id(intel_plane);
3242
9414f563 3243 trans_wm->plane_en[i] = false;
024c9045 3244 }
407b50f3
DL		 3245}
3246
024c9045 3247static void skl_compute_pipe_wm(struct intel_crtc_state *cstate,
2d41c0b5 3248 struct skl_ddb_allocation *ddb,
2d41c0b5
PB		 3249 struct skl_pipe_wm *pipe_wm)
3250{
024c9045 3251 struct drm_device *dev = cstate->base.crtc->dev;
2d41c0b5 3252 const struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5
PB		 3253 int level, max_level = ilk_wm_max_level(dev);
3254
3255 for (level = 0; level <= max_level; level++) {
024c9045
MR		 3256 skl_compute_wm_level(dev_priv, ddb, cstate,
3257 level, &pipe_wm->wm[level]);
2d41c0b5 3258 }
024c9045 3259 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3260
024c9045 3261 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
2d41c0b5
PB		 3262}
3263
3264static void skl_compute_wm_results(struct drm_device *dev,
2d41c0b5
PB		 3265 struct skl_pipe_wm *p_wm,
3266 struct skl_wm_values *r,
3267 struct intel_crtc *intel_crtc)
3268{
3269 int level, max_level = ilk_wm_max_level(dev);
3270 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3271 uint32_t temp;
3272 int i;
2d41c0b5
PB		 3273
3274 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3275 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3276 temp = 0;
2d41c0b5
PB		 3277
3278 temp |= p_wm->wm[level].plane_res_l[i] <<
3279 PLANE_WM_LINES_SHIFT;
3280 temp |= p_wm->wm[level].plane_res_b[i];
3281 if (p_wm->wm[level].plane_en[i])
3282 temp |= PLANE_WM_EN;
3283
3284 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3285 }
3286
3287 temp = 0;
2d41c0b5 3288
4969d33e
MR		 3289 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3290 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
2d41c0b5 3291
4969d33e 3292 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
2d41c0b5
PB		 3293 temp |= PLANE_WM_EN;
3294
4969d33e 3295 r->plane[pipe][PLANE_CURSOR][level] = temp;
2d41c0b5
PB		 3296
3297 }
3298
9414f563
DL		 3299 /* transition WMs */
3300 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3301 temp = 0;
3302 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3303 temp |= p_wm->trans_wm.plane_res_b[i];
3304 if (p_wm->trans_wm.plane_en[i])
3305 temp |= PLANE_WM_EN;
3306
3307 r->plane_trans[pipe][i] = temp;
3308 }
3309
3310 temp = 0;
4969d33e
MR		 3311 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3312 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3313 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
9414f563
DL		 3314 temp |= PLANE_WM_EN;
3315
4969d33e 3316 r->plane_trans[pipe][PLANE_CURSOR] = temp;
9414f563 3317
2d41c0b5
PB		 3318 r->wm_linetime[pipe] = p_wm->linetime;
3319}
3320
f0f59a00
VS		 3321static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3322 i915_reg_t reg,
16160e3d
DL		 3323 const struct skl_ddb_entry *entry)
3324{
3325 if (entry->end)
3326 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3327 else
3328 I915_WRITE(reg, 0);
3329}
3330
2d41c0b5
PB		 3331static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3332 const struct skl_wm_values *new)
3333{
3334 struct drm_device *dev = dev_priv->dev;
3335 struct intel_crtc *crtc;
3336
19c8054c 3337 for_each_intel_crtc(dev, crtc) {
2d41c0b5
PB		 3338 int i, level, max_level = ilk_wm_max_level(dev);
3339 enum pipe pipe = crtc->pipe;
3340
5d374d96
DL		 3341 if (!new->dirty[pipe])
3342 continue;
8211bd5b 3343
5d374d96 3344 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3345
5d374d96
DL		 3346 for (level = 0; level <= max_level; level++) {
3347 for (i = 0; i < intel_num_planes(crtc); i++)
3348 I915_WRITE(PLANE_WM(pipe, i, level),
3349 new->plane[pipe][i][level]);
3350 I915_WRITE(CUR_WM(pipe, level),
4969d33e 3351 new->plane[pipe][PLANE_CURSOR][level]);
2d41c0b5 3352 }
5d374d96
DL		 3353 for (i = 0; i < intel_num_planes(crtc); i++)
3354 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3355 new->plane_trans[pipe][i]);
4969d33e
MR		 3356 I915_WRITE(CUR_WM_TRANS(pipe),
3357 new->plane_trans[pipe][PLANE_CURSOR]);
5d374d96 3358
2cd601c6 3359 for (i = 0; i < intel_num_planes(crtc); i++) {
5d374d96
DL		 3360 skl_ddb_entry_write(dev_priv,
3361 PLANE_BUF_CFG(pipe, i),
3362 &new->ddb.plane[pipe][i]);
2cd601c6
CK		 3363 skl_ddb_entry_write(dev_priv,
3364 PLANE_NV12_BUF_CFG(pipe, i),
3365 &new->ddb.y_plane[pipe][i]);
3366 }
5d374d96
DL		 3367
3368 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
4969d33e 3369 &new->ddb.plane[pipe][PLANE_CURSOR]);
2d41c0b5 3370 }
2d41c0b5
PB		 3371}
3372
0e8fb7ba
DL		 3373/*
3374 * When setting up a new DDB allocation arrangement, we need to correctly
3375 * sequence the times at which the new allocations for the pipes are taken into
3376 * account or we'll have pipes fetching from space previously allocated to
3377 * another pipe.
3378 *
3379 * Roughly the sequence looks like:
3380 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3381 * overlapping with a previous light-up pipe (another way to put it is:
3382 * pipes with their new allocation strickly included into their old ones).
3383 * 2. re-allocate the other pipes that get their allocation reduced
3384 * 3. allocate the pipes having their allocation increased
3385 *
3386 * Steps 1. and 2. are here to take care of the following case:
3387 * - Initially DDB looks like this:
3388 * | B | C |
3389 * - enable pipe A.
3390 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3391 * allocation
3392 * | A | B | C |
3393 *
3394 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3395 */
3396
d21b795c
DL		 3397static void
3398skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3399{
0e8fb7ba
DL		 3400 int plane;
3401
d21b795c
DL		 3402 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3403
dd740780 3404 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3405 I915_WRITE(PLANE_SURF(pipe, plane),
3406 I915_READ(PLANE_SURF(pipe, plane)));
3407 }
3408 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3409}
3410
3411static bool
3412skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3413 const struct skl_ddb_allocation *new,
3414 enum pipe pipe)
3415{
3416 uint16_t old_size, new_size;
3417
3418 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3419 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3420
3421 return old_size != new_size &&
3422 new->pipe[pipe].start >= old->pipe[pipe].start &&
3423 new->pipe[pipe].end <= old->pipe[pipe].end;
3424}
3425
3426static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3427 struct skl_wm_values *new_values)
3428{
3429 struct drm_device *dev = dev_priv->dev;
3430 struct skl_ddb_allocation *cur_ddb, *new_ddb;
c929cb45 3431 bool reallocated[I915_MAX_PIPES] = {};
0e8fb7ba
DL		 3432 struct intel_crtc *crtc;
3433 enum pipe pipe;
3434
3435 new_ddb = &new_values->ddb;
3436 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3437
3438 /*
3439 * First pass: flush the pipes with the new allocation contained into
3440 * the old space.
3441 *
3442 * We'll wait for the vblank on those pipes to ensure we can safely
3443 * re-allocate the freed space without this pipe fetching from it.
3444 */
3445 for_each_intel_crtc(dev, crtc) {
3446 if (!crtc->active)
3447 continue;
3448
3449 pipe = crtc->pipe;
3450
3451 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3452 continue;
3453
d21b795c 3454 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3455 intel_wait_for_vblank(dev, pipe);
3456
3457 reallocated[pipe] = true;
3458 }
3459
3460
3461 /*
3462 * Second pass: flush the pipes that are having their allocation
3463 * reduced, but overlapping with a previous allocation.
3464 *
3465 * Here as well we need to wait for the vblank to make sure the freed
3466 * space is not used anymore.
3467 */
3468 for_each_intel_crtc(dev, crtc) {
3469 if (!crtc->active)
3470 continue;
3471
3472 pipe = crtc->pipe;
3473
3474 if (reallocated[pipe])
3475 continue;
3476
3477 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3478 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3479 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3480 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3481 reallocated[pipe] = true;
0e8fb7ba 3482 }
0e8fb7ba
DL		 3483 }
3484
3485 /*
3486 * Third pass: flush the pipes that got more space allocated.
3487 *
3488 * We don't need to actively wait for the update here, next vblank
3489 * will just get more DDB space with the correct WM values.
3490 */
3491 for_each_intel_crtc(dev, crtc) {
3492 if (!crtc->active)
3493 continue;
3494
3495 pipe = crtc->pipe;
3496
3497 /*
3498 * At this point, only the pipes more space than before are
3499 * left to re-allocate.
3500 */
3501 if (reallocated[pipe])
3502 continue;
3503
d21b795c 3504 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3505 }
3506}
3507
2d41c0b5 3508static bool skl_update_pipe_wm(struct drm_crtc *crtc,
2d41c0b5
PB		 3509 struct skl_ddb_allocation *ddb, /* out */
3510 struct skl_pipe_wm *pipe_wm /* out */)
3511{
3512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3513 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
2d41c0b5 3514
aa363136 3515 skl_allocate_pipe_ddb(cstate, ddb);
024c9045 3516 skl_compute_pipe_wm(cstate, ddb, pipe_wm);
2d41c0b5 3517
4e0963c7 3518 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
2d41c0b5
PB		 3519 return false;
3520
4e0963c7 3521 intel_crtc->wm.active.skl = *pipe_wm;
2cd601c6 3522
2d41c0b5
PB		 3523 return true;
3524}
3525
3526static void skl_update_other_pipe_wm(struct drm_device *dev,
3527 struct drm_crtc *crtc,
2d41c0b5
PB		 3528 struct skl_wm_values *r)
3529{
3530 struct intel_crtc *intel_crtc;
3531 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3532
3533 /*
3534 * If the WM update hasn't changed the allocation for this_crtc (the
3535 * crtc we are currently computing the new WM values for), other
3536 * enabled crtcs will keep the same allocation and we don't need to
3537 * recompute anything for them.
3538 */
3539 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3540 return;
3541
3542 /*
3543 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3544 * other active pipes need new DDB allocation and WM values.
3545 */
19c8054c 3546 for_each_intel_crtc(dev, intel_crtc) {
2d41c0b5
PB		 3547 struct skl_pipe_wm pipe_wm = {};
3548 bool wm_changed;
3549
3550 if (this_crtc->pipe == intel_crtc->pipe)
3551 continue;
3552
3553 if (!intel_crtc->active)
3554 continue;
3555
aa363136 3556 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
2d41c0b5
PB		 3557 &r->ddb, &pipe_wm);
3558
3559 /*
3560 * If we end up re-computing the other pipe WM values, it's
3561 * because it was really needed, so we expect the WM values to
3562 * be different.
3563 */
3564 WARN_ON(!wm_changed);
3565
024c9045 3566 skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
2d41c0b5
PB		 3567 r->dirty[intel_crtc->pipe] = true;
3568 }
3569}
3570
adda50b8
BP		 3571static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3572{
3573 watermarks->wm_linetime[pipe] = 0;
3574 memset(watermarks->plane[pipe], 0,
3575 sizeof(uint32_t) * 8 * I915_MAX_PLANES);
adda50b8
BP		 3576 memset(watermarks->plane_trans[pipe],
3577 0, sizeof(uint32_t) * I915_MAX_PLANES);
4969d33e 3578 watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
adda50b8
BP		 3579
3580 /* Clear ddb entries for pipe */
3581 memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3582 memset(&watermarks->ddb.plane[pipe], 0,
3583 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3584 memset(&watermarks->ddb.y_plane[pipe], 0,
3585 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
4969d33e
MR		 3586 memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3587 sizeof(struct skl_ddb_entry));
adda50b8
BP		 3588
3589}
3590
2d41c0b5
PB		 3591static void skl_update_wm(struct drm_crtc *crtc)
3592{
3593 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3594 struct drm_device *dev = crtc->dev;
3595 struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5 3596 struct skl_wm_values *results = &dev_priv->wm.skl_results;
4e0963c7
MR		 3597 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3598 struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl;
2d41c0b5 3599
adda50b8
BP		 3600
3601 /* Clear all dirty flags */
3602 memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3603
3604 skl_clear_wm(results, intel_crtc->pipe);
2d41c0b5 3605
aa363136 3606 if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm))
2d41c0b5
PB		 3607 return;
3608
4e0963c7 3609 skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
2d41c0b5
PB		 3610 results->dirty[intel_crtc->pipe] = true;
3611
aa363136 3612 skl_update_other_pipe_wm(dev, crtc, results);
2d41c0b5 3613 skl_write_wm_values(dev_priv, results);
0e8fb7ba 3614 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 3615
3616 /* store the new configuration */
3617 dev_priv->wm.skl_hw = *results;
2d41c0b5
PB		 3618}
3619
d93c0372 3620static void ilk_program_watermarks(struct intel_crtc_state *cstate)
801bcfff 3621{
d93c0372
MR		 3622 struct drm_crtc *crtc = cstate->base.crtc;
3623 struct drm_device *dev = crtc->dev;
3624 struct drm_i915_private *dev_priv = to_i915(dev);
b9d5c839 3625 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 3626 struct ilk_wm_maximums max;
aa363136 3627 struct intel_wm_config *config = &dev_priv->wm.config;
820c1980 3628 struct ilk_wm_values results = {};
77c122bc 3629 enum intel_ddb_partitioning partitioning;
261a27d1 3630
aa363136
MR		 3631 ilk_compute_wm_maximums(dev, 1, config, INTEL_DDB_PART_1_2, &max);
3632 ilk_wm_merge(dev, config, &max, &lp_wm_1_2);
a485bfb8
VS		 3633
3634 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1 3635 if (INTEL_INFO(dev)->gen >= 7 &&
aa363136
MR		 3636 config->num_pipes_active == 1 && config->sprites_enabled) {
3637 ilk_compute_wm_maximums(dev, 1, config, INTEL_DDB_PART_5_6, &max);
3638 ilk_wm_merge(dev, config, &max, &lp_wm_5_6);
0362c781 3639
820c1980 3640 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 3641 } else {
198a1e9b 3642 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 3643 }
3644
198a1e9b 3645 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 3646 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 3647
820c1980 3648 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 3649
820c1980 3650 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 3651}
3652
b9d5c839
VS		 3653static void ilk_update_wm(struct drm_crtc *crtc)
3654{
b9d5c839
VS		 3655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3656 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
b9d5c839
VS		 3657
3658 WARN_ON(cstate->base.active != intel_crtc->active);
3659
3660 /*
3661 * IVB workaround: must disable low power watermarks for at least
3662 * one frame before enabling scaling. LP watermarks can be re-enabled
3663 * when scaling is disabled.
3664 *
3665 * WaCxSRDisabledForSpriteScaling:ivb
3666 */
3667 if (cstate->disable_lp_wm) {
3668 ilk_disable_lp_wm(crtc->dev);
3669 intel_wait_for_vblank(crtc->dev, intel_crtc->pipe);
3670 }
3671
4e0963c7 3672 intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
b9d5c839 3673
d93c0372 3674 ilk_program_watermarks(cstate);
b9d5c839
VS		 3675}
3676
3078999f
PB		 3677static void skl_pipe_wm_active_state(uint32_t val,
3678 struct skl_pipe_wm *active,
3679 bool is_transwm,
3680 bool is_cursor,
3681 int i,
3682 int level)
3683{
3684 bool is_enabled = (val & PLANE_WM_EN) != 0;
3685
3686 if (!is_transwm) {
3687 if (!is_cursor) {
3688 active->wm[level].plane_en[i] = is_enabled;
3689 active->wm[level].plane_res_b[i] =
3690 val & PLANE_WM_BLOCKS_MASK;
3691 active->wm[level].plane_res_l[i] =
3692 (val >> PLANE_WM_LINES_SHIFT) &
3693 PLANE_WM_LINES_MASK;
3694 } else {
4969d33e
MR		 3695 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3696 active->wm[level].plane_res_b[PLANE_CURSOR] =
3078999f 3697 val & PLANE_WM_BLOCKS_MASK;
4969d33e 3698 active->wm[level].plane_res_l[PLANE_CURSOR] =
3078999f
PB		 3699 (val >> PLANE_WM_LINES_SHIFT) &
3700 PLANE_WM_LINES_MASK;
3701 }
3702 } else {
3703 if (!is_cursor) {
3704 active->trans_wm.plane_en[i] = is_enabled;
3705 active->trans_wm.plane_res_b[i] =
3706 val & PLANE_WM_BLOCKS_MASK;
3707 active->trans_wm.plane_res_l[i] =
3708 (val >> PLANE_WM_LINES_SHIFT) &
3709 PLANE_WM_LINES_MASK;
3710 } else {
4969d33e
MR		 3711 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3712 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3078999f 3713 val & PLANE_WM_BLOCKS_MASK;
4969d33e 3714 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3078999f
PB		 3715 (val >> PLANE_WM_LINES_SHIFT) &
3716 PLANE_WM_LINES_MASK;
3717 }
3718 }
3719}
3720
3721static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3722{
3723 struct drm_device *dev = crtc->dev;
3724 struct drm_i915_private *dev_priv = dev->dev_private;
3725 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3726 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7
MR		 3727 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3728 struct skl_pipe_wm *active = &cstate->wm.optimal.skl;
3078999f
PB		 3729 enum pipe pipe = intel_crtc->pipe;
3730 int level, i, max_level;
3731 uint32_t temp;
3732
3733 max_level = ilk_wm_max_level(dev);
3734
3735 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3736
3737 for (level = 0; level <= max_level; level++) {
3738 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3739 hw->plane[pipe][i][level] =
3740 I915_READ(PLANE_WM(pipe, i, level));
4969d33e 3741 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3078999f
PB		 3742 }
3743
3744 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3745 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4969d33e 3746 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3078999f 3747
3ef00284 3748 if (!intel_crtc->active)
3078999f
PB		 3749 return;
3750
3751 hw->dirty[pipe] = true;
3752
3753 active->linetime = hw->wm_linetime[pipe];
3754
3755 for (level = 0; level <= max_level; level++) {
3756 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3757 temp = hw->plane[pipe][i][level];
3758 skl_pipe_wm_active_state(temp, active, false,
3759 false, i, level);
3760 }
4969d33e 3761 temp = hw->plane[pipe][PLANE_CURSOR][level];
3078999f
PB		 3762 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3763 }
3764
3765 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3766 temp = hw->plane_trans[pipe][i];
3767 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3768 }
3769
4969d33e 3770 temp = hw->plane_trans[pipe][PLANE_CURSOR];
3078999f 3771 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4e0963c7
MR		 3772
3773 intel_crtc->wm.active.skl = *active;
3078999f
PB		 3774}
3775
3776void skl_wm_get_hw_state(struct drm_device *dev)
3777{
a269c583
DL		 3778 struct drm_i915_private *dev_priv = dev->dev_private;
3779 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 3780 struct drm_crtc *crtc;
3781
a269c583 3782 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 3783 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3784 skl_pipe_wm_get_hw_state(crtc);
3785}
3786
243e6a44
VS		 3787static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3788{
3789 struct drm_device *dev = crtc->dev;
3790 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3791 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 3792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7
MR		 3793 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3794 struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
243e6a44 3795 enum pipe pipe = intel_crtc->pipe;
f0f59a00 3796 static const i915_reg_t wm0_pipe_reg[] = {
243e6a44
VS		 3797 [PIPE_A] = WM0_PIPEA_ILK,
3798 [PIPE_B] = WM0_PIPEB_ILK,
3799 [PIPE_C] = WM0_PIPEC_IVB,
3800 };
3801
3802 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 3803 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 3804 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 3805
3ef00284 3806 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 3807
3808 if (active->pipe_enabled) {
243e6a44
VS		 3809 u32 tmp = hw->wm_pipe[pipe];
3810
3811 /*
3812 * For active pipes LP0 watermark is marked as
3813 * enabled, and LP1+ watermaks as disabled since
3814 * we can't really reverse compute them in case
3815 * multiple pipes are active.
3816 */
3817 active->wm[0].enable = true;
3818 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3819 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3820 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3821 active->linetime = hw->wm_linetime[pipe];
3822 } else {
3823 int level, max_level = ilk_wm_max_level(dev);
3824
3825 /*
3826 * For inactive pipes, all watermark levels
3827 * should be marked as enabled but zeroed,
3828 * which is what we'd compute them to.
3829 */
3830 for (level = 0; level <= max_level; level++)
3831 active->wm[level].enable = true;
3832 }
4e0963c7
MR		 3833
3834 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 3835}
3836
6eb1a681
VS		 3837#define _FW_WM(value, plane) \
3838 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3839#define _FW_WM_VLV(value, plane) \
3840 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3841
3842static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3843 struct vlv_wm_values *wm)
3844{
3845 enum pipe pipe;
3846 uint32_t tmp;
3847
3848 for_each_pipe(dev_priv, pipe) {
3849 tmp = I915_READ(VLV_DDL(pipe));
3850
3851 wm->ddl[pipe].primary =
3852 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3853 wm->ddl[pipe].cursor =
3854 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3855 wm->ddl[pipe].sprite[0] =
3856 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3857 wm->ddl[pipe].sprite[1] =
3858 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3859 }
3860
3861 tmp = I915_READ(DSPFW1);
3862 wm->sr.plane = _FW_WM(tmp, SR);
3863 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3864 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3865 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3866
3867 tmp = I915_READ(DSPFW2);
3868 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3869 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3870 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3871
3872 tmp = I915_READ(DSPFW3);
3873 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3874
3875 if (IS_CHERRYVIEW(dev_priv)) {
3876 tmp = I915_READ(DSPFW7_CHV);
3877 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3878 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3879
3880 tmp = I915_READ(DSPFW8_CHV);
3881 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3882 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
3883
3884 tmp = I915_READ(DSPFW9_CHV);
3885 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
3886 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
3887
3888 tmp = I915_READ(DSPHOWM);
3889 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3890 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
3891 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
3892 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
3893 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3894 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3895 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3896 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3897 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3898 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3899 } else {
3900 tmp = I915_READ(DSPFW7);
3901 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3902 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3903
3904 tmp = I915_READ(DSPHOWM);
3905 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3906 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3907 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3908 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3909 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3910 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3911 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3912 }
3913}
3914
3915#undef _FW_WM
3916#undef _FW_WM_VLV
3917
3918void vlv_wm_get_hw_state(struct drm_device *dev)
3919{
3920 struct drm_i915_private *dev_priv = to_i915(dev);
3921 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
3922 struct intel_plane *plane;
3923 enum pipe pipe;
3924 u32 val;
3925
3926 vlv_read_wm_values(dev_priv, wm);
3927
3928 for_each_intel_plane(dev, plane) {
3929 switch (plane->base.type) {
3930 int sprite;
3931 case DRM_PLANE_TYPE_CURSOR:
3932 plane->wm.fifo_size = 63;
3933 break;
3934 case DRM_PLANE_TYPE_PRIMARY:
3935 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
3936 break;
3937 case DRM_PLANE_TYPE_OVERLAY:
3938 sprite = plane->plane;
3939 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
3940 break;
3941 }
3942 }
3943
3944 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
3945 wm->level = VLV_WM_LEVEL_PM2;
3946
3947 if (IS_CHERRYVIEW(dev_priv)) {
3948 mutex_lock(&dev_priv->rps.hw_lock);
3949
3950 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
3951 if (val & DSP_MAXFIFO_PM5_ENABLE)
3952 wm->level = VLV_WM_LEVEL_PM5;
3953
58590c14
VS		 3954 /*
3955 * If DDR DVFS is disabled in the BIOS, Punit
3956 * will never ack the request. So if that happens
3957 * assume we don't have to enable/disable DDR DVFS
3958 * dynamically. To test that just set the REQ_ACK
3959 * bit to poke the Punit, but don't change the
3960 * HIGH/LOW bits so that we don't actually change
3961 * the current state.
3962 */
6eb1a681 3963 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 3964 val |= FORCE_DDR_FREQ_REQ_ACK;
3965 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
3966
3967 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
3968 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
3969 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
3970 "assuming DDR DVFS is disabled\n");
3971 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
3972 } else {
3973 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
3974 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
3975 wm->level = VLV_WM_LEVEL_DDR_DVFS;
3976 }
6eb1a681
VS		 3977
3978 mutex_unlock(&dev_priv->rps.hw_lock);
3979 }
3980
3981 for_each_pipe(dev_priv, pipe)
3982 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
3983 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
3984 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
3985
3986 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
3987 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
3988}
3989
243e6a44
VS		 3990void ilk_wm_get_hw_state(struct drm_device *dev)
3991{
3992 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3993 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 3994 struct drm_crtc *crtc;
3995
70e1e0ec 3996 for_each_crtc(dev, crtc)
243e6a44
VS		 3997 ilk_pipe_wm_get_hw_state(crtc);
3998
3999 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4000 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4001 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4002
4003 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4004 if (INTEL_INFO(dev)->gen >= 7) {
4005 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4006 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4007 }
243e6a44 4008
a42a5719 4009 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 4010 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4011 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4012 else if (IS_IVYBRIDGE(dev))
4013 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4014 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4015
4016 hw->enable_fbc_wm =
4017 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4018}
4019
b445e3b0
ED		 4020/**
4021 * intel_update_watermarks - update FIFO watermark values based on current modes
4022 *
4023 * Calculate watermark values for the various WM regs based on current mode
4024 * and plane configuration.
4025 *
4026 * There are several cases to deal with here:
4027 * - normal (i.e. non-self-refresh)
4028 * - self-refresh (SR) mode
4029 * - lines are large relative to FIFO size (buffer can hold up to 2)
4030 * - lines are small relative to FIFO size (buffer can hold more than 2
4031 * lines), so need to account for TLB latency
4032 *
4033 * The normal calculation is:
4034 * watermark = dotclock * bytes per pixel * latency
4035 * where latency is platform & configuration dependent (we assume pessimal
4036 * values here).
4037 *
4038 * The SR calculation is:
4039 * watermark = (trunc(latency/line time)+1) * surface width *
4040 * bytes per pixel
4041 * where
4042 * line time = htotal / dotclock
4043 * surface width = hdisplay for normal plane and 64 for cursor
4044 * and latency is assumed to be high, as above.
4045 *
4046 * The final value programmed to the register should always be rounded up,
4047 * and include an extra 2 entries to account for clock crossings.
4048 *
4049 * We don't use the sprite, so we can ignore that. And on Crestline we have
4050 * to set the non-SR watermarks to 8.
4051 */
46ba614c 4052void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4053{
46ba614c 4054 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 4055
4056 if (dev_priv->display.update_wm)
46ba614c 4057 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4058}
4059
9270388e
DV		 4060/**
4061 * Lock protecting IPS related data structures
9270388e
DV		 4062 */
4063DEFINE_SPINLOCK(mchdev_lock);
4064
4065/* Global for IPS driver to get at the current i915 device. Protected by
4066 * mchdev_lock. */
4067static struct drm_i915_private *i915_mch_dev;
4068
2b4e57bd
ED		 4069bool ironlake_set_drps(struct drm_device *dev, u8 val)
4070{
4071 struct drm_i915_private *dev_priv = dev->dev_private;
4072 u16 rgvswctl;
4073
9270388e
DV		 4074 assert_spin_locked(&mchdev_lock);
4075
2b4e57bd
ED		 4076 rgvswctl = I915_READ16(MEMSWCTL);
4077 if (rgvswctl & MEMCTL_CMD_STS) {
4078 DRM_DEBUG("gpu busy, RCS change rejected\n");
4079 return false; /* still busy with another command */
4080 }
4081
4082 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4083 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4084 I915_WRITE16(MEMSWCTL, rgvswctl);
4085 POSTING_READ16(MEMSWCTL);
4086
4087 rgvswctl |= MEMCTL_CMD_STS;
4088 I915_WRITE16(MEMSWCTL, rgvswctl);
4089
4090 return true;
4091}
4092
8090c6b9 4093static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 4094{
4095 struct drm_i915_private *dev_priv = dev->dev_private;
4096 u32 rgvmodectl = I915_READ(MEMMODECTL);
4097 u8 fmax, fmin, fstart, vstart;
4098
9270388e
DV		 4099 spin_lock_irq(&mchdev_lock);
4100
2b4e57bd
ED		 4101 /* Enable temp reporting */
4102 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4103 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4104
4105 /* 100ms RC evaluation intervals */
4106 I915_WRITE(RCUPEI, 100000);
4107 I915_WRITE(RCDNEI, 100000);
4108
4109 /* Set max/min thresholds to 90ms and 80ms respectively */
4110 I915_WRITE(RCBMAXAVG, 90000);
4111 I915_WRITE(RCBMINAVG, 80000);
4112
4113 I915_WRITE(MEMIHYST, 1);
4114
4115 /* Set up min, max, and cur for interrupt handling */
4116 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4117 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4118 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4119 MEMMODE_FSTART_SHIFT;
4120
616847e7 4121 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4122 PXVFREQ_PX_SHIFT;
4123
20e4d407
DV		 4124 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4125 dev_priv->ips.fstart = fstart;
2b4e57bd 4126
20e4d407
DV		 4127 dev_priv->ips.max_delay = fstart;
4128 dev_priv->ips.min_delay = fmin;
4129 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4130
4131 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4132 fmax, fmin, fstart);
4133
4134 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4135
4136 /*
4137 * Interrupts will be enabled in ironlake_irq_postinstall
4138 */
4139
4140 I915_WRITE(VIDSTART, vstart);
4141 POSTING_READ(VIDSTART);
4142
4143 rgvmodectl |= MEMMODE_SWMODE_EN;
4144 I915_WRITE(MEMMODECTL, rgvmodectl);
4145
9270388e 4146 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4147 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4148 mdelay(1);
2b4e57bd
ED		 4149
4150 ironlake_set_drps(dev, fstart);
4151
7d81c3e0
VS		 4152 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4153 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4154 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4155 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4156 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4157
4158 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4159}
4160
8090c6b9 4161static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 4162{
4163 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 4164 u16 rgvswctl;
4165
4166 spin_lock_irq(&mchdev_lock);
4167
4168 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4169
4170 /* Ack interrupts, disable EFC interrupt */
4171 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4172 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4173 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4174 I915_WRITE(DEIIR, DE_PCU_EVENT);
4175 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4176
4177 /* Go back to the starting frequency */
20e4d407 4178 ironlake_set_drps(dev, dev_priv->ips.fstart);
dd92d8de 4179 mdelay(1);
2b4e57bd
ED		 4180 rgvswctl |= MEMCTL_CMD_STS;
4181 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4182 mdelay(1);
2b4e57bd 4183
9270388e 4184 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4185}
4186
acbe9475
DV		 4187/* There's a funny hw issue where the hw returns all 0 when reading from
4188 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4189 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4190 * all limits and the gpu stuck at whatever frequency it is at atm).
4191 */
74ef1173 4192static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4193{
7b9e0ae6 4194 u32 limits;
2b4e57bd 4195
20b46e59
DV		 4196 /* Only set the down limit when we've reached the lowest level to avoid
4197 * getting more interrupts, otherwise leave this clear. This prevents a
4198 * race in the hw when coming out of rc6: There's a tiny window where
4199 * the hw runs at the minimal clock before selecting the desired
4200 * frequency, if the down threshold expires in that window we will not
4201 * receive a down interrupt. */
74ef1173
AG		 4202 if (IS_GEN9(dev_priv->dev)) {
4203 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4204 if (val <= dev_priv->rps.min_freq_softlimit)
4205 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4206 } else {
4207 limits = dev_priv->rps.max_freq_softlimit << 24;
4208 if (val <= dev_priv->rps.min_freq_softlimit)
4209 limits |= dev_priv->rps.min_freq_softlimit << 16;
4210 }
20b46e59
DV		 4211
4212 return limits;
4213}
4214
dd75fdc8
CW		 4215static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4216{
4217 int new_power;
8a586437
AG		 4218 u32 threshold_up = 0, threshold_down = 0; /* in % */
4219 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4220
4221 new_power = dev_priv->rps.power;
4222 switch (dev_priv->rps.power) {
4223 case LOW_POWER:
b39fb297 4224 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4225 new_power = BETWEEN;
4226 break;
4227
4228 case BETWEEN:
b39fb297 4229 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 4230 new_power = LOW_POWER;
b39fb297 4231 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4232 new_power = HIGH_POWER;
4233 break;
4234
4235 case HIGH_POWER:
b39fb297 4236 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4237 new_power = BETWEEN;
4238 break;
4239 }
4240 /* Max/min bins are special */
aed242ff 4241 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4242 new_power = LOW_POWER;
aed242ff 4243 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4244 new_power = HIGH_POWER;
4245 if (new_power == dev_priv->rps.power)
4246 return;
4247
4248 /* Note the units here are not exactly 1us, but 1280ns. */
4249 switch (new_power) {
4250 case LOW_POWER:
4251 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4252 ei_up = 16000;
4253 threshold_up = 95;
dd75fdc8
CW		 4254
4255 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4256 ei_down = 32000;
4257 threshold_down = 85;
dd75fdc8
CW		 4258 break;
4259
4260 case BETWEEN:
4261 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4262 ei_up = 13000;
4263 threshold_up = 90;
dd75fdc8
CW		 4264
4265 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4266 ei_down = 32000;
4267 threshold_down = 75;
dd75fdc8
CW		 4268 break;
4269
4270 case HIGH_POWER:
4271 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4272 ei_up = 10000;
4273 threshold_up = 85;
dd75fdc8
CW		 4274
4275 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4276 ei_down = 32000;
4277 threshold_down = 60;
dd75fdc8
CW		 4278 break;
4279 }
4280
8a586437
AG		 4281 I915_WRITE(GEN6_RP_UP_EI,
4282 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4283 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4284 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4285
4286 I915_WRITE(GEN6_RP_DOWN_EI,
4287 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4288 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4289 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4290
4291 I915_WRITE(GEN6_RP_CONTROL,
4292 GEN6_RP_MEDIA_TURBO |
4293 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4294 GEN6_RP_MEDIA_IS_GFX |
4295 GEN6_RP_ENABLE |
4296 GEN6_RP_UP_BUSY_AVG |
4297 GEN6_RP_DOWN_IDLE_AVG);
4298
dd75fdc8 4299 dev_priv->rps.power = new_power;
8fb55197
CW		 4300 dev_priv->rps.up_threshold = threshold_up;
4301 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4302 dev_priv->rps.last_adj = 0;
4303}
4304
2876ce73
CW		 4305static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4306{
4307 u32 mask = 0;
4308
4309 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4310 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4311 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4312 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4313
7b3c29f6
CW		 4314 mask &= dev_priv->pm_rps_events;
4315
59d02a1f 4316 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4317}
4318
b8a5ff8d
JM		 4319/* gen6_set_rps is called to update the frequency request, but should also be
4320 * called when the range (min_delay and max_delay) is modified so that we can
4321 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
ffe02b40 4322static void gen6_set_rps(struct drm_device *dev, u8 val)
20b46e59
DV		 4323{
4324 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 4325
23eafea6 4326 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
e87a005d 4327 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
23eafea6
SAK		 4328 return;
4329
4fc688ce 4330 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4331 WARN_ON(val > dev_priv->rps.max_freq);
4332 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4333
eb64cad1
CW		 4334 /* min/max delay may still have been modified so be sure to
4335 * write the limits value.
4336 */
4337 if (val != dev_priv->rps.cur_freq) {
4338 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4339
5704195c
AG		 4340 if (IS_GEN9(dev))
4341 I915_WRITE(GEN6_RPNSWREQ,
4342 GEN9_FREQUENCY(val));
4343 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 4344 I915_WRITE(GEN6_RPNSWREQ,
4345 HSW_FREQUENCY(val));
4346 else
4347 I915_WRITE(GEN6_RPNSWREQ,
4348 GEN6_FREQUENCY(val) |
4349 GEN6_OFFSET(0) |
4350 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4351 }
7b9e0ae6 4352
7b9e0ae6
CW		 4353 /* Make sure we continue to get interrupts
4354 * until we hit the minimum or maximum frequencies.
4355 */
74ef1173 4356 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4357 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4358
d5570a72
BW		 4359 POSTING_READ(GEN6_RPNSWREQ);
4360
b39fb297 4361 dev_priv->rps.cur_freq = val;
0f94592e 4362 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
2b4e57bd
ED		 4363}
4364
ffe02b40
VS		 4365static void valleyview_set_rps(struct drm_device *dev, u8 val)
4366{
4367 struct drm_i915_private *dev_priv = dev->dev_private;
4368
4369 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4370 WARN_ON(val > dev_priv->rps.max_freq);
4371 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40
VS		 4372
4373 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4374 "Odd GPU freq value\n"))
4375 val &= ~1;
4376
cd25dd5b
D		 4377 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4378
8fb55197 4379 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4380 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4381 if (!IS_CHERRYVIEW(dev_priv))
4382 gen6_set_rps_thresholds(dev_priv, val);
4383 }
ffe02b40 4384
ffe02b40
VS		 4385 dev_priv->rps.cur_freq = val;
4386 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4387}
4388
a7f6e231 4389/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4390 *
4391 * * If Gfx is Idle, then
a7f6e231
D		 4392 * 1. Forcewake Media well.
4393 * 2. Request idle freq.
4394 * 3. Release Forcewake of Media well.
76c3552f
D		 4395*/
4396static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4397{
aed242ff 4398 u32 val = dev_priv->rps.idle_freq;
5549d25f 4399
aed242ff 4400 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4401 return;
4402
a7f6e231
D		 4403 /* Wake up the media well, as that takes a lot less
4404 * power than the Render well. */
4405 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4406 valleyview_set_rps(dev_priv->dev, val);
4407 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 4408}
4409
43cf3bf0
CW		 4410void gen6_rps_busy(struct drm_i915_private *dev_priv)
4411{
4412 mutex_lock(&dev_priv->rps.hw_lock);
4413 if (dev_priv->rps.enabled) {
4414 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4415 gen6_rps_reset_ei(dev_priv);
4416 I915_WRITE(GEN6_PMINTRMSK,
4417 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4418 }
4419 mutex_unlock(&dev_priv->rps.hw_lock);
4420}
4421
b29c19b6
CW		 4422void gen6_rps_idle(struct drm_i915_private *dev_priv)
4423{
691bb717
DL		 4424 struct drm_device *dev = dev_priv->dev;
4425
b29c19b6 4426 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4427 if (dev_priv->rps.enabled) {
666a4537 4428 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
76c3552f 4429 vlv_set_rps_idle(dev_priv);
7526ed79 4430 else
aed242ff 4431 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
c0951f0c 4432 dev_priv->rps.last_adj = 0;
43cf3bf0 4433 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
c0951f0c 4434 }
8d3afd7d 4435 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 4436
8d3afd7d 4437 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 4438 while (!list_empty(&dev_priv->rps.clients))
4439 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 4440 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4441}
4442
1854d5ca 4443void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 4444 struct intel_rps_client *rps,
4445 unsigned long submitted)
b29c19b6 4446{
8d3afd7d
CW		 4447 /* This is intentionally racy! We peek at the state here, then
4448 * validate inside the RPS worker.
4449 */
4450 if (!(dev_priv->mm.busy &&
4451 dev_priv->rps.enabled &&
4452 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4453 return;
43cf3bf0 4454
e61b9958
CW		 4455 /* Force a RPS boost (and don't count it against the client) if
4456 * the GPU is severely congested.
4457 */
d0bc54f2 4458 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 4459 rps = NULL;
4460
8d3afd7d
CW		 4461 spin_lock(&dev_priv->rps.client_lock);
4462 if (rps == NULL || list_empty(&rps->link)) {
4463 spin_lock_irq(&dev_priv->irq_lock);
4464 if (dev_priv->rps.interrupts_enabled) {
4465 dev_priv->rps.client_boost = true;
4466 queue_work(dev_priv->wq, &dev_priv->rps.work);
4467 }
4468 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 4469
2e1b8730
CW		 4470 if (rps != NULL) {
4471 list_add(&rps->link, &dev_priv->rps.clients);
4472 rps->boosts++;
1854d5ca
CW		 4473 } else
4474 dev_priv->rps.boosts++;
c0951f0c 4475 }
8d3afd7d 4476 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4477}
4478
ffe02b40 4479void intel_set_rps(struct drm_device *dev, u8 val)
0a073b84 4480{
666a4537 4481 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
ffe02b40
VS		 4482 valleyview_set_rps(dev, val);
4483 else
4484 gen6_set_rps(dev, val);
0a073b84
JB		 4485}
4486
20e49366
ZW		 4487static void gen9_disable_rps(struct drm_device *dev)
4488{
4489 struct drm_i915_private *dev_priv = dev->dev_private;
4490
4491 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4492 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 4493}
4494
44fc7d5c 4495static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 4496{
4497 struct drm_i915_private *dev_priv = dev->dev_private;
4498
4499 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4500 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
44fc7d5c
DV		 4501}
4502
38807746
D		 4503static void cherryview_disable_rps(struct drm_device *dev)
4504{
4505 struct drm_i915_private *dev_priv = dev->dev_private;
4506
4507 I915_WRITE(GEN6_RC_CONTROL, 0);
4508}
4509
44fc7d5c
DV		 4510static void valleyview_disable_rps(struct drm_device *dev)
4511{
4512 struct drm_i915_private *dev_priv = dev->dev_private;
4513
98a2e5f9
D		 4514 /* we're doing forcewake before Disabling RC6,
4515 * This what the BIOS expects when going into suspend */
59bad947 4516 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 4517
44fc7d5c 4518 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4519
59bad947 4520 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 4521}
4522
dc39fff7
BW		 4523static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4524{
666a4537 4525 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
91ca689a
ID		 4526 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4527 mode = GEN6_RC_CTL_RC6_ENABLE;
4528 else
4529 mode = 0;
4530 }
58abf1da
RV		 4531 if (HAS_RC6p(dev))
4532 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4533 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4534 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4535 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4536
4537 else
4538 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4539 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
dc39fff7
BW		 4540}
4541
e6069ca8 4542static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 4543{
e7d66d89
DV		 4544 /* No RC6 before Ironlake and code is gone for ilk. */
4545 if (INTEL_INFO(dev)->gen < 6)
e6069ca8
ID		 4546 return 0;
4547
456470eb 4548 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 4549 if (enable_rc6 >= 0) {
4550 int mask;
4551
58abf1da 4552 if (HAS_RC6p(dev))
e6069ca8
ID		 4553 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4554 INTEL_RC6pp_ENABLE;
4555 else
4556 mask = INTEL_RC6_ENABLE;
4557
4558 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 4559 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4560 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 4561
4562 return enable_rc6 & mask;
4563 }
2b4e57bd 4564
8bade1ad 4565 if (IS_IVYBRIDGE(dev))
cca84a1f 4566 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 4567
4568 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 4569}
4570
e6069ca8
ID		 4571int intel_enable_rc6(const struct drm_device *dev)
4572{
4573 return i915.enable_rc6;
4574}
4575
93ee2920 4576static void gen6_init_rps_frequencies(struct drm_device *dev)
3280e8b0 4577{
93ee2920
TR		 4578 struct drm_i915_private *dev_priv = dev->dev_private;
4579 uint32_t rp_state_cap;
4580 u32 ddcc_status = 0;
4581 int ret;
4582
3280e8b0
BW		 4583 /* All of these values are in units of 50MHz */
4584 dev_priv->rps.cur_freq = 0;
93ee2920 4585 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
35040562
BP		 4586 if (IS_BROXTON(dev)) {
4587 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4588 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4589 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4590 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
4591 } else {
4592 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4593 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4594 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4595 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4596 }
4597
3280e8b0
BW		 4598 /* hw_max = RP0 until we check for overclocking */
4599 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4600
93ee2920 4601 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
ef11bdb3
RV		 4602 if (IS_HASWELL(dev) || IS_BROADWELL(dev) ||
4603 IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
93ee2920
TR		 4604 ret = sandybridge_pcode_read(dev_priv,
4605 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4606 &ddcc_status);
4607 if (0 == ret)
4608 dev_priv->rps.efficient_freq =
46efa4ab
TR		 4609 clamp_t(u8,
4610 ((ddcc_status >> 8) & 0xff),
4611 dev_priv->rps.min_freq,
4612 dev_priv->rps.max_freq);
93ee2920
TR		 4613 }
4614
ef11bdb3 4615 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
c5e0688c
AG		 4616 /* Store the frequency values in 16.66 MHZ units, which is
4617 the natural hardware unit for SKL */
4618 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4619 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4620 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4621 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4622 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4623 }
4624
aed242ff
CW		 4625 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4626
3280e8b0
BW		 4627 /* Preserve min/max settings in case of re-init */
4628 if (dev_priv->rps.max_freq_softlimit == 0)
4629 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4630
93ee2920
TR		 4631 if (dev_priv->rps.min_freq_softlimit == 0) {
4632 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4633 dev_priv->rps.min_freq_softlimit =
813b5e69
VS		 4634 max_t(int, dev_priv->rps.efficient_freq,
4635 intel_freq_opcode(dev_priv, 450));
93ee2920
TR		 4636 else
4637 dev_priv->rps.min_freq_softlimit =
4638 dev_priv->rps.min_freq;
4639 }
3280e8b0
BW		 4640}
4641
b6fef0ef 4642/* See the Gen9_GT_PM_Programming_Guide doc for the below */
20e49366 4643static void gen9_enable_rps(struct drm_device *dev)
b6fef0ef
JB		 4644{
4645 struct drm_i915_private *dev_priv = dev->dev_private;
4646
4647 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4648
ba1c554c
DL		 4649 gen6_init_rps_frequencies(dev);
4650
23eafea6 4651 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
e87a005d 4652 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
23eafea6
SAK		 4653 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4654 return;
4655 }
4656
0beb059a
AG		 4657 /* Program defaults and thresholds for RPS*/
4658 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4659 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4660
4661 /* 1 second timeout*/
4662 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4663 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4664
b6fef0ef 4665 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 4666
0beb059a
AG		 4667 /* Leaning on the below call to gen6_set_rps to program/setup the
4668 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4669 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4670 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4671 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
b6fef0ef
JB		 4672
4673 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4674}
4675
4676static void gen9_enable_rc6(struct drm_device *dev)
20e49366
ZW		 4677{
4678 struct drm_i915_private *dev_priv = dev->dev_private;
4679 struct intel_engine_cs *ring;
4680 uint32_t rc6_mask = 0;
4681 int unused;
4682
4683 /* 1a: Software RC state - RC0 */
4684 I915_WRITE(GEN6_RC_STATE, 0);
4685
4686 /* 1b: Get forcewake during program sequence. Although the driver
4687 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4688 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4689
4690 /* 2a: Disable RC states. */
4691 I915_WRITE(GEN6_RC_CONTROL, 0);
4692
4693 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 4694
4695 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
e7674b8c 4696 if (IS_SKYLAKE(dev))
63a4dec2
SAK		 4697 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4698 else
4699 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 4700 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4701 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4702 for_each_ring(ring, dev_priv, unused)
4703 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
97c322e7
SAK		 4704
4705 if (HAS_GUC_UCODE(dev))
4706 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4707
20e49366 4708 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 4709
38c23527
ZW		 4710 /* 2c: Program Coarse Power Gating Policies. */
4711 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4712 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4713
20e49366
ZW		 4714 /* 3a: Enable RC6 */
4715 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4716 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4717 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4718 "on" : "off");
3e7732a0 4719 /* WaRsUseTimeoutMode */
e87a005d 4720 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
cbdc12a9 4721 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
3e7732a0 4722 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 4723 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4724 GEN7_RC_CTL_TO_MODE |
4725 rc6_mask);
3e7732a0
SAK		 4726 } else {
4727 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 4728 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4729 GEN6_RC_CTL_EI_MODE(1) |
4730 rc6_mask);
3e7732a0 4731 }
20e49366 4732
cb07bae0
SK		 4733 /*
4734 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 4735 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 4736 */
06e668ac 4737 if (NEEDS_WaRsDisableCoarsePowerGating(dev))
f2d2fe95
SAK		 4738 I915_WRITE(GEN9_PG_ENABLE, 0);
4739 else
4740 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4741 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 4742
59bad947 4743 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4744
4745}
4746
6edee7f3
BW		 4747static void gen8_enable_rps(struct drm_device *dev)
4748{
4749 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4750 struct intel_engine_cs *ring;
93ee2920 4751 uint32_t rc6_mask = 0;
6edee7f3
BW		 4752 int unused;
4753
4754 /* 1a: Software RC state - RC0 */
4755 I915_WRITE(GEN6_RC_STATE, 0);
4756
4757 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4758 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4759 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4760
4761 /* 2a: Disable RC states. */
4762 I915_WRITE(GEN6_RC_CONTROL, 0);
4763
93ee2920
TR		 4764 /* Initialize rps frequencies */
4765 gen6_init_rps_frequencies(dev);
6edee7f3
BW		 4766
4767 /* 2b: Program RC6 thresholds.*/
4768 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4769 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4770 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4771 for_each_ring(ring, dev_priv, unused)
4772 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4773 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 4774 if (IS_BROADWELL(dev))
4775 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4776 else
4777 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 4778
4779 /* 3: Enable RC6 */
4780 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4781 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 4782 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 4783 if (IS_BROADWELL(dev))
4784 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4785 GEN7_RC_CTL_TO_MODE |
4786 rc6_mask);
4787 else
4788 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4789 GEN6_RC_CTL_EI_MODE(1) |
4790 rc6_mask);
6edee7f3
BW		 4791
4792 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 4793 I915_WRITE(GEN6_RPNSWREQ,
4794 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4795 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4796 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 4797 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4798 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4799
4800 /* Docs recommend 900MHz, and 300 MHz respectively */
4801 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4802 dev_priv->rps.max_freq_softlimit << 24 |
4803 dev_priv->rps.min_freq_softlimit << 16);
4804
4805 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4806 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4807 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4808 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4809
4810 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 4811
4812 /* 5: Enable RPS */
7526ed79
DV		 4813 I915_WRITE(GEN6_RP_CONTROL,
4814 GEN6_RP_MEDIA_TURBO |
4815 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4816 GEN6_RP_MEDIA_IS_GFX |
4817 GEN6_RP_ENABLE |
4818 GEN6_RP_UP_BUSY_AVG |
4819 GEN6_RP_DOWN_IDLE_AVG);
4820
4821 /* 6: Ring frequency + overclocking (our driver does this later */
4822
c7f3153a 4823 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4824 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
7526ed79 4825
59bad947 4826 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4827}
4828
79f5b2c7 4829static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 4830{
79f5b2c7 4831 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4832 struct intel_engine_cs *ring;
d060c169 4833 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 4834 u32 gtfifodbg;
2b4e57bd 4835 int rc6_mode;
42c0526c 4836 int i, ret;
2b4e57bd 4837
4fc688ce 4838 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4839
2b4e57bd
ED		 4840 /* Here begins a magic sequence of register writes to enable
4841 * auto-downclocking.
4842 *
4843 * Perhaps there might be some value in exposing these to
4844 * userspace...
4845 */
4846 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 4847
4848 /* Clear the DBG now so we don't confuse earlier errors */
4849 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4850 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4851 I915_WRITE(GTFIFODBG, gtfifodbg);
4852 }
4853
59bad947 4854 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 4855
93ee2920
TR		 4856 /* Initialize rps frequencies */
4857 gen6_init_rps_frequencies(dev);
dd0a1aa1 4858
2b4e57bd
ED		 4859 /* disable the counters and set deterministic thresholds */
4860 I915_WRITE(GEN6_RC_CONTROL, 0);
4861
4862 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4863 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4864 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4865 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4866 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4867
b4519513
CW		 4868 for_each_ring(ring, dev_priv, i)
4869 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 4870
4871 I915_WRITE(GEN6_RC_SLEEP, 0);
4872 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 4873 if (IS_IVYBRIDGE(dev))
351aa566
SM		 4874 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4875 else
4876 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 4877 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 4878 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4879
5a7dc92a 4880 /* Check if we are enabling RC6 */
2b4e57bd
ED		 4881 rc6_mode = intel_enable_rc6(dev_priv->dev);
4882 if (rc6_mode & INTEL_RC6_ENABLE)
4883 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4884
5a7dc92a
ED		 4885 /* We don't use those on Haswell */
4886 if (!IS_HASWELL(dev)) {
4887 if (rc6_mode & INTEL_RC6p_ENABLE)
4888 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 4889
5a7dc92a
ED		 4890 if (rc6_mode & INTEL_RC6pp_ENABLE)
4891 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4892 }
2b4e57bd 4893
dc39fff7 4894 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 4895
4896 I915_WRITE(GEN6_RC_CONTROL,
4897 rc6_mask |
4898 GEN6_RC_CTL_EI_MODE(1) |
4899 GEN6_RC_CTL_HW_ENABLE);
4900
dd75fdc8
CW		 4901 /* Power down if completely idle for over 50ms */
4902 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 4903 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 4904
42c0526c 4905 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 4906 if (ret)
42c0526c 4907 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 4908
4909 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4910 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4911 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 4912 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 4913 (pcu_mbox & 0xff) * 50);
b39fb297 4914 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 4915 }
4916
dd75fdc8 4917 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4918 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
2b4e57bd 4919
31643d54
BW		 4920 rc6vids = 0;
4921 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4922 if (IS_GEN6(dev) && ret) {
4923 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4924 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4925 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4926 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4927 rc6vids &= 0xffff00;
4928 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4929 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4930 if (ret)
4931 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4932 }
4933
59bad947 4934 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 4935}
4936
c2bc2fc5 4937static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 4938{
79f5b2c7 4939 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 4940 int min_freq = 15;
3ebecd07
CW		 4941 unsigned int gpu_freq;
4942 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 4943 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 4944 int scaling_factor = 180;
eda79642 4945 struct cpufreq_policy *policy;
2b4e57bd 4946
4fc688ce 4947 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4948
eda79642
BW		 4949 policy = cpufreq_cpu_get(0);
4950 if (policy) {
4951 max_ia_freq = policy->cpuinfo.max_freq;
4952 cpufreq_cpu_put(policy);
4953 } else {
4954 /*
4955 * Default to measured freq if none found, PCU will ensure we
4956 * don't go over
4957 */
2b4e57bd 4958 max_ia_freq = tsc_khz;
eda79642 4959 }
2b4e57bd
ED		 4960
4961 /* Convert from kHz to MHz */
4962 max_ia_freq /= 1000;
4963
153b4b95 4964 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 4965 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4966 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 4967
ef11bdb3 4968 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4c8c7743
AG		 4969 /* Convert GT frequency to 50 HZ units */
4970 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
4971 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
4972 } else {
4973 min_gpu_freq = dev_priv->rps.min_freq;
4974 max_gpu_freq = dev_priv->rps.max_freq;
4975 }
4976
2b4e57bd
ED		 4977 /*
4978 * For each potential GPU frequency, load a ring frequency we'd like
4979 * to use for memory access. We do this by specifying the IA frequency
4980 * the PCU should use as a reference to determine the ring frequency.
4981 */
4c8c7743
AG		 4982 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
4983 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 4984 unsigned int ia_freq = 0, ring_freq = 0;
4985
ef11bdb3 4986 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4c8c7743
AG		 4987 /*
4988 * ring_freq = 2 * GT. ring_freq is in 100MHz units
4989 * No floor required for ring frequency on SKL.
4990 */
4991 ring_freq = gpu_freq;
4992 } else if (INTEL_INFO(dev)->gen >= 8) {
46c764d4
BW		 4993 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4994 ring_freq = max(min_ring_freq, gpu_freq);
4995 } else if (IS_HASWELL(dev)) {
f6aca45c 4996 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 4997 ring_freq = max(min_ring_freq, ring_freq);
4998 /* leave ia_freq as the default, chosen by cpufreq */
4999 } else {
5000 /* On older processors, there is no separate ring
5001 * clock domain, so in order to boost the bandwidth
5002 * of the ring, we need to upclock the CPU (ia_freq).
5003 *
5004 * For GPU frequencies less than 750MHz,
5005 * just use the lowest ring freq.
5006 */
5007 if (gpu_freq < min_freq)
5008 ia_freq = 800;
5009 else
5010 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5011 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5012 }
2b4e57bd 5013
42c0526c
BW		 5014 sandybridge_pcode_write(dev_priv,
5015 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5016 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5017 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5018 gpu_freq);
2b4e57bd 5019 }
2b4e57bd
ED		 5020}
5021
c2bc2fc5
ID		 5022void gen6_update_ring_freq(struct drm_device *dev)
5023{
5024 struct drm_i915_private *dev_priv = dev->dev_private;
5025
97d3308a 5026 if (!HAS_CORE_RING_FREQ(dev))
c2bc2fc5
ID		 5027 return;
5028
5029 mutex_lock(&dev_priv->rps.hw_lock);
5030 __gen6_update_ring_freq(dev);
5031 mutex_unlock(&dev_priv->rps.hw_lock);
5032}
5033
03af2045 5034static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09 5035{
095acd5f 5036 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 5037 u32 val, rp0;
5038
5b5929cb 5039 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5040
5b5929cb
JN		 5041 switch (INTEL_INFO(dev)->eu_total) {
5042 case 8:
5043 /* (2 * 4) config */
5044 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5045 break;
5046 case 12:
5047 /* (2 * 6) config */
5048 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5049 break;
5050 case 16:
5051 /* (2 * 8) config */
5052 default:
5053 /* Setting (2 * 8) Min RP0 for any other combination */
5054 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5055 break;
095acd5f 5056 }
5b5929cb
JN		 5057
5058 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5059
2b6b3a09
D		 5060 return rp0;
5061}
5062
5063static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5064{
5065 u32 val, rpe;
5066
5067 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5068 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5069
5070 return rpe;
5071}
5072
7707df4a
D		 5073static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5074{
5075 u32 val, rp1;
5076
5b5929cb
JN		 5077 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5078 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5079
7707df4a
D		 5080 return rp1;
5081}
5082
f8f2b001
D		 5083static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5084{
5085 u32 val, rp1;
5086
5087 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5088
5089 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5090
5091 return rp1;
5092}
5093
03af2045 5094static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5095{
5096 u32 val, rp0;
5097
64936258 5098 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5099
5100 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5101 /* Clamp to max */
5102 rp0 = min_t(u32, rp0, 0xea);
5103
5104 return rp0;
5105}
5106
5107static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5108{
5109 u32 val, rpe;
5110
64936258 5111 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5112 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5113 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5114 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5115
5116 return rpe;
5117}
5118
03af2045 5119static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5120{
36146035
ID		 5121 u32 val;
5122
5123 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5124 /*
5125 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5126 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5127 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5128 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5129 * to make sure it matches what Punit accepts.
5130 */
5131 return max_t(u32, val, 0xc0);
0a073b84
JB		 5132}
5133
ae48434c
ID		 5134/* Check that the pctx buffer wasn't move under us. */
5135static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5136{
5137 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5138
5139 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5140 dev_priv->vlv_pctx->stolen->start);
5141}
5142
38807746
D		 5143
5144/* Check that the pcbr address is not empty. */
5145static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5146{
5147 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5148
5149 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5150}
5151
5152static void cherryview_setup_pctx(struct drm_device *dev)
5153{
5154 struct drm_i915_private *dev_priv = dev->dev_private;
5155 unsigned long pctx_paddr, paddr;
5156 struct i915_gtt *gtt = &dev_priv->gtt;
5157 u32 pcbr;
5158 int pctx_size = 32*1024;
5159
5160 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5161
5162 pcbr = I915_READ(VLV_PCBR);
5163 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5164 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746
D		 5165 paddr = (dev_priv->mm.stolen_base +
5166 (gtt->stolen_size - pctx_size));
5167
5168 pctx_paddr = (paddr & (~4095));
5169 I915_WRITE(VLV_PCBR, pctx_paddr);
5170 }
ce611ef8
VS		 5171
5172 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5173}
5174
c9cddffc
JB		 5175static void valleyview_setup_pctx(struct drm_device *dev)
5176{
5177 struct drm_i915_private *dev_priv = dev->dev_private;
5178 struct drm_i915_gem_object *pctx;
5179 unsigned long pctx_paddr;
5180 u32 pcbr;
5181 int pctx_size = 24*1024;
5182
17b0c1f7
ID		 5183 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5184
c9cddffc
JB		 5185 pcbr = I915_READ(VLV_PCBR);
5186 if (pcbr) {
5187 /* BIOS set it up already, grab the pre-alloc'd space */
5188 int pcbr_offset;
5189
5190 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5191 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5192 pcbr_offset,
190d6cd5 5193 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5194 pctx_size);
5195 goto out;
5196 }
5197
ce611ef8
VS		 5198 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5199
c9cddffc
JB		 5200 /*
5201 * From the Gunit register HAS:
5202 * The Gfx driver is expected to program this register and ensure
5203 * proper allocation within Gfx stolen memory. For example, this
5204 * register should be programmed such than the PCBR range does not
5205 * overlap with other ranges, such as the frame buffer, protected
5206 * memory, or any other relevant ranges.
5207 */
5208 pctx = i915_gem_object_create_stolen(dev, pctx_size);
5209 if (!pctx) {
5210 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5211 return;
5212 }
5213
5214 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5215 I915_WRITE(VLV_PCBR, pctx_paddr);
5216
5217out:
ce611ef8 5218 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 5219 dev_priv->vlv_pctx = pctx;
5220}
5221
ae48434c
ID		 5222static void valleyview_cleanup_pctx(struct drm_device *dev)
5223{
5224 struct drm_i915_private *dev_priv = dev->dev_private;
5225
5226 if (WARN_ON(!dev_priv->vlv_pctx))
5227 return;
5228
5229 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5230 dev_priv->vlv_pctx = NULL;
5231}
5232
4e80519e
ID		 5233static void valleyview_init_gt_powersave(struct drm_device *dev)
5234{
5235 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5236 u32 val;
4e80519e
ID		 5237
5238 valleyview_setup_pctx(dev);
5239
5240 mutex_lock(&dev_priv->rps.hw_lock);
5241
2bb25c17
VS		 5242 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5243 switch ((val >> 6) & 3) {
5244 case 0:
5245 case 1:
5246 dev_priv->mem_freq = 800;
5247 break;
5248 case 2:
5249 dev_priv->mem_freq = 1066;
5250 break;
5251 case 3:
5252 dev_priv->mem_freq = 1333;
5253 break;
5254 }
80b83b62 5255 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5256
4e80519e
ID		 5257 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5258 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5259 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5260 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5261 dev_priv->rps.max_freq);
5262
5263 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5264 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5265 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5266 dev_priv->rps.efficient_freq);
5267
f8f2b001
D		 5268 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5269 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5270 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5271 dev_priv->rps.rp1_freq);
5272
4e80519e
ID		 5273 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5274 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5275 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e
ID		 5276 dev_priv->rps.min_freq);
5277
aed242ff
CW		 5278 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5279
4e80519e
ID		 5280 /* Preserve min/max settings in case of re-init */
5281 if (dev_priv->rps.max_freq_softlimit == 0)
5282 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5283
5284 if (dev_priv->rps.min_freq_softlimit == 0)
5285 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5286
5287 mutex_unlock(&dev_priv->rps.hw_lock);
5288}
5289
38807746
D		 5290static void cherryview_init_gt_powersave(struct drm_device *dev)
5291{
2b6b3a09 5292 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5293 u32 val;
2b6b3a09 5294
38807746 5295 cherryview_setup_pctx(dev);
2b6b3a09
D		 5296
5297 mutex_lock(&dev_priv->rps.hw_lock);
5298
a580516d 5299 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5300 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5301 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5302
2bb25c17 5303 switch ((val >> 2) & 0x7) {
2bb25c17 5304 case 3:
2bb25c17
VS		 5305 dev_priv->mem_freq = 2000;
5306 break;
bfa7df01 5307 default:
2bb25c17
VS		 5308 dev_priv->mem_freq = 1600;
5309 break;
5310 }
80b83b62 5311 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5312
2b6b3a09
D		 5313 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5314 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5315 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5316 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5317 dev_priv->rps.max_freq);
5318
5319 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5320 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5321 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5322 dev_priv->rps.efficient_freq);
5323
7707df4a
D		 5324 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5325 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5326 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5327 dev_priv->rps.rp1_freq);
5328
5b7c91b7
D		 5329 /* PUnit validated range is only [RPe, RP0] */
5330 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5331 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5332 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5333 dev_priv->rps.min_freq);
5334
1c14762d
VS		 5335 WARN_ONCE((dev_priv->rps.max_freq |
5336 dev_priv->rps.efficient_freq |
5337 dev_priv->rps.rp1_freq |
5338 dev_priv->rps.min_freq) & 1,
5339 "Odd GPU freq values\n");
5340
aed242ff
CW		 5341 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5342
2b6b3a09
D		 5343 /* Preserve min/max settings in case of re-init */
5344 if (dev_priv->rps.max_freq_softlimit == 0)
5345 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5346
5347 if (dev_priv->rps.min_freq_softlimit == 0)
5348 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5349
5350 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 5351}
5352
4e80519e
ID		 5353static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5354{
5355 valleyview_cleanup_pctx(dev);
5356}
5357
38807746
D		 5358static void cherryview_enable_rps(struct drm_device *dev)
5359{
5360 struct drm_i915_private *dev_priv = dev->dev_private;
5361 struct intel_engine_cs *ring;
2b6b3a09 5362 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5363 int i;
5364
5365 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5366
5367 gtfifodbg = I915_READ(GTFIFODBG);
5368 if (gtfifodbg) {
5369 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5370 gtfifodbg);
5371 I915_WRITE(GTFIFODBG, gtfifodbg);
5372 }
5373
5374 cherryview_check_pctx(dev_priv);
5375
5376 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5377 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5378 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5379
160614a2
VS		 5380 /* Disable RC states. */
5381 I915_WRITE(GEN6_RC_CONTROL, 0);
5382
38807746
D		 5383 /* 2a: Program RC6 thresholds.*/
5384 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5385 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5386 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5387
5388 for_each_ring(ring, dev_priv, i)
5389 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5390 I915_WRITE(GEN6_RC_SLEEP, 0);
5391
f4f71c7d
D		 5392 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5393 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 5394
5395 /* allows RC6 residency counter to work */
5396 I915_WRITE(VLV_COUNTER_CONTROL,
5397 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5398 VLV_MEDIA_RC6_COUNT_EN |
5399 VLV_RENDER_RC6_COUNT_EN));
5400
5401 /* For now we assume BIOS is allocating and populating the PCBR */
5402 pcbr = I915_READ(VLV_PCBR);
5403
38807746
D		 5404 /* 3: Enable RC6 */
5405 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5406 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5407 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 5408
5409 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5410
2b6b3a09 5411 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5412 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 5413 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5414 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5415 I915_WRITE(GEN6_RP_UP_EI, 66000);
5416 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5417
5418 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5419
5420 /* 5: Enable RPS */
5421 I915_WRITE(GEN6_RP_CONTROL,
5422 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 5423 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 5424 GEN6_RP_ENABLE |
5425 GEN6_RP_UP_BUSY_AVG |
5426 GEN6_RP_DOWN_IDLE_AVG);
5427
3ef62342
D		 5428 /* Setting Fixed Bias */
5429 val = VLV_OVERRIDE_EN |
5430 VLV_SOC_TDP_EN |
5431 CHV_BIAS_CPU_50_SOC_50;
5432 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5433
2b6b3a09
D		 5434 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5435
8d40c3ae
VS		 5436 /* RPS code assumes GPLL is used */
5437 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5438
742f491d 5439 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 5440 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5441
5442 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5443 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5444 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2b6b3a09
D		 5445 dev_priv->rps.cur_freq);
5446
5447 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5448 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5449 dev_priv->rps.efficient_freq);
5450
5451 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5452
59bad947 5453 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 5454}
5455
0a073b84
JB		 5456static void valleyview_enable_rps(struct drm_device *dev)
5457{
5458 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 5459 struct intel_engine_cs *ring;
2a5913a8 5460 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 5461 int i;
5462
5463 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5464
ae48434c
ID		 5465 valleyview_check_pctx(dev_priv);
5466
0a073b84 5467 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 5468 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5469 gtfifodbg);
0a073b84
JB		 5470 I915_WRITE(GTFIFODBG, gtfifodbg);
5471 }
5472
c8d9a590 5473 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5474 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5475
160614a2
VS		 5476 /* Disable RC states. */
5477 I915_WRITE(GEN6_RC_CONTROL, 0);
5478
cad725fe 5479 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 5480 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5481 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5482 I915_WRITE(GEN6_RP_UP_EI, 66000);
5483 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5484
5485 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5486
5487 I915_WRITE(GEN6_RP_CONTROL,
5488 GEN6_RP_MEDIA_TURBO |
5489 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5490 GEN6_RP_MEDIA_IS_GFX |
5491 GEN6_RP_ENABLE |
5492 GEN6_RP_UP_BUSY_AVG |
5493 GEN6_RP_DOWN_IDLE_CONT);
5494
5495 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5496 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5497 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5498
5499 for_each_ring(ring, dev_priv, i)
5500 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5501
2f0aa304 5502 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5503
5504 /* allows RC6 residency counter to work */
49798eb2 5505 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5506 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5507 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5508 VLV_MEDIA_RC6_COUNT_EN |
5509 VLV_RENDER_RC6_COUNT_EN));
31685c25 5510
a2b23fe0 5511 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 5512 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 5513
5514 intel_print_rc6_info(dev, rc6_mode);
5515
a2b23fe0 5516 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5517
3ef62342
D		 5518 /* Setting Fixed Bias */
5519 val = VLV_OVERRIDE_EN |
5520 VLV_SOC_TDP_EN |
5521 VLV_BIAS_CPU_125_SOC_875;
5522 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5523
64936258 5524 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 5525
8d40c3ae
VS		 5526 /* RPS code assumes GPLL is used */
5527 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5528
742f491d 5529 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 5530 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5531
b39fb297 5532 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 5533 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5534 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
b39fb297 5535 dev_priv->rps.cur_freq);
0a073b84 5536
73008b98 5537 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5538 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
b39fb297 5539 dev_priv->rps.efficient_freq);
0a073b84 5540
b39fb297 5541 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 5542
59bad947 5543 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 5544}
5545
dde18883
ED		 5546static unsigned long intel_pxfreq(u32 vidfreq)
5547{
5548 unsigned long freq;
5549 int div = (vidfreq & 0x3f0000) >> 16;
5550 int post = (vidfreq & 0x3000) >> 12;
5551 int pre = (vidfreq & 0x7);
5552
5553 if (!pre)
5554 return 0;
5555
5556 freq = ((div * 133333) / ((1<<post) * pre));
5557
5558 return freq;
5559}
5560
eb48eb00
DV		 5561static const struct cparams {
5562 u16 i;
5563 u16 t;
5564 u16 m;
5565 u16 c;
5566} cparams[] = {
5567 { 1, 1333, 301, 28664 },
5568 { 1, 1066, 294, 24460 },
5569 { 1, 800, 294, 25192 },
5570 { 0, 1333, 276, 27605 },
5571 { 0, 1066, 276, 27605 },
5572 { 0, 800, 231, 23784 },
5573};
5574
f531dcb2 5575static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5576{
5577 u64 total_count, diff, ret;
5578 u32 count1, count2, count3, m = 0, c = 0;
5579 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5580 int i;
5581
02d71956
DV		 5582 assert_spin_locked(&mchdev_lock);
5583
20e4d407 5584 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 5585
5586 /* Prevent division-by-zero if we are asking too fast.
5587 * Also, we don't get interesting results if we are polling
5588 * faster than once in 10ms, so just return the saved value
5589 * in such cases.
5590 */
5591 if (diff1 <= 10)
20e4d407 5592 return dev_priv->ips.chipset_power;
eb48eb00
DV		 5593
5594 count1 = I915_READ(DMIEC);
5595 count2 = I915_READ(DDREC);
5596 count3 = I915_READ(CSIEC);
5597
5598 total_count = count1 + count2 + count3;
5599
5600 /* FIXME: handle per-counter overflow */
20e4d407
DV		 5601 if (total_count < dev_priv->ips.last_count1) {
5602 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 5603 diff += total_count;
5604 } else {
20e4d407 5605 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 5606 }
5607
5608 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 5609 if (cparams[i].i == dev_priv->ips.c_m &&
5610 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 5611 m = cparams[i].m;
5612 c = cparams[i].c;
5613 break;
5614 }
5615 }
5616
5617 diff = div_u64(diff, diff1);
5618 ret = ((m * diff) + c);
5619 ret = div_u64(ret, 10);
5620
20e4d407
DV		 5621 dev_priv->ips.last_count1 = total_count;
5622 dev_priv->ips.last_time1 = now;
eb48eb00 5623
20e4d407 5624 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 5625
5626 return ret;
5627}
5628
f531dcb2
CW		 5629unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5630{
3d13ef2e 5631 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5632 unsigned long val;
5633
3d13ef2e 5634 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5635 return 0;
5636
5637 spin_lock_irq(&mchdev_lock);
5638
5639 val = __i915_chipset_val(dev_priv);
5640
5641 spin_unlock_irq(&mchdev_lock);
5642
5643 return val;
5644}
5645
eb48eb00
DV		 5646unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5647{
5648 unsigned long m, x, b;
5649 u32 tsfs;
5650
5651 tsfs = I915_READ(TSFS);
5652
5653 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5654 x = I915_READ8(TR1);
5655
5656 b = tsfs & TSFS_INTR_MASK;
5657
5658 return ((m * x) / 127) - b;
5659}
5660
d972d6ee
MK		 5661static int _pxvid_to_vd(u8 pxvid)
5662{
5663 if (pxvid == 0)
5664 return 0;
5665
5666 if (pxvid >= 8 && pxvid < 31)
5667 pxvid = 31;
5668
5669 return (pxvid + 2) * 125;
5670}
5671
5672static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 5673{
3d13ef2e 5674 struct drm_device *dev = dev_priv->dev;
d972d6ee
MK		 5675 const int vd = _pxvid_to_vd(pxvid);
5676 const int vm = vd - 1125;
5677
3d13ef2e 5678 if (INTEL_INFO(dev)->is_mobile)
d972d6ee
MK		 5679 return vm > 0 ? vm : 0;
5680
5681 return vd;
eb48eb00
DV		 5682}
5683
02d71956 5684static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 5685{
5ed0bdf2 5686 u64 now, diff, diffms;
eb48eb00
DV		 5687 u32 count;
5688
02d71956 5689 assert_spin_locked(&mchdev_lock);
eb48eb00 5690
5ed0bdf2
TG		 5691 now = ktime_get_raw_ns();
5692 diffms = now - dev_priv->ips.last_time2;
5693 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 5694
5695 /* Don't divide by 0 */
eb48eb00
DV		 5696 if (!diffms)
5697 return;
5698
5699 count = I915_READ(GFXEC);
5700
20e4d407
DV		 5701 if (count < dev_priv->ips.last_count2) {
5702 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 5703 diff += count;
5704 } else {
20e4d407 5705 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 5706 }
5707
20e4d407
DV		 5708 dev_priv->ips.last_count2 = count;
5709 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 5710
5711 /* More magic constants... */
5712 diff = diff * 1181;
5713 diff = div_u64(diff, diffms * 10);
20e4d407 5714 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 5715}
5716
02d71956
DV		 5717void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5718{
3d13ef2e
DL		 5719 struct drm_device *dev = dev_priv->dev;
5720
5721 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 5722 return;
5723
9270388e 5724 spin_lock_irq(&mchdev_lock);
02d71956
DV		 5725
5726 __i915_update_gfx_val(dev_priv);
5727
9270388e 5728 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 5729}
5730
f531dcb2 5731static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5732{
5733 unsigned long t, corr, state1, corr2, state2;
5734 u32 pxvid, ext_v;
5735
02d71956
DV		 5736 assert_spin_locked(&mchdev_lock);
5737
616847e7 5738 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 5739 pxvid = (pxvid >> 24) & 0x7f;
5740 ext_v = pvid_to_extvid(dev_priv, pxvid);
5741
5742 state1 = ext_v;
5743
5744 t = i915_mch_val(dev_priv);
5745
5746 /* Revel in the empirically derived constants */
5747
5748 /* Correction factor in 1/100000 units */
5749 if (t > 80)
5750 corr = ((t * 2349) + 135940);
5751 else if (t >= 50)
5752 corr = ((t * 964) + 29317);
5753 else /* < 50 */
5754 corr = ((t * 301) + 1004);
5755
5756 corr = corr * ((150142 * state1) / 10000 - 78642);
5757 corr /= 100000;
20e4d407 5758 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 5759
5760 state2 = (corr2 * state1) / 10000;
5761 state2 /= 100; /* convert to mW */
5762
02d71956 5763 __i915_update_gfx_val(dev_priv);
eb48eb00 5764
20e4d407 5765 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 5766}
5767
f531dcb2
CW		 5768unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5769{
3d13ef2e 5770 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5771 unsigned long val;
5772
3d13ef2e 5773 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5774 return 0;
5775
5776 spin_lock_irq(&mchdev_lock);
5777
5778 val = __i915_gfx_val(dev_priv);
5779
5780 spin_unlock_irq(&mchdev_lock);
5781
5782 return val;
5783}
5784
eb48eb00
DV		 5785/**
5786 * i915_read_mch_val - return value for IPS use
5787 *
5788 * Calculate and return a value for the IPS driver to use when deciding whether
5789 * we have thermal and power headroom to increase CPU or GPU power budget.
5790 */
5791unsigned long i915_read_mch_val(void)
5792{
5793 struct drm_i915_private *dev_priv;
5794 unsigned long chipset_val, graphics_val, ret = 0;
5795
9270388e 5796 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5797 if (!i915_mch_dev)
5798 goto out_unlock;
5799 dev_priv = i915_mch_dev;
5800
f531dcb2
CW		 5801 chipset_val = __i915_chipset_val(dev_priv);
5802 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 5803
5804 ret = chipset_val + graphics_val;
5805
5806out_unlock:
9270388e 5807 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5808
5809 return ret;
5810}
5811EXPORT_SYMBOL_GPL(i915_read_mch_val);
5812
5813/**
5814 * i915_gpu_raise - raise GPU frequency limit
5815 *
5816 * Raise the limit; IPS indicates we have thermal headroom.
5817 */
5818bool i915_gpu_raise(void)
5819{
5820 struct drm_i915_private *dev_priv;
5821 bool ret = true;
5822
9270388e 5823 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5824 if (!i915_mch_dev) {
5825 ret = false;
5826 goto out_unlock;
5827 }
5828 dev_priv = i915_mch_dev;
5829
20e4d407
DV		 5830 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5831 dev_priv->ips.max_delay--;
eb48eb00
DV		 5832
5833out_unlock:
9270388e 5834 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5835
5836 return ret;
5837}
5838EXPORT_SYMBOL_GPL(i915_gpu_raise);
5839
5840/**
5841 * i915_gpu_lower - lower GPU frequency limit
5842 *
5843 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5844 * frequency maximum.
5845 */
5846bool i915_gpu_lower(void)
5847{
5848 struct drm_i915_private *dev_priv;
5849 bool ret = true;
5850
9270388e 5851 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5852 if (!i915_mch_dev) {
5853 ret = false;
5854 goto out_unlock;
5855 }
5856 dev_priv = i915_mch_dev;
5857
20e4d407
DV		 5858 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5859 dev_priv->ips.max_delay++;
eb48eb00
DV		 5860
5861out_unlock:
9270388e 5862 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5863
5864 return ret;
5865}
5866EXPORT_SYMBOL_GPL(i915_gpu_lower);
5867
5868/**
5869 * i915_gpu_busy - indicate GPU business to IPS
5870 *
5871 * Tell the IPS driver whether or not the GPU is busy.
5872 */
5873bool i915_gpu_busy(void)
5874{
5875 struct drm_i915_private *dev_priv;
a4872ba6 5876 struct intel_engine_cs *ring;
eb48eb00 5877 bool ret = false;
f047e395 5878 int i;
eb48eb00 5879
9270388e 5880 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5881 if (!i915_mch_dev)
5882 goto out_unlock;
5883 dev_priv = i915_mch_dev;
5884
f047e395
CW		 5885 for_each_ring(ring, dev_priv, i)
5886 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 5887
5888out_unlock:
9270388e 5889 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5890
5891 return ret;
5892}
5893EXPORT_SYMBOL_GPL(i915_gpu_busy);
5894
5895/**
5896 * i915_gpu_turbo_disable - disable graphics turbo
5897 *
5898 * Disable graphics turbo by resetting the max frequency and setting the
5899 * current frequency to the default.
5900 */
5901bool i915_gpu_turbo_disable(void)
5902{
5903 struct drm_i915_private *dev_priv;
5904 bool ret = true;
5905
9270388e 5906 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5907 if (!i915_mch_dev) {
5908 ret = false;
5909 goto out_unlock;
5910 }
5911 dev_priv = i915_mch_dev;
5912
20e4d407 5913 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 5914
20e4d407 5915 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 5916 ret = false;
5917
5918out_unlock:
9270388e 5919 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5920
5921 return ret;
5922}
5923EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5924
5925/**
5926 * Tells the intel_ips driver that the i915 driver is now loaded, if
5927 * IPS got loaded first.
5928 *
5929 * This awkward dance is so that neither module has to depend on the
5930 * other in order for IPS to do the appropriate communication of
5931 * GPU turbo limits to i915.
5932 */
5933static void
5934ips_ping_for_i915_load(void)
5935{
5936 void (*link)(void);
5937
5938 link = symbol_get(ips_link_to_i915_driver);
5939 if (link) {
5940 link();
5941 symbol_put(ips_link_to_i915_driver);
5942 }
5943}
5944
5945void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5946{
02d71956
DV		 5947 /* We only register the i915 ips part with intel-ips once everything is
5948 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 5949 spin_lock_irq(&mchdev_lock);
eb48eb00 5950 i915_mch_dev = dev_priv;
9270388e 5951 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5952
5953 ips_ping_for_i915_load();
5954}
5955
5956void intel_gpu_ips_teardown(void)
5957{
9270388e 5958 spin_lock_irq(&mchdev_lock);
eb48eb00 5959 i915_mch_dev = NULL;
9270388e 5960 spin_unlock_irq(&mchdev_lock);
eb48eb00 5961}
76c3552f 5962
8090c6b9 5963static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 5964{
5965 struct drm_i915_private *dev_priv = dev->dev_private;
5966 u32 lcfuse;
5967 u8 pxw[16];
5968 int i;
5969
5970 /* Disable to program */
5971 I915_WRITE(ECR, 0);
5972 POSTING_READ(ECR);
5973
5974 /* Program energy weights for various events */
5975 I915_WRITE(SDEW, 0x15040d00);
5976 I915_WRITE(CSIEW0, 0x007f0000);
5977 I915_WRITE(CSIEW1, 0x1e220004);
5978 I915_WRITE(CSIEW2, 0x04000004);
5979
5980 for (i = 0; i < 5; i++)
616847e7 5981 I915_WRITE(PEW(i), 0);
dde18883 5982 for (i = 0; i < 3; i++)
616847e7 5983 I915_WRITE(DEW(i), 0);
dde18883
ED		 5984
5985 /* Program P-state weights to account for frequency power adjustment */
5986 for (i = 0; i < 16; i++) {
616847e7 5987 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 5988 unsigned long freq = intel_pxfreq(pxvidfreq);
5989 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5990 PXVFREQ_PX_SHIFT;
5991 unsigned long val;
5992
5993 val = vid * vid;
5994 val *= (freq / 1000);
5995 val *= 255;
5996 val /= (127*127*900);
5997 if (val > 0xff)
5998 DRM_ERROR("bad pxval: %ld\n", val);
5999 pxw[i] = val;
6000 }
6001 /* Render standby states get 0 weight */
6002 pxw[14] = 0;
6003 pxw[15] = 0;
6004
6005 for (i = 0; i < 4; i++) {
6006 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6007 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6008 I915_WRITE(PXW(i), val);
dde18883
ED		 6009 }
6010
6011 /* Adjust magic regs to magic values (more experimental results) */
6012 I915_WRITE(OGW0, 0);
6013 I915_WRITE(OGW1, 0);
6014 I915_WRITE(EG0, 0x00007f00);
6015 I915_WRITE(EG1, 0x0000000e);
6016 I915_WRITE(EG2, 0x000e0000);
6017 I915_WRITE(EG3, 0x68000300);
6018 I915_WRITE(EG4, 0x42000000);
6019 I915_WRITE(EG5, 0x00140031);
6020 I915_WRITE(EG6, 0);
6021 I915_WRITE(EG7, 0);
6022
6023 for (i = 0; i < 8; i++)
616847e7 6024 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6025
6026 /* Enable PMON + select events */
6027 I915_WRITE(ECR, 0x80000019);
6028
6029 lcfuse = I915_READ(LCFUSE02);
6030
20e4d407 6031 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6032}
6033
ae48434c
ID		 6034void intel_init_gt_powersave(struct drm_device *dev)
6035{
b268c699
ID		 6036 struct drm_i915_private *dev_priv = dev->dev_private;
6037
e6069ca8 6038 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
b268c699
ID		 6039 /*
6040 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6041 * requirement.
6042 */
6043 if (!i915.enable_rc6) {
6044 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6045 intel_runtime_pm_get(dev_priv);
6046 }
e6069ca8 6047
38807746
D		 6048 if (IS_CHERRYVIEW(dev))
6049 cherryview_init_gt_powersave(dev);
6050 else if (IS_VALLEYVIEW(dev))
4e80519e 6051 valleyview_init_gt_powersave(dev);
ae48434c
ID		 6052}
6053
6054void intel_cleanup_gt_powersave(struct drm_device *dev)
6055{
b268c699
ID		 6056 struct drm_i915_private *dev_priv = dev->dev_private;
6057
38807746
D		 6058 if (IS_CHERRYVIEW(dev))
6059 return;
6060 else if (IS_VALLEYVIEW(dev))
4e80519e 6061 valleyview_cleanup_gt_powersave(dev);
b268c699
ID		 6062
6063 if (!i915.enable_rc6)
6064 intel_runtime_pm_put(dev_priv);
ae48434c
ID		 6065}
6066
dbea3cea
ID		 6067static void gen6_suspend_rps(struct drm_device *dev)
6068{
6069 struct drm_i915_private *dev_priv = dev->dev_private;
6070
6071 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6072
4c2a8897 6073 gen6_disable_rps_interrupts(dev);
dbea3cea
ID		 6074}
6075
156c7ca0
JB		 6076/**
6077 * intel_suspend_gt_powersave - suspend PM work and helper threads
6078 * @dev: drm device
6079 *
6080 * We don't want to disable RC6 or other features here, we just want
6081 * to make sure any work we've queued has finished and won't bother
6082 * us while we're suspended.
6083 */
6084void intel_suspend_gt_powersave(struct drm_device *dev)
6085{
6086 struct drm_i915_private *dev_priv = dev->dev_private;
6087
d4d70aa5
ID		 6088 if (INTEL_INFO(dev)->gen < 6)
6089 return;
6090
dbea3cea 6091 gen6_suspend_rps(dev);
b47adc17
D		 6092
6093 /* Force GPU to min freq during suspend */
6094 gen6_rps_idle(dev_priv);
156c7ca0
JB		 6095}
6096
8090c6b9
DV		 6097void intel_disable_gt_powersave(struct drm_device *dev)
6098{
1a01ab3b
JB		 6099 struct drm_i915_private *dev_priv = dev->dev_private;
6100
930ebb46 6101 if (IS_IRONLAKE_M(dev)) {
8090c6b9 6102 ironlake_disable_drps(dev);
38807746 6103 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 6104 intel_suspend_gt_powersave(dev);
e494837a 6105
4fc688ce 6106 mutex_lock(&dev_priv->rps.hw_lock);
20e49366
ZW		 6107 if (INTEL_INFO(dev)->gen >= 9)
6108 gen9_disable_rps(dev);
6109 else if (IS_CHERRYVIEW(dev))
38807746
D		 6110 cherryview_disable_rps(dev);
6111 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 6112 valleyview_disable_rps(dev);
6113 else
6114 gen6_disable_rps(dev);
e534770a 6115
c0951f0c 6116 dev_priv->rps.enabled = false;
4fc688ce 6117 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 6118 }
8090c6b9
DV		 6119}
6120
1a01ab3b
JB		 6121static void intel_gen6_powersave_work(struct work_struct *work)
6122{
6123 struct drm_i915_private *dev_priv =
6124 container_of(work, struct drm_i915_private,
6125 rps.delayed_resume_work.work);
6126 struct drm_device *dev = dev_priv->dev;
6127
4fc688ce 6128 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 6129
4c2a8897 6130 gen6_reset_rps_interrupts(dev);
3cc134e3 6131
38807746
D		 6132 if (IS_CHERRYVIEW(dev)) {
6133 cherryview_enable_rps(dev);
6134 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 6135 valleyview_enable_rps(dev);
20e49366 6136 } else if (INTEL_INFO(dev)->gen >= 9) {
b6fef0ef 6137 gen9_enable_rc6(dev);
20e49366 6138 gen9_enable_rps(dev);
ef11bdb3 6139 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
cc017fb4 6140 __gen6_update_ring_freq(dev);
6edee7f3
BW		 6141 } else if (IS_BROADWELL(dev)) {
6142 gen8_enable_rps(dev);
c2bc2fc5 6143 __gen6_update_ring_freq(dev);
0a073b84
JB		 6144 } else {
6145 gen6_enable_rps(dev);
c2bc2fc5 6146 __gen6_update_ring_freq(dev);
0a073b84 6147 }
aed242ff
CW		 6148
6149 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6150 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6151
6152 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6153 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6154
c0951f0c 6155 dev_priv->rps.enabled = true;
3cc134e3 6156
4c2a8897 6157 gen6_enable_rps_interrupts(dev);
3cc134e3 6158
4fc688ce 6159 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 6160
6161 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 6162}
6163
8090c6b9
DV		 6164void intel_enable_gt_powersave(struct drm_device *dev)
6165{
1a01ab3b
JB		 6166 struct drm_i915_private *dev_priv = dev->dev_private;
6167
f61018b1
YZ		 6168 /* Powersaving is controlled by the host when inside a VM */
6169 if (intel_vgpu_active(dev))
6170 return;
6171
8090c6b9 6172 if (IS_IRONLAKE_M(dev)) {
dc1d0136 6173 mutex_lock(&dev->struct_mutex);
8090c6b9 6174 ironlake_enable_drps(dev);
8090c6b9 6175 intel_init_emon(dev);
dc1d0136 6176 mutex_unlock(&dev->struct_mutex);
38807746 6177 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 6178 /*
6179 * PCU communication is slow and this doesn't need to be
6180 * done at any specific time, so do this out of our fast path
6181 * to make resume and init faster.
c6df39b5
ID		 6182 *
6183 * We depend on the HW RC6 power context save/restore
6184 * mechanism when entering D3 through runtime PM suspend. So
6185 * disable RPM until RPS/RC6 is properly setup. We can only
6186 * get here via the driver load/system resume/runtime resume
6187 * paths, so the _noresume version is enough (and in case of
6188 * runtime resume it's necessary).
1a01ab3b 6189 */
c6df39b5
ID		 6190 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6191 round_jiffies_up_relative(HZ)))
6192 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 6193 }
6194}
6195
c6df39b5
ID		 6196void intel_reset_gt_powersave(struct drm_device *dev)
6197{
6198 struct drm_i915_private *dev_priv = dev->dev_private;
6199
dbea3cea
ID		 6200 if (INTEL_INFO(dev)->gen < 6)
6201 return;
6202
6203 gen6_suspend_rps(dev);
c6df39b5 6204 dev_priv->rps.enabled = false;
c6df39b5
ID		 6205}
6206
3107bd48
DV		 6207static void ibx_init_clock_gating(struct drm_device *dev)
6208{
6209 struct drm_i915_private *dev_priv = dev->dev_private;
6210
6211 /*
6212 * On Ibex Peak and Cougar Point, we need to disable clock
6213 * gating for the panel power sequencer or it will fail to
6214 * start up when no ports are active.
6215 */
6216 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6217}
6218
0e088b8f
VS		 6219static void g4x_disable_trickle_feed(struct drm_device *dev)
6220{
6221 struct drm_i915_private *dev_priv = dev->dev_private;
b12ce1d8 6222 enum pipe pipe;
0e088b8f 6223
055e393f 6224 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6225 I915_WRITE(DSPCNTR(pipe),
6226 I915_READ(DSPCNTR(pipe)) |
6227 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6228
6229 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6230 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6231 }
6232}
6233
017636cc
VS		 6234static void ilk_init_lp_watermarks(struct drm_device *dev)
6235{
6236 struct drm_i915_private *dev_priv = dev->dev_private;
6237
6238 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6239 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6240 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6241
6242 /*
6243 * Don't touch WM1S_LP_EN here.
6244 * Doing so could cause underruns.
6245 */
6246}
6247
1fa61106 6248static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6249{
6250 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6251 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6252
f1e8fa56
DL		 6253 /*
6254 * Required for FBC
6255 * WaFbcDisableDpfcClockGating:ilk
6256 */
4d47e4f5
DL		 6257 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6258 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6259 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6260
6261 I915_WRITE(PCH_3DCGDIS0,
6262 MARIUNIT_CLOCK_GATE_DISABLE |
6263 SVSMUNIT_CLOCK_GATE_DISABLE);
6264 I915_WRITE(PCH_3DCGDIS1,
6265 VFMUNIT_CLOCK_GATE_DISABLE);
6266
6f1d69b0
ED		 6267 /*
6268 * According to the spec the following bits should be set in
6269 * order to enable memory self-refresh
6270 * The bit 22/21 of 0x42004
6271 * The bit 5 of 0x42020
6272 * The bit 15 of 0x45000
6273 */
6274 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6275 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6276 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6277 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6278 I915_WRITE(DISP_ARB_CTL,
6279 (I915_READ(DISP_ARB_CTL) |
6280 DISP_FBC_WM_DIS));
017636cc
VS		 6281
6282 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6283
6284 /*
6285 * Based on the document from hardware guys the following bits
6286 * should be set unconditionally in order to enable FBC.
6287 * The bit 22 of 0x42000
6288 * The bit 22 of 0x42004
6289 * The bit 7,8,9 of 0x42020.
6290 */
6291 if (IS_IRONLAKE_M(dev)) {
4bb35334 6292 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6293 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6294 I915_READ(ILK_DISPLAY_CHICKEN1) |
6295 ILK_FBCQ_DIS);
6296 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6297 I915_READ(ILK_DISPLAY_CHICKEN2) |
6298 ILK_DPARB_GATE);
6f1d69b0
ED		 6299 }
6300
4d47e4f5
DL		 6301 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6302
6f1d69b0
ED		 6303 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6304 I915_READ(ILK_DISPLAY_CHICKEN2) |
6305 ILK_ELPIN_409_SELECT);
6306 I915_WRITE(_3D_CHICKEN2,
6307 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6308 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6309
ecdb4eb7 6310 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6311 I915_WRITE(CACHE_MODE_0,
6312 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6313
4e04632e
AG		 6314 /* WaDisable_RenderCache_OperationalFlush:ilk */
6315 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6316
0e088b8f 6317 g4x_disable_trickle_feed(dev);
bdad2b2f 6318
3107bd48
DV		 6319 ibx_init_clock_gating(dev);
6320}
6321
6322static void cpt_init_clock_gating(struct drm_device *dev)
6323{
6324 struct drm_i915_private *dev_priv = dev->dev_private;
6325 int pipe;
3f704fa2 6326 uint32_t val;
3107bd48
DV		 6327
6328 /*
6329 * On Ibex Peak and Cougar Point, we need to disable clock
6330 * gating for the panel power sequencer or it will fail to
6331 * start up when no ports are active.
6332 */
cd664078
JB		 6333 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6334 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6335 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6336 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6337 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6338 /* The below fixes the weird display corruption, a few pixels shifted
6339 * downward, on (only) LVDS of some HP laptops with IVY.
6340 */
055e393f 6341 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6342 val = I915_READ(TRANS_CHICKEN2(pipe));
6343 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6344 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6345 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6346 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6347 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6348 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6349 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6350 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6351 }
3107bd48 6352 /* WADP0ClockGatingDisable */
055e393f 6353 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6354 I915_WRITE(TRANS_CHICKEN1(pipe),
6355 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6356 }
6f1d69b0
ED		 6357}
6358
1d7aaa0c
DV		 6359static void gen6_check_mch_setup(struct drm_device *dev)
6360{
6361 struct drm_i915_private *dev_priv = dev->dev_private;
6362 uint32_t tmp;
6363
6364 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6365 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6366 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6367 tmp);
1d7aaa0c
DV		 6368}
6369
1fa61106 6370static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6371{
6372 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6373 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6374
231e54f6 6375 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 6376
6377 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6378 I915_READ(ILK_DISPLAY_CHICKEN2) |
6379 ILK_ELPIN_409_SELECT);
6380
ecdb4eb7 6381 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 6382 I915_WRITE(_3D_CHICKEN,
6383 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6384
4e04632e
AG		 6385 /* WaDisable_RenderCache_OperationalFlush:snb */
6386 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6387
8d85d272
VS		 6388 /*
6389 * BSpec recoomends 8x4 when MSAA is used,
6390 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6391 *
6392 * Note that PS/WM thread counts depend on the WIZ hashing
6393 * disable bit, which we don't touch here, but it's good
6394 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 6395 */
6396 I915_WRITE(GEN6_GT_MODE,
98533251 6397 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 6398
017636cc 6399 ilk_init_lp_watermarks(dev);
6f1d69b0 6400
6f1d69b0 6401 I915_WRITE(CACHE_MODE_0,
50743298 6402 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 6403
6404 I915_WRITE(GEN6_UCGCTL1,
6405 I915_READ(GEN6_UCGCTL1) |
6406 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6407 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6408
6409 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6410 * gating disable must be set. Failure to set it results in
6411 * flickering pixels due to Z write ordering failures after
6412 * some amount of runtime in the Mesa "fire" demo, and Unigine
6413 * Sanctuary and Tropics, and apparently anything else with
6414 * alpha test or pixel discard.
6415 *
6416 * According to the spec, bit 11 (RCCUNIT) must also be set,
6417 * but we didn't debug actual testcases to find it out.
0f846f81 6418 *
ef59318c
VS		 6419 * WaDisableRCCUnitClockGating:snb
6420 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 6421 */
6422 I915_WRITE(GEN6_UCGCTL2,
6423 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6424 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6425
5eb146dd 6426 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 6427 I915_WRITE(_3D_CHICKEN3,
6428 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 6429
e927ecde
VS		 6430 /*
6431 * Bspec says:
6432 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6433 * 3DSTATE_SF number of SF output attributes is more than 16."
6434 */
6435 I915_WRITE(_3D_CHICKEN3,
6436 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6437
6f1d69b0
ED		 6438 /*
6439 * According to the spec the following bits should be
6440 * set in order to enable memory self-refresh and fbc:
6441 * The bit21 and bit22 of 0x42000
6442 * The bit21 and bit22 of 0x42004
6443 * The bit5 and bit7 of 0x42020
6444 * The bit14 of 0x70180
6445 * The bit14 of 0x71180
4bb35334
DL		 6446 *
6447 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 6448 */
6449 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6450 I915_READ(ILK_DISPLAY_CHICKEN1) |
6451 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6452 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6453 I915_READ(ILK_DISPLAY_CHICKEN2) |
6454 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 6455 I915_WRITE(ILK_DSPCLK_GATE_D,
6456 I915_READ(ILK_DSPCLK_GATE_D) |
6457 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6458 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6459
0e088b8f 6460 g4x_disable_trickle_feed(dev);
f8f2ac9a 6461
3107bd48 6462 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6463
6464 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6465}
6466
6467static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6468{
6469 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6470
3aad9059 6471 /*
46680e0a 6472 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 6473 *
6474 * This actually overrides the dispatch
6475 * mode for all thread types.
6476 */
6f1d69b0
ED		 6477 reg &= ~GEN7_FF_SCHED_MASK;
6478 reg |= GEN7_FF_TS_SCHED_HW;
6479 reg |= GEN7_FF_VS_SCHED_HW;
6480 reg |= GEN7_FF_DS_SCHED_HW;
6481
6482 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6483}
6484
17a303ec
PZ		 6485static void lpt_init_clock_gating(struct drm_device *dev)
6486{
6487 struct drm_i915_private *dev_priv = dev->dev_private;
6488
6489 /*
6490 * TODO: this bit should only be enabled when really needed, then
6491 * disabled when not needed anymore in order to save power.
6492 */
c2699524 6493 if (HAS_PCH_LPT_LP(dev))
17a303ec
PZ		 6494 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6495 I915_READ(SOUTH_DSPCLK_GATE_D) |
6496 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 6497
6498 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 6499 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6500 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 6501 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 6502}
6503
7d708ee4
ID		 6504static void lpt_suspend_hw(struct drm_device *dev)
6505{
6506 struct drm_i915_private *dev_priv = dev->dev_private;
6507
c2699524 6508 if (HAS_PCH_LPT_LP(dev)) {
7d708ee4
ID		 6509 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6510
6511 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6512 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6513 }
6514}
6515
47c2bd97 6516static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 6517{
6518 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 6519 enum pipe pipe;
4d487cff 6520 uint32_t misccpctl;
1020a5c2 6521
7ad0dbab 6522 ilk_init_lp_watermarks(dev);
50ed5fbd 6523
ab57fff1 6524 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 6525 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 6526
ab57fff1 6527 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 6528 I915_WRITE(CHICKEN_PAR1_1,
6529 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6530
ab57fff1 6531 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 6532 for_each_pipe(dev_priv, pipe) {
07d27e20 6533 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 6534 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 6535 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 6536 }
63801f21 6537
ab57fff1
BW		 6538 /* WaVSRefCountFullforceMissDisable:bdw */
6539 /* WaDSRefCountFullforceMissDisable:bdw */
6540 I915_WRITE(GEN7_FF_THREAD_MODE,
6541 I915_READ(GEN7_FF_THREAD_MODE) &
6542 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 6543
295e8bb7
VS		 6544 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6545 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 6546
6547 /* WaDisableSDEUnitClockGating:bdw */
6548 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6549 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 6550
4d487cff
VS		 6551 /*
6552 * WaProgramL3SqcReg1Default:bdw
6553 * WaTempDisableDOPClkGating:bdw
6554 */
6555 misccpctl = I915_READ(GEN7_MISCCPCTL);
6556 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6557 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6558 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6559
6d50b065
VS		 6560 /*
6561 * WaGttCachingOffByDefault:bdw
6562 * GTT cache may not work with big pages, so if those
6563 * are ever enabled GTT cache may need to be disabled.
6564 */
6565 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6566
89d6b2b8 6567 lpt_init_clock_gating(dev);
1020a5c2
BW		 6568}
6569
cad2a2d7
ED		 6570static void haswell_init_clock_gating(struct drm_device *dev)
6571{
6572 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 6573
017636cc 6574 ilk_init_lp_watermarks(dev);
cad2a2d7 6575
f3fc4884
FJ		 6576 /* L3 caching of data atomics doesn't work -- disable it. */
6577 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6578 I915_WRITE(HSW_ROW_CHICKEN3,
6579 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6580
ecdb4eb7 6581 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 6582 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6583 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6584 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6585
e36ea7ff
VS		 6586 /* WaVSRefCountFullforceMissDisable:hsw */
6587 I915_WRITE(GEN7_FF_THREAD_MODE,
6588 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 6589
4e04632e
AG		 6590 /* WaDisable_RenderCache_OperationalFlush:hsw */
6591 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6592
fe27c606
CW		 6593 /* enable HiZ Raw Stall Optimization */
6594 I915_WRITE(CACHE_MODE_0_GEN7,
6595 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6596
ecdb4eb7 6597 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 6598 I915_WRITE(CACHE_MODE_1,
6599 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 6600
a12c4967
VS		 6601 /*
6602 * BSpec recommends 8x4 when MSAA is used,
6603 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6604 *
6605 * Note that PS/WM thread counts depend on the WIZ hashing
6606 * disable bit, which we don't touch here, but it's good
6607 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 6608 */
6609 I915_WRITE(GEN7_GT_MODE,
98533251 6610 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 6611
94411593
KG		 6612 /* WaSampleCChickenBitEnable:hsw */
6613 I915_WRITE(HALF_SLICE_CHICKEN3,
6614 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6615
ecdb4eb7 6616 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 6617 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6618
90a88643
PZ		 6619 /* WaRsPkgCStateDisplayPMReq:hsw */
6620 I915_WRITE(CHICKEN_PAR1_1,
6621 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 6622
17a303ec 6623 lpt_init_clock_gating(dev);
cad2a2d7
ED		 6624}
6625
1fa61106 6626static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6627{
6628 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 6629 uint32_t snpcr;
6f1d69b0 6630
017636cc 6631 ilk_init_lp_watermarks(dev);
6f1d69b0 6632
231e54f6 6633 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6634
ecdb4eb7 6635 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 6636 I915_WRITE(_3D_CHICKEN3,
6637 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6638
ecdb4eb7 6639 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 6640 I915_WRITE(IVB_CHICKEN3,
6641 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6642 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6643
ecdb4eb7 6644 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 6645 if (IS_IVB_GT1(dev))
6646 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6647 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6648
4e04632e
AG		 6649 /* WaDisable_RenderCache_OperationalFlush:ivb */
6650 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6651
ecdb4eb7 6652 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 6653 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6654 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6655
ecdb4eb7 6656 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 6657 I915_WRITE(GEN7_L3CNTLREG1,
6658 GEN7_WA_FOR_GEN7_L3_CONTROL);
6659 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 6660 GEN7_WA_L3_CHICKEN_MODE);
6661 if (IS_IVB_GT1(dev))
6662 I915_WRITE(GEN7_ROW_CHICKEN2,
6663 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 6664 else {
6665 /* must write both registers */
6666 I915_WRITE(GEN7_ROW_CHICKEN2,
6667 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 6668 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6669 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 6670 }
6f1d69b0 6671
ecdb4eb7 6672 /* WaForceL3Serialization:ivb */
61939d97
JB		 6673 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6674 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6675
1b80a19a 6676 /*
0f846f81 6677 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6678 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 6679 */
6680 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 6681 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6682
ecdb4eb7 6683 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 6684 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6685 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6686 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6687
0e088b8f 6688 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6689
6690 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 6691
22721343
CW		 6692 if (0) { /* causes HiZ corruption on ivb:gt1 */
6693 /* enable HiZ Raw Stall Optimization */
6694 I915_WRITE(CACHE_MODE_0_GEN7,
6695 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6696 }
116f2b6d 6697
ecdb4eb7 6698 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 6699 I915_WRITE(CACHE_MODE_1,
6700 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 6701
a607c1a4
VS		 6702 /*
6703 * BSpec recommends 8x4 when MSAA is used,
6704 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6705 *
6706 * Note that PS/WM thread counts depend on the WIZ hashing
6707 * disable bit, which we don't touch here, but it's good
6708 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 6709 */
6710 I915_WRITE(GEN7_GT_MODE,
98533251 6711 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 6712
20848223
BW		 6713 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6714 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6715 snpcr |= GEN6_MBC_SNPCR_MED;
6716 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 6717
ab5c608b
BW		 6718 if (!HAS_PCH_NOP(dev))
6719 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6720
6721 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6722}
6723
c6beb13e
VS		 6724static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6725{
6726 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6727
6728 /*
6729 * Disable trickle feed and enable pnd deadline calculation
6730 */
6731 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6732 I915_WRITE(CBR1_VLV, 0);
6733}
6734
1fa61106 6735static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6736{
6737 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 6738
c6beb13e 6739 vlv_init_display_clock_gating(dev_priv);
6f1d69b0 6740
ecdb4eb7 6741 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 6742 I915_WRITE(_3D_CHICKEN3,
6743 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6744
ecdb4eb7 6745 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 6746 I915_WRITE(IVB_CHICKEN3,
6747 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6748 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6749
fad7d36e 6750 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 6751 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 6752 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 6753 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6754 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6755
4e04632e
AG		 6756 /* WaDisable_RenderCache_OperationalFlush:vlv */
6757 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6758
ecdb4eb7 6759 /* WaForceL3Serialization:vlv */
61939d97
JB		 6760 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6761 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6762
ecdb4eb7 6763 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 6764 I915_WRITE(GEN7_ROW_CHICKEN2,
6765 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6766
ecdb4eb7 6767 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 6768 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6769 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6770 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6771
46680e0a
VS		 6772 gen7_setup_fixed_func_scheduler(dev_priv);
6773
3c0edaeb 6774 /*
0f846f81 6775 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6776 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 6777 */
6778 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 6779 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6780
c98f5062
AG		 6781 /* WaDisableL3Bank2xClockGate:vlv
6782 * Disabling L3 clock gating- MMIO 940c[25] = 1
6783 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6784 I915_WRITE(GEN7_UCGCTL4,
6785 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 6786
afd58e79
VS		 6787 /*
6788 * BSpec says this must be set, even though
6789 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6790 */
6b26c86d
DV		 6791 I915_WRITE(CACHE_MODE_1,
6792 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 6793
da2518f9
VS		 6794 /*
6795 * BSpec recommends 8x4 when MSAA is used,
6796 * however in practice 16x4 seems fastest.
6797 *
6798 * Note that PS/WM thread counts depend on the WIZ hashing
6799 * disable bit, which we don't touch here, but it's good
6800 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6801 */
6802 I915_WRITE(GEN7_GT_MODE,
6803 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6804
031994ee
VS		 6805 /*
6806 * WaIncreaseL3CreditsForVLVB0:vlv
6807 * This is the hardware default actually.
6808 */
6809 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6810
2d809570 6811 /*
ecdb4eb7 6812 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 6813 * Disable clock gating on th GCFG unit to prevent a delay
6814 * in the reporting of vblank events.
6815 */
7a0d1eed 6816 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 6817}
6818
a4565da8
VS		 6819static void cherryview_init_clock_gating(struct drm_device *dev)
6820{
6821 struct drm_i915_private *dev_priv = dev->dev_private;
6822
c6beb13e 6823 vlv_init_display_clock_gating(dev_priv);
dd811e70 6824
232ce337
VS		 6825 /* WaVSRefCountFullforceMissDisable:chv */
6826 /* WaDSRefCountFullforceMissDisable:chv */
6827 I915_WRITE(GEN7_FF_THREAD_MODE,
6828 I915_READ(GEN7_FF_THREAD_MODE) &
6829 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 6830
6831 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6832 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6833 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 6834
6835 /* WaDisableCSUnitClockGating:chv */
6836 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6837 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 6838
6839 /* WaDisableSDEUnitClockGating:chv */
6840 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6841 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065
VS		 6842
6843 /*
6844 * GTT cache may not work with big pages, so if those
6845 * are ever enabled GTT cache may need to be disabled.
6846 */
6847 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 6848}
6849
1fa61106 6850static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6851{
6852 struct drm_i915_private *dev_priv = dev->dev_private;
6853 uint32_t dspclk_gate;
6854
6855 I915_WRITE(RENCLK_GATE_D1, 0);
6856 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6857 GS_UNIT_CLOCK_GATE_DISABLE |
6858 CL_UNIT_CLOCK_GATE_DISABLE);
6859 I915_WRITE(RAMCLK_GATE_D, 0);
6860 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6861 OVRUNIT_CLOCK_GATE_DISABLE |
6862 OVCUNIT_CLOCK_GATE_DISABLE;
6863 if (IS_GM45(dev))
6864 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6865 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 6866
6867 /* WaDisableRenderCachePipelinedFlush */
6868 I915_WRITE(CACHE_MODE_0,
6869 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 6870
4e04632e
AG		 6871 /* WaDisable_RenderCache_OperationalFlush:g4x */
6872 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6873
0e088b8f 6874 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6875}
6876
1fa61106 6877static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6878{
6879 struct drm_i915_private *dev_priv = dev->dev_private;
6880
6881 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6882 I915_WRITE(RENCLK_GATE_D2, 0);
6883 I915_WRITE(DSPCLK_GATE_D, 0);
6884 I915_WRITE(RAMCLK_GATE_D, 0);
6885 I915_WRITE16(DEUC, 0);
20f94967
VS		 6886 I915_WRITE(MI_ARB_STATE,
6887 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6888
6889 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6890 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6891}
6892
1fa61106 6893static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6894{
6895 struct drm_i915_private *dev_priv = dev->dev_private;
6896
6897 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6898 I965_RCC_CLOCK_GATE_DISABLE |
6899 I965_RCPB_CLOCK_GATE_DISABLE |
6900 I965_ISC_CLOCK_GATE_DISABLE |
6901 I965_FBC_CLOCK_GATE_DISABLE);
6902 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 6903 I915_WRITE(MI_ARB_STATE,
6904 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6905
6906 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6907 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6908}
6909
1fa61106 6910static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6911{
6912 struct drm_i915_private *dev_priv = dev->dev_private;
6913 u32 dstate = I915_READ(D_STATE);
6914
6915 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6916 DSTATE_DOT_CLOCK_GATING;
6917 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 6918
6919 if (IS_PINEVIEW(dev))
6920 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 6921
6922 /* IIR "flip pending" means done if this bit is set */
6923 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 6924
6925 /* interrupts should cause a wake up from C3 */
3299254f 6926 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 6927
6928 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6929 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 6930
6931 I915_WRITE(MI_ARB_STATE,
6932 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6933}
6934
1fa61106 6935static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6936{
6937 struct drm_i915_private *dev_priv = dev->dev_private;
6938
6939 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 6940
6941 /* interrupts should cause a wake up from C3 */
6942 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6943 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 6944
6945 I915_WRITE(MEM_MODE,
6946 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6947}
6948
1fa61106 6949static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6950{
6951 struct drm_i915_private *dev_priv = dev->dev_private;
6952
6953 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 6954
6955 I915_WRITE(MEM_MODE,
6956 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6957 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6958}
6959
6f1d69b0
ED		 6960void intel_init_clock_gating(struct drm_device *dev)
6961{
6962 struct drm_i915_private *dev_priv = dev->dev_private;
6963
c57e3551
DL		 6964 if (dev_priv->display.init_clock_gating)
6965 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 6966}
6967
7d708ee4
ID		 6968void intel_suspend_hw(struct drm_device *dev)
6969{
6970 if (HAS_PCH_LPT(dev))
6971 lpt_suspend_hw(dev);
6972}
6973
1fa61106
ED		 6974/* Set up chip specific power management-related functions */
6975void intel_init_pm(struct drm_device *dev)
6976{
6977 struct drm_i915_private *dev_priv = dev->dev_private;
6978
7ff0ebcc 6979 intel_fbc_init(dev_priv);
1fa61106 6980
c921aba8
DV		 6981 /* For cxsr */
6982 if (IS_PINEVIEW(dev))
6983 i915_pineview_get_mem_freq(dev);
6984 else if (IS_GEN5(dev))
6985 i915_ironlake_get_mem_freq(dev);
6986
1fa61106 6987 /* For FIFO watermark updates */
f5ed50cb 6988 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c
PB		 6989 skl_setup_wm_latency(dev);
6990
a82abe43
ID		 6991 if (IS_BROXTON(dev))
6992 dev_priv->display.init_clock_gating =
6993 bxt_init_clock_gating;
2d41c0b5 6994 dev_priv->display.update_wm = skl_update_wm;
c83155a6 6995 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 6996 ilk_setup_wm_latency(dev);
53615a5e 6997
bd602544
VS		 6998 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6999 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7000 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7001 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7002 dev_priv->display.update_wm = ilk_update_wm;
86c8bbbe 7003 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
d93c0372 7004 dev_priv->display.program_watermarks = ilk_program_watermarks;
bd602544
VS		 7005 } else {
7006 DRM_DEBUG_KMS("Failed to read display plane latency. "
7007 "Disable CxSR\n");
7008 }
7009
7010 if (IS_GEN5(dev))
1fa61106 7011 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 7012 else if (IS_GEN6(dev))
1fa61106 7013 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 7014 else if (IS_IVYBRIDGE(dev))
1fa61106 7015 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 7016 else if (IS_HASWELL(dev))
cad2a2d7 7017 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 7018 else if (INTEL_INFO(dev)->gen == 8)
47c2bd97 7019 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
a4565da8 7020 } else if (IS_CHERRYVIEW(dev)) {
262cd2e1
VS		 7021 vlv_setup_wm_latency(dev);
7022
7023 dev_priv->display.update_wm = vlv_update_wm;
a4565da8
VS		 7024 dev_priv->display.init_clock_gating =
7025 cherryview_init_clock_gating;
1fa61106 7026 } else if (IS_VALLEYVIEW(dev)) {
26e1fe4f
VS		 7027 vlv_setup_wm_latency(dev);
7028
7029 dev_priv->display.update_wm = vlv_update_wm;
1fa61106
ED		 7030 dev_priv->display.init_clock_gating =
7031 valleyview_init_clock_gating;
1fa61106
ED		 7032 } else if (IS_PINEVIEW(dev)) {
7033 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7034 dev_priv->is_ddr3,
7035 dev_priv->fsb_freq,
7036 dev_priv->mem_freq)) {
7037 DRM_INFO("failed to find known CxSR latency "
7038 "(found ddr%s fsb freq %d, mem freq %d), "
7039 "disabling CxSR\n",
7040 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7041 dev_priv->fsb_freq, dev_priv->mem_freq);
7042 /* Disable CxSR and never update its watermark again */
5209b1f4 7043 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7044 dev_priv->display.update_wm = NULL;
7045 } else
7046 dev_priv->display.update_wm = pineview_update_wm;
7047 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7048 } else if (IS_G4X(dev)) {
7049 dev_priv->display.update_wm = g4x_update_wm;
7050 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7051 } else if (IS_GEN4(dev)) {
7052 dev_priv->display.update_wm = i965_update_wm;
7053 if (IS_CRESTLINE(dev))
7054 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7055 else if (IS_BROADWATER(dev))
7056 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7057 } else if (IS_GEN3(dev)) {
7058 dev_priv->display.update_wm = i9xx_update_wm;
7059 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7060 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 7061 } else if (IS_GEN2(dev)) {
7062 if (INTEL_INFO(dev)->num_pipes == 1) {
7063 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7064 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7065 } else {
7066 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7067 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 7068 }
7069
7070 if (IS_I85X(dev) || IS_I865G(dev))
7071 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7072 else
7073 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7074 } else {
7075 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7076 }
7077}
7078
151a49d0 7079int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7080{
4fc688ce 7081 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7082
7083 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7084 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7085 return -EAGAIN;
7086 }
7087
7088 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 7089 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW		 7090 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7091
7092 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7093 500)) {
7094 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7095 return -ETIMEDOUT;
7096 }
7097
7098 *val = I915_READ(GEN6_PCODE_DATA);
7099 I915_WRITE(GEN6_PCODE_DATA, 0);
7100
7101 return 0;
7102}
7103
151a49d0 7104int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 7105{
4fc688ce 7106 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7107
7108 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7109 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7110 return -EAGAIN;
7111 }
7112
7113 I915_WRITE(GEN6_PCODE_DATA, val);
7114 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7115
7116 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7117 500)) {
7118 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7119 return -ETIMEDOUT;
7120 }
7121
7122 I915_WRITE(GEN6_PCODE_DATA, 0);
7123
7124 return 0;
7125}
a0e4e199 7126
dd06f88c 7127static int vlv_gpu_freq_div(unsigned int czclk_freq)
855ba3be 7128{
dd06f88c
VS		 7129 switch (czclk_freq) {
7130 case 200:
7131 return 10;
7132 case 267:
7133 return 12;
7134 case 320:
7135 case 333:
dd06f88c 7136 return 16;
ab3fb157
VS		 7137 case 400:
7138 return 20;
855ba3be
JB		 7139 default:
7140 return -1;
7141 }
dd06f88c 7142}
855ba3be 7143
dd06f88c
VS		 7144static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7145{
bfa7df01 7146 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
dd06f88c
VS		 7147
7148 div = vlv_gpu_freq_div(czclk_freq);
7149 if (div < 0)
7150 return div;
7151
7152 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
855ba3be
JB		 7153}
7154
b55dd647 7155static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7156{
bfa7df01 7157 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
855ba3be 7158
dd06f88c
VS		 7159 mul = vlv_gpu_freq_div(czclk_freq);
7160 if (mul < 0)
7161 return mul;
855ba3be 7162
dd06f88c 7163 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
855ba3be
JB		 7164}
7165
b55dd647 7166static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7167{
bfa7df01 7168 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
22b1b2f8 7169
dd06f88c
VS		 7170 div = vlv_gpu_freq_div(czclk_freq) / 2;
7171 if (div < 0)
7172 return div;
22b1b2f8 7173
dd06f88c 7174 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
22b1b2f8
D		 7175}
7176
b55dd647 7177static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7178{
bfa7df01 7179 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
22b1b2f8 7180
dd06f88c
VS		 7181 mul = vlv_gpu_freq_div(czclk_freq) / 2;
7182 if (mul < 0)
7183 return mul;
22b1b2f8 7184
1c14762d 7185 /* CHV needs even values */
dd06f88c 7186 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
22b1b2f8
D		 7187}
7188
616bc820 7189int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7190{
80b6dda4 7191 if (IS_GEN9(dev_priv->dev))
500a3d2e
MK		 7192 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7193 GEN9_FREQ_SCALER);
80b6dda4 7194 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7195 return chv_gpu_freq(dev_priv, val);
22b1b2f8 7196 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7197 return byt_gpu_freq(dev_priv, val);
7198 else
7199 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7200}
7201
616bc820
VS		 7202int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7203{
80b6dda4 7204 if (IS_GEN9(dev_priv->dev))
500a3d2e
MK		 7205 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7206 GT_FREQUENCY_MULTIPLIER);
80b6dda4 7207 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7208 return chv_freq_opcode(dev_priv, val);
22b1b2f8 7209 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7210 return byt_freq_opcode(dev_priv, val);
7211 else
500a3d2e 7212 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
616bc820 7213}
22b1b2f8 7214
6ad790c0
CW		 7215struct request_boost {
7216 struct work_struct work;
eed29a5b 7217 struct drm_i915_gem_request *req;
6ad790c0
CW		 7218};
7219
7220static void __intel_rps_boost_work(struct work_struct *work)
7221{
7222 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7223 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7224
e61b9958
CW		 7225 if (!i915_gem_request_completed(req, true))
7226 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7227 req->emitted_jiffies);
6ad790c0 7228
e61b9958 7229 i915_gem_request_unreference__unlocked(req);
6ad790c0
CW		 7230 kfree(boost);
7231}
7232
7233void intel_queue_rps_boost_for_request(struct drm_device *dev,
eed29a5b 7234 struct drm_i915_gem_request *req)
6ad790c0
CW		 7235{
7236 struct request_boost *boost;
7237
eed29a5b 7238 if (req == NULL || INTEL_INFO(dev)->gen < 6)
6ad790c0
CW		 7239 return;
7240
e61b9958
CW		 7241 if (i915_gem_request_completed(req, true))
7242 return;
7243
6ad790c0
CW		 7244 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7245 if (boost == NULL)
7246 return;
7247
eed29a5b
DV		 7248 i915_gem_request_reference(req);
7249 boost->req = req;
6ad790c0
CW		 7250
7251 INIT_WORK(&boost->work, __intel_rps_boost_work);
7252 queue_work(to_i915(dev)->wq, &boost->work);
7253}
7254
f742a552 7255void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 7256{
7257 struct drm_i915_private *dev_priv = dev->dev_private;
7258
f742a552 7259 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 7260 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 7261
907b28c5
CW		 7262 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7263 intel_gen6_powersave_work);
1854d5ca 7264 INIT_LIST_HEAD(&dev_priv->rps.clients);
2e1b8730
CW		 7265 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7266 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
5d584b2e 7267
33688d95 7268 dev_priv->pm.suspended = false;
1f814dac 7269 atomic_set(&dev_priv->pm.wakeref_count, 0);
2b19efeb 7270 atomic_set(&dev_priv->pm.atomic_seq, 0);
907b28c5 7271}
Linux 6.x block layer and io_uring tree(s)