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drm/i915/bdw: enable eDRAM.
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
f9dcb0df 33#include <linux/vgaarb.h>
f4db9321 34#include <drm/i915_powerwell.h>
8a187455 35#include <linux/pm_runtime.h>
85208be0 36
dc39fff7
BW		 37/**
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54#define INTEL_RC6_ENABLE (1<<0)
55#define INTEL_RC6p_ENABLE (1<<1)
56#define INTEL_RC6pp_ENABLE (1<<2)
57
f6750b3c
ED		 58/* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 61 *
f6750b3c
ED		 62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
85208be0 64 *
f6750b3c
ED		 65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
85208be0
ED		 67 */
68
1fa61106 69static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 70{
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 u32 fbc_ctl;
73
74 /* Disable compression */
75 fbc_ctl = I915_READ(FBC_CONTROL);
76 if ((fbc_ctl & FBC_CTL_EN) == 0)
77 return;
78
79 fbc_ctl &= ~FBC_CTL_EN;
80 I915_WRITE(FBC_CONTROL, fbc_ctl);
81
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
85 return;
86 }
87
88 DRM_DEBUG_KMS("disabled FBC\n");
89}
90
993495ae 91static void i8xx_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 92{
93 struct drm_device *dev = crtc->dev;
94 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 95 struct drm_framebuffer *fb = crtc->primary->fb;
85208be0
ED		 96 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
97 struct drm_i915_gem_object *obj = intel_fb->obj;
98 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
99 int cfb_pitch;
7f2cf220 100 int i;
159f9875 101 u32 fbc_ctl;
85208be0 102
5c3fe8b0 103 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
85208be0
ED		 104 if (fb->pitches[0] < cfb_pitch)
105 cfb_pitch = fb->pitches[0];
106
42a430f5
VS		 107 /* FBC_CTL wants 32B or 64B units */
108 if (IS_GEN2(dev))
109 cfb_pitch = (cfb_pitch / 32) - 1;
110 else
111 cfb_pitch = (cfb_pitch / 64) - 1;
85208be0
ED		 112
113 /* Clear old tags */
114 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
115 I915_WRITE(FBC_TAG + (i * 4), 0);
116
159f9875
VS		 117 if (IS_GEN4(dev)) {
118 u32 fbc_ctl2;
119
120 /* Set it up... */
121 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
7f2cf220 122 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
159f9875
VS		 123 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
124 I915_WRITE(FBC_FENCE_OFF, crtc->y);
125 }
85208be0
ED		 126
127 /* enable it... */
993495ae
VS		 128 fbc_ctl = I915_READ(FBC_CONTROL);
129 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
130 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
85208be0
ED		 131 if (IS_I945GM(dev))
132 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
133 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
85208be0
ED		 134 fbc_ctl |= obj->fence_reg;
135 I915_WRITE(FBC_CONTROL, fbc_ctl);
136
5cd5410e 137 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
84f44ce7 138 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 139}
140
1fa61106 141static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 142{
143 struct drm_i915_private *dev_priv = dev->dev_private;
144
145 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
146}
147
993495ae 148static void g4x_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 149{
150 struct drm_device *dev = crtc->dev;
151 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 152 struct drm_framebuffer *fb = crtc->primary->fb;
85208be0
ED		 153 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
154 struct drm_i915_gem_object *obj = intel_fb->obj;
155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85208be0
ED		 156 u32 dpfc_ctl;
157
3fa2e0ee
VS		 158 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
159 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
160 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
161 else
162 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
85208be0 163 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
85208be0 164
85208be0
ED		 165 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
166
167 /* enable it... */
fe74c1a5 168 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
85208be0 169
84f44ce7 170 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 171}
172
1fa61106 173static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 174{
175 struct drm_i915_private *dev_priv = dev->dev_private;
176 u32 dpfc_ctl;
177
178 /* Disable compression */
179 dpfc_ctl = I915_READ(DPFC_CONTROL);
180 if (dpfc_ctl & DPFC_CTL_EN) {
181 dpfc_ctl &= ~DPFC_CTL_EN;
182 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
183
184 DRM_DEBUG_KMS("disabled FBC\n");
185 }
186}
187
1fa61106 188static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 189{
190 struct drm_i915_private *dev_priv = dev->dev_private;
191
192 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
193}
194
195static void sandybridge_blit_fbc_update(struct drm_device *dev)
196{
197 struct drm_i915_private *dev_priv = dev->dev_private;
198 u32 blt_ecoskpd;
199
200 /* Make sure blitter notifies FBC of writes */
940aece4
D		 201
202 /* Blitter is part of Media powerwell on VLV. No impact of
203 * his param in other platforms for now */
204 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
c8d9a590 205
85208be0
ED		 206 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
207 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
208 GEN6_BLITTER_LOCK_SHIFT;
209 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
210 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
211 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
212 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
213 GEN6_BLITTER_LOCK_SHIFT);
214 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
215 POSTING_READ(GEN6_BLITTER_ECOSKPD);
c8d9a590 216
940aece4 217 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
85208be0
ED		 218}
219
993495ae 220static void ironlake_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 221{
222 struct drm_device *dev = crtc->dev;
223 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 224 struct drm_framebuffer *fb = crtc->primary->fb;
85208be0
ED		 225 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
226 struct drm_i915_gem_object *obj = intel_fb->obj;
227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85208be0
ED		 228 u32 dpfc_ctl;
229
46f3dab9 230 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
3fa2e0ee
VS		 231 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
232 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
233 else
234 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
d629336b
VS		 235 dpfc_ctl |= DPFC_CTL_FENCE_EN;
236 if (IS_GEN5(dev))
237 dpfc_ctl |= obj->fence_reg;
85208be0 238
85208be0 239 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
f343c5f6 240 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
85208be0
ED		 241 /* enable it... */
242 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
243
244 if (IS_GEN6(dev)) {
245 I915_WRITE(SNB_DPFC_CTL_SA,
246 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
247 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
248 sandybridge_blit_fbc_update(dev);
249 }
250
84f44ce7 251 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 252}
253
1fa61106 254static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 255{
256 struct drm_i915_private *dev_priv = dev->dev_private;
257 u32 dpfc_ctl;
258
259 /* Disable compression */
260 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
261 if (dpfc_ctl & DPFC_CTL_EN) {
262 dpfc_ctl &= ~DPFC_CTL_EN;
263 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
264
265 DRM_DEBUG_KMS("disabled FBC\n");
266 }
267}
268
1fa61106 269static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 270{
271 struct drm_i915_private *dev_priv = dev->dev_private;
272
273 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
274}
275
993495ae 276static void gen7_enable_fbc(struct drm_crtc *crtc)
abe959c7
RV		 277{
278 struct drm_device *dev = crtc->dev;
279 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 280 struct drm_framebuffer *fb = crtc->primary->fb;
abe959c7
RV		 281 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
282 struct drm_i915_gem_object *obj = intel_fb->obj;
283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3fa2e0ee 284 u32 dpfc_ctl;
abe959c7 285
3fa2e0ee
VS		 286 dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
287 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
288 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
289 else
290 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
291 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
292
293 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
abe959c7 294
891348b2 295 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 296 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
2adb6db8
VS		 297 I915_WRITE(ILK_DISPLAY_CHICKEN1,
298 I915_READ(ILK_DISPLAY_CHICKEN1) |
299 ILK_FBCQ_DIS);
28554164 300 } else {
2adb6db8 301 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
8f670bb1
VS		 302 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
303 I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
304 HSW_FBCQ_DIS);
891348b2 305 }
b74ea102 306
abe959c7
RV		 307 I915_WRITE(SNB_DPFC_CTL_SA,
308 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
309 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
310
311 sandybridge_blit_fbc_update(dev);
312
b19870ee 313 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
abe959c7
RV		 314}
315
85208be0
ED		 316bool intel_fbc_enabled(struct drm_device *dev)
317{
318 struct drm_i915_private *dev_priv = dev->dev_private;
319
320 if (!dev_priv->display.fbc_enabled)
321 return false;
322
323 return dev_priv->display.fbc_enabled(dev);
324}
325
326static void intel_fbc_work_fn(struct work_struct *__work)
327{
328 struct intel_fbc_work *work =
329 container_of(to_delayed_work(__work),
330 struct intel_fbc_work, work);
331 struct drm_device *dev = work->crtc->dev;
332 struct drm_i915_private *dev_priv = dev->dev_private;
333
334 mutex_lock(&dev->struct_mutex);
5c3fe8b0 335 if (work == dev_priv->fbc.fbc_work) {
85208be0
ED		 336 /* Double check that we haven't switched fb without cancelling
337 * the prior work.
338 */
f4510a27 339 if (work->crtc->primary->fb == work->fb) {
993495ae 340 dev_priv->display.enable_fbc(work->crtc);
85208be0 341
5c3fe8b0 342 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
f4510a27 343 dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
5c3fe8b0 344 dev_priv->fbc.y = work->crtc->y;
85208be0
ED		 345 }
346
5c3fe8b0 347 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 348 }
349 mutex_unlock(&dev->struct_mutex);
350
351 kfree(work);
352}
353
354static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
355{
5c3fe8b0 356 if (dev_priv->fbc.fbc_work == NULL)
85208be0
ED		 357 return;
358
359 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
360
361 /* Synchronisation is provided by struct_mutex and checking of
5c3fe8b0 362 * dev_priv->fbc.fbc_work, so we can perform the cancellation
85208be0
ED		 363 * entirely asynchronously.
364 */
5c3fe8b0 365 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
85208be0 366 /* tasklet was killed before being run, clean up */
5c3fe8b0 367 kfree(dev_priv->fbc.fbc_work);
85208be0
ED		 368
369 /* Mark the work as no longer wanted so that if it does
370 * wake-up (because the work was already running and waiting
371 * for our mutex), it will discover that is no longer
372 * necessary to run.
373 */
5c3fe8b0 374 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 375}
376
993495ae 377static void intel_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 378{
379 struct intel_fbc_work *work;
380 struct drm_device *dev = crtc->dev;
381 struct drm_i915_private *dev_priv = dev->dev_private;
382
383 if (!dev_priv->display.enable_fbc)
384 return;
385
386 intel_cancel_fbc_work(dev_priv);
387
b14c5679 388 work = kzalloc(sizeof(*work), GFP_KERNEL);
85208be0 389 if (work == NULL) {
6cdcb5e7 390 DRM_ERROR("Failed to allocate FBC work structure\n");
993495ae 391 dev_priv->display.enable_fbc(crtc);
85208be0
ED		 392 return;
393 }
394
395 work->crtc = crtc;
f4510a27 396 work->fb = crtc->primary->fb;
85208be0
ED		 397 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
398
5c3fe8b0 399 dev_priv->fbc.fbc_work = work;
85208be0 400
85208be0
ED		 401 /* Delay the actual enabling to let pageflipping cease and the
402 * display to settle before starting the compression. Note that
403 * this delay also serves a second purpose: it allows for a
404 * vblank to pass after disabling the FBC before we attempt
405 * to modify the control registers.
406 *
407 * A more complicated solution would involve tracking vblanks
408 * following the termination of the page-flipping sequence
409 * and indeed performing the enable as a co-routine and not
410 * waiting synchronously upon the vblank.
7457d617
DL		 411 *
412 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
85208be0
ED		 413 */
414 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
415}
416
417void intel_disable_fbc(struct drm_device *dev)
418{
419 struct drm_i915_private *dev_priv = dev->dev_private;
420
421 intel_cancel_fbc_work(dev_priv);
422
423 if (!dev_priv->display.disable_fbc)
424 return;
425
426 dev_priv->display.disable_fbc(dev);
5c3fe8b0 427 dev_priv->fbc.plane = -1;
85208be0
ED		 428}
429
29ebf90f
CW		 430static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
431 enum no_fbc_reason reason)
432{
433 if (dev_priv->fbc.no_fbc_reason == reason)
434 return false;
435
436 dev_priv->fbc.no_fbc_reason = reason;
437 return true;
438}
439
85208be0
ED		 440/**
441 * intel_update_fbc - enable/disable FBC as needed
442 * @dev: the drm_device
443 *
444 * Set up the framebuffer compression hardware at mode set time. We
445 * enable it if possible:
446 * - plane A only (on pre-965)
447 * - no pixel mulitply/line duplication
448 * - no alpha buffer discard
449 * - no dual wide
f85da868 450 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
85208be0
ED		 451 *
452 * We can't assume that any compression will take place (worst case),
453 * so the compressed buffer has to be the same size as the uncompressed
454 * one. It also must reside (along with the line length buffer) in
455 * stolen memory.
456 *
457 * We need to enable/disable FBC on a global basis.
458 */
459void intel_update_fbc(struct drm_device *dev)
460{
461 struct drm_i915_private *dev_priv = dev->dev_private;
462 struct drm_crtc *crtc = NULL, *tmp_crtc;
463 struct intel_crtc *intel_crtc;
464 struct drm_framebuffer *fb;
465 struct intel_framebuffer *intel_fb;
466 struct drm_i915_gem_object *obj;
ef644fda 467 const struct drm_display_mode *adjusted_mode;
37327abd 468 unsigned int max_width, max_height;
85208be0 469
3a77c4c4 470 if (!HAS_FBC(dev)) {
29ebf90f 471 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
85208be0 472 return;
29ebf90f 473 }
85208be0 474
d330a953 475 if (!i915.powersave) {
29ebf90f
CW		 476 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
477 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0 478 return;
29ebf90f 479 }
85208be0
ED		 480
481 /*
482 * If FBC is already on, we just have to verify that we can
483 * keep it that way...
484 * Need to disable if:
485 * - more than one pipe is active
486 * - changing FBC params (stride, fence, mode)
487 * - new fb is too large to fit in compressed buffer
488 * - going to an unsupported config (interlace, pixel multiply, etc.)
489 */
490 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 491 if (intel_crtc_active(tmp_crtc) &&
4c445e0e 492 to_intel_crtc(tmp_crtc)->primary_enabled) {
85208be0 493 if (crtc) {
29ebf90f
CW		 494 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
495 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
85208be0
ED		 496 goto out_disable;
497 }
498 crtc = tmp_crtc;
499 }
500 }
501
f4510a27 502 if (!crtc || crtc->primary->fb == NULL) {
29ebf90f
CW		 503 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
504 DRM_DEBUG_KMS("no output, disabling\n");
85208be0
ED		 505 goto out_disable;
506 }
507
508 intel_crtc = to_intel_crtc(crtc);
f4510a27 509 fb = crtc->primary->fb;
85208be0
ED		 510 intel_fb = to_intel_framebuffer(fb);
511 obj = intel_fb->obj;
ef644fda 512 adjusted_mode = &intel_crtc->config.adjusted_mode;
85208be0 513
d330a953 514 if (i915.enable_fbc < 0 &&
8a5729a3 515 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
29ebf90f
CW		 516 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
517 DRM_DEBUG_KMS("disabled per chip default\n");
8a5729a3 518 goto out_disable;
85208be0 519 }
d330a953 520 if (!i915.enable_fbc) {
29ebf90f
CW		 521 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
522 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0
ED		 523 goto out_disable;
524 }
ef644fda
VS		 525 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
526 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
29ebf90f
CW		 527 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
528 DRM_DEBUG_KMS("mode incompatible with compression, "
529 "disabling\n");
85208be0
ED		 530 goto out_disable;
531 }
f85da868
PZ		 532
533 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
37327abd
VS		 534 max_width = 4096;
535 max_height = 2048;
f85da868 536 } else {
37327abd
VS		 537 max_width = 2048;
538 max_height = 1536;
f85da868 539 }
37327abd
VS		 540 if (intel_crtc->config.pipe_src_w > max_width ||
541 intel_crtc->config.pipe_src_h > max_height) {
29ebf90f
CW		 542 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
543 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
85208be0
ED		 544 goto out_disable;
545 }
8f94d24b 546 if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
c5a44aa0 547 intel_crtc->plane != PLANE_A) {
29ebf90f 548 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
c5a44aa0 549 DRM_DEBUG_KMS("plane not A, disabling compression\n");
85208be0
ED		 550 goto out_disable;
551 }
552
553 /* The use of a CPU fence is mandatory in order to detect writes
554 * by the CPU to the scanout and trigger updates to the FBC.
555 */
556 if (obj->tiling_mode != I915_TILING_X ||
557 obj->fence_reg == I915_FENCE_REG_NONE) {
29ebf90f
CW		 558 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
559 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
85208be0
ED		 560 goto out_disable;
561 }
562
563 /* If the kernel debugger is active, always disable compression */
564 if (in_dbg_master())
565 goto out_disable;
566
11be49eb 567 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
29ebf90f
CW		 568 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
569 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
11be49eb
CW		 570 goto out_disable;
571 }
572
85208be0
ED		 573 /* If the scanout has not changed, don't modify the FBC settings.
574 * Note that we make the fundamental assumption that the fb->obj
575 * cannot be unpinned (and have its GTT offset and fence revoked)
576 * without first being decoupled from the scanout and FBC disabled.
577 */
5c3fe8b0
BW		 578 if (dev_priv->fbc.plane == intel_crtc->plane &&
579 dev_priv->fbc.fb_id == fb->base.id &&
580 dev_priv->fbc.y == crtc->y)
85208be0
ED		 581 return;
582
583 if (intel_fbc_enabled(dev)) {
584 /* We update FBC along two paths, after changing fb/crtc
585 * configuration (modeswitching) and after page-flipping
586 * finishes. For the latter, we know that not only did
587 * we disable the FBC at the start of the page-flip
588 * sequence, but also more than one vblank has passed.
589 *
590 * For the former case of modeswitching, it is possible
591 * to switch between two FBC valid configurations
592 * instantaneously so we do need to disable the FBC
593 * before we can modify its control registers. We also
594 * have to wait for the next vblank for that to take
595 * effect. However, since we delay enabling FBC we can
596 * assume that a vblank has passed since disabling and
597 * that we can safely alter the registers in the deferred
598 * callback.
599 *
600 * In the scenario that we go from a valid to invalid
601 * and then back to valid FBC configuration we have
602 * no strict enforcement that a vblank occurred since
603 * disabling the FBC. However, along all current pipe
604 * disabling paths we do need to wait for a vblank at
605 * some point. And we wait before enabling FBC anyway.
606 */
607 DRM_DEBUG_KMS("disabling active FBC for update\n");
608 intel_disable_fbc(dev);
609 }
610
993495ae 611 intel_enable_fbc(crtc);
29ebf90f 612 dev_priv->fbc.no_fbc_reason = FBC_OK;
85208be0
ED		 613 return;
614
615out_disable:
616 /* Multiple disables should be harmless */
617 if (intel_fbc_enabled(dev)) {
618 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
619 intel_disable_fbc(dev);
620 }
11be49eb 621 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 622}
623
c921aba8
DV		 624static void i915_pineview_get_mem_freq(struct drm_device *dev)
625{
50227e1c 626 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 627 u32 tmp;
628
629 tmp = I915_READ(CLKCFG);
630
631 switch (tmp & CLKCFG_FSB_MASK) {
632 case CLKCFG_FSB_533:
633 dev_priv->fsb_freq = 533; /* 133*4 */
634 break;
635 case CLKCFG_FSB_800:
636 dev_priv->fsb_freq = 800; /* 200*4 */
637 break;
638 case CLKCFG_FSB_667:
639 dev_priv->fsb_freq = 667; /* 167*4 */
640 break;
641 case CLKCFG_FSB_400:
642 dev_priv->fsb_freq = 400; /* 100*4 */
643 break;
644 }
645
646 switch (tmp & CLKCFG_MEM_MASK) {
647 case CLKCFG_MEM_533:
648 dev_priv->mem_freq = 533;
649 break;
650 case CLKCFG_MEM_667:
651 dev_priv->mem_freq = 667;
652 break;
653 case CLKCFG_MEM_800:
654 dev_priv->mem_freq = 800;
655 break;
656 }
657
658 /* detect pineview DDR3 setting */
659 tmp = I915_READ(CSHRDDR3CTL);
660 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
661}
662
663static void i915_ironlake_get_mem_freq(struct drm_device *dev)
664{
50227e1c 665 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 666 u16 ddrpll, csipll;
667
668 ddrpll = I915_READ16(DDRMPLL1);
669 csipll = I915_READ16(CSIPLL0);
670
671 switch (ddrpll & 0xff) {
672 case 0xc:
673 dev_priv->mem_freq = 800;
674 break;
675 case 0x10:
676 dev_priv->mem_freq = 1066;
677 break;
678 case 0x14:
679 dev_priv->mem_freq = 1333;
680 break;
681 case 0x18:
682 dev_priv->mem_freq = 1600;
683 break;
684 default:
685 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
686 ddrpll & 0xff);
687 dev_priv->mem_freq = 0;
688 break;
689 }
690
20e4d407 691 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 692
693 switch (csipll & 0x3ff) {
694 case 0x00c:
695 dev_priv->fsb_freq = 3200;
696 break;
697 case 0x00e:
698 dev_priv->fsb_freq = 3733;
699 break;
700 case 0x010:
701 dev_priv->fsb_freq = 4266;
702 break;
703 case 0x012:
704 dev_priv->fsb_freq = 4800;
705 break;
706 case 0x014:
707 dev_priv->fsb_freq = 5333;
708 break;
709 case 0x016:
710 dev_priv->fsb_freq = 5866;
711 break;
712 case 0x018:
713 dev_priv->fsb_freq = 6400;
714 break;
715 default:
716 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
717 csipll & 0x3ff);
718 dev_priv->fsb_freq = 0;
719 break;
720 }
721
722 if (dev_priv->fsb_freq == 3200) {
20e4d407 723 dev_priv->ips.c_m = 0;
c921aba8 724 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 725 dev_priv->ips.c_m = 1;
c921aba8 726 } else {
20e4d407 727 dev_priv->ips.c_m = 2;
c921aba8
DV		 728 }
729}
730
b445e3b0
ED		 731static const struct cxsr_latency cxsr_latency_table[] = {
732 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
733 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
734 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
735 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
736 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
737
738 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
739 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
740 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
741 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
742 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
743
744 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
745 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
746 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
747 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
748 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
749
750 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
751 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
752 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
753 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
754 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
755
756 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
757 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
758 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
759 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
760 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
761
762 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
763 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
764 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
765 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
766 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
767};
768
63c62275 769static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 770 int is_ddr3,
771 int fsb,
772 int mem)
773{
774 const struct cxsr_latency *latency;
775 int i;
776
777 if (fsb == 0 || mem == 0)
778 return NULL;
779
780 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
781 latency = &cxsr_latency_table[i];
782 if (is_desktop == latency->is_desktop &&
783 is_ddr3 == latency->is_ddr3 &&
784 fsb == latency->fsb_freq && mem == latency->mem_freq)
785 return latency;
786 }
787
788 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
789
790 return NULL;
791}
792
1fa61106 793static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 794{
795 struct drm_i915_private *dev_priv = dev->dev_private;
796
797 /* deactivate cxsr */
798 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
799}
800
801/*
802 * Latency for FIFO fetches is dependent on several factors:
803 * - memory configuration (speed, channels)
804 * - chipset
805 * - current MCH state
806 * It can be fairly high in some situations, so here we assume a fairly
807 * pessimal value. It's a tradeoff between extra memory fetches (if we
808 * set this value too high, the FIFO will fetch frequently to stay full)
809 * and power consumption (set it too low to save power and we might see
810 * FIFO underruns and display "flicker").
811 *
812 * A value of 5us seems to be a good balance; safe for very low end
813 * platforms but not overly aggressive on lower latency configs.
814 */
815static const int latency_ns = 5000;
816
1fa61106 817static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 818{
819 struct drm_i915_private *dev_priv = dev->dev_private;
820 uint32_t dsparb = I915_READ(DSPARB);
821 int size;
822
823 size = dsparb & 0x7f;
824 if (plane)
825 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
826
827 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
828 plane ? "B" : "A", size);
829
830 return size;
831}
832
feb56b93 833static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 834{
835 struct drm_i915_private *dev_priv = dev->dev_private;
836 uint32_t dsparb = I915_READ(DSPARB);
837 int size;
838
839 size = dsparb & 0x1ff;
840 if (plane)
841 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
842 size >>= 1; /* Convert to cachelines */
843
844 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
845 plane ? "B" : "A", size);
846
847 return size;
848}
849
1fa61106 850static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 851{
852 struct drm_i915_private *dev_priv = dev->dev_private;
853 uint32_t dsparb = I915_READ(DSPARB);
854 int size;
855
856 size = dsparb & 0x7f;
857 size >>= 2; /* Convert to cachelines */
858
859 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
860 plane ? "B" : "A",
861 size);
862
863 return size;
864}
865
b445e3b0
ED		 866/* Pineview has different values for various configs */
867static const struct intel_watermark_params pineview_display_wm = {
868 PINEVIEW_DISPLAY_FIFO,
869 PINEVIEW_MAX_WM,
870 PINEVIEW_DFT_WM,
871 PINEVIEW_GUARD_WM,
872 PINEVIEW_FIFO_LINE_SIZE
873};
874static const struct intel_watermark_params pineview_display_hplloff_wm = {
875 PINEVIEW_DISPLAY_FIFO,
876 PINEVIEW_MAX_WM,
877 PINEVIEW_DFT_HPLLOFF_WM,
878 PINEVIEW_GUARD_WM,
879 PINEVIEW_FIFO_LINE_SIZE
880};
881static const struct intel_watermark_params pineview_cursor_wm = {
882 PINEVIEW_CURSOR_FIFO,
883 PINEVIEW_CURSOR_MAX_WM,
884 PINEVIEW_CURSOR_DFT_WM,
885 PINEVIEW_CURSOR_GUARD_WM,
886 PINEVIEW_FIFO_LINE_SIZE,
887};
888static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
889 PINEVIEW_CURSOR_FIFO,
890 PINEVIEW_CURSOR_MAX_WM,
891 PINEVIEW_CURSOR_DFT_WM,
892 PINEVIEW_CURSOR_GUARD_WM,
893 PINEVIEW_FIFO_LINE_SIZE
894};
895static const struct intel_watermark_params g4x_wm_info = {
896 G4X_FIFO_SIZE,
897 G4X_MAX_WM,
898 G4X_MAX_WM,
899 2,
900 G4X_FIFO_LINE_SIZE,
901};
902static const struct intel_watermark_params g4x_cursor_wm_info = {
903 I965_CURSOR_FIFO,
904 I965_CURSOR_MAX_WM,
905 I965_CURSOR_DFT_WM,
906 2,
907 G4X_FIFO_LINE_SIZE,
908};
909static const struct intel_watermark_params valleyview_wm_info = {
910 VALLEYVIEW_FIFO_SIZE,
911 VALLEYVIEW_MAX_WM,
912 VALLEYVIEW_MAX_WM,
913 2,
914 G4X_FIFO_LINE_SIZE,
915};
916static const struct intel_watermark_params valleyview_cursor_wm_info = {
917 I965_CURSOR_FIFO,
918 VALLEYVIEW_CURSOR_MAX_WM,
919 I965_CURSOR_DFT_WM,
920 2,
921 G4X_FIFO_LINE_SIZE,
922};
923static const struct intel_watermark_params i965_cursor_wm_info = {
924 I965_CURSOR_FIFO,
925 I965_CURSOR_MAX_WM,
926 I965_CURSOR_DFT_WM,
927 2,
928 I915_FIFO_LINE_SIZE,
929};
930static const struct intel_watermark_params i945_wm_info = {
931 I945_FIFO_SIZE,
932 I915_MAX_WM,
933 1,
934 2,
935 I915_FIFO_LINE_SIZE
936};
937static const struct intel_watermark_params i915_wm_info = {
938 I915_FIFO_SIZE,
939 I915_MAX_WM,
940 1,
941 2,
942 I915_FIFO_LINE_SIZE
943};
feb56b93 944static const struct intel_watermark_params i830_wm_info = {
b445e3b0
ED		 945 I855GM_FIFO_SIZE,
946 I915_MAX_WM,
947 1,
948 2,
949 I830_FIFO_LINE_SIZE
950};
feb56b93 951static const struct intel_watermark_params i845_wm_info = {
b445e3b0
ED		 952 I830_FIFO_SIZE,
953 I915_MAX_WM,
954 1,
955 2,
956 I830_FIFO_LINE_SIZE
957};
958
b445e3b0
ED		 959/**
960 * intel_calculate_wm - calculate watermark level
961 * @clock_in_khz: pixel clock
962 * @wm: chip FIFO params
963 * @pixel_size: display pixel size
964 * @latency_ns: memory latency for the platform
965 *
966 * Calculate the watermark level (the level at which the display plane will
967 * start fetching from memory again). Each chip has a different display
968 * FIFO size and allocation, so the caller needs to figure that out and pass
969 * in the correct intel_watermark_params structure.
970 *
971 * As the pixel clock runs, the FIFO will be drained at a rate that depends
972 * on the pixel size. When it reaches the watermark level, it'll start
973 * fetching FIFO line sized based chunks from memory until the FIFO fills
974 * past the watermark point. If the FIFO drains completely, a FIFO underrun
975 * will occur, and a display engine hang could result.
976 */
977static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
978 const struct intel_watermark_params *wm,
979 int fifo_size,
980 int pixel_size,
981 unsigned long latency_ns)
982{
983 long entries_required, wm_size;
984
985 /*
986 * Note: we need to make sure we don't overflow for various clock &
987 * latency values.
988 * clocks go from a few thousand to several hundred thousand.
989 * latency is usually a few thousand
990 */
991 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
992 1000;
993 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
994
995 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
996
997 wm_size = fifo_size - (entries_required + wm->guard_size);
998
999 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1000
1001 /* Don't promote wm_size to unsigned... */
1002 if (wm_size > (long)wm->max_wm)
1003 wm_size = wm->max_wm;
1004 if (wm_size <= 0)
1005 wm_size = wm->default_wm;
1006 return wm_size;
1007}
1008
1009static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1010{
1011 struct drm_crtc *crtc, *enabled = NULL;
1012
1013 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 1014 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1015 if (enabled)
1016 return NULL;
1017 enabled = crtc;
1018 }
1019 }
1020
1021 return enabled;
1022}
1023
46ba614c 1024static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1025{
46ba614c 1026 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1027 struct drm_i915_private *dev_priv = dev->dev_private;
1028 struct drm_crtc *crtc;
1029 const struct cxsr_latency *latency;
1030 u32 reg;
1031 unsigned long wm;
1032
1033 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1034 dev_priv->fsb_freq, dev_priv->mem_freq);
1035 if (!latency) {
1036 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1037 pineview_disable_cxsr(dev);
1038 return;
1039 }
1040
1041 crtc = single_enabled_crtc(dev);
1042 if (crtc) {
241bfc38 1043 const struct drm_display_mode *adjusted_mode;
f4510a27 1044 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
241bfc38
DL		 1045 int clock;
1046
1047 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1048 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 1049
1050 /* Display SR */
1051 wm = intel_calculate_wm(clock, &pineview_display_wm,
1052 pineview_display_wm.fifo_size,
1053 pixel_size, latency->display_sr);
1054 reg = I915_READ(DSPFW1);
1055 reg &= ~DSPFW_SR_MASK;
1056 reg |= wm << DSPFW_SR_SHIFT;
1057 I915_WRITE(DSPFW1, reg);
1058 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1059
1060 /* cursor SR */
1061 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1062 pineview_display_wm.fifo_size,
1063 pixel_size, latency->cursor_sr);
1064 reg = I915_READ(DSPFW3);
1065 reg &= ~DSPFW_CURSOR_SR_MASK;
1066 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1067 I915_WRITE(DSPFW3, reg);
1068
1069 /* Display HPLL off SR */
1070 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1071 pineview_display_hplloff_wm.fifo_size,
1072 pixel_size, latency->display_hpll_disable);
1073 reg = I915_READ(DSPFW3);
1074 reg &= ~DSPFW_HPLL_SR_MASK;
1075 reg |= wm & DSPFW_HPLL_SR_MASK;
1076 I915_WRITE(DSPFW3, reg);
1077
1078 /* cursor HPLL off SR */
1079 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1080 pineview_display_hplloff_wm.fifo_size,
1081 pixel_size, latency->cursor_hpll_disable);
1082 reg = I915_READ(DSPFW3);
1083 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1084 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1085 I915_WRITE(DSPFW3, reg);
1086 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1087
1088 /* activate cxsr */
1089 I915_WRITE(DSPFW3,
1090 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1091 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1092 } else {
1093 pineview_disable_cxsr(dev);
1094 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1095 }
1096}
1097
1098static bool g4x_compute_wm0(struct drm_device *dev,
1099 int plane,
1100 const struct intel_watermark_params *display,
1101 int display_latency_ns,
1102 const struct intel_watermark_params *cursor,
1103 int cursor_latency_ns,
1104 int *plane_wm,
1105 int *cursor_wm)
1106{
1107 struct drm_crtc *crtc;
4fe8590a 1108 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1109 int htotal, hdisplay, clock, pixel_size;
1110 int line_time_us, line_count;
1111 int entries, tlb_miss;
1112
1113 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1114 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1115 *cursor_wm = cursor->guard_size;
1116 *plane_wm = display->guard_size;
1117 return false;
1118 }
1119
4fe8590a 1120 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1121 clock = adjusted_mode->crtc_clock;
fec8cba3 1122 htotal = adjusted_mode->crtc_htotal;
37327abd 1123 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1124 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1125
1126 /* Use the small buffer method to calculate plane watermark */
1127 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1128 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1129 if (tlb_miss > 0)
1130 entries += tlb_miss;
1131 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1132 *plane_wm = entries + display->guard_size;
1133 if (*plane_wm > (int)display->max_wm)
1134 *plane_wm = display->max_wm;
1135
1136 /* Use the large buffer method to calculate cursor watermark */
922044c9 1137 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 1138 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
7bb836dd 1139 entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
b445e3b0
ED		 1140 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1141 if (tlb_miss > 0)
1142 entries += tlb_miss;
1143 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1144 *cursor_wm = entries + cursor->guard_size;
1145 if (*cursor_wm > (int)cursor->max_wm)
1146 *cursor_wm = (int)cursor->max_wm;
1147
1148 return true;
1149}
1150
1151/*
1152 * Check the wm result.
1153 *
1154 * If any calculated watermark values is larger than the maximum value that
1155 * can be programmed into the associated watermark register, that watermark
1156 * must be disabled.
1157 */
1158static bool g4x_check_srwm(struct drm_device *dev,
1159 int display_wm, int cursor_wm,
1160 const struct intel_watermark_params *display,
1161 const struct intel_watermark_params *cursor)
1162{
1163 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1164 display_wm, cursor_wm);
1165
1166 if (display_wm > display->max_wm) {
1167 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1168 display_wm, display->max_wm);
1169 return false;
1170 }
1171
1172 if (cursor_wm > cursor->max_wm) {
1173 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1174 cursor_wm, cursor->max_wm);
1175 return false;
1176 }
1177
1178 if (!(display_wm || cursor_wm)) {
1179 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1180 return false;
1181 }
1182
1183 return true;
1184}
1185
1186static bool g4x_compute_srwm(struct drm_device *dev,
1187 int plane,
1188 int latency_ns,
1189 const struct intel_watermark_params *display,
1190 const struct intel_watermark_params *cursor,
1191 int *display_wm, int *cursor_wm)
1192{
1193 struct drm_crtc *crtc;
4fe8590a 1194 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1195 int hdisplay, htotal, pixel_size, clock;
1196 unsigned long line_time_us;
1197 int line_count, line_size;
1198 int small, large;
1199 int entries;
1200
1201 if (!latency_ns) {
1202 *display_wm = *cursor_wm = 0;
1203 return false;
1204 }
1205
1206 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a 1207 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1208 clock = adjusted_mode->crtc_clock;
fec8cba3 1209 htotal = adjusted_mode->crtc_htotal;
37327abd 1210 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1211 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0 1212
922044c9 1213 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1214 line_count = (latency_ns / line_time_us + 1000) / 1000;
1215 line_size = hdisplay * pixel_size;
1216
1217 /* Use the minimum of the small and large buffer method for primary */
1218 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1219 large = line_count * line_size;
1220
1221 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1222 *display_wm = entries + display->guard_size;
1223
1224 /* calculate the self-refresh watermark for display cursor */
7bb836dd 1225 entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
b445e3b0
ED		 1226 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1227 *cursor_wm = entries + cursor->guard_size;
1228
1229 return g4x_check_srwm(dev,
1230 *display_wm, *cursor_wm,
1231 display, cursor);
1232}
1233
1234static bool vlv_compute_drain_latency(struct drm_device *dev,
1235 int plane,
1236 int *plane_prec_mult,
1237 int *plane_dl,
1238 int *cursor_prec_mult,
1239 int *cursor_dl)
1240{
1241 struct drm_crtc *crtc;
1242 int clock, pixel_size;
1243 int entries;
1244
1245 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1246 if (!intel_crtc_active(crtc))
b445e3b0
ED		 1247 return false;
1248
241bfc38 1249 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
f4510a27 1250 pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
b445e3b0
ED		 1251
1252 entries = (clock / 1000) * pixel_size;
1253 *plane_prec_mult = (entries > 256) ?
1254 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1255 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1256 pixel_size);
1257
1258 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1259 *cursor_prec_mult = (entries > 256) ?
1260 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1261 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1262
1263 return true;
1264}
1265
1266/*
1267 * Update drain latency registers of memory arbiter
1268 *
1269 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1270 * to be programmed. Each plane has a drain latency multiplier and a drain
1271 * latency value.
1272 */
1273
1274static void vlv_update_drain_latency(struct drm_device *dev)
1275{
1276 struct drm_i915_private *dev_priv = dev->dev_private;
1277 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1278 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1279 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1280 either 16 or 32 */
1281
1282 /* For plane A, Cursor A */
1283 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1284 &cursor_prec_mult, &cursora_dl)) {
1285 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1286 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1287 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1288 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1289
1290 I915_WRITE(VLV_DDL1, cursora_prec |
1291 (cursora_dl << DDL_CURSORA_SHIFT) |
1292 planea_prec | planea_dl);
1293 }
1294
1295 /* For plane B, Cursor B */
1296 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1297 &cursor_prec_mult, &cursorb_dl)) {
1298 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1299 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1300 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1301 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1302
1303 I915_WRITE(VLV_DDL2, cursorb_prec |
1304 (cursorb_dl << DDL_CURSORB_SHIFT) |
1305 planeb_prec | planeb_dl);
1306 }
1307}
1308
1309#define single_plane_enabled(mask) is_power_of_2(mask)
1310
46ba614c 1311static void valleyview_update_wm(struct drm_crtc *crtc)
b445e3b0 1312{
46ba614c 1313 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1314 static const int sr_latency_ns = 12000;
1315 struct drm_i915_private *dev_priv = dev->dev_private;
1316 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1317 int plane_sr, cursor_sr;
af6c4575 1318 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0
ED		 1319 unsigned int enabled = 0;
1320
1321 vlv_update_drain_latency(dev);
1322
51cea1f4 1323 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1324 &valleyview_wm_info, latency_ns,
1325 &valleyview_cursor_wm_info, latency_ns,
1326 &planea_wm, &cursora_wm))
51cea1f4 1327 enabled |= 1 << PIPE_A;
b445e3b0 1328
51cea1f4 1329 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1330 &valleyview_wm_info, latency_ns,
1331 &valleyview_cursor_wm_info, latency_ns,
1332 &planeb_wm, &cursorb_wm))
51cea1f4 1333 enabled |= 1 << PIPE_B;
b445e3b0 1334
b445e3b0
ED		 1335 if (single_plane_enabled(enabled) &&
1336 g4x_compute_srwm(dev, ffs(enabled) - 1,
1337 sr_latency_ns,
1338 &valleyview_wm_info,
1339 &valleyview_cursor_wm_info,
af6c4575
CW		 1340 &plane_sr, &ignore_cursor_sr) &&
1341 g4x_compute_srwm(dev, ffs(enabled) - 1,
1342 2*sr_latency_ns,
1343 &valleyview_wm_info,
1344 &valleyview_cursor_wm_info,
52bd02d8 1345 &ignore_plane_sr, &cursor_sr)) {
b445e3b0 1346 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
52bd02d8 1347 } else {
b445e3b0
ED		 1348 I915_WRITE(FW_BLC_SELF_VLV,
1349 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
52bd02d8
CW		 1350 plane_sr = cursor_sr = 0;
1351 }
b445e3b0
ED		 1352
1353 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1354 planea_wm, cursora_wm,
1355 planeb_wm, cursorb_wm,
1356 plane_sr, cursor_sr);
1357
1358 I915_WRITE(DSPFW1,
1359 (plane_sr << DSPFW_SR_SHIFT) |
1360 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1361 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1362 planea_wm);
1363 I915_WRITE(DSPFW2,
8c919b28 1364 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1365 (cursora_wm << DSPFW_CURSORA_SHIFT));
1366 I915_WRITE(DSPFW3,
8c919b28
CW		 1367 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1368 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
b445e3b0
ED		 1369}
1370
46ba614c 1371static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1372{
46ba614c 1373 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1374 static const int sr_latency_ns = 12000;
1375 struct drm_i915_private *dev_priv = dev->dev_private;
1376 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1377 int plane_sr, cursor_sr;
1378 unsigned int enabled = 0;
1379
51cea1f4 1380 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1381 &g4x_wm_info, latency_ns,
1382 &g4x_cursor_wm_info, latency_ns,
1383 &planea_wm, &cursora_wm))
51cea1f4 1384 enabled |= 1 << PIPE_A;
b445e3b0 1385
51cea1f4 1386 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1387 &g4x_wm_info, latency_ns,
1388 &g4x_cursor_wm_info, latency_ns,
1389 &planeb_wm, &cursorb_wm))
51cea1f4 1390 enabled |= 1 << PIPE_B;
b445e3b0 1391
b445e3b0
ED		 1392 if (single_plane_enabled(enabled) &&
1393 g4x_compute_srwm(dev, ffs(enabled) - 1,
1394 sr_latency_ns,
1395 &g4x_wm_info,
1396 &g4x_cursor_wm_info,
52bd02d8 1397 &plane_sr, &cursor_sr)) {
b445e3b0 1398 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
52bd02d8 1399 } else {
b445e3b0
ED		 1400 I915_WRITE(FW_BLC_SELF,
1401 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
52bd02d8
CW		 1402 plane_sr = cursor_sr = 0;
1403 }
b445e3b0
ED		 1404
1405 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1406 planea_wm, cursora_wm,
1407 planeb_wm, cursorb_wm,
1408 plane_sr, cursor_sr);
1409
1410 I915_WRITE(DSPFW1,
1411 (plane_sr << DSPFW_SR_SHIFT) |
1412 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1413 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1414 planea_wm);
1415 I915_WRITE(DSPFW2,
8c919b28 1416 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1417 (cursora_wm << DSPFW_CURSORA_SHIFT));
1418 /* HPLL off in SR has some issues on G4x... disable it */
1419 I915_WRITE(DSPFW3,
8c919b28 1420 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0
ED		 1421 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1422}
1423
46ba614c 1424static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1425{
46ba614c 1426 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1427 struct drm_i915_private *dev_priv = dev->dev_private;
1428 struct drm_crtc *crtc;
1429 int srwm = 1;
1430 int cursor_sr = 16;
1431
1432 /* Calc sr entries for one plane configs */
1433 crtc = single_enabled_crtc(dev);
1434 if (crtc) {
1435 /* self-refresh has much higher latency */
1436 static const int sr_latency_ns = 12000;
4fe8590a
VS		 1437 const struct drm_display_mode *adjusted_mode =
1438 &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1439 int clock = adjusted_mode->crtc_clock;
fec8cba3 1440 int htotal = adjusted_mode->crtc_htotal;
37327abd 1441 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1442 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1443 unsigned long line_time_us;
1444 int entries;
1445
922044c9 1446 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1447
1448 /* Use ns/us then divide to preserve precision */
1449 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1450 pixel_size * hdisplay;
1451 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1452 srwm = I965_FIFO_SIZE - entries;
1453 if (srwm < 0)
1454 srwm = 1;
1455 srwm &= 0x1ff;
1456 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1457 entries, srwm);
1458
1459 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
7bb836dd 1460 pixel_size * to_intel_crtc(crtc)->cursor_width;
b445e3b0
ED		 1461 entries = DIV_ROUND_UP(entries,
1462 i965_cursor_wm_info.cacheline_size);
1463 cursor_sr = i965_cursor_wm_info.fifo_size -
1464 (entries + i965_cursor_wm_info.guard_size);
1465
1466 if (cursor_sr > i965_cursor_wm_info.max_wm)
1467 cursor_sr = i965_cursor_wm_info.max_wm;
1468
1469 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1470 "cursor %d\n", srwm, cursor_sr);
1471
1472 if (IS_CRESTLINE(dev))
1473 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1474 } else {
1475 /* Turn off self refresh if both pipes are enabled */
1476 if (IS_CRESTLINE(dev))
1477 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1478 & ~FW_BLC_SELF_EN);
1479 }
1480
1481 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1482 srwm);
1483
1484 /* 965 has limitations... */
1485 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1486 (8 << 16) | (8 << 8) | (8 << 0));
1487 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1488 /* update cursor SR watermark */
1489 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1490}
1491
46ba614c 1492static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1493{
46ba614c 1494 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1495 struct drm_i915_private *dev_priv = dev->dev_private;
1496 const struct intel_watermark_params *wm_info;
1497 uint32_t fwater_lo;
1498 uint32_t fwater_hi;
1499 int cwm, srwm = 1;
1500 int fifo_size;
1501 int planea_wm, planeb_wm;
1502 struct drm_crtc *crtc, *enabled = NULL;
1503
1504 if (IS_I945GM(dev))
1505 wm_info = &i945_wm_info;
1506 else if (!IS_GEN2(dev))
1507 wm_info = &i915_wm_info;
1508 else
feb56b93 1509 wm_info = &i830_wm_info;
b445e3b0
ED		 1510
1511 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1512 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1513 if (intel_crtc_active(crtc)) {
241bfc38 1514 const struct drm_display_mode *adjusted_mode;
f4510a27 1515 int cpp = crtc->primary->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1516 if (IS_GEN2(dev))
1517 cpp = 4;
1518
241bfc38
DL		 1519 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1520 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1521 wm_info, fifo_size, cpp,
b445e3b0
ED		 1522 latency_ns);
1523 enabled = crtc;
1524 } else
1525 planea_wm = fifo_size - wm_info->guard_size;
1526
1527 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1528 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1529 if (intel_crtc_active(crtc)) {
241bfc38 1530 const struct drm_display_mode *adjusted_mode;
f4510a27 1531 int cpp = crtc->primary->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1532 if (IS_GEN2(dev))
1533 cpp = 4;
1534
241bfc38
DL		 1535 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1536 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1537 wm_info, fifo_size, cpp,
b445e3b0
ED		 1538 latency_ns);
1539 if (enabled == NULL)
1540 enabled = crtc;
1541 else
1542 enabled = NULL;
1543 } else
1544 planeb_wm = fifo_size - wm_info->guard_size;
1545
1546 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1547
2ab1bc9d
DV		 1548 if (IS_I915GM(dev) && enabled) {
1549 struct intel_framebuffer *fb;
1550
1551 fb = to_intel_framebuffer(enabled->primary->fb);
1552
1553 /* self-refresh seems busted with untiled */
1554 if (fb->obj->tiling_mode == I915_TILING_NONE)
1555 enabled = NULL;
1556 }
1557
b445e3b0
ED		 1558 /*
1559 * Overlay gets an aggressive default since video jitter is bad.
1560 */
1561 cwm = 2;
1562
1563 /* Play safe and disable self-refresh before adjusting watermarks. */
1564 if (IS_I945G(dev) || IS_I945GM(dev))
1565 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1566 else if (IS_I915GM(dev))
3f2dc5ac 1567 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_SELF_EN));
b445e3b0
ED		 1568
1569 /* Calc sr entries for one plane configs */
1570 if (HAS_FW_BLC(dev) && enabled) {
1571 /* self-refresh has much higher latency */
1572 static const int sr_latency_ns = 6000;
4fe8590a
VS		 1573 const struct drm_display_mode *adjusted_mode =
1574 &to_intel_crtc(enabled)->config.adjusted_mode;
241bfc38 1575 int clock = adjusted_mode->crtc_clock;
fec8cba3 1576 int htotal = adjusted_mode->crtc_htotal;
f727b490 1577 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
f4510a27 1578 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1579 unsigned long line_time_us;
1580 int entries;
1581
922044c9 1582 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1583
1584 /* Use ns/us then divide to preserve precision */
1585 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1586 pixel_size * hdisplay;
1587 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1588 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1589 srwm = wm_info->fifo_size - entries;
1590 if (srwm < 0)
1591 srwm = 1;
1592
1593 if (IS_I945G(dev) || IS_I945GM(dev))
1594 I915_WRITE(FW_BLC_SELF,
1595 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1596 else if (IS_I915GM(dev))
1597 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1598 }
1599
1600 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1601 planea_wm, planeb_wm, cwm, srwm);
1602
1603 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1604 fwater_hi = (cwm & 0x1f);
1605
1606 /* Set request length to 8 cachelines per fetch */
1607 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1608 fwater_hi = fwater_hi | (1 << 8);
1609
1610 I915_WRITE(FW_BLC, fwater_lo);
1611 I915_WRITE(FW_BLC2, fwater_hi);
1612
1613 if (HAS_FW_BLC(dev)) {
1614 if (enabled) {
1615 if (IS_I945G(dev) || IS_I945GM(dev))
1616 I915_WRITE(FW_BLC_SELF,
1617 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1618 else if (IS_I915GM(dev))
3f2dc5ac 1619 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_SELF_EN));
b445e3b0
ED		 1620 DRM_DEBUG_KMS("memory self refresh enabled\n");
1621 } else
1622 DRM_DEBUG_KMS("memory self refresh disabled\n");
1623 }
1624}
1625
feb56b93 1626static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1627{
46ba614c 1628 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1629 struct drm_i915_private *dev_priv = dev->dev_private;
1630 struct drm_crtc *crtc;
241bfc38 1631 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1632 uint32_t fwater_lo;
1633 int planea_wm;
1634
1635 crtc = single_enabled_crtc(dev);
1636 if (crtc == NULL)
1637 return;
1638
241bfc38
DL		 1639 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1640 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1641 &i845_wm_info,
b445e3b0 1642 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1643 4, latency_ns);
b445e3b0
ED		 1644 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1645 fwater_lo |= (3<<8) | planea_wm;
1646
1647 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1648
1649 I915_WRITE(FW_BLC, fwater_lo);
1650}
1651
3658729a
VS		 1652static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1653 struct drm_crtc *crtc)
801bcfff
PZ		 1654{
1655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fd4daa9c 1656 uint32_t pixel_rate;
801bcfff 1657
241bfc38 1658 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
801bcfff
PZ		 1659
1660 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1661 * adjust the pixel_rate here. */
1662
fd4daa9c 1663 if (intel_crtc->config.pch_pfit.enabled) {
801bcfff 1664 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
fd4daa9c 1665 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
801bcfff 1666
37327abd
VS		 1667 pipe_w = intel_crtc->config.pipe_src_w;
1668 pipe_h = intel_crtc->config.pipe_src_h;
801bcfff
PZ		 1669 pfit_w = (pfit_size >> 16) & 0xFFFF;
1670 pfit_h = pfit_size & 0xFFFF;
1671 if (pipe_w < pfit_w)
1672 pipe_w = pfit_w;
1673 if (pipe_h < pfit_h)
1674 pipe_h = pfit_h;
1675
1676 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1677 pfit_w * pfit_h);
1678 }
1679
1680 return pixel_rate;
1681}
1682
37126462 1683/* latency must be in 0.1us units. */
23297044 1684static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1685 uint32_t latency)
1686{
1687 uint64_t ret;
1688
3312ba65
VS		 1689 if (WARN(latency == 0, "Latency value missing\n"))
1690 return UINT_MAX;
1691
801bcfff
PZ		 1692 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1693 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1694
1695 return ret;
1696}
1697
37126462 1698/* latency must be in 0.1us units. */
23297044 1699static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1700 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1701 uint32_t latency)
1702{
1703 uint32_t ret;
1704
3312ba65
VS		 1705 if (WARN(latency == 0, "Latency value missing\n"))
1706 return UINT_MAX;
1707
801bcfff
PZ		 1708 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1709 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1710 ret = DIV_ROUND_UP(ret, 64) + 2;
1711 return ret;
1712}
1713
23297044 1714static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1715 uint8_t bytes_per_pixel)
1716{
1717 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1718}
1719
820c1980 1720struct ilk_pipe_wm_parameters {
801bcfff 1721 bool active;
801bcfff
PZ		 1722 uint32_t pipe_htotal;
1723 uint32_t pixel_rate;
c35426d2
VS		 1724 struct intel_plane_wm_parameters pri;
1725 struct intel_plane_wm_parameters spr;
1726 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 1727};
1728
820c1980 1729struct ilk_wm_maximums {
cca32e9a
PZ		 1730 uint16_t pri;
1731 uint16_t spr;
1732 uint16_t cur;
1733 uint16_t fbc;
1734};
1735
240264f4
VS		 1736/* used in computing the new watermarks state */
1737struct intel_wm_config {
1738 unsigned int num_pipes_active;
1739 bool sprites_enabled;
1740 bool sprites_scaled;
240264f4
VS		 1741};
1742
37126462
VS		 1743/*
1744 * For both WM_PIPE and WM_LP.
1745 * mem_value must be in 0.1us units.
1746 */
820c1980 1747static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
cca32e9a
PZ		 1748 uint32_t mem_value,
1749 bool is_lp)
801bcfff 1750{
cca32e9a
PZ		 1751 uint32_t method1, method2;
1752
c35426d2 1753 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 1754 return 0;
1755
23297044 1756 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1757 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1758 mem_value);
1759
1760 if (!is_lp)
1761 return method1;
1762
23297044 1763 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 1764 params->pipe_htotal,
c35426d2
VS		 1765 params->pri.horiz_pixels,
1766 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1767 mem_value);
1768
1769 return min(method1, method2);
801bcfff
PZ		 1770}
1771
37126462
VS		 1772/*
1773 * For both WM_PIPE and WM_LP.
1774 * mem_value must be in 0.1us units.
1775 */
820c1980 1776static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1777 uint32_t mem_value)
1778{
1779 uint32_t method1, method2;
1780
c35426d2 1781 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 1782 return 0;
1783
23297044 1784 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1785 params->spr.bytes_per_pixel,
801bcfff 1786 mem_value);
23297044 1787 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 1788 params->pipe_htotal,
c35426d2
VS		 1789 params->spr.horiz_pixels,
1790 params->spr.bytes_per_pixel,
801bcfff
PZ		 1791 mem_value);
1792 return min(method1, method2);
1793}
1794
37126462
VS		 1795/*
1796 * For both WM_PIPE and WM_LP.
1797 * mem_value must be in 0.1us units.
1798 */
820c1980 1799static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1800 uint32_t mem_value)
1801{
c35426d2 1802 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 1803 return 0;
1804
23297044 1805 return ilk_wm_method2(params->pixel_rate,
801bcfff 1806 params->pipe_htotal,
c35426d2
VS		 1807 params->cur.horiz_pixels,
1808 params->cur.bytes_per_pixel,
801bcfff
PZ		 1809 mem_value);
1810}
1811
cca32e9a 1812/* Only for WM_LP. */
820c1980 1813static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1fda9882 1814 uint32_t pri_val)
cca32e9a 1815{
c35426d2 1816 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 1817 return 0;
1818
23297044 1819 return ilk_wm_fbc(pri_val,
c35426d2
VS		 1820 params->pri.horiz_pixels,
1821 params->pri.bytes_per_pixel);
cca32e9a
PZ		 1822}
1823
158ae64f
VS		 1824static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1825{
416f4727
VS		 1826 if (INTEL_INFO(dev)->gen >= 8)
1827 return 3072;
1828 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1829 return 768;
1830 else
1831 return 512;
1832}
1833
4e975081
VS		 1834static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1835 int level, bool is_sprite)
1836{
1837 if (INTEL_INFO(dev)->gen >= 8)
1838 /* BDW primary/sprite plane watermarks */
1839 return level == 0 ? 255 : 2047;
1840 else if (INTEL_INFO(dev)->gen >= 7)
1841 /* IVB/HSW primary/sprite plane watermarks */
1842 return level == 0 ? 127 : 1023;
1843 else if (!is_sprite)
1844 /* ILK/SNB primary plane watermarks */
1845 return level == 0 ? 127 : 511;
1846 else
1847 /* ILK/SNB sprite plane watermarks */
1848 return level == 0 ? 63 : 255;
1849}
1850
1851static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1852 int level)
1853{
1854 if (INTEL_INFO(dev)->gen >= 7)
1855 return level == 0 ? 63 : 255;
1856 else
1857 return level == 0 ? 31 : 63;
1858}
1859
1860static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1861{
1862 if (INTEL_INFO(dev)->gen >= 8)
1863 return 31;
1864 else
1865 return 15;
1866}
1867
158ae64f
VS		 1868/* Calculate the maximum primary/sprite plane watermark */
1869static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1870 int level,
240264f4 1871 const struct intel_wm_config *config,
158ae64f
VS		 1872 enum intel_ddb_partitioning ddb_partitioning,
1873 bool is_sprite)
1874{
1875 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1876
1877 /* if sprites aren't enabled, sprites get nothing */
240264f4 1878 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1879 return 0;
1880
1881 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1882 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1883 fifo_size /= INTEL_INFO(dev)->num_pipes;
1884
1885 /*
1886 * For some reason the non self refresh
1887 * FIFO size is only half of the self
1888 * refresh FIFO size on ILK/SNB.
1889 */
1890 if (INTEL_INFO(dev)->gen <= 6)
1891 fifo_size /= 2;
1892 }
1893
240264f4 1894 if (config->sprites_enabled) {
158ae64f
VS		 1895 /* level 0 is always calculated with 1:1 split */
1896 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1897 if (is_sprite)
1898 fifo_size *= 5;
1899 fifo_size /= 6;
1900 } else {
1901 fifo_size /= 2;
1902 }
1903 }
1904
1905 /* clamp to max that the registers can hold */
4e975081 1906 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1907}
1908
1909/* Calculate the maximum cursor plane watermark */
1910static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1911 int level,
1912 const struct intel_wm_config *config)
158ae64f
VS		 1913{
1914 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1915 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1916 return 64;
1917
1918 /* otherwise just report max that registers can hold */
4e975081 1919 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1920}
1921
d34ff9c6 1922static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1923 int level,
1924 const struct intel_wm_config *config,
1925 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1926 struct ilk_wm_maximums *max)
158ae64f 1927{
240264f4
VS		 1928 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1929 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1930 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1931 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1932}
1933
d9395655 1934static bool ilk_validate_wm_level(int level,
820c1980 1935 const struct ilk_wm_maximums *max,
d9395655 1936 struct intel_wm_level *result)
a9786a11
VS		 1937{
1938 bool ret;
1939
1940 /* already determined to be invalid? */
1941 if (!result->enable)
1942 return false;
1943
1944 result->enable = result->pri_val <= max->pri &&
1945 result->spr_val <= max->spr &&
1946 result->cur_val <= max->cur;
1947
1948 ret = result->enable;
1949
1950 /*
1951 * HACK until we can pre-compute everything,
1952 * and thus fail gracefully if LP0 watermarks
1953 * are exceeded...
1954 */
1955 if (level == 0 && !result->enable) {
1956 if (result->pri_val > max->pri)
1957 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1958 level, result->pri_val, max->pri);
1959 if (result->spr_val > max->spr)
1960 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1961 level, result->spr_val, max->spr);
1962 if (result->cur_val > max->cur)
1963 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1964 level, result->cur_val, max->cur);
1965
1966 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1967 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1968 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1969 result->enable = true;
1970 }
1971
a9786a11
VS		 1972 return ret;
1973}
1974
d34ff9c6 1975static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
6f5ddd17 1976 int level,
820c1980 1977 const struct ilk_pipe_wm_parameters *p,
1fd527cc 1978 struct intel_wm_level *result)
6f5ddd17
VS		 1979{
1980 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1981 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1982 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1983
1984 /* WM1+ latency values stored in 0.5us units */
1985 if (level > 0) {
1986 pri_latency *= 5;
1987 spr_latency *= 5;
1988 cur_latency *= 5;
1989 }
1990
1991 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
1992 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
1993 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
1994 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
1995 result->enable = true;
1996}
1997
801bcfff
PZ		 1998static uint32_t
1999hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2000{
2001 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 2003 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 2004 u32 linetime, ips_linetime;
1f8eeabf 2005
801bcfff
PZ		 2006 if (!intel_crtc_active(crtc))
2007 return 0;
1011d8c4 2008
1f8eeabf
ED		 2009 /* The WM are computed with base on how long it takes to fill a single
2010 * row at the given clock rate, multiplied by 8.
2011 * */
fec8cba3
JB		 2012 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2013 mode->crtc_clock);
2014 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
85a02deb 2015 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 2016
801bcfff
PZ		 2017 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2018 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2019}
2020
12b134df
VS		 2021static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2022{
2023 struct drm_i915_private *dev_priv = dev->dev_private;
2024
a42a5719 2025 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2026 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2027
2028 wm[0] = (sskpd >> 56) & 0xFF;
2029 if (wm[0] == 0)
2030 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2031 wm[1] = (sskpd >> 4) & 0xFF;
2032 wm[2] = (sskpd >> 12) & 0xFF;
2033 wm[3] = (sskpd >> 20) & 0x1FF;
2034 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2035 } else if (INTEL_INFO(dev)->gen >= 6) {
2036 uint32_t sskpd = I915_READ(MCH_SSKPD);
2037
2038 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2039 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2040 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2041 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2042 } else if (INTEL_INFO(dev)->gen >= 5) {
2043 uint32_t mltr = I915_READ(MLTR_ILK);
2044
2045 /* ILK primary LP0 latency is 700 ns */
2046 wm[0] = 7;
2047 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2048 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2049 }
2050}
2051
53615a5e
VS		 2052static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2053{
2054 /* ILK sprite LP0 latency is 1300 ns */
2055 if (INTEL_INFO(dev)->gen == 5)
2056 wm[0] = 13;
2057}
2058
2059static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2060{
2061 /* ILK cursor LP0 latency is 1300 ns */
2062 if (INTEL_INFO(dev)->gen == 5)
2063 wm[0] = 13;
2064
2065 /* WaDoubleCursorLP3Latency:ivb */
2066 if (IS_IVYBRIDGE(dev))
2067 wm[3] *= 2;
2068}
2069
ad0d6dc4 2070static int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2071{
26ec971e 2072 /* how many WM levels are we expecting */
a42a5719 2073 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2074 return 4;
26ec971e 2075 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2076 return 3;
26ec971e 2077 else
ad0d6dc4
VS		 2078 return 2;
2079}
2080
2081static void intel_print_wm_latency(struct drm_device *dev,
2082 const char *name,
2083 const uint16_t wm[5])
2084{
2085 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2086
2087 for (level = 0; level <= max_level; level++) {
2088 unsigned int latency = wm[level];
2089
2090 if (latency == 0) {
2091 DRM_ERROR("%s WM%d latency not provided\n",
2092 name, level);
2093 continue;
2094 }
2095
2096 /* WM1+ latency values in 0.5us units */
2097 if (level > 0)
2098 latency *= 5;
2099
2100 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2101 name, level, wm[level],
2102 latency / 10, latency % 10);
2103 }
2104}
2105
fa50ad61 2106static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2107{
2108 struct drm_i915_private *dev_priv = dev->dev_private;
2109
2110 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2111
2112 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2113 sizeof(dev_priv->wm.pri_latency));
2114 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2115 sizeof(dev_priv->wm.pri_latency));
2116
2117 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2118 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2119
2120 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2121 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2122 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
53615a5e
VS		 2123}
2124
820c1980 2125static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2a44b76b 2126 struct ilk_pipe_wm_parameters *p)
1011d8c4 2127{
7c4a395f
VS		 2128 struct drm_device *dev = crtc->dev;
2129 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2130 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2131 struct drm_plane *plane;
1011d8c4 2132
2a44b76b
VS		 2133 if (!intel_crtc_active(crtc))
2134 return;
801bcfff 2135
2a44b76b
VS		 2136 p->active = true;
2137 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2138 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2139 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2140 p->cur.bytes_per_pixel = 4;
2141 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2142 p->cur.horiz_pixels = intel_crtc->cursor_width;
2143 /* TODO: for now, assume primary and cursor planes are always enabled. */
2144 p->pri.enabled = true;
2145 p->cur.enabled = true;
7c4a395f 2146
af2b653b 2147 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
801bcfff 2148 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2149
2a44b76b 2150 if (intel_plane->pipe == pipe) {
7c4a395f 2151 p->spr = intel_plane->wm;
2a44b76b
VS		 2152 break;
2153 }
2154 }
2155}
2156
2157static void ilk_compute_wm_config(struct drm_device *dev,
2158 struct intel_wm_config *config)
2159{
2160 struct intel_crtc *intel_crtc;
2161
2162 /* Compute the currently _active_ config */
2163 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2164 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
cca32e9a 2165
2a44b76b
VS		 2166 if (!wm->pipe_enabled)
2167 continue;
cca32e9a 2168
2a44b76b
VS		 2169 config->sprites_enabled |= wm->sprites_enabled;
2170 config->sprites_scaled |= wm->sprites_scaled;
2171 config->num_pipes_active++;
cca32e9a 2172 }
801bcfff
PZ		 2173}
2174
0b2ae6d7
VS		 2175/* Compute new watermarks for the pipe */
2176static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
820c1980 2177 const struct ilk_pipe_wm_parameters *params,
0b2ae6d7
VS		 2178 struct intel_pipe_wm *pipe_wm)
2179{
2180 struct drm_device *dev = crtc->dev;
d34ff9c6 2181 const struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7
VS		 2182 int level, max_level = ilk_wm_max_level(dev);
2183 /* LP0 watermark maximums depend on this pipe alone */
2184 struct intel_wm_config config = {
2185 .num_pipes_active = 1,
2186 .sprites_enabled = params->spr.enabled,
2187 .sprites_scaled = params->spr.scaled,
2188 };
820c1980 2189 struct ilk_wm_maximums max;
0b2ae6d7 2190
0b2ae6d7 2191 /* LP0 watermarks always use 1/2 DDB partitioning */
34982fe1 2192 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
0b2ae6d7 2193
2a44b76b
VS		 2194 pipe_wm->pipe_enabled = params->active;
2195 pipe_wm->sprites_enabled = params->spr.enabled;
2196 pipe_wm->sprites_scaled = params->spr.scaled;
2197
7b39a0b7
VS		 2198 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2199 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2200 max_level = 1;
2201
2202 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2203 if (params->spr.scaled)
2204 max_level = 0;
2205
0b2ae6d7
VS		 2206 for (level = 0; level <= max_level; level++)
2207 ilk_compute_wm_level(dev_priv, level, params,
2208 &pipe_wm->wm[level]);
2209
a42a5719 2210 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2211 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7
VS		 2212
2213 /* At least LP0 must be valid */
d9395655 2214 return ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]);
0b2ae6d7
VS		 2215}
2216
2217/*
2218 * Merge the watermarks from all active pipes for a specific level.
2219 */
2220static void ilk_merge_wm_level(struct drm_device *dev,
2221 int level,
2222 struct intel_wm_level *ret_wm)
2223{
2224 const struct intel_crtc *intel_crtc;
2225
2226 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
fe392efd
VS		 2227 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2228 const struct intel_wm_level *wm = &active->wm[level];
2229
2230 if (!active->pipe_enabled)
2231 continue;
0b2ae6d7
VS		 2232
2233 if (!wm->enable)
2234 return;
2235
2236 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2237 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2238 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2239 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2240 }
2241
2242 ret_wm->enable = true;
2243}
2244
2245/*
2246 * Merge all low power watermarks for all active pipes.
2247 */
2248static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2249 const struct intel_wm_config *config,
820c1980 2250 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2251 struct intel_pipe_wm *merged)
2252{
2253 int level, max_level = ilk_wm_max_level(dev);
2254
0ba22e26
VS		 2255 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2256 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2257 config->num_pipes_active > 1)
2258 return;
2259
6c8b6c28
VS		 2260 /* ILK: FBC WM must be disabled always */
2261 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2262
2263 /* merge each WM1+ level */
2264 for (level = 1; level <= max_level; level++) {
2265 struct intel_wm_level *wm = &merged->wm[level];
2266
2267 ilk_merge_wm_level(dev, level, wm);
2268
d9395655 2269 if (!ilk_validate_wm_level(level, max, wm))
0b2ae6d7
VS		 2270 break;
2271
2272 /*
2273 * The spec says it is preferred to disable
2274 * FBC WMs instead of disabling a WM level.
2275 */
2276 if (wm->fbc_val > max->fbc) {
2277 merged->fbc_wm_enabled = false;
2278 wm->fbc_val = 0;
2279 }
2280 }
6c8b6c28
VS		 2281
2282 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2283 /*
2284 * FIXME this is racy. FBC might get enabled later.
2285 * What we should check here is whether FBC can be
2286 * enabled sometime later.
2287 */
2288 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2289 for (level = 2; level <= max_level; level++) {
2290 struct intel_wm_level *wm = &merged->wm[level];
2291
2292 wm->enable = false;
2293 }
2294 }
0b2ae6d7
VS		 2295}
2296
b380ca3c
VS		 2297static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2298{
2299 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2300 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2301}
2302
a68d68ee
VS		 2303/* The value we need to program into the WM_LPx latency field */
2304static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2305{
2306 struct drm_i915_private *dev_priv = dev->dev_private;
2307
a42a5719 2308 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2309 return 2 * level;
2310 else
2311 return dev_priv->wm.pri_latency[level];
2312}
2313
820c1980 2314static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2315 const struct intel_pipe_wm *merged,
609cedef 2316 enum intel_ddb_partitioning partitioning,
820c1980 2317 struct ilk_wm_values *results)
801bcfff 2318{
0b2ae6d7
VS		 2319 struct intel_crtc *intel_crtc;
2320 int level, wm_lp;
cca32e9a 2321
0362c781 2322 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2323 results->partitioning = partitioning;
cca32e9a 2324
0b2ae6d7 2325 /* LP1+ register values */
cca32e9a 2326 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2327 const struct intel_wm_level *r;
801bcfff 2328
b380ca3c 2329 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2330
0362c781 2331 r = &merged->wm[level];
0b2ae6d7 2332 if (!r->enable)
cca32e9a
PZ		 2333 break;
2334
416f4727 2335 results->wm_lp[wm_lp - 1] = WM3_LP_EN |
a68d68ee 2336 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2337 (r->pri_val << WM1_LP_SR_SHIFT) |
2338 r->cur_val;
2339
2340 if (INTEL_INFO(dev)->gen >= 8)
2341 results->wm_lp[wm_lp - 1] |=
2342 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2343 else
2344 results->wm_lp[wm_lp - 1] |=
2345 r->fbc_val << WM1_LP_FBC_SHIFT;
2346
6cef2b8a
VS		 2347 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2348 WARN_ON(wm_lp != 1);
2349 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2350 } else
2351 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2352 }
801bcfff 2353
0b2ae6d7
VS		 2354 /* LP0 register values */
2355 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2356 enum pipe pipe = intel_crtc->pipe;
2357 const struct intel_wm_level *r =
2358 &intel_crtc->wm.active.wm[0];
2359
2360 if (WARN_ON(!r->enable))
2361 continue;
2362
2363 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2364
0b2ae6d7
VS		 2365 results->wm_pipe[pipe] =
2366 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2367 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2368 r->cur_val;
801bcfff
PZ		 2369 }
2370}
2371
861f3389
PZ		 2372/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2373 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2374static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2375 struct intel_pipe_wm *r1,
2376 struct intel_pipe_wm *r2)
861f3389 2377{
198a1e9b
VS		 2378 int level, max_level = ilk_wm_max_level(dev);
2379 int level1 = 0, level2 = 0;
861f3389 2380
198a1e9b
VS		 2381 for (level = 1; level <= max_level; level++) {
2382 if (r1->wm[level].enable)
2383 level1 = level;
2384 if (r2->wm[level].enable)
2385 level2 = level;
861f3389
PZ		 2386 }
2387
198a1e9b
VS		 2388 if (level1 == level2) {
2389 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2390 return r2;
2391 else
2392 return r1;
198a1e9b 2393 } else if (level1 > level2) {
861f3389
PZ		 2394 return r1;
2395 } else {
2396 return r2;
2397 }
2398}
2399
49a687c4
VS		 2400/* dirty bits used to track which watermarks need changes */
2401#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2402#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2403#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2404#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2405#define WM_DIRTY_FBC (1 << 24)
2406#define WM_DIRTY_DDB (1 << 25)
2407
2408static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
820c1980
ID		 2409 const struct ilk_wm_values *old,
2410 const struct ilk_wm_values *new)
49a687c4
VS		 2411{
2412 unsigned int dirty = 0;
2413 enum pipe pipe;
2414 int wm_lp;
2415
2416 for_each_pipe(pipe) {
2417 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2418 dirty |= WM_DIRTY_LINETIME(pipe);
2419 /* Must disable LP1+ watermarks too */
2420 dirty |= WM_DIRTY_LP_ALL;
2421 }
2422
2423 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2424 dirty |= WM_DIRTY_PIPE(pipe);
2425 /* Must disable LP1+ watermarks too */
2426 dirty |= WM_DIRTY_LP_ALL;
2427 }
2428 }
2429
2430 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2431 dirty |= WM_DIRTY_FBC;
2432 /* Must disable LP1+ watermarks too */
2433 dirty |= WM_DIRTY_LP_ALL;
2434 }
2435
2436 if (old->partitioning != new->partitioning) {
2437 dirty |= WM_DIRTY_DDB;
2438 /* Must disable LP1+ watermarks too */
2439 dirty |= WM_DIRTY_LP_ALL;
2440 }
2441
2442 /* LP1+ watermarks already deemed dirty, no need to continue */
2443 if (dirty & WM_DIRTY_LP_ALL)
2444 return dirty;
2445
2446 /* Find the lowest numbered LP1+ watermark in need of an update... */
2447 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2448 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2449 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2450 break;
2451 }
2452
2453 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2454 for (; wm_lp <= 3; wm_lp++)
2455 dirty |= WM_DIRTY_LP(wm_lp);
2456
2457 return dirty;
2458}
2459
8553c18e
VS		 2460static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2461 unsigned int dirty)
801bcfff 2462{
820c1980 2463 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2464 bool changed = false;
801bcfff 2465
facd619b
VS		 2466 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2467 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2468 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2469 changed = true;
facd619b
VS		 2470 }
2471 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2472 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2473 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2474 changed = true;
facd619b
VS		 2475 }
2476 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2477 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2478 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2479 changed = true;
facd619b 2480 }
801bcfff 2481
facd619b
VS		 2482 /*
2483 * Don't touch WM1S_LP_EN here.
2484 * Doing so could cause underruns.
2485 */
6cef2b8a 2486
8553c18e
VS		 2487 return changed;
2488}
2489
2490/*
2491 * The spec says we shouldn't write when we don't need, because every write
2492 * causes WMs to be re-evaluated, expending some power.
2493 */
820c1980
ID		 2494static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2495 struct ilk_wm_values *results)
8553c18e
VS		 2496{
2497 struct drm_device *dev = dev_priv->dev;
820c1980 2498 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2499 unsigned int dirty;
2500 uint32_t val;
2501
2502 dirty = ilk_compute_wm_dirty(dev, previous, results);
2503 if (!dirty)
2504 return;
2505
2506 _ilk_disable_lp_wm(dev_priv, dirty);
2507
49a687c4 2508 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2509 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2510 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2511 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2512 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2513 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2514
49a687c4 2515 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2516 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2517 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2518 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2519 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2520 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2521
49a687c4 2522 if (dirty & WM_DIRTY_DDB) {
a42a5719 2523 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2524 val = I915_READ(WM_MISC);
2525 if (results->partitioning == INTEL_DDB_PART_1_2)
2526 val &= ~WM_MISC_DATA_PARTITION_5_6;
2527 else
2528 val |= WM_MISC_DATA_PARTITION_5_6;
2529 I915_WRITE(WM_MISC, val);
2530 } else {
2531 val = I915_READ(DISP_ARB_CTL2);
2532 if (results->partitioning == INTEL_DDB_PART_1_2)
2533 val &= ~DISP_DATA_PARTITION_5_6;
2534 else
2535 val |= DISP_DATA_PARTITION_5_6;
2536 I915_WRITE(DISP_ARB_CTL2, val);
2537 }
1011d8c4
PZ		 2538 }
2539
49a687c4 2540 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2541 val = I915_READ(DISP_ARB_CTL);
2542 if (results->enable_fbc_wm)
2543 val &= ~DISP_FBC_WM_DIS;
2544 else
2545 val |= DISP_FBC_WM_DIS;
2546 I915_WRITE(DISP_ARB_CTL, val);
2547 }
2548
954911eb
ID		 2549 if (dirty & WM_DIRTY_LP(1) &&
2550 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2551 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2552
2553 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2554 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2555 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2556 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2557 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2558 }
801bcfff 2559
facd619b 2560 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2561 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2562 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2563 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2564 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2565 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2566
2567 dev_priv->wm.hw = *results;
801bcfff
PZ		 2568}
2569
8553c18e
VS		 2570static bool ilk_disable_lp_wm(struct drm_device *dev)
2571{
2572 struct drm_i915_private *dev_priv = dev->dev_private;
2573
2574 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2575}
2576
820c1980 2577static void ilk_update_wm(struct drm_crtc *crtc)
801bcfff 2578{
7c4a395f 2579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 2580 struct drm_device *dev = crtc->dev;
801bcfff 2581 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980
ID		 2582 struct ilk_wm_maximums max;
2583 struct ilk_pipe_wm_parameters params = {};
2584 struct ilk_wm_values results = {};
77c122bc 2585 enum intel_ddb_partitioning partitioning;
7c4a395f 2586 struct intel_pipe_wm pipe_wm = {};
198a1e9b 2587 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 2588 struct intel_wm_config config = {};
7c4a395f 2589
2a44b76b 2590 ilk_compute_wm_parameters(crtc, &params);
7c4a395f
VS		 2591
2592 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2593
2594 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2595 return;
861f3389 2596
7c4a395f 2597 intel_crtc->wm.active = pipe_wm;
861f3389 2598
2a44b76b
VS		 2599 ilk_compute_wm_config(dev, &config);
2600
34982fe1 2601 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
0ba22e26 2602 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 2603
2604 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 2605 if (INTEL_INFO(dev)->gen >= 7 &&
2606 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 2607 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
0ba22e26 2608 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 2609
820c1980 2610 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 2611 } else {
198a1e9b 2612 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 2613 }
2614
198a1e9b 2615 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 2616 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 2617
820c1980 2618 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 2619
820c1980 2620 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 2621}
2622
820c1980 2623static void ilk_update_sprite_wm(struct drm_plane *plane,
adf3d35e 2624 struct drm_crtc *crtc,
526682e9 2625 uint32_t sprite_width, int pixel_size,
bdd57d03 2626 bool enabled, bool scaled)
526682e9 2627{
8553c18e 2628 struct drm_device *dev = plane->dev;
adf3d35e 2629 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 2630
adf3d35e
VS		 2631 intel_plane->wm.enabled = enabled;
2632 intel_plane->wm.scaled = scaled;
2633 intel_plane->wm.horiz_pixels = sprite_width;
2634 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 2635
8553c18e
VS		 2636 /*
2637 * IVB workaround: must disable low power watermarks for at least
2638 * one frame before enabling scaling. LP watermarks can be re-enabled
2639 * when scaling is disabled.
2640 *
2641 * WaCxSRDisabledForSpriteScaling:ivb
2642 */
2643 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2644 intel_wait_for_vblank(dev, intel_plane->pipe);
2645
820c1980 2646 ilk_update_wm(crtc);
526682e9
PZ		 2647}
2648
243e6a44
VS		 2649static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2650{
2651 struct drm_device *dev = crtc->dev;
2652 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 2653 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 2654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2655 struct intel_pipe_wm *active = &intel_crtc->wm.active;
2656 enum pipe pipe = intel_crtc->pipe;
2657 static const unsigned int wm0_pipe_reg[] = {
2658 [PIPE_A] = WM0_PIPEA_ILK,
2659 [PIPE_B] = WM0_PIPEB_ILK,
2660 [PIPE_C] = WM0_PIPEC_IVB,
2661 };
2662
2663 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 2664 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2665 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 2666
2a44b76b
VS		 2667 active->pipe_enabled = intel_crtc_active(crtc);
2668
2669 if (active->pipe_enabled) {
243e6a44
VS		 2670 u32 tmp = hw->wm_pipe[pipe];
2671
2672 /*
2673 * For active pipes LP0 watermark is marked as
2674 * enabled, and LP1+ watermaks as disabled since
2675 * we can't really reverse compute them in case
2676 * multiple pipes are active.
2677 */
2678 active->wm[0].enable = true;
2679 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2680 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2681 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2682 active->linetime = hw->wm_linetime[pipe];
2683 } else {
2684 int level, max_level = ilk_wm_max_level(dev);
2685
2686 /*
2687 * For inactive pipes, all watermark levels
2688 * should be marked as enabled but zeroed,
2689 * which is what we'd compute them to.
2690 */
2691 for (level = 0; level <= max_level; level++)
2692 active->wm[level].enable = true;
2693 }
2694}
2695
2696void ilk_wm_get_hw_state(struct drm_device *dev)
2697{
2698 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 2699 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 2700 struct drm_crtc *crtc;
2701
2702 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2703 ilk_pipe_wm_get_hw_state(crtc);
2704
2705 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2706 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2707 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2708
2709 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 2710 if (INTEL_INFO(dev)->gen >= 7) {
2711 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2712 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2713 }
243e6a44 2714
a42a5719 2715 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 2716 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2717 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2718 else if (IS_IVYBRIDGE(dev))
2719 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2720 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 2721
2722 hw->enable_fbc_wm =
2723 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2724}
2725
b445e3b0
ED		 2726/**
2727 * intel_update_watermarks - update FIFO watermark values based on current modes
2728 *
2729 * Calculate watermark values for the various WM regs based on current mode
2730 * and plane configuration.
2731 *
2732 * There are several cases to deal with here:
2733 * - normal (i.e. non-self-refresh)
2734 * - self-refresh (SR) mode
2735 * - lines are large relative to FIFO size (buffer can hold up to 2)
2736 * - lines are small relative to FIFO size (buffer can hold more than 2
2737 * lines), so need to account for TLB latency
2738 *
2739 * The normal calculation is:
2740 * watermark = dotclock * bytes per pixel * latency
2741 * where latency is platform & configuration dependent (we assume pessimal
2742 * values here).
2743 *
2744 * The SR calculation is:
2745 * watermark = (trunc(latency/line time)+1) * surface width *
2746 * bytes per pixel
2747 * where
2748 * line time = htotal / dotclock
2749 * surface width = hdisplay for normal plane and 64 for cursor
2750 * and latency is assumed to be high, as above.
2751 *
2752 * The final value programmed to the register should always be rounded up,
2753 * and include an extra 2 entries to account for clock crossings.
2754 *
2755 * We don't use the sprite, so we can ignore that. And on Crestline we have
2756 * to set the non-SR watermarks to 8.
2757 */
46ba614c 2758void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 2759{
46ba614c 2760 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 2761
2762 if (dev_priv->display.update_wm)
46ba614c 2763 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 2764}
2765
adf3d35e
VS		 2766void intel_update_sprite_watermarks(struct drm_plane *plane,
2767 struct drm_crtc *crtc,
4c4ff43a 2768 uint32_t sprite_width, int pixel_size,
39db4a4d 2769 bool enabled, bool scaled)
b445e3b0 2770{
adf3d35e 2771 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 2772
2773 if (dev_priv->display.update_sprite_wm)
adf3d35e 2774 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
39db4a4d 2775 pixel_size, enabled, scaled);
b445e3b0
ED		 2776}
2777
2b4e57bd
ED		 2778static struct drm_i915_gem_object *
2779intel_alloc_context_page(struct drm_device *dev)
2780{
2781 struct drm_i915_gem_object *ctx;
2782 int ret;
2783
2784 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2785
2786 ctx = i915_gem_alloc_object(dev, 4096);
2787 if (!ctx) {
2788 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2789 return NULL;
2790 }
2791
c69766f2 2792 ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
2b4e57bd
ED		 2793 if (ret) {
2794 DRM_ERROR("failed to pin power context: %d\n", ret);
2795 goto err_unref;
2796 }
2797
2798 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2799 if (ret) {
2800 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2801 goto err_unpin;
2802 }
2803
2804 return ctx;
2805
2806err_unpin:
d7f46fc4 2807 i915_gem_object_ggtt_unpin(ctx);
2b4e57bd
ED		 2808err_unref:
2809 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 2810 return NULL;
2811}
2812
9270388e
DV		 2813/**
2814 * Lock protecting IPS related data structures
9270388e
DV		 2815 */
2816DEFINE_SPINLOCK(mchdev_lock);
2817
2818/* Global for IPS driver to get at the current i915 device. Protected by
2819 * mchdev_lock. */
2820static struct drm_i915_private *i915_mch_dev;
2821
2b4e57bd
ED		 2822bool ironlake_set_drps(struct drm_device *dev, u8 val)
2823{
2824 struct drm_i915_private *dev_priv = dev->dev_private;
2825 u16 rgvswctl;
2826
9270388e
DV		 2827 assert_spin_locked(&mchdev_lock);
2828
2b4e57bd
ED		 2829 rgvswctl = I915_READ16(MEMSWCTL);
2830 if (rgvswctl & MEMCTL_CMD_STS) {
2831 DRM_DEBUG("gpu busy, RCS change rejected\n");
2832 return false; /* still busy with another command */
2833 }
2834
2835 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2836 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2837 I915_WRITE16(MEMSWCTL, rgvswctl);
2838 POSTING_READ16(MEMSWCTL);
2839
2840 rgvswctl |= MEMCTL_CMD_STS;
2841 I915_WRITE16(MEMSWCTL, rgvswctl);
2842
2843 return true;
2844}
2845
8090c6b9 2846static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 2847{
2848 struct drm_i915_private *dev_priv = dev->dev_private;
2849 u32 rgvmodectl = I915_READ(MEMMODECTL);
2850 u8 fmax, fmin, fstart, vstart;
2851
9270388e
DV		 2852 spin_lock_irq(&mchdev_lock);
2853
2b4e57bd
ED		 2854 /* Enable temp reporting */
2855 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2856 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2857
2858 /* 100ms RC evaluation intervals */
2859 I915_WRITE(RCUPEI, 100000);
2860 I915_WRITE(RCDNEI, 100000);
2861
2862 /* Set max/min thresholds to 90ms and 80ms respectively */
2863 I915_WRITE(RCBMAXAVG, 90000);
2864 I915_WRITE(RCBMINAVG, 80000);
2865
2866 I915_WRITE(MEMIHYST, 1);
2867
2868 /* Set up min, max, and cur for interrupt handling */
2869 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2870 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2871 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2872 MEMMODE_FSTART_SHIFT;
2873
2874 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2875 PXVFREQ_PX_SHIFT;
2876
20e4d407
DV		 2877 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2878 dev_priv->ips.fstart = fstart;
2b4e57bd 2879
20e4d407
DV		 2880 dev_priv->ips.max_delay = fstart;
2881 dev_priv->ips.min_delay = fmin;
2882 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 2883
2884 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2885 fmax, fmin, fstart);
2886
2887 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2888
2889 /*
2890 * Interrupts will be enabled in ironlake_irq_postinstall
2891 */
2892
2893 I915_WRITE(VIDSTART, vstart);
2894 POSTING_READ(VIDSTART);
2895
2896 rgvmodectl |= MEMMODE_SWMODE_EN;
2897 I915_WRITE(MEMMODECTL, rgvmodectl);
2898
9270388e 2899 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 2900 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 2901 mdelay(1);
2b4e57bd
ED		 2902
2903 ironlake_set_drps(dev, fstart);
2904
20e4d407 2905 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 2906 I915_READ(0x112e0);
20e4d407
DV		 2907 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2908 dev_priv->ips.last_count2 = I915_READ(0x112f4);
2909 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 2910
2911 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2912}
2913
8090c6b9 2914static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 2915{
2916 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 2917 u16 rgvswctl;
2918
2919 spin_lock_irq(&mchdev_lock);
2920
2921 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 2922
2923 /* Ack interrupts, disable EFC interrupt */
2924 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2925 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2926 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2927 I915_WRITE(DEIIR, DE_PCU_EVENT);
2928 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2929
2930 /* Go back to the starting frequency */
20e4d407 2931 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 2932 mdelay(1);
2b4e57bd
ED		 2933 rgvswctl |= MEMCTL_CMD_STS;
2934 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 2935 mdelay(1);
2b4e57bd 2936
9270388e 2937 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2938}
2939
acbe9475
DV		 2940/* There's a funny hw issue where the hw returns all 0 when reading from
2941 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2942 * ourselves, instead of doing a rmw cycle (which might result in us clearing
2943 * all limits and the gpu stuck at whatever frequency it is at atm).
2944 */
6917c7b9 2945static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 2946{
7b9e0ae6 2947 u32 limits;
2b4e57bd 2948
20b46e59
DV		 2949 /* Only set the down limit when we've reached the lowest level to avoid
2950 * getting more interrupts, otherwise leave this clear. This prevents a
2951 * race in the hw when coming out of rc6: There's a tiny window where
2952 * the hw runs at the minimal clock before selecting the desired
2953 * frequency, if the down threshold expires in that window we will not
2954 * receive a down interrupt. */
b39fb297
BW		 2955 limits = dev_priv->rps.max_freq_softlimit << 24;
2956 if (val <= dev_priv->rps.min_freq_softlimit)
2957 limits |= dev_priv->rps.min_freq_softlimit << 16;
20b46e59
DV		 2958
2959 return limits;
2960}
2961
dd75fdc8
CW		 2962static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
2963{
2964 int new_power;
2965
2966 new_power = dev_priv->rps.power;
2967 switch (dev_priv->rps.power) {
2968 case LOW_POWER:
b39fb297 2969 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 2970 new_power = BETWEEN;
2971 break;
2972
2973 case BETWEEN:
b39fb297 2974 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 2975 new_power = LOW_POWER;
b39fb297 2976 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 2977 new_power = HIGH_POWER;
2978 break;
2979
2980 case HIGH_POWER:
b39fb297 2981 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 2982 new_power = BETWEEN;
2983 break;
2984 }
2985 /* Max/min bins are special */
b39fb297 2986 if (val == dev_priv->rps.min_freq_softlimit)
dd75fdc8 2987 new_power = LOW_POWER;
b39fb297 2988 if (val == dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 2989 new_power = HIGH_POWER;
2990 if (new_power == dev_priv->rps.power)
2991 return;
2992
2993 /* Note the units here are not exactly 1us, but 1280ns. */
2994 switch (new_power) {
2995 case LOW_POWER:
2996 /* Upclock if more than 95% busy over 16ms */
2997 I915_WRITE(GEN6_RP_UP_EI, 12500);
2998 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
2999
3000 /* Downclock if less than 85% busy over 32ms */
3001 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3002 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3003
3004 I915_WRITE(GEN6_RP_CONTROL,
3005 GEN6_RP_MEDIA_TURBO |
3006 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3007 GEN6_RP_MEDIA_IS_GFX |
3008 GEN6_RP_ENABLE |
3009 GEN6_RP_UP_BUSY_AVG |
3010 GEN6_RP_DOWN_IDLE_AVG);
3011 break;
3012
3013 case BETWEEN:
3014 /* Upclock if more than 90% busy over 13ms */
3015 I915_WRITE(GEN6_RP_UP_EI, 10250);
3016 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3017
3018 /* Downclock if less than 75% busy over 32ms */
3019 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3020 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3021
3022 I915_WRITE(GEN6_RP_CONTROL,
3023 GEN6_RP_MEDIA_TURBO |
3024 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3025 GEN6_RP_MEDIA_IS_GFX |
3026 GEN6_RP_ENABLE |
3027 GEN6_RP_UP_BUSY_AVG |
3028 GEN6_RP_DOWN_IDLE_AVG);
3029 break;
3030
3031 case HIGH_POWER:
3032 /* Upclock if more than 85% busy over 10ms */
3033 I915_WRITE(GEN6_RP_UP_EI, 8000);
3034 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3035
3036 /* Downclock if less than 60% busy over 32ms */
3037 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3038 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3039
3040 I915_WRITE(GEN6_RP_CONTROL,
3041 GEN6_RP_MEDIA_TURBO |
3042 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3043 GEN6_RP_MEDIA_IS_GFX |
3044 GEN6_RP_ENABLE |
3045 GEN6_RP_UP_BUSY_AVG |
3046 GEN6_RP_DOWN_IDLE_AVG);
3047 break;
3048 }
3049
3050 dev_priv->rps.power = new_power;
3051 dev_priv->rps.last_adj = 0;
3052}
3053
2876ce73
CW		 3054static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3055{
3056 u32 mask = 0;
3057
3058 if (val > dev_priv->rps.min_freq_softlimit)
3059 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3060 if (val < dev_priv->rps.max_freq_softlimit)
3061 mask |= GEN6_PM_RP_UP_THRESHOLD;
3062
3063 /* IVB and SNB hard hangs on looping batchbuffer
3064 * if GEN6_PM_UP_EI_EXPIRED is masked.
3065 */
3066 if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3067 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3068
3069 return ~mask;
3070}
3071
b8a5ff8d
JM		 3072/* gen6_set_rps is called to update the frequency request, but should also be
3073 * called when the range (min_delay and max_delay) is modified so that we can
3074 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
20b46e59
DV		 3075void gen6_set_rps(struct drm_device *dev, u8 val)
3076{
3077 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 3078
4fc688ce 3079 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
b39fb297
BW		 3080 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3081 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
004777cb 3082
eb64cad1
CW		 3083 /* min/max delay may still have been modified so be sure to
3084 * write the limits value.
3085 */
3086 if (val != dev_priv->rps.cur_freq) {
3087 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 3088
50e6a2a7 3089 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 3090 I915_WRITE(GEN6_RPNSWREQ,
3091 HSW_FREQUENCY(val));
3092 else
3093 I915_WRITE(GEN6_RPNSWREQ,
3094 GEN6_FREQUENCY(val) |
3095 GEN6_OFFSET(0) |
3096 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 3097 }
7b9e0ae6 3098
7b9e0ae6
CW		 3099 /* Make sure we continue to get interrupts
3100 * until we hit the minimum or maximum frequencies.
3101 */
eb64cad1 3102 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
2876ce73 3103 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 3104
d5570a72
BW		 3105 POSTING_READ(GEN6_RPNSWREQ);
3106
b39fb297 3107 dev_priv->rps.cur_freq = val;
be2cde9a 3108 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3109}
3110
76c3552f
D		 3111/* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3112 *
3113 * * If Gfx is Idle, then
3114 * 1. Mask Turbo interrupts
3115 * 2. Bring up Gfx clock
3116 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3117 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3118 * 5. Unmask Turbo interrupts
3119*/
3120static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3121{
3122 /*
3123 * When we are idle. Drop to min voltage state.
3124 */
3125
b39fb297 3126 if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
76c3552f
D		 3127 return;
3128
3129 /* Mask turbo interrupt so that they will not come in between */
3130 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3131
650ad970 3132 vlv_force_gfx_clock(dev_priv, true);
76c3552f 3133
b39fb297 3134 dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
76c3552f
D		 3135
3136 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
b39fb297 3137 dev_priv->rps.min_freq_softlimit);
76c3552f
D		 3138
3139 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3140 & GENFREQSTATUS) == 0, 5))
3141 DRM_ERROR("timed out waiting for Punit\n");
3142
650ad970 3143 vlv_force_gfx_clock(dev_priv, false);
76c3552f 3144
2876ce73
CW		 3145 I915_WRITE(GEN6_PMINTRMSK,
3146 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
76c3552f
D		 3147}
3148
b29c19b6
CW		 3149void gen6_rps_idle(struct drm_i915_private *dev_priv)
3150{
691bb717
DL		 3151 struct drm_device *dev = dev_priv->dev;
3152
b29c19b6 3153 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3154 if (dev_priv->rps.enabled) {
691bb717 3155 if (IS_VALLEYVIEW(dev))
76c3552f 3156 vlv_set_rps_idle(dev_priv);
c0951f0c 3157 else
b39fb297 3158 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
c0951f0c
CW		 3159 dev_priv->rps.last_adj = 0;
3160 }
b29c19b6
CW		 3161 mutex_unlock(&dev_priv->rps.hw_lock);
3162}
3163
3164void gen6_rps_boost(struct drm_i915_private *dev_priv)
3165{
691bb717
DL		 3166 struct drm_device *dev = dev_priv->dev;
3167
b29c19b6 3168 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3169 if (dev_priv->rps.enabled) {
691bb717 3170 if (IS_VALLEYVIEW(dev))
b39fb297 3171 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
c0951f0c 3172 else
b39fb297 3173 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
c0951f0c
CW		 3174 dev_priv->rps.last_adj = 0;
3175 }
b29c19b6
CW		 3176 mutex_unlock(&dev_priv->rps.hw_lock);
3177}
3178
0a073b84
JB		 3179void valleyview_set_rps(struct drm_device *dev, u8 val)
3180{
3181 struct drm_i915_private *dev_priv = dev->dev_private;
7a67092a 3182
0a073b84 3183 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
b39fb297
BW		 3184 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3185 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
0a073b84 3186
73008b98 3187 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
b39fb297
BW		 3188 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3189 dev_priv->rps.cur_freq,
2ec3815f 3190 vlv_gpu_freq(dev_priv, val), val);
0a073b84 3191
2876ce73
CW		 3192 if (val != dev_priv->rps.cur_freq)
3193 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
0a073b84 3194
09c87db8 3195 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
0a073b84 3196
b39fb297 3197 dev_priv->rps.cur_freq = val;
2ec3815f 3198 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
0a073b84
JB		 3199}
3200
44fc7d5c 3201static void gen6_disable_rps_interrupts(struct drm_device *dev)
2b4e57bd
ED		 3202{
3203 struct drm_i915_private *dev_priv = dev->dev_private;
3204
2b4e57bd 3205 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
a6706b45
D		 3206 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3207 ~dev_priv->pm_rps_events);
2b4e57bd
ED		 3208 /* Complete PM interrupt masking here doesn't race with the rps work
3209 * item again unmasking PM interrupts because that is using a different
3210 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3211 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3212
59cdb63d 3213 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3 3214 dev_priv->rps.pm_iir = 0;
59cdb63d 3215 spin_unlock_irq(&dev_priv->irq_lock);
2b4e57bd 3216
a6706b45 3217 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
2b4e57bd
ED		 3218}
3219
44fc7d5c 3220static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 3221{
3222 struct drm_i915_private *dev_priv = dev->dev_private;
3223
3224 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 3225 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
d20d4f0c 3226
44fc7d5c
DV		 3227 gen6_disable_rps_interrupts(dev);
3228}
3229
3230static void valleyview_disable_rps(struct drm_device *dev)
3231{
3232 struct drm_i915_private *dev_priv = dev->dev_private;
3233
3234 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 3235
44fc7d5c 3236 gen6_disable_rps_interrupts(dev);
d20d4f0c
JB		 3237}
3238
dc39fff7
BW		 3239static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3240{
91ca689a
ID		 3241 if (IS_VALLEYVIEW(dev)) {
3242 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
3243 mode = GEN6_RC_CTL_RC6_ENABLE;
3244 else
3245 mode = 0;
3246 }
dc39fff7 3247 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
1c79b42f
BW		 3248 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3249 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3250 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
dc39fff7
BW		 3251}
3252
e6069ca8 3253static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 3254{
eb4926e4
DL		 3255 /* No RC6 before Ironlake */
3256 if (INTEL_INFO(dev)->gen < 5)
3257 return 0;
3258
e6069ca8
ID		 3259 /* RC6 is only on Ironlake mobile not on desktop */
3260 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
3261 return 0;
3262
f033579f
ID		 3263 /* Disable RC6 on Broadwell for now */
3264 if (IS_BROADWELL(dev))
3265 return 0;
3266
456470eb 3267 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 3268 if (enable_rc6 >= 0) {
3269 int mask;
3270
3271 if (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
3272 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
3273 INTEL_RC6pp_ENABLE;
3274 else
3275 mask = INTEL_RC6_ENABLE;
3276
3277 if ((enable_rc6 & mask) != enable_rc6)
3278 DRM_INFO("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3279 enable_rc6, enable_rc6 & mask, mask);
3280
3281 return enable_rc6 & mask;
3282 }
2b4e57bd 3283
6567d748
CW		 3284 /* Disable RC6 on Ironlake */
3285 if (INTEL_INFO(dev)->gen == 5)
3286 return 0;
2b4e57bd 3287
8bade1ad 3288 if (IS_IVYBRIDGE(dev))
cca84a1f 3289 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 3290
3291 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 3292}
3293
e6069ca8
ID		 3294int intel_enable_rc6(const struct drm_device *dev)
3295{
3296 return i915.enable_rc6;
3297}
3298
44fc7d5c
DV		 3299static void gen6_enable_rps_interrupts(struct drm_device *dev)
3300{
3301 struct drm_i915_private *dev_priv = dev->dev_private;
3302
3303 spin_lock_irq(&dev_priv->irq_lock);
a0b3335a 3304 WARN_ON(dev_priv->rps.pm_iir);
a6706b45
D		 3305 snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3306 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
44fc7d5c 3307 spin_unlock_irq(&dev_priv->irq_lock);
44fc7d5c
DV		 3308}
3309
3280e8b0
BW		 3310static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)
3311{
3312 /* All of these values are in units of 50MHz */
3313 dev_priv->rps.cur_freq = 0;
3314 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3315 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3316 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
3317 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
3318 /* XXX: only BYT has a special efficient freq */
3319 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
3320 /* hw_max = RP0 until we check for overclocking */
3321 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3322
3323 /* Preserve min/max settings in case of re-init */
3324 if (dev_priv->rps.max_freq_softlimit == 0)
3325 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3326
3327 if (dev_priv->rps.min_freq_softlimit == 0)
3328 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3329}
3330
6edee7f3
BW		 3331static void gen8_enable_rps(struct drm_device *dev)
3332{
3333 struct drm_i915_private *dev_priv = dev->dev_private;
3334 struct intel_ring_buffer *ring;
3335 uint32_t rc6_mask = 0, rp_state_cap;
3336 int unused;
3337
3338 /* 1a: Software RC state - RC0 */
3339 I915_WRITE(GEN6_RC_STATE, 0);
3340
3341 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3342 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
c8d9a590 3343 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3344
3345 /* 2a: Disable RC states. */
3346 I915_WRITE(GEN6_RC_CONTROL, 0);
3347
3348 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3280e8b0 3349 parse_rp_state_cap(dev_priv, rp_state_cap);
6edee7f3
BW		 3350
3351 /* 2b: Program RC6 thresholds.*/
3352 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3353 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3354 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3355 for_each_ring(ring, dev_priv, unused)
3356 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3357 I915_WRITE(GEN6_RC_SLEEP, 0);
3358 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3359
3360 /* 3: Enable RC6 */
3361 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3362 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 3363 intel_print_rc6_info(dev, rc6_mask);
6edee7f3 3364 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
abbf9d2c
BW		 3365 GEN6_RC_CTL_EI_MODE(1) |
3366 rc6_mask);
6edee7f3
BW		 3367
3368 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 3369 I915_WRITE(GEN6_RPNSWREQ,
3370 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3371 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3372 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
6edee7f3
BW		 3373 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3374 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3375
3376 /* Docs recommend 900MHz, and 300 MHz respectively */
3377 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
b39fb297
BW		 3378 dev_priv->rps.max_freq_softlimit << 24 |
3379 dev_priv->rps.min_freq_softlimit << 16);
6edee7f3
BW		 3380
3381 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3382 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3383 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3384 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3385
3386 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3387
3388 /* 5: Enable RPS */
3389 I915_WRITE(GEN6_RP_CONTROL,
3390 GEN6_RP_MEDIA_TURBO |
3391 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3392 GEN6_RP_MEDIA_IS_GFX |
3393 GEN6_RP_ENABLE |
3394 GEN6_RP_UP_BUSY_AVG |
3395 GEN6_RP_DOWN_IDLE_AVG);
3396
3397 /* 6: Ring frequency + overclocking (our driver does this later */
3398
3399 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3400
3401 gen6_enable_rps_interrupts(dev);
3402
c8d9a590 3403 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3404}
3405
79f5b2c7 3406static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 3407{
79f5b2c7 3408 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 3409 struct intel_ring_buffer *ring;
2a5913a8 3410 u32 rp_state_cap;
7b9e0ae6 3411 u32 gt_perf_status;
d060c169 3412 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 3413 u32 gtfifodbg;
2b4e57bd 3414 int rc6_mode;
42c0526c 3415 int i, ret;
2b4e57bd 3416
4fc688ce 3417 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3418
2b4e57bd
ED		 3419 /* Here begins a magic sequence of register writes to enable
3420 * auto-downclocking.
3421 *
3422 * Perhaps there might be some value in exposing these to
3423 * userspace...
3424 */
3425 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 3426
3427 /* Clear the DBG now so we don't confuse earlier errors */
3428 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3429 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3430 I915_WRITE(GTFIFODBG, gtfifodbg);
3431 }
3432
c8d9a590 3433 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 3434
7b9e0ae6
CW		 3435 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3436 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3437
3280e8b0 3438 parse_rp_state_cap(dev_priv, rp_state_cap);
dd0a1aa1 3439
2b4e57bd
ED		 3440 /* disable the counters and set deterministic thresholds */
3441 I915_WRITE(GEN6_RC_CONTROL, 0);
3442
3443 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3444 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3445 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3446 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3447 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3448
b4519513
CW		 3449 for_each_ring(ring, dev_priv, i)
3450 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 3451
3452 I915_WRITE(GEN6_RC_SLEEP, 0);
3453 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 3454 if (IS_IVYBRIDGE(dev))
351aa566
SM		 3455 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3456 else
3457 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 3458 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 3459 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3460
5a7dc92a 3461 /* Check if we are enabling RC6 */
2b4e57bd
ED		 3462 rc6_mode = intel_enable_rc6(dev_priv->dev);
3463 if (rc6_mode & INTEL_RC6_ENABLE)
3464 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3465
5a7dc92a
ED		 3466 /* We don't use those on Haswell */
3467 if (!IS_HASWELL(dev)) {
3468 if (rc6_mode & INTEL_RC6p_ENABLE)
3469 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 3470
5a7dc92a
ED		 3471 if (rc6_mode & INTEL_RC6pp_ENABLE)
3472 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3473 }
2b4e57bd 3474
dc39fff7 3475 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 3476
3477 I915_WRITE(GEN6_RC_CONTROL,
3478 rc6_mask |
3479 GEN6_RC_CTL_EI_MODE(1) |
3480 GEN6_RC_CTL_HW_ENABLE);
3481
dd75fdc8
CW		 3482 /* Power down if completely idle for over 50ms */
3483 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 3484 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 3485
42c0526c 3486 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 3487 if (ret)
42c0526c 3488 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 3489
3490 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3491 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3492 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 3493 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 3494 (pcu_mbox & 0xff) * 50);
b39fb297 3495 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 3496 }
3497
dd75fdc8 3498 dev_priv->rps.power = HIGH_POWER; /* force a reset */
b39fb297 3499 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
2b4e57bd 3500
44fc7d5c 3501 gen6_enable_rps_interrupts(dev);
2b4e57bd 3502
31643d54
BW		 3503 rc6vids = 0;
3504 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3505 if (IS_GEN6(dev) && ret) {
3506 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3507 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3508 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3509 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3510 rc6vids &= 0xffff00;
3511 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3512 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3513 if (ret)
3514 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3515 }
3516
c8d9a590 3517 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 3518}
3519
c2bc2fc5 3520static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 3521{
79f5b2c7 3522 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 3523 int min_freq = 15;
3ebecd07
CW		 3524 unsigned int gpu_freq;
3525 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd 3526 int scaling_factor = 180;
eda79642 3527 struct cpufreq_policy *policy;
2b4e57bd 3528
4fc688ce 3529 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3530
eda79642
BW		 3531 policy = cpufreq_cpu_get(0);
3532 if (policy) {
3533 max_ia_freq = policy->cpuinfo.max_freq;
3534 cpufreq_cpu_put(policy);
3535 } else {
3536 /*
3537 * Default to measured freq if none found, PCU will ensure we
3538 * don't go over
3539 */
2b4e57bd 3540 max_ia_freq = tsc_khz;
eda79642 3541 }
2b4e57bd
ED		 3542
3543 /* Convert from kHz to MHz */
3544 max_ia_freq /= 1000;
3545
153b4b95 3546 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 3547 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3548 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 3549
2b4e57bd
ED		 3550 /*
3551 * For each potential GPU frequency, load a ring frequency we'd like
3552 * to use for memory access. We do this by specifying the IA frequency
3553 * the PCU should use as a reference to determine the ring frequency.
3554 */
b39fb297 3555 for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
2b4e57bd 3556 gpu_freq--) {
b39fb297 3557 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
3ebecd07
CW		 3558 unsigned int ia_freq = 0, ring_freq = 0;
3559
46c764d4
BW		 3560 if (INTEL_INFO(dev)->gen >= 8) {
3561 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3562 ring_freq = max(min_ring_freq, gpu_freq);
3563 } else if (IS_HASWELL(dev)) {
f6aca45c 3564 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 3565 ring_freq = max(min_ring_freq, ring_freq);
3566 /* leave ia_freq as the default, chosen by cpufreq */
3567 } else {
3568 /* On older processors, there is no separate ring
3569 * clock domain, so in order to boost the bandwidth
3570 * of the ring, we need to upclock the CPU (ia_freq).
3571 *
3572 * For GPU frequencies less than 750MHz,
3573 * just use the lowest ring freq.
3574 */
3575 if (gpu_freq < min_freq)
3576 ia_freq = 800;
3577 else
3578 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3579 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3580 }
2b4e57bd 3581
42c0526c
BW		 3582 sandybridge_pcode_write(dev_priv,
3583 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 3584 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3585 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3586 gpu_freq);
2b4e57bd 3587 }
2b4e57bd
ED		 3588}
3589
c2bc2fc5
ID		 3590void gen6_update_ring_freq(struct drm_device *dev)
3591{
3592 struct drm_i915_private *dev_priv = dev->dev_private;
3593
3594 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
3595 return;
3596
3597 mutex_lock(&dev_priv->rps.hw_lock);
3598 __gen6_update_ring_freq(dev);
3599 mutex_unlock(&dev_priv->rps.hw_lock);
3600}
3601
0a073b84
JB		 3602int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3603{
3604 u32 val, rp0;
3605
64936258 3606 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 3607
3608 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3609 /* Clamp to max */
3610 rp0 = min_t(u32, rp0, 0xea);
3611
3612 return rp0;
3613}
3614
3615static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3616{
3617 u32 val, rpe;
3618
64936258 3619 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 3620 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 3621 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 3622 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3623
3624 return rpe;
3625}
3626
3627int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3628{
64936258 3629 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 3630}
3631
ae48434c
ID		 3632/* Check that the pctx buffer wasn't move under us. */
3633static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
3634{
3635 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
3636
3637 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
3638 dev_priv->vlv_pctx->stolen->start);
3639}
3640
c9cddffc
JB		 3641static void valleyview_setup_pctx(struct drm_device *dev)
3642{
3643 struct drm_i915_private *dev_priv = dev->dev_private;
3644 struct drm_i915_gem_object *pctx;
3645 unsigned long pctx_paddr;
3646 u32 pcbr;
3647 int pctx_size = 24*1024;
3648
17b0c1f7
ID		 3649 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3650
c9cddffc
JB		 3651 pcbr = I915_READ(VLV_PCBR);
3652 if (pcbr) {
3653 /* BIOS set it up already, grab the pre-alloc'd space */
3654 int pcbr_offset;
3655
3656 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3657 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3658 pcbr_offset,
190d6cd5 3659 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 3660 pctx_size);
3661 goto out;
3662 }
3663
3664 /*
3665 * From the Gunit register HAS:
3666 * The Gfx driver is expected to program this register and ensure
3667 * proper allocation within Gfx stolen memory. For example, this
3668 * register should be programmed such than the PCBR range does not
3669 * overlap with other ranges, such as the frame buffer, protected
3670 * memory, or any other relevant ranges.
3671 */
3672 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3673 if (!pctx) {
3674 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3675 return;
3676 }
3677
3678 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3679 I915_WRITE(VLV_PCBR, pctx_paddr);
3680
3681out:
3682 dev_priv->vlv_pctx = pctx;
3683}
3684
ae48434c
ID		 3685static void valleyview_cleanup_pctx(struct drm_device *dev)
3686{
3687 struct drm_i915_private *dev_priv = dev->dev_private;
3688
3689 if (WARN_ON(!dev_priv->vlv_pctx))
3690 return;
3691
3692 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3693 dev_priv->vlv_pctx = NULL;
3694}
3695
4e80519e
ID		 3696static void valleyview_init_gt_powersave(struct drm_device *dev)
3697{
3698 struct drm_i915_private *dev_priv = dev->dev_private;
3699
3700 valleyview_setup_pctx(dev);
3701
3702 mutex_lock(&dev_priv->rps.hw_lock);
3703
3704 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
3705 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
3706 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3707 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
3708 dev_priv->rps.max_freq);
3709
3710 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
3711 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3712 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3713 dev_priv->rps.efficient_freq);
3714
3715 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
3716 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3717 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
3718 dev_priv->rps.min_freq);
3719
3720 /* Preserve min/max settings in case of re-init */
3721 if (dev_priv->rps.max_freq_softlimit == 0)
3722 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3723
3724 if (dev_priv->rps.min_freq_softlimit == 0)
3725 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3726
3727 mutex_unlock(&dev_priv->rps.hw_lock);
3728}
3729
3730static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
3731{
3732 valleyview_cleanup_pctx(dev);
3733}
3734
0a073b84
JB		 3735static void valleyview_enable_rps(struct drm_device *dev)
3736{
3737 struct drm_i915_private *dev_priv = dev->dev_private;
3738 struct intel_ring_buffer *ring;
2a5913a8 3739 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 3740 int i;
3741
3742 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3743
ae48434c
ID		 3744 valleyview_check_pctx(dev_priv);
3745
0a073b84 3746 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 3747 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
3748 gtfifodbg);
0a073b84
JB		 3749 I915_WRITE(GTFIFODBG, gtfifodbg);
3750 }
3751
c8d9a590
D		 3752 /* If VLV, Forcewake all wells, else re-direct to regular path */
3753 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 3754
3755 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3756 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3757 I915_WRITE(GEN6_RP_UP_EI, 66000);
3758 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3759
3760 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3761
3762 I915_WRITE(GEN6_RP_CONTROL,
3763 GEN6_RP_MEDIA_TURBO |
3764 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3765 GEN6_RP_MEDIA_IS_GFX |
3766 GEN6_RP_ENABLE |
3767 GEN6_RP_UP_BUSY_AVG |
3768 GEN6_RP_DOWN_IDLE_CONT);
3769
3770 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3771 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3772 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3773
3774 for_each_ring(ring, dev_priv, i)
3775 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3776
2f0aa304 3777 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 3778
3779 /* allows RC6 residency counter to work */
49798eb2
JB		 3780 I915_WRITE(VLV_COUNTER_CONTROL,
3781 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
3782 VLV_MEDIA_RC6_COUNT_EN |
3783 VLV_RENDER_RC6_COUNT_EN));
a2b23fe0 3784 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 3785 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 3786
3787 intel_print_rc6_info(dev, rc6_mode);
3788
a2b23fe0 3789 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 3790
64936258 3791 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 3792
3793 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3794 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3795
b39fb297 3796 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 3797 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
b39fb297
BW		 3798 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3799 dev_priv->rps.cur_freq);
0a073b84 3800
73008b98 3801 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
b39fb297
BW		 3802 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3803 dev_priv->rps.efficient_freq);
0a073b84 3804
b39fb297 3805 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 3806
44fc7d5c 3807 gen6_enable_rps_interrupts(dev);
0a073b84 3808
c8d9a590 3809 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 3810}
3811
930ebb46 3812void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 3813{
3814 struct drm_i915_private *dev_priv = dev->dev_private;
3815
3e373948 3816 if (dev_priv->ips.renderctx) {
d7f46fc4 3817 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
3e373948
DV		 3818 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3819 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 3820 }
3821
3e373948 3822 if (dev_priv->ips.pwrctx) {
d7f46fc4 3823 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
3e373948
DV		 3824 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3825 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 3826 }
3827}
3828
930ebb46 3829static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3830{
3831 struct drm_i915_private *dev_priv = dev->dev_private;
3832
3833 if (I915_READ(PWRCTXA)) {
3834 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3835 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3836 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3837 50);
3838
3839 I915_WRITE(PWRCTXA, 0);
3840 POSTING_READ(PWRCTXA);
3841
3842 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3843 POSTING_READ(RSTDBYCTL);
3844 }
2b4e57bd
ED		 3845}
3846
3847static int ironlake_setup_rc6(struct drm_device *dev)
3848{
3849 struct drm_i915_private *dev_priv = dev->dev_private;
3850
3e373948
DV		 3851 if (dev_priv->ips.renderctx == NULL)
3852 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3853 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 3854 return -ENOMEM;
3855
3e373948
DV		 3856 if (dev_priv->ips.pwrctx == NULL)
3857 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3858 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 3859 ironlake_teardown_rc6(dev);
3860 return -ENOMEM;
3861 }
3862
3863 return 0;
3864}
3865
930ebb46 3866static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3867{
3868 struct drm_i915_private *dev_priv = dev->dev_private;
6d90c952 3869 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3e960501 3870 bool was_interruptible;
2b4e57bd
ED		 3871 int ret;
3872
3873 /* rc6 disabled by default due to repeated reports of hanging during
3874 * boot and resume.
3875 */
3876 if (!intel_enable_rc6(dev))
3877 return;
3878
79f5b2c7
DV		 3879 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3880
2b4e57bd 3881 ret = ironlake_setup_rc6(dev);
79f5b2c7 3882 if (ret)
2b4e57bd 3883 return;
2b4e57bd 3884
3e960501
CW		 3885 was_interruptible = dev_priv->mm.interruptible;
3886 dev_priv->mm.interruptible = false;
3887
2b4e57bd
ED		 3888 /*
3889 * GPU can automatically power down the render unit if given a page
3890 * to save state.
3891 */
6d90c952 3892 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 3893 if (ret) {
3894 ironlake_teardown_rc6(dev);
3e960501 3895 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 3896 return;
3897 }
3898
6d90c952
DV		 3899 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3900 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 3901 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
6d90c952
DV		 3902 MI_MM_SPACE_GTT |
3903 MI_SAVE_EXT_STATE_EN |
3904 MI_RESTORE_EXT_STATE_EN |
3905 MI_RESTORE_INHIBIT);
3906 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3907 intel_ring_emit(ring, MI_NOOP);
3908 intel_ring_emit(ring, MI_FLUSH);
3909 intel_ring_advance(ring);
2b4e57bd
ED		 3910
3911 /*
3912 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3913 * does an implicit flush, combined with MI_FLUSH above, it should be
3914 * safe to assume that renderctx is valid
3915 */
3e960501
CW		 3916 ret = intel_ring_idle(ring);
3917 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 3918 if (ret) {
def27a58 3919 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 3920 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 3921 return;
3922 }
3923
f343c5f6 3924 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
2b4e57bd 3925 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
dc39fff7 3926
91ca689a 3927 intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
2b4e57bd
ED		 3928}
3929
dde18883
ED		 3930static unsigned long intel_pxfreq(u32 vidfreq)
3931{
3932 unsigned long freq;
3933 int div = (vidfreq & 0x3f0000) >> 16;
3934 int post = (vidfreq & 0x3000) >> 12;
3935 int pre = (vidfreq & 0x7);
3936
3937 if (!pre)
3938 return 0;
3939
3940 freq = ((div * 133333) / ((1<<post) * pre));
3941
3942 return freq;
3943}
3944
eb48eb00
DV		 3945static const struct cparams {
3946 u16 i;
3947 u16 t;
3948 u16 m;
3949 u16 c;
3950} cparams[] = {
3951 { 1, 1333, 301, 28664 },
3952 { 1, 1066, 294, 24460 },
3953 { 1, 800, 294, 25192 },
3954 { 0, 1333, 276, 27605 },
3955 { 0, 1066, 276, 27605 },
3956 { 0, 800, 231, 23784 },
3957};
3958
f531dcb2 3959static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 3960{
3961 u64 total_count, diff, ret;
3962 u32 count1, count2, count3, m = 0, c = 0;
3963 unsigned long now = jiffies_to_msecs(jiffies), diff1;
3964 int i;
3965
02d71956
DV		 3966 assert_spin_locked(&mchdev_lock);
3967
20e4d407 3968 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 3969
3970 /* Prevent division-by-zero if we are asking too fast.
3971 * Also, we don't get interesting results if we are polling
3972 * faster than once in 10ms, so just return the saved value
3973 * in such cases.
3974 */
3975 if (diff1 <= 10)
20e4d407 3976 return dev_priv->ips.chipset_power;
eb48eb00
DV		 3977
3978 count1 = I915_READ(DMIEC);
3979 count2 = I915_READ(DDREC);
3980 count3 = I915_READ(CSIEC);
3981
3982 total_count = count1 + count2 + count3;
3983
3984 /* FIXME: handle per-counter overflow */
20e4d407
DV		 3985 if (total_count < dev_priv->ips.last_count1) {
3986 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 3987 diff += total_count;
3988 } else {
20e4d407 3989 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 3990 }
3991
3992 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 3993 if (cparams[i].i == dev_priv->ips.c_m &&
3994 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 3995 m = cparams[i].m;
3996 c = cparams[i].c;
3997 break;
3998 }
3999 }
4000
4001 diff = div_u64(diff, diff1);
4002 ret = ((m * diff) + c);
4003 ret = div_u64(ret, 10);
4004
20e4d407
DV		 4005 dev_priv->ips.last_count1 = total_count;
4006 dev_priv->ips.last_time1 = now;
eb48eb00 4007
20e4d407 4008 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 4009
4010 return ret;
4011}
4012
f531dcb2
CW		 4013unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4014{
3d13ef2e 4015 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 4016 unsigned long val;
4017
3d13ef2e 4018 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 4019 return 0;
4020
4021 spin_lock_irq(&mchdev_lock);
4022
4023 val = __i915_chipset_val(dev_priv);
4024
4025 spin_unlock_irq(&mchdev_lock);
4026
4027 return val;
4028}
4029
eb48eb00
DV		 4030unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4031{
4032 unsigned long m, x, b;
4033 u32 tsfs;
4034
4035 tsfs = I915_READ(TSFS);
4036
4037 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4038 x = I915_READ8(TR1);
4039
4040 b = tsfs & TSFS_INTR_MASK;
4041
4042 return ((m * x) / 127) - b;
4043}
4044
4045static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4046{
3d13ef2e 4047 struct drm_device *dev = dev_priv->dev;
eb48eb00
DV		 4048 static const struct v_table {
4049 u16 vd; /* in .1 mil */
4050 u16 vm; /* in .1 mil */
4051 } v_table[] = {
4052 { 0, 0, },
4053 { 375, 0, },
4054 { 500, 0, },
4055 { 625, 0, },
4056 { 750, 0, },
4057 { 875, 0, },
4058 { 1000, 0, },
4059 { 1125, 0, },
4060 { 4125, 3000, },
4061 { 4125, 3000, },
4062 { 4125, 3000, },
4063 { 4125, 3000, },
4064 { 4125, 3000, },
4065 { 4125, 3000, },
4066 { 4125, 3000, },
4067 { 4125, 3000, },
4068 { 4125, 3000, },
4069 { 4125, 3000, },
4070 { 4125, 3000, },
4071 { 4125, 3000, },
4072 { 4125, 3000, },
4073 { 4125, 3000, },
4074 { 4125, 3000, },
4075 { 4125, 3000, },
4076 { 4125, 3000, },
4077 { 4125, 3000, },
4078 { 4125, 3000, },
4079 { 4125, 3000, },
4080 { 4125, 3000, },
4081 { 4125, 3000, },
4082 { 4125, 3000, },
4083 { 4125, 3000, },
4084 { 4250, 3125, },
4085 { 4375, 3250, },
4086 { 4500, 3375, },
4087 { 4625, 3500, },
4088 { 4750, 3625, },
4089 { 4875, 3750, },
4090 { 5000, 3875, },
4091 { 5125, 4000, },
4092 { 5250, 4125, },
4093 { 5375, 4250, },
4094 { 5500, 4375, },
4095 { 5625, 4500, },
4096 { 5750, 4625, },
4097 { 5875, 4750, },
4098 { 6000, 4875, },
4099 { 6125, 5000, },
4100 { 6250, 5125, },
4101 { 6375, 5250, },
4102 { 6500, 5375, },
4103 { 6625, 5500, },
4104 { 6750, 5625, },
4105 { 6875, 5750, },
4106 { 7000, 5875, },
4107 { 7125, 6000, },
4108 { 7250, 6125, },
4109 { 7375, 6250, },
4110 { 7500, 6375, },
4111 { 7625, 6500, },
4112 { 7750, 6625, },
4113 { 7875, 6750, },
4114 { 8000, 6875, },
4115 { 8125, 7000, },
4116 { 8250, 7125, },
4117 { 8375, 7250, },
4118 { 8500, 7375, },
4119 { 8625, 7500, },
4120 { 8750, 7625, },
4121 { 8875, 7750, },
4122 { 9000, 7875, },
4123 { 9125, 8000, },
4124 { 9250, 8125, },
4125 { 9375, 8250, },
4126 { 9500, 8375, },
4127 { 9625, 8500, },
4128 { 9750, 8625, },
4129 { 9875, 8750, },
4130 { 10000, 8875, },
4131 { 10125, 9000, },
4132 { 10250, 9125, },
4133 { 10375, 9250, },
4134 { 10500, 9375, },
4135 { 10625, 9500, },
4136 { 10750, 9625, },
4137 { 10875, 9750, },
4138 { 11000, 9875, },
4139 { 11125, 10000, },
4140 { 11250, 10125, },
4141 { 11375, 10250, },
4142 { 11500, 10375, },
4143 { 11625, 10500, },
4144 { 11750, 10625, },
4145 { 11875, 10750, },
4146 { 12000, 10875, },
4147 { 12125, 11000, },
4148 { 12250, 11125, },
4149 { 12375, 11250, },
4150 { 12500, 11375, },
4151 { 12625, 11500, },
4152 { 12750, 11625, },
4153 { 12875, 11750, },
4154 { 13000, 11875, },
4155 { 13125, 12000, },
4156 { 13250, 12125, },
4157 { 13375, 12250, },
4158 { 13500, 12375, },
4159 { 13625, 12500, },
4160 { 13750, 12625, },
4161 { 13875, 12750, },
4162 { 14000, 12875, },
4163 { 14125, 13000, },
4164 { 14250, 13125, },
4165 { 14375, 13250, },
4166 { 14500, 13375, },
4167 { 14625, 13500, },
4168 { 14750, 13625, },
4169 { 14875, 13750, },
4170 { 15000, 13875, },
4171 { 15125, 14000, },
4172 { 15250, 14125, },
4173 { 15375, 14250, },
4174 { 15500, 14375, },
4175 { 15625, 14500, },
4176 { 15750, 14625, },
4177 { 15875, 14750, },
4178 { 16000, 14875, },
4179 { 16125, 15000, },
4180 };
3d13ef2e 4181 if (INTEL_INFO(dev)->is_mobile)
eb48eb00
DV		 4182 return v_table[pxvid].vm;
4183 else
4184 return v_table[pxvid].vd;
4185}
4186
02d71956 4187static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4188{
4189 struct timespec now, diff1;
4190 u64 diff;
4191 unsigned long diffms;
4192 u32 count;
4193
02d71956 4194 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 4195
4196 getrawmonotonic(&now);
20e4d407 4197 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 4198
4199 /* Don't divide by 0 */
4200 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4201 if (!diffms)
4202 return;
4203
4204 count = I915_READ(GFXEC);
4205
20e4d407
DV		 4206 if (count < dev_priv->ips.last_count2) {
4207 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 4208 diff += count;
4209 } else {
20e4d407 4210 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 4211 }
4212
20e4d407
DV		 4213 dev_priv->ips.last_count2 = count;
4214 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 4215
4216 /* More magic constants... */
4217 diff = diff * 1181;
4218 diff = div_u64(diff, diffms * 10);
20e4d407 4219 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 4220}
4221
02d71956
DV		 4222void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4223{
3d13ef2e
DL		 4224 struct drm_device *dev = dev_priv->dev;
4225
4226 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 4227 return;
4228
9270388e 4229 spin_lock_irq(&mchdev_lock);
02d71956
DV		 4230
4231 __i915_update_gfx_val(dev_priv);
4232
9270388e 4233 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 4234}
4235
f531dcb2 4236static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4237{
4238 unsigned long t, corr, state1, corr2, state2;
4239 u32 pxvid, ext_v;
4240
02d71956
DV		 4241 assert_spin_locked(&mchdev_lock);
4242
b39fb297 4243 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
eb48eb00
DV		 4244 pxvid = (pxvid >> 24) & 0x7f;
4245 ext_v = pvid_to_extvid(dev_priv, pxvid);
4246
4247 state1 = ext_v;
4248
4249 t = i915_mch_val(dev_priv);
4250
4251 /* Revel in the empirically derived constants */
4252
4253 /* Correction factor in 1/100000 units */
4254 if (t > 80)
4255 corr = ((t * 2349) + 135940);
4256 else if (t >= 50)
4257 corr = ((t * 964) + 29317);
4258 else /* < 50 */
4259 corr = ((t * 301) + 1004);
4260
4261 corr = corr * ((150142 * state1) / 10000 - 78642);
4262 corr /= 100000;
20e4d407 4263 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 4264
4265 state2 = (corr2 * state1) / 10000;
4266 state2 /= 100; /* convert to mW */
4267
02d71956 4268 __i915_update_gfx_val(dev_priv);
eb48eb00 4269
20e4d407 4270 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 4271}
4272
f531dcb2
CW		 4273unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4274{
3d13ef2e 4275 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 4276 unsigned long val;
4277
3d13ef2e 4278 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 4279 return 0;
4280
4281 spin_lock_irq(&mchdev_lock);
4282
4283 val = __i915_gfx_val(dev_priv);
4284
4285 spin_unlock_irq(&mchdev_lock);
4286
4287 return val;
4288}
4289
eb48eb00
DV		 4290/**
4291 * i915_read_mch_val - return value for IPS use
4292 *
4293 * Calculate and return a value for the IPS driver to use when deciding whether
4294 * we have thermal and power headroom to increase CPU or GPU power budget.
4295 */
4296unsigned long i915_read_mch_val(void)
4297{
4298 struct drm_i915_private *dev_priv;
4299 unsigned long chipset_val, graphics_val, ret = 0;
4300
9270388e 4301 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4302 if (!i915_mch_dev)
4303 goto out_unlock;
4304 dev_priv = i915_mch_dev;
4305
f531dcb2
CW		 4306 chipset_val = __i915_chipset_val(dev_priv);
4307 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 4308
4309 ret = chipset_val + graphics_val;
4310
4311out_unlock:
9270388e 4312 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4313
4314 return ret;
4315}
4316EXPORT_SYMBOL_GPL(i915_read_mch_val);
4317
4318/**
4319 * i915_gpu_raise - raise GPU frequency limit
4320 *
4321 * Raise the limit; IPS indicates we have thermal headroom.
4322 */
4323bool i915_gpu_raise(void)
4324{
4325 struct drm_i915_private *dev_priv;
4326 bool ret = true;
4327
9270388e 4328 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4329 if (!i915_mch_dev) {
4330 ret = false;
4331 goto out_unlock;
4332 }
4333 dev_priv = i915_mch_dev;
4334
20e4d407
DV		 4335 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4336 dev_priv->ips.max_delay--;
eb48eb00
DV		 4337
4338out_unlock:
9270388e 4339 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4340
4341 return ret;
4342}
4343EXPORT_SYMBOL_GPL(i915_gpu_raise);
4344
4345/**
4346 * i915_gpu_lower - lower GPU frequency limit
4347 *
4348 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4349 * frequency maximum.
4350 */
4351bool i915_gpu_lower(void)
4352{
4353 struct drm_i915_private *dev_priv;
4354 bool ret = true;
4355
9270388e 4356 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4357 if (!i915_mch_dev) {
4358 ret = false;
4359 goto out_unlock;
4360 }
4361 dev_priv = i915_mch_dev;
4362
20e4d407
DV		 4363 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4364 dev_priv->ips.max_delay++;
eb48eb00
DV		 4365
4366out_unlock:
9270388e 4367 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4368
4369 return ret;
4370}
4371EXPORT_SYMBOL_GPL(i915_gpu_lower);
4372
4373/**
4374 * i915_gpu_busy - indicate GPU business to IPS
4375 *
4376 * Tell the IPS driver whether or not the GPU is busy.
4377 */
4378bool i915_gpu_busy(void)
4379{
4380 struct drm_i915_private *dev_priv;
f047e395 4381 struct intel_ring_buffer *ring;
eb48eb00 4382 bool ret = false;
f047e395 4383 int i;
eb48eb00 4384
9270388e 4385 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4386 if (!i915_mch_dev)
4387 goto out_unlock;
4388 dev_priv = i915_mch_dev;
4389
f047e395
CW		 4390 for_each_ring(ring, dev_priv, i)
4391 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 4392
4393out_unlock:
9270388e 4394 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4395
4396 return ret;
4397}
4398EXPORT_SYMBOL_GPL(i915_gpu_busy);
4399
4400/**
4401 * i915_gpu_turbo_disable - disable graphics turbo
4402 *
4403 * Disable graphics turbo by resetting the max frequency and setting the
4404 * current frequency to the default.
4405 */
4406bool i915_gpu_turbo_disable(void)
4407{
4408 struct drm_i915_private *dev_priv;
4409 bool ret = true;
4410
9270388e 4411 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4412 if (!i915_mch_dev) {
4413 ret = false;
4414 goto out_unlock;
4415 }
4416 dev_priv = i915_mch_dev;
4417
20e4d407 4418 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 4419
20e4d407 4420 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 4421 ret = false;
4422
4423out_unlock:
9270388e 4424 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4425
4426 return ret;
4427}
4428EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4429
4430/**
4431 * Tells the intel_ips driver that the i915 driver is now loaded, if
4432 * IPS got loaded first.
4433 *
4434 * This awkward dance is so that neither module has to depend on the
4435 * other in order for IPS to do the appropriate communication of
4436 * GPU turbo limits to i915.
4437 */
4438static void
4439ips_ping_for_i915_load(void)
4440{
4441 void (*link)(void);
4442
4443 link = symbol_get(ips_link_to_i915_driver);
4444 if (link) {
4445 link();
4446 symbol_put(ips_link_to_i915_driver);
4447 }
4448}
4449
4450void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4451{
02d71956
DV		 4452 /* We only register the i915 ips part with intel-ips once everything is
4453 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 4454 spin_lock_irq(&mchdev_lock);
eb48eb00 4455 i915_mch_dev = dev_priv;
9270388e 4456 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4457
4458 ips_ping_for_i915_load();
4459}
4460
4461void intel_gpu_ips_teardown(void)
4462{
9270388e 4463 spin_lock_irq(&mchdev_lock);
eb48eb00 4464 i915_mch_dev = NULL;
9270388e 4465 spin_unlock_irq(&mchdev_lock);
eb48eb00 4466}
76c3552f 4467
8090c6b9 4468static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 4469{
4470 struct drm_i915_private *dev_priv = dev->dev_private;
4471 u32 lcfuse;
4472 u8 pxw[16];
4473 int i;
4474
4475 /* Disable to program */
4476 I915_WRITE(ECR, 0);
4477 POSTING_READ(ECR);
4478
4479 /* Program energy weights for various events */
4480 I915_WRITE(SDEW, 0x15040d00);
4481 I915_WRITE(CSIEW0, 0x007f0000);
4482 I915_WRITE(CSIEW1, 0x1e220004);
4483 I915_WRITE(CSIEW2, 0x04000004);
4484
4485 for (i = 0; i < 5; i++)
4486 I915_WRITE(PEW + (i * 4), 0);
4487 for (i = 0; i < 3; i++)
4488 I915_WRITE(DEW + (i * 4), 0);
4489
4490 /* Program P-state weights to account for frequency power adjustment */
4491 for (i = 0; i < 16; i++) {
4492 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4493 unsigned long freq = intel_pxfreq(pxvidfreq);
4494 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4495 PXVFREQ_PX_SHIFT;
4496 unsigned long val;
4497
4498 val = vid * vid;
4499 val *= (freq / 1000);
4500 val *= 255;
4501 val /= (127*127*900);
4502 if (val > 0xff)
4503 DRM_ERROR("bad pxval: %ld\n", val);
4504 pxw[i] = val;
4505 }
4506 /* Render standby states get 0 weight */
4507 pxw[14] = 0;
4508 pxw[15] = 0;
4509
4510 for (i = 0; i < 4; i++) {
4511 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4512 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4513 I915_WRITE(PXW + (i * 4), val);
4514 }
4515
4516 /* Adjust magic regs to magic values (more experimental results) */
4517 I915_WRITE(OGW0, 0);
4518 I915_WRITE(OGW1, 0);
4519 I915_WRITE(EG0, 0x00007f00);
4520 I915_WRITE(EG1, 0x0000000e);
4521 I915_WRITE(EG2, 0x000e0000);
4522 I915_WRITE(EG3, 0x68000300);
4523 I915_WRITE(EG4, 0x42000000);
4524 I915_WRITE(EG5, 0x00140031);
4525 I915_WRITE(EG6, 0);
4526 I915_WRITE(EG7, 0);
4527
4528 for (i = 0; i < 8; i++)
4529 I915_WRITE(PXWL + (i * 4), 0);
4530
4531 /* Enable PMON + select events */
4532 I915_WRITE(ECR, 0x80000019);
4533
4534 lcfuse = I915_READ(LCFUSE02);
4535
20e4d407 4536 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 4537}
4538
ae48434c
ID		 4539void intel_init_gt_powersave(struct drm_device *dev)
4540{
e6069ca8
ID		 4541 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
4542
ae48434c 4543 if (IS_VALLEYVIEW(dev))
4e80519e 4544 valleyview_init_gt_powersave(dev);
ae48434c
ID		 4545}
4546
4547void intel_cleanup_gt_powersave(struct drm_device *dev)
4548{
4549 if (IS_VALLEYVIEW(dev))
4e80519e 4550 valleyview_cleanup_gt_powersave(dev);
ae48434c
ID		 4551}
4552
8090c6b9
DV		 4553void intel_disable_gt_powersave(struct drm_device *dev)
4554{
1a01ab3b
JB		 4555 struct drm_i915_private *dev_priv = dev->dev_private;
4556
fd0c0642
DV		 4557 /* Interrupts should be disabled already to avoid re-arming. */
4558 WARN_ON(dev->irq_enabled);
4559
930ebb46 4560 if (IS_IRONLAKE_M(dev)) {
8090c6b9 4561 ironlake_disable_drps(dev);
930ebb46 4562 ironlake_disable_rc6(dev);
14dd0ea8 4563 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1a01ab3b 4564 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
250848ca 4565 cancel_work_sync(&dev_priv->rps.work);
4fc688ce 4566 mutex_lock(&dev_priv->rps.hw_lock);
d20d4f0c
JB		 4567 if (IS_VALLEYVIEW(dev))
4568 valleyview_disable_rps(dev);
4569 else
4570 gen6_disable_rps(dev);
c0951f0c 4571 dev_priv->rps.enabled = false;
4fc688ce 4572 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 4573 }
8090c6b9
DV		 4574}
4575
1a01ab3b
JB		 4576static void intel_gen6_powersave_work(struct work_struct *work)
4577{
4578 struct drm_i915_private *dev_priv =
4579 container_of(work, struct drm_i915_private,
4580 rps.delayed_resume_work.work);
4581 struct drm_device *dev = dev_priv->dev;
4582
4fc688ce 4583 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84
JB		 4584
4585 if (IS_VALLEYVIEW(dev)) {
4586 valleyview_enable_rps(dev);
6edee7f3
BW		 4587 } else if (IS_BROADWELL(dev)) {
4588 gen8_enable_rps(dev);
c2bc2fc5 4589 __gen6_update_ring_freq(dev);
0a073b84
JB		 4590 } else {
4591 gen6_enable_rps(dev);
c2bc2fc5 4592 __gen6_update_ring_freq(dev);
0a073b84 4593 }
c0951f0c 4594 dev_priv->rps.enabled = true;
4fc688ce 4595 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 4596
4597 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 4598}
4599
8090c6b9
DV		 4600void intel_enable_gt_powersave(struct drm_device *dev)
4601{
1a01ab3b
JB		 4602 struct drm_i915_private *dev_priv = dev->dev_private;
4603
8090c6b9 4604 if (IS_IRONLAKE_M(dev)) {
dc1d0136 4605 mutex_lock(&dev->struct_mutex);
8090c6b9
DV		 4606 ironlake_enable_drps(dev);
4607 ironlake_enable_rc6(dev);
4608 intel_init_emon(dev);
dc1d0136 4609 mutex_unlock(&dev->struct_mutex);
0a073b84 4610 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1a01ab3b
JB		 4611 /*
4612 * PCU communication is slow and this doesn't need to be
4613 * done at any specific time, so do this out of our fast path
4614 * to make resume and init faster.
c6df39b5
ID		 4615 *
4616 * We depend on the HW RC6 power context save/restore
4617 * mechanism when entering D3 through runtime PM suspend. So
4618 * disable RPM until RPS/RC6 is properly setup. We can only
4619 * get here via the driver load/system resume/runtime resume
4620 * paths, so the _noresume version is enough (and in case of
4621 * runtime resume it's necessary).
1a01ab3b 4622 */
c6df39b5
ID		 4623 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4624 round_jiffies_up_relative(HZ)))
4625 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 4626 }
4627}
4628
c6df39b5
ID		 4629void intel_reset_gt_powersave(struct drm_device *dev)
4630{
4631 struct drm_i915_private *dev_priv = dev->dev_private;
4632
4633 dev_priv->rps.enabled = false;
4634 intel_enable_gt_powersave(dev);
4635}
4636
3107bd48
DV		 4637static void ibx_init_clock_gating(struct drm_device *dev)
4638{
4639 struct drm_i915_private *dev_priv = dev->dev_private;
4640
4641 /*
4642 * On Ibex Peak and Cougar Point, we need to disable clock
4643 * gating for the panel power sequencer or it will fail to
4644 * start up when no ports are active.
4645 */
4646 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4647}
4648
0e088b8f
VS		 4649static void g4x_disable_trickle_feed(struct drm_device *dev)
4650{
4651 struct drm_i915_private *dev_priv = dev->dev_private;
4652 int pipe;
4653
4654 for_each_pipe(pipe) {
4655 I915_WRITE(DSPCNTR(pipe),
4656 I915_READ(DSPCNTR(pipe)) |
4657 DISPPLANE_TRICKLE_FEED_DISABLE);
1dba99f4 4658 intel_flush_primary_plane(dev_priv, pipe);
0e088b8f
VS		 4659 }
4660}
4661
017636cc
VS		 4662static void ilk_init_lp_watermarks(struct drm_device *dev)
4663{
4664 struct drm_i915_private *dev_priv = dev->dev_private;
4665
4666 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
4667 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
4668 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
4669
4670 /*
4671 * Don't touch WM1S_LP_EN here.
4672 * Doing so could cause underruns.
4673 */
4674}
4675
1fa61106 4676static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4677{
4678 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4679 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4680
f1e8fa56
DL		 4681 /*
4682 * Required for FBC
4683 * WaFbcDisableDpfcClockGating:ilk
4684 */
4d47e4f5
DL		 4685 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4686 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4687 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4688
4689 I915_WRITE(PCH_3DCGDIS0,
4690 MARIUNIT_CLOCK_GATE_DISABLE |
4691 SVSMUNIT_CLOCK_GATE_DISABLE);
4692 I915_WRITE(PCH_3DCGDIS1,
4693 VFMUNIT_CLOCK_GATE_DISABLE);
4694
6f1d69b0
ED		 4695 /*
4696 * According to the spec the following bits should be set in
4697 * order to enable memory self-refresh
4698 * The bit 22/21 of 0x42004
4699 * The bit 5 of 0x42020
4700 * The bit 15 of 0x45000
4701 */
4702 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4703 (I915_READ(ILK_DISPLAY_CHICKEN2) |
4704 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 4705 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4706 I915_WRITE(DISP_ARB_CTL,
4707 (I915_READ(DISP_ARB_CTL) |
4708 DISP_FBC_WM_DIS));
017636cc
VS		 4709
4710 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 4711
4712 /*
4713 * Based on the document from hardware guys the following bits
4714 * should be set unconditionally in order to enable FBC.
4715 * The bit 22 of 0x42000
4716 * The bit 22 of 0x42004
4717 * The bit 7,8,9 of 0x42020.
4718 */
4719 if (IS_IRONLAKE_M(dev)) {
4bb35334 4720 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 4721 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4722 I915_READ(ILK_DISPLAY_CHICKEN1) |
4723 ILK_FBCQ_DIS);
4724 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4725 I915_READ(ILK_DISPLAY_CHICKEN2) |
4726 ILK_DPARB_GATE);
6f1d69b0
ED		 4727 }
4728
4d47e4f5
DL		 4729 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4730
6f1d69b0
ED		 4731 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4732 I915_READ(ILK_DISPLAY_CHICKEN2) |
4733 ILK_ELPIN_409_SELECT);
4734 I915_WRITE(_3D_CHICKEN2,
4735 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4736 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 4737
ecdb4eb7 4738 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 4739 I915_WRITE(CACHE_MODE_0,
4740 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 4741
4e04632e
AG		 4742 /* WaDisable_RenderCache_OperationalFlush:ilk */
4743 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
4744
0e088b8f 4745 g4x_disable_trickle_feed(dev);
bdad2b2f 4746
3107bd48
DV		 4747 ibx_init_clock_gating(dev);
4748}
4749
4750static void cpt_init_clock_gating(struct drm_device *dev)
4751{
4752 struct drm_i915_private *dev_priv = dev->dev_private;
4753 int pipe;
3f704fa2 4754 uint32_t val;
3107bd48
DV		 4755
4756 /*
4757 * On Ibex Peak and Cougar Point, we need to disable clock
4758 * gating for the panel power sequencer or it will fail to
4759 * start up when no ports are active.
4760 */
cd664078
JB		 4761 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
4762 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
4763 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 4764 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4765 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 4766 /* The below fixes the weird display corruption, a few pixels shifted
4767 * downward, on (only) LVDS of some HP laptops with IVY.
4768 */
3f704fa2 4769 for_each_pipe(pipe) {
dc4bd2d1
PZ		 4770 val = I915_READ(TRANS_CHICKEN2(pipe));
4771 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4772 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 4773 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 4774 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 4775 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4776 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4777 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 4778 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4779 }
3107bd48
DV		 4780 /* WADP0ClockGatingDisable */
4781 for_each_pipe(pipe) {
4782 I915_WRITE(TRANS_CHICKEN1(pipe),
4783 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4784 }
6f1d69b0
ED		 4785}
4786
1d7aaa0c
DV		 4787static void gen6_check_mch_setup(struct drm_device *dev)
4788{
4789 struct drm_i915_private *dev_priv = dev->dev_private;
4790 uint32_t tmp;
4791
4792 tmp = I915_READ(MCH_SSKPD);
4793 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4794 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4795 DRM_INFO("This can cause pipe underruns and display issues.\n");
4796 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4797 }
4798}
4799
1fa61106 4800static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4801{
4802 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4803 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4804
231e54f6 4805 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 4806
4807 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4808 I915_READ(ILK_DISPLAY_CHICKEN2) |
4809 ILK_ELPIN_409_SELECT);
4810
ecdb4eb7 4811 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 4812 I915_WRITE(_3D_CHICKEN,
4813 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4814
ecdb4eb7 4815 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 4816 if (IS_SNB_GT1(dev))
4817 I915_WRITE(GEN6_GT_MODE,
4818 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4819
4e04632e
AG		 4820 /* WaDisable_RenderCache_OperationalFlush:snb */
4821 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
4822
8d85d272
VS		 4823 /*
4824 * BSpec recoomends 8x4 when MSAA is used,
4825 * however in practice 16x4 seems fastest.
c5c98a58
VS		 4826 *
4827 * Note that PS/WM thread counts depend on the WIZ hashing
4828 * disable bit, which we don't touch here, but it's good
4829 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 4830 */
4831 I915_WRITE(GEN6_GT_MODE,
4832 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
4833
017636cc 4834 ilk_init_lp_watermarks(dev);
6f1d69b0 4835
6f1d69b0 4836 I915_WRITE(CACHE_MODE_0,
50743298 4837 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 4838
4839 I915_WRITE(GEN6_UCGCTL1,
4840 I915_READ(GEN6_UCGCTL1) |
4841 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4842 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4843
4844 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4845 * gating disable must be set. Failure to set it results in
4846 * flickering pixels due to Z write ordering failures after
4847 * some amount of runtime in the Mesa "fire" demo, and Unigine
4848 * Sanctuary and Tropics, and apparently anything else with
4849 * alpha test or pixel discard.
4850 *
4851 * According to the spec, bit 11 (RCCUNIT) must also be set,
4852 * but we didn't debug actual testcases to find it out.
0f846f81 4853 *
ef59318c
VS		 4854 * WaDisableRCCUnitClockGating:snb
4855 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 4856 */
4857 I915_WRITE(GEN6_UCGCTL2,
4858 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4859 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4860
5eb146dd 4861 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 4862 I915_WRITE(_3D_CHICKEN3,
4863 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 4864
e927ecde
VS		 4865 /*
4866 * Bspec says:
4867 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
4868 * 3DSTATE_SF number of SF output attributes is more than 16."
4869 */
4870 I915_WRITE(_3D_CHICKEN3,
4871 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
4872
6f1d69b0
ED		 4873 /*
4874 * According to the spec the following bits should be
4875 * set in order to enable memory self-refresh and fbc:
4876 * The bit21 and bit22 of 0x42000
4877 * The bit21 and bit22 of 0x42004
4878 * The bit5 and bit7 of 0x42020
4879 * The bit14 of 0x70180
4880 * The bit14 of 0x71180
4bb35334
DL		 4881 *
4882 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 4883 */
4884 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4885 I915_READ(ILK_DISPLAY_CHICKEN1) |
4886 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4887 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4888 I915_READ(ILK_DISPLAY_CHICKEN2) |
4889 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 4890 I915_WRITE(ILK_DSPCLK_GATE_D,
4891 I915_READ(ILK_DSPCLK_GATE_D) |
4892 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
4893 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 4894
0e088b8f 4895 g4x_disable_trickle_feed(dev);
f8f2ac9a 4896
3107bd48 4897 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4898
4899 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4900}
4901
4902static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4903{
4904 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4905
3aad9059 4906 /*
46680e0a 4907 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 4908 *
4909 * This actually overrides the dispatch
4910 * mode for all thread types.
4911 */
6f1d69b0
ED		 4912 reg &= ~GEN7_FF_SCHED_MASK;
4913 reg |= GEN7_FF_TS_SCHED_HW;
4914 reg |= GEN7_FF_VS_SCHED_HW;
4915 reg |= GEN7_FF_DS_SCHED_HW;
4916
4917 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4918}
4919
17a303ec
PZ		 4920static void lpt_init_clock_gating(struct drm_device *dev)
4921{
4922 struct drm_i915_private *dev_priv = dev->dev_private;
4923
4924 /*
4925 * TODO: this bit should only be enabled when really needed, then
4926 * disabled when not needed anymore in order to save power.
4927 */
4928 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4929 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4930 I915_READ(SOUTH_DSPCLK_GATE_D) |
4931 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 4932
4933 /* WADPOClockGatingDisable:hsw */
4934 I915_WRITE(_TRANSA_CHICKEN1,
4935 I915_READ(_TRANSA_CHICKEN1) |
4936 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 4937}
4938
7d708ee4
ID		 4939static void lpt_suspend_hw(struct drm_device *dev)
4940{
4941 struct drm_i915_private *dev_priv = dev->dev_private;
4942
4943 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4944 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4945
4946 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4947 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4948 }
4949}
4950
1020a5c2
BW		 4951static void gen8_init_clock_gating(struct drm_device *dev)
4952{
4953 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 4954 enum pipe pipe;
1020a5c2
BW		 4955
4956 I915_WRITE(WM3_LP_ILK, 0);
4957 I915_WRITE(WM2_LP_ILK, 0);
4958 I915_WRITE(WM1_LP_ILK, 0);
50ed5fbd
BW		 4959
4960 /* FIXME(BDW): Check all the w/a, some might only apply to
4961 * pre-production hw. */
4962
c8966e10
KG		 4963 /* WaDisablePartialInstShootdown:bdw */
4964 I915_WRITE(GEN8_ROW_CHICKEN,
4965 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
4966
1411e6a5
KG		 4967 /* WaDisableThreadStallDopClockGating:bdw */
4968 /* FIXME: Unclear whether we really need this on production bdw. */
4969 I915_WRITE(GEN8_ROW_CHICKEN,
4970 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
4971
4167e32c
DL		 4972 /*
4973 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
4974 * pre-production hardware
4975 */
fd392b60
BW		 4976 I915_WRITE(HALF_SLICE_CHICKEN3,
4977 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
bf66347c
BW		 4978 I915_WRITE(HALF_SLICE_CHICKEN3,
4979 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
4afe8d33
BW		 4980 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
4981
7f88da0c
BW		 4982 I915_WRITE(_3D_CHICKEN3,
4983 _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
4984
a75f3628
BW		 4985 I915_WRITE(COMMON_SLICE_CHICKEN2,
4986 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
4987
4c2e7a5f
BW		 4988 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4989 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
4990
ab57fff1 4991 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 4992 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 4993
ab57fff1 4994 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 4995 I915_WRITE(CHICKEN_PAR1_1,
4996 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
4997
ab57fff1 4998 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
07d27e20
DL		 4999 for_each_pipe(pipe) {
5000 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 5001 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 5002 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 5003 }
63801f21
BW		 5004
5005 /* Use Force Non-Coherent whenever executing a 3D context. This is a
5006 * workaround for for a possible hang in the unlikely event a TLB
5007 * invalidation occurs during a PSD flush.
5008 */
5009 I915_WRITE(HDC_CHICKEN0,
5010 I915_READ(HDC_CHICKEN0) |
5011 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
ab57fff1
BW		 5012
5013 /* WaVSRefCountFullforceMissDisable:bdw */
5014 /* WaDSRefCountFullforceMissDisable:bdw */
5015 I915_WRITE(GEN7_FF_THREAD_MODE,
5016 I915_READ(GEN7_FF_THREAD_MODE) &
5017 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c
VS		 5018
5019 /*
5020 * BSpec recommends 8x4 when MSAA is used,
5021 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5022 *
5023 * Note that PS/WM thread counts depend on the WIZ hashing
5024 * disable bit, which we don't touch here, but it's good
5025 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
36075a4c
VS		 5026 */
5027 I915_WRITE(GEN7_GT_MODE,
5028 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
295e8bb7
VS		 5029
5030 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5031 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 5032
5033 /* WaDisableSDEUnitClockGating:bdw */
5034 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5035 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680
DL		 5036
5037 /* Wa4x4STCOptimizationDisable:bdw */
5038 I915_WRITE(CACHE_MODE_1,
5039 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
1020a5c2
BW		 5040}
5041
cad2a2d7
ED		 5042static void haswell_init_clock_gating(struct drm_device *dev)
5043{
5044 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 5045
017636cc 5046 ilk_init_lp_watermarks(dev);
cad2a2d7 5047
f3fc4884
FJ		 5048 /* L3 caching of data atomics doesn't work -- disable it. */
5049 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5050 I915_WRITE(HSW_ROW_CHICKEN3,
5051 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5052
ecdb4eb7 5053 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 5054 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5055 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5056 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5057
e36ea7ff
VS		 5058 /* WaVSRefCountFullforceMissDisable:hsw */
5059 I915_WRITE(GEN7_FF_THREAD_MODE,
5060 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 5061
4e04632e
AG		 5062 /* WaDisable_RenderCache_OperationalFlush:hsw */
5063 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5064
fe27c606
CW		 5065 /* enable HiZ Raw Stall Optimization */
5066 I915_WRITE(CACHE_MODE_0_GEN7,
5067 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5068
ecdb4eb7 5069 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 5070 I915_WRITE(CACHE_MODE_1,
5071 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 5072
a12c4967
VS		 5073 /*
5074 * BSpec recommends 8x4 when MSAA is used,
5075 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5076 *
5077 * Note that PS/WM thread counts depend on the WIZ hashing
5078 * disable bit, which we don't touch here, but it's good
5079 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 5080 */
5081 I915_WRITE(GEN7_GT_MODE,
5082 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5083
ecdb4eb7 5084 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 5085 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5086
90a88643
PZ		 5087 /* WaRsPkgCStateDisplayPMReq:hsw */
5088 I915_WRITE(CHICKEN_PAR1_1,
5089 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 5090
17a303ec 5091 lpt_init_clock_gating(dev);
cad2a2d7
ED		 5092}
5093
1fa61106 5094static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5095{
5096 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 5097 uint32_t snpcr;
6f1d69b0 5098
017636cc 5099 ilk_init_lp_watermarks(dev);
6f1d69b0 5100
231e54f6 5101 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5102
ecdb4eb7 5103 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 5104 I915_WRITE(_3D_CHICKEN3,
5105 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5106
ecdb4eb7 5107 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 5108 I915_WRITE(IVB_CHICKEN3,
5109 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5110 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5111
ecdb4eb7 5112 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 5113 if (IS_IVB_GT1(dev))
5114 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5115 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 5116
4e04632e
AG		 5117 /* WaDisable_RenderCache_OperationalFlush:ivb */
5118 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5119
ecdb4eb7 5120 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 5121 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5122 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5123
ecdb4eb7 5124 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 5125 I915_WRITE(GEN7_L3CNTLREG1,
5126 GEN7_WA_FOR_GEN7_L3_CONTROL);
5127 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 5128 GEN7_WA_L3_CHICKEN_MODE);
5129 if (IS_IVB_GT1(dev))
5130 I915_WRITE(GEN7_ROW_CHICKEN2,
5131 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 5132 else {
5133 /* must write both registers */
5134 I915_WRITE(GEN7_ROW_CHICKEN2,
5135 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 5136 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5137 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 5138 }
6f1d69b0 5139
ecdb4eb7 5140 /* WaForceL3Serialization:ivb */
61939d97
JB		 5141 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5142 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5143
1b80a19a 5144 /*
0f846f81 5145 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5146 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 5147 */
5148 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 5149 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 5150
ecdb4eb7 5151 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 5152 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5153 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5154 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5155
0e088b8f 5156 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5157
5158 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 5159
22721343
CW		 5160 if (0) { /* causes HiZ corruption on ivb:gt1 */
5161 /* enable HiZ Raw Stall Optimization */
5162 I915_WRITE(CACHE_MODE_0_GEN7,
5163 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5164 }
116f2b6d 5165
ecdb4eb7 5166 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 5167 I915_WRITE(CACHE_MODE_1,
5168 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 5169
a607c1a4
VS		 5170 /*
5171 * BSpec recommends 8x4 when MSAA is used,
5172 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5173 *
5174 * Note that PS/WM thread counts depend on the WIZ hashing
5175 * disable bit, which we don't touch here, but it's good
5176 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 5177 */
5178 I915_WRITE(GEN7_GT_MODE,
5179 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5180
20848223
BW		 5181 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5182 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5183 snpcr |= GEN6_MBC_SNPCR_MED;
5184 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 5185
ab5c608b
BW		 5186 if (!HAS_PCH_NOP(dev))
5187 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5188
5189 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5190}
5191
1fa61106 5192static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5193{
5194 struct drm_i915_private *dev_priv = dev->dev_private;
85b1d7b3
JB		 5195 u32 val;
5196
5197 mutex_lock(&dev_priv->rps.hw_lock);
5198 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5199 mutex_unlock(&dev_priv->rps.hw_lock);
5200 switch ((val >> 6) & 3) {
5201 case 0:
f64a28a7 5202 case 1:
f6d51948 5203 dev_priv->mem_freq = 800;
85b1d7b3 5204 break;
f64a28a7 5205 case 2:
f6d51948 5206 dev_priv->mem_freq = 1066;
85b1d7b3 5207 break;
f64a28a7 5208 case 3:
2325991e 5209 dev_priv->mem_freq = 1333;
f64a28a7 5210 break;
85b1d7b3
JB		 5211 }
5212 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
6f1d69b0 5213
d60c4473
ID		 5214 dev_priv->vlv_cdclk_freq = valleyview_cur_cdclk(dev_priv);
5215 DRM_DEBUG_DRIVER("Current CD clock rate: %d MHz",
5216 dev_priv->vlv_cdclk_freq);
5217
d7fe0cc0 5218 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5219
ecdb4eb7 5220 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 5221 I915_WRITE(_3D_CHICKEN3,
5222 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5223
ecdb4eb7 5224 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 5225 I915_WRITE(IVB_CHICKEN3,
5226 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5227 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5228
fad7d36e 5229 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 5230 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 5231 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 5232 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5233 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 5234
4e04632e
AG		 5235 /* WaDisable_RenderCache_OperationalFlush:vlv */
5236 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5237
ecdb4eb7 5238 /* WaForceL3Serialization:vlv */
61939d97
JB		 5239 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5240 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5241
ecdb4eb7 5242 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 5243 I915_WRITE(GEN7_ROW_CHICKEN2,
5244 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5245
ecdb4eb7 5246 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 5247 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5248 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5249 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5250
46680e0a
VS		 5251 gen7_setup_fixed_func_scheduler(dev_priv);
5252
3c0edaeb 5253 /*
0f846f81 5254 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5255 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 5256 */
5257 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 5258 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 5259
c5c32cda 5260 /* WaDisableL3Bank2xClockGate:vlv */
e3f33d46
JB		 5261 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5262
e0d8d59b 5263 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 5264
afd58e79
VS		 5265 /*
5266 * BSpec says this must be set, even though
5267 * WaDisable4x2SubspanOptimization isn't listed for VLV.
5268 */
6b26c86d
DV		 5269 I915_WRITE(CACHE_MODE_1,
5270 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 5271
031994ee
VS		 5272 /*
5273 * WaIncreaseL3CreditsForVLVB0:vlv
5274 * This is the hardware default actually.
5275 */
5276 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
5277
2d809570 5278 /*
ecdb4eb7 5279 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 5280 * Disable clock gating on th GCFG unit to prevent a delay
5281 * in the reporting of vblank events.
5282 */
7a0d1eed 5283 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 5284}
5285
1fa61106 5286static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5287{
5288 struct drm_i915_private *dev_priv = dev->dev_private;
5289 uint32_t dspclk_gate;
5290
5291 I915_WRITE(RENCLK_GATE_D1, 0);
5292 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5293 GS_UNIT_CLOCK_GATE_DISABLE |
5294 CL_UNIT_CLOCK_GATE_DISABLE);
5295 I915_WRITE(RAMCLK_GATE_D, 0);
5296 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5297 OVRUNIT_CLOCK_GATE_DISABLE |
5298 OVCUNIT_CLOCK_GATE_DISABLE;
5299 if (IS_GM45(dev))
5300 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5301 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 5302
5303 /* WaDisableRenderCachePipelinedFlush */
5304 I915_WRITE(CACHE_MODE_0,
5305 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 5306
4e04632e
AG		 5307 /* WaDisable_RenderCache_OperationalFlush:g4x */
5308 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5309
0e088b8f 5310 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5311}
5312
1fa61106 5313static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5314{
5315 struct drm_i915_private *dev_priv = dev->dev_private;
5316
5317 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5318 I915_WRITE(RENCLK_GATE_D2, 0);
5319 I915_WRITE(DSPCLK_GATE_D, 0);
5320 I915_WRITE(RAMCLK_GATE_D, 0);
5321 I915_WRITE16(DEUC, 0);
20f94967
VS		 5322 I915_WRITE(MI_ARB_STATE,
5323 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 5324
5325 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5326 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 5327}
5328
1fa61106 5329static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5330{
5331 struct drm_i915_private *dev_priv = dev->dev_private;
5332
5333 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5334 I965_RCC_CLOCK_GATE_DISABLE |
5335 I965_RCPB_CLOCK_GATE_DISABLE |
5336 I965_ISC_CLOCK_GATE_DISABLE |
5337 I965_FBC_CLOCK_GATE_DISABLE);
5338 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 5339 I915_WRITE(MI_ARB_STATE,
5340 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 5341
5342 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5343 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 5344}
5345
1fa61106 5346static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5347{
5348 struct drm_i915_private *dev_priv = dev->dev_private;
5349 u32 dstate = I915_READ(D_STATE);
5350
5351 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5352 DSTATE_DOT_CLOCK_GATING;
5353 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 5354
5355 if (IS_PINEVIEW(dev))
5356 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 5357
5358 /* IIR "flip pending" means done if this bit is set */
5359 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6f1d69b0
ED		 5360}
5361
1fa61106 5362static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5363{
5364 struct drm_i915_private *dev_priv = dev->dev_private;
5365
5366 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5367}
5368
1fa61106 5369static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5370{
5371 struct drm_i915_private *dev_priv = dev->dev_private;
5372
5373 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5374}
5375
6f1d69b0
ED		 5376void intel_init_clock_gating(struct drm_device *dev)
5377{
5378 struct drm_i915_private *dev_priv = dev->dev_private;
5379
5380 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 5381}
5382
7d708ee4
ID		 5383void intel_suspend_hw(struct drm_device *dev)
5384{
5385 if (HAS_PCH_LPT(dev))
5386 lpt_suspend_hw(dev);
5387}
5388
c1ca727f
ID		 5389#define for_each_power_well(i, power_well, domain_mask, power_domains) \
5390 for (i = 0; \
5391 i < (power_domains)->power_well_count && \
5392 ((power_well) = &(power_domains)->power_wells[i]); \
5393 i++) \
5394 if ((power_well)->domains & (domain_mask))
5395
5396#define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5397 for (i = (power_domains)->power_well_count - 1; \
5398 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5399 i--) \
5400 if ((power_well)->domains & (domain_mask))
5401
15d199ea
PZ		 5402/**
5403 * We should only use the power well if we explicitly asked the hardware to
5404 * enable it, so check if it's enabled and also check if we've requested it to
5405 * be enabled.
5406 */
da7e29bd 5407static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
c1ca727f
ID		 5408 struct i915_power_well *power_well)
5409{
c1ca727f
ID		 5410 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5411 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5412}
5413
da7e29bd 5414bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
ddf9c536
ID		 5415 enum intel_display_power_domain domain)
5416{
ddf9c536
ID		 5417 struct i915_power_domains *power_domains;
5418
5419 power_domains = &dev_priv->power_domains;
5420
5421 return power_domains->domain_use_count[domain];
5422}
5423
da7e29bd 5424bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
b97186f0 5425 enum intel_display_power_domain domain)
15d199ea 5426{
c1ca727f
ID		 5427 struct i915_power_domains *power_domains;
5428 struct i915_power_well *power_well;
5429 bool is_enabled;
5430 int i;
15d199ea 5431
882244a3
PZ		 5432 if (dev_priv->pm.suspended)
5433 return false;
5434
c1ca727f
ID		 5435 power_domains = &dev_priv->power_domains;
5436
5437 is_enabled = true;
5438
5439 mutex_lock(&power_domains->lock);
5440 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6f3ef5dd
ID		 5441 if (power_well->always_on)
5442 continue;
5443
c6cb582e 5444 if (!power_well->ops->is_enabled(dev_priv, power_well)) {
c1ca727f
ID		 5445 is_enabled = false;
5446 break;
5447 }
5448 }
5449 mutex_unlock(&power_domains->lock);
5450
5451 return is_enabled;
15d199ea
PZ		 5452}
5453
93c73e8c
ID		 5454/*
5455 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5456 * when not needed anymore. We have 4 registers that can request the power well
5457 * to be enabled, and it will only be disabled if none of the registers is
5458 * requesting it to be enabled.
5459 */
d5e8fdc8
PZ		 5460static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5461{
5462 struct drm_device *dev = dev_priv->dev;
5463 unsigned long irqflags;
5464
f9dcb0df
PZ		 5465 /*
5466 * After we re-enable the power well, if we touch VGA register 0x3d5
5467 * we'll get unclaimed register interrupts. This stops after we write
5468 * anything to the VGA MSR register. The vgacon module uses this
5469 * register all the time, so if we unbind our driver and, as a
5470 * consequence, bind vgacon, we'll get stuck in an infinite loop at
5471 * console_unlock(). So make here we touch the VGA MSR register, making
5472 * sure vgacon can keep working normally without triggering interrupts
5473 * and error messages.
5474 */
5475 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5476 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
5477 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5478
d5e8fdc8
PZ		 5479 if (IS_BROADWELL(dev)) {
5480 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5481 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5482 dev_priv->de_irq_mask[PIPE_B]);
5483 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5484 ~dev_priv->de_irq_mask[PIPE_B] |
5485 GEN8_PIPE_VBLANK);
5486 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5487 dev_priv->de_irq_mask[PIPE_C]);
5488 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5489 ~dev_priv->de_irq_mask[PIPE_C] |
5490 GEN8_PIPE_VBLANK);
5491 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5492 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5493 }
5494}
5495
dd7c0b66
ID		 5496static void reset_vblank_counter(struct drm_device *dev, enum pipe pipe)
5497{
5498 assert_spin_locked(&dev->vbl_lock);
5499
5500 dev->vblank[pipe].last = 0;
5501}
5502
d5e8fdc8
PZ		 5503static void hsw_power_well_post_disable(struct drm_i915_private *dev_priv)
5504{
5505 struct drm_device *dev = dev_priv->dev;
07d27e20 5506 enum pipe pipe;
d5e8fdc8
PZ		 5507 unsigned long irqflags;
5508
5509 /*
5510 * After this, the registers on the pipes that are part of the power
5511 * well will become zero, so we have to adjust our counters according to
5512 * that.
5513 *
5514 * FIXME: Should we do this in general in drm_vblank_post_modeset?
5515 */
5516 spin_lock_irqsave(&dev->vbl_lock, irqflags);
07d27e20
DL		 5517 for_each_pipe(pipe)
5518 if (pipe != PIPE_A)
dd7c0b66 5519 reset_vblank_counter(dev, pipe);
d5e8fdc8
PZ		 5520 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
5521}
5522
da7e29bd 5523static void hsw_set_power_well(struct drm_i915_private *dev_priv,
c1ca727f 5524 struct i915_power_well *power_well, bool enable)
d0d3e513 5525{
fa42e23c
PZ		 5526 bool is_enabled, enable_requested;
5527 uint32_t tmp;
d0d3e513 5528
fa42e23c 5529 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
6aedd1f5
PZ		 5530 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5531 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
d0d3e513 5532
fa42e23c
PZ		 5533 if (enable) {
5534 if (!enable_requested)
6aedd1f5
PZ		 5535 I915_WRITE(HSW_PWR_WELL_DRIVER,
5536 HSW_PWR_WELL_ENABLE_REQUEST);
d0d3e513 5537
fa42e23c
PZ		 5538 if (!is_enabled) {
5539 DRM_DEBUG_KMS("Enabling power well\n");
5540 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
6aedd1f5 5541 HSW_PWR_WELL_STATE_ENABLED), 20))
fa42e23c
PZ		 5542 DRM_ERROR("Timeout enabling power well\n");
5543 }
596cc11e 5544
d5e8fdc8 5545 hsw_power_well_post_enable(dev_priv);
fa42e23c
PZ		 5546 } else {
5547 if (enable_requested) {
5548 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
9dbd8feb 5549 POSTING_READ(HSW_PWR_WELL_DRIVER);
fa42e23c 5550 DRM_DEBUG_KMS("Requesting to disable the power well\n");
9dbd8feb 5551
d5e8fdc8 5552 hsw_power_well_post_disable(dev_priv);
d0d3e513
ED		 5553 }
5554 }
fa42e23c 5555}
d0d3e513 5556
c6cb582e
ID		 5557static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
5558 struct i915_power_well *power_well)
5559{
5560 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
5561
5562 /*
5563 * We're taking over the BIOS, so clear any requests made by it since
5564 * the driver is in charge now.
5565 */
5566 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5567 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5568}
5569
5570static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
5571 struct i915_power_well *power_well)
5572{
c6cb582e
ID		 5573 hsw_set_power_well(dev_priv, power_well, true);
5574}
5575
5576static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
5577 struct i915_power_well *power_well)
5578{
5579 hsw_set_power_well(dev_priv, power_well, false);
c6cb582e
ID		 5580}
5581
a45f4466
ID		 5582static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
5583 struct i915_power_well *power_well)
5584{
5585}
5586
5587static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
5588 struct i915_power_well *power_well)
5589{
5590 return true;
5591}
5592
77961eb9
ID		 5593static void vlv_set_power_well(struct drm_i915_private *dev_priv,
5594 struct i915_power_well *power_well, bool enable)
5595{
5596 enum punit_power_well power_well_id = power_well->data;
5597 u32 mask;
5598 u32 state;
5599 u32 ctrl;
5600
5601 mask = PUNIT_PWRGT_MASK(power_well_id);
5602 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
5603 PUNIT_PWRGT_PWR_GATE(power_well_id);
5604
5605 mutex_lock(&dev_priv->rps.hw_lock);
5606
5607#define COND \
5608 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
5609
5610 if (COND)
5611 goto out;
5612
5613 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
5614 ctrl &= ~mask;
5615 ctrl |= state;
5616 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
5617
5618 if (wait_for(COND, 100))
5619 DRM_ERROR("timout setting power well state %08x (%08x)\n",
5620 state,
5621 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
5622
5623#undef COND
5624
5625out:
5626 mutex_unlock(&dev_priv->rps.hw_lock);
5627}
5628
5629static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
5630 struct i915_power_well *power_well)
5631{
5632 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
5633}
5634
5635static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
5636 struct i915_power_well *power_well)
5637{
5638 vlv_set_power_well(dev_priv, power_well, true);
5639}
5640
5641static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
5642 struct i915_power_well *power_well)
5643{
5644 vlv_set_power_well(dev_priv, power_well, false);
5645}
5646
5647static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
5648 struct i915_power_well *power_well)
5649{
5650 int power_well_id = power_well->data;
5651 bool enabled = false;
5652 u32 mask;
5653 u32 state;
5654 u32 ctrl;
5655
5656 mask = PUNIT_PWRGT_MASK(power_well_id);
5657 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
5658
5659 mutex_lock(&dev_priv->rps.hw_lock);
5660
5661 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
5662 /*
5663 * We only ever set the power-on and power-gate states, anything
5664 * else is unexpected.
5665 */
5666 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
5667 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
5668 if (state == ctrl)
5669 enabled = true;
5670
5671 /*
5672 * A transient state at this point would mean some unexpected party
5673 * is poking at the power controls too.
5674 */
5675 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
5676 WARN_ON(ctrl != state);
5677
5678 mutex_unlock(&dev_priv->rps.hw_lock);
5679
5680 return enabled;
5681}
5682
5683static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
5684 struct i915_power_well *power_well)
5685{
5686 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
5687
5688 vlv_set_power_well(dev_priv, power_well, true);
5689
5690 spin_lock_irq(&dev_priv->irq_lock);
5691 valleyview_enable_display_irqs(dev_priv);
5692 spin_unlock_irq(&dev_priv->irq_lock);
5693
5694 /*
5695 * During driver initialization we need to defer enabling hotplug
5696 * processing until fbdev is set up.
5697 */
5698 if (dev_priv->enable_hotplug_processing)
5699 intel_hpd_init(dev_priv->dev);
5700
5701 i915_redisable_vga_power_on(dev_priv->dev);
5702}
5703
5704static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
5705 struct i915_power_well *power_well)
5706{
5707 struct drm_device *dev = dev_priv->dev;
5708 enum pipe pipe;
5709
5710 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
5711
5712 spin_lock_irq(&dev_priv->irq_lock);
5713 for_each_pipe(pipe)
5714 __intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
5715
5716 valleyview_disable_display_irqs(dev_priv);
5717 spin_unlock_irq(&dev_priv->irq_lock);
5718
5719 spin_lock_irq(&dev->vbl_lock);
5720 for_each_pipe(pipe)
5721 reset_vblank_counter(dev, pipe);
5722 spin_unlock_irq(&dev->vbl_lock);
5723
5724 vlv_set_power_well(dev_priv, power_well, false);
5725}
5726
25eaa003
ID		 5727static void check_power_well_state(struct drm_i915_private *dev_priv,
5728 struct i915_power_well *power_well)
5729{
5730 bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
5731
5732 if (power_well->always_on || !i915.disable_power_well) {
5733 if (!enabled)
5734 goto mismatch;
5735
5736 return;
5737 }
5738
5739 if (enabled != (power_well->count > 0))
5740 goto mismatch;
5741
5742 return;
5743
5744mismatch:
5745 WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
5746 power_well->name, power_well->always_on, enabled,
5747 power_well->count, i915.disable_power_well);
5748}
5749
da7e29bd 5750void intel_display_power_get(struct drm_i915_private *dev_priv,
6765625e
VS		 5751 enum intel_display_power_domain domain)
5752{
83c00f55 5753 struct i915_power_domains *power_domains;
c1ca727f
ID		 5754 struct i915_power_well *power_well;
5755 int i;
6765625e 5756
9e6ea71a
PZ		 5757 intel_runtime_pm_get(dev_priv);
5758
83c00f55
ID		 5759 power_domains = &dev_priv->power_domains;
5760
5761 mutex_lock(&power_domains->lock);
1da51581 5762
25eaa003
ID		 5763 for_each_power_well(i, power_well, BIT(domain), power_domains) {
5764 if (!power_well->count++) {
5765 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
c6cb582e 5766 power_well->ops->enable(dev_priv, power_well);
25eaa003
ID		 5767 }
5768
5769 check_power_well_state(dev_priv, power_well);
5770 }
1da51581 5771
ddf9c536
ID		 5772 power_domains->domain_use_count[domain]++;
5773
83c00f55 5774 mutex_unlock(&power_domains->lock);
6765625e
VS		 5775}
5776
da7e29bd 5777void intel_display_power_put(struct drm_i915_private *dev_priv,
6765625e
VS		 5778 enum intel_display_power_domain domain)
5779{
83c00f55 5780 struct i915_power_domains *power_domains;
c1ca727f
ID		 5781 struct i915_power_well *power_well;
5782 int i;
6765625e 5783
83c00f55
ID		 5784 power_domains = &dev_priv->power_domains;
5785
5786 mutex_lock(&power_domains->lock);
1da51581 5787
1da51581
ID		 5788 WARN_ON(!power_domains->domain_use_count[domain]);
5789 power_domains->domain_use_count[domain]--;
ddf9c536 5790
70bf407c
ID		 5791 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5792 WARN_ON(!power_well->count);
5793
25eaa003
ID		 5794 if (!--power_well->count && i915.disable_power_well) {
5795 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
c6cb582e 5796 power_well->ops->disable(dev_priv, power_well);
25eaa003
ID		 5797 }
5798
5799 check_power_well_state(dev_priv, power_well);
70bf407c 5800 }
1da51581 5801
83c00f55 5802 mutex_unlock(&power_domains->lock);
9e6ea71a
PZ		 5803
5804 intel_runtime_pm_put(dev_priv);
6765625e
VS		 5805}
5806
83c00f55 5807static struct i915_power_domains *hsw_pwr;
a38911a3
WX		 5808
5809/* Display audio driver power well request */
5810void i915_request_power_well(void)
5811{
b4ed4484
ID		 5812 struct drm_i915_private *dev_priv;
5813
a38911a3
WX		 5814 if (WARN_ON(!hsw_pwr))
5815 return;
5816
b4ed4484
ID		 5817 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5818 power_domains);
da7e29bd 5819 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
a38911a3
WX		 5820}
5821EXPORT_SYMBOL_GPL(i915_request_power_well);
5822
5823/* Display audio driver power well release */
5824void i915_release_power_well(void)
5825{
b4ed4484
ID		 5826 struct drm_i915_private *dev_priv;
5827
a38911a3
WX		 5828 if (WARN_ON(!hsw_pwr))
5829 return;
5830
b4ed4484
ID		 5831 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5832 power_domains);
da7e29bd 5833 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
a38911a3
WX		 5834}
5835EXPORT_SYMBOL_GPL(i915_release_power_well);
5836
efcad917
ID		 5837#define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
5838
5839#define HSW_ALWAYS_ON_POWER_DOMAINS ( \
5840 BIT(POWER_DOMAIN_PIPE_A) | \
f5938f36 5841 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
319be8ae
ID		 5842 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
5843 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
5844 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
5845 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
5846 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
5847 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
5848 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
5849 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
5850 BIT(POWER_DOMAIN_PORT_CRT) | \
f5938f36 5851 BIT(POWER_DOMAIN_INIT))
efcad917
ID		 5852#define HSW_DISPLAY_POWER_DOMAINS ( \
5853 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
5854 BIT(POWER_DOMAIN_INIT))
5855
5856#define BDW_ALWAYS_ON_POWER_DOMAINS ( \
5857 HSW_ALWAYS_ON_POWER_DOMAINS | \
5858 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
5859#define BDW_DISPLAY_POWER_DOMAINS ( \
5860 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
5861 BIT(POWER_DOMAIN_INIT))
5862
77961eb9
ID		 5863#define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
5864#define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
5865
5866#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
5867 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
5868 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
5869 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
5870 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
5871 BIT(POWER_DOMAIN_PORT_CRT) | \
5872 BIT(POWER_DOMAIN_INIT))
5873
5874#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
5875 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
5876 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
5877 BIT(POWER_DOMAIN_INIT))
5878
5879#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
5880 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
5881 BIT(POWER_DOMAIN_INIT))
5882
5883#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
5884 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
5885 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
5886 BIT(POWER_DOMAIN_INIT))
5887
5888#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
5889 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
5890 BIT(POWER_DOMAIN_INIT))
5891
a45f4466
ID		 5892static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
5893 .sync_hw = i9xx_always_on_power_well_noop,
5894 .enable = i9xx_always_on_power_well_noop,
5895 .disable = i9xx_always_on_power_well_noop,
5896 .is_enabled = i9xx_always_on_power_well_enabled,
5897};
c6cb582e 5898
1c2256df
ID		 5899static struct i915_power_well i9xx_always_on_power_well[] = {
5900 {
5901 .name = "always-on",
5902 .always_on = 1,
5903 .domains = POWER_DOMAIN_MASK,
c6cb582e 5904 .ops = &i9xx_always_on_power_well_ops,
1c2256df
ID		 5905 },
5906};
5907
c6cb582e
ID		 5908static const struct i915_power_well_ops hsw_power_well_ops = {
5909 .sync_hw = hsw_power_well_sync_hw,
5910 .enable = hsw_power_well_enable,
5911 .disable = hsw_power_well_disable,
5912 .is_enabled = hsw_power_well_enabled,
5913};
5914
c1ca727f 5915static struct i915_power_well hsw_power_wells[] = {
6f3ef5dd
ID		 5916 {
5917 .name = "always-on",
5918 .always_on = 1,
5919 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
c6cb582e 5920 .ops = &i9xx_always_on_power_well_ops,
6f3ef5dd 5921 },
c1ca727f
ID		 5922 {
5923 .name = "display",
efcad917 5924 .domains = HSW_DISPLAY_POWER_DOMAINS,
c6cb582e 5925 .ops = &hsw_power_well_ops,
c1ca727f
ID		 5926 },
5927};
5928
5929static struct i915_power_well bdw_power_wells[] = {
6f3ef5dd
ID		 5930 {
5931 .name = "always-on",
5932 .always_on = 1,
5933 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
c6cb582e 5934 .ops = &i9xx_always_on_power_well_ops,
6f3ef5dd 5935 },
c1ca727f
ID		 5936 {
5937 .name = "display",
efcad917 5938 .domains = BDW_DISPLAY_POWER_DOMAINS,
c6cb582e 5939 .ops = &hsw_power_well_ops,
c1ca727f
ID		 5940 },
5941};
5942
77961eb9
ID		 5943static const struct i915_power_well_ops vlv_display_power_well_ops = {
5944 .sync_hw = vlv_power_well_sync_hw,
5945 .enable = vlv_display_power_well_enable,
5946 .disable = vlv_display_power_well_disable,
5947 .is_enabled = vlv_power_well_enabled,
5948};
5949
5950static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
5951 .sync_hw = vlv_power_well_sync_hw,
5952 .enable = vlv_power_well_enable,
5953 .disable = vlv_power_well_disable,
5954 .is_enabled = vlv_power_well_enabled,
5955};
5956
5957static struct i915_power_well vlv_power_wells[] = {
5958 {
5959 .name = "always-on",
5960 .always_on = 1,
5961 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
5962 .ops = &i9xx_always_on_power_well_ops,
5963 },
5964 {
5965 .name = "display",
5966 .domains = VLV_DISPLAY_POWER_DOMAINS,
5967 .data = PUNIT_POWER_WELL_DISP2D,
5968 .ops = &vlv_display_power_well_ops,
5969 },
5970 {
5971 .name = "dpio-common",
5972 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
5973 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
5974 .ops = &vlv_dpio_power_well_ops,
5975 },
5976 {
5977 .name = "dpio-tx-b-01",
5978 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
5979 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
5980 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
5981 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
5982 .ops = &vlv_dpio_power_well_ops,
5983 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
5984 },
5985 {
5986 .name = "dpio-tx-b-23",
5987 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
5988 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
5989 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
5990 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
5991 .ops = &vlv_dpio_power_well_ops,
5992 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
5993 },
5994 {
5995 .name = "dpio-tx-c-01",
5996 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
5997 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
5998 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
5999 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6000 .ops = &vlv_dpio_power_well_ops,
6001 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
6002 },
6003 {
6004 .name = "dpio-tx-c-23",
6005 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6006 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6007 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6008 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6009 .ops = &vlv_dpio_power_well_ops,
6010 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
6011 },
6012};
6013
c1ca727f
ID		 6014#define set_power_wells(power_domains, __power_wells) ({ \
6015 (power_domains)->power_wells = (__power_wells); \
6016 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
6017})
6018
da7e29bd 6019int intel_power_domains_init(struct drm_i915_private *dev_priv)
a38911a3 6020{
83c00f55 6021 struct i915_power_domains *power_domains = &dev_priv->power_domains;
c1ca727f 6022
83c00f55 6023 mutex_init(&power_domains->lock);
a38911a3 6024
c1ca727f
ID		 6025 /*
6026 * The enabling order will be from lower to higher indexed wells,
6027 * the disabling order is reversed.
6028 */
da7e29bd 6029 if (IS_HASWELL(dev_priv->dev)) {
c1ca727f
ID		 6030 set_power_wells(power_domains, hsw_power_wells);
6031 hsw_pwr = power_domains;
da7e29bd 6032 } else if (IS_BROADWELL(dev_priv->dev)) {
c1ca727f
ID		 6033 set_power_wells(power_domains, bdw_power_wells);
6034 hsw_pwr = power_domains;
77961eb9
ID		 6035 } else if (IS_VALLEYVIEW(dev_priv->dev)) {
6036 set_power_wells(power_domains, vlv_power_wells);
c1ca727f 6037 } else {
1c2256df 6038 set_power_wells(power_domains, i9xx_always_on_power_well);
c1ca727f 6039 }
a38911a3
WX		 6040
6041 return 0;
6042}
6043
da7e29bd 6044void intel_power_domains_remove(struct drm_i915_private *dev_priv)
a38911a3
WX		 6045{
6046 hsw_pwr = NULL;
6047}
6048
da7e29bd 6049static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
9cdb826c 6050{
83c00f55
ID		 6051 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6052 struct i915_power_well *power_well;
c1ca727f 6053 int i;
9cdb826c 6054
83c00f55 6055 mutex_lock(&power_domains->lock);
a45f4466
ID		 6056 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains)
6057 power_well->ops->sync_hw(dev_priv, power_well);
83c00f55 6058 mutex_unlock(&power_domains->lock);
a38911a3
WX		 6059}
6060
da7e29bd 6061void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
d0d3e513 6062{
fa42e23c 6063 /* For now, we need the power well to be always enabled. */
da7e29bd
ID		 6064 intel_display_set_init_power(dev_priv, true);
6065 intel_power_domains_resume(dev_priv);
d0d3e513
ED		 6066}
6067
c67a470b
PZ		 6068void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
6069{
d361ae26 6070 intel_runtime_pm_get(dev_priv);
c67a470b
PZ		 6071}
6072
6073void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
6074{
d361ae26 6075 intel_runtime_pm_put(dev_priv);
c67a470b
PZ		 6076}
6077
8a187455
PZ		 6078void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
6079{
6080 struct drm_device *dev = dev_priv->dev;
6081 struct device *device = &dev->pdev->dev;
6082
6083 if (!HAS_RUNTIME_PM(dev))
6084 return;
6085
6086 pm_runtime_get_sync(device);
6087 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
6088}
6089
c6df39b5
ID		 6090void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
6091{
6092 struct drm_device *dev = dev_priv->dev;
6093 struct device *device = &dev->pdev->dev;
6094
6095 if (!HAS_RUNTIME_PM(dev))
6096 return;
6097
6098 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
6099 pm_runtime_get_noresume(device);
6100}
6101
8a187455
PZ		 6102void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
6103{
6104 struct drm_device *dev = dev_priv->dev;
6105 struct device *device = &dev->pdev->dev;
6106
6107 if (!HAS_RUNTIME_PM(dev))
6108 return;
6109
6110 pm_runtime_mark_last_busy(device);
6111 pm_runtime_put_autosuspend(device);
6112}
6113
6114void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
6115{
6116 struct drm_device *dev = dev_priv->dev;
6117 struct device *device = &dev->pdev->dev;
6118
8a187455
PZ		 6119 if (!HAS_RUNTIME_PM(dev))
6120 return;
6121
6122 pm_runtime_set_active(device);
6123
aeab0b5a
ID		 6124 /*
6125 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6126 * requirement.
6127 */
6128 if (!intel_enable_rc6(dev)) {
6129 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6130 return;
6131 }
6132
8a187455
PZ		 6133 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
6134 pm_runtime_mark_last_busy(device);
6135 pm_runtime_use_autosuspend(device);
ba0239e0
PZ		 6136
6137 pm_runtime_put_autosuspend(device);
8a187455
PZ		 6138}
6139
6140void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
6141{
6142 struct drm_device *dev = dev_priv->dev;
6143 struct device *device = &dev->pdev->dev;
6144
6145 if (!HAS_RUNTIME_PM(dev))
6146 return;
6147
aeab0b5a
ID		 6148 if (!intel_enable_rc6(dev))
6149 return;
6150
8a187455
PZ		 6151 /* Make sure we're not suspended first. */
6152 pm_runtime_get_sync(device);
6153 pm_runtime_disable(device);
6154}
6155
1fa61106
ED		 6156/* Set up chip specific power management-related functions */
6157void intel_init_pm(struct drm_device *dev)
6158{
6159 struct drm_i915_private *dev_priv = dev->dev_private;
6160
3a77c4c4 6161 if (HAS_FBC(dev)) {
40045465 6162 if (INTEL_INFO(dev)->gen >= 7) {
1fa61106 6163 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
40045465
VS		 6164 dev_priv->display.enable_fbc = gen7_enable_fbc;
6165 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6166 } else if (INTEL_INFO(dev)->gen >= 5) {
6167 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6168 dev_priv->display.enable_fbc = ironlake_enable_fbc;
1fa61106
ED		 6169 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6170 } else if (IS_GM45(dev)) {
6171 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6172 dev_priv->display.enable_fbc = g4x_enable_fbc;
6173 dev_priv->display.disable_fbc = g4x_disable_fbc;
40045465 6174 } else {
1fa61106
ED		 6175 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6176 dev_priv->display.enable_fbc = i8xx_enable_fbc;
6177 dev_priv->display.disable_fbc = i8xx_disable_fbc;
993495ae
VS		 6178
6179 /* This value was pulled out of someone's hat */
6180 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
1fa61106 6181 }
1fa61106
ED		 6182 }
6183
c921aba8
DV		 6184 /* For cxsr */
6185 if (IS_PINEVIEW(dev))
6186 i915_pineview_get_mem_freq(dev);
6187 else if (IS_GEN5(dev))
6188 i915_ironlake_get_mem_freq(dev);
6189
1fa61106
ED		 6190 /* For FIFO watermark updates */
6191 if (HAS_PCH_SPLIT(dev)) {
fa50ad61 6192 ilk_setup_wm_latency(dev);
53615a5e 6193
bd602544
VS		 6194 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6195 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6196 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6197 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6198 dev_priv->display.update_wm = ilk_update_wm;
6199 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6200 } else {
6201 DRM_DEBUG_KMS("Failed to read display plane latency. "
6202 "Disable CxSR\n");
6203 }
6204
6205 if (IS_GEN5(dev))
1fa61106 6206 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 6207 else if (IS_GEN6(dev))
1fa61106 6208 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 6209 else if (IS_IVYBRIDGE(dev))
1fa61106 6210 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 6211 else if (IS_HASWELL(dev))
cad2a2d7 6212 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 6213 else if (INTEL_INFO(dev)->gen == 8)
1020a5c2 6214 dev_priv->display.init_clock_gating = gen8_init_clock_gating;
1fa61106
ED		 6215 } else if (IS_VALLEYVIEW(dev)) {
6216 dev_priv->display.update_wm = valleyview_update_wm;
6217 dev_priv->display.init_clock_gating =
6218 valleyview_init_clock_gating;
1fa61106
ED		 6219 } else if (IS_PINEVIEW(dev)) {
6220 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6221 dev_priv->is_ddr3,
6222 dev_priv->fsb_freq,
6223 dev_priv->mem_freq)) {
6224 DRM_INFO("failed to find known CxSR latency "
6225 "(found ddr%s fsb freq %d, mem freq %d), "
6226 "disabling CxSR\n",
6227 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6228 dev_priv->fsb_freq, dev_priv->mem_freq);
6229 /* Disable CxSR and never update its watermark again */
6230 pineview_disable_cxsr(dev);
6231 dev_priv->display.update_wm = NULL;
6232 } else
6233 dev_priv->display.update_wm = pineview_update_wm;
6234 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6235 } else if (IS_G4X(dev)) {
6236 dev_priv->display.update_wm = g4x_update_wm;
6237 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6238 } else if (IS_GEN4(dev)) {
6239 dev_priv->display.update_wm = i965_update_wm;
6240 if (IS_CRESTLINE(dev))
6241 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6242 else if (IS_BROADWATER(dev))
6243 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6244 } else if (IS_GEN3(dev)) {
6245 dev_priv->display.update_wm = i9xx_update_wm;
6246 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6247 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 6248 } else if (IS_GEN2(dev)) {
6249 if (INTEL_INFO(dev)->num_pipes == 1) {
6250 dev_priv->display.update_wm = i845_update_wm;
1fa61106 6251 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 6252 } else {
6253 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 6254 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 6255 }
6256
6257 if (IS_I85X(dev) || IS_I865G(dev))
6258 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6259 else
6260 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6261 } else {
6262 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 6263 }
6264}
6265
42c0526c
BW		 6266int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
6267{
4fc688ce 6268 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6269
6270 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6271 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6272 return -EAGAIN;
6273 }
6274
6275 I915_WRITE(GEN6_PCODE_DATA, *val);
6276 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6277
6278 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6279 500)) {
6280 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6281 return -ETIMEDOUT;
6282 }
6283
6284 *val = I915_READ(GEN6_PCODE_DATA);
6285 I915_WRITE(GEN6_PCODE_DATA, 0);
6286
6287 return 0;
6288}
6289
6290int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
6291{
4fc688ce 6292 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6293
6294 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6295 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6296 return -EAGAIN;
6297 }
6298
6299 I915_WRITE(GEN6_PCODE_DATA, val);
6300 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6301
6302 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6303 500)) {
6304 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6305 return -ETIMEDOUT;
6306 }
6307
6308 I915_WRITE(GEN6_PCODE_DATA, 0);
6309
6310 return 0;
6311}
a0e4e199 6312
2ec3815f 6313int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
855ba3be 6314{
07ab118b 6315 int div;
855ba3be 6316
07ab118b 6317 /* 4 x czclk */
2ec3815f 6318 switch (dev_priv->mem_freq) {
855ba3be 6319 case 800:
07ab118b 6320 div = 10;
855ba3be
JB		 6321 break;
6322 case 1066:
07ab118b 6323 div = 12;
855ba3be
JB		 6324 break;
6325 case 1333:
07ab118b 6326 div = 16;
855ba3be
JB		 6327 break;
6328 default:
6329 return -1;
6330 }
6331
2ec3815f 6332 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
855ba3be
JB		 6333}
6334
2ec3815f 6335int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 6336{
07ab118b 6337 int mul;
855ba3be 6338
07ab118b 6339 /* 4 x czclk */
2ec3815f 6340 switch (dev_priv->mem_freq) {
855ba3be 6341 case 800:
07ab118b 6342 mul = 10;
855ba3be
JB		 6343 break;
6344 case 1066:
07ab118b 6345 mul = 12;
855ba3be
JB		 6346 break;
6347 case 1333:
07ab118b 6348 mul = 16;
855ba3be
JB		 6349 break;
6350 default:
6351 return -1;
6352 }
6353
2ec3815f 6354 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
855ba3be
JB		 6355}
6356
f742a552 6357void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 6358{
6359 struct drm_i915_private *dev_priv = dev->dev_private;
6360
f742a552
DV		 6361 mutex_init(&dev_priv->rps.hw_lock);
6362
907b28c5
CW		 6363 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6364 intel_gen6_powersave_work);
5d584b2e 6365
33688d95 6366 dev_priv->pm.suspended = false;
5d584b2e 6367 dev_priv->pm.irqs_disabled = false;
907b28c5 6368}
Linux 6.x block layer and io_uring tree(s)