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1d8e1c75 CW |
1 | /* |
2 | * Copyright © 2006-2010 Intel Corporation | |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Dave Airlie <airlied@linux.ie> | |
27 | * Jesse Barnes <jesse.barnes@intel.com> | |
28 | * Chris Wilson <chris@chris-wilson.co.uk> | |
29 | */ | |
30 | ||
a70491cc JP |
31 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
32 | ||
7bd90909 | 33 | #include <linux/moduleparam.h> |
1d8e1c75 CW |
34 | #include "intel_drv.h" |
35 | ||
36 | void | |
4c6df4b4 | 37 | intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, |
1d8e1c75 CW |
38 | struct drm_display_mode *adjusted_mode) |
39 | { | |
4c6df4b4 | 40 | drm_mode_copy(adjusted_mode, fixed_mode); |
a52690e4 ID |
41 | |
42 | drm_mode_set_crtcinfo(adjusted_mode, 0); | |
1d8e1c75 CW |
43 | } |
44 | ||
525997e0 JN |
45 | /** |
46 | * intel_find_panel_downclock - find the reduced downclock for LVDS in EDID | |
47 | * @dev: drm device | |
48 | * @fixed_mode : panel native mode | |
49 | * @connector: LVDS/eDP connector | |
50 | * | |
51 | * Return downclock_avail | |
52 | * Find the reduced downclock for LVDS/eDP in EDID. | |
53 | */ | |
54 | struct drm_display_mode * | |
55 | intel_find_panel_downclock(struct drm_device *dev, | |
56 | struct drm_display_mode *fixed_mode, | |
57 | struct drm_connector *connector) | |
58 | { | |
59 | struct drm_display_mode *scan, *tmp_mode; | |
60 | int temp_downclock; | |
61 | ||
62 | temp_downclock = fixed_mode->clock; | |
63 | tmp_mode = NULL; | |
64 | ||
65 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
66 | /* | |
67 | * If one mode has the same resolution with the fixed_panel | |
68 | * mode while they have the different refresh rate, it means | |
69 | * that the reduced downclock is found. In such | |
70 | * case we can set the different FPx0/1 to dynamically select | |
71 | * between low and high frequency. | |
72 | */ | |
73 | if (scan->hdisplay == fixed_mode->hdisplay && | |
74 | scan->hsync_start == fixed_mode->hsync_start && | |
75 | scan->hsync_end == fixed_mode->hsync_end && | |
76 | scan->htotal == fixed_mode->htotal && | |
77 | scan->vdisplay == fixed_mode->vdisplay && | |
78 | scan->vsync_start == fixed_mode->vsync_start && | |
79 | scan->vsync_end == fixed_mode->vsync_end && | |
80 | scan->vtotal == fixed_mode->vtotal) { | |
81 | if (scan->clock < temp_downclock) { | |
82 | /* | |
83 | * The downclock is already found. But we | |
84 | * expect to find the lower downclock. | |
85 | */ | |
86 | temp_downclock = scan->clock; | |
87 | tmp_mode = scan; | |
88 | } | |
89 | } | |
90 | } | |
91 | ||
92 | if (temp_downclock < fixed_mode->clock) | |
93 | return drm_mode_duplicate(dev, tmp_mode); | |
94 | else | |
95 | return NULL; | |
96 | } | |
97 | ||
1d8e1c75 CW |
98 | /* adjusted_mode has been preset to be the panel's fixed mode */ |
99 | void | |
b074cec8 JB |
100 | intel_pch_panel_fitting(struct intel_crtc *intel_crtc, |
101 | struct intel_crtc_config *pipe_config, | |
102 | int fitting_mode) | |
1d8e1c75 | 103 | { |
37327abd | 104 | struct drm_display_mode *adjusted_mode; |
1d8e1c75 CW |
105 | int x, y, width, height; |
106 | ||
b074cec8 JB |
107 | adjusted_mode = &pipe_config->adjusted_mode; |
108 | ||
1d8e1c75 CW |
109 | x = y = width = height = 0; |
110 | ||
111 | /* Native modes don't need fitting */ | |
37327abd VS |
112 | if (adjusted_mode->hdisplay == pipe_config->pipe_src_w && |
113 | adjusted_mode->vdisplay == pipe_config->pipe_src_h) | |
1d8e1c75 CW |
114 | goto done; |
115 | ||
116 | switch (fitting_mode) { | |
117 | case DRM_MODE_SCALE_CENTER: | |
37327abd VS |
118 | width = pipe_config->pipe_src_w; |
119 | height = pipe_config->pipe_src_h; | |
1d8e1c75 CW |
120 | x = (adjusted_mode->hdisplay - width + 1)/2; |
121 | y = (adjusted_mode->vdisplay - height + 1)/2; | |
122 | break; | |
123 | ||
124 | case DRM_MODE_SCALE_ASPECT: | |
125 | /* Scale but preserve the aspect ratio */ | |
126 | { | |
9084e7d2 DV |
127 | u32 scaled_width = adjusted_mode->hdisplay |
128 | * pipe_config->pipe_src_h; | |
129 | u32 scaled_height = pipe_config->pipe_src_w | |
130 | * adjusted_mode->vdisplay; | |
1d8e1c75 | 131 | if (scaled_width > scaled_height) { /* pillar */ |
37327abd | 132 | width = scaled_height / pipe_config->pipe_src_h; |
302983e9 | 133 | if (width & 1) |
0206e353 | 134 | width++; |
1d8e1c75 CW |
135 | x = (adjusted_mode->hdisplay - width + 1) / 2; |
136 | y = 0; | |
137 | height = adjusted_mode->vdisplay; | |
138 | } else if (scaled_width < scaled_height) { /* letter */ | |
37327abd | 139 | height = scaled_width / pipe_config->pipe_src_w; |
302983e9 AJ |
140 | if (height & 1) |
141 | height++; | |
1d8e1c75 CW |
142 | y = (adjusted_mode->vdisplay - height + 1) / 2; |
143 | x = 0; | |
144 | width = adjusted_mode->hdisplay; | |
145 | } else { | |
146 | x = y = 0; | |
147 | width = adjusted_mode->hdisplay; | |
148 | height = adjusted_mode->vdisplay; | |
149 | } | |
150 | } | |
151 | break; | |
152 | ||
1d8e1c75 CW |
153 | case DRM_MODE_SCALE_FULLSCREEN: |
154 | x = y = 0; | |
155 | width = adjusted_mode->hdisplay; | |
156 | height = adjusted_mode->vdisplay; | |
157 | break; | |
ab3e67f4 JB |
158 | |
159 | default: | |
160 | WARN(1, "bad panel fit mode: %d\n", fitting_mode); | |
161 | return; | |
1d8e1c75 CW |
162 | } |
163 | ||
164 | done: | |
b074cec8 JB |
165 | pipe_config->pch_pfit.pos = (x << 16) | y; |
166 | pipe_config->pch_pfit.size = (width << 16) | height; | |
fd4daa9c | 167 | pipe_config->pch_pfit.enabled = pipe_config->pch_pfit.size != 0; |
1d8e1c75 | 168 | } |
a9573556 | 169 | |
2dd24552 JB |
170 | static void |
171 | centre_horizontally(struct drm_display_mode *mode, | |
172 | int width) | |
173 | { | |
174 | u32 border, sync_pos, blank_width, sync_width; | |
175 | ||
176 | /* keep the hsync and hblank widths constant */ | |
177 | sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start; | |
178 | blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start; | |
179 | sync_pos = (blank_width - sync_width + 1) / 2; | |
180 | ||
181 | border = (mode->hdisplay - width + 1) / 2; | |
182 | border += border & 1; /* make the border even */ | |
183 | ||
184 | mode->crtc_hdisplay = width; | |
185 | mode->crtc_hblank_start = width + border; | |
186 | mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width; | |
187 | ||
188 | mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos; | |
189 | mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width; | |
190 | } | |
191 | ||
192 | static void | |
193 | centre_vertically(struct drm_display_mode *mode, | |
194 | int height) | |
195 | { | |
196 | u32 border, sync_pos, blank_width, sync_width; | |
197 | ||
198 | /* keep the vsync and vblank widths constant */ | |
199 | sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start; | |
200 | blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start; | |
201 | sync_pos = (blank_width - sync_width + 1) / 2; | |
202 | ||
203 | border = (mode->vdisplay - height + 1) / 2; | |
204 | ||
205 | mode->crtc_vdisplay = height; | |
206 | mode->crtc_vblank_start = height + border; | |
207 | mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width; | |
208 | ||
209 | mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos; | |
210 | mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width; | |
211 | } | |
212 | ||
213 | static inline u32 panel_fitter_scaling(u32 source, u32 target) | |
214 | { | |
215 | /* | |
216 | * Floating point operation is not supported. So the FACTOR | |
217 | * is defined, which can avoid the floating point computation | |
218 | * when calculating the panel ratio. | |
219 | */ | |
220 | #define ACCURACY 12 | |
221 | #define FACTOR (1 << ACCURACY) | |
222 | u32 ratio = source * FACTOR / target; | |
223 | return (FACTOR * ratio + FACTOR/2) / FACTOR; | |
224 | } | |
225 | ||
9084e7d2 DV |
226 | static void i965_scale_aspect(struct intel_crtc_config *pipe_config, |
227 | u32 *pfit_control) | |
228 | { | |
229 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; | |
230 | u32 scaled_width = adjusted_mode->hdisplay * | |
231 | pipe_config->pipe_src_h; | |
232 | u32 scaled_height = pipe_config->pipe_src_w * | |
233 | adjusted_mode->vdisplay; | |
234 | ||
235 | /* 965+ is easy, it does everything in hw */ | |
236 | if (scaled_width > scaled_height) | |
237 | *pfit_control |= PFIT_ENABLE | | |
238 | PFIT_SCALING_PILLAR; | |
239 | else if (scaled_width < scaled_height) | |
240 | *pfit_control |= PFIT_ENABLE | | |
241 | PFIT_SCALING_LETTER; | |
242 | else if (adjusted_mode->hdisplay != pipe_config->pipe_src_w) | |
243 | *pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO; | |
244 | } | |
245 | ||
246 | static void i9xx_scale_aspect(struct intel_crtc_config *pipe_config, | |
247 | u32 *pfit_control, u32 *pfit_pgm_ratios, | |
248 | u32 *border) | |
249 | { | |
250 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; | |
251 | u32 scaled_width = adjusted_mode->hdisplay * | |
252 | pipe_config->pipe_src_h; | |
253 | u32 scaled_height = pipe_config->pipe_src_w * | |
254 | adjusted_mode->vdisplay; | |
255 | u32 bits; | |
256 | ||
257 | /* | |
258 | * For earlier chips we have to calculate the scaling | |
259 | * ratio by hand and program it into the | |
260 | * PFIT_PGM_RATIO register | |
261 | */ | |
262 | if (scaled_width > scaled_height) { /* pillar */ | |
263 | centre_horizontally(adjusted_mode, | |
264 | scaled_height / | |
265 | pipe_config->pipe_src_h); | |
266 | ||
267 | *border = LVDS_BORDER_ENABLE; | |
268 | if (pipe_config->pipe_src_h != adjusted_mode->vdisplay) { | |
269 | bits = panel_fitter_scaling(pipe_config->pipe_src_h, | |
270 | adjusted_mode->vdisplay); | |
271 | ||
272 | *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | |
273 | bits << PFIT_VERT_SCALE_SHIFT); | |
274 | *pfit_control |= (PFIT_ENABLE | | |
275 | VERT_INTERP_BILINEAR | | |
276 | HORIZ_INTERP_BILINEAR); | |
277 | } | |
278 | } else if (scaled_width < scaled_height) { /* letter */ | |
279 | centre_vertically(adjusted_mode, | |
280 | scaled_width / | |
281 | pipe_config->pipe_src_w); | |
282 | ||
283 | *border = LVDS_BORDER_ENABLE; | |
284 | if (pipe_config->pipe_src_w != adjusted_mode->hdisplay) { | |
285 | bits = panel_fitter_scaling(pipe_config->pipe_src_w, | |
286 | adjusted_mode->hdisplay); | |
287 | ||
288 | *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | |
289 | bits << PFIT_VERT_SCALE_SHIFT); | |
290 | *pfit_control |= (PFIT_ENABLE | | |
291 | VERT_INTERP_BILINEAR | | |
292 | HORIZ_INTERP_BILINEAR); | |
293 | } | |
294 | } else { | |
295 | /* Aspects match, Let hw scale both directions */ | |
296 | *pfit_control |= (PFIT_ENABLE | | |
297 | VERT_AUTO_SCALE | HORIZ_AUTO_SCALE | | |
298 | VERT_INTERP_BILINEAR | | |
299 | HORIZ_INTERP_BILINEAR); | |
300 | } | |
301 | } | |
302 | ||
2dd24552 JB |
303 | void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc, |
304 | struct intel_crtc_config *pipe_config, | |
305 | int fitting_mode) | |
306 | { | |
307 | struct drm_device *dev = intel_crtc->base.dev; | |
2dd24552 | 308 | u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0; |
37327abd | 309 | struct drm_display_mode *adjusted_mode; |
2dd24552 | 310 | |
2dd24552 JB |
311 | adjusted_mode = &pipe_config->adjusted_mode; |
312 | ||
313 | /* Native modes don't need fitting */ | |
37327abd VS |
314 | if (adjusted_mode->hdisplay == pipe_config->pipe_src_w && |
315 | adjusted_mode->vdisplay == pipe_config->pipe_src_h) | |
2dd24552 JB |
316 | goto out; |
317 | ||
318 | switch (fitting_mode) { | |
319 | case DRM_MODE_SCALE_CENTER: | |
320 | /* | |
321 | * For centered modes, we have to calculate border widths & | |
322 | * heights and modify the values programmed into the CRTC. | |
323 | */ | |
37327abd VS |
324 | centre_horizontally(adjusted_mode, pipe_config->pipe_src_w); |
325 | centre_vertically(adjusted_mode, pipe_config->pipe_src_h); | |
2dd24552 JB |
326 | border = LVDS_BORDER_ENABLE; |
327 | break; | |
328 | case DRM_MODE_SCALE_ASPECT: | |
329 | /* Scale but preserve the aspect ratio */ | |
9084e7d2 DV |
330 | if (INTEL_INFO(dev)->gen >= 4) |
331 | i965_scale_aspect(pipe_config, &pfit_control); | |
332 | else | |
333 | i9xx_scale_aspect(pipe_config, &pfit_control, | |
334 | &pfit_pgm_ratios, &border); | |
2dd24552 | 335 | break; |
2dd24552 JB |
336 | case DRM_MODE_SCALE_FULLSCREEN: |
337 | /* | |
338 | * Full scaling, even if it changes the aspect ratio. | |
339 | * Fortunately this is all done for us in hw. | |
340 | */ | |
37327abd VS |
341 | if (pipe_config->pipe_src_h != adjusted_mode->vdisplay || |
342 | pipe_config->pipe_src_w != adjusted_mode->hdisplay) { | |
2dd24552 JB |
343 | pfit_control |= PFIT_ENABLE; |
344 | if (INTEL_INFO(dev)->gen >= 4) | |
345 | pfit_control |= PFIT_SCALING_AUTO; | |
346 | else | |
347 | pfit_control |= (VERT_AUTO_SCALE | | |
348 | VERT_INTERP_BILINEAR | | |
349 | HORIZ_AUTO_SCALE | | |
350 | HORIZ_INTERP_BILINEAR); | |
351 | } | |
352 | break; | |
ab3e67f4 JB |
353 | default: |
354 | WARN(1, "bad panel fit mode: %d\n", fitting_mode); | |
355 | return; | |
2dd24552 JB |
356 | } |
357 | ||
358 | /* 965+ wants fuzzy fitting */ | |
359 | /* FIXME: handle multiple panels by failing gracefully */ | |
360 | if (INTEL_INFO(dev)->gen >= 4) | |
361 | pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) | | |
362 | PFIT_FILTER_FUZZY); | |
363 | ||
773875bf DV |
364 | /* Make sure pre-965 set dither correctly for 18bpp panels. */ |
365 | if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18) | |
366 | pfit_control |= PANEL_8TO6_DITHER_ENABLE; | |
367 | ||
2dd24552 JB |
368 | out: |
369 | if ((pfit_control & PFIT_ENABLE) == 0) { | |
370 | pfit_control = 0; | |
371 | pfit_pgm_ratios = 0; | |
372 | } | |
373 | ||
2deefda5 DV |
374 | pipe_config->gmch_pfit.control = pfit_control; |
375 | pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios; | |
68fc8742 | 376 | pipe_config->gmch_pfit.lvds_border_bits = border; |
2dd24552 JB |
377 | } |
378 | ||
525997e0 JN |
379 | enum drm_connector_status |
380 | intel_panel_detect(struct drm_device *dev) | |
381 | { | |
382 | struct drm_i915_private *dev_priv = dev->dev_private; | |
383 | ||
384 | /* Assume that the BIOS does not lie through the OpRegion... */ | |
385 | if (!i915.panel_ignore_lid && dev_priv->opregion.lid_state) { | |
386 | return ioread32(dev_priv->opregion.lid_state) & 0x1 ? | |
387 | connector_status_connected : | |
388 | connector_status_disconnected; | |
389 | } | |
390 | ||
391 | switch (i915.panel_ignore_lid) { | |
392 | case -2: | |
393 | return connector_status_connected; | |
394 | case -1: | |
395 | return connector_status_disconnected; | |
396 | default: | |
397 | return connector_status_unknown; | |
398 | } | |
399 | } | |
400 | ||
7bd688cd JN |
401 | static u32 intel_panel_compute_brightness(struct intel_connector *connector, |
402 | u32 val) | |
7bd90909 | 403 | { |
7bd688cd | 404 | struct drm_device *dev = connector->base.dev; |
4dca20ef | 405 | struct drm_i915_private *dev_priv = dev->dev_private; |
f91c15e0 JN |
406 | struct intel_panel *panel = &connector->panel; |
407 | ||
408 | WARN_ON(panel->backlight.max == 0); | |
4dca20ef | 409 | |
d330a953 | 410 | if (i915.invert_brightness < 0) |
4dca20ef CE |
411 | return val; |
412 | ||
d330a953 | 413 | if (i915.invert_brightness > 0 || |
d6540632 | 414 | dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) { |
f91c15e0 | 415 | return panel->backlight.max - val; |
d6540632 | 416 | } |
7bd90909 CE |
417 | |
418 | return val; | |
419 | } | |
420 | ||
96ab4c70 | 421 | static u32 bdw_get_backlight(struct intel_connector *connector) |
0b0b053a | 422 | { |
96ab4c70 | 423 | struct drm_device *dev = connector->base.dev; |
bfd7590d | 424 | struct drm_i915_private *dev_priv = dev->dev_private; |
0b0b053a | 425 | |
96ab4c70 DV |
426 | return I915_READ(BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK; |
427 | } | |
07bf139b | 428 | |
7bd688cd | 429 | static u32 pch_get_backlight(struct intel_connector *connector) |
a9573556 | 430 | { |
7bd688cd | 431 | struct drm_device *dev = connector->base.dev; |
a9573556 | 432 | struct drm_i915_private *dev_priv = dev->dev_private; |
8ba2d185 | 433 | |
7bd688cd JN |
434 | return I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; |
435 | } | |
a9573556 | 436 | |
7bd688cd JN |
437 | static u32 i9xx_get_backlight(struct intel_connector *connector) |
438 | { | |
439 | struct drm_device *dev = connector->base.dev; | |
440 | struct drm_i915_private *dev_priv = dev->dev_private; | |
636baebf | 441 | struct intel_panel *panel = &connector->panel; |
7bd688cd | 442 | u32 val; |
07bf139b | 443 | |
7bd688cd JN |
444 | val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; |
445 | if (INTEL_INFO(dev)->gen < 4) | |
446 | val >>= 1; | |
ba3820ad | 447 | |
636baebf | 448 | if (panel->backlight.combination_mode) { |
7bd688cd | 449 | u8 lbpc; |
ba3820ad | 450 | |
7bd688cd JN |
451 | pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc); |
452 | val *= lbpc; | |
a9573556 CW |
453 | } |
454 | ||
7bd688cd JN |
455 | return val; |
456 | } | |
457 | ||
458 | static u32 _vlv_get_backlight(struct drm_device *dev, enum pipe pipe) | |
459 | { | |
460 | struct drm_i915_private *dev_priv = dev->dev_private; | |
461 | ||
462 | return I915_READ(VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK; | |
463 | } | |
464 | ||
465 | static u32 vlv_get_backlight(struct intel_connector *connector) | |
466 | { | |
467 | struct drm_device *dev = connector->base.dev; | |
468 | enum pipe pipe = intel_get_pipe_from_connector(connector); | |
469 | ||
470 | return _vlv_get_backlight(dev, pipe); | |
471 | } | |
472 | ||
473 | static u32 intel_panel_get_backlight(struct intel_connector *connector) | |
474 | { | |
475 | struct drm_device *dev = connector->base.dev; | |
476 | struct drm_i915_private *dev_priv = dev->dev_private; | |
477 | u32 val; | |
478 | unsigned long flags; | |
479 | ||
480 | spin_lock_irqsave(&dev_priv->backlight_lock, flags); | |
481 | ||
482 | val = dev_priv->display.get_backlight(connector); | |
483 | val = intel_panel_compute_brightness(connector, val); | |
8ba2d185 | 484 | |
58c68779 | 485 | spin_unlock_irqrestore(&dev_priv->backlight_lock, flags); |
8ba2d185 | 486 | |
a9573556 CW |
487 | DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val); |
488 | return val; | |
489 | } | |
490 | ||
96ab4c70 | 491 | static void bdw_set_backlight(struct intel_connector *connector, u32 level) |
f8e10062 | 492 | { |
96ab4c70 | 493 | struct drm_device *dev = connector->base.dev; |
f8e10062 BW |
494 | struct drm_i915_private *dev_priv = dev->dev_private; |
495 | u32 val = I915_READ(BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK; | |
496 | I915_WRITE(BLC_PWM_PCH_CTL2, val | level); | |
497 | } | |
498 | ||
7bd688cd | 499 | static void pch_set_backlight(struct intel_connector *connector, u32 level) |
a9573556 | 500 | { |
7bd688cd | 501 | struct drm_device *dev = connector->base.dev; |
a9573556 | 502 | struct drm_i915_private *dev_priv = dev->dev_private; |
7bd688cd JN |
503 | u32 tmp; |
504 | ||
505 | tmp = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; | |
506 | I915_WRITE(BLC_PWM_CPU_CTL, tmp | level); | |
a9573556 CW |
507 | } |
508 | ||
7bd688cd | 509 | static void i9xx_set_backlight(struct intel_connector *connector, u32 level) |
a9573556 | 510 | { |
7bd688cd | 511 | struct drm_device *dev = connector->base.dev; |
a9573556 | 512 | struct drm_i915_private *dev_priv = dev->dev_private; |
f91c15e0 | 513 | struct intel_panel *panel = &connector->panel; |
b329b328 | 514 | u32 tmp, mask; |
ba3820ad | 515 | |
f91c15e0 JN |
516 | WARN_ON(panel->backlight.max == 0); |
517 | ||
636baebf | 518 | if (panel->backlight.combination_mode) { |
ba3820ad TI |
519 | u8 lbpc; |
520 | ||
f91c15e0 | 521 | lbpc = level * 0xfe / panel->backlight.max + 1; |
ba3820ad TI |
522 | level /= lbpc; |
523 | pci_write_config_byte(dev->pdev, PCI_LBPC, lbpc); | |
524 | } | |
525 | ||
b329b328 JN |
526 | if (IS_GEN4(dev)) { |
527 | mask = BACKLIGHT_DUTY_CYCLE_MASK; | |
528 | } else { | |
a9573556 | 529 | level <<= 1; |
b329b328 JN |
530 | mask = BACKLIGHT_DUTY_CYCLE_MASK_PNV; |
531 | } | |
7bd688cd | 532 | |
b329b328 | 533 | tmp = I915_READ(BLC_PWM_CTL) & ~mask; |
7bd688cd JN |
534 | I915_WRITE(BLC_PWM_CTL, tmp | level); |
535 | } | |
536 | ||
537 | static void vlv_set_backlight(struct intel_connector *connector, u32 level) | |
538 | { | |
539 | struct drm_device *dev = connector->base.dev; | |
540 | struct drm_i915_private *dev_priv = dev->dev_private; | |
541 | enum pipe pipe = intel_get_pipe_from_connector(connector); | |
542 | u32 tmp; | |
543 | ||
544 | tmp = I915_READ(VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK; | |
545 | I915_WRITE(VLV_BLC_PWM_CTL(pipe), tmp | level); | |
546 | } | |
547 | ||
548 | static void | |
549 | intel_panel_actually_set_backlight(struct intel_connector *connector, u32 level) | |
550 | { | |
551 | struct drm_device *dev = connector->base.dev; | |
552 | struct drm_i915_private *dev_priv = dev->dev_private; | |
553 | ||
554 | DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level); | |
555 | ||
556 | level = intel_panel_compute_brightness(connector, level); | |
557 | dev_priv->display.set_backlight(connector, level); | |
a9573556 | 558 | } |
47356eb6 | 559 | |
d6540632 | 560 | /* set backlight brightness to level in range [0..max] */ |
752aa88a JB |
561 | void intel_panel_set_backlight(struct intel_connector *connector, u32 level, |
562 | u32 max) | |
47356eb6 | 563 | { |
752aa88a | 564 | struct drm_device *dev = connector->base.dev; |
47356eb6 | 565 | struct drm_i915_private *dev_priv = dev->dev_private; |
58c68779 | 566 | struct intel_panel *panel = &connector->panel; |
752aa88a | 567 | enum pipe pipe = intel_get_pipe_from_connector(connector); |
d6540632 | 568 | u32 freq; |
8ba2d185 | 569 | unsigned long flags; |
721e82c0 | 570 | u64 n; |
8ba2d185 | 571 | |
dc5a4363 | 572 | if (!panel->backlight.present || pipe == INVALID_PIPE) |
752aa88a JB |
573 | return; |
574 | ||
58c68779 | 575 | spin_lock_irqsave(&dev_priv->backlight_lock, flags); |
d6540632 | 576 | |
f91c15e0 | 577 | WARN_ON(panel->backlight.max == 0); |
d6540632 | 578 | |
f91c15e0 JN |
579 | /* scale to hardware max, but be careful to not overflow */ |
580 | freq = panel->backlight.max; | |
721e82c0 AL |
581 | n = (u64)level * freq; |
582 | do_div(n, max); | |
583 | level = n; | |
47356eb6 | 584 | |
58c68779 JN |
585 | panel->backlight.level = level; |
586 | if (panel->backlight.device) | |
587 | panel->backlight.device->props.brightness = level; | |
b6b3ba5b | 588 | |
58c68779 | 589 | if (panel->backlight.enabled) |
7bd688cd | 590 | intel_panel_actually_set_backlight(connector, level); |
f91c15e0 | 591 | |
58c68779 | 592 | spin_unlock_irqrestore(&dev_priv->backlight_lock, flags); |
f52c619a TI |
593 | } |
594 | ||
7bd688cd JN |
595 | static void pch_disable_backlight(struct intel_connector *connector) |
596 | { | |
597 | struct drm_device *dev = connector->base.dev; | |
598 | struct drm_i915_private *dev_priv = dev->dev_private; | |
599 | u32 tmp; | |
600 | ||
3bd712e5 JN |
601 | intel_panel_actually_set_backlight(connector, 0); |
602 | ||
7bd688cd JN |
603 | tmp = I915_READ(BLC_PWM_CPU_CTL2); |
604 | I915_WRITE(BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE); | |
605 | ||
606 | tmp = I915_READ(BLC_PWM_PCH_CTL1); | |
607 | I915_WRITE(BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE); | |
608 | } | |
609 | ||
3bd712e5 JN |
610 | static void i9xx_disable_backlight(struct intel_connector *connector) |
611 | { | |
612 | intel_panel_actually_set_backlight(connector, 0); | |
613 | } | |
614 | ||
7bd688cd JN |
615 | static void i965_disable_backlight(struct intel_connector *connector) |
616 | { | |
617 | struct drm_device *dev = connector->base.dev; | |
618 | struct drm_i915_private *dev_priv = dev->dev_private; | |
619 | u32 tmp; | |
620 | ||
3bd712e5 JN |
621 | intel_panel_actually_set_backlight(connector, 0); |
622 | ||
7bd688cd JN |
623 | tmp = I915_READ(BLC_PWM_CTL2); |
624 | I915_WRITE(BLC_PWM_CTL2, tmp & ~BLM_PWM_ENABLE); | |
625 | } | |
626 | ||
627 | static void vlv_disable_backlight(struct intel_connector *connector) | |
628 | { | |
629 | struct drm_device *dev = connector->base.dev; | |
630 | struct drm_i915_private *dev_priv = dev->dev_private; | |
631 | enum pipe pipe = intel_get_pipe_from_connector(connector); | |
632 | u32 tmp; | |
633 | ||
3bd712e5 JN |
634 | intel_panel_actually_set_backlight(connector, 0); |
635 | ||
7bd688cd JN |
636 | tmp = I915_READ(VLV_BLC_PWM_CTL2(pipe)); |
637 | I915_WRITE(VLV_BLC_PWM_CTL2(pipe), tmp & ~BLM_PWM_ENABLE); | |
638 | } | |
639 | ||
752aa88a | 640 | void intel_panel_disable_backlight(struct intel_connector *connector) |
f52c619a | 641 | { |
752aa88a | 642 | struct drm_device *dev = connector->base.dev; |
f52c619a | 643 | struct drm_i915_private *dev_priv = dev->dev_private; |
58c68779 | 644 | struct intel_panel *panel = &connector->panel; |
752aa88a | 645 | enum pipe pipe = intel_get_pipe_from_connector(connector); |
8ba2d185 JN |
646 | unsigned long flags; |
647 | ||
dc5a4363 | 648 | if (!panel->backlight.present || pipe == INVALID_PIPE) |
752aa88a JB |
649 | return; |
650 | ||
3f577573 JN |
651 | /* |
652 | * Do not disable backlight on the vgaswitcheroo path. When switching | |
653 | * away from i915, the other client may depend on i915 to handle the | |
654 | * backlight. This will leave the backlight on unnecessarily when | |
655 | * another client is not activated. | |
656 | */ | |
657 | if (dev->switch_power_state == DRM_SWITCH_POWER_CHANGING) { | |
658 | DRM_DEBUG_DRIVER("Skipping backlight disable on vga switch\n"); | |
659 | return; | |
660 | } | |
661 | ||
58c68779 | 662 | spin_lock_irqsave(&dev_priv->backlight_lock, flags); |
47356eb6 | 663 | |
58c68779 | 664 | panel->backlight.enabled = false; |
3bd712e5 | 665 | dev_priv->display.disable_backlight(connector); |
24ded204 | 666 | |
7bd688cd JN |
667 | spin_unlock_irqrestore(&dev_priv->backlight_lock, flags); |
668 | } | |
24ded204 | 669 | |
96ab4c70 DV |
670 | static void bdw_enable_backlight(struct intel_connector *connector) |
671 | { | |
672 | struct drm_device *dev = connector->base.dev; | |
673 | struct drm_i915_private *dev_priv = dev->dev_private; | |
674 | struct intel_panel *panel = &connector->panel; | |
675 | u32 pch_ctl1, pch_ctl2; | |
676 | ||
677 | pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1); | |
678 | if (pch_ctl1 & BLM_PCH_PWM_ENABLE) { | |
679 | DRM_DEBUG_KMS("pch backlight already enabled\n"); | |
680 | pch_ctl1 &= ~BLM_PCH_PWM_ENABLE; | |
681 | I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1); | |
682 | } | |
24ded204 | 683 | |
96ab4c70 DV |
684 | pch_ctl2 = panel->backlight.max << 16; |
685 | I915_WRITE(BLC_PWM_PCH_CTL2, pch_ctl2); | |
a4f32fc3 | 686 | |
96ab4c70 DV |
687 | pch_ctl1 = 0; |
688 | if (panel->backlight.active_low_pwm) | |
689 | pch_ctl1 |= BLM_PCH_POLARITY; | |
8ba2d185 | 690 | |
96ab4c70 DV |
691 | /* BDW always uses the pch pwm controls. */ |
692 | pch_ctl1 |= BLM_PCH_OVERRIDE_ENABLE; | |
693 | ||
694 | I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1); | |
695 | POSTING_READ(BLC_PWM_PCH_CTL1); | |
696 | I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_PWM_ENABLE); | |
697 | ||
698 | /* This won't stick until the above enable. */ | |
699 | intel_panel_actually_set_backlight(connector, panel->backlight.level); | |
47356eb6 CW |
700 | } |
701 | ||
7bd688cd JN |
702 | static void pch_enable_backlight(struct intel_connector *connector) |
703 | { | |
704 | struct drm_device *dev = connector->base.dev; | |
705 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3bd712e5 | 706 | struct intel_panel *panel = &connector->panel; |
7bd688cd JN |
707 | enum pipe pipe = intel_get_pipe_from_connector(connector); |
708 | enum transcoder cpu_transcoder = | |
709 | intel_pipe_to_cpu_transcoder(dev_priv, pipe); | |
b35684b8 | 710 | u32 cpu_ctl2, pch_ctl1, pch_ctl2; |
7bd688cd | 711 | |
b35684b8 JN |
712 | cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2); |
713 | if (cpu_ctl2 & BLM_PWM_ENABLE) { | |
714 | WARN(1, "cpu backlight already enabled\n"); | |
715 | cpu_ctl2 &= ~BLM_PWM_ENABLE; | |
716 | I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2); | |
717 | } | |
7bd688cd | 718 | |
b35684b8 JN |
719 | pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1); |
720 | if (pch_ctl1 & BLM_PCH_PWM_ENABLE) { | |
721 | DRM_DEBUG_KMS("pch backlight already enabled\n"); | |
722 | pch_ctl1 &= ~BLM_PCH_PWM_ENABLE; | |
723 | I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1); | |
724 | } | |
7bd688cd JN |
725 | |
726 | if (cpu_transcoder == TRANSCODER_EDP) | |
b35684b8 | 727 | cpu_ctl2 = BLM_TRANSCODER_EDP; |
7bd688cd | 728 | else |
b35684b8 JN |
729 | cpu_ctl2 = BLM_PIPE(cpu_transcoder); |
730 | I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2); | |
7bd688cd | 731 | POSTING_READ(BLC_PWM_CPU_CTL2); |
b35684b8 | 732 | I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2 | BLM_PWM_ENABLE); |
3bd712e5 | 733 | |
b35684b8 | 734 | /* This won't stick until the above enable. */ |
3bd712e5 | 735 | intel_panel_actually_set_backlight(connector, panel->backlight.level); |
b35684b8 JN |
736 | |
737 | pch_ctl2 = panel->backlight.max << 16; | |
738 | I915_WRITE(BLC_PWM_PCH_CTL2, pch_ctl2); | |
739 | ||
b35684b8 JN |
740 | pch_ctl1 = 0; |
741 | if (panel->backlight.active_low_pwm) | |
742 | pch_ctl1 |= BLM_PCH_POLARITY; | |
96ab4c70 | 743 | |
b35684b8 JN |
744 | I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1); |
745 | POSTING_READ(BLC_PWM_PCH_CTL1); | |
746 | I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_PWM_ENABLE); | |
3bd712e5 JN |
747 | } |
748 | ||
749 | static void i9xx_enable_backlight(struct intel_connector *connector) | |
750 | { | |
b35684b8 JN |
751 | struct drm_device *dev = connector->base.dev; |
752 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3bd712e5 | 753 | struct intel_panel *panel = &connector->panel; |
b35684b8 JN |
754 | u32 ctl, freq; |
755 | ||
756 | ctl = I915_READ(BLC_PWM_CTL); | |
757 | if (ctl & BACKLIGHT_DUTY_CYCLE_MASK_PNV) { | |
758 | WARN(1, "backlight already enabled\n"); | |
759 | I915_WRITE(BLC_PWM_CTL, 0); | |
760 | } | |
3bd712e5 | 761 | |
b35684b8 JN |
762 | freq = panel->backlight.max; |
763 | if (panel->backlight.combination_mode) | |
764 | freq /= 0xff; | |
765 | ||
766 | ctl = freq << 17; | |
b6ab66aa | 767 | if (panel->backlight.combination_mode) |
b35684b8 JN |
768 | ctl |= BLM_LEGACY_MODE; |
769 | if (IS_PINEVIEW(dev) && panel->backlight.active_low_pwm) | |
770 | ctl |= BLM_POLARITY_PNV; | |
771 | ||
772 | I915_WRITE(BLC_PWM_CTL, ctl); | |
773 | POSTING_READ(BLC_PWM_CTL); | |
774 | ||
775 | /* XXX: combine this into above write? */ | |
3bd712e5 | 776 | intel_panel_actually_set_backlight(connector, panel->backlight.level); |
7bd688cd | 777 | } |
8ba2d185 | 778 | |
7bd688cd JN |
779 | static void i965_enable_backlight(struct intel_connector *connector) |
780 | { | |
781 | struct drm_device *dev = connector->base.dev; | |
782 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3bd712e5 | 783 | struct intel_panel *panel = &connector->panel; |
7bd688cd | 784 | enum pipe pipe = intel_get_pipe_from_connector(connector); |
b35684b8 | 785 | u32 ctl, ctl2, freq; |
7bd688cd | 786 | |
b35684b8 JN |
787 | ctl2 = I915_READ(BLC_PWM_CTL2); |
788 | if (ctl2 & BLM_PWM_ENABLE) { | |
789 | WARN(1, "backlight already enabled\n"); | |
790 | ctl2 &= ~BLM_PWM_ENABLE; | |
791 | I915_WRITE(BLC_PWM_CTL2, ctl2); | |
792 | } | |
7bd688cd | 793 | |
b35684b8 JN |
794 | freq = panel->backlight.max; |
795 | if (panel->backlight.combination_mode) | |
796 | freq /= 0xff; | |
7bd688cd | 797 | |
b35684b8 JN |
798 | ctl = freq << 16; |
799 | I915_WRITE(BLC_PWM_CTL, ctl); | |
3bd712e5 | 800 | |
b35684b8 | 801 | /* XXX: combine this into above write? */ |
3bd712e5 | 802 | intel_panel_actually_set_backlight(connector, panel->backlight.level); |
b35684b8 JN |
803 | |
804 | ctl2 = BLM_PIPE(pipe); | |
805 | if (panel->backlight.combination_mode) | |
806 | ctl2 |= BLM_COMBINATION_MODE; | |
807 | if (panel->backlight.active_low_pwm) | |
808 | ctl2 |= BLM_POLARITY_I965; | |
809 | I915_WRITE(BLC_PWM_CTL2, ctl2); | |
810 | POSTING_READ(BLC_PWM_CTL2); | |
811 | I915_WRITE(BLC_PWM_CTL2, ctl2 | BLM_PWM_ENABLE); | |
7bd688cd JN |
812 | } |
813 | ||
814 | static void vlv_enable_backlight(struct intel_connector *connector) | |
815 | { | |
816 | struct drm_device *dev = connector->base.dev; | |
817 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3bd712e5 | 818 | struct intel_panel *panel = &connector->panel; |
7bd688cd | 819 | enum pipe pipe = intel_get_pipe_from_connector(connector); |
b35684b8 | 820 | u32 ctl, ctl2; |
7bd688cd | 821 | |
b35684b8 JN |
822 | ctl2 = I915_READ(VLV_BLC_PWM_CTL2(pipe)); |
823 | if (ctl2 & BLM_PWM_ENABLE) { | |
824 | WARN(1, "backlight already enabled\n"); | |
825 | ctl2 &= ~BLM_PWM_ENABLE; | |
826 | I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2); | |
827 | } | |
7bd688cd | 828 | |
b35684b8 JN |
829 | ctl = panel->backlight.max << 16; |
830 | I915_WRITE(VLV_BLC_PWM_CTL(pipe), ctl); | |
7bd688cd | 831 | |
b35684b8 JN |
832 | /* XXX: combine this into above write? */ |
833 | intel_panel_actually_set_backlight(connector, panel->backlight.level); | |
7bd688cd | 834 | |
b35684b8 JN |
835 | ctl2 = 0; |
836 | if (panel->backlight.active_low_pwm) | |
837 | ctl2 |= BLM_POLARITY_I965; | |
838 | I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2); | |
7bd688cd | 839 | POSTING_READ(VLV_BLC_PWM_CTL2(pipe)); |
b35684b8 | 840 | I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2 | BLM_PWM_ENABLE); |
47356eb6 CW |
841 | } |
842 | ||
752aa88a | 843 | void intel_panel_enable_backlight(struct intel_connector *connector) |
47356eb6 | 844 | { |
752aa88a | 845 | struct drm_device *dev = connector->base.dev; |
47356eb6 | 846 | struct drm_i915_private *dev_priv = dev->dev_private; |
58c68779 | 847 | struct intel_panel *panel = &connector->panel; |
752aa88a | 848 | enum pipe pipe = intel_get_pipe_from_connector(connector); |
8ba2d185 JN |
849 | unsigned long flags; |
850 | ||
dc5a4363 | 851 | if (!panel->backlight.present || pipe == INVALID_PIPE) |
752aa88a JB |
852 | return; |
853 | ||
6f2bcceb | 854 | DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe)); |
540b5d02 | 855 | |
58c68779 | 856 | spin_lock_irqsave(&dev_priv->backlight_lock, flags); |
47356eb6 | 857 | |
f91c15e0 JN |
858 | WARN_ON(panel->backlight.max == 0); |
859 | ||
58c68779 | 860 | if (panel->backlight.level == 0) { |
f91c15e0 | 861 | panel->backlight.level = panel->backlight.max; |
58c68779 JN |
862 | if (panel->backlight.device) |
863 | panel->backlight.device->props.brightness = | |
864 | panel->backlight.level; | |
b6b3ba5b | 865 | } |
47356eb6 | 866 | |
3bd712e5 | 867 | dev_priv->display.enable_backlight(connector); |
58c68779 | 868 | panel->backlight.enabled = true; |
8ba2d185 | 869 | |
58c68779 | 870 | spin_unlock_irqrestore(&dev_priv->backlight_lock, flags); |
47356eb6 CW |
871 | } |
872 | ||
912e8b12 | 873 | #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE) |
db31af1d | 874 | static int intel_backlight_device_update_status(struct backlight_device *bd) |
aaa6fd2a | 875 | { |
752aa88a JB |
876 | struct intel_connector *connector = bl_get_data(bd); |
877 | struct drm_device *dev = connector->base.dev; | |
878 | ||
51fd371b | 879 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
540b5d02 CW |
880 | DRM_DEBUG_KMS("updating intel_backlight, brightness=%d/%d\n", |
881 | bd->props.brightness, bd->props.max_brightness); | |
752aa88a | 882 | intel_panel_set_backlight(connector, bd->props.brightness, |
d6540632 | 883 | bd->props.max_brightness); |
51fd371b | 884 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
aaa6fd2a MG |
885 | return 0; |
886 | } | |
887 | ||
db31af1d | 888 | static int intel_backlight_device_get_brightness(struct backlight_device *bd) |
aaa6fd2a | 889 | { |
752aa88a JB |
890 | struct intel_connector *connector = bl_get_data(bd); |
891 | struct drm_device *dev = connector->base.dev; | |
c8c8fb33 | 892 | struct drm_i915_private *dev_priv = dev->dev_private; |
7bd688cd | 893 | int ret; |
752aa88a | 894 | |
c8c8fb33 | 895 | intel_runtime_pm_get(dev_priv); |
51fd371b | 896 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
7bd688cd | 897 | ret = intel_panel_get_backlight(connector); |
51fd371b | 898 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
c8c8fb33 | 899 | intel_runtime_pm_put(dev_priv); |
752aa88a | 900 | |
7bd688cd | 901 | return ret; |
aaa6fd2a MG |
902 | } |
903 | ||
db31af1d JN |
904 | static const struct backlight_ops intel_backlight_device_ops = { |
905 | .update_status = intel_backlight_device_update_status, | |
906 | .get_brightness = intel_backlight_device_get_brightness, | |
aaa6fd2a MG |
907 | }; |
908 | ||
db31af1d | 909 | static int intel_backlight_device_register(struct intel_connector *connector) |
aaa6fd2a | 910 | { |
58c68779 | 911 | struct intel_panel *panel = &connector->panel; |
aaa6fd2a | 912 | struct backlight_properties props; |
aaa6fd2a | 913 | |
58c68779 | 914 | if (WARN_ON(panel->backlight.device)) |
dc652f90 JN |
915 | return -ENODEV; |
916 | ||
7bd688cd JN |
917 | BUG_ON(panel->backlight.max == 0); |
918 | ||
af437cfd | 919 | memset(&props, 0, sizeof(props)); |
aaa6fd2a | 920 | props.type = BACKLIGHT_RAW; |
58c68779 | 921 | props.brightness = panel->backlight.level; |
7bd688cd | 922 | props.max_brightness = panel->backlight.max; |
58c68779 JN |
923 | |
924 | /* | |
925 | * Note: using the same name independent of the connector prevents | |
926 | * registration of multiple backlight devices in the driver. | |
927 | */ | |
928 | panel->backlight.device = | |
aaa6fd2a | 929 | backlight_device_register("intel_backlight", |
db31af1d JN |
930 | connector->base.kdev, |
931 | connector, | |
932 | &intel_backlight_device_ops, &props); | |
aaa6fd2a | 933 | |
58c68779 | 934 | if (IS_ERR(panel->backlight.device)) { |
aaa6fd2a | 935 | DRM_ERROR("Failed to register backlight: %ld\n", |
58c68779 JN |
936 | PTR_ERR(panel->backlight.device)); |
937 | panel->backlight.device = NULL; | |
aaa6fd2a MG |
938 | return -ENODEV; |
939 | } | |
aaa6fd2a MG |
940 | return 0; |
941 | } | |
942 | ||
db31af1d | 943 | static void intel_backlight_device_unregister(struct intel_connector *connector) |
aaa6fd2a | 944 | { |
58c68779 JN |
945 | struct intel_panel *panel = &connector->panel; |
946 | ||
947 | if (panel->backlight.device) { | |
948 | backlight_device_unregister(panel->backlight.device); | |
949 | panel->backlight.device = NULL; | |
dc652f90 | 950 | } |
aaa6fd2a | 951 | } |
db31af1d JN |
952 | #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */ |
953 | static int intel_backlight_device_register(struct intel_connector *connector) | |
954 | { | |
955 | return 0; | |
956 | } | |
957 | static void intel_backlight_device_unregister(struct intel_connector *connector) | |
958 | { | |
959 | } | |
960 | #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */ | |
961 | ||
f91c15e0 JN |
962 | /* |
963 | * Note: The setup hooks can't assume pipe is set! | |
964 | * | |
965 | * XXX: Query mode clock or hardware clock and program PWM modulation frequency | |
966 | * appropriately when it's 0. Use VBT and/or sane defaults. | |
967 | */ | |
96ab4c70 | 968 | static int bdw_setup_backlight(struct intel_connector *connector) |
aaa6fd2a | 969 | { |
96ab4c70 | 970 | struct drm_device *dev = connector->base.dev; |
aaa6fd2a | 971 | struct drm_i915_private *dev_priv = dev->dev_private; |
96ab4c70 DV |
972 | struct intel_panel *panel = &connector->panel; |
973 | u32 pch_ctl1, pch_ctl2, val; | |
974 | ||
975 | pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1); | |
976 | panel->backlight.active_low_pwm = pch_ctl1 & BLM_PCH_POLARITY; | |
977 | ||
978 | pch_ctl2 = I915_READ(BLC_PWM_PCH_CTL2); | |
979 | panel->backlight.max = pch_ctl2 >> 16; | |
980 | if (!panel->backlight.max) | |
981 | return -ENODEV; | |
982 | ||
983 | val = bdw_get_backlight(connector); | |
984 | panel->backlight.level = intel_panel_compute_brightness(connector, val); | |
985 | ||
986 | panel->backlight.enabled = (pch_ctl1 & BLM_PCH_PWM_ENABLE) && | |
987 | panel->backlight.level != 0; | |
988 | ||
989 | return 0; | |
990 | } | |
991 | ||
7bd688cd JN |
992 | static int pch_setup_backlight(struct intel_connector *connector) |
993 | { | |
636baebf JN |
994 | struct drm_device *dev = connector->base.dev; |
995 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7bd688cd | 996 | struct intel_panel *panel = &connector->panel; |
636baebf | 997 | u32 cpu_ctl2, pch_ctl1, pch_ctl2, val; |
7bd688cd | 998 | |
636baebf JN |
999 | pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1); |
1000 | panel->backlight.active_low_pwm = pch_ctl1 & BLM_PCH_POLARITY; | |
1001 | ||
1002 | pch_ctl2 = I915_READ(BLC_PWM_PCH_CTL2); | |
1003 | panel->backlight.max = pch_ctl2 >> 16; | |
7bd688cd JN |
1004 | if (!panel->backlight.max) |
1005 | return -ENODEV; | |
1006 | ||
1007 | val = pch_get_backlight(connector); | |
1008 | panel->backlight.level = intel_panel_compute_brightness(connector, val); | |
1009 | ||
636baebf JN |
1010 | cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2); |
1011 | panel->backlight.enabled = (cpu_ctl2 & BLM_PWM_ENABLE) && | |
1012 | (pch_ctl1 & BLM_PCH_PWM_ENABLE) && panel->backlight.level != 0; | |
1013 | ||
7bd688cd JN |
1014 | return 0; |
1015 | } | |
1016 | ||
1017 | static int i9xx_setup_backlight(struct intel_connector *connector) | |
1018 | { | |
636baebf JN |
1019 | struct drm_device *dev = connector->base.dev; |
1020 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7bd688cd | 1021 | struct intel_panel *panel = &connector->panel; |
636baebf JN |
1022 | u32 ctl, val; |
1023 | ||
1024 | ctl = I915_READ(BLC_PWM_CTL); | |
1025 | ||
b6ab66aa | 1026 | if (IS_GEN2(dev) || IS_I915GM(dev) || IS_I945GM(dev)) |
636baebf JN |
1027 | panel->backlight.combination_mode = ctl & BLM_LEGACY_MODE; |
1028 | ||
1029 | if (IS_PINEVIEW(dev)) | |
1030 | panel->backlight.active_low_pwm = ctl & BLM_POLARITY_PNV; | |
1031 | ||
1032 | panel->backlight.max = ctl >> 17; | |
1033 | if (panel->backlight.combination_mode) | |
1034 | panel->backlight.max *= 0xff; | |
7bd688cd | 1035 | |
7bd688cd JN |
1036 | if (!panel->backlight.max) |
1037 | return -ENODEV; | |
1038 | ||
1039 | val = i9xx_get_backlight(connector); | |
1040 | panel->backlight.level = intel_panel_compute_brightness(connector, val); | |
1041 | ||
636baebf JN |
1042 | panel->backlight.enabled = panel->backlight.level != 0; |
1043 | ||
7bd688cd JN |
1044 | return 0; |
1045 | } | |
1046 | ||
1047 | static int i965_setup_backlight(struct intel_connector *connector) | |
1048 | { | |
636baebf JN |
1049 | struct drm_device *dev = connector->base.dev; |
1050 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7bd688cd | 1051 | struct intel_panel *panel = &connector->panel; |
636baebf JN |
1052 | u32 ctl, ctl2, val; |
1053 | ||
1054 | ctl2 = I915_READ(BLC_PWM_CTL2); | |
1055 | panel->backlight.combination_mode = ctl2 & BLM_COMBINATION_MODE; | |
1056 | panel->backlight.active_low_pwm = ctl2 & BLM_POLARITY_I965; | |
1057 | ||
1058 | ctl = I915_READ(BLC_PWM_CTL); | |
1059 | panel->backlight.max = ctl >> 16; | |
1060 | if (panel->backlight.combination_mode) | |
1061 | panel->backlight.max *= 0xff; | |
7bd688cd | 1062 | |
7bd688cd JN |
1063 | if (!panel->backlight.max) |
1064 | return -ENODEV; | |
1065 | ||
1066 | val = i9xx_get_backlight(connector); | |
1067 | panel->backlight.level = intel_panel_compute_brightness(connector, val); | |
1068 | ||
636baebf JN |
1069 | panel->backlight.enabled = (ctl2 & BLM_PWM_ENABLE) && |
1070 | panel->backlight.level != 0; | |
1071 | ||
7bd688cd JN |
1072 | return 0; |
1073 | } | |
1074 | ||
1075 | static int vlv_setup_backlight(struct intel_connector *connector) | |
1076 | { | |
1077 | struct drm_device *dev = connector->base.dev; | |
1078 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1079 | struct intel_panel *panel = &connector->panel; | |
1080 | enum pipe pipe; | |
636baebf | 1081 | u32 ctl, ctl2, val; |
7bd688cd JN |
1082 | |
1083 | for_each_pipe(pipe) { | |
1084 | u32 cur_val = I915_READ(VLV_BLC_PWM_CTL(pipe)); | |
1085 | ||
1086 | /* Skip if the modulation freq is already set */ | |
1087 | if (cur_val & ~BACKLIGHT_DUTY_CYCLE_MASK) | |
1088 | continue; | |
1089 | ||
1090 | cur_val &= BACKLIGHT_DUTY_CYCLE_MASK; | |
1091 | I915_WRITE(VLV_BLC_PWM_CTL(pipe), (0xf42 << 16) | | |
1092 | cur_val); | |
1093 | } | |
1094 | ||
636baebf JN |
1095 | ctl2 = I915_READ(VLV_BLC_PWM_CTL2(PIPE_A)); |
1096 | panel->backlight.active_low_pwm = ctl2 & BLM_POLARITY_I965; | |
1097 | ||
1098 | ctl = I915_READ(VLV_BLC_PWM_CTL(PIPE_A)); | |
1099 | panel->backlight.max = ctl >> 16; | |
7bd688cd JN |
1100 | if (!panel->backlight.max) |
1101 | return -ENODEV; | |
1102 | ||
1103 | val = _vlv_get_backlight(dev, PIPE_A); | |
1104 | panel->backlight.level = intel_panel_compute_brightness(connector, val); | |
1105 | ||
636baebf JN |
1106 | panel->backlight.enabled = (ctl2 & BLM_PWM_ENABLE) && |
1107 | panel->backlight.level != 0; | |
1108 | ||
7bd688cd JN |
1109 | return 0; |
1110 | } | |
1111 | ||
0657b6b1 | 1112 | int intel_panel_setup_backlight(struct drm_connector *connector) |
aaa6fd2a | 1113 | { |
db31af1d | 1114 | struct drm_device *dev = connector->dev; |
7bd688cd | 1115 | struct drm_i915_private *dev_priv = dev->dev_private; |
db31af1d | 1116 | struct intel_connector *intel_connector = to_intel_connector(connector); |
58c68779 | 1117 | struct intel_panel *panel = &intel_connector->panel; |
7bd688cd JN |
1118 | unsigned long flags; |
1119 | int ret; | |
db31af1d | 1120 | |
c675949e JN |
1121 | if (!dev_priv->vbt.backlight.present) { |
1122 | DRM_DEBUG_KMS("native backlight control not available per VBT\n"); | |
1123 | return 0; | |
1124 | } | |
1125 | ||
7bd688cd JN |
1126 | /* set level and max in panel struct */ |
1127 | spin_lock_irqsave(&dev_priv->backlight_lock, flags); | |
1128 | ret = dev_priv->display.setup_backlight(intel_connector); | |
1129 | spin_unlock_irqrestore(&dev_priv->backlight_lock, flags); | |
1130 | ||
1131 | if (ret) { | |
1132 | DRM_DEBUG_KMS("failed to setup backlight for connector %s\n", | |
c23cc417 | 1133 | connector->name); |
7bd688cd JN |
1134 | return ret; |
1135 | } | |
db31af1d | 1136 | |
db31af1d JN |
1137 | intel_backlight_device_register(intel_connector); |
1138 | ||
c91c9f32 JN |
1139 | panel->backlight.present = true; |
1140 | ||
c445b3b1 JN |
1141 | DRM_DEBUG_KMS("backlight initialized, %s, brightness %u/%u, " |
1142 | "sysfs interface %sregistered\n", | |
1143 | panel->backlight.enabled ? "enabled" : "disabled", | |
1144 | panel->backlight.level, panel->backlight.max, | |
1145 | panel->backlight.device ? "" : "not "); | |
1146 | ||
aaa6fd2a MG |
1147 | return 0; |
1148 | } | |
1149 | ||
db31af1d | 1150 | void intel_panel_destroy_backlight(struct drm_connector *connector) |
aaa6fd2a | 1151 | { |
db31af1d | 1152 | struct intel_connector *intel_connector = to_intel_connector(connector); |
c91c9f32 | 1153 | struct intel_panel *panel = &intel_connector->panel; |
db31af1d | 1154 | |
c91c9f32 | 1155 | panel->backlight.present = false; |
db31af1d | 1156 | intel_backlight_device_unregister(intel_connector); |
aaa6fd2a | 1157 | } |
1d508706 | 1158 | |
7bd688cd JN |
1159 | /* Set up chip specific backlight functions */ |
1160 | void intel_panel_init_backlight_funcs(struct drm_device *dev) | |
1161 | { | |
1162 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1163 | ||
96ab4c70 DV |
1164 | if (IS_BROADWELL(dev)) { |
1165 | dev_priv->display.setup_backlight = bdw_setup_backlight; | |
1166 | dev_priv->display.enable_backlight = bdw_enable_backlight; | |
1167 | dev_priv->display.disable_backlight = pch_disable_backlight; | |
1168 | dev_priv->display.set_backlight = bdw_set_backlight; | |
1169 | dev_priv->display.get_backlight = bdw_get_backlight; | |
1170 | } else if (HAS_PCH_SPLIT(dev)) { | |
7bd688cd JN |
1171 | dev_priv->display.setup_backlight = pch_setup_backlight; |
1172 | dev_priv->display.enable_backlight = pch_enable_backlight; | |
1173 | dev_priv->display.disable_backlight = pch_disable_backlight; | |
1174 | dev_priv->display.set_backlight = pch_set_backlight; | |
1175 | dev_priv->display.get_backlight = pch_get_backlight; | |
7bd688cd JN |
1176 | } else if (IS_VALLEYVIEW(dev)) { |
1177 | dev_priv->display.setup_backlight = vlv_setup_backlight; | |
1178 | dev_priv->display.enable_backlight = vlv_enable_backlight; | |
1179 | dev_priv->display.disable_backlight = vlv_disable_backlight; | |
1180 | dev_priv->display.set_backlight = vlv_set_backlight; | |
1181 | dev_priv->display.get_backlight = vlv_get_backlight; | |
7bd688cd JN |
1182 | } else if (IS_GEN4(dev)) { |
1183 | dev_priv->display.setup_backlight = i965_setup_backlight; | |
1184 | dev_priv->display.enable_backlight = i965_enable_backlight; | |
1185 | dev_priv->display.disable_backlight = i965_disable_backlight; | |
1186 | dev_priv->display.set_backlight = i9xx_set_backlight; | |
1187 | dev_priv->display.get_backlight = i9xx_get_backlight; | |
7bd688cd JN |
1188 | } else { |
1189 | dev_priv->display.setup_backlight = i9xx_setup_backlight; | |
3bd712e5 JN |
1190 | dev_priv->display.enable_backlight = i9xx_enable_backlight; |
1191 | dev_priv->display.disable_backlight = i9xx_disable_backlight; | |
7bd688cd JN |
1192 | dev_priv->display.set_backlight = i9xx_set_backlight; |
1193 | dev_priv->display.get_backlight = i9xx_get_backlight; | |
7bd688cd JN |
1194 | } |
1195 | } | |
1196 | ||
dd06f90e | 1197 | int intel_panel_init(struct intel_panel *panel, |
4b6ed685 VK |
1198 | struct drm_display_mode *fixed_mode, |
1199 | struct drm_display_mode *downclock_mode) | |
1d508706 | 1200 | { |
dd06f90e | 1201 | panel->fixed_mode = fixed_mode; |
4b6ed685 | 1202 | panel->downclock_mode = downclock_mode; |
dd06f90e | 1203 | |
1d508706 JN |
1204 | return 0; |
1205 | } | |
1206 | ||
1207 | void intel_panel_fini(struct intel_panel *panel) | |
1208 | { | |
dd06f90e JN |
1209 | struct intel_connector *intel_connector = |
1210 | container_of(panel, struct intel_connector, panel); | |
1211 | ||
1212 | if (panel->fixed_mode) | |
1213 | drm_mode_destroy(intel_connector->base.dev, panel->fixed_mode); | |
ec9ed197 VK |
1214 | |
1215 | if (panel->downclock_mode) | |
1216 | drm_mode_destroy(intel_connector->base.dev, | |
1217 | panel->downclock_mode); | |
1d508706 | 1218 | } |