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1d8e1c75 CW |
1 | /* |
2 | * Copyright © 2006-2010 Intel Corporation | |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Dave Airlie <airlied@linux.ie> | |
27 | * Jesse Barnes <jesse.barnes@intel.com> | |
28 | * Chris Wilson <chris@chris-wilson.co.uk> | |
29 | */ | |
30 | ||
a70491cc JP |
31 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
32 | ||
7bd90909 | 33 | #include <linux/moduleparam.h> |
1d8e1c75 CW |
34 | #include "intel_drv.h" |
35 | ||
36 | void | |
4c6df4b4 | 37 | intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, |
1d8e1c75 CW |
38 | struct drm_display_mode *adjusted_mode) |
39 | { | |
4c6df4b4 | 40 | drm_mode_copy(adjusted_mode, fixed_mode); |
a52690e4 ID |
41 | |
42 | drm_mode_set_crtcinfo(adjusted_mode, 0); | |
1d8e1c75 CW |
43 | } |
44 | ||
45 | /* adjusted_mode has been preset to be the panel's fixed mode */ | |
46 | void | |
b074cec8 JB |
47 | intel_pch_panel_fitting(struct intel_crtc *intel_crtc, |
48 | struct intel_crtc_config *pipe_config, | |
49 | int fitting_mode) | |
1d8e1c75 | 50 | { |
37327abd | 51 | struct drm_display_mode *adjusted_mode; |
1d8e1c75 CW |
52 | int x, y, width, height; |
53 | ||
b074cec8 JB |
54 | adjusted_mode = &pipe_config->adjusted_mode; |
55 | ||
1d8e1c75 CW |
56 | x = y = width = height = 0; |
57 | ||
58 | /* Native modes don't need fitting */ | |
37327abd VS |
59 | if (adjusted_mode->hdisplay == pipe_config->pipe_src_w && |
60 | adjusted_mode->vdisplay == pipe_config->pipe_src_h) | |
1d8e1c75 CW |
61 | goto done; |
62 | ||
63 | switch (fitting_mode) { | |
64 | case DRM_MODE_SCALE_CENTER: | |
37327abd VS |
65 | width = pipe_config->pipe_src_w; |
66 | height = pipe_config->pipe_src_h; | |
1d8e1c75 CW |
67 | x = (adjusted_mode->hdisplay - width + 1)/2; |
68 | y = (adjusted_mode->vdisplay - height + 1)/2; | |
69 | break; | |
70 | ||
71 | case DRM_MODE_SCALE_ASPECT: | |
72 | /* Scale but preserve the aspect ratio */ | |
73 | { | |
9084e7d2 DV |
74 | u32 scaled_width = adjusted_mode->hdisplay |
75 | * pipe_config->pipe_src_h; | |
76 | u32 scaled_height = pipe_config->pipe_src_w | |
77 | * adjusted_mode->vdisplay; | |
1d8e1c75 | 78 | if (scaled_width > scaled_height) { /* pillar */ |
37327abd | 79 | width = scaled_height / pipe_config->pipe_src_h; |
302983e9 | 80 | if (width & 1) |
0206e353 | 81 | width++; |
1d8e1c75 CW |
82 | x = (adjusted_mode->hdisplay - width + 1) / 2; |
83 | y = 0; | |
84 | height = adjusted_mode->vdisplay; | |
85 | } else if (scaled_width < scaled_height) { /* letter */ | |
37327abd | 86 | height = scaled_width / pipe_config->pipe_src_w; |
302983e9 AJ |
87 | if (height & 1) |
88 | height++; | |
1d8e1c75 CW |
89 | y = (adjusted_mode->vdisplay - height + 1) / 2; |
90 | x = 0; | |
91 | width = adjusted_mode->hdisplay; | |
92 | } else { | |
93 | x = y = 0; | |
94 | width = adjusted_mode->hdisplay; | |
95 | height = adjusted_mode->vdisplay; | |
96 | } | |
97 | } | |
98 | break; | |
99 | ||
1d8e1c75 CW |
100 | case DRM_MODE_SCALE_FULLSCREEN: |
101 | x = y = 0; | |
102 | width = adjusted_mode->hdisplay; | |
103 | height = adjusted_mode->vdisplay; | |
104 | break; | |
ab3e67f4 JB |
105 | |
106 | default: | |
107 | WARN(1, "bad panel fit mode: %d\n", fitting_mode); | |
108 | return; | |
1d8e1c75 CW |
109 | } |
110 | ||
111 | done: | |
b074cec8 JB |
112 | pipe_config->pch_pfit.pos = (x << 16) | y; |
113 | pipe_config->pch_pfit.size = (width << 16) | height; | |
fd4daa9c | 114 | pipe_config->pch_pfit.enabled = pipe_config->pch_pfit.size != 0; |
1d8e1c75 | 115 | } |
a9573556 | 116 | |
2dd24552 JB |
117 | static void |
118 | centre_horizontally(struct drm_display_mode *mode, | |
119 | int width) | |
120 | { | |
121 | u32 border, sync_pos, blank_width, sync_width; | |
122 | ||
123 | /* keep the hsync and hblank widths constant */ | |
124 | sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start; | |
125 | blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start; | |
126 | sync_pos = (blank_width - sync_width + 1) / 2; | |
127 | ||
128 | border = (mode->hdisplay - width + 1) / 2; | |
129 | border += border & 1; /* make the border even */ | |
130 | ||
131 | mode->crtc_hdisplay = width; | |
132 | mode->crtc_hblank_start = width + border; | |
133 | mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width; | |
134 | ||
135 | mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos; | |
136 | mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width; | |
137 | } | |
138 | ||
139 | static void | |
140 | centre_vertically(struct drm_display_mode *mode, | |
141 | int height) | |
142 | { | |
143 | u32 border, sync_pos, blank_width, sync_width; | |
144 | ||
145 | /* keep the vsync and vblank widths constant */ | |
146 | sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start; | |
147 | blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start; | |
148 | sync_pos = (blank_width - sync_width + 1) / 2; | |
149 | ||
150 | border = (mode->vdisplay - height + 1) / 2; | |
151 | ||
152 | mode->crtc_vdisplay = height; | |
153 | mode->crtc_vblank_start = height + border; | |
154 | mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width; | |
155 | ||
156 | mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos; | |
157 | mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width; | |
158 | } | |
159 | ||
160 | static inline u32 panel_fitter_scaling(u32 source, u32 target) | |
161 | { | |
162 | /* | |
163 | * Floating point operation is not supported. So the FACTOR | |
164 | * is defined, which can avoid the floating point computation | |
165 | * when calculating the panel ratio. | |
166 | */ | |
167 | #define ACCURACY 12 | |
168 | #define FACTOR (1 << ACCURACY) | |
169 | u32 ratio = source * FACTOR / target; | |
170 | return (FACTOR * ratio + FACTOR/2) / FACTOR; | |
171 | } | |
172 | ||
9084e7d2 DV |
173 | static void i965_scale_aspect(struct intel_crtc_config *pipe_config, |
174 | u32 *pfit_control) | |
175 | { | |
176 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; | |
177 | u32 scaled_width = adjusted_mode->hdisplay * | |
178 | pipe_config->pipe_src_h; | |
179 | u32 scaled_height = pipe_config->pipe_src_w * | |
180 | adjusted_mode->vdisplay; | |
181 | ||
182 | /* 965+ is easy, it does everything in hw */ | |
183 | if (scaled_width > scaled_height) | |
184 | *pfit_control |= PFIT_ENABLE | | |
185 | PFIT_SCALING_PILLAR; | |
186 | else if (scaled_width < scaled_height) | |
187 | *pfit_control |= PFIT_ENABLE | | |
188 | PFIT_SCALING_LETTER; | |
189 | else if (adjusted_mode->hdisplay != pipe_config->pipe_src_w) | |
190 | *pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO; | |
191 | } | |
192 | ||
193 | static void i9xx_scale_aspect(struct intel_crtc_config *pipe_config, | |
194 | u32 *pfit_control, u32 *pfit_pgm_ratios, | |
195 | u32 *border) | |
196 | { | |
197 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; | |
198 | u32 scaled_width = adjusted_mode->hdisplay * | |
199 | pipe_config->pipe_src_h; | |
200 | u32 scaled_height = pipe_config->pipe_src_w * | |
201 | adjusted_mode->vdisplay; | |
202 | u32 bits; | |
203 | ||
204 | /* | |
205 | * For earlier chips we have to calculate the scaling | |
206 | * ratio by hand and program it into the | |
207 | * PFIT_PGM_RATIO register | |
208 | */ | |
209 | if (scaled_width > scaled_height) { /* pillar */ | |
210 | centre_horizontally(adjusted_mode, | |
211 | scaled_height / | |
212 | pipe_config->pipe_src_h); | |
213 | ||
214 | *border = LVDS_BORDER_ENABLE; | |
215 | if (pipe_config->pipe_src_h != adjusted_mode->vdisplay) { | |
216 | bits = panel_fitter_scaling(pipe_config->pipe_src_h, | |
217 | adjusted_mode->vdisplay); | |
218 | ||
219 | *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | |
220 | bits << PFIT_VERT_SCALE_SHIFT); | |
221 | *pfit_control |= (PFIT_ENABLE | | |
222 | VERT_INTERP_BILINEAR | | |
223 | HORIZ_INTERP_BILINEAR); | |
224 | } | |
225 | } else if (scaled_width < scaled_height) { /* letter */ | |
226 | centre_vertically(adjusted_mode, | |
227 | scaled_width / | |
228 | pipe_config->pipe_src_w); | |
229 | ||
230 | *border = LVDS_BORDER_ENABLE; | |
231 | if (pipe_config->pipe_src_w != adjusted_mode->hdisplay) { | |
232 | bits = panel_fitter_scaling(pipe_config->pipe_src_w, | |
233 | adjusted_mode->hdisplay); | |
234 | ||
235 | *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | |
236 | bits << PFIT_VERT_SCALE_SHIFT); | |
237 | *pfit_control |= (PFIT_ENABLE | | |
238 | VERT_INTERP_BILINEAR | | |
239 | HORIZ_INTERP_BILINEAR); | |
240 | } | |
241 | } else { | |
242 | /* Aspects match, Let hw scale both directions */ | |
243 | *pfit_control |= (PFIT_ENABLE | | |
244 | VERT_AUTO_SCALE | HORIZ_AUTO_SCALE | | |
245 | VERT_INTERP_BILINEAR | | |
246 | HORIZ_INTERP_BILINEAR); | |
247 | } | |
248 | } | |
249 | ||
2dd24552 JB |
250 | void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc, |
251 | struct intel_crtc_config *pipe_config, | |
252 | int fitting_mode) | |
253 | { | |
254 | struct drm_device *dev = intel_crtc->base.dev; | |
2dd24552 | 255 | u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0; |
37327abd | 256 | struct drm_display_mode *adjusted_mode; |
2dd24552 | 257 | |
2dd24552 JB |
258 | adjusted_mode = &pipe_config->adjusted_mode; |
259 | ||
260 | /* Native modes don't need fitting */ | |
37327abd VS |
261 | if (adjusted_mode->hdisplay == pipe_config->pipe_src_w && |
262 | adjusted_mode->vdisplay == pipe_config->pipe_src_h) | |
2dd24552 JB |
263 | goto out; |
264 | ||
265 | switch (fitting_mode) { | |
266 | case DRM_MODE_SCALE_CENTER: | |
267 | /* | |
268 | * For centered modes, we have to calculate border widths & | |
269 | * heights and modify the values programmed into the CRTC. | |
270 | */ | |
37327abd VS |
271 | centre_horizontally(adjusted_mode, pipe_config->pipe_src_w); |
272 | centre_vertically(adjusted_mode, pipe_config->pipe_src_h); | |
2dd24552 JB |
273 | border = LVDS_BORDER_ENABLE; |
274 | break; | |
275 | case DRM_MODE_SCALE_ASPECT: | |
276 | /* Scale but preserve the aspect ratio */ | |
9084e7d2 DV |
277 | if (INTEL_INFO(dev)->gen >= 4) |
278 | i965_scale_aspect(pipe_config, &pfit_control); | |
279 | else | |
280 | i9xx_scale_aspect(pipe_config, &pfit_control, | |
281 | &pfit_pgm_ratios, &border); | |
2dd24552 | 282 | break; |
2dd24552 JB |
283 | case DRM_MODE_SCALE_FULLSCREEN: |
284 | /* | |
285 | * Full scaling, even if it changes the aspect ratio. | |
286 | * Fortunately this is all done for us in hw. | |
287 | */ | |
37327abd VS |
288 | if (pipe_config->pipe_src_h != adjusted_mode->vdisplay || |
289 | pipe_config->pipe_src_w != adjusted_mode->hdisplay) { | |
2dd24552 JB |
290 | pfit_control |= PFIT_ENABLE; |
291 | if (INTEL_INFO(dev)->gen >= 4) | |
292 | pfit_control |= PFIT_SCALING_AUTO; | |
293 | else | |
294 | pfit_control |= (VERT_AUTO_SCALE | | |
295 | VERT_INTERP_BILINEAR | | |
296 | HORIZ_AUTO_SCALE | | |
297 | HORIZ_INTERP_BILINEAR); | |
298 | } | |
299 | break; | |
ab3e67f4 JB |
300 | default: |
301 | WARN(1, "bad panel fit mode: %d\n", fitting_mode); | |
302 | return; | |
2dd24552 JB |
303 | } |
304 | ||
305 | /* 965+ wants fuzzy fitting */ | |
306 | /* FIXME: handle multiple panels by failing gracefully */ | |
307 | if (INTEL_INFO(dev)->gen >= 4) | |
308 | pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) | | |
309 | PFIT_FILTER_FUZZY); | |
310 | ||
311 | out: | |
312 | if ((pfit_control & PFIT_ENABLE) == 0) { | |
313 | pfit_control = 0; | |
314 | pfit_pgm_ratios = 0; | |
315 | } | |
316 | ||
317 | /* Make sure pre-965 set dither correctly for 18bpp panels. */ | |
318 | if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18) | |
319 | pfit_control |= PANEL_8TO6_DITHER_ENABLE; | |
320 | ||
2deefda5 DV |
321 | pipe_config->gmch_pfit.control = pfit_control; |
322 | pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios; | |
68fc8742 | 323 | pipe_config->gmch_pfit.lvds_border_bits = border; |
2dd24552 JB |
324 | } |
325 | ||
7bd688cd JN |
326 | static u32 intel_panel_compute_brightness(struct intel_connector *connector, |
327 | u32 val) | |
7bd90909 | 328 | { |
7bd688cd | 329 | struct drm_device *dev = connector->base.dev; |
4dca20ef | 330 | struct drm_i915_private *dev_priv = dev->dev_private; |
f91c15e0 JN |
331 | struct intel_panel *panel = &connector->panel; |
332 | ||
333 | WARN_ON(panel->backlight.max == 0); | |
4dca20ef | 334 | |
d330a953 | 335 | if (i915.invert_brightness < 0) |
4dca20ef CE |
336 | return val; |
337 | ||
d330a953 | 338 | if (i915.invert_brightness > 0 || |
d6540632 | 339 | dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) { |
f91c15e0 | 340 | return panel->backlight.max - val; |
d6540632 | 341 | } |
7bd90909 CE |
342 | |
343 | return val; | |
344 | } | |
345 | ||
96ab4c70 | 346 | static u32 bdw_get_backlight(struct intel_connector *connector) |
0b0b053a | 347 | { |
96ab4c70 | 348 | struct drm_device *dev = connector->base.dev; |
bfd7590d | 349 | struct drm_i915_private *dev_priv = dev->dev_private; |
0b0b053a | 350 | |
96ab4c70 DV |
351 | return I915_READ(BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK; |
352 | } | |
07bf139b | 353 | |
7bd688cd | 354 | static u32 pch_get_backlight(struct intel_connector *connector) |
a9573556 | 355 | { |
7bd688cd | 356 | struct drm_device *dev = connector->base.dev; |
a9573556 | 357 | struct drm_i915_private *dev_priv = dev->dev_private; |
8ba2d185 | 358 | |
7bd688cd JN |
359 | return I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; |
360 | } | |
a9573556 | 361 | |
7bd688cd JN |
362 | static u32 i9xx_get_backlight(struct intel_connector *connector) |
363 | { | |
364 | struct drm_device *dev = connector->base.dev; | |
365 | struct drm_i915_private *dev_priv = dev->dev_private; | |
636baebf | 366 | struct intel_panel *panel = &connector->panel; |
7bd688cd | 367 | u32 val; |
07bf139b | 368 | |
7bd688cd JN |
369 | val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; |
370 | if (INTEL_INFO(dev)->gen < 4) | |
371 | val >>= 1; | |
ba3820ad | 372 | |
636baebf | 373 | if (panel->backlight.combination_mode) { |
7bd688cd | 374 | u8 lbpc; |
ba3820ad | 375 | |
7bd688cd JN |
376 | pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc); |
377 | val *= lbpc; | |
a9573556 CW |
378 | } |
379 | ||
7bd688cd JN |
380 | return val; |
381 | } | |
382 | ||
383 | static u32 _vlv_get_backlight(struct drm_device *dev, enum pipe pipe) | |
384 | { | |
385 | struct drm_i915_private *dev_priv = dev->dev_private; | |
386 | ||
387 | return I915_READ(VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK; | |
388 | } | |
389 | ||
390 | static u32 vlv_get_backlight(struct intel_connector *connector) | |
391 | { | |
392 | struct drm_device *dev = connector->base.dev; | |
393 | enum pipe pipe = intel_get_pipe_from_connector(connector); | |
394 | ||
395 | return _vlv_get_backlight(dev, pipe); | |
396 | } | |
397 | ||
398 | static u32 intel_panel_get_backlight(struct intel_connector *connector) | |
399 | { | |
400 | struct drm_device *dev = connector->base.dev; | |
401 | struct drm_i915_private *dev_priv = dev->dev_private; | |
402 | u32 val; | |
403 | unsigned long flags; | |
404 | ||
405 | spin_lock_irqsave(&dev_priv->backlight_lock, flags); | |
406 | ||
407 | val = dev_priv->display.get_backlight(connector); | |
408 | val = intel_panel_compute_brightness(connector, val); | |
8ba2d185 | 409 | |
58c68779 | 410 | spin_unlock_irqrestore(&dev_priv->backlight_lock, flags); |
8ba2d185 | 411 | |
a9573556 CW |
412 | DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val); |
413 | return val; | |
414 | } | |
415 | ||
96ab4c70 | 416 | static void bdw_set_backlight(struct intel_connector *connector, u32 level) |
f8e10062 | 417 | { |
96ab4c70 | 418 | struct drm_device *dev = connector->base.dev; |
f8e10062 BW |
419 | struct drm_i915_private *dev_priv = dev->dev_private; |
420 | u32 val = I915_READ(BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK; | |
421 | I915_WRITE(BLC_PWM_PCH_CTL2, val | level); | |
422 | } | |
423 | ||
7bd688cd | 424 | static void pch_set_backlight(struct intel_connector *connector, u32 level) |
a9573556 | 425 | { |
7bd688cd | 426 | struct drm_device *dev = connector->base.dev; |
a9573556 | 427 | struct drm_i915_private *dev_priv = dev->dev_private; |
7bd688cd JN |
428 | u32 tmp; |
429 | ||
430 | tmp = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; | |
431 | I915_WRITE(BLC_PWM_CPU_CTL, tmp | level); | |
a9573556 CW |
432 | } |
433 | ||
7bd688cd | 434 | static void i9xx_set_backlight(struct intel_connector *connector, u32 level) |
a9573556 | 435 | { |
7bd688cd | 436 | struct drm_device *dev = connector->base.dev; |
a9573556 | 437 | struct drm_i915_private *dev_priv = dev->dev_private; |
f91c15e0 | 438 | struct intel_panel *panel = &connector->panel; |
b329b328 | 439 | u32 tmp, mask; |
ba3820ad | 440 | |
f91c15e0 JN |
441 | WARN_ON(panel->backlight.max == 0); |
442 | ||
636baebf | 443 | if (panel->backlight.combination_mode) { |
ba3820ad TI |
444 | u8 lbpc; |
445 | ||
f91c15e0 | 446 | lbpc = level * 0xfe / panel->backlight.max + 1; |
ba3820ad TI |
447 | level /= lbpc; |
448 | pci_write_config_byte(dev->pdev, PCI_LBPC, lbpc); | |
449 | } | |
450 | ||
b329b328 JN |
451 | if (IS_GEN4(dev)) { |
452 | mask = BACKLIGHT_DUTY_CYCLE_MASK; | |
453 | } else { | |
a9573556 | 454 | level <<= 1; |
b329b328 JN |
455 | mask = BACKLIGHT_DUTY_CYCLE_MASK_PNV; |
456 | } | |
7bd688cd | 457 | |
b329b328 | 458 | tmp = I915_READ(BLC_PWM_CTL) & ~mask; |
7bd688cd JN |
459 | I915_WRITE(BLC_PWM_CTL, tmp | level); |
460 | } | |
461 | ||
462 | static void vlv_set_backlight(struct intel_connector *connector, u32 level) | |
463 | { | |
464 | struct drm_device *dev = connector->base.dev; | |
465 | struct drm_i915_private *dev_priv = dev->dev_private; | |
466 | enum pipe pipe = intel_get_pipe_from_connector(connector); | |
467 | u32 tmp; | |
468 | ||
469 | tmp = I915_READ(VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK; | |
470 | I915_WRITE(VLV_BLC_PWM_CTL(pipe), tmp | level); | |
471 | } | |
472 | ||
473 | static void | |
474 | intel_panel_actually_set_backlight(struct intel_connector *connector, u32 level) | |
475 | { | |
476 | struct drm_device *dev = connector->base.dev; | |
477 | struct drm_i915_private *dev_priv = dev->dev_private; | |
478 | ||
479 | DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level); | |
480 | ||
481 | level = intel_panel_compute_brightness(connector, level); | |
482 | dev_priv->display.set_backlight(connector, level); | |
a9573556 | 483 | } |
47356eb6 | 484 | |
d6540632 | 485 | /* set backlight brightness to level in range [0..max] */ |
752aa88a JB |
486 | void intel_panel_set_backlight(struct intel_connector *connector, u32 level, |
487 | u32 max) | |
47356eb6 | 488 | { |
752aa88a | 489 | struct drm_device *dev = connector->base.dev; |
47356eb6 | 490 | struct drm_i915_private *dev_priv = dev->dev_private; |
58c68779 | 491 | struct intel_panel *panel = &connector->panel; |
752aa88a | 492 | enum pipe pipe = intel_get_pipe_from_connector(connector); |
d6540632 | 493 | u32 freq; |
8ba2d185 JN |
494 | unsigned long flags; |
495 | ||
dc5a4363 | 496 | if (!panel->backlight.present || pipe == INVALID_PIPE) |
752aa88a JB |
497 | return; |
498 | ||
58c68779 | 499 | spin_lock_irqsave(&dev_priv->backlight_lock, flags); |
d6540632 | 500 | |
f91c15e0 | 501 | WARN_ON(panel->backlight.max == 0); |
d6540632 | 502 | |
f91c15e0 JN |
503 | /* scale to hardware max, but be careful to not overflow */ |
504 | freq = panel->backlight.max; | |
22505b82 AL |
505 | if (freq < max) |
506 | level = level * freq / max; | |
507 | else | |
508 | level = freq / max * level; | |
47356eb6 | 509 | |
58c68779 JN |
510 | panel->backlight.level = level; |
511 | if (panel->backlight.device) | |
512 | panel->backlight.device->props.brightness = level; | |
b6b3ba5b | 513 | |
58c68779 | 514 | if (panel->backlight.enabled) |
7bd688cd | 515 | intel_panel_actually_set_backlight(connector, level); |
f91c15e0 | 516 | |
58c68779 | 517 | spin_unlock_irqrestore(&dev_priv->backlight_lock, flags); |
f52c619a TI |
518 | } |
519 | ||
7bd688cd JN |
520 | static void pch_disable_backlight(struct intel_connector *connector) |
521 | { | |
522 | struct drm_device *dev = connector->base.dev; | |
523 | struct drm_i915_private *dev_priv = dev->dev_private; | |
524 | u32 tmp; | |
525 | ||
3bd712e5 JN |
526 | intel_panel_actually_set_backlight(connector, 0); |
527 | ||
7bd688cd JN |
528 | tmp = I915_READ(BLC_PWM_CPU_CTL2); |
529 | I915_WRITE(BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE); | |
530 | ||
531 | tmp = I915_READ(BLC_PWM_PCH_CTL1); | |
532 | I915_WRITE(BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE); | |
533 | } | |
534 | ||
3bd712e5 JN |
535 | static void i9xx_disable_backlight(struct intel_connector *connector) |
536 | { | |
537 | intel_panel_actually_set_backlight(connector, 0); | |
538 | } | |
539 | ||
7bd688cd JN |
540 | static void i965_disable_backlight(struct intel_connector *connector) |
541 | { | |
542 | struct drm_device *dev = connector->base.dev; | |
543 | struct drm_i915_private *dev_priv = dev->dev_private; | |
544 | u32 tmp; | |
545 | ||
3bd712e5 JN |
546 | intel_panel_actually_set_backlight(connector, 0); |
547 | ||
7bd688cd JN |
548 | tmp = I915_READ(BLC_PWM_CTL2); |
549 | I915_WRITE(BLC_PWM_CTL2, tmp & ~BLM_PWM_ENABLE); | |
550 | } | |
551 | ||
552 | static void vlv_disable_backlight(struct intel_connector *connector) | |
553 | { | |
554 | struct drm_device *dev = connector->base.dev; | |
555 | struct drm_i915_private *dev_priv = dev->dev_private; | |
556 | enum pipe pipe = intel_get_pipe_from_connector(connector); | |
557 | u32 tmp; | |
558 | ||
3bd712e5 JN |
559 | intel_panel_actually_set_backlight(connector, 0); |
560 | ||
7bd688cd JN |
561 | tmp = I915_READ(VLV_BLC_PWM_CTL2(pipe)); |
562 | I915_WRITE(VLV_BLC_PWM_CTL2(pipe), tmp & ~BLM_PWM_ENABLE); | |
563 | } | |
564 | ||
752aa88a | 565 | void intel_panel_disable_backlight(struct intel_connector *connector) |
f52c619a | 566 | { |
752aa88a | 567 | struct drm_device *dev = connector->base.dev; |
f52c619a | 568 | struct drm_i915_private *dev_priv = dev->dev_private; |
58c68779 | 569 | struct intel_panel *panel = &connector->panel; |
752aa88a | 570 | enum pipe pipe = intel_get_pipe_from_connector(connector); |
8ba2d185 JN |
571 | unsigned long flags; |
572 | ||
dc5a4363 | 573 | if (!panel->backlight.present || pipe == INVALID_PIPE) |
752aa88a JB |
574 | return; |
575 | ||
3f577573 JN |
576 | /* |
577 | * Do not disable backlight on the vgaswitcheroo path. When switching | |
578 | * away from i915, the other client may depend on i915 to handle the | |
579 | * backlight. This will leave the backlight on unnecessarily when | |
580 | * another client is not activated. | |
581 | */ | |
582 | if (dev->switch_power_state == DRM_SWITCH_POWER_CHANGING) { | |
583 | DRM_DEBUG_DRIVER("Skipping backlight disable on vga switch\n"); | |
584 | return; | |
585 | } | |
586 | ||
58c68779 | 587 | spin_lock_irqsave(&dev_priv->backlight_lock, flags); |
47356eb6 | 588 | |
58c68779 | 589 | panel->backlight.enabled = false; |
3bd712e5 | 590 | dev_priv->display.disable_backlight(connector); |
24ded204 | 591 | |
7bd688cd JN |
592 | spin_unlock_irqrestore(&dev_priv->backlight_lock, flags); |
593 | } | |
24ded204 | 594 | |
96ab4c70 DV |
595 | static void bdw_enable_backlight(struct intel_connector *connector) |
596 | { | |
597 | struct drm_device *dev = connector->base.dev; | |
598 | struct drm_i915_private *dev_priv = dev->dev_private; | |
599 | struct intel_panel *panel = &connector->panel; | |
600 | u32 pch_ctl1, pch_ctl2; | |
601 | ||
602 | pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1); | |
603 | if (pch_ctl1 & BLM_PCH_PWM_ENABLE) { | |
604 | DRM_DEBUG_KMS("pch backlight already enabled\n"); | |
605 | pch_ctl1 &= ~BLM_PCH_PWM_ENABLE; | |
606 | I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1); | |
607 | } | |
24ded204 | 608 | |
96ab4c70 DV |
609 | pch_ctl2 = panel->backlight.max << 16; |
610 | I915_WRITE(BLC_PWM_PCH_CTL2, pch_ctl2); | |
a4f32fc3 | 611 | |
96ab4c70 DV |
612 | pch_ctl1 = 0; |
613 | if (panel->backlight.active_low_pwm) | |
614 | pch_ctl1 |= BLM_PCH_POLARITY; | |
8ba2d185 | 615 | |
96ab4c70 DV |
616 | /* BDW always uses the pch pwm controls. */ |
617 | pch_ctl1 |= BLM_PCH_OVERRIDE_ENABLE; | |
618 | ||
619 | I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1); | |
620 | POSTING_READ(BLC_PWM_PCH_CTL1); | |
621 | I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_PWM_ENABLE); | |
622 | ||
623 | /* This won't stick until the above enable. */ | |
624 | intel_panel_actually_set_backlight(connector, panel->backlight.level); | |
47356eb6 CW |
625 | } |
626 | ||
7bd688cd JN |
627 | static void pch_enable_backlight(struct intel_connector *connector) |
628 | { | |
629 | struct drm_device *dev = connector->base.dev; | |
630 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3bd712e5 | 631 | struct intel_panel *panel = &connector->panel; |
7bd688cd JN |
632 | enum pipe pipe = intel_get_pipe_from_connector(connector); |
633 | enum transcoder cpu_transcoder = | |
634 | intel_pipe_to_cpu_transcoder(dev_priv, pipe); | |
b35684b8 | 635 | u32 cpu_ctl2, pch_ctl1, pch_ctl2; |
7bd688cd | 636 | |
b35684b8 JN |
637 | cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2); |
638 | if (cpu_ctl2 & BLM_PWM_ENABLE) { | |
639 | WARN(1, "cpu backlight already enabled\n"); | |
640 | cpu_ctl2 &= ~BLM_PWM_ENABLE; | |
641 | I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2); | |
642 | } | |
7bd688cd | 643 | |
b35684b8 JN |
644 | pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1); |
645 | if (pch_ctl1 & BLM_PCH_PWM_ENABLE) { | |
646 | DRM_DEBUG_KMS("pch backlight already enabled\n"); | |
647 | pch_ctl1 &= ~BLM_PCH_PWM_ENABLE; | |
648 | I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1); | |
649 | } | |
7bd688cd JN |
650 | |
651 | if (cpu_transcoder == TRANSCODER_EDP) | |
b35684b8 | 652 | cpu_ctl2 = BLM_TRANSCODER_EDP; |
7bd688cd | 653 | else |
b35684b8 JN |
654 | cpu_ctl2 = BLM_PIPE(cpu_transcoder); |
655 | I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2); | |
7bd688cd | 656 | POSTING_READ(BLC_PWM_CPU_CTL2); |
b35684b8 | 657 | I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2 | BLM_PWM_ENABLE); |
3bd712e5 | 658 | |
b35684b8 | 659 | /* This won't stick until the above enable. */ |
3bd712e5 | 660 | intel_panel_actually_set_backlight(connector, panel->backlight.level); |
b35684b8 JN |
661 | |
662 | pch_ctl2 = panel->backlight.max << 16; | |
663 | I915_WRITE(BLC_PWM_PCH_CTL2, pch_ctl2); | |
664 | ||
b35684b8 JN |
665 | pch_ctl1 = 0; |
666 | if (panel->backlight.active_low_pwm) | |
667 | pch_ctl1 |= BLM_PCH_POLARITY; | |
96ab4c70 | 668 | |
b35684b8 JN |
669 | I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1); |
670 | POSTING_READ(BLC_PWM_PCH_CTL1); | |
671 | I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_PWM_ENABLE); | |
3bd712e5 JN |
672 | } |
673 | ||
674 | static void i9xx_enable_backlight(struct intel_connector *connector) | |
675 | { | |
b35684b8 JN |
676 | struct drm_device *dev = connector->base.dev; |
677 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3bd712e5 | 678 | struct intel_panel *panel = &connector->panel; |
b35684b8 JN |
679 | u32 ctl, freq; |
680 | ||
681 | ctl = I915_READ(BLC_PWM_CTL); | |
682 | if (ctl & BACKLIGHT_DUTY_CYCLE_MASK_PNV) { | |
683 | WARN(1, "backlight already enabled\n"); | |
684 | I915_WRITE(BLC_PWM_CTL, 0); | |
685 | } | |
3bd712e5 | 686 | |
b35684b8 JN |
687 | freq = panel->backlight.max; |
688 | if (panel->backlight.combination_mode) | |
689 | freq /= 0xff; | |
690 | ||
691 | ctl = freq << 17; | |
692 | if (IS_GEN2(dev) && panel->backlight.combination_mode) | |
693 | ctl |= BLM_LEGACY_MODE; | |
694 | if (IS_PINEVIEW(dev) && panel->backlight.active_low_pwm) | |
695 | ctl |= BLM_POLARITY_PNV; | |
696 | ||
697 | I915_WRITE(BLC_PWM_CTL, ctl); | |
698 | POSTING_READ(BLC_PWM_CTL); | |
699 | ||
700 | /* XXX: combine this into above write? */ | |
3bd712e5 | 701 | intel_panel_actually_set_backlight(connector, panel->backlight.level); |
7bd688cd | 702 | } |
8ba2d185 | 703 | |
7bd688cd JN |
704 | static void i965_enable_backlight(struct intel_connector *connector) |
705 | { | |
706 | struct drm_device *dev = connector->base.dev; | |
707 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3bd712e5 | 708 | struct intel_panel *panel = &connector->panel; |
7bd688cd | 709 | enum pipe pipe = intel_get_pipe_from_connector(connector); |
b35684b8 | 710 | u32 ctl, ctl2, freq; |
7bd688cd | 711 | |
b35684b8 JN |
712 | ctl2 = I915_READ(BLC_PWM_CTL2); |
713 | if (ctl2 & BLM_PWM_ENABLE) { | |
714 | WARN(1, "backlight already enabled\n"); | |
715 | ctl2 &= ~BLM_PWM_ENABLE; | |
716 | I915_WRITE(BLC_PWM_CTL2, ctl2); | |
717 | } | |
7bd688cd | 718 | |
b35684b8 JN |
719 | freq = panel->backlight.max; |
720 | if (panel->backlight.combination_mode) | |
721 | freq /= 0xff; | |
7bd688cd | 722 | |
b35684b8 JN |
723 | ctl = freq << 16; |
724 | I915_WRITE(BLC_PWM_CTL, ctl); | |
3bd712e5 | 725 | |
b35684b8 | 726 | /* XXX: combine this into above write? */ |
3bd712e5 | 727 | intel_panel_actually_set_backlight(connector, panel->backlight.level); |
b35684b8 JN |
728 | |
729 | ctl2 = BLM_PIPE(pipe); | |
730 | if (panel->backlight.combination_mode) | |
731 | ctl2 |= BLM_COMBINATION_MODE; | |
732 | if (panel->backlight.active_low_pwm) | |
733 | ctl2 |= BLM_POLARITY_I965; | |
734 | I915_WRITE(BLC_PWM_CTL2, ctl2); | |
735 | POSTING_READ(BLC_PWM_CTL2); | |
736 | I915_WRITE(BLC_PWM_CTL2, ctl2 | BLM_PWM_ENABLE); | |
7bd688cd JN |
737 | } |
738 | ||
739 | static void vlv_enable_backlight(struct intel_connector *connector) | |
740 | { | |
741 | struct drm_device *dev = connector->base.dev; | |
742 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3bd712e5 | 743 | struct intel_panel *panel = &connector->panel; |
7bd688cd | 744 | enum pipe pipe = intel_get_pipe_from_connector(connector); |
b35684b8 | 745 | u32 ctl, ctl2; |
7bd688cd | 746 | |
b35684b8 JN |
747 | ctl2 = I915_READ(VLV_BLC_PWM_CTL2(pipe)); |
748 | if (ctl2 & BLM_PWM_ENABLE) { | |
749 | WARN(1, "backlight already enabled\n"); | |
750 | ctl2 &= ~BLM_PWM_ENABLE; | |
751 | I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2); | |
752 | } | |
7bd688cd | 753 | |
b35684b8 JN |
754 | ctl = panel->backlight.max << 16; |
755 | I915_WRITE(VLV_BLC_PWM_CTL(pipe), ctl); | |
7bd688cd | 756 | |
b35684b8 JN |
757 | /* XXX: combine this into above write? */ |
758 | intel_panel_actually_set_backlight(connector, panel->backlight.level); | |
7bd688cd | 759 | |
b35684b8 JN |
760 | ctl2 = 0; |
761 | if (panel->backlight.active_low_pwm) | |
762 | ctl2 |= BLM_POLARITY_I965; | |
763 | I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2); | |
7bd688cd | 764 | POSTING_READ(VLV_BLC_PWM_CTL2(pipe)); |
b35684b8 | 765 | I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2 | BLM_PWM_ENABLE); |
47356eb6 CW |
766 | } |
767 | ||
752aa88a | 768 | void intel_panel_enable_backlight(struct intel_connector *connector) |
47356eb6 | 769 | { |
752aa88a | 770 | struct drm_device *dev = connector->base.dev; |
47356eb6 | 771 | struct drm_i915_private *dev_priv = dev->dev_private; |
58c68779 | 772 | struct intel_panel *panel = &connector->panel; |
752aa88a | 773 | enum pipe pipe = intel_get_pipe_from_connector(connector); |
8ba2d185 JN |
774 | unsigned long flags; |
775 | ||
dc5a4363 | 776 | if (!panel->backlight.present || pipe == INVALID_PIPE) |
752aa88a JB |
777 | return; |
778 | ||
6f2bcceb | 779 | DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe)); |
540b5d02 | 780 | |
58c68779 | 781 | spin_lock_irqsave(&dev_priv->backlight_lock, flags); |
47356eb6 | 782 | |
f91c15e0 JN |
783 | WARN_ON(panel->backlight.max == 0); |
784 | ||
58c68779 | 785 | if (panel->backlight.level == 0) { |
f91c15e0 | 786 | panel->backlight.level = panel->backlight.max; |
58c68779 JN |
787 | if (panel->backlight.device) |
788 | panel->backlight.device->props.brightness = | |
789 | panel->backlight.level; | |
b6b3ba5b | 790 | } |
47356eb6 | 791 | |
3bd712e5 | 792 | dev_priv->display.enable_backlight(connector); |
58c68779 | 793 | panel->backlight.enabled = true; |
8ba2d185 | 794 | |
58c68779 | 795 | spin_unlock_irqrestore(&dev_priv->backlight_lock, flags); |
47356eb6 CW |
796 | } |
797 | ||
fe16d949 CW |
798 | enum drm_connector_status |
799 | intel_panel_detect(struct drm_device *dev) | |
800 | { | |
801 | struct drm_i915_private *dev_priv = dev->dev_private; | |
802 | ||
803 | /* Assume that the BIOS does not lie through the OpRegion... */ | |
d330a953 | 804 | if (!i915.panel_ignore_lid && dev_priv->opregion.lid_state) { |
fe16d949 CW |
805 | return ioread32(dev_priv->opregion.lid_state) & 0x1 ? |
806 | connector_status_connected : | |
807 | connector_status_disconnected; | |
a726915c | 808 | } |
fe16d949 | 809 | |
d330a953 | 810 | switch (i915.panel_ignore_lid) { |
a726915c DV |
811 | case -2: |
812 | return connector_status_connected; | |
813 | case -1: | |
814 | return connector_status_disconnected; | |
815 | default: | |
816 | return connector_status_unknown; | |
817 | } | |
fe16d949 | 818 | } |
aaa6fd2a | 819 | |
912e8b12 | 820 | #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE) |
db31af1d | 821 | static int intel_backlight_device_update_status(struct backlight_device *bd) |
aaa6fd2a | 822 | { |
752aa88a JB |
823 | struct intel_connector *connector = bl_get_data(bd); |
824 | struct drm_device *dev = connector->base.dev; | |
825 | ||
826 | mutex_lock(&dev->mode_config.mutex); | |
540b5d02 CW |
827 | DRM_DEBUG_KMS("updating intel_backlight, brightness=%d/%d\n", |
828 | bd->props.brightness, bd->props.max_brightness); | |
752aa88a | 829 | intel_panel_set_backlight(connector, bd->props.brightness, |
d6540632 | 830 | bd->props.max_brightness); |
752aa88a | 831 | mutex_unlock(&dev->mode_config.mutex); |
aaa6fd2a MG |
832 | return 0; |
833 | } | |
834 | ||
db31af1d | 835 | static int intel_backlight_device_get_brightness(struct backlight_device *bd) |
aaa6fd2a | 836 | { |
752aa88a JB |
837 | struct intel_connector *connector = bl_get_data(bd); |
838 | struct drm_device *dev = connector->base.dev; | |
c8c8fb33 | 839 | struct drm_i915_private *dev_priv = dev->dev_private; |
7bd688cd | 840 | int ret; |
752aa88a | 841 | |
c8c8fb33 | 842 | intel_runtime_pm_get(dev_priv); |
752aa88a | 843 | mutex_lock(&dev->mode_config.mutex); |
7bd688cd | 844 | ret = intel_panel_get_backlight(connector); |
752aa88a | 845 | mutex_unlock(&dev->mode_config.mutex); |
c8c8fb33 | 846 | intel_runtime_pm_put(dev_priv); |
752aa88a | 847 | |
7bd688cd | 848 | return ret; |
aaa6fd2a MG |
849 | } |
850 | ||
db31af1d JN |
851 | static const struct backlight_ops intel_backlight_device_ops = { |
852 | .update_status = intel_backlight_device_update_status, | |
853 | .get_brightness = intel_backlight_device_get_brightness, | |
aaa6fd2a MG |
854 | }; |
855 | ||
db31af1d | 856 | static int intel_backlight_device_register(struct intel_connector *connector) |
aaa6fd2a | 857 | { |
58c68779 | 858 | struct intel_panel *panel = &connector->panel; |
aaa6fd2a | 859 | struct backlight_properties props; |
aaa6fd2a | 860 | |
58c68779 | 861 | if (WARN_ON(panel->backlight.device)) |
dc652f90 JN |
862 | return -ENODEV; |
863 | ||
7bd688cd JN |
864 | BUG_ON(panel->backlight.max == 0); |
865 | ||
af437cfd | 866 | memset(&props, 0, sizeof(props)); |
aaa6fd2a | 867 | props.type = BACKLIGHT_RAW; |
58c68779 | 868 | props.brightness = panel->backlight.level; |
7bd688cd | 869 | props.max_brightness = panel->backlight.max; |
58c68779 JN |
870 | |
871 | /* | |
872 | * Note: using the same name independent of the connector prevents | |
873 | * registration of multiple backlight devices in the driver. | |
874 | */ | |
875 | panel->backlight.device = | |
aaa6fd2a | 876 | backlight_device_register("intel_backlight", |
db31af1d JN |
877 | connector->base.kdev, |
878 | connector, | |
879 | &intel_backlight_device_ops, &props); | |
aaa6fd2a | 880 | |
58c68779 | 881 | if (IS_ERR(panel->backlight.device)) { |
aaa6fd2a | 882 | DRM_ERROR("Failed to register backlight: %ld\n", |
58c68779 JN |
883 | PTR_ERR(panel->backlight.device)); |
884 | panel->backlight.device = NULL; | |
aaa6fd2a MG |
885 | return -ENODEV; |
886 | } | |
aaa6fd2a MG |
887 | return 0; |
888 | } | |
889 | ||
db31af1d | 890 | static void intel_backlight_device_unregister(struct intel_connector *connector) |
aaa6fd2a | 891 | { |
58c68779 JN |
892 | struct intel_panel *panel = &connector->panel; |
893 | ||
894 | if (panel->backlight.device) { | |
895 | backlight_device_unregister(panel->backlight.device); | |
896 | panel->backlight.device = NULL; | |
dc652f90 | 897 | } |
aaa6fd2a | 898 | } |
db31af1d JN |
899 | #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */ |
900 | static int intel_backlight_device_register(struct intel_connector *connector) | |
901 | { | |
902 | return 0; | |
903 | } | |
904 | static void intel_backlight_device_unregister(struct intel_connector *connector) | |
905 | { | |
906 | } | |
907 | #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */ | |
908 | ||
f91c15e0 JN |
909 | /* |
910 | * Note: The setup hooks can't assume pipe is set! | |
911 | * | |
912 | * XXX: Query mode clock or hardware clock and program PWM modulation frequency | |
913 | * appropriately when it's 0. Use VBT and/or sane defaults. | |
914 | */ | |
96ab4c70 | 915 | static int bdw_setup_backlight(struct intel_connector *connector) |
aaa6fd2a | 916 | { |
96ab4c70 | 917 | struct drm_device *dev = connector->base.dev; |
aaa6fd2a | 918 | struct drm_i915_private *dev_priv = dev->dev_private; |
96ab4c70 DV |
919 | struct intel_panel *panel = &connector->panel; |
920 | u32 pch_ctl1, pch_ctl2, val; | |
921 | ||
922 | pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1); | |
923 | panel->backlight.active_low_pwm = pch_ctl1 & BLM_PCH_POLARITY; | |
924 | ||
925 | pch_ctl2 = I915_READ(BLC_PWM_PCH_CTL2); | |
926 | panel->backlight.max = pch_ctl2 >> 16; | |
927 | if (!panel->backlight.max) | |
928 | return -ENODEV; | |
929 | ||
930 | val = bdw_get_backlight(connector); | |
931 | panel->backlight.level = intel_panel_compute_brightness(connector, val); | |
932 | ||
933 | panel->backlight.enabled = (pch_ctl1 & BLM_PCH_PWM_ENABLE) && | |
934 | panel->backlight.level != 0; | |
935 | ||
936 | return 0; | |
937 | } | |
938 | ||
7bd688cd JN |
939 | static int pch_setup_backlight(struct intel_connector *connector) |
940 | { | |
636baebf JN |
941 | struct drm_device *dev = connector->base.dev; |
942 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7bd688cd | 943 | struct intel_panel *panel = &connector->panel; |
636baebf | 944 | u32 cpu_ctl2, pch_ctl1, pch_ctl2, val; |
7bd688cd | 945 | |
636baebf JN |
946 | pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1); |
947 | panel->backlight.active_low_pwm = pch_ctl1 & BLM_PCH_POLARITY; | |
948 | ||
949 | pch_ctl2 = I915_READ(BLC_PWM_PCH_CTL2); | |
950 | panel->backlight.max = pch_ctl2 >> 16; | |
7bd688cd JN |
951 | if (!panel->backlight.max) |
952 | return -ENODEV; | |
953 | ||
954 | val = pch_get_backlight(connector); | |
955 | panel->backlight.level = intel_panel_compute_brightness(connector, val); | |
956 | ||
636baebf JN |
957 | cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2); |
958 | panel->backlight.enabled = (cpu_ctl2 & BLM_PWM_ENABLE) && | |
959 | (pch_ctl1 & BLM_PCH_PWM_ENABLE) && panel->backlight.level != 0; | |
960 | ||
7bd688cd JN |
961 | return 0; |
962 | } | |
963 | ||
964 | static int i9xx_setup_backlight(struct intel_connector *connector) | |
965 | { | |
636baebf JN |
966 | struct drm_device *dev = connector->base.dev; |
967 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7bd688cd | 968 | struct intel_panel *panel = &connector->panel; |
636baebf JN |
969 | u32 ctl, val; |
970 | ||
971 | ctl = I915_READ(BLC_PWM_CTL); | |
972 | ||
973 | if (IS_GEN2(dev)) | |
974 | panel->backlight.combination_mode = ctl & BLM_LEGACY_MODE; | |
975 | ||
976 | if (IS_PINEVIEW(dev)) | |
977 | panel->backlight.active_low_pwm = ctl & BLM_POLARITY_PNV; | |
978 | ||
979 | panel->backlight.max = ctl >> 17; | |
980 | if (panel->backlight.combination_mode) | |
981 | panel->backlight.max *= 0xff; | |
7bd688cd | 982 | |
7bd688cd JN |
983 | if (!panel->backlight.max) |
984 | return -ENODEV; | |
985 | ||
986 | val = i9xx_get_backlight(connector); | |
987 | panel->backlight.level = intel_panel_compute_brightness(connector, val); | |
988 | ||
636baebf JN |
989 | panel->backlight.enabled = panel->backlight.level != 0; |
990 | ||
7bd688cd JN |
991 | return 0; |
992 | } | |
993 | ||
994 | static int i965_setup_backlight(struct intel_connector *connector) | |
995 | { | |
636baebf JN |
996 | struct drm_device *dev = connector->base.dev; |
997 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7bd688cd | 998 | struct intel_panel *panel = &connector->panel; |
636baebf JN |
999 | u32 ctl, ctl2, val; |
1000 | ||
1001 | ctl2 = I915_READ(BLC_PWM_CTL2); | |
1002 | panel->backlight.combination_mode = ctl2 & BLM_COMBINATION_MODE; | |
1003 | panel->backlight.active_low_pwm = ctl2 & BLM_POLARITY_I965; | |
1004 | ||
1005 | ctl = I915_READ(BLC_PWM_CTL); | |
1006 | panel->backlight.max = ctl >> 16; | |
1007 | if (panel->backlight.combination_mode) | |
1008 | panel->backlight.max *= 0xff; | |
7bd688cd | 1009 | |
7bd688cd JN |
1010 | if (!panel->backlight.max) |
1011 | return -ENODEV; | |
1012 | ||
1013 | val = i9xx_get_backlight(connector); | |
1014 | panel->backlight.level = intel_panel_compute_brightness(connector, val); | |
1015 | ||
636baebf JN |
1016 | panel->backlight.enabled = (ctl2 & BLM_PWM_ENABLE) && |
1017 | panel->backlight.level != 0; | |
1018 | ||
7bd688cd JN |
1019 | return 0; |
1020 | } | |
1021 | ||
1022 | static int vlv_setup_backlight(struct intel_connector *connector) | |
1023 | { | |
1024 | struct drm_device *dev = connector->base.dev; | |
1025 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1026 | struct intel_panel *panel = &connector->panel; | |
1027 | enum pipe pipe; | |
636baebf | 1028 | u32 ctl, ctl2, val; |
7bd688cd JN |
1029 | |
1030 | for_each_pipe(pipe) { | |
1031 | u32 cur_val = I915_READ(VLV_BLC_PWM_CTL(pipe)); | |
1032 | ||
1033 | /* Skip if the modulation freq is already set */ | |
1034 | if (cur_val & ~BACKLIGHT_DUTY_CYCLE_MASK) | |
1035 | continue; | |
1036 | ||
1037 | cur_val &= BACKLIGHT_DUTY_CYCLE_MASK; | |
1038 | I915_WRITE(VLV_BLC_PWM_CTL(pipe), (0xf42 << 16) | | |
1039 | cur_val); | |
1040 | } | |
1041 | ||
636baebf JN |
1042 | ctl2 = I915_READ(VLV_BLC_PWM_CTL2(PIPE_A)); |
1043 | panel->backlight.active_low_pwm = ctl2 & BLM_POLARITY_I965; | |
1044 | ||
1045 | ctl = I915_READ(VLV_BLC_PWM_CTL(PIPE_A)); | |
1046 | panel->backlight.max = ctl >> 16; | |
7bd688cd JN |
1047 | if (!panel->backlight.max) |
1048 | return -ENODEV; | |
1049 | ||
1050 | val = _vlv_get_backlight(dev, PIPE_A); | |
1051 | panel->backlight.level = intel_panel_compute_brightness(connector, val); | |
1052 | ||
636baebf JN |
1053 | panel->backlight.enabled = (ctl2 & BLM_PWM_ENABLE) && |
1054 | panel->backlight.level != 0; | |
1055 | ||
7bd688cd JN |
1056 | return 0; |
1057 | } | |
1058 | ||
0657b6b1 | 1059 | int intel_panel_setup_backlight(struct drm_connector *connector) |
aaa6fd2a | 1060 | { |
db31af1d | 1061 | struct drm_device *dev = connector->dev; |
7bd688cd | 1062 | struct drm_i915_private *dev_priv = dev->dev_private; |
db31af1d | 1063 | struct intel_connector *intel_connector = to_intel_connector(connector); |
58c68779 | 1064 | struct intel_panel *panel = &intel_connector->panel; |
7bd688cd JN |
1065 | unsigned long flags; |
1066 | int ret; | |
db31af1d | 1067 | |
7bd688cd JN |
1068 | /* set level and max in panel struct */ |
1069 | spin_lock_irqsave(&dev_priv->backlight_lock, flags); | |
1070 | ret = dev_priv->display.setup_backlight(intel_connector); | |
1071 | spin_unlock_irqrestore(&dev_priv->backlight_lock, flags); | |
1072 | ||
1073 | if (ret) { | |
1074 | DRM_DEBUG_KMS("failed to setup backlight for connector %s\n", | |
1075 | drm_get_connector_name(connector)); | |
1076 | return ret; | |
1077 | } | |
db31af1d | 1078 | |
db31af1d JN |
1079 | intel_backlight_device_register(intel_connector); |
1080 | ||
c91c9f32 JN |
1081 | panel->backlight.present = true; |
1082 | ||
c445b3b1 JN |
1083 | DRM_DEBUG_KMS("backlight initialized, %s, brightness %u/%u, " |
1084 | "sysfs interface %sregistered\n", | |
1085 | panel->backlight.enabled ? "enabled" : "disabled", | |
1086 | panel->backlight.level, panel->backlight.max, | |
1087 | panel->backlight.device ? "" : "not "); | |
1088 | ||
aaa6fd2a MG |
1089 | return 0; |
1090 | } | |
1091 | ||
db31af1d | 1092 | void intel_panel_destroy_backlight(struct drm_connector *connector) |
aaa6fd2a | 1093 | { |
db31af1d | 1094 | struct intel_connector *intel_connector = to_intel_connector(connector); |
c91c9f32 | 1095 | struct intel_panel *panel = &intel_connector->panel; |
db31af1d | 1096 | |
c91c9f32 | 1097 | panel->backlight.present = false; |
db31af1d | 1098 | intel_backlight_device_unregister(intel_connector); |
aaa6fd2a | 1099 | } |
1d508706 | 1100 | |
ec9ed197 VK |
1101 | /** |
1102 | * intel_find_panel_downclock - find the reduced downclock for LVDS in EDID | |
1103 | * @dev: drm device | |
1104 | * @fixed_mode : panel native mode | |
1105 | * @connector: LVDS/eDP connector | |
1106 | * | |
1107 | * Return downclock_avail | |
1108 | * Find the reduced downclock for LVDS/eDP in EDID. | |
1109 | */ | |
1110 | struct drm_display_mode * | |
1111 | intel_find_panel_downclock(struct drm_device *dev, | |
1112 | struct drm_display_mode *fixed_mode, | |
1113 | struct drm_connector *connector) | |
1114 | { | |
1115 | struct drm_display_mode *scan, *tmp_mode; | |
1116 | int temp_downclock; | |
1117 | ||
1118 | temp_downclock = fixed_mode->clock; | |
1119 | tmp_mode = NULL; | |
1120 | ||
1121 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
1122 | /* | |
1123 | * If one mode has the same resolution with the fixed_panel | |
1124 | * mode while they have the different refresh rate, it means | |
1125 | * that the reduced downclock is found. In such | |
1126 | * case we can set the different FPx0/1 to dynamically select | |
1127 | * between low and high frequency. | |
1128 | */ | |
1129 | if (scan->hdisplay == fixed_mode->hdisplay && | |
1130 | scan->hsync_start == fixed_mode->hsync_start && | |
1131 | scan->hsync_end == fixed_mode->hsync_end && | |
1132 | scan->htotal == fixed_mode->htotal && | |
1133 | scan->vdisplay == fixed_mode->vdisplay && | |
1134 | scan->vsync_start == fixed_mode->vsync_start && | |
1135 | scan->vsync_end == fixed_mode->vsync_end && | |
1136 | scan->vtotal == fixed_mode->vtotal) { | |
1137 | if (scan->clock < temp_downclock) { | |
1138 | /* | |
1139 | * The downclock is already found. But we | |
1140 | * expect to find the lower downclock. | |
1141 | */ | |
1142 | temp_downclock = scan->clock; | |
1143 | tmp_mode = scan; | |
1144 | } | |
1145 | } | |
1146 | } | |
1147 | ||
1148 | if (temp_downclock < fixed_mode->clock) | |
1149 | return drm_mode_duplicate(dev, tmp_mode); | |
1150 | else | |
1151 | return NULL; | |
1152 | } | |
1153 | ||
7bd688cd JN |
1154 | /* Set up chip specific backlight functions */ |
1155 | void intel_panel_init_backlight_funcs(struct drm_device *dev) | |
1156 | { | |
1157 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1158 | ||
96ab4c70 DV |
1159 | if (IS_BROADWELL(dev)) { |
1160 | dev_priv->display.setup_backlight = bdw_setup_backlight; | |
1161 | dev_priv->display.enable_backlight = bdw_enable_backlight; | |
1162 | dev_priv->display.disable_backlight = pch_disable_backlight; | |
1163 | dev_priv->display.set_backlight = bdw_set_backlight; | |
1164 | dev_priv->display.get_backlight = bdw_get_backlight; | |
1165 | } else if (HAS_PCH_SPLIT(dev)) { | |
7bd688cd JN |
1166 | dev_priv->display.setup_backlight = pch_setup_backlight; |
1167 | dev_priv->display.enable_backlight = pch_enable_backlight; | |
1168 | dev_priv->display.disable_backlight = pch_disable_backlight; | |
1169 | dev_priv->display.set_backlight = pch_set_backlight; | |
1170 | dev_priv->display.get_backlight = pch_get_backlight; | |
7bd688cd JN |
1171 | } else if (IS_VALLEYVIEW(dev)) { |
1172 | dev_priv->display.setup_backlight = vlv_setup_backlight; | |
1173 | dev_priv->display.enable_backlight = vlv_enable_backlight; | |
1174 | dev_priv->display.disable_backlight = vlv_disable_backlight; | |
1175 | dev_priv->display.set_backlight = vlv_set_backlight; | |
1176 | dev_priv->display.get_backlight = vlv_get_backlight; | |
7bd688cd JN |
1177 | } else if (IS_GEN4(dev)) { |
1178 | dev_priv->display.setup_backlight = i965_setup_backlight; | |
1179 | dev_priv->display.enable_backlight = i965_enable_backlight; | |
1180 | dev_priv->display.disable_backlight = i965_disable_backlight; | |
1181 | dev_priv->display.set_backlight = i9xx_set_backlight; | |
1182 | dev_priv->display.get_backlight = i9xx_get_backlight; | |
7bd688cd JN |
1183 | } else { |
1184 | dev_priv->display.setup_backlight = i9xx_setup_backlight; | |
3bd712e5 JN |
1185 | dev_priv->display.enable_backlight = i9xx_enable_backlight; |
1186 | dev_priv->display.disable_backlight = i9xx_disable_backlight; | |
7bd688cd JN |
1187 | dev_priv->display.set_backlight = i9xx_set_backlight; |
1188 | dev_priv->display.get_backlight = i9xx_get_backlight; | |
7bd688cd JN |
1189 | } |
1190 | } | |
1191 | ||
dd06f90e JN |
1192 | int intel_panel_init(struct intel_panel *panel, |
1193 | struct drm_display_mode *fixed_mode) | |
1d508706 | 1194 | { |
dd06f90e JN |
1195 | panel->fixed_mode = fixed_mode; |
1196 | ||
1d508706 JN |
1197 | return 0; |
1198 | } | |
1199 | ||
1200 | void intel_panel_fini(struct intel_panel *panel) | |
1201 | { | |
dd06f90e JN |
1202 | struct intel_connector *intel_connector = |
1203 | container_of(panel, struct intel_connector, panel); | |
1204 | ||
1205 | if (panel->fixed_mode) | |
1206 | drm_mode_destroy(intel_connector->base.dev, panel->fixed_mode); | |
ec9ed197 VK |
1207 | |
1208 | if (panel->downclock_mode) | |
1209 | drm_mode_destroy(intel_connector->base.dev, | |
1210 | panel->downclock_mode); | |
1d508706 | 1211 | } |