[linux-block.git] / drivers / gpu / drm / i915 / intel_mocs.c

/*
 * Copyright (c) 2015 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions: *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include "intel_mocs.h"
#include "intel_lrc.h"
#include "intel_ringbuffer.h"

/* structures required */
struct drm_i915_mocs_entry {
	u32 control_value;
	u16 l3cc_value;
};

struct drm_i915_mocs_table {
	u32 size;
	const struct drm_i915_mocs_entry *table;
};

/* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
#define LE_CACHEABILITY(value)	((value) << 0)
#define LE_TGT_CACHE(value)	((value) << 2)
#define LE_LRUM(value)		((value) << 4)
#define LE_AOM(value)		((value) << 6)
#define LE_RSC(value)		((value) << 7)
#define LE_SCC(value)		((value) << 8)
#define LE_PFM(value)		((value) << 11)
#define LE_SCF(value)		((value) << 14)

/* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
#define L3_ESC(value)		((value) << 0)
#define L3_SCC(value)		((value) << 1)
#define L3_CACHEABILITY(value)	((value) << 4)

/* Helper defines */
#define GEN9_NUM_MOCS_ENTRIES	62  /* 62 out of 64 - 63 & 64 are reserved. */

/* (e)LLC caching options */
#define LE_PAGETABLE		0
#define LE_UC			1
#define LE_WT			2
#define LE_WB			3

/* L3 caching options */
#define L3_DIRECT		0
#define L3_UC			1
#define L3_RESERVED		2
#define L3_WB			3

/* Target cache */
#define ELLC			0
#define LLC			1
#define LLC_ELLC		2

/*
 * MOCS tables
 *
 * These are the MOCS tables that are programmed across all the rings.
 * The control value is programmed to all the rings that support the
 * MOCS registers. While the l3cc_values are only programmed to the
 * LNCFCMOCS0 - LNCFCMOCS32 registers.
 *
 * These tables are intended to be kept reasonably consistent across
 * platforms. However some of the fields are not applicable to all of
 * them.
 *
 * Entries not part of the following tables are undefined as far as
 * userspace is concerned and shouldn't be relied upon.  For the time
 * being they will be implicitly initialized to the strictest caching
 * configuration (uncached) to guarantee forwards compatibility with
 * userspace programs written against more recent kernels providing
 * additional MOCS entries.
 *
 * NOTE: These tables MUST start with being uncached and the length
 *       MUST be less than 63 as the last two registers are reserved
 *       by the hardware.  These tables are part of the kernel ABI and
 *       may only be updated incrementally by adding entries at the
 *       end.
 */
static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
	/* { 0x00000009, 0x0010 } */
	{ (LE_CACHEABILITY(LE_UC) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(0) |
	   LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
	  (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC)) },
	/* { 0x00000038, 0x0030 } */
	{ (LE_CACHEABILITY(LE_PAGETABLE) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(3) |
	   LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
	  (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) },
	/* { 0x0000003b, 0x0030 } */
	{ (LE_CACHEABILITY(LE_WB) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(3) |
	   LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
	  (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) }
};

/* NOTE: the LE_TGT_CACHE is not used on Broxton */
static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
	/* { 0x00000009, 0x0010 } */
	{ (LE_CACHEABILITY(LE_UC) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(0) |
	   LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
	  (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC)) },
	/* { 0x00000038, 0x0030 } */
	{ (LE_CACHEABILITY(LE_PAGETABLE) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(3) |
	   LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
	  (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) },
	/* { 0x0000003b, 0x0030 } */
	{ (LE_CACHEABILITY(LE_WB) | LE_TGT_CACHE(LLC_ELLC) | LE_LRUM(3) |
	   LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | LE_PFM(0) | LE_SCF(0)),
	  (L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB)) }
};

/**
 * get_mocs_settings()
 * @dev_priv:	i915 device.
 * @table:      Output table that will be made to point at appropriate
 *	      MOCS values for the device.
 *
 * This function will return the values of the MOCS table that needs to
 * be programmed for the platform. It will return the values that need
 * to be programmed and if they need to be programmed.
 *
 * Return: true if there are applicable MOCS settings for the device.
 */
static bool get_mocs_settings(struct drm_i915_private *dev_priv,
			      struct drm_i915_mocs_table *table)
{
	bool result = false;

	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
		table->size  = ARRAY_SIZE(skylake_mocs_table);
		table->table = skylake_mocs_table;
		result = true;
	} else if (IS_BROXTON(dev_priv)) {
		table->size  = ARRAY_SIZE(broxton_mocs_table);
		table->table = broxton_mocs_table;
		result = true;
	} else {
		WARN_ONCE(INTEL_INFO(dev_priv)->gen >= 9,
			  "Platform that should have a MOCS table does not.\n");
	}

	/* WaDisableSkipCaching:skl,bxt,kbl */
	if (IS_GEN9(dev_priv)) {
		int i;

		for (i = 0; i < table->size; i++)
			if (WARN_ON(table->table[i].l3cc_value &
				    (L3_ESC(1) | L3_SCC(0x7))))
				return false;
	}

	return result;
}

static i915_reg_t mocs_register(enum intel_engine_id ring, int index)
{
	switch (ring) {
	case RCS:
		return GEN9_GFX_MOCS(index);
	case VCS:
		return GEN9_MFX0_MOCS(index);
	case BCS:
		return GEN9_BLT_MOCS(index);
	case VECS:
		return GEN9_VEBOX_MOCS(index);
	case VCS2:
		return GEN9_MFX1_MOCS(index);
	default:
		MISSING_CASE(ring);
		return INVALID_MMIO_REG;
	}
}

/**
 * intel_mocs_init_engine() - emit the mocs control table
 * @engine:	The engine for whom to emit the registers.
 *
 * This function simply emits a MI_LOAD_REGISTER_IMM command for the
 * given table starting at the given address.
 *
 * Return: 0 on success, otherwise the error status.
 */
int intel_mocs_init_engine(struct intel_engine_cs *engine)
{
	struct drm_i915_private *dev_priv = engine->i915;
	struct drm_i915_mocs_table table;
	unsigned int index;

	if (!get_mocs_settings(dev_priv, &table))
		return 0;

	if (WARN_ON(table.size > GEN9_NUM_MOCS_ENTRIES))
		return -ENODEV;

	for (index = 0; index < table.size; index++)
		I915_WRITE(mocs_register(engine->id, index),
			   table.table[index].control_value);

	/*
	 * Ok, now set the unused entries to uncached. These entries
	 * are officially undefined and no contract for the contents
	 * and settings is given for these entries.
	 *
	 * Entry 0 in the table is uncached - so we are just writing
	 * that value to all the used entries.
	 */
	for (; index < GEN9_NUM_MOCS_ENTRIES; index++)
		I915_WRITE(mocs_register(engine->id, index),
			   table.table[0].control_value);

	return 0;
}

/**
 * emit_mocs_control_table() - emit the mocs control table
 * @req:	Request to set up the MOCS table for.
 * @table:	The values to program into the control regs.
 *
 * This function simply emits a MI_LOAD_REGISTER_IMM command for the
 * given table starting at the given address.
 *
 * Return: 0 on success, otherwise the error status.
 */
static int emit_mocs_control_table(struct drm_i915_gem_request *req,
				   const struct drm_i915_mocs_table *table)
{
	struct intel_ringbuffer *ringbuf = req->ringbuf;
	enum intel_engine_id engine = req->engine->id;
	unsigned int index;
	int ret;

	if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES))
		return -ENODEV;

	ret = intel_ring_begin(req, 2 + 2 * GEN9_NUM_MOCS_ENTRIES);
	if (ret)
		return ret;

	intel_logical_ring_emit(ringbuf,
				MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES));

	for (index = 0; index < table->size; index++) {
		intel_logical_ring_emit_reg(ringbuf,
					    mocs_register(engine, index));
		intel_logical_ring_emit(ringbuf,
					table->table[index].control_value);
	}

	/*
	 * Ok, now set the unused entries to uncached. These entries
	 * are officially undefined and no contract for the contents
	 * and settings is given for these entries.
	 *
	 * Entry 0 in the table is uncached - so we are just writing
	 * that value to all the used entries.
	 */
	for (; index < GEN9_NUM_MOCS_ENTRIES; index++) {
		intel_logical_ring_emit_reg(ringbuf,
					    mocs_register(engine, index));
		intel_logical_ring_emit(ringbuf,
					table->table[0].control_value);
	}

	intel_logical_ring_emit(ringbuf, MI_NOOP);
	intel_logical_ring_advance(ringbuf);

	return 0;
}

static inline u32 l3cc_combine(const struct drm_i915_mocs_table *table,
			       u16 low,
			       u16 high)
{
	return table->table[low].l3cc_value |
	       table->table[high].l3cc_value << 16;
}

/**
 * emit_mocs_l3cc_table() - emit the mocs control table
 * @req:	Request to set up the MOCS table for.
 * @table:	The values to program into the control regs.
 *
 * This function simply emits a MI_LOAD_REGISTER_IMM command for the
 * given table starting at the given address. This register set is
 * programmed in pairs.
 *
 * Return: 0 on success, otherwise the error status.
 */
static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req,
				const struct drm_i915_mocs_table *table)
{
	struct intel_ringbuffer *ringbuf = req->ringbuf;
	unsigned int i;
	int ret;

	if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES))
		return -ENODEV;

	ret = intel_ring_begin(req, 2 + GEN9_NUM_MOCS_ENTRIES);
	if (ret)
		return ret;

	intel_logical_ring_emit(ringbuf,
			MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES / 2));

	for (i = 0; i < table->size/2; i++) {
		intel_logical_ring_emit_reg(ringbuf, GEN9_LNCFCMOCS(i));
		intel_logical_ring_emit(ringbuf,
					l3cc_combine(table, 2*i, 2*i+1));
	}

	if (table->size & 0x01) {
		/* Odd table size - 1 left over */
		intel_logical_ring_emit_reg(ringbuf, GEN9_LNCFCMOCS(i));
		intel_logical_ring_emit(ringbuf, l3cc_combine(table, 2*i, 0));
		i++;
	}

	/*
	 * Now set the rest of the table to uncached - use entry 0 as
	 * this will be uncached. Leave the last pair uninitialised as
	 * they are reserved by the hardware.
	 */
	for (; i < GEN9_NUM_MOCS_ENTRIES / 2; i++) {
		intel_logical_ring_emit_reg(ringbuf, GEN9_LNCFCMOCS(i));
		intel_logical_ring_emit(ringbuf, l3cc_combine(table, 0, 0));
	}

	intel_logical_ring_emit(ringbuf, MI_NOOP);
	intel_logical_ring_advance(ringbuf);

	return 0;
}

/**
 * intel_mocs_init_l3cc_table() - program the mocs control table
 * @dev:      The the device to be programmed.
 *
 * This function simply programs the mocs registers for the given table
 * starting at the given address. This register set is  programmed in pairs.
 *
 * These registers may get programmed more than once, it is simpler to
 * re-program 32 registers than maintain the state of when they were programmed.
 * We are always reprogramming with the same values and this only on context
 * start.
 *
 * Return: Nothing.
 */
void intel_mocs_init_l3cc_table(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct drm_i915_mocs_table table;
	unsigned int i;

	if (!get_mocs_settings(dev_priv, &table))
		return;

	for (i = 0; i < table.size/2; i++)
		I915_WRITE(GEN9_LNCFCMOCS(i), l3cc_combine(&table, 2*i, 2*i+1));

	/* Odd table size - 1 left over */
	if (table.size & 0x01) {
		I915_WRITE(GEN9_LNCFCMOCS(i), l3cc_combine(&table, 2*i, 0));
		i++;
	}

	/*
	 * Now set the rest of the table to uncached - use entry 0 as
	 * this will be uncached. Leave the last pair as initialised as
	 * they are reserved by the hardware.
	 */
	for (; i < (GEN9_NUM_MOCS_ENTRIES / 2); i++)
		I915_WRITE(GEN9_LNCFCMOCS(i), l3cc_combine(&table, 0, 0));
}

/**
 * intel_rcs_context_init_mocs() - program the MOCS register.
 * @req:	Request to set up the MOCS tables for.
 *
 * This function will emit a batch buffer with the values required for
 * programming the MOCS register values for all the currently supported
 * rings.
 *
 * These registers are partially stored in the RCS context, so they are
 * emitted at the same time so that when a context is created these registers
 * are set up. These registers have to be emitted into the start of the
 * context as setting the ELSP will re-init some of these registers back
 * to the hw values.
 *
 * Return: 0 on success, otherwise the error status.
 */
int intel_rcs_context_init_mocs(struct drm_i915_gem_request *req)
{
	struct drm_i915_mocs_table t;
	int ret;

	if (get_mocs_settings(req->i915, &t)) {
		/* Program the RCS control registers */
		ret = emit_mocs_control_table(req, &t);
		if (ret)
			return ret;

		/* Now program the l3cc registers */
		ret = emit_mocs_l3cc_table(req, &t);
		if (ret)
			return ret;
	}

	return 0;
}
Commit	Line	Data
3bbaba0c PA	1	/*
	2	* Copyright (c) 2015 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions: *
	10	* The above copyright notice and this permission notice (including the next
	11	* paragraph) shall be included in all copies or substantial portions of the
	12	* Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	18	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	19	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	20	* SOFTWARE.
	21	*/
	22
	23	#include "intel_mocs.h"
	24	#include "intel_lrc.h"
	25	#include "intel_ringbuffer.h"
	26
	27	/* structures required */
	28	struct drm_i915_mocs_entry {
	29	u32 control_value;
	30	u16 l3cc_value;
	31	};
	32
	33	struct drm_i915_mocs_table {
	34	u32 size;
	35	const struct drm_i915_mocs_entry *table;
	36	};
	37
	38	/* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
	39	#define LE_CACHEABILITY(value) ((value) << 0)
	40	#define LE_TGT_CACHE(value) ((value) << 2)
	41	#define LE_LRUM(value) ((value) << 4)
	42	#define LE_AOM(value) ((value) << 6)
	43	#define LE_RSC(value) ((value) << 7)
	44	#define LE_SCC(value) ((value) << 8)
	45	#define LE_PFM(value) ((value) << 11)
	46	#define LE_SCF(value) ((value) << 14)
	47
	48	/* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
	49	#define L3_ESC(value) ((value) << 0)
	50	#define L3_SCC(value) ((value) << 1)
	51	#define L3_CACHEABILITY(value) ((value) << 4)
	52
	53	/* Helper defines */
	54	#define GEN9_NUM_MOCS_ENTRIES 62 /* 62 out of 64 - 63 & 64 are reserved. */
	55
	56	/* (e)LLC caching options */
	57	#define LE_PAGETABLE 0
	58	#define LE_UC 1
	59	#define LE_WT 2
	60	#define LE_WB 3
	61
	62	/* L3 caching options */
	63	#define L3_DIRECT 0
	64	#define L3_UC 1
65	#define L3_RESERVED 2
66	#define L3_WB 3
67
68	/* Target cache */
69	#define ELLC 0
70	#define LLC 1
71	#define LLC_ELLC 2
72
73	/*
74	* MOCS tables
75	*
76	* These are the MOCS tables that are programmed across all the rings.
77	* The control value is programmed to all the rings that support the
78	* MOCS registers. While the l3cc_values are only programmed to the
79	* LNCFCMOCS0 - LNCFCMOCS32 registers.
80	*
81	* These tables are intended to be kept reasonably consistent across
82	* platforms. However some of the fields are not applicable to all of
83	* them.
84	*
85	* Entries not part of the following tables are undefined as far as
86	* userspace is concerned and shouldn't be relied upon. For the time
87	* being they will be implicitly initialized to the strictest caching
88	* configuration (uncached) to guarantee forwards compatibility with
89	* userspace programs written against more recent kernels providing
90	* additional MOCS entries.
91	*
92	* NOTE: These tables MUST start with being uncached and the length
93	* MUST be less than 63 as the last two registers are reserved
94	* by the hardware. These tables are part of the kernel ABI and
95	* may only be updated incrementally by adding entries at the
96	* end.
97	*/
98	static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
99	/* { 0x00000009, 0x0010 } */
100	{ (LE_CACHEABILITY(LE_UC) \| LE_TGT_CACHE(LLC_ELLC) \| LE_LRUM(0) \|
101	LE_AOM(0) \| LE_RSC(0) \| LE_SCC(0) \| LE_PFM(0) \| LE_SCF(0)),
102	(L3_ESC(0) \| L3_SCC(0) \| L3_CACHEABILITY(L3_UC)) },
103	/* { 0x00000038, 0x0030 } */
104	{ (LE_CACHEABILITY(LE_PAGETABLE) \| LE_TGT_CACHE(LLC_ELLC) \| LE_LRUM(3) \|
105	LE_AOM(0) \| LE_RSC(0) \| LE_SCC(0) \| LE_PFM(0) \| LE_SCF(0)),
106	(L3_ESC(0) \| L3_SCC(0) \| L3_CACHEABILITY(L3_WB)) },
107	/* { 0x0000003b, 0x0030 } */
108	{ (LE_CACHEABILITY(LE_WB) \| LE_TGT_CACHE(LLC_ELLC) \| LE_LRUM(3) \|
109	LE_AOM(0) \| LE_RSC(0) \| LE_SCC(0) \| LE_PFM(0) \| LE_SCF(0)),
110	(L3_ESC(0) \| L3_SCC(0) \| L3_CACHEABILITY(L3_WB)) }
111	};
112
113	/* NOTE: the LE_TGT_CACHE is not used on Broxton */
114	static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
115	/* { 0x00000009, 0x0010 } */
116	{ (LE_CACHEABILITY(LE_UC) \| LE_TGT_CACHE(LLC_ELLC) \| LE_LRUM(0) \|
117	LE_AOM(0) \| LE_RSC(0) \| LE_SCC(0) \| LE_PFM(0) \| LE_SCF(0)),
118	(L3_ESC(0) \| L3_SCC(0) \| L3_CACHEABILITY(L3_UC)) },
119	/* { 0x00000038, 0x0030 } */
120	{ (LE_CACHEABILITY(LE_PAGETABLE) \| LE_TGT_CACHE(LLC_ELLC) \| LE_LRUM(3) \|
121	LE_AOM(0) \| LE_RSC(0) \| LE_SCC(0) \| LE_PFM(0) \| LE_SCF(0)),
122	(L3_ESC(0) \| L3_SCC(0) \| L3_CACHEABILITY(L3_WB)) },
123	/* { 0x0000003b, 0x0030 } */
124	{ (LE_CACHEABILITY(LE_WB) \| LE_TGT_CACHE(LLC_ELLC) \| LE_LRUM(3) \|
125	LE_AOM(0) \| LE_RSC(0) \| LE_SCC(0) \| LE_PFM(0) \| LE_SCF(0)),
126	(L3_ESC(0) \| L3_SCC(0) \| L3_CACHEABILITY(L3_WB)) }
127	};
128
129	/**
130	* get_mocs_settings()
0ccdacf6	131	* @dev_priv: i915 device.
3bbaba0c	132	* @table: Output table that will be made to point at appropriate
0ccdacf6	133	* MOCS values for the device.
3bbaba0c PA	134	*
	135	* This function will return the values of the MOCS table that needs to
	136	* be programmed for the platform. It will return the values that need
	137	* to be programmed and if they need to be programmed.
	138	*
	139	* Return: true if there are applicable MOCS settings for the device.
	140	*/
0ccdacf6	141	static bool get_mocs_settings(struct drm_i915_private *dev_priv,
3bbaba0c PA	142	struct drm_i915_mocs_table *table)
	143	{
	144	bool result = false;
	145
0ccdacf6	146	if (IS_SKYLAKE(dev_priv) \|\| IS_KABYLAKE(dev_priv)) {
3bbaba0c PA	147	table->size = ARRAY_SIZE(skylake_mocs_table);
	148	table->table = skylake_mocs_table;
	149	result = true;
0ccdacf6	150	} else if (IS_BROXTON(dev_priv)) {
3bbaba0c PA	151	table->size = ARRAY_SIZE(broxton_mocs_table);
	152	table->table = broxton_mocs_table;
	153	result = true;
	154	} else {
0ccdacf6	155	WARN_ONCE(INTEL_INFO(dev_priv)->gen >= 9,
3bbaba0c PA	156	"Platform that should have a MOCS table does not.\n");
	157	}
	158
6fc29133 MK	159	/* WaDisableSkipCaching:skl,bxt,kbl */
	160	if (IS_GEN9(dev_priv)) {
	161	int i;
	162
	163	for (i = 0; i < table->size; i++)
	164	if (WARN_ON(table->table[i].l3cc_value &
030daa0f	165	(L3_ESC(1) \| L3_SCC(0x7))))
6fc29133 MK	166	return false;
	167	}
	168
3bbaba0c PA	169	return result;
	170	}
	171
117897f4	172	static i915_reg_t mocs_register(enum intel_engine_id ring, int index)
e6c4c763 VS	173	{
	174	switch (ring) {
	175	case RCS:
	176	return GEN9_GFX_MOCS(index);
	177	case VCS:
	178	return GEN9_MFX0_MOCS(index);
	179	case BCS:
	180	return GEN9_BLT_MOCS(index);
	181	case VECS:
	182	return GEN9_VEBOX_MOCS(index);
	183	case VCS2:
	184	return GEN9_MFX1_MOCS(index);
	185	default:
	186	MISSING_CASE(ring);
f0f59a00	187	return INVALID_MMIO_REG;
e6c4c763 VS	188	}
	189	}
	190
0ccdacf6 PA	191	/**
	192	* intel_mocs_init_engine() - emit the mocs control table
	193	* @engine: The engine for whom to emit the registers.
	194	*
	195	* This function simply emits a MI_LOAD_REGISTER_IMM command for the
	196	* given table starting at the given address.
	197	*
	198	* Return: 0 on success, otherwise the error status.
	199	*/
	200	int intel_mocs_init_engine(struct intel_engine_cs *engine)
	201	{
c033666a	202	struct drm_i915_private *dev_priv = engine->i915;
0ccdacf6 PA	203	struct drm_i915_mocs_table table;
	204	unsigned int index;
	205
	206	if (!get_mocs_settings(dev_priv, &table))
	207	return 0;
	208
	209	if (WARN_ON(table.size > GEN9_NUM_MOCS_ENTRIES))
	210	return -ENODEV;
	211
	212	for (index = 0; index < table.size; index++)
	213	I915_WRITE(mocs_register(engine->id, index),
	214	table.table[index].control_value);
	215
	216	/*
	217	* Ok, now set the unused entries to uncached. These entries
	218	* are officially undefined and no contract for the contents
	219	* and settings is given for these entries.
	220	*
	221	* Entry 0 in the table is uncached - so we are just writing
	222	* that value to all the used entries.
	223	*/
	224	for (; index < GEN9_NUM_MOCS_ENTRIES; index++)
	225	I915_WRITE(mocs_register(engine->id, index),
	226	table.table[0].control_value);
	227
	228	return 0;
	229	}
	230
3bbaba0c PA	231	/**
	232	* emit_mocs_control_table() - emit the mocs control table
	233	* @req: Request to set up the MOCS table for.
	234	* @table: The values to program into the control regs.
3bbaba0c PA	235	*
	236	* This function simply emits a MI_LOAD_REGISTER_IMM command for the
	237	* given table starting at the given address.
	238	*
	239	* Return: 0 on success, otherwise the error status.
	240	*/
	241	static int emit_mocs_control_table(struct drm_i915_gem_request *req,
0ccdacf6	242	const struct drm_i915_mocs_table *table)
3bbaba0c PA	243	{
3bbaba0c PA	244	struct intel_ringbuffer *ringbuf = req->ringbuf;
0ccdacf6	245	enum intel_engine_id engine = req->engine->id;
3bbaba0c PA	246	unsigned int index;
	247	int ret;
	248
	249	if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES))
	250	return -ENODEV;
	251
987046ad CW	252	ret = intel_ring_begin(req, 2 + 2 * GEN9_NUM_MOCS_ENTRIES);
987046ad CW	253	if (ret)
3bbaba0c	254	return ret;
3bbaba0c PA	255
	256	intel_logical_ring_emit(ringbuf,
	257	MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES));
	258
	259	for (index = 0; index < table->size; index++) {
0ccdacf6 PA	260	intel_logical_ring_emit_reg(ringbuf,
0ccdacf6 PA	261	mocs_register(engine, index));
3bbaba0c PA	262	intel_logical_ring_emit(ringbuf,
	263	table->table[index].control_value);
	264	}
	265
	266	/*
	267	* Ok, now set the unused entries to uncached. These entries
	268	* are officially undefined and no contract for the contents
	269	* and settings is given for these entries.
	270	*
	271	* Entry 0 in the table is uncached - so we are just writing
	272	* that value to all the used entries.
	273	*/
	274	for (; index < GEN9_NUM_MOCS_ENTRIES; index++) {
0ccdacf6 PA	275	intel_logical_ring_emit_reg(ringbuf,
	276	mocs_register(engine, index));
	277	intel_logical_ring_emit(ringbuf,
	278	table->table[0].control_value);
3bbaba0c PA	279	}
	280
	281	intel_logical_ring_emit(ringbuf, MI_NOOP);
	282	intel_logical_ring_advance(ringbuf);
	283
	284	return 0;
	285	}
	286
0ccdacf6 PA	287	static inline u32 l3cc_combine(const struct drm_i915_mocs_table *table,
	288	u16 low,
	289	u16 high)
	290	{
	291	return table->table[low].l3cc_value \|
	292	table->table[high].l3cc_value << 16;
	293	}
	294
3bbaba0c PA	295	/**
	296	* emit_mocs_l3cc_table() - emit the mocs control table
	297	* @req: Request to set up the MOCS table for.
	298	* @table: The values to program into the control regs.
	299	*
	300	* This function simply emits a MI_LOAD_REGISTER_IMM command for the
	301	* given table starting at the given address. This register set is
	302	* programmed in pairs.
	303	*
	304	* Return: 0 on success, otherwise the error status.
	305	*/
	306	static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req,
	307	const struct drm_i915_mocs_table *table)
	308	{
	309	struct intel_ringbuffer *ringbuf = req->ringbuf;
3bbaba0c	310	unsigned int i;
3bbaba0c PA	311	int ret;
	312
	313	if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES))
	314	return -ENODEV;
	315
987046ad CW	316	ret = intel_ring_begin(req, 2 + GEN9_NUM_MOCS_ENTRIES);
987046ad CW	317	if (ret)
3bbaba0c	318	return ret;
3bbaba0c PA	319
	320	intel_logical_ring_emit(ringbuf,
	321	MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES / 2));
	322
0ccdacf6	323	for (i = 0; i < table->size/2; i++) {
f92a9162	324	intel_logical_ring_emit_reg(ringbuf, GEN9_LNCFCMOCS(i));
0ccdacf6 PA	325	intel_logical_ring_emit(ringbuf,
0ccdacf6 PA	326	l3cc_combine(table, 2i, 2i+1));
3bbaba0c PA	327	}
	328
	329	if (table->size & 0x01) {
	330	/* Odd table size - 1 left over */
0ccdacf6 PA	331	intel_logical_ring_emit_reg(ringbuf, GEN9_LNCFCMOCS(i));
	332	intel_logical_ring_emit(ringbuf, l3cc_combine(table, 2*i, 0));
	333	i++;
	334	}
3bbaba0c PA	335
	336	/*
	337	* Now set the rest of the table to uncached - use entry 0 as
	338	* this will be uncached. Leave the last pair uninitialised as
	339	* they are reserved by the hardware.
	340	*/
	341	for (; i < GEN9_NUM_MOCS_ENTRIES / 2; i++) {
f92a9162	342	intel_logical_ring_emit_reg(ringbuf, GEN9_LNCFCMOCS(i));
0ccdacf6	343	intel_logical_ring_emit(ringbuf, l3cc_combine(table, 0, 0));
3bbaba0c PA	344	}
	345
	346	intel_logical_ring_emit(ringbuf, MI_NOOP);
	347	intel_logical_ring_advance(ringbuf);
	348
	349	return 0;
	350	}
	351
0ccdacf6 PA	352	/**
	353	* intel_mocs_init_l3cc_table() - program the mocs control table
	354	* @dev: The the device to be programmed.
	355	*
	356	* This function simply programs the mocs registers for the given table
	357	* starting at the given address. This register set is programmed in pairs.
	358	*
	359	* These registers may get programmed more than once, it is simpler to
	360	* re-program 32 registers than maintain the state of when they were programmed.
	361	* We are always reprogramming with the same values and this only on context
	362	* start.
	363	*
	364	* Return: Nothing.
	365	*/
	366	void intel_mocs_init_l3cc_table(struct drm_device *dev)
	367	{
	368	struct drm_i915_private *dev_priv = to_i915(dev);
	369	struct drm_i915_mocs_table table;
	370	unsigned int i;
	371
	372	if (!get_mocs_settings(dev_priv, &table))
	373	return;
	374
	375	for (i = 0; i < table.size/2; i++)
	376	I915_WRITE(GEN9_LNCFCMOCS(i), l3cc_combine(&table, 2i, 2i+1));
	377
	378	/* Odd table size - 1 left over */
	379	if (table.size & 0x01) {
	380	I915_WRITE(GEN9_LNCFCMOCS(i), l3cc_combine(&table, 2*i, 0));
	381	i++;
	382	}
	383
	384	/*
	385	* Now set the rest of the table to uncached - use entry 0 as
	386	* this will be uncached. Leave the last pair as initialised as
	387	* they are reserved by the hardware.
	388	*/
	389	for (; i < (GEN9_NUM_MOCS_ENTRIES / 2); i++)
	390	I915_WRITE(GEN9_LNCFCMOCS(i), l3cc_combine(&table, 0, 0));
	391	}
	392
3bbaba0c PA	393	/**
	394	* intel_rcs_context_init_mocs() - program the MOCS register.
	395	* @req: Request to set up the MOCS tables for.
	396	*
	397	* This function will emit a batch buffer with the values required for
	398	* programming the MOCS register values for all the currently supported
	399	* rings.
	400	*
	401	* These registers are partially stored in the RCS context, so they are
	402	* emitted at the same time so that when a context is created these registers
	403	* are set up. These registers have to be emitted into the start of the
	404	* context as setting the ELSP will re-init some of these registers back
	405	* to the hw values.
	406	*
	407	* Return: 0 on success, otherwise the error status.
	408	*/
	409	int intel_rcs_context_init_mocs(struct drm_i915_gem_request *req)
	410	{
	411	struct drm_i915_mocs_table t;
	412	int ret;
	413
0ccdacf6 PA	414	if (get_mocs_settings(req->i915, &t)) {
	415	/* Program the RCS control registers */
	416	ret = emit_mocs_control_table(req, &t);
	417	if (ret)
	418	return ret;
3bbaba0c PA	419
	420	/* Now program the l3cc registers */
	421	ret = emit_mocs_l3cc_table(req, &t);
	422	if (ret)
	423	return ret;
	424	}
	425
	426	return 0;
	427	}