drm/i915/lvds: Introduce intel_lvds_connector
[linux-block.git] / drivers / gpu / drm / i915 / intel_lvds.c
CommitLineData
79e53945
JB
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 */
29
c1c7af60 30#include <acpi/button.h>
565dcd46 31#include <linux/dmi.h>
79e53945 32#include <linux/i2c.h>
5a0e3ad6 33#include <linux/slab.h>
760285e7
DH
34#include <drm/drmP.h>
35#include <drm/drm_crtc.h>
36#include <drm/drm_edid.h>
79e53945 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
79e53945 39#include "i915_drv.h"
e99da35f 40#include <linux/acpi.h>
79e53945 41
3fbe18d6 42/* Private structure for the integrated LVDS support */
c7362c4d
JN
43struct intel_lvds_connector {
44 struct intel_connector base;
45};
46
29b99b48 47struct intel_lvds_encoder {
ea5b213a 48 struct intel_encoder base;
788319d4 49
219adae1 50 struct edid *edid;
788319d4 51
3fbe18d6
ZY
52 int fitting_mode;
53 u32 pfit_control;
54 u32 pfit_pgm_ratios;
e9e331a8 55 bool pfit_dirty;
788319d4
CW
56
57 struct drm_display_mode *fixed_mode;
3fbe18d6
ZY
58};
59
29b99b48 60static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
ea5b213a 61{
29b99b48 62 return container_of(encoder, struct intel_lvds_encoder, base.base);
ea5b213a
CW
63}
64
c7362c4d
JN
65static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector)
66{
67 return container_of(connector, struct intel_lvds_connector, base.base);
68}
69
29b99b48 70static struct intel_lvds_encoder *intel_attached_lvds(struct drm_connector *connector)
788319d4
CW
71{
72 return container_of(intel_attached_encoder(connector),
29b99b48 73 struct intel_lvds_encoder, base);
788319d4
CW
74}
75
b1dc332c
DV
76static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
77 enum pipe *pipe)
78{
79 struct drm_device *dev = encoder->base.dev;
80 struct drm_i915_private *dev_priv = dev->dev_private;
81 u32 lvds_reg, tmp;
82
83 if (HAS_PCH_SPLIT(dev)) {
84 lvds_reg = PCH_LVDS;
85 } else {
86 lvds_reg = LVDS;
87 }
88
89 tmp = I915_READ(lvds_reg);
90
91 if (!(tmp & LVDS_PORT_EN))
92 return false;
93
94 if (HAS_PCH_CPT(dev))
95 *pipe = PORT_TO_PIPE_CPT(tmp);
96 else
97 *pipe = PORT_TO_PIPE(tmp);
98
99 return true;
100}
101
79e53945
JB
102/**
103 * Sets the power state for the panel.
104 */
c22834ec 105static void intel_enable_lvds(struct intel_encoder *encoder)
79e53945 106{
c22834ec 107 struct drm_device *dev = encoder->base.dev;
29b99b48 108 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
c22834ec 109 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 110 struct drm_i915_private *dev_priv = dev->dev_private;
de842eff 111 u32 ctl_reg, lvds_reg, stat_reg;
541998a1 112
c619eed4 113 if (HAS_PCH_SPLIT(dev)) {
541998a1 114 ctl_reg = PCH_PP_CONTROL;
469d1296 115 lvds_reg = PCH_LVDS;
de842eff 116 stat_reg = PCH_PP_STATUS;
541998a1
ZW
117 } else {
118 ctl_reg = PP_CONTROL;
469d1296 119 lvds_reg = LVDS;
de842eff 120 stat_reg = PP_STATUS;
541998a1 121 }
79e53945 122
2a1292fd 123 I915_WRITE(lvds_reg, I915_READ(lvds_reg) | LVDS_PORT_EN);
e9e331a8 124
29b99b48 125 if (lvds_encoder->pfit_dirty) {
2a1292fd
CW
126 /*
127 * Enable automatic panel scaling so that non-native modes
128 * fill the screen. The panel fitter should only be
129 * adjusted whilst the pipe is disabled, according to
130 * register description and PRM.
131 */
132 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
29b99b48
JN
133 lvds_encoder->pfit_control,
134 lvds_encoder->pfit_pgm_ratios);
de842eff 135
29b99b48
JN
136 I915_WRITE(PFIT_PGM_RATIOS, lvds_encoder->pfit_pgm_ratios);
137 I915_WRITE(PFIT_CONTROL, lvds_encoder->pfit_control);
138 lvds_encoder->pfit_dirty = false;
2a1292fd
CW
139 }
140
141 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
142 POSTING_READ(lvds_reg);
de842eff
KP
143 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
144 DRM_ERROR("timed out waiting for panel to power on\n");
2a1292fd 145
24ded204 146 intel_panel_enable_backlight(dev, intel_crtc->pipe);
2a1292fd
CW
147}
148
c22834ec 149static void intel_disable_lvds(struct intel_encoder *encoder)
2a1292fd 150{
c22834ec 151 struct drm_device *dev = encoder->base.dev;
29b99b48 152 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
2a1292fd 153 struct drm_i915_private *dev_priv = dev->dev_private;
de842eff 154 u32 ctl_reg, lvds_reg, stat_reg;
2a1292fd
CW
155
156 if (HAS_PCH_SPLIT(dev)) {
157 ctl_reg = PCH_PP_CONTROL;
158 lvds_reg = PCH_LVDS;
de842eff 159 stat_reg = PCH_PP_STATUS;
2a1292fd
CW
160 } else {
161 ctl_reg = PP_CONTROL;
162 lvds_reg = LVDS;
de842eff 163 stat_reg = PP_STATUS;
2a1292fd
CW
164 }
165
47356eb6 166 intel_panel_disable_backlight(dev);
2a1292fd
CW
167
168 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
de842eff
KP
169 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
170 DRM_ERROR("timed out waiting for panel to power off\n");
2a1292fd 171
29b99b48 172 if (lvds_encoder->pfit_control) {
2a1292fd 173 I915_WRITE(PFIT_CONTROL, 0);
29b99b48 174 lvds_encoder->pfit_dirty = true;
79e53945 175 }
2a1292fd
CW
176
177 I915_WRITE(lvds_reg, I915_READ(lvds_reg) & ~LVDS_PORT_EN);
c9f9ccc1 178 POSTING_READ(lvds_reg);
79e53945
JB
179}
180
79e53945
JB
181static int intel_lvds_mode_valid(struct drm_connector *connector,
182 struct drm_display_mode *mode)
183{
29b99b48
JN
184 struct intel_lvds_encoder *lvds_encoder = intel_attached_lvds(connector);
185 struct drm_display_mode *fixed_mode = lvds_encoder->fixed_mode;
79e53945 186
788319d4
CW
187 if (mode->hdisplay > fixed_mode->hdisplay)
188 return MODE_PANEL;
189 if (mode->vdisplay > fixed_mode->vdisplay)
190 return MODE_PANEL;
79e53945
JB
191
192 return MODE_OK;
193}
194
49be663f
CW
195static void
196centre_horizontally(struct drm_display_mode *mode,
197 int width)
198{
199 u32 border, sync_pos, blank_width, sync_width;
200
201 /* keep the hsync and hblank widths constant */
202 sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start;
203 blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start;
204 sync_pos = (blank_width - sync_width + 1) / 2;
205
206 border = (mode->hdisplay - width + 1) / 2;
207 border += border & 1; /* make the border even */
208
209 mode->crtc_hdisplay = width;
210 mode->crtc_hblank_start = width + border;
211 mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width;
212
213 mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos;
214 mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width;
f9bef081
DV
215
216 mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET;
49be663f
CW
217}
218
219static void
220centre_vertically(struct drm_display_mode *mode,
221 int height)
222{
223 u32 border, sync_pos, blank_width, sync_width;
224
225 /* keep the vsync and vblank widths constant */
226 sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start;
227 blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start;
228 sync_pos = (blank_width - sync_width + 1) / 2;
229
230 border = (mode->vdisplay - height + 1) / 2;
231
232 mode->crtc_vdisplay = height;
233 mode->crtc_vblank_start = height + border;
234 mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width;
235
236 mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos;
237 mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width;
f9bef081
DV
238
239 mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET;
49be663f
CW
240}
241
242static inline u32 panel_fitter_scaling(u32 source, u32 target)
243{
244 /*
245 * Floating point operation is not supported. So the FACTOR
246 * is defined, which can avoid the floating point computation
247 * when calculating the panel ratio.
248 */
249#define ACCURACY 12
250#define FACTOR (1 << ACCURACY)
251 u32 ratio = source * FACTOR / target;
252 return (FACTOR * ratio + FACTOR/2) / FACTOR;
253}
254
79e53945 255static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
e811f5ae 256 const struct drm_display_mode *mode,
79e53945
JB
257 struct drm_display_mode *adjusted_mode)
258{
259 struct drm_device *dev = encoder->dev;
260 struct drm_i915_private *dev_priv = dev->dev_private;
29b99b48
JN
261 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
262 struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc;
49be663f 263 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
9db4a9c7 264 int pipe;
79e53945
JB
265
266 /* Should never happen!! */
a6c45cf0 267 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
1ae8c0a5 268 DRM_ERROR("Can't support LVDS on pipe A\n");
79e53945
JB
269 return false;
270 }
271
29b99b48 272 if (intel_encoder_check_is_cloned(&lvds_encoder->base))
e24c5c29 273 return false;
1d8e1c75 274
79e53945 275 /*
71677043 276 * We have timings from the BIOS for the panel, put them in
79e53945
JB
277 * to the adjusted mode. The CRTC will be set up for this mode,
278 * with the panel scaling set up to source from the H/VDisplay
279 * of the original mode.
280 */
29b99b48 281 intel_fixed_panel_mode(lvds_encoder->fixed_mode, adjusted_mode);
1d8e1c75
CW
282
283 if (HAS_PCH_SPLIT(dev)) {
29b99b48 284 intel_pch_panel_fitting(dev, lvds_encoder->fitting_mode,
1d8e1c75
CW
285 mode, adjusted_mode);
286 return true;
287 }
79e53945 288
3fbe18d6
ZY
289 /* Native modes don't need fitting */
290 if (adjusted_mode->hdisplay == mode->hdisplay &&
49be663f 291 adjusted_mode->vdisplay == mode->vdisplay)
3fbe18d6 292 goto out;
3fbe18d6
ZY
293
294 /* 965+ wants fuzzy fitting */
a6c45cf0 295 if (INTEL_INFO(dev)->gen >= 4)
49be663f
CW
296 pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
297 PFIT_FILTER_FUZZY);
298
3fbe18d6
ZY
299 /*
300 * Enable automatic panel scaling for non-native modes so that they fill
301 * the screen. Should be enabled before the pipe is enabled, according
302 * to register description and PRM.
303 * Change the value here to see the borders for debugging
304 */
9db4a9c7
JB
305 for_each_pipe(pipe)
306 I915_WRITE(BCLRPAT(pipe), 0);
3fbe18d6 307
f9bef081
DV
308 drm_mode_set_crtcinfo(adjusted_mode, 0);
309
29b99b48 310 switch (lvds_encoder->fitting_mode) {
53bd8389 311 case DRM_MODE_SCALE_CENTER:
3fbe18d6
ZY
312 /*
313 * For centered modes, we have to calculate border widths &
314 * heights and modify the values programmed into the CRTC.
315 */
49be663f
CW
316 centre_horizontally(adjusted_mode, mode->hdisplay);
317 centre_vertically(adjusted_mode, mode->vdisplay);
318 border = LVDS_BORDER_ENABLE;
3fbe18d6 319 break;
49be663f 320
3fbe18d6 321 case DRM_MODE_SCALE_ASPECT:
49be663f 322 /* Scale but preserve the aspect ratio */
a6c45cf0 323 if (INTEL_INFO(dev)->gen >= 4) {
49be663f
CW
324 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
325 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
326
3fbe18d6 327 /* 965+ is easy, it does everything in hw */
49be663f 328 if (scaled_width > scaled_height)
257e48f1 329 pfit_control |= PFIT_ENABLE | PFIT_SCALING_PILLAR;
49be663f 330 else if (scaled_width < scaled_height)
257e48f1
CW
331 pfit_control |= PFIT_ENABLE | PFIT_SCALING_LETTER;
332 else if (adjusted_mode->hdisplay != mode->hdisplay)
333 pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
3fbe18d6 334 } else {
49be663f
CW
335 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
336 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
3fbe18d6
ZY
337 /*
338 * For earlier chips we have to calculate the scaling
339 * ratio by hand and program it into the
340 * PFIT_PGM_RATIO register
341 */
49be663f
CW
342 if (scaled_width > scaled_height) { /* pillar */
343 centre_horizontally(adjusted_mode, scaled_height / mode->vdisplay);
344
345 border = LVDS_BORDER_ENABLE;
346 if (mode->vdisplay != adjusted_mode->vdisplay) {
347 u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay);
348 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
349 bits << PFIT_VERT_SCALE_SHIFT);
350 pfit_control |= (PFIT_ENABLE |
351 VERT_INTERP_BILINEAR |
352 HORIZ_INTERP_BILINEAR);
353 }
354 } else if (scaled_width < scaled_height) { /* letter */
355 centre_vertically(adjusted_mode, scaled_width / mode->hdisplay);
356
357 border = LVDS_BORDER_ENABLE;
358 if (mode->hdisplay != adjusted_mode->hdisplay) {
359 u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay);
360 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
361 bits << PFIT_VERT_SCALE_SHIFT);
362 pfit_control |= (PFIT_ENABLE |
363 VERT_INTERP_BILINEAR |
364 HORIZ_INTERP_BILINEAR);
365 }
366 } else
367 /* Aspects match, Let hw scale both directions */
368 pfit_control |= (PFIT_ENABLE |
369 VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
3fbe18d6
ZY
370 VERT_INTERP_BILINEAR |
371 HORIZ_INTERP_BILINEAR);
3fbe18d6
ZY
372 }
373 break;
374
375 case DRM_MODE_SCALE_FULLSCREEN:
376 /*
377 * Full scaling, even if it changes the aspect ratio.
378 * Fortunately this is all done for us in hw.
379 */
257e48f1
CW
380 if (mode->vdisplay != adjusted_mode->vdisplay ||
381 mode->hdisplay != adjusted_mode->hdisplay) {
382 pfit_control |= PFIT_ENABLE;
383 if (INTEL_INFO(dev)->gen >= 4)
384 pfit_control |= PFIT_SCALING_AUTO;
385 else
386 pfit_control |= (VERT_AUTO_SCALE |
387 VERT_INTERP_BILINEAR |
388 HORIZ_AUTO_SCALE |
389 HORIZ_INTERP_BILINEAR);
390 }
3fbe18d6 391 break;
49be663f 392
3fbe18d6
ZY
393 default:
394 break;
395 }
396
397out:
72389a33 398 /* If not enabling scaling, be consistent and always use 0. */
bee17e5a
CW
399 if ((pfit_control & PFIT_ENABLE) == 0) {
400 pfit_control = 0;
401 pfit_pgm_ratios = 0;
402 }
72389a33
CW
403
404 /* Make sure pre-965 set dither correctly */
405 if (INTEL_INFO(dev)->gen < 4 && dev_priv->lvds_dither)
406 pfit_control |= PANEL_8TO6_DITHER_ENABLE;
407
29b99b48
JN
408 if (pfit_control != lvds_encoder->pfit_control ||
409 pfit_pgm_ratios != lvds_encoder->pfit_pgm_ratios) {
410 lvds_encoder->pfit_control = pfit_control;
411 lvds_encoder->pfit_pgm_ratios = pfit_pgm_ratios;
412 lvds_encoder->pfit_dirty = true;
e9e331a8 413 }
49be663f
CW
414 dev_priv->lvds_border_bits = border;
415
79e53945
JB
416 /*
417 * XXX: It would be nice to support lower refresh rates on the
418 * panels to reduce power consumption, and perhaps match the
419 * user's requested refresh rate.
420 */
421
422 return true;
423}
424
79e53945
JB
425static void intel_lvds_mode_set(struct drm_encoder *encoder,
426 struct drm_display_mode *mode,
427 struct drm_display_mode *adjusted_mode)
428{
79e53945
JB
429 /*
430 * The LVDS pin pair will already have been turned on in the
431 * intel_crtc_mode_set since it has a large impact on the DPLL
432 * settings.
433 */
79e53945
JB
434}
435
436/**
437 * Detect the LVDS connection.
438 *
b42d4c5c
JB
439 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means
440 * connected and closed means disconnected. We also send hotplug events as
441 * needed, using lid status notification from the input layer.
79e53945 442 */
7b334fcb 443static enum drm_connector_status
930a9e28 444intel_lvds_detect(struct drm_connector *connector, bool force)
79e53945 445{
7b9c5abe 446 struct drm_device *dev = connector->dev;
6ee3b5a1 447 enum drm_connector_status status;
b42d4c5c 448
fe16d949
CW
449 status = intel_panel_detect(dev);
450 if (status != connector_status_unknown)
451 return status;
01fe9dbd 452
6ee3b5a1 453 return connector_status_connected;
79e53945
JB
454}
455
456/**
457 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
458 */
459static int intel_lvds_get_modes(struct drm_connector *connector)
460{
29b99b48 461 struct intel_lvds_encoder *lvds_encoder = intel_attached_lvds(connector);
79e53945 462 struct drm_device *dev = connector->dev;
788319d4 463 struct drm_display_mode *mode;
79e53945 464
29b99b48
JN
465 if (lvds_encoder->edid)
466 return drm_add_edid_modes(connector, lvds_encoder->edid);
79e53945 467
29b99b48 468 mode = drm_mode_duplicate(dev, lvds_encoder->fixed_mode);
311bd68e 469 if (mode == NULL)
788319d4 470 return 0;
79e53945 471
788319d4
CW
472 drm_mode_probed_add(connector, mode);
473 return 1;
79e53945
JB
474}
475
0544edfd
TB
476static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
477{
bc0daf48 478 DRM_INFO("Skipping forced modeset for %s\n", id->ident);
0544edfd
TB
479 return 1;
480}
481
482/* The GPU hangs up on these systems if modeset is performed on LID open */
483static const struct dmi_system_id intel_no_modeset_on_lid[] = {
484 {
485 .callback = intel_no_modeset_on_lid_dmi_callback,
486 .ident = "Toshiba Tecra A11",
487 .matches = {
488 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
489 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
490 },
491 },
492
493 { } /* terminating entry */
494};
495
c9354c85
LT
496/*
497 * Lid events. Note the use of 'modeset_on_lid':
498 * - we set it on lid close, and reset it on open
499 * - we use it as a "only once" bit (ie we ignore
500 * duplicate events where it was already properly
501 * set/reset)
502 * - the suspend/resume paths will also set it to
503 * zero, since they restore the mode ("lid open").
504 */
c1c7af60
JB
505static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
506 void *unused)
507{
508 struct drm_i915_private *dev_priv =
509 container_of(nb, struct drm_i915_private, lid_notifier);
510 struct drm_device *dev = dev_priv->dev;
a2565377 511 struct drm_connector *connector = dev_priv->int_lvds_connector;
c1c7af60 512
2fb4e61d
AW
513 if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
514 return NOTIFY_OK;
515
a2565377
ZY
516 /*
517 * check and update the status of LVDS connector after receiving
518 * the LID nofication event.
519 */
520 if (connector)
7b334fcb 521 connector->status = connector->funcs->detect(connector,
930a9e28 522 false);
7b334fcb 523
0544edfd
TB
524 /* Don't force modeset on machines where it causes a GPU lockup */
525 if (dmi_check_system(intel_no_modeset_on_lid))
526 return NOTIFY_OK;
c9354c85
LT
527 if (!acpi_lid_open()) {
528 dev_priv->modeset_on_lid = 1;
529 return NOTIFY_OK;
06891e27 530 }
c1c7af60 531
c9354c85
LT
532 if (!dev_priv->modeset_on_lid)
533 return NOTIFY_OK;
534
535 dev_priv->modeset_on_lid = 0;
536
537 mutex_lock(&dev->mode_config.mutex);
3b7a89fc 538 intel_modeset_check_state(dev);
c9354c85 539 mutex_unlock(&dev->mode_config.mutex);
06324194 540
c1c7af60
JB
541 return NOTIFY_OK;
542}
543
79e53945
JB
544/**
545 * intel_lvds_destroy - unregister and free LVDS structures
546 * @connector: connector to free
547 *
548 * Unregister the DDC bus for this connector then free the driver private
549 * structure.
550 */
551static void intel_lvds_destroy(struct drm_connector *connector)
552{
c1c7af60 553 struct drm_device *dev = connector->dev;
c1c7af60 554 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 555
aaa6fd2a
MG
556 intel_panel_destroy_backlight(dev);
557
c1c7af60
JB
558 if (dev_priv->lid_notifier.notifier_call)
559 acpi_lid_notifier_unregister(&dev_priv->lid_notifier);
79e53945
JB
560 drm_sysfs_connector_remove(connector);
561 drm_connector_cleanup(connector);
562 kfree(connector);
563}
564
335041ed
JB
565static int intel_lvds_set_property(struct drm_connector *connector,
566 struct drm_property *property,
567 uint64_t value)
568{
29b99b48 569 struct intel_lvds_encoder *lvds_encoder = intel_attached_lvds(connector);
3fbe18d6 570 struct drm_device *dev = connector->dev;
3fbe18d6 571
788319d4 572 if (property == dev->mode_config.scaling_mode_property) {
29b99b48 573 struct drm_crtc *crtc = lvds_encoder->base.base.crtc;
bb8a3560 574
53bd8389
JB
575 if (value == DRM_MODE_SCALE_NONE) {
576 DRM_DEBUG_KMS("no scaling not supported\n");
788319d4 577 return -EINVAL;
3fbe18d6 578 }
788319d4 579
29b99b48 580 if (lvds_encoder->fitting_mode == value) {
3fbe18d6
ZY
581 /* the LVDS scaling property is not changed */
582 return 0;
583 }
29b99b48 584 lvds_encoder->fitting_mode = value;
3fbe18d6
ZY
585 if (crtc && crtc->enabled) {
586 /*
587 * If the CRTC is enabled, the display will be changed
588 * according to the new panel fitting mode.
589 */
a6778b3c
DV
590 intel_set_mode(crtc, &crtc->mode,
591 crtc->x, crtc->y, crtc->fb);
3fbe18d6
ZY
592 }
593 }
594
335041ed
JB
595 return 0;
596}
597
79e53945 598static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = {
79e53945 599 .mode_fixup = intel_lvds_mode_fixup,
79e53945 600 .mode_set = intel_lvds_mode_set,
1f703855 601 .disable = intel_encoder_noop,
79e53945
JB
602};
603
604static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
605 .get_modes = intel_lvds_get_modes,
606 .mode_valid = intel_lvds_mode_valid,
df0e9248 607 .best_encoder = intel_best_encoder,
79e53945
JB
608};
609
610static const struct drm_connector_funcs intel_lvds_connector_funcs = {
c22834ec 611 .dpms = intel_connector_dpms,
79e53945
JB
612 .detect = intel_lvds_detect,
613 .fill_modes = drm_helper_probe_single_connector_modes,
335041ed 614 .set_property = intel_lvds_set_property,
79e53945
JB
615 .destroy = intel_lvds_destroy,
616};
617
79e53945 618static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
ea5b213a 619 .destroy = intel_encoder_destroy,
79e53945
JB
620};
621
425d244c
JW
622static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
623{
bc0daf48 624 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
425d244c
JW
625 return 1;
626}
79e53945 627
425d244c 628/* These systems claim to have LVDS, but really don't */
93c05f22 629static const struct dmi_system_id intel_no_lvds[] = {
425d244c
JW
630 {
631 .callback = intel_no_lvds_dmi_callback,
632 .ident = "Apple Mac Mini (Core series)",
633 .matches = {
98acd46f 634 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
635 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
636 },
637 },
638 {
639 .callback = intel_no_lvds_dmi_callback,
640 .ident = "Apple Mac Mini (Core 2 series)",
641 .matches = {
98acd46f 642 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
643 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
644 },
645 },
646 {
647 .callback = intel_no_lvds_dmi_callback,
648 .ident = "MSI IM-945GSE-A",
649 .matches = {
650 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
651 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
652 },
653 },
654 {
655 .callback = intel_no_lvds_dmi_callback,
656 .ident = "Dell Studio Hybrid",
657 .matches = {
658 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
659 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
660 },
661 },
70aa96ca
JW
662 {
663 .callback = intel_no_lvds_dmi_callback,
b066254f
PC
664 .ident = "Dell OptiPlex FX170",
665 .matches = {
666 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
667 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
668 },
669 },
670 {
671 .callback = intel_no_lvds_dmi_callback,
70aa96ca
JW
672 .ident = "AOpen Mini PC",
673 .matches = {
674 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
675 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
676 },
677 },
ed8c754b
TV
678 {
679 .callback = intel_no_lvds_dmi_callback,
680 .ident = "AOpen Mini PC MP915",
681 .matches = {
682 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
683 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
684 },
685 },
22ab70d3
KP
686 {
687 .callback = intel_no_lvds_dmi_callback,
688 .ident = "AOpen i915GMm-HFS",
689 .matches = {
690 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
691 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
692 },
693 },
e57b6886
DV
694 {
695 .callback = intel_no_lvds_dmi_callback,
696 .ident = "AOpen i45GMx-I",
697 .matches = {
698 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
699 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
700 },
701 },
fa0864b2
MC
702 {
703 .callback = intel_no_lvds_dmi_callback,
704 .ident = "Aopen i945GTt-VFA",
705 .matches = {
706 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
707 },
708 },
9875557e
SB
709 {
710 .callback = intel_no_lvds_dmi_callback,
711 .ident = "Clientron U800",
712 .matches = {
713 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
714 DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
715 },
716 },
6a574b5b 717 {
44306ab3
JS
718 .callback = intel_no_lvds_dmi_callback,
719 .ident = "Clientron E830",
720 .matches = {
721 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
722 DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
723 },
724 },
725 {
6a574b5b
HG
726 .callback = intel_no_lvds_dmi_callback,
727 .ident = "Asus EeeBox PC EB1007",
728 .matches = {
729 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
730 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
731 },
732 },
0999bbe0
AJ
733 {
734 .callback = intel_no_lvds_dmi_callback,
735 .ident = "Asus AT5NM10T-I",
736 .matches = {
737 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
738 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
739 },
740 },
33471119
JBG
741 {
742 .callback = intel_no_lvds_dmi_callback,
743 .ident = "Hewlett-Packard HP t5740e Thin Client",
744 .matches = {
745 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
746 DMI_MATCH(DMI_PRODUCT_NAME, "HP t5740e Thin Client"),
747 },
748 },
f5b8a7ed
MG
749 {
750 .callback = intel_no_lvds_dmi_callback,
751 .ident = "Hewlett-Packard t5745",
752 .matches = {
753 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 754 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
f5b8a7ed
MG
755 },
756 },
757 {
758 .callback = intel_no_lvds_dmi_callback,
759 .ident = "Hewlett-Packard st5747",
760 .matches = {
761 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 762 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
f5b8a7ed
MG
763 },
764 },
97effadb
AA
765 {
766 .callback = intel_no_lvds_dmi_callback,
767 .ident = "MSI Wind Box DC500",
768 .matches = {
769 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
770 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
771 },
772 },
9756fe38
SS
773 {
774 .callback = intel_no_lvds_dmi_callback,
775 .ident = "ZOTAC ZBOXSD-ID12/ID13",
776 .matches = {
777 DMI_MATCH(DMI_BOARD_VENDOR, "ZOTAC"),
778 DMI_MATCH(DMI_BOARD_NAME, "ZBOXSD-ID12/ID13"),
779 },
780 },
a51d4ed0
CW
781 {
782 .callback = intel_no_lvds_dmi_callback,
783 .ident = "Gigabyte GA-D525TUD",
784 .matches = {
785 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
786 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
787 },
788 },
425d244c
JW
789
790 { } /* terminating entry */
791};
79e53945 792
18f9ed12
ZY
793/**
794 * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID
795 * @dev: drm device
796 * @connector: LVDS connector
797 *
798 * Find the reduced downclock for LVDS in EDID.
799 */
800static void intel_find_lvds_downclock(struct drm_device *dev,
788319d4
CW
801 struct drm_display_mode *fixed_mode,
802 struct drm_connector *connector)
18f9ed12
ZY
803{
804 struct drm_i915_private *dev_priv = dev->dev_private;
788319d4 805 struct drm_display_mode *scan;
18f9ed12
ZY
806 int temp_downclock;
807
788319d4 808 temp_downclock = fixed_mode->clock;
18f9ed12
ZY
809 list_for_each_entry(scan, &connector->probed_modes, head) {
810 /*
811 * If one mode has the same resolution with the fixed_panel
812 * mode while they have the different refresh rate, it means
813 * that the reduced downclock is found for the LVDS. In such
814 * case we can set the different FPx0/1 to dynamically select
815 * between low and high frequency.
816 */
788319d4
CW
817 if (scan->hdisplay == fixed_mode->hdisplay &&
818 scan->hsync_start == fixed_mode->hsync_start &&
819 scan->hsync_end == fixed_mode->hsync_end &&
820 scan->htotal == fixed_mode->htotal &&
821 scan->vdisplay == fixed_mode->vdisplay &&
822 scan->vsync_start == fixed_mode->vsync_start &&
823 scan->vsync_end == fixed_mode->vsync_end &&
824 scan->vtotal == fixed_mode->vtotal) {
18f9ed12
ZY
825 if (scan->clock < temp_downclock) {
826 /*
827 * The downclock is already found. But we
828 * expect to find the lower downclock.
829 */
830 temp_downclock = scan->clock;
831 }
832 }
833 }
788319d4 834 if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) {
18f9ed12
ZY
835 /* We found the downclock for LVDS. */
836 dev_priv->lvds_downclock_avail = 1;
837 dev_priv->lvds_downclock = temp_downclock;
838 DRM_DEBUG_KMS("LVDS downclock is found in EDID. "
788319d4
CW
839 "Normal clock %dKhz, downclock %dKhz\n",
840 fixed_mode->clock, temp_downclock);
18f9ed12 841 }
18f9ed12
ZY
842}
843
7cf4f69d
ZY
844/*
845 * Enumerate the child dev array parsed from VBT to check whether
846 * the LVDS is present.
847 * If it is present, return 1.
848 * If it is not present, return false.
849 * If no child dev is parsed from VBT, it assumes that the LVDS is present.
7cf4f69d 850 */
270eea0f
CW
851static bool lvds_is_present_in_vbt(struct drm_device *dev,
852 u8 *i2c_pin)
7cf4f69d
ZY
853{
854 struct drm_i915_private *dev_priv = dev->dev_private;
425904dd 855 int i;
7cf4f69d
ZY
856
857 if (!dev_priv->child_dev_num)
425904dd 858 return true;
7cf4f69d 859
7cf4f69d 860 for (i = 0; i < dev_priv->child_dev_num; i++) {
425904dd
CW
861 struct child_device_config *child = dev_priv->child_dev + i;
862
863 /* If the device type is not LFP, continue.
864 * We have to check both the new identifiers as well as the
865 * old for compatibility with some BIOSes.
7cf4f69d 866 */
425904dd
CW
867 if (child->device_type != DEVICE_TYPE_INT_LFP &&
868 child->device_type != DEVICE_TYPE_LFP)
7cf4f69d
ZY
869 continue;
870
3bd7d909
DK
871 if (intel_gmbus_is_port_valid(child->i2c_pin))
872 *i2c_pin = child->i2c_pin;
270eea0f 873
425904dd
CW
874 /* However, we cannot trust the BIOS writers to populate
875 * the VBT correctly. Since LVDS requires additional
876 * information from AIM blocks, a non-zero addin offset is
877 * a good indicator that the LVDS is actually present.
7cf4f69d 878 */
425904dd
CW
879 if (child->addin_offset)
880 return true;
881
882 /* But even then some BIOS writers perform some black magic
883 * and instantiate the device without reference to any
884 * additional data. Trust that if the VBT was written into
885 * the OpRegion then they have validated the LVDS's existence.
886 */
887 if (dev_priv->opregion.vbt)
888 return true;
7cf4f69d 889 }
425904dd
CW
890
891 return false;
7cf4f69d
ZY
892}
893
f3cfcba6
CW
894static bool intel_lvds_supported(struct drm_device *dev)
895{
896 /* With the introduction of the PCH we gained a dedicated
897 * LVDS presence pin, use it. */
898 if (HAS_PCH_SPLIT(dev))
899 return true;
900
901 /* Otherwise LVDS was only attached to mobile products,
902 * except for the inglorious 830gm */
903 return IS_MOBILE(dev) && !IS_I830(dev);
904}
905
79e53945
JB
906/**
907 * intel_lvds_init - setup LVDS connectors on this device
908 * @dev: drm device
909 *
910 * Create the connector, register the LVDS DDC bus, and try to figure out what
911 * modes we can display on the LVDS panel (if present).
912 */
c5d1b51d 913bool intel_lvds_init(struct drm_device *dev)
79e53945
JB
914{
915 struct drm_i915_private *dev_priv = dev->dev_private;
29b99b48 916 struct intel_lvds_encoder *lvds_encoder;
21d40d37 917 struct intel_encoder *intel_encoder;
c7362c4d 918 struct intel_lvds_connector *lvds_connector;
bb8a3560 919 struct intel_connector *intel_connector;
79e53945
JB
920 struct drm_connector *connector;
921 struct drm_encoder *encoder;
922 struct drm_display_mode *scan; /* *modes, *bios_mode; */
923 struct drm_crtc *crtc;
924 u32 lvds;
270eea0f
CW
925 int pipe;
926 u8 pin;
79e53945 927
f3cfcba6
CW
928 if (!intel_lvds_supported(dev))
929 return false;
930
425d244c
JW
931 /* Skip init on machines we know falsely report LVDS */
932 if (dmi_check_system(intel_no_lvds))
c5d1b51d 933 return false;
565dcd46 934
270eea0f
CW
935 pin = GMBUS_PORT_PANEL;
936 if (!lvds_is_present_in_vbt(dev, &pin)) {
11ba1592 937 DRM_DEBUG_KMS("LVDS is not present in VBT\n");
c5d1b51d 938 return false;
38b3037e 939 }
e99da35f 940
c619eed4 941 if (HAS_PCH_SPLIT(dev)) {
541998a1 942 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
c5d1b51d 943 return false;
5ceb0f9b 944 if (dev_priv->edp.support) {
28c97730 945 DRM_DEBUG_KMS("disable LVDS for eDP support\n");
c5d1b51d 946 return false;
32f9d658 947 }
541998a1
ZW
948 }
949
29b99b48
JN
950 lvds_encoder = kzalloc(sizeof(struct intel_lvds_encoder), GFP_KERNEL);
951 if (!lvds_encoder)
c5d1b51d 952 return false;
79e53945 953
c7362c4d
JN
954 lvds_connector = kzalloc(sizeof(struct intel_lvds_connector), GFP_KERNEL);
955 if (!lvds_connector) {
29b99b48 956 kfree(lvds_encoder);
c5d1b51d 957 return false;
bb8a3560
ZW
958 }
959
e9e331a8 960 if (!HAS_PCH_SPLIT(dev)) {
29b99b48 961 lvds_encoder->pfit_control = I915_READ(PFIT_CONTROL);
e9e331a8
CW
962 }
963
29b99b48 964 intel_encoder = &lvds_encoder->base;
4ef69c7a 965 encoder = &intel_encoder->base;
c7362c4d 966 intel_connector = &lvds_connector->base;
ea5b213a 967 connector = &intel_connector->base;
bb8a3560 968 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
79e53945
JB
969 DRM_MODE_CONNECTOR_LVDS);
970
4ef69c7a 971 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
79e53945
JB
972 DRM_MODE_ENCODER_LVDS);
973
c22834ec
DV
974 intel_encoder->enable = intel_enable_lvds;
975 intel_encoder->disable = intel_disable_lvds;
b1dc332c
DV
976 intel_encoder->get_hw_state = intel_lvds_get_hw_state;
977 intel_connector->get_hw_state = intel_connector_get_hw_state;
c22834ec 978
df0e9248 979 intel_connector_attach_encoder(intel_connector, intel_encoder);
21d40d37 980 intel_encoder->type = INTEL_OUTPUT_LVDS;
79e53945 981
66a9278e 982 intel_encoder->cloneable = false;
27f8227b
JB
983 if (HAS_PCH_SPLIT(dev))
984 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
0b9f43a0
DV
985 else if (IS_GEN4(dev))
986 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
27f8227b
JB
987 else
988 intel_encoder->crtc_mask = (1 << 1);
989
79e53945
JB
990 drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs);
991 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
992 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
993 connector->interlace_allowed = false;
994 connector->doublescan_allowed = false;
995
3fbe18d6
ZY
996 /* create the scaling mode property */
997 drm_mode_create_scaling_mode_property(dev);
998 /*
999 * the initial panel fitting mode will be FULL_SCREEN.
1000 */
79e53945 1001
bb8a3560 1002 drm_connector_attach_property(&intel_connector->base,
3fbe18d6 1003 dev->mode_config.scaling_mode_property,
dd1ea37d 1004 DRM_MODE_SCALE_ASPECT);
29b99b48 1005 lvds_encoder->fitting_mode = DRM_MODE_SCALE_ASPECT;
79e53945
JB
1006 /*
1007 * LVDS discovery:
1008 * 1) check for EDID on DDC
1009 * 2) check for VBT data
1010 * 3) check to see if LVDS is already on
1011 * if none of the above, no panel
1012 * 4) make sure lid is open
1013 * if closed, act like it's not there for now
1014 */
1015
79e53945
JB
1016 /*
1017 * Attempt to get the fixed panel mode from DDC. Assume that the
1018 * preferred mode is the right one.
1019 */
29b99b48
JN
1020 lvds_encoder->edid = drm_get_edid(connector,
1021 intel_gmbus_get_adapter(dev_priv, pin));
1022 if (lvds_encoder->edid) {
1023 if (drm_add_edid_modes(connector, lvds_encoder->edid)) {
3f8ff0e7 1024 drm_mode_connector_update_edid_property(connector,
29b99b48 1025 lvds_encoder->edid);
3f8ff0e7 1026 } else {
29b99b48
JN
1027 kfree(lvds_encoder->edid);
1028 lvds_encoder->edid = NULL;
3f8ff0e7
CW
1029 }
1030 }
29b99b48 1031 if (!lvds_encoder->edid) {
788319d4
CW
1032 /* Didn't get an EDID, so
1033 * Set wide sync ranges so we get all modes
1034 * handed to valid_mode for checking
1035 */
1036 connector->display_info.min_vfreq = 0;
1037 connector->display_info.max_vfreq = 200;
1038 connector->display_info.min_hfreq = 0;
1039 connector->display_info.max_hfreq = 200;
1040 }
79e53945
JB
1041
1042 list_for_each_entry(scan, &connector->probed_modes, head) {
79e53945 1043 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
29b99b48
JN
1044 lvds_encoder->fixed_mode = drm_mode_duplicate(dev, scan);
1045 intel_find_lvds_downclock(dev, lvds_encoder->fixed_mode,
788319d4 1046 connector);
565dcd46 1047 goto out;
79e53945 1048 }
79e53945
JB
1049 }
1050
1051 /* Failed to get EDID, what about VBT? */
88631706 1052 if (dev_priv->lfp_lvds_vbt_mode) {
29b99b48 1053 lvds_encoder->fixed_mode =
88631706 1054 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
29b99b48
JN
1055 if (lvds_encoder->fixed_mode) {
1056 lvds_encoder->fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
e285f3cd
JB
1057 goto out;
1058 }
79e53945
JB
1059 }
1060
1061 /*
1062 * If we didn't get EDID, try checking if the panel is already turned
1063 * on. If so, assume that whatever is currently programmed is the
1064 * correct mode.
1065 */
541998a1 1066
f2b115e6 1067 /* Ironlake: FIXME if still fail, not try pipe mode now */
c619eed4 1068 if (HAS_PCH_SPLIT(dev))
541998a1
ZW
1069 goto failed;
1070
79e53945
JB
1071 lvds = I915_READ(LVDS);
1072 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
f875c15a 1073 crtc = intel_get_crtc_for_pipe(dev, pipe);
79e53945
JB
1074
1075 if (crtc && (lvds & LVDS_PORT_EN)) {
29b99b48
JN
1076 lvds_encoder->fixed_mode = intel_crtc_mode_get(dev, crtc);
1077 if (lvds_encoder->fixed_mode) {
1078 lvds_encoder->fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
565dcd46 1079 goto out;
79e53945
JB
1080 }
1081 }
1082
1083 /* If we still don't have a mode after all that, give up. */
29b99b48 1084 if (!lvds_encoder->fixed_mode)
79e53945
JB
1085 goto failed;
1086
79e53945 1087out:
24ded204
DV
1088 /*
1089 * Unlock registers and just
1090 * leave them unlocked
1091 */
c619eed4 1092 if (HAS_PCH_SPLIT(dev)) {
ed10fca9
KP
1093 I915_WRITE(PCH_PP_CONTROL,
1094 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
1095 } else {
ed10fca9
KP
1096 I915_WRITE(PP_CONTROL,
1097 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
541998a1 1098 }
c1c7af60
JB
1099 dev_priv->lid_notifier.notifier_call = intel_lid_notify;
1100 if (acpi_lid_notifier_register(&dev_priv->lid_notifier)) {
28c97730 1101 DRM_DEBUG_KMS("lid notifier registration failed\n");
c1c7af60
JB
1102 dev_priv->lid_notifier.notifier_call = NULL;
1103 }
a2565377
ZY
1104 /* keep the LVDS connector */
1105 dev_priv->int_lvds_connector = connector;
79e53945 1106 drm_sysfs_connector_add(connector);
aaa6fd2a
MG
1107
1108 intel_panel_setup_backlight(dev);
1109
c5d1b51d 1110 return true;
79e53945
JB
1111
1112failed:
8a4c47f3 1113 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
79e53945 1114 drm_connector_cleanup(connector);
1991bdfa 1115 drm_encoder_cleanup(encoder);
29b99b48 1116 kfree(lvds_encoder);
c7362c4d 1117 kfree(lvds_connector);
c5d1b51d 1118 return false;
79e53945 1119}