drm/i915: move PCH pfit controls into pipe_config
[linux-block.git] / drivers / gpu / drm / i915 / intel_lvds.c
CommitLineData
79e53945
JB
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 */
29
c1c7af60 30#include <acpi/button.h>
565dcd46 31#include <linux/dmi.h>
79e53945 32#include <linux/i2c.h>
5a0e3ad6 33#include <linux/slab.h>
760285e7
DH
34#include <drm/drmP.h>
35#include <drm/drm_crtc.h>
36#include <drm/drm_edid.h>
79e53945 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
79e53945 39#include "i915_drv.h"
e99da35f 40#include <linux/acpi.h>
79e53945 41
3fbe18d6 42/* Private structure for the integrated LVDS support */
c7362c4d
JN
43struct intel_lvds_connector {
44 struct intel_connector base;
788319d4 45
db1740a0 46 struct notifier_block lid_notifier;
c7362c4d
JN
47};
48
29b99b48 49struct intel_lvds_encoder {
ea5b213a 50 struct intel_encoder base;
788319d4 51
13c7d870 52 bool is_dual_link;
7dec0606 53 u32 reg;
788319d4 54
62165e0d 55 struct intel_lvds_connector *attached_connector;
3fbe18d6
ZY
56};
57
29b99b48 58static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
ea5b213a 59{
29b99b48 60 return container_of(encoder, struct intel_lvds_encoder, base.base);
ea5b213a
CW
61}
62
c7362c4d 63static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector)
788319d4 64{
c7362c4d 65 return container_of(connector, struct intel_lvds_connector, base.base);
788319d4
CW
66}
67
b1dc332c
DV
68static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
69 enum pipe *pipe)
70{
71 struct drm_device *dev = encoder->base.dev;
72 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606
DV
73 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
74 u32 tmp;
b1dc332c 75
7dec0606 76 tmp = I915_READ(lvds_encoder->reg);
b1dc332c
DV
77
78 if (!(tmp & LVDS_PORT_EN))
79 return false;
80
81 if (HAS_PCH_CPT(dev))
82 *pipe = PORT_TO_PIPE_CPT(tmp);
83 else
84 *pipe = PORT_TO_PIPE(tmp);
85
86 return true;
87}
88
fc683091
DV
89/* The LVDS pin pair needs to be on before the DPLLs are enabled.
90 * This is an exception to the general rule that mode_set doesn't turn
91 * things on.
92 */
93static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder)
94{
95 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
96 struct drm_device *dev = encoder->base.dev;
97 struct drm_i915_private *dev_priv = dev->dev_private;
98 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
99 struct drm_display_mode *fixed_mode =
100 lvds_encoder->attached_connector->base.panel.fixed_mode;
101 int pipe = intel_crtc->pipe;
102 u32 temp;
103
fc683091
DV
104 temp = I915_READ(lvds_encoder->reg);
105 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
62810e5a
DV
106
107 if (HAS_PCH_CPT(dev)) {
108 temp &= ~PORT_TRANS_SEL_MASK;
109 temp |= PORT_TRANS_SEL_CPT(pipe);
fc683091 110 } else {
62810e5a
DV
111 if (pipe == 1) {
112 temp |= LVDS_PIPEB_SELECT;
113 } else {
114 temp &= ~LVDS_PIPEB_SELECT;
115 }
fc683091 116 }
62810e5a 117
fc683091
DV
118 /* set the corresponsding LVDS_BORDER bit */
119 temp |= dev_priv->lvds_border_bits;
120 /* Set the B0-B3 data pairs corresponding to whether we're going to
121 * set the DPLLs for dual-channel mode or not.
122 */
123 if (lvds_encoder->is_dual_link)
124 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
125 else
126 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
127
128 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
129 * appropriately here, but we need to look more thoroughly into how
130 * panels behave in the two modes.
131 */
62810e5a
DV
132
133 /* Set the dithering flag on LVDS as needed, note that there is no
134 * special lvds dither control bit on pch-split platforms, dithering is
135 * only controlled through the PIPECONF reg. */
136 if (INTEL_INFO(dev)->gen == 4) {
d8b32247
DV
137 /* Bspec wording suggests that LVDS port dithering only exists
138 * for 18bpp panels. */
139 if (intel_crtc->config.dither &&
140 intel_crtc->config.pipe_bpp == 18)
fc683091
DV
141 temp |= LVDS_ENABLE_DITHER;
142 else
143 temp &= ~LVDS_ENABLE_DITHER;
144 }
145 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
146 if (fixed_mode->flags & DRM_MODE_FLAG_NHSYNC)
147 temp |= LVDS_HSYNC_POLARITY;
148 if (fixed_mode->flags & DRM_MODE_FLAG_NVSYNC)
149 temp |= LVDS_VSYNC_POLARITY;
150
151 I915_WRITE(lvds_encoder->reg, temp);
152}
153
79e53945
JB
154/**
155 * Sets the power state for the panel.
156 */
c22834ec 157static void intel_enable_lvds(struct intel_encoder *encoder)
79e53945 158{
c22834ec 159 struct drm_device *dev = encoder->base.dev;
29b99b48 160 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
c22834ec 161 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 162 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606 163 u32 ctl_reg, stat_reg;
541998a1 164
c619eed4 165 if (HAS_PCH_SPLIT(dev)) {
541998a1 166 ctl_reg = PCH_PP_CONTROL;
de842eff 167 stat_reg = PCH_PP_STATUS;
541998a1
ZW
168 } else {
169 ctl_reg = PP_CONTROL;
de842eff 170 stat_reg = PP_STATUS;
541998a1 171 }
79e53945 172
7dec0606 173 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
e9e331a8 174
2a1292fd 175 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
7dec0606 176 POSTING_READ(lvds_encoder->reg);
de842eff
KP
177 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
178 DRM_ERROR("timed out waiting for panel to power on\n");
2a1292fd 179
24ded204 180 intel_panel_enable_backlight(dev, intel_crtc->pipe);
2a1292fd
CW
181}
182
c22834ec 183static void intel_disable_lvds(struct intel_encoder *encoder)
2a1292fd 184{
c22834ec 185 struct drm_device *dev = encoder->base.dev;
29b99b48 186 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
2a1292fd 187 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606 188 u32 ctl_reg, stat_reg;
2a1292fd
CW
189
190 if (HAS_PCH_SPLIT(dev)) {
191 ctl_reg = PCH_PP_CONTROL;
de842eff 192 stat_reg = PCH_PP_STATUS;
2a1292fd
CW
193 } else {
194 ctl_reg = PP_CONTROL;
de842eff 195 stat_reg = PP_STATUS;
2a1292fd
CW
196 }
197
47356eb6 198 intel_panel_disable_backlight(dev);
2a1292fd
CW
199
200 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
de842eff
KP
201 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
202 DRM_ERROR("timed out waiting for panel to power off\n");
2a1292fd 203
7dec0606
DV
204 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
205 POSTING_READ(lvds_encoder->reg);
79e53945
JB
206}
207
79e53945
JB
208static int intel_lvds_mode_valid(struct drm_connector *connector,
209 struct drm_display_mode *mode)
210{
dd06f90e
JN
211 struct intel_connector *intel_connector = to_intel_connector(connector);
212 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
79e53945 213
788319d4
CW
214 if (mode->hdisplay > fixed_mode->hdisplay)
215 return MODE_PANEL;
216 if (mode->vdisplay > fixed_mode->vdisplay)
217 return MODE_PANEL;
79e53945
JB
218
219 return MODE_OK;
220}
221
7ae89233
DV
222static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
223 struct intel_crtc_config *pipe_config)
79e53945 224{
7ae89233 225 struct drm_device *dev = intel_encoder->base.dev;
79e53945 226 struct drm_i915_private *dev_priv = dev->dev_private;
7ae89233
DV
227 struct intel_lvds_encoder *lvds_encoder =
228 to_lvds_encoder(&intel_encoder->base);
4d891523
JN
229 struct intel_connector *intel_connector =
230 &lvds_encoder->attached_connector->base;
7ae89233 231 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
29b99b48 232 struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc;
4e53c2e0 233 unsigned int lvds_bpp;
9db4a9c7 234 int pipe;
79e53945
JB
235
236 /* Should never happen!! */
a6c45cf0 237 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
1ae8c0a5 238 DRM_ERROR("Can't support LVDS on pipe A\n");
79e53945
JB
239 return false;
240 }
241
29b99b48 242 if (intel_encoder_check_is_cloned(&lvds_encoder->base))
e24c5c29 243 return false;
1d8e1c75 244
4e53c2e0
DV
245 if ((I915_READ(lvds_encoder->reg) & LVDS_A3_POWER_MASK) ==
246 LVDS_A3_POWER_UP)
247 lvds_bpp = 8*3;
248 else
249 lvds_bpp = 6*3;
250
251 if (lvds_bpp != pipe_config->pipe_bpp) {
252 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
253 pipe_config->pipe_bpp, lvds_bpp);
254 pipe_config->pipe_bpp = lvds_bpp;
255 }
d8b32247 256
79e53945 257 /*
71677043 258 * We have timings from the BIOS for the panel, put them in
79e53945
JB
259 * to the adjusted mode. The CRTC will be set up for this mode,
260 * with the panel scaling set up to source from the H/VDisplay
261 * of the original mode.
262 */
4d891523 263 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
dd06f90e 264 adjusted_mode);
1d8e1c75
CW
265
266 if (HAS_PCH_SPLIT(dev)) {
5bfe2ac0
DV
267 pipe_config->has_pch_encoder = true;
268
b074cec8
JB
269 intel_pch_panel_fitting(intel_crtc, pipe_config,
270 intel_connector->panel.fitting_mode);
1d8e1c75 271 return true;
2dd24552
JB
272 } else {
273 intel_gmch_panel_fitting(intel_crtc, pipe_config,
274 intel_connector->panel.fitting_mode);
1d8e1c75 275 }
79e53945 276
3fbe18d6
ZY
277 /*
278 * Enable automatic panel scaling for non-native modes so that they fill
279 * the screen. Should be enabled before the pipe is enabled, according
280 * to register description and PRM.
281 * Change the value here to see the borders for debugging
282 */
9db4a9c7
JB
283 for_each_pipe(pipe)
284 I915_WRITE(BCLRPAT(pipe), 0);
3fbe18d6 285
f9bef081 286 drm_mode_set_crtcinfo(adjusted_mode, 0);
7ae89233 287 pipe_config->timings_set = true;
f9bef081 288
79e53945
JB
289 /*
290 * XXX: It would be nice to support lower refresh rates on the
291 * panels to reduce power consumption, and perhaps match the
292 * user's requested refresh rate.
293 */
294
295 return true;
296}
297
79e53945
JB
298static void intel_lvds_mode_set(struct drm_encoder *encoder,
299 struct drm_display_mode *mode,
300 struct drm_display_mode *adjusted_mode)
301{
79e53945
JB
302 /*
303 * The LVDS pin pair will already have been turned on in the
304 * intel_crtc_mode_set since it has a large impact on the DPLL
305 * settings.
306 */
79e53945
JB
307}
308
309/**
310 * Detect the LVDS connection.
311 *
b42d4c5c
JB
312 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means
313 * connected and closed means disconnected. We also send hotplug events as
314 * needed, using lid status notification from the input layer.
79e53945 315 */
7b334fcb 316static enum drm_connector_status
930a9e28 317intel_lvds_detect(struct drm_connector *connector, bool force)
79e53945 318{
7b9c5abe 319 struct drm_device *dev = connector->dev;
6ee3b5a1 320 enum drm_connector_status status;
b42d4c5c 321
fe16d949
CW
322 status = intel_panel_detect(dev);
323 if (status != connector_status_unknown)
324 return status;
01fe9dbd 325
6ee3b5a1 326 return connector_status_connected;
79e53945
JB
327}
328
329/**
330 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
331 */
332static int intel_lvds_get_modes(struct drm_connector *connector)
333{
62165e0d 334 struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);
79e53945 335 struct drm_device *dev = connector->dev;
788319d4 336 struct drm_display_mode *mode;
79e53945 337
9cd300e0 338 /* use cached edid if we have one */
2aa4f099 339 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
9cd300e0 340 return drm_add_edid_modes(connector, lvds_connector->base.edid);
79e53945 341
dd06f90e 342 mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode);
311bd68e 343 if (mode == NULL)
788319d4 344 return 0;
79e53945 345
788319d4
CW
346 drm_mode_probed_add(connector, mode);
347 return 1;
79e53945
JB
348}
349
0544edfd
TB
350static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
351{
bc0daf48 352 DRM_INFO("Skipping forced modeset for %s\n", id->ident);
0544edfd
TB
353 return 1;
354}
355
356/* The GPU hangs up on these systems if modeset is performed on LID open */
357static const struct dmi_system_id intel_no_modeset_on_lid[] = {
358 {
359 .callback = intel_no_modeset_on_lid_dmi_callback,
360 .ident = "Toshiba Tecra A11",
361 .matches = {
362 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
363 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
364 },
365 },
366
367 { } /* terminating entry */
368};
369
c9354c85 370/*
b8efb17b
ZR
371 * Lid events. Note the use of 'modeset':
372 * - we set it to MODESET_ON_LID_OPEN on lid close,
373 * and set it to MODESET_DONE on open
c9354c85 374 * - we use it as a "only once" bit (ie we ignore
b8efb17b
ZR
375 * duplicate events where it was already properly set)
376 * - the suspend/resume paths will set it to
377 * MODESET_SUSPENDED and ignore the lid open event,
378 * because they restore the mode ("lid open").
c9354c85 379 */
c1c7af60
JB
380static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
381 void *unused)
382{
db1740a0
JN
383 struct intel_lvds_connector *lvds_connector =
384 container_of(nb, struct intel_lvds_connector, lid_notifier);
385 struct drm_connector *connector = &lvds_connector->base.base;
386 struct drm_device *dev = connector->dev;
387 struct drm_i915_private *dev_priv = dev->dev_private;
c1c7af60 388
2fb4e61d
AW
389 if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
390 return NOTIFY_OK;
391
b8efb17b
ZR
392 mutex_lock(&dev_priv->modeset_restore_lock);
393 if (dev_priv->modeset_restore == MODESET_SUSPENDED)
394 goto exit;
a2565377
ZY
395 /*
396 * check and update the status of LVDS connector after receiving
397 * the LID nofication event.
398 */
db1740a0 399 connector->status = connector->funcs->detect(connector, false);
7b334fcb 400
0544edfd
TB
401 /* Don't force modeset on machines where it causes a GPU lockup */
402 if (dmi_check_system(intel_no_modeset_on_lid))
b8efb17b 403 goto exit;
c9354c85 404 if (!acpi_lid_open()) {
b8efb17b
ZR
405 /* do modeset on next lid open event */
406 dev_priv->modeset_restore = MODESET_ON_LID_OPEN;
407 goto exit;
06891e27 408 }
c1c7af60 409
b8efb17b
ZR
410 if (dev_priv->modeset_restore == MODESET_DONE)
411 goto exit;
c9354c85 412
a0e99e68 413 drm_modeset_lock_all(dev);
45e2b5f6 414 intel_modeset_setup_hw_state(dev, true);
a0e99e68 415 drm_modeset_unlock_all(dev);
06324194 416
b8efb17b
ZR
417 dev_priv->modeset_restore = MODESET_DONE;
418
419exit:
420 mutex_unlock(&dev_priv->modeset_restore_lock);
c1c7af60
JB
421 return NOTIFY_OK;
422}
423
79e53945
JB
424/**
425 * intel_lvds_destroy - unregister and free LVDS structures
426 * @connector: connector to free
427 *
428 * Unregister the DDC bus for this connector then free the driver private
429 * structure.
430 */
431static void intel_lvds_destroy(struct drm_connector *connector)
432{
db1740a0
JN
433 struct intel_lvds_connector *lvds_connector =
434 to_lvds_connector(connector);
79e53945 435
db1740a0
JN
436 if (lvds_connector->lid_notifier.notifier_call)
437 acpi_lid_notifier_unregister(&lvds_connector->lid_notifier);
79e53945 438
9cd300e0
JN
439 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
440 kfree(lvds_connector->base.edid);
441
1d508706 442 intel_panel_fini(&lvds_connector->base.panel);
aaa6fd2a 443
79e53945
JB
444 drm_sysfs_connector_remove(connector);
445 drm_connector_cleanup(connector);
446 kfree(connector);
447}
448
335041ed
JB
449static int intel_lvds_set_property(struct drm_connector *connector,
450 struct drm_property *property,
451 uint64_t value)
452{
4d891523 453 struct intel_connector *intel_connector = to_intel_connector(connector);
3fbe18d6 454 struct drm_device *dev = connector->dev;
3fbe18d6 455
788319d4 456 if (property == dev->mode_config.scaling_mode_property) {
62165e0d 457 struct drm_crtc *crtc;
bb8a3560 458
53bd8389
JB
459 if (value == DRM_MODE_SCALE_NONE) {
460 DRM_DEBUG_KMS("no scaling not supported\n");
788319d4 461 return -EINVAL;
3fbe18d6 462 }
788319d4 463
4d891523 464 if (intel_connector->panel.fitting_mode == value) {
3fbe18d6
ZY
465 /* the LVDS scaling property is not changed */
466 return 0;
467 }
4d891523 468 intel_connector->panel.fitting_mode = value;
62165e0d
JN
469
470 crtc = intel_attached_encoder(connector)->base.crtc;
3fbe18d6
ZY
471 if (crtc && crtc->enabled) {
472 /*
473 * If the CRTC is enabled, the display will be changed
474 * according to the new panel fitting mode.
475 */
c0c36b94 476 intel_crtc_restore_mode(crtc);
3fbe18d6
ZY
477 }
478 }
479
335041ed
JB
480 return 0;
481}
482
79e53945 483static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = {
79e53945 484 .mode_set = intel_lvds_mode_set,
79e53945
JB
485};
486
487static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
488 .get_modes = intel_lvds_get_modes,
489 .mode_valid = intel_lvds_mode_valid,
df0e9248 490 .best_encoder = intel_best_encoder,
79e53945
JB
491};
492
493static const struct drm_connector_funcs intel_lvds_connector_funcs = {
c22834ec 494 .dpms = intel_connector_dpms,
79e53945
JB
495 .detect = intel_lvds_detect,
496 .fill_modes = drm_helper_probe_single_connector_modes,
335041ed 497 .set_property = intel_lvds_set_property,
79e53945
JB
498 .destroy = intel_lvds_destroy,
499};
500
79e53945 501static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
ea5b213a 502 .destroy = intel_encoder_destroy,
79e53945
JB
503};
504
425d244c
JW
505static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
506{
bc0daf48 507 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
425d244c
JW
508 return 1;
509}
79e53945 510
425d244c 511/* These systems claim to have LVDS, but really don't */
93c05f22 512static const struct dmi_system_id intel_no_lvds[] = {
425d244c
JW
513 {
514 .callback = intel_no_lvds_dmi_callback,
515 .ident = "Apple Mac Mini (Core series)",
516 .matches = {
98acd46f 517 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
518 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
519 },
520 },
521 {
522 .callback = intel_no_lvds_dmi_callback,
523 .ident = "Apple Mac Mini (Core 2 series)",
524 .matches = {
98acd46f 525 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
526 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
527 },
528 },
529 {
530 .callback = intel_no_lvds_dmi_callback,
531 .ident = "MSI IM-945GSE-A",
532 .matches = {
533 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
534 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
535 },
536 },
537 {
538 .callback = intel_no_lvds_dmi_callback,
539 .ident = "Dell Studio Hybrid",
540 .matches = {
541 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
542 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
543 },
544 },
70aa96ca
JW
545 {
546 .callback = intel_no_lvds_dmi_callback,
b066254f
PC
547 .ident = "Dell OptiPlex FX170",
548 .matches = {
549 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
550 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
551 },
552 },
553 {
554 .callback = intel_no_lvds_dmi_callback,
70aa96ca
JW
555 .ident = "AOpen Mini PC",
556 .matches = {
557 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
558 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
559 },
560 },
ed8c754b
TV
561 {
562 .callback = intel_no_lvds_dmi_callback,
563 .ident = "AOpen Mini PC MP915",
564 .matches = {
565 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
566 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
567 },
568 },
22ab70d3
KP
569 {
570 .callback = intel_no_lvds_dmi_callback,
571 .ident = "AOpen i915GMm-HFS",
572 .matches = {
573 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
574 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
575 },
576 },
e57b6886
DV
577 {
578 .callback = intel_no_lvds_dmi_callback,
579 .ident = "AOpen i45GMx-I",
580 .matches = {
581 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
582 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
583 },
584 },
fa0864b2
MC
585 {
586 .callback = intel_no_lvds_dmi_callback,
587 .ident = "Aopen i945GTt-VFA",
588 .matches = {
589 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
590 },
591 },
9875557e
SB
592 {
593 .callback = intel_no_lvds_dmi_callback,
594 .ident = "Clientron U800",
595 .matches = {
596 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
597 DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
598 },
599 },
6a574b5b 600 {
44306ab3
JS
601 .callback = intel_no_lvds_dmi_callback,
602 .ident = "Clientron E830",
603 .matches = {
604 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
605 DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
606 },
607 },
608 {
6a574b5b
HG
609 .callback = intel_no_lvds_dmi_callback,
610 .ident = "Asus EeeBox PC EB1007",
611 .matches = {
612 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
613 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
614 },
615 },
0999bbe0
AJ
616 {
617 .callback = intel_no_lvds_dmi_callback,
618 .ident = "Asus AT5NM10T-I",
619 .matches = {
620 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
621 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
622 },
623 },
33471119
JBG
624 {
625 .callback = intel_no_lvds_dmi_callback,
626 .ident = "Hewlett-Packard HP t5740e Thin Client",
627 .matches = {
628 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
629 DMI_MATCH(DMI_PRODUCT_NAME, "HP t5740e Thin Client"),
630 },
631 },
f5b8a7ed
MG
632 {
633 .callback = intel_no_lvds_dmi_callback,
634 .ident = "Hewlett-Packard t5745",
635 .matches = {
636 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 637 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
f5b8a7ed
MG
638 },
639 },
640 {
641 .callback = intel_no_lvds_dmi_callback,
642 .ident = "Hewlett-Packard st5747",
643 .matches = {
644 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 645 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
f5b8a7ed
MG
646 },
647 },
97effadb
AA
648 {
649 .callback = intel_no_lvds_dmi_callback,
650 .ident = "MSI Wind Box DC500",
651 .matches = {
652 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
653 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
654 },
655 },
a51d4ed0
CW
656 {
657 .callback = intel_no_lvds_dmi_callback,
658 .ident = "Gigabyte GA-D525TUD",
659 .matches = {
660 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
661 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
662 },
663 },
c31407a3
CW
664 {
665 .callback = intel_no_lvds_dmi_callback,
666 .ident = "Supermicro X7SPA-H",
667 .matches = {
668 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
669 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
670 },
671 },
9e9dd0e8
CL
672 {
673 .callback = intel_no_lvds_dmi_callback,
674 .ident = "Fujitsu Esprimo Q900",
675 .matches = {
676 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
677 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
678 },
679 },
425d244c
JW
680
681 { } /* terminating entry */
682};
79e53945 683
18f9ed12
ZY
684/**
685 * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID
686 * @dev: drm device
687 * @connector: LVDS connector
688 *
689 * Find the reduced downclock for LVDS in EDID.
690 */
691static void intel_find_lvds_downclock(struct drm_device *dev,
788319d4
CW
692 struct drm_display_mode *fixed_mode,
693 struct drm_connector *connector)
18f9ed12
ZY
694{
695 struct drm_i915_private *dev_priv = dev->dev_private;
788319d4 696 struct drm_display_mode *scan;
18f9ed12
ZY
697 int temp_downclock;
698
788319d4 699 temp_downclock = fixed_mode->clock;
18f9ed12
ZY
700 list_for_each_entry(scan, &connector->probed_modes, head) {
701 /*
702 * If one mode has the same resolution with the fixed_panel
703 * mode while they have the different refresh rate, it means
704 * that the reduced downclock is found for the LVDS. In such
705 * case we can set the different FPx0/1 to dynamically select
706 * between low and high frequency.
707 */
788319d4
CW
708 if (scan->hdisplay == fixed_mode->hdisplay &&
709 scan->hsync_start == fixed_mode->hsync_start &&
710 scan->hsync_end == fixed_mode->hsync_end &&
711 scan->htotal == fixed_mode->htotal &&
712 scan->vdisplay == fixed_mode->vdisplay &&
713 scan->vsync_start == fixed_mode->vsync_start &&
714 scan->vsync_end == fixed_mode->vsync_end &&
715 scan->vtotal == fixed_mode->vtotal) {
18f9ed12
ZY
716 if (scan->clock < temp_downclock) {
717 /*
718 * The downclock is already found. But we
719 * expect to find the lower downclock.
720 */
721 temp_downclock = scan->clock;
722 }
723 }
724 }
788319d4 725 if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) {
18f9ed12
ZY
726 /* We found the downclock for LVDS. */
727 dev_priv->lvds_downclock_avail = 1;
728 dev_priv->lvds_downclock = temp_downclock;
729 DRM_DEBUG_KMS("LVDS downclock is found in EDID. "
788319d4
CW
730 "Normal clock %dKhz, downclock %dKhz\n",
731 fixed_mode->clock, temp_downclock);
18f9ed12 732 }
18f9ed12
ZY
733}
734
7cf4f69d
ZY
735/*
736 * Enumerate the child dev array parsed from VBT to check whether
737 * the LVDS is present.
738 * If it is present, return 1.
739 * If it is not present, return false.
740 * If no child dev is parsed from VBT, it assumes that the LVDS is present.
7cf4f69d 741 */
270eea0f
CW
742static bool lvds_is_present_in_vbt(struct drm_device *dev,
743 u8 *i2c_pin)
7cf4f69d
ZY
744{
745 struct drm_i915_private *dev_priv = dev->dev_private;
425904dd 746 int i;
7cf4f69d
ZY
747
748 if (!dev_priv->child_dev_num)
425904dd 749 return true;
7cf4f69d 750
7cf4f69d 751 for (i = 0; i < dev_priv->child_dev_num; i++) {
425904dd
CW
752 struct child_device_config *child = dev_priv->child_dev + i;
753
754 /* If the device type is not LFP, continue.
755 * We have to check both the new identifiers as well as the
756 * old for compatibility with some BIOSes.
7cf4f69d 757 */
425904dd
CW
758 if (child->device_type != DEVICE_TYPE_INT_LFP &&
759 child->device_type != DEVICE_TYPE_LFP)
7cf4f69d
ZY
760 continue;
761
3bd7d909
DK
762 if (intel_gmbus_is_port_valid(child->i2c_pin))
763 *i2c_pin = child->i2c_pin;
270eea0f 764
425904dd
CW
765 /* However, we cannot trust the BIOS writers to populate
766 * the VBT correctly. Since LVDS requires additional
767 * information from AIM blocks, a non-zero addin offset is
768 * a good indicator that the LVDS is actually present.
7cf4f69d 769 */
425904dd
CW
770 if (child->addin_offset)
771 return true;
772
773 /* But even then some BIOS writers perform some black magic
774 * and instantiate the device without reference to any
775 * additional data. Trust that if the VBT was written into
776 * the OpRegion then they have validated the LVDS's existence.
777 */
778 if (dev_priv->opregion.vbt)
779 return true;
7cf4f69d 780 }
425904dd
CW
781
782 return false;
7cf4f69d
ZY
783}
784
1974cad0
DV
785static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
786{
787 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
788 return 1;
789}
790
791static const struct dmi_system_id intel_dual_link_lvds[] = {
792 {
793 .callback = intel_dual_link_lvds_callback,
794 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
795 .matches = {
796 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
797 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
798 },
799 },
800 { } /* terminating entry */
801};
802
803bool intel_is_dual_link_lvds(struct drm_device *dev)
13c7d870
DV
804{
805 struct intel_encoder *encoder;
806 struct intel_lvds_encoder *lvds_encoder;
807
808 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
809 base.head) {
810 if (encoder->type == INTEL_OUTPUT_LVDS) {
811 lvds_encoder = to_lvds_encoder(&encoder->base);
812
813 return lvds_encoder->is_dual_link;
814 }
815 }
816
817 return false;
818}
819
7dec0606 820static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
1974cad0 821{
7dec0606 822 struct drm_device *dev = lvds_encoder->base.base.dev;
1974cad0
DV
823 unsigned int val;
824 struct drm_i915_private *dev_priv = dev->dev_private;
1974cad0
DV
825
826 /* use the module option value if specified */
827 if (i915_lvds_channel_mode > 0)
828 return i915_lvds_channel_mode == 2;
829
830 if (dmi_check_system(intel_dual_link_lvds))
831 return true;
832
13c7d870
DV
833 /* BIOS should set the proper LVDS register value at boot, but
834 * in reality, it doesn't set the value when the lid is closed;
835 * we need to check "the value to be set" in VBT when LVDS
836 * register is uninitialized.
837 */
7dec0606 838 val = I915_READ(lvds_encoder->reg);
13c7d870
DV
839 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
840 val = dev_priv->bios_lvds_val;
841
1974cad0
DV
842 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
843}
844
f3cfcba6
CW
845static bool intel_lvds_supported(struct drm_device *dev)
846{
847 /* With the introduction of the PCH we gained a dedicated
848 * LVDS presence pin, use it. */
311e359c 849 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
f3cfcba6
CW
850 return true;
851
852 /* Otherwise LVDS was only attached to mobile products,
853 * except for the inglorious 830gm */
311e359c
PZ
854 if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
855 return true;
856
857 return false;
f3cfcba6
CW
858}
859
79e53945
JB
860/**
861 * intel_lvds_init - setup LVDS connectors on this device
862 * @dev: drm device
863 *
864 * Create the connector, register the LVDS DDC bus, and try to figure out what
865 * modes we can display on the LVDS panel (if present).
866 */
c5d1b51d 867bool intel_lvds_init(struct drm_device *dev)
79e53945
JB
868{
869 struct drm_i915_private *dev_priv = dev->dev_private;
29b99b48 870 struct intel_lvds_encoder *lvds_encoder;
21d40d37 871 struct intel_encoder *intel_encoder;
c7362c4d 872 struct intel_lvds_connector *lvds_connector;
bb8a3560 873 struct intel_connector *intel_connector;
79e53945
JB
874 struct drm_connector *connector;
875 struct drm_encoder *encoder;
876 struct drm_display_mode *scan; /* *modes, *bios_mode; */
dd06f90e 877 struct drm_display_mode *fixed_mode = NULL;
9cd300e0 878 struct edid *edid;
79e53945
JB
879 struct drm_crtc *crtc;
880 u32 lvds;
270eea0f
CW
881 int pipe;
882 u8 pin;
79e53945 883
f3cfcba6
CW
884 if (!intel_lvds_supported(dev))
885 return false;
886
425d244c
JW
887 /* Skip init on machines we know falsely report LVDS */
888 if (dmi_check_system(intel_no_lvds))
c5d1b51d 889 return false;
565dcd46 890
270eea0f
CW
891 pin = GMBUS_PORT_PANEL;
892 if (!lvds_is_present_in_vbt(dev, &pin)) {
11ba1592 893 DRM_DEBUG_KMS("LVDS is not present in VBT\n");
c5d1b51d 894 return false;
38b3037e 895 }
e99da35f 896
c619eed4 897 if (HAS_PCH_SPLIT(dev)) {
541998a1 898 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
c5d1b51d 899 return false;
5ceb0f9b 900 if (dev_priv->edp.support) {
28c97730 901 DRM_DEBUG_KMS("disable LVDS for eDP support\n");
c5d1b51d 902 return false;
32f9d658 903 }
541998a1
ZW
904 }
905
29b99b48
JN
906 lvds_encoder = kzalloc(sizeof(struct intel_lvds_encoder), GFP_KERNEL);
907 if (!lvds_encoder)
c5d1b51d 908 return false;
79e53945 909
c7362c4d
JN
910 lvds_connector = kzalloc(sizeof(struct intel_lvds_connector), GFP_KERNEL);
911 if (!lvds_connector) {
29b99b48 912 kfree(lvds_encoder);
c5d1b51d 913 return false;
bb8a3560
ZW
914 }
915
62165e0d
JN
916 lvds_encoder->attached_connector = lvds_connector;
917
29b99b48 918 intel_encoder = &lvds_encoder->base;
4ef69c7a 919 encoder = &intel_encoder->base;
c7362c4d 920 intel_connector = &lvds_connector->base;
ea5b213a 921 connector = &intel_connector->base;
bb8a3560 922 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
79e53945
JB
923 DRM_MODE_CONNECTOR_LVDS);
924
4ef69c7a 925 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
79e53945
JB
926 DRM_MODE_ENCODER_LVDS);
927
c22834ec 928 intel_encoder->enable = intel_enable_lvds;
fc683091 929 intel_encoder->pre_pll_enable = intel_pre_pll_enable_lvds;
7ae89233 930 intel_encoder->compute_config = intel_lvds_compute_config;
c22834ec 931 intel_encoder->disable = intel_disable_lvds;
b1dc332c
DV
932 intel_encoder->get_hw_state = intel_lvds_get_hw_state;
933 intel_connector->get_hw_state = intel_connector_get_hw_state;
c22834ec 934
df0e9248 935 intel_connector_attach_encoder(intel_connector, intel_encoder);
21d40d37 936 intel_encoder->type = INTEL_OUTPUT_LVDS;
79e53945 937
66a9278e 938 intel_encoder->cloneable = false;
27f8227b
JB
939 if (HAS_PCH_SPLIT(dev))
940 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
0b9f43a0
DV
941 else if (IS_GEN4(dev))
942 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
27f8227b
JB
943 else
944 intel_encoder->crtc_mask = (1 << 1);
945
79e53945
JB
946 drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs);
947 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
948 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
949 connector->interlace_allowed = false;
950 connector->doublescan_allowed = false;
951
7dec0606
DV
952 if (HAS_PCH_SPLIT(dev)) {
953 lvds_encoder->reg = PCH_LVDS;
954 } else {
955 lvds_encoder->reg = LVDS;
956 }
957
3fbe18d6
ZY
958 /* create the scaling mode property */
959 drm_mode_create_scaling_mode_property(dev);
662595df 960 drm_object_attach_property(&connector->base,
3fbe18d6 961 dev->mode_config.scaling_mode_property,
dd1ea37d 962 DRM_MODE_SCALE_ASPECT);
4d891523 963 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
79e53945
JB
964 /*
965 * LVDS discovery:
966 * 1) check for EDID on DDC
967 * 2) check for VBT data
968 * 3) check to see if LVDS is already on
969 * if none of the above, no panel
970 * 4) make sure lid is open
971 * if closed, act like it's not there for now
972 */
973
79e53945
JB
974 /*
975 * Attempt to get the fixed panel mode from DDC. Assume that the
976 * preferred mode is the right one.
977 */
9cd300e0
JN
978 edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv, pin));
979 if (edid) {
980 if (drm_add_edid_modes(connector, edid)) {
3f8ff0e7 981 drm_mode_connector_update_edid_property(connector,
9cd300e0 982 edid);
3f8ff0e7 983 } else {
9cd300e0
JN
984 kfree(edid);
985 edid = ERR_PTR(-EINVAL);
3f8ff0e7 986 }
9cd300e0
JN
987 } else {
988 edid = ERR_PTR(-ENOENT);
3f8ff0e7 989 }
9cd300e0
JN
990 lvds_connector->base.edid = edid;
991
992 if (IS_ERR_OR_NULL(edid)) {
788319d4
CW
993 /* Didn't get an EDID, so
994 * Set wide sync ranges so we get all modes
995 * handed to valid_mode for checking
996 */
997 connector->display_info.min_vfreq = 0;
998 connector->display_info.max_vfreq = 200;
999 connector->display_info.min_hfreq = 0;
1000 connector->display_info.max_hfreq = 200;
1001 }
79e53945
JB
1002
1003 list_for_each_entry(scan, &connector->probed_modes, head) {
79e53945 1004 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
6a9d51b7
CW
1005 DRM_DEBUG_KMS("using preferred mode from EDID: ");
1006 drm_mode_debug_printmodeline(scan);
1007
dd06f90e 1008 fixed_mode = drm_mode_duplicate(dev, scan);
6a9d51b7
CW
1009 if (fixed_mode) {
1010 intel_find_lvds_downclock(dev, fixed_mode,
1011 connector);
1012 goto out;
1013 }
79e53945 1014 }
79e53945
JB
1015 }
1016
1017 /* Failed to get EDID, what about VBT? */
88631706 1018 if (dev_priv->lfp_lvds_vbt_mode) {
6a9d51b7
CW
1019 DRM_DEBUG_KMS("using mode from VBT: ");
1020 drm_mode_debug_printmodeline(dev_priv->lfp_lvds_vbt_mode);
1021
dd06f90e
JN
1022 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1023 if (fixed_mode) {
1024 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
e285f3cd
JB
1025 goto out;
1026 }
79e53945
JB
1027 }
1028
1029 /*
1030 * If we didn't get EDID, try checking if the panel is already turned
1031 * on. If so, assume that whatever is currently programmed is the
1032 * correct mode.
1033 */
541998a1 1034
f2b115e6 1035 /* Ironlake: FIXME if still fail, not try pipe mode now */
c619eed4 1036 if (HAS_PCH_SPLIT(dev))
541998a1
ZW
1037 goto failed;
1038
79e53945
JB
1039 lvds = I915_READ(LVDS);
1040 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
f875c15a 1041 crtc = intel_get_crtc_for_pipe(dev, pipe);
79e53945
JB
1042
1043 if (crtc && (lvds & LVDS_PORT_EN)) {
dd06f90e
JN
1044 fixed_mode = intel_crtc_mode_get(dev, crtc);
1045 if (fixed_mode) {
6a9d51b7
CW
1046 DRM_DEBUG_KMS("using current (BIOS) mode: ");
1047 drm_mode_debug_printmodeline(fixed_mode);
dd06f90e 1048 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
565dcd46 1049 goto out;
79e53945
JB
1050 }
1051 }
1052
1053 /* If we still don't have a mode after all that, give up. */
dd06f90e 1054 if (!fixed_mode)
79e53945
JB
1055 goto failed;
1056
79e53945 1057out:
7dec0606 1058 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
13c7d870
DV
1059 DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
1060 lvds_encoder->is_dual_link ? "dual" : "single");
1061
24ded204
DV
1062 /*
1063 * Unlock registers and just
1064 * leave them unlocked
1065 */
c619eed4 1066 if (HAS_PCH_SPLIT(dev)) {
ed10fca9
KP
1067 I915_WRITE(PCH_PP_CONTROL,
1068 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
1069 } else {
ed10fca9
KP
1070 I915_WRITE(PP_CONTROL,
1071 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
541998a1 1072 }
db1740a0
JN
1073 lvds_connector->lid_notifier.notifier_call = intel_lid_notify;
1074 if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) {
28c97730 1075 DRM_DEBUG_KMS("lid notifier registration failed\n");
db1740a0 1076 lvds_connector->lid_notifier.notifier_call = NULL;
c1c7af60 1077 }
79e53945 1078 drm_sysfs_connector_add(connector);
aaa6fd2a 1079
dd06f90e 1080 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 1081 intel_panel_setup_backlight(connector);
aaa6fd2a 1082
c5d1b51d 1083 return true;
79e53945
JB
1084
1085failed:
8a4c47f3 1086 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
79e53945 1087 drm_connector_cleanup(connector);
1991bdfa 1088 drm_encoder_cleanup(encoder);
dd06f90e
JN
1089 if (fixed_mode)
1090 drm_mode_destroy(dev, fixed_mode);
29b99b48 1091 kfree(lvds_encoder);
c7362c4d 1092 kfree(lvds_connector);
c5d1b51d 1093 return false;
79e53945 1094}