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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Dave Airlie <airlied@linux.ie> | |
27 | * Jesse Barnes <jesse.barnes@intel.com> | |
28 | */ | |
29 | ||
565dcd46 | 30 | #include <linux/dmi.h> |
79e53945 JB |
31 | #include <linux/i2c.h> |
32 | #include "drmP.h" | |
33 | #include "drm.h" | |
34 | #include "drm_crtc.h" | |
35 | #include "drm_edid.h" | |
36 | #include "intel_drv.h" | |
37 | #include "i915_drm.h" | |
38 | #include "i915_drv.h" | |
39 | ||
7fb85bfb | 40 | #define I915_LVDS "i915_lvds" |
41 | ||
79e53945 JB |
42 | /** |
43 | * Sets the backlight level. | |
44 | * | |
45 | * \param level backlight level, from 0 to intel_lvds_get_max_backlight(). | |
46 | */ | |
47 | static void intel_lvds_set_backlight(struct drm_device *dev, int level) | |
48 | { | |
49 | struct drm_i915_private *dev_priv = dev->dev_private; | |
541998a1 | 50 | u32 blc_pwm_ctl, reg; |
79e53945 | 51 | |
541998a1 ZW |
52 | if (IS_IGDNG(dev)) |
53 | reg = BLC_PWM_CPU_CTL; | |
54 | else | |
55 | reg = BLC_PWM_CTL; | |
79e53945 | 56 | |
541998a1 ZW |
57 | blc_pwm_ctl = I915_READ(reg) & ~BACKLIGHT_DUTY_CYCLE_MASK; |
58 | I915_WRITE(reg, (blc_pwm_ctl | | |
79e53945 JB |
59 | (level << BACKLIGHT_DUTY_CYCLE_SHIFT))); |
60 | } | |
61 | ||
62 | /** | |
63 | * Returns the maximum level of the backlight duty cycle field. | |
64 | */ | |
65 | static u32 intel_lvds_get_max_backlight(struct drm_device *dev) | |
66 | { | |
67 | struct drm_i915_private *dev_priv = dev->dev_private; | |
541998a1 ZW |
68 | u32 reg; |
69 | ||
70 | if (IS_IGDNG(dev)) | |
71 | reg = BLC_PWM_PCH_CTL2; | |
72 | else | |
73 | reg = BLC_PWM_CTL; | |
79e53945 | 74 | |
541998a1 | 75 | return ((I915_READ(reg) & BACKLIGHT_MODULATION_FREQ_MASK) >> |
79e53945 JB |
76 | BACKLIGHT_MODULATION_FREQ_SHIFT) * 2; |
77 | } | |
78 | ||
79 | /** | |
80 | * Sets the power state for the panel. | |
81 | */ | |
82 | static void intel_lvds_set_power(struct drm_device *dev, bool on) | |
83 | { | |
84 | struct drm_i915_private *dev_priv = dev->dev_private; | |
541998a1 ZW |
85 | u32 pp_status, ctl_reg, status_reg; |
86 | ||
87 | if (IS_IGDNG(dev)) { | |
88 | ctl_reg = PCH_PP_CONTROL; | |
89 | status_reg = PCH_PP_STATUS; | |
90 | } else { | |
91 | ctl_reg = PP_CONTROL; | |
92 | status_reg = PP_STATUS; | |
93 | } | |
79e53945 JB |
94 | |
95 | if (on) { | |
541998a1 | 96 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) | |
79e53945 JB |
97 | POWER_TARGET_ON); |
98 | do { | |
541998a1 | 99 | pp_status = I915_READ(status_reg); |
79e53945 JB |
100 | } while ((pp_status & PP_ON) == 0); |
101 | ||
102 | intel_lvds_set_backlight(dev, dev_priv->backlight_duty_cycle); | |
103 | } else { | |
104 | intel_lvds_set_backlight(dev, 0); | |
105 | ||
541998a1 | 106 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) & |
79e53945 JB |
107 | ~POWER_TARGET_ON); |
108 | do { | |
541998a1 | 109 | pp_status = I915_READ(status_reg); |
79e53945 JB |
110 | } while (pp_status & PP_ON); |
111 | } | |
112 | } | |
113 | ||
114 | static void intel_lvds_dpms(struct drm_encoder *encoder, int mode) | |
115 | { | |
116 | struct drm_device *dev = encoder->dev; | |
117 | ||
118 | if (mode == DRM_MODE_DPMS_ON) | |
119 | intel_lvds_set_power(dev, true); | |
120 | else | |
121 | intel_lvds_set_power(dev, false); | |
122 | ||
123 | /* XXX: We never power down the LVDS pairs. */ | |
124 | } | |
125 | ||
126 | static void intel_lvds_save(struct drm_connector *connector) | |
127 | { | |
128 | struct drm_device *dev = connector->dev; | |
129 | struct drm_i915_private *dev_priv = dev->dev_private; | |
541998a1 ZW |
130 | u32 pp_on_reg, pp_off_reg, pp_ctl_reg, pp_div_reg; |
131 | u32 pwm_ctl_reg; | |
132 | ||
133 | if (IS_IGDNG(dev)) { | |
134 | pp_on_reg = PCH_PP_ON_DELAYS; | |
135 | pp_off_reg = PCH_PP_OFF_DELAYS; | |
136 | pp_ctl_reg = PCH_PP_CONTROL; | |
137 | pp_div_reg = PCH_PP_DIVISOR; | |
138 | pwm_ctl_reg = BLC_PWM_CPU_CTL; | |
139 | } else { | |
140 | pp_on_reg = PP_ON_DELAYS; | |
141 | pp_off_reg = PP_OFF_DELAYS; | |
142 | pp_ctl_reg = PP_CONTROL; | |
143 | pp_div_reg = PP_DIVISOR; | |
144 | pwm_ctl_reg = BLC_PWM_CTL; | |
145 | } | |
79e53945 | 146 | |
541998a1 ZW |
147 | dev_priv->savePP_ON = I915_READ(pp_on_reg); |
148 | dev_priv->savePP_OFF = I915_READ(pp_off_reg); | |
149 | dev_priv->savePP_CONTROL = I915_READ(pp_ctl_reg); | |
150 | dev_priv->savePP_DIVISOR = I915_READ(pp_div_reg); | |
151 | dev_priv->saveBLC_PWM_CTL = I915_READ(pwm_ctl_reg); | |
79e53945 JB |
152 | dev_priv->backlight_duty_cycle = (dev_priv->saveBLC_PWM_CTL & |
153 | BACKLIGHT_DUTY_CYCLE_MASK); | |
154 | ||
155 | /* | |
156 | * If the light is off at server startup, just make it full brightness | |
157 | */ | |
158 | if (dev_priv->backlight_duty_cycle == 0) | |
159 | dev_priv->backlight_duty_cycle = | |
160 | intel_lvds_get_max_backlight(dev); | |
161 | } | |
162 | ||
163 | static void intel_lvds_restore(struct drm_connector *connector) | |
164 | { | |
165 | struct drm_device *dev = connector->dev; | |
166 | struct drm_i915_private *dev_priv = dev->dev_private; | |
541998a1 ZW |
167 | u32 pp_on_reg, pp_off_reg, pp_ctl_reg, pp_div_reg; |
168 | u32 pwm_ctl_reg; | |
169 | ||
170 | if (IS_IGDNG(dev)) { | |
171 | pp_on_reg = PCH_PP_ON_DELAYS; | |
172 | pp_off_reg = PCH_PP_OFF_DELAYS; | |
173 | pp_ctl_reg = PCH_PP_CONTROL; | |
174 | pp_div_reg = PCH_PP_DIVISOR; | |
175 | pwm_ctl_reg = BLC_PWM_CPU_CTL; | |
176 | } else { | |
177 | pp_on_reg = PP_ON_DELAYS; | |
178 | pp_off_reg = PP_OFF_DELAYS; | |
179 | pp_ctl_reg = PP_CONTROL; | |
180 | pp_div_reg = PP_DIVISOR; | |
181 | pwm_ctl_reg = BLC_PWM_CTL; | |
182 | } | |
79e53945 | 183 | |
541998a1 ZW |
184 | I915_WRITE(pwm_ctl_reg, dev_priv->saveBLC_PWM_CTL); |
185 | I915_WRITE(pp_on_reg, dev_priv->savePP_ON); | |
186 | I915_WRITE(pp_off_reg, dev_priv->savePP_OFF); | |
187 | I915_WRITE(pp_div_reg, dev_priv->savePP_DIVISOR); | |
188 | I915_WRITE(pp_ctl_reg, dev_priv->savePP_CONTROL); | |
79e53945 JB |
189 | if (dev_priv->savePP_CONTROL & POWER_TARGET_ON) |
190 | intel_lvds_set_power(dev, true); | |
191 | else | |
192 | intel_lvds_set_power(dev, false); | |
193 | } | |
194 | ||
195 | static int intel_lvds_mode_valid(struct drm_connector *connector, | |
196 | struct drm_display_mode *mode) | |
197 | { | |
198 | struct drm_device *dev = connector->dev; | |
199 | struct drm_i915_private *dev_priv = dev->dev_private; | |
200 | struct drm_display_mode *fixed_mode = dev_priv->panel_fixed_mode; | |
201 | ||
202 | if (fixed_mode) { | |
203 | if (mode->hdisplay > fixed_mode->hdisplay) | |
204 | return MODE_PANEL; | |
205 | if (mode->vdisplay > fixed_mode->vdisplay) | |
206 | return MODE_PANEL; | |
207 | } | |
208 | ||
209 | return MODE_OK; | |
210 | } | |
211 | ||
212 | static bool intel_lvds_mode_fixup(struct drm_encoder *encoder, | |
213 | struct drm_display_mode *mode, | |
214 | struct drm_display_mode *adjusted_mode) | |
215 | { | |
216 | struct drm_device *dev = encoder->dev; | |
217 | struct drm_i915_private *dev_priv = dev->dev_private; | |
218 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
219 | struct drm_encoder *tmp_encoder; | |
220 | ||
221 | /* Should never happen!! */ | |
222 | if (!IS_I965G(dev) && intel_crtc->pipe == 0) { | |
223 | printk(KERN_ERR "Can't support LVDS on pipe A\n"); | |
224 | return false; | |
225 | } | |
226 | ||
227 | /* Should never happen!! */ | |
228 | list_for_each_entry(tmp_encoder, &dev->mode_config.encoder_list, head) { | |
229 | if (tmp_encoder != encoder && tmp_encoder->crtc == encoder->crtc) { | |
230 | printk(KERN_ERR "Can't enable LVDS and another " | |
231 | "encoder on the same pipe\n"); | |
232 | return false; | |
233 | } | |
234 | } | |
235 | ||
236 | /* | |
237 | * If we have timings from the BIOS for the panel, put them in | |
238 | * to the adjusted mode. The CRTC will be set up for this mode, | |
239 | * with the panel scaling set up to source from the H/VDisplay | |
240 | * of the original mode. | |
241 | */ | |
242 | if (dev_priv->panel_fixed_mode != NULL) { | |
243 | adjusted_mode->hdisplay = dev_priv->panel_fixed_mode->hdisplay; | |
244 | adjusted_mode->hsync_start = | |
245 | dev_priv->panel_fixed_mode->hsync_start; | |
246 | adjusted_mode->hsync_end = | |
247 | dev_priv->panel_fixed_mode->hsync_end; | |
248 | adjusted_mode->htotal = dev_priv->panel_fixed_mode->htotal; | |
249 | adjusted_mode->vdisplay = dev_priv->panel_fixed_mode->vdisplay; | |
250 | adjusted_mode->vsync_start = | |
251 | dev_priv->panel_fixed_mode->vsync_start; | |
252 | adjusted_mode->vsync_end = | |
253 | dev_priv->panel_fixed_mode->vsync_end; | |
254 | adjusted_mode->vtotal = dev_priv->panel_fixed_mode->vtotal; | |
255 | adjusted_mode->clock = dev_priv->panel_fixed_mode->clock; | |
256 | drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); | |
257 | } | |
258 | ||
259 | /* | |
260 | * XXX: It would be nice to support lower refresh rates on the | |
261 | * panels to reduce power consumption, and perhaps match the | |
262 | * user's requested refresh rate. | |
263 | */ | |
264 | ||
265 | return true; | |
266 | } | |
267 | ||
268 | static void intel_lvds_prepare(struct drm_encoder *encoder) | |
269 | { | |
270 | struct drm_device *dev = encoder->dev; | |
271 | struct drm_i915_private *dev_priv = dev->dev_private; | |
541998a1 | 272 | u32 reg; |
79e53945 | 273 | |
541998a1 ZW |
274 | if (IS_IGDNG(dev)) |
275 | reg = BLC_PWM_CPU_CTL; | |
276 | else | |
277 | reg = BLC_PWM_CTL; | |
79e53945 | 278 | |
541998a1 | 279 | dev_priv->saveBLC_PWM_CTL = I915_READ(reg); |
79e53945 JB |
280 | dev_priv->backlight_duty_cycle = (dev_priv->saveBLC_PWM_CTL & |
281 | BACKLIGHT_DUTY_CYCLE_MASK); | |
282 | ||
283 | intel_lvds_set_power(dev, false); | |
284 | } | |
285 | ||
286 | static void intel_lvds_commit( struct drm_encoder *encoder) | |
287 | { | |
288 | struct drm_device *dev = encoder->dev; | |
289 | struct drm_i915_private *dev_priv = dev->dev_private; | |
290 | ||
291 | if (dev_priv->backlight_duty_cycle == 0) | |
292 | dev_priv->backlight_duty_cycle = | |
293 | intel_lvds_get_max_backlight(dev); | |
294 | ||
295 | intel_lvds_set_power(dev, true); | |
296 | } | |
297 | ||
298 | static void intel_lvds_mode_set(struct drm_encoder *encoder, | |
299 | struct drm_display_mode *mode, | |
300 | struct drm_display_mode *adjusted_mode) | |
301 | { | |
302 | struct drm_device *dev = encoder->dev; | |
303 | struct drm_i915_private *dev_priv = dev->dev_private; | |
304 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
305 | u32 pfit_control; | |
306 | ||
307 | /* | |
308 | * The LVDS pin pair will already have been turned on in the | |
309 | * intel_crtc_mode_set since it has a large impact on the DPLL | |
310 | * settings. | |
311 | */ | |
312 | ||
541998a1 ZW |
313 | /* No panel fitting yet, fixme */ |
314 | if (IS_IGDNG(dev)) | |
315 | return; | |
316 | ||
79e53945 JB |
317 | /* |
318 | * Enable automatic panel scaling so that non-native modes fill the | |
319 | * screen. Should be enabled before the pipe is enabled, according to | |
320 | * register description and PRM. | |
321 | */ | |
322 | if (mode->hdisplay != adjusted_mode->hdisplay || | |
323 | mode->vdisplay != adjusted_mode->vdisplay) | |
324 | pfit_control = (PFIT_ENABLE | VERT_AUTO_SCALE | | |
325 | HORIZ_AUTO_SCALE | VERT_INTERP_BILINEAR | | |
326 | HORIZ_INTERP_BILINEAR); | |
327 | else | |
328 | pfit_control = 0; | |
329 | ||
330 | if (!IS_I965G(dev)) { | |
2b5cde2b | 331 | if (dev_priv->panel_wants_dither || dev_priv->lvds_dither) |
79e53945 JB |
332 | pfit_control |= PANEL_8TO6_DITHER_ENABLE; |
333 | } | |
334 | else | |
335 | pfit_control |= intel_crtc->pipe << PFIT_PIPE_SHIFT; | |
336 | ||
337 | I915_WRITE(PFIT_CONTROL, pfit_control); | |
338 | } | |
339 | ||
340 | /** | |
341 | * Detect the LVDS connection. | |
342 | * | |
343 | * This always returns CONNECTOR_STATUS_CONNECTED. This connector should only have | |
344 | * been set up if the LVDS was actually connected anyway. | |
345 | */ | |
346 | static enum drm_connector_status intel_lvds_detect(struct drm_connector *connector) | |
347 | { | |
348 | return connector_status_connected; | |
349 | } | |
350 | ||
351 | /** | |
352 | * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. | |
353 | */ | |
354 | static int intel_lvds_get_modes(struct drm_connector *connector) | |
355 | { | |
356 | struct drm_device *dev = connector->dev; | |
357 | struct intel_output *intel_output = to_intel_output(connector); | |
358 | struct drm_i915_private *dev_priv = dev->dev_private; | |
359 | int ret = 0; | |
360 | ||
361 | ret = intel_ddc_get_modes(intel_output); | |
362 | ||
363 | if (ret) | |
364 | return ret; | |
365 | ||
366 | /* Didn't get an EDID, so | |
367 | * Set wide sync ranges so we get all modes | |
368 | * handed to valid_mode for checking | |
369 | */ | |
370 | connector->display_info.min_vfreq = 0; | |
371 | connector->display_info.max_vfreq = 200; | |
372 | connector->display_info.min_hfreq = 0; | |
373 | connector->display_info.max_hfreq = 200; | |
374 | ||
375 | if (dev_priv->panel_fixed_mode != NULL) { | |
376 | struct drm_display_mode *mode; | |
377 | ||
79e53945 JB |
378 | mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode); |
379 | drm_mode_probed_add(connector, mode); | |
79e53945 JB |
380 | |
381 | return 1; | |
382 | } | |
383 | ||
384 | return 0; | |
385 | } | |
386 | ||
387 | /** | |
388 | * intel_lvds_destroy - unregister and free LVDS structures | |
389 | * @connector: connector to free | |
390 | * | |
391 | * Unregister the DDC bus for this connector then free the driver private | |
392 | * structure. | |
393 | */ | |
394 | static void intel_lvds_destroy(struct drm_connector *connector) | |
395 | { | |
396 | struct intel_output *intel_output = to_intel_output(connector); | |
397 | ||
398 | if (intel_output->ddc_bus) | |
399 | intel_i2c_destroy(intel_output->ddc_bus); | |
400 | drm_sysfs_connector_remove(connector); | |
401 | drm_connector_cleanup(connector); | |
402 | kfree(connector); | |
403 | } | |
404 | ||
335041ed JB |
405 | static int intel_lvds_set_property(struct drm_connector *connector, |
406 | struct drm_property *property, | |
407 | uint64_t value) | |
408 | { | |
335041ed JB |
409 | return 0; |
410 | } | |
411 | ||
79e53945 JB |
412 | static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = { |
413 | .dpms = intel_lvds_dpms, | |
414 | .mode_fixup = intel_lvds_mode_fixup, | |
415 | .prepare = intel_lvds_prepare, | |
416 | .mode_set = intel_lvds_mode_set, | |
417 | .commit = intel_lvds_commit, | |
418 | }; | |
419 | ||
420 | static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { | |
421 | .get_modes = intel_lvds_get_modes, | |
422 | .mode_valid = intel_lvds_mode_valid, | |
423 | .best_encoder = intel_best_encoder, | |
424 | }; | |
425 | ||
426 | static const struct drm_connector_funcs intel_lvds_connector_funcs = { | |
c9fb15f6 | 427 | .dpms = drm_helper_connector_dpms, |
79e53945 JB |
428 | .save = intel_lvds_save, |
429 | .restore = intel_lvds_restore, | |
430 | .detect = intel_lvds_detect, | |
431 | .fill_modes = drm_helper_probe_single_connector_modes, | |
335041ed | 432 | .set_property = intel_lvds_set_property, |
79e53945 JB |
433 | .destroy = intel_lvds_destroy, |
434 | }; | |
435 | ||
436 | ||
437 | static void intel_lvds_enc_destroy(struct drm_encoder *encoder) | |
438 | { | |
439 | drm_encoder_cleanup(encoder); | |
440 | } | |
441 | ||
442 | static const struct drm_encoder_funcs intel_lvds_enc_funcs = { | |
443 | .destroy = intel_lvds_enc_destroy, | |
444 | }; | |
445 | ||
425d244c JW |
446 | static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
447 | { | |
7fb85bfb | 448 | DRM_DEBUG_KMS(I915_LVDS, |
449 | "Skipping LVDS initialization for %s\n", id->ident); | |
425d244c JW |
450 | return 1; |
451 | } | |
79e53945 | 452 | |
425d244c | 453 | /* These systems claim to have LVDS, but really don't */ |
93c05f22 | 454 | static const struct dmi_system_id intel_no_lvds[] = { |
425d244c JW |
455 | { |
456 | .callback = intel_no_lvds_dmi_callback, | |
457 | .ident = "Apple Mac Mini (Core series)", | |
458 | .matches = { | |
459 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
460 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), | |
461 | }, | |
462 | }, | |
463 | { | |
464 | .callback = intel_no_lvds_dmi_callback, | |
465 | .ident = "Apple Mac Mini (Core 2 series)", | |
466 | .matches = { | |
467 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
468 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), | |
469 | }, | |
470 | }, | |
471 | { | |
472 | .callback = intel_no_lvds_dmi_callback, | |
473 | .ident = "MSI IM-945GSE-A", | |
474 | .matches = { | |
475 | DMI_MATCH(DMI_SYS_VENDOR, "MSI"), | |
476 | DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), | |
477 | }, | |
478 | }, | |
479 | { | |
480 | .callback = intel_no_lvds_dmi_callback, | |
481 | .ident = "Dell Studio Hybrid", | |
482 | .matches = { | |
483 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
484 | DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), | |
485 | }, | |
486 | }, | |
70aa96ca JW |
487 | { |
488 | .callback = intel_no_lvds_dmi_callback, | |
489 | .ident = "AOpen Mini PC", | |
490 | .matches = { | |
491 | DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), | |
492 | DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), | |
493 | }, | |
494 | }, | |
fa0864b2 MC |
495 | { |
496 | .callback = intel_no_lvds_dmi_callback, | |
497 | .ident = "Aopen i945GTt-VFA", | |
498 | .matches = { | |
499 | DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), | |
500 | }, | |
501 | }, | |
425d244c JW |
502 | |
503 | { } /* terminating entry */ | |
504 | }; | |
79e53945 JB |
505 | |
506 | /** | |
507 | * intel_lvds_init - setup LVDS connectors on this device | |
508 | * @dev: drm device | |
509 | * | |
510 | * Create the connector, register the LVDS DDC bus, and try to figure out what | |
511 | * modes we can display on the LVDS panel (if present). | |
512 | */ | |
513 | void intel_lvds_init(struct drm_device *dev) | |
514 | { | |
515 | struct drm_i915_private *dev_priv = dev->dev_private; | |
516 | struct intel_output *intel_output; | |
517 | struct drm_connector *connector; | |
518 | struct drm_encoder *encoder; | |
519 | struct drm_display_mode *scan; /* *modes, *bios_mode; */ | |
520 | struct drm_crtc *crtc; | |
521 | u32 lvds; | |
541998a1 | 522 | int pipe, gpio = GPIOC; |
79e53945 | 523 | |
425d244c JW |
524 | /* Skip init on machines we know falsely report LVDS */ |
525 | if (dmi_check_system(intel_no_lvds)) | |
565dcd46 | 526 | return; |
565dcd46 | 527 | |
541998a1 ZW |
528 | if (IS_IGDNG(dev)) { |
529 | if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0) | |
530 | return; | |
531 | gpio = PCH_GPIOC; | |
532 | } | |
533 | ||
79e53945 JB |
534 | intel_output = kzalloc(sizeof(struct intel_output), GFP_KERNEL); |
535 | if (!intel_output) { | |
536 | return; | |
537 | } | |
538 | ||
539 | connector = &intel_output->base; | |
540 | encoder = &intel_output->enc; | |
541 | drm_connector_init(dev, &intel_output->base, &intel_lvds_connector_funcs, | |
542 | DRM_MODE_CONNECTOR_LVDS); | |
543 | ||
544 | drm_encoder_init(dev, &intel_output->enc, &intel_lvds_enc_funcs, | |
545 | DRM_MODE_ENCODER_LVDS); | |
546 | ||
547 | drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc); | |
548 | intel_output->type = INTEL_OUTPUT_LVDS; | |
549 | ||
550 | drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs); | |
551 | drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); | |
552 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
553 | connector->interlace_allowed = false; | |
554 | connector->doublescan_allowed = false; | |
555 | ||
556 | ||
557 | /* | |
558 | * LVDS discovery: | |
559 | * 1) check for EDID on DDC | |
560 | * 2) check for VBT data | |
561 | * 3) check to see if LVDS is already on | |
562 | * if none of the above, no panel | |
563 | * 4) make sure lid is open | |
564 | * if closed, act like it's not there for now | |
565 | */ | |
566 | ||
567 | /* Set up the DDC bus. */ | |
541998a1 | 568 | intel_output->ddc_bus = intel_i2c_create(dev, gpio, "LVDSDDC_C"); |
79e53945 JB |
569 | if (!intel_output->ddc_bus) { |
570 | dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration " | |
571 | "failed.\n"); | |
572 | goto failed; | |
573 | } | |
574 | ||
575 | /* | |
576 | * Attempt to get the fixed panel mode from DDC. Assume that the | |
577 | * preferred mode is the right one. | |
578 | */ | |
579 | intel_ddc_get_modes(intel_output); | |
580 | ||
581 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
582 | mutex_lock(&dev->mode_config.mutex); | |
583 | if (scan->type & DRM_MODE_TYPE_PREFERRED) { | |
584 | dev_priv->panel_fixed_mode = | |
585 | drm_mode_duplicate(dev, scan); | |
586 | mutex_unlock(&dev->mode_config.mutex); | |
565dcd46 | 587 | goto out; |
79e53945 JB |
588 | } |
589 | mutex_unlock(&dev->mode_config.mutex); | |
590 | } | |
591 | ||
592 | /* Failed to get EDID, what about VBT? */ | |
88631706 | 593 | if (dev_priv->lfp_lvds_vbt_mode) { |
79e53945 JB |
594 | mutex_lock(&dev->mode_config.mutex); |
595 | dev_priv->panel_fixed_mode = | |
88631706 | 596 | drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); |
79e53945 | 597 | mutex_unlock(&dev->mode_config.mutex); |
e285f3cd JB |
598 | if (dev_priv->panel_fixed_mode) { |
599 | dev_priv->panel_fixed_mode->type |= | |
600 | DRM_MODE_TYPE_PREFERRED; | |
e285f3cd JB |
601 | goto out; |
602 | } | |
79e53945 JB |
603 | } |
604 | ||
605 | /* | |
606 | * If we didn't get EDID, try checking if the panel is already turned | |
607 | * on. If so, assume that whatever is currently programmed is the | |
608 | * correct mode. | |
609 | */ | |
541998a1 ZW |
610 | |
611 | /* IGDNG: FIXME if still fail, not try pipe mode now */ | |
612 | if (IS_IGDNG(dev)) | |
613 | goto failed; | |
614 | ||
79e53945 JB |
615 | lvds = I915_READ(LVDS); |
616 | pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; | |
617 | crtc = intel_get_crtc_from_pipe(dev, pipe); | |
618 | ||
619 | if (crtc && (lvds & LVDS_PORT_EN)) { | |
620 | dev_priv->panel_fixed_mode = intel_crtc_mode_get(dev, crtc); | |
621 | if (dev_priv->panel_fixed_mode) { | |
622 | dev_priv->panel_fixed_mode->type |= | |
623 | DRM_MODE_TYPE_PREFERRED; | |
565dcd46 | 624 | goto out; |
79e53945 JB |
625 | } |
626 | } | |
627 | ||
628 | /* If we still don't have a mode after all that, give up. */ | |
629 | if (!dev_priv->panel_fixed_mode) | |
630 | goto failed; | |
631 | ||
79e53945 | 632 | out: |
541998a1 ZW |
633 | if (IS_IGDNG(dev)) { |
634 | u32 pwm; | |
635 | /* make sure PWM is enabled */ | |
636 | pwm = I915_READ(BLC_PWM_CPU_CTL2); | |
637 | pwm |= (PWM_ENABLE | PWM_PIPE_B); | |
638 | I915_WRITE(BLC_PWM_CPU_CTL2, pwm); | |
639 | ||
640 | pwm = I915_READ(BLC_PWM_PCH_CTL1); | |
641 | pwm |= PWM_PCH_ENABLE; | |
642 | I915_WRITE(BLC_PWM_PCH_CTL1, pwm); | |
643 | } | |
79e53945 JB |
644 | drm_sysfs_connector_add(connector); |
645 | return; | |
646 | ||
647 | failed: | |
7fb85bfb | 648 | DRM_DEBUG_KMS(I915_LVDS, "No LVDS modes found, disabling.\n"); |
79e53945 JB |
649 | if (intel_output->ddc_bus) |
650 | intel_i2c_destroy(intel_output->ddc_bus); | |
651 | drm_connector_cleanup(connector); | |
652 | kfree(connector); | |
653 | } |