Commit | Line | Data |
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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Dave Airlie <airlied@linux.ie> | |
27 | * Jesse Barnes <jesse.barnes@intel.com> | |
28 | */ | |
29 | ||
c1c7af60 | 30 | #include <acpi/button.h> |
565dcd46 | 31 | #include <linux/dmi.h> |
79e53945 | 32 | #include <linux/i2c.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
4eddaeec | 34 | #include <linux/vga_switcheroo.h> |
760285e7 | 35 | #include <drm/drmP.h> |
c6f95f27 | 36 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
37 | #include <drm/drm_crtc.h> |
38 | #include <drm/drm_edid.h> | |
79e53945 | 39 | #include "intel_drv.h" |
760285e7 | 40 | #include <drm/i915_drm.h> |
79e53945 | 41 | #include "i915_drv.h" |
e99da35f | 42 | #include <linux/acpi.h> |
79e53945 | 43 | |
3fbe18d6 | 44 | /* Private structure for the integrated LVDS support */ |
c7362c4d JN |
45 | struct intel_lvds_connector { |
46 | struct intel_connector base; | |
788319d4 | 47 | |
db1740a0 | 48 | struct notifier_block lid_notifier; |
c7362c4d JN |
49 | }; |
50 | ||
29b99b48 | 51 | struct intel_lvds_encoder { |
ea5b213a | 52 | struct intel_encoder base; |
788319d4 | 53 | |
13c7d870 | 54 | bool is_dual_link; |
f0f59a00 | 55 | i915_reg_t reg; |
1f835a77 | 56 | u32 a3_power; |
788319d4 | 57 | |
62165e0d | 58 | struct intel_lvds_connector *attached_connector; |
3fbe18d6 ZY |
59 | }; |
60 | ||
29b99b48 | 61 | static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder) |
ea5b213a | 62 | { |
29b99b48 | 63 | return container_of(encoder, struct intel_lvds_encoder, base.base); |
ea5b213a CW |
64 | } |
65 | ||
c7362c4d | 66 | static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector) |
788319d4 | 67 | { |
c7362c4d | 68 | return container_of(connector, struct intel_lvds_connector, base.base); |
788319d4 CW |
69 | } |
70 | ||
b1dc332c DV |
71 | static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, |
72 | enum pipe *pipe) | |
73 | { | |
74 | struct drm_device *dev = encoder->base.dev; | |
75 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7dec0606 | 76 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
34a6c70f | 77 | enum intel_display_power_domain power_domain; |
7dec0606 | 78 | u32 tmp; |
ecb24482 | 79 | bool ret; |
b1dc332c | 80 | |
34a6c70f | 81 | power_domain = intel_display_port_power_domain(encoder); |
ecb24482 | 82 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
34a6c70f PZ |
83 | return false; |
84 | ||
ecb24482 ID |
85 | ret = false; |
86 | ||
7dec0606 | 87 | tmp = I915_READ(lvds_encoder->reg); |
b1dc332c DV |
88 | |
89 | if (!(tmp & LVDS_PORT_EN)) | |
ecb24482 | 90 | goto out; |
b1dc332c DV |
91 | |
92 | if (HAS_PCH_CPT(dev)) | |
93 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
94 | else | |
95 | *pipe = PORT_TO_PIPE(tmp); | |
96 | ||
ecb24482 ID |
97 | ret = true; |
98 | ||
99 | out: | |
100 | intel_display_power_put(dev_priv, power_domain); | |
101 | ||
102 | return ret; | |
b1dc332c DV |
103 | } |
104 | ||
045ac3b5 | 105 | static void intel_lvds_get_config(struct intel_encoder *encoder, |
5cec258b | 106 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
107 | { |
108 | struct drm_device *dev = encoder->base.dev; | |
109 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d0669d00 VS |
110 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
111 | u32 tmp, flags = 0; | |
18442d08 | 112 | int dotclock; |
045ac3b5 | 113 | |
d0669d00 | 114 | tmp = I915_READ(lvds_encoder->reg); |
045ac3b5 JB |
115 | if (tmp & LVDS_HSYNC_POLARITY) |
116 | flags |= DRM_MODE_FLAG_NHSYNC; | |
117 | else | |
118 | flags |= DRM_MODE_FLAG_PHSYNC; | |
119 | if (tmp & LVDS_VSYNC_POLARITY) | |
120 | flags |= DRM_MODE_FLAG_NVSYNC; | |
121 | else | |
122 | flags |= DRM_MODE_FLAG_PVSYNC; | |
123 | ||
2d112de7 | 124 | pipe_config->base.adjusted_mode.flags |= flags; |
06922821 | 125 | |
6b89cdde DV |
126 | /* gen2/3 store dither state in pfit control, needs to match */ |
127 | if (INTEL_INFO(dev)->gen < 4) { | |
128 | tmp = I915_READ(PFIT_CONTROL); | |
129 | ||
130 | pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; | |
131 | } | |
132 | ||
18442d08 VS |
133 | dotclock = pipe_config->port_clock; |
134 | ||
135 | if (HAS_PCH_SPLIT(dev_priv->dev)) | |
136 | ironlake_check_encoder_dotclock(pipe_config, dotclock); | |
137 | ||
2d112de7 | 138 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
045ac3b5 JB |
139 | } |
140 | ||
f6736a1a | 141 | static void intel_pre_enable_lvds(struct intel_encoder *encoder) |
fc683091 DV |
142 | { |
143 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); | |
144 | struct drm_device *dev = encoder->base.dev; | |
145 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55607e8a | 146 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
124abe07 | 147 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
55607e8a | 148 | int pipe = crtc->pipe; |
fc683091 DV |
149 | u32 temp; |
150 | ||
55607e8a DV |
151 | if (HAS_PCH_SPLIT(dev)) { |
152 | assert_fdi_rx_pll_disabled(dev_priv, pipe); | |
153 | assert_shared_dpll_disabled(dev_priv, | |
154 | intel_crtc_to_shared_dpll(crtc)); | |
155 | } else { | |
156 | assert_pll_disabled(dev_priv, pipe); | |
157 | } | |
158 | ||
fc683091 DV |
159 | temp = I915_READ(lvds_encoder->reg); |
160 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; | |
62810e5a DV |
161 | |
162 | if (HAS_PCH_CPT(dev)) { | |
163 | temp &= ~PORT_TRANS_SEL_MASK; | |
164 | temp |= PORT_TRANS_SEL_CPT(pipe); | |
fc683091 | 165 | } else { |
62810e5a DV |
166 | if (pipe == 1) { |
167 | temp |= LVDS_PIPEB_SELECT; | |
168 | } else { | |
169 | temp &= ~LVDS_PIPEB_SELECT; | |
170 | } | |
fc683091 | 171 | } |
62810e5a | 172 | |
fc683091 | 173 | /* set the corresponsding LVDS_BORDER bit */ |
2fa2fe9a | 174 | temp &= ~LVDS_BORDER_ENABLE; |
6e3c9717 | 175 | temp |= crtc->config->gmch_pfit.lvds_border_bits; |
fc683091 DV |
176 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
177 | * set the DPLLs for dual-channel mode or not. | |
178 | */ | |
179 | if (lvds_encoder->is_dual_link) | |
180 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; | |
181 | else | |
182 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); | |
183 | ||
184 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
185 | * appropriately here, but we need to look more thoroughly into how | |
1f835a77 PZ |
186 | * panels behave in the two modes. For now, let's just maintain the |
187 | * value we got from the BIOS. | |
fc683091 | 188 | */ |
1f835a77 PZ |
189 | temp &= ~LVDS_A3_POWER_MASK; |
190 | temp |= lvds_encoder->a3_power; | |
62810e5a DV |
191 | |
192 | /* Set the dithering flag on LVDS as needed, note that there is no | |
193 | * special lvds dither control bit on pch-split platforms, dithering is | |
194 | * only controlled through the PIPECONF reg. */ | |
195 | if (INTEL_INFO(dev)->gen == 4) { | |
d8b32247 DV |
196 | /* Bspec wording suggests that LVDS port dithering only exists |
197 | * for 18bpp panels. */ | |
6e3c9717 | 198 | if (crtc->config->dither && crtc->config->pipe_bpp == 18) |
fc683091 DV |
199 | temp |= LVDS_ENABLE_DITHER; |
200 | else | |
201 | temp &= ~LVDS_ENABLE_DITHER; | |
202 | } | |
203 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); | |
4c6df4b4 | 204 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
fc683091 | 205 | temp |= LVDS_HSYNC_POLARITY; |
4c6df4b4 | 206 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
fc683091 DV |
207 | temp |= LVDS_VSYNC_POLARITY; |
208 | ||
209 | I915_WRITE(lvds_encoder->reg, temp); | |
210 | } | |
211 | ||
79e53945 JB |
212 | /** |
213 | * Sets the power state for the panel. | |
214 | */ | |
c22834ec | 215 | static void intel_enable_lvds(struct intel_encoder *encoder) |
79e53945 | 216 | { |
c22834ec | 217 | struct drm_device *dev = encoder->base.dev; |
29b99b48 | 218 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
752aa88a JB |
219 | struct intel_connector *intel_connector = |
220 | &lvds_encoder->attached_connector->base; | |
79e53945 | 221 | struct drm_i915_private *dev_priv = dev->dev_private; |
f0f59a00 | 222 | i915_reg_t ctl_reg, stat_reg; |
541998a1 | 223 | |
c619eed4 | 224 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 225 | ctl_reg = PCH_PP_CONTROL; |
de842eff | 226 | stat_reg = PCH_PP_STATUS; |
541998a1 ZW |
227 | } else { |
228 | ctl_reg = PP_CONTROL; | |
de842eff | 229 | stat_reg = PP_STATUS; |
541998a1 | 230 | } |
79e53945 | 231 | |
7dec0606 | 232 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); |
e9e331a8 | 233 | |
2a1292fd | 234 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); |
7dec0606 | 235 | POSTING_READ(lvds_encoder->reg); |
de842eff KP |
236 | if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000)) |
237 | DRM_ERROR("timed out waiting for panel to power on\n"); | |
2a1292fd | 238 | |
752aa88a | 239 | intel_panel_enable_backlight(intel_connector); |
2a1292fd CW |
240 | } |
241 | ||
c22834ec | 242 | static void intel_disable_lvds(struct intel_encoder *encoder) |
2a1292fd | 243 | { |
c22834ec | 244 | struct drm_device *dev = encoder->base.dev; |
29b99b48 | 245 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
2a1292fd | 246 | struct drm_i915_private *dev_priv = dev->dev_private; |
f0f59a00 | 247 | i915_reg_t ctl_reg, stat_reg; |
2a1292fd CW |
248 | |
249 | if (HAS_PCH_SPLIT(dev)) { | |
250 | ctl_reg = PCH_PP_CONTROL; | |
de842eff | 251 | stat_reg = PCH_PP_STATUS; |
2a1292fd CW |
252 | } else { |
253 | ctl_reg = PP_CONTROL; | |
de842eff | 254 | stat_reg = PP_STATUS; |
2a1292fd CW |
255 | } |
256 | ||
2a1292fd | 257 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); |
de842eff KP |
258 | if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000)) |
259 | DRM_ERROR("timed out waiting for panel to power off\n"); | |
2a1292fd | 260 | |
7dec0606 DV |
261 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); |
262 | POSTING_READ(lvds_encoder->reg); | |
79e53945 JB |
263 | } |
264 | ||
d26a5b6e VS |
265 | static void gmch_disable_lvds(struct intel_encoder *encoder) |
266 | { | |
267 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); | |
268 | struct intel_connector *intel_connector = | |
269 | &lvds_encoder->attached_connector->base; | |
270 | ||
271 | intel_panel_disable_backlight(intel_connector); | |
272 | ||
273 | intel_disable_lvds(encoder); | |
274 | } | |
275 | ||
276 | static void pch_disable_lvds(struct intel_encoder *encoder) | |
277 | { | |
278 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); | |
279 | struct intel_connector *intel_connector = | |
280 | &lvds_encoder->attached_connector->base; | |
281 | ||
282 | intel_panel_disable_backlight(intel_connector); | |
283 | } | |
284 | ||
285 | static void pch_post_disable_lvds(struct intel_encoder *encoder) | |
286 | { | |
287 | intel_disable_lvds(encoder); | |
288 | } | |
289 | ||
c19de8eb DL |
290 | static enum drm_mode_status |
291 | intel_lvds_mode_valid(struct drm_connector *connector, | |
292 | struct drm_display_mode *mode) | |
79e53945 | 293 | { |
dd06f90e JN |
294 | struct intel_connector *intel_connector = to_intel_connector(connector); |
295 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
7f7b58cc | 296 | int max_pixclk = to_i915(connector->dev)->max_dotclk_freq; |
79e53945 | 297 | |
788319d4 CW |
298 | if (mode->hdisplay > fixed_mode->hdisplay) |
299 | return MODE_PANEL; | |
300 | if (mode->vdisplay > fixed_mode->vdisplay) | |
301 | return MODE_PANEL; | |
7f7b58cc MK |
302 | if (fixed_mode->clock > max_pixclk) |
303 | return MODE_CLOCK_HIGH; | |
79e53945 JB |
304 | |
305 | return MODE_OK; | |
306 | } | |
307 | ||
7ae89233 | 308 | static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder, |
5cec258b | 309 | struct intel_crtc_state *pipe_config) |
79e53945 | 310 | { |
7ae89233 | 311 | struct drm_device *dev = intel_encoder->base.dev; |
7ae89233 DV |
312 | struct intel_lvds_encoder *lvds_encoder = |
313 | to_lvds_encoder(&intel_encoder->base); | |
4d891523 JN |
314 | struct intel_connector *intel_connector = |
315 | &lvds_encoder->attached_connector->base; | |
2d112de7 | 316 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
d21bd67b | 317 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
4e53c2e0 | 318 | unsigned int lvds_bpp; |
79e53945 JB |
319 | |
320 | /* Should never happen!! */ | |
a6c45cf0 | 321 | if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) { |
1ae8c0a5 | 322 | DRM_ERROR("Can't support LVDS on pipe A\n"); |
79e53945 JB |
323 | return false; |
324 | } | |
325 | ||
1f835a77 | 326 | if (lvds_encoder->a3_power == LVDS_A3_POWER_UP) |
4e53c2e0 DV |
327 | lvds_bpp = 8*3; |
328 | else | |
329 | lvds_bpp = 6*3; | |
330 | ||
e29c22c0 | 331 | if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { |
4e53c2e0 DV |
332 | DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n", |
333 | pipe_config->pipe_bpp, lvds_bpp); | |
334 | pipe_config->pipe_bpp = lvds_bpp; | |
335 | } | |
d8b32247 | 336 | |
79e53945 | 337 | /* |
71677043 | 338 | * We have timings from the BIOS for the panel, put them in |
79e53945 JB |
339 | * to the adjusted mode. The CRTC will be set up for this mode, |
340 | * with the panel scaling set up to source from the H/VDisplay | |
341 | * of the original mode. | |
342 | */ | |
4d891523 | 343 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
dd06f90e | 344 | adjusted_mode); |
1d8e1c75 CW |
345 | |
346 | if (HAS_PCH_SPLIT(dev)) { | |
5bfe2ac0 DV |
347 | pipe_config->has_pch_encoder = true; |
348 | ||
b074cec8 JB |
349 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
350 | intel_connector->panel.fitting_mode); | |
2dd24552 JB |
351 | } else { |
352 | intel_gmch_panel_fitting(intel_crtc, pipe_config, | |
353 | intel_connector->panel.fitting_mode); | |
79e53945 | 354 | |
21d8a475 | 355 | } |
f9bef081 | 356 | |
79e53945 JB |
357 | /* |
358 | * XXX: It would be nice to support lower refresh rates on the | |
359 | * panels to reduce power consumption, and perhaps match the | |
360 | * user's requested refresh rate. | |
361 | */ | |
362 | ||
363 | return true; | |
364 | } | |
365 | ||
79e53945 JB |
366 | /** |
367 | * Detect the LVDS connection. | |
368 | * | |
b42d4c5c JB |
369 | * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means |
370 | * connected and closed means disconnected. We also send hotplug events as | |
371 | * needed, using lid status notification from the input layer. | |
79e53945 | 372 | */ |
7b334fcb | 373 | static enum drm_connector_status |
930a9e28 | 374 | intel_lvds_detect(struct drm_connector *connector, bool force) |
79e53945 | 375 | { |
7b9c5abe | 376 | struct drm_device *dev = connector->dev; |
6ee3b5a1 | 377 | enum drm_connector_status status; |
b42d4c5c | 378 | |
164c8598 | 379 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
c23cc417 | 380 | connector->base.id, connector->name); |
164c8598 | 381 | |
fe16d949 CW |
382 | status = intel_panel_detect(dev); |
383 | if (status != connector_status_unknown) | |
384 | return status; | |
01fe9dbd | 385 | |
6ee3b5a1 | 386 | return connector_status_connected; |
79e53945 JB |
387 | } |
388 | ||
389 | /** | |
390 | * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. | |
391 | */ | |
392 | static int intel_lvds_get_modes(struct drm_connector *connector) | |
393 | { | |
62165e0d | 394 | struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector); |
79e53945 | 395 | struct drm_device *dev = connector->dev; |
788319d4 | 396 | struct drm_display_mode *mode; |
79e53945 | 397 | |
9cd300e0 | 398 | /* use cached edid if we have one */ |
2aa4f099 | 399 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
9cd300e0 | 400 | return drm_add_edid_modes(connector, lvds_connector->base.edid); |
79e53945 | 401 | |
dd06f90e | 402 | mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode); |
311bd68e | 403 | if (mode == NULL) |
788319d4 | 404 | return 0; |
79e53945 | 405 | |
788319d4 CW |
406 | drm_mode_probed_add(connector, mode); |
407 | return 1; | |
79e53945 JB |
408 | } |
409 | ||
0544edfd TB |
410 | static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id) |
411 | { | |
bc0daf48 | 412 | DRM_INFO("Skipping forced modeset for %s\n", id->ident); |
0544edfd TB |
413 | return 1; |
414 | } | |
415 | ||
416 | /* The GPU hangs up on these systems if modeset is performed on LID open */ | |
417 | static const struct dmi_system_id intel_no_modeset_on_lid[] = { | |
418 | { | |
419 | .callback = intel_no_modeset_on_lid_dmi_callback, | |
420 | .ident = "Toshiba Tecra A11", | |
421 | .matches = { | |
422 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
423 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"), | |
424 | }, | |
425 | }, | |
426 | ||
427 | { } /* terminating entry */ | |
428 | }; | |
429 | ||
c9354c85 | 430 | /* |
b8efb17b ZR |
431 | * Lid events. Note the use of 'modeset': |
432 | * - we set it to MODESET_ON_LID_OPEN on lid close, | |
433 | * and set it to MODESET_DONE on open | |
c9354c85 | 434 | * - we use it as a "only once" bit (ie we ignore |
b8efb17b ZR |
435 | * duplicate events where it was already properly set) |
436 | * - the suspend/resume paths will set it to | |
437 | * MODESET_SUSPENDED and ignore the lid open event, | |
438 | * because they restore the mode ("lid open"). | |
c9354c85 | 439 | */ |
c1c7af60 JB |
440 | static int intel_lid_notify(struct notifier_block *nb, unsigned long val, |
441 | void *unused) | |
442 | { | |
db1740a0 JN |
443 | struct intel_lvds_connector *lvds_connector = |
444 | container_of(nb, struct intel_lvds_connector, lid_notifier); | |
445 | struct drm_connector *connector = &lvds_connector->base.base; | |
446 | struct drm_device *dev = connector->dev; | |
447 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c1c7af60 | 448 | |
2fb4e61d AW |
449 | if (dev->switch_power_state != DRM_SWITCH_POWER_ON) |
450 | return NOTIFY_OK; | |
451 | ||
b8efb17b ZR |
452 | mutex_lock(&dev_priv->modeset_restore_lock); |
453 | if (dev_priv->modeset_restore == MODESET_SUSPENDED) | |
454 | goto exit; | |
a2565377 ZY |
455 | /* |
456 | * check and update the status of LVDS connector after receiving | |
457 | * the LID nofication event. | |
458 | */ | |
db1740a0 | 459 | connector->status = connector->funcs->detect(connector, false); |
7b334fcb | 460 | |
0544edfd TB |
461 | /* Don't force modeset on machines where it causes a GPU lockup */ |
462 | if (dmi_check_system(intel_no_modeset_on_lid)) | |
b8efb17b | 463 | goto exit; |
c9354c85 | 464 | if (!acpi_lid_open()) { |
b8efb17b ZR |
465 | /* do modeset on next lid open event */ |
466 | dev_priv->modeset_restore = MODESET_ON_LID_OPEN; | |
467 | goto exit; | |
06891e27 | 468 | } |
c1c7af60 | 469 | |
b8efb17b ZR |
470 | if (dev_priv->modeset_restore == MODESET_DONE) |
471 | goto exit; | |
c9354c85 | 472 | |
5be19d91 DV |
473 | /* |
474 | * Some old platform's BIOS love to wreak havoc while the lid is closed. | |
475 | * We try to detect this here and undo any damage. The split for PCH | |
476 | * platforms is rather conservative and a bit arbitrary expect that on | |
477 | * those platforms VGA disabling requires actual legacy VGA I/O access, | |
478 | * and as part of the cleanup in the hw state restore we also redisable | |
479 | * the vga plane. | |
480 | */ | |
42bf7b46 | 481 | if (!HAS_PCH_SPLIT(dev)) |
043e9bda | 482 | intel_display_resume(dev); |
06324194 | 483 | |
b8efb17b ZR |
484 | dev_priv->modeset_restore = MODESET_DONE; |
485 | ||
486 | exit: | |
487 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
c1c7af60 JB |
488 | return NOTIFY_OK; |
489 | } | |
490 | ||
79e53945 JB |
491 | /** |
492 | * intel_lvds_destroy - unregister and free LVDS structures | |
493 | * @connector: connector to free | |
494 | * | |
495 | * Unregister the DDC bus for this connector then free the driver private | |
496 | * structure. | |
497 | */ | |
498 | static void intel_lvds_destroy(struct drm_connector *connector) | |
499 | { | |
db1740a0 JN |
500 | struct intel_lvds_connector *lvds_connector = |
501 | to_lvds_connector(connector); | |
79e53945 | 502 | |
db1740a0 JN |
503 | if (lvds_connector->lid_notifier.notifier_call) |
504 | acpi_lid_notifier_unregister(&lvds_connector->lid_notifier); | |
79e53945 | 505 | |
9cd300e0 JN |
506 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
507 | kfree(lvds_connector->base.edid); | |
508 | ||
1d508706 | 509 | intel_panel_fini(&lvds_connector->base.panel); |
aaa6fd2a | 510 | |
79e53945 JB |
511 | drm_connector_cleanup(connector); |
512 | kfree(connector); | |
513 | } | |
514 | ||
335041ed JB |
515 | static int intel_lvds_set_property(struct drm_connector *connector, |
516 | struct drm_property *property, | |
517 | uint64_t value) | |
518 | { | |
4d891523 | 519 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3fbe18d6 | 520 | struct drm_device *dev = connector->dev; |
3fbe18d6 | 521 | |
788319d4 | 522 | if (property == dev->mode_config.scaling_mode_property) { |
62165e0d | 523 | struct drm_crtc *crtc; |
bb8a3560 | 524 | |
53bd8389 JB |
525 | if (value == DRM_MODE_SCALE_NONE) { |
526 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
788319d4 | 527 | return -EINVAL; |
3fbe18d6 | 528 | } |
788319d4 | 529 | |
4d891523 | 530 | if (intel_connector->panel.fitting_mode == value) { |
3fbe18d6 ZY |
531 | /* the LVDS scaling property is not changed */ |
532 | return 0; | |
533 | } | |
4d891523 | 534 | intel_connector->panel.fitting_mode = value; |
62165e0d JN |
535 | |
536 | crtc = intel_attached_encoder(connector)->base.crtc; | |
83d65738 | 537 | if (crtc && crtc->state->enable) { |
3fbe18d6 ZY |
538 | /* |
539 | * If the CRTC is enabled, the display will be changed | |
540 | * according to the new panel fitting mode. | |
541 | */ | |
c0c36b94 | 542 | intel_crtc_restore_mode(crtc); |
3fbe18d6 ZY |
543 | } |
544 | } | |
545 | ||
335041ed JB |
546 | return 0; |
547 | } | |
548 | ||
79e53945 JB |
549 | static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { |
550 | .get_modes = intel_lvds_get_modes, | |
551 | .mode_valid = intel_lvds_mode_valid, | |
df0e9248 | 552 | .best_encoder = intel_best_encoder, |
79e53945 JB |
553 | }; |
554 | ||
555 | static const struct drm_connector_funcs intel_lvds_connector_funcs = { | |
4d688a2a | 556 | .dpms = drm_atomic_helper_connector_dpms, |
79e53945 JB |
557 | .detect = intel_lvds_detect, |
558 | .fill_modes = drm_helper_probe_single_connector_modes, | |
335041ed | 559 | .set_property = intel_lvds_set_property, |
2545e4a6 | 560 | .atomic_get_property = intel_connector_atomic_get_property, |
79e53945 | 561 | .destroy = intel_lvds_destroy, |
c6f95f27 | 562 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 563 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
79e53945 JB |
564 | }; |
565 | ||
79e53945 | 566 | static const struct drm_encoder_funcs intel_lvds_enc_funcs = { |
ea5b213a | 567 | .destroy = intel_encoder_destroy, |
79e53945 JB |
568 | }; |
569 | ||
bbe1c274 | 570 | static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
425d244c | 571 | { |
bc0daf48 | 572 | DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); |
425d244c JW |
573 | return 1; |
574 | } | |
79e53945 | 575 | |
425d244c | 576 | /* These systems claim to have LVDS, but really don't */ |
93c05f22 | 577 | static const struct dmi_system_id intel_no_lvds[] = { |
425d244c JW |
578 | { |
579 | .callback = intel_no_lvds_dmi_callback, | |
580 | .ident = "Apple Mac Mini (Core series)", | |
581 | .matches = { | |
98acd46f | 582 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
583 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), |
584 | }, | |
585 | }, | |
586 | { | |
587 | .callback = intel_no_lvds_dmi_callback, | |
588 | .ident = "Apple Mac Mini (Core 2 series)", | |
589 | .matches = { | |
98acd46f | 590 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
591 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), |
592 | }, | |
593 | }, | |
594 | { | |
595 | .callback = intel_no_lvds_dmi_callback, | |
596 | .ident = "MSI IM-945GSE-A", | |
597 | .matches = { | |
598 | DMI_MATCH(DMI_SYS_VENDOR, "MSI"), | |
599 | DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), | |
600 | }, | |
601 | }, | |
602 | { | |
603 | .callback = intel_no_lvds_dmi_callback, | |
604 | .ident = "Dell Studio Hybrid", | |
605 | .matches = { | |
606 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
607 | DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), | |
608 | }, | |
609 | }, | |
70aa96ca JW |
610 | { |
611 | .callback = intel_no_lvds_dmi_callback, | |
b066254f PC |
612 | .ident = "Dell OptiPlex FX170", |
613 | .matches = { | |
614 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
615 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), | |
616 | }, | |
617 | }, | |
618 | { | |
619 | .callback = intel_no_lvds_dmi_callback, | |
70aa96ca JW |
620 | .ident = "AOpen Mini PC", |
621 | .matches = { | |
622 | DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), | |
623 | DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), | |
624 | }, | |
625 | }, | |
ed8c754b TV |
626 | { |
627 | .callback = intel_no_lvds_dmi_callback, | |
628 | .ident = "AOpen Mini PC MP915", | |
629 | .matches = { | |
630 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
631 | DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), | |
632 | }, | |
633 | }, | |
22ab70d3 KP |
634 | { |
635 | .callback = intel_no_lvds_dmi_callback, | |
636 | .ident = "AOpen i915GMm-HFS", | |
637 | .matches = { | |
638 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
639 | DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), | |
640 | }, | |
641 | }, | |
e57b6886 DV |
642 | { |
643 | .callback = intel_no_lvds_dmi_callback, | |
644 | .ident = "AOpen i45GMx-I", | |
645 | .matches = { | |
646 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
647 | DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), | |
648 | }, | |
649 | }, | |
fa0864b2 MC |
650 | { |
651 | .callback = intel_no_lvds_dmi_callback, | |
652 | .ident = "Aopen i945GTt-VFA", | |
653 | .matches = { | |
654 | DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), | |
655 | }, | |
656 | }, | |
9875557e SB |
657 | { |
658 | .callback = intel_no_lvds_dmi_callback, | |
659 | .ident = "Clientron U800", | |
660 | .matches = { | |
661 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
662 | DMI_MATCH(DMI_PRODUCT_NAME, "U800"), | |
663 | }, | |
664 | }, | |
6a574b5b | 665 | { |
44306ab3 JS |
666 | .callback = intel_no_lvds_dmi_callback, |
667 | .ident = "Clientron E830", | |
668 | .matches = { | |
669 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
670 | DMI_MATCH(DMI_PRODUCT_NAME, "E830"), | |
671 | }, | |
672 | }, | |
673 | { | |
6a574b5b HG |
674 | .callback = intel_no_lvds_dmi_callback, |
675 | .ident = "Asus EeeBox PC EB1007", | |
676 | .matches = { | |
677 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), | |
678 | DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), | |
679 | }, | |
680 | }, | |
0999bbe0 AJ |
681 | { |
682 | .callback = intel_no_lvds_dmi_callback, | |
683 | .ident = "Asus AT5NM10T-I", | |
684 | .matches = { | |
685 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
686 | DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), | |
687 | }, | |
688 | }, | |
33471119 JBG |
689 | { |
690 | .callback = intel_no_lvds_dmi_callback, | |
45a211d7 | 691 | .ident = "Hewlett-Packard HP t5740", |
33471119 JBG |
692 | .matches = { |
693 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
45a211d7 | 694 | DMI_MATCH(DMI_PRODUCT_NAME, " t5740"), |
33471119 JBG |
695 | }, |
696 | }, | |
f5b8a7ed MG |
697 | { |
698 | .callback = intel_no_lvds_dmi_callback, | |
699 | .ident = "Hewlett-Packard t5745", | |
700 | .matches = { | |
701 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
62004978 | 702 | DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), |
f5b8a7ed MG |
703 | }, |
704 | }, | |
705 | { | |
706 | .callback = intel_no_lvds_dmi_callback, | |
707 | .ident = "Hewlett-Packard st5747", | |
708 | .matches = { | |
709 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
62004978 | 710 | DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), |
f5b8a7ed MG |
711 | }, |
712 | }, | |
97effadb AA |
713 | { |
714 | .callback = intel_no_lvds_dmi_callback, | |
715 | .ident = "MSI Wind Box DC500", | |
716 | .matches = { | |
717 | DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), | |
718 | DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), | |
719 | }, | |
720 | }, | |
a51d4ed0 CW |
721 | { |
722 | .callback = intel_no_lvds_dmi_callback, | |
723 | .ident = "Gigabyte GA-D525TUD", | |
724 | .matches = { | |
725 | DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), | |
726 | DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), | |
727 | }, | |
728 | }, | |
c31407a3 CW |
729 | { |
730 | .callback = intel_no_lvds_dmi_callback, | |
731 | .ident = "Supermicro X7SPA-H", | |
732 | .matches = { | |
733 | DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), | |
734 | DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), | |
735 | }, | |
736 | }, | |
9e9dd0e8 CL |
737 | { |
738 | .callback = intel_no_lvds_dmi_callback, | |
739 | .ident = "Fujitsu Esprimo Q900", | |
740 | .matches = { | |
741 | DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), | |
742 | DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"), | |
743 | }, | |
744 | }, | |
645378d8 RP |
745 | { |
746 | .callback = intel_no_lvds_dmi_callback, | |
747 | .ident = "Intel D410PT", | |
748 | .matches = { | |
749 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
750 | DMI_MATCH(DMI_BOARD_NAME, "D410PT"), | |
751 | }, | |
752 | }, | |
753 | { | |
754 | .callback = intel_no_lvds_dmi_callback, | |
755 | .ident = "Intel D425KT", | |
756 | .matches = { | |
757 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
758 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"), | |
759 | }, | |
760 | }, | |
e5614f0c CW |
761 | { |
762 | .callback = intel_no_lvds_dmi_callback, | |
763 | .ident = "Intel D510MO", | |
764 | .matches = { | |
765 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
766 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"), | |
767 | }, | |
768 | }, | |
dcf6d294 JN |
769 | { |
770 | .callback = intel_no_lvds_dmi_callback, | |
771 | .ident = "Intel D525MW", | |
772 | .matches = { | |
773 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
774 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"), | |
775 | }, | |
776 | }, | |
425d244c JW |
777 | |
778 | { } /* terminating entry */ | |
779 | }; | |
79e53945 | 780 | |
7cf4f69d ZY |
781 | /* |
782 | * Enumerate the child dev array parsed from VBT to check whether | |
783 | * the LVDS is present. | |
784 | * If it is present, return 1. | |
785 | * If it is not present, return false. | |
786 | * If no child dev is parsed from VBT, it assumes that the LVDS is present. | |
7cf4f69d | 787 | */ |
270eea0f CW |
788 | static bool lvds_is_present_in_vbt(struct drm_device *dev, |
789 | u8 *i2c_pin) | |
7cf4f69d ZY |
790 | { |
791 | struct drm_i915_private *dev_priv = dev->dev_private; | |
425904dd | 792 | int i; |
7cf4f69d | 793 | |
41aa3448 | 794 | if (!dev_priv->vbt.child_dev_num) |
425904dd | 795 | return true; |
7cf4f69d | 796 | |
41aa3448 | 797 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
768f69c9 PZ |
798 | union child_device_config *uchild = dev_priv->vbt.child_dev + i; |
799 | struct old_child_dev_config *child = &uchild->old; | |
425904dd CW |
800 | |
801 | /* If the device type is not LFP, continue. | |
802 | * We have to check both the new identifiers as well as the | |
803 | * old for compatibility with some BIOSes. | |
7cf4f69d | 804 | */ |
425904dd CW |
805 | if (child->device_type != DEVICE_TYPE_INT_LFP && |
806 | child->device_type != DEVICE_TYPE_LFP) | |
7cf4f69d ZY |
807 | continue; |
808 | ||
88ac7939 | 809 | if (intel_gmbus_is_valid_pin(dev_priv, child->i2c_pin)) |
3bd7d909 | 810 | *i2c_pin = child->i2c_pin; |
270eea0f | 811 | |
425904dd CW |
812 | /* However, we cannot trust the BIOS writers to populate |
813 | * the VBT correctly. Since LVDS requires additional | |
814 | * information from AIM blocks, a non-zero addin offset is | |
815 | * a good indicator that the LVDS is actually present. | |
7cf4f69d | 816 | */ |
425904dd CW |
817 | if (child->addin_offset) |
818 | return true; | |
819 | ||
820 | /* But even then some BIOS writers perform some black magic | |
821 | * and instantiate the device without reference to any | |
822 | * additional data. Trust that if the VBT was written into | |
823 | * the OpRegion then they have validated the LVDS's existence. | |
824 | */ | |
825 | if (dev_priv->opregion.vbt) | |
826 | return true; | |
7cf4f69d | 827 | } |
425904dd CW |
828 | |
829 | return false; | |
7cf4f69d ZY |
830 | } |
831 | ||
1974cad0 DV |
832 | static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) |
833 | { | |
834 | DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); | |
835 | return 1; | |
836 | } | |
837 | ||
838 | static const struct dmi_system_id intel_dual_link_lvds[] = { | |
839 | { | |
840 | .callback = intel_dual_link_lvds_callback, | |
3916e3fd LW |
841 | .ident = "Apple MacBook Pro 15\" (2010)", |
842 | .matches = { | |
843 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
844 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"), | |
845 | }, | |
846 | }, | |
847 | { | |
848 | .callback = intel_dual_link_lvds_callback, | |
849 | .ident = "Apple MacBook Pro 15\" (2011)", | |
1974cad0 DV |
850 | .matches = { |
851 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
852 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), | |
853 | }, | |
854 | }, | |
3916e3fd LW |
855 | { |
856 | .callback = intel_dual_link_lvds_callback, | |
857 | .ident = "Apple MacBook Pro 15\" (2012)", | |
858 | .matches = { | |
859 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
860 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"), | |
861 | }, | |
862 | }, | |
1974cad0 DV |
863 | { } /* terminating entry */ |
864 | }; | |
865 | ||
866 | bool intel_is_dual_link_lvds(struct drm_device *dev) | |
13c7d870 DV |
867 | { |
868 | struct intel_encoder *encoder; | |
869 | struct intel_lvds_encoder *lvds_encoder; | |
870 | ||
b2784e15 | 871 | for_each_intel_encoder(dev, encoder) { |
13c7d870 DV |
872 | if (encoder->type == INTEL_OUTPUT_LVDS) { |
873 | lvds_encoder = to_lvds_encoder(&encoder->base); | |
874 | ||
875 | return lvds_encoder->is_dual_link; | |
876 | } | |
877 | } | |
878 | ||
879 | return false; | |
880 | } | |
881 | ||
7dec0606 | 882 | static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) |
1974cad0 | 883 | { |
7dec0606 | 884 | struct drm_device *dev = lvds_encoder->base.base.dev; |
1974cad0 DV |
885 | unsigned int val; |
886 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1974cad0 DV |
887 | |
888 | /* use the module option value if specified */ | |
d330a953 JN |
889 | if (i915.lvds_channel_mode > 0) |
890 | return i915.lvds_channel_mode == 2; | |
1974cad0 | 891 | |
6f317cfe LW |
892 | /* single channel LVDS is limited to 112 MHz */ |
893 | if (lvds_encoder->attached_connector->base.panel.fixed_mode->clock | |
894 | > 112999) | |
895 | return true; | |
896 | ||
1974cad0 DV |
897 | if (dmi_check_system(intel_dual_link_lvds)) |
898 | return true; | |
899 | ||
13c7d870 DV |
900 | /* BIOS should set the proper LVDS register value at boot, but |
901 | * in reality, it doesn't set the value when the lid is closed; | |
902 | * we need to check "the value to be set" in VBT when LVDS | |
903 | * register is uninitialized. | |
904 | */ | |
7dec0606 | 905 | val = I915_READ(lvds_encoder->reg); |
13c7d870 | 906 | if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED))) |
41aa3448 | 907 | val = dev_priv->vbt.bios_lvds_val; |
13c7d870 | 908 | |
1974cad0 DV |
909 | return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; |
910 | } | |
911 | ||
f3cfcba6 CW |
912 | static bool intel_lvds_supported(struct drm_device *dev) |
913 | { | |
914 | /* With the introduction of the PCH we gained a dedicated | |
915 | * LVDS presence pin, use it. */ | |
311e359c | 916 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
f3cfcba6 CW |
917 | return true; |
918 | ||
919 | /* Otherwise LVDS was only attached to mobile products, | |
920 | * except for the inglorious 830gm */ | |
311e359c PZ |
921 | if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) |
922 | return true; | |
923 | ||
924 | return false; | |
f3cfcba6 CW |
925 | } |
926 | ||
79e53945 JB |
927 | /** |
928 | * intel_lvds_init - setup LVDS connectors on this device | |
929 | * @dev: drm device | |
930 | * | |
931 | * Create the connector, register the LVDS DDC bus, and try to figure out what | |
932 | * modes we can display on the LVDS panel (if present). | |
933 | */ | |
c9093354 | 934 | void intel_lvds_init(struct drm_device *dev) |
79e53945 JB |
935 | { |
936 | struct drm_i915_private *dev_priv = dev->dev_private; | |
29b99b48 | 937 | struct intel_lvds_encoder *lvds_encoder; |
21d40d37 | 938 | struct intel_encoder *intel_encoder; |
c7362c4d | 939 | struct intel_lvds_connector *lvds_connector; |
bb8a3560 | 940 | struct intel_connector *intel_connector; |
79e53945 JB |
941 | struct drm_connector *connector; |
942 | struct drm_encoder *encoder; | |
943 | struct drm_display_mode *scan; /* *modes, *bios_mode; */ | |
dd06f90e | 944 | struct drm_display_mode *fixed_mode = NULL; |
4b6ed685 | 945 | struct drm_display_mode *downclock_mode = NULL; |
9cd300e0 | 946 | struct edid *edid; |
79e53945 | 947 | struct drm_crtc *crtc; |
f0f59a00 | 948 | i915_reg_t lvds_reg; |
79e53945 | 949 | u32 lvds; |
270eea0f CW |
950 | int pipe; |
951 | u8 pin; | |
79e53945 | 952 | |
b0616c53 DV |
953 | /* |
954 | * Unlock registers and just leave them unlocked. Do this before | |
955 | * checking quirk lists to avoid bogus WARNINGs. | |
956 | */ | |
957 | if (HAS_PCH_SPLIT(dev)) { | |
958 | I915_WRITE(PCH_PP_CONTROL, | |
959 | I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS); | |
c5796b71 | 960 | } else if (INTEL_INFO(dev_priv)->gen < 5) { |
b0616c53 DV |
961 | I915_WRITE(PP_CONTROL, |
962 | I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); | |
963 | } | |
f3cfcba6 | 964 | if (!intel_lvds_supported(dev)) |
c9093354 | 965 | return; |
f3cfcba6 | 966 | |
425d244c JW |
967 | /* Skip init on machines we know falsely report LVDS */ |
968 | if (dmi_check_system(intel_no_lvds)) | |
c9093354 | 969 | return; |
565dcd46 | 970 | |
d0669d00 VS |
971 | if (HAS_PCH_SPLIT(dev)) |
972 | lvds_reg = PCH_LVDS; | |
973 | else | |
974 | lvds_reg = LVDS; | |
975 | ||
976 | lvds = I915_READ(lvds_reg); | |
977 | ||
c619eed4 | 978 | if (HAS_PCH_SPLIT(dev)) { |
d0669d00 | 979 | if ((lvds & LVDS_DETECTED) == 0) |
c9093354 | 980 | return; |
41aa3448 | 981 | if (dev_priv->vbt.edp_support) { |
28c97730 | 982 | DRM_DEBUG_KMS("disable LVDS for eDP support\n"); |
c9093354 | 983 | return; |
32f9d658 | 984 | } |
541998a1 ZW |
985 | } |
986 | ||
eebaed64 CW |
987 | pin = GMBUS_PIN_PANEL; |
988 | if (!lvds_is_present_in_vbt(dev, &pin)) { | |
d0669d00 | 989 | if ((lvds & LVDS_PORT_EN) == 0) { |
eebaed64 CW |
990 | DRM_DEBUG_KMS("LVDS is not present in VBT\n"); |
991 | return; | |
992 | } | |
993 | DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n"); | |
994 | } | |
995 | ||
96d12cbd ID |
996 | /* Set the Panel Power On/Off timings if uninitialized. */ |
997 | if (INTEL_INFO(dev_priv)->gen < 5 && | |
998 | I915_READ(PP_ON_DELAYS) == 0 && I915_READ(PP_OFF_DELAYS) == 0) { | |
999 | /* Set T2 to 40ms and T5 to 200ms */ | |
1000 | I915_WRITE(PP_ON_DELAYS, 0x019007d0); | |
1001 | ||
1002 | /* Set T3 to 35ms and Tx to 200ms */ | |
1003 | I915_WRITE(PP_OFF_DELAYS, 0x015e07d0); | |
1004 | ||
1005 | DRM_DEBUG_KMS("Panel power timings uninitialized, setting defaults\n"); | |
1006 | } | |
1007 | ||
b14c5679 | 1008 | lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL); |
29b99b48 | 1009 | if (!lvds_encoder) |
c9093354 | 1010 | return; |
79e53945 | 1011 | |
b14c5679 | 1012 | lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL); |
c7362c4d | 1013 | if (!lvds_connector) { |
29b99b48 | 1014 | kfree(lvds_encoder); |
c9093354 | 1015 | return; |
bb8a3560 ZW |
1016 | } |
1017 | ||
9bdbd0b9 ACO |
1018 | if (intel_connector_init(&lvds_connector->base) < 0) { |
1019 | kfree(lvds_connector); | |
1020 | kfree(lvds_encoder); | |
1021 | return; | |
1022 | } | |
1023 | ||
62165e0d JN |
1024 | lvds_encoder->attached_connector = lvds_connector; |
1025 | ||
29b99b48 | 1026 | intel_encoder = &lvds_encoder->base; |
4ef69c7a | 1027 | encoder = &intel_encoder->base; |
c7362c4d | 1028 | intel_connector = &lvds_connector->base; |
ea5b213a | 1029 | connector = &intel_connector->base; |
bb8a3560 | 1030 | drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, |
79e53945 JB |
1031 | DRM_MODE_CONNECTOR_LVDS); |
1032 | ||
4ef69c7a | 1033 | drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, |
13a3d91f | 1034 | DRM_MODE_ENCODER_LVDS, NULL); |
79e53945 | 1035 | |
c22834ec | 1036 | intel_encoder->enable = intel_enable_lvds; |
f6736a1a | 1037 | intel_encoder->pre_enable = intel_pre_enable_lvds; |
7ae89233 | 1038 | intel_encoder->compute_config = intel_lvds_compute_config; |
d26a5b6e VS |
1039 | if (HAS_PCH_SPLIT(dev_priv)) { |
1040 | intel_encoder->disable = pch_disable_lvds; | |
1041 | intel_encoder->post_disable = pch_post_disable_lvds; | |
1042 | } else { | |
1043 | intel_encoder->disable = gmch_disable_lvds; | |
1044 | } | |
b1dc332c | 1045 | intel_encoder->get_hw_state = intel_lvds_get_hw_state; |
045ac3b5 | 1046 | intel_encoder->get_config = intel_lvds_get_config; |
b1dc332c | 1047 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
4932e2c3 | 1048 | intel_connector->unregister = intel_connector_unregister; |
c22834ec | 1049 | |
df0e9248 | 1050 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
21d40d37 | 1051 | intel_encoder->type = INTEL_OUTPUT_LVDS; |
79e53945 | 1052 | |
bc079e8b | 1053 | intel_encoder->cloneable = 0; |
27f8227b JB |
1054 | if (HAS_PCH_SPLIT(dev)) |
1055 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
0b9f43a0 DV |
1056 | else if (IS_GEN4(dev)) |
1057 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
27f8227b JB |
1058 | else |
1059 | intel_encoder->crtc_mask = (1 << 1); | |
1060 | ||
79e53945 JB |
1061 | drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); |
1062 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
1063 | connector->interlace_allowed = false; | |
1064 | connector->doublescan_allowed = false; | |
1065 | ||
d0669d00 | 1066 | lvds_encoder->reg = lvds_reg; |
7dec0606 | 1067 | |
3fbe18d6 ZY |
1068 | /* create the scaling mode property */ |
1069 | drm_mode_create_scaling_mode_property(dev); | |
662595df | 1070 | drm_object_attach_property(&connector->base, |
3fbe18d6 | 1071 | dev->mode_config.scaling_mode_property, |
dd1ea37d | 1072 | DRM_MODE_SCALE_ASPECT); |
4d891523 | 1073 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
79e53945 JB |
1074 | /* |
1075 | * LVDS discovery: | |
1076 | * 1) check for EDID on DDC | |
1077 | * 2) check for VBT data | |
1078 | * 3) check to see if LVDS is already on | |
1079 | * if none of the above, no panel | |
1080 | * 4) make sure lid is open | |
1081 | * if closed, act like it's not there for now | |
1082 | */ | |
1083 | ||
79e53945 JB |
1084 | /* |
1085 | * Attempt to get the fixed panel mode from DDC. Assume that the | |
1086 | * preferred mode is the right one. | |
1087 | */ | |
4da98541 | 1088 | mutex_lock(&dev->mode_config.mutex); |
4eddaeec LW |
1089 | if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC) |
1090 | edid = drm_get_edid_switcheroo(connector, | |
1091 | intel_gmbus_get_adapter(dev_priv, pin)); | |
1092 | else | |
1093 | edid = drm_get_edid(connector, | |
1094 | intel_gmbus_get_adapter(dev_priv, pin)); | |
9cd300e0 JN |
1095 | if (edid) { |
1096 | if (drm_add_edid_modes(connector, edid)) { | |
3f8ff0e7 | 1097 | drm_mode_connector_update_edid_property(connector, |
9cd300e0 | 1098 | edid); |
3f8ff0e7 | 1099 | } else { |
9cd300e0 JN |
1100 | kfree(edid); |
1101 | edid = ERR_PTR(-EINVAL); | |
3f8ff0e7 | 1102 | } |
9cd300e0 JN |
1103 | } else { |
1104 | edid = ERR_PTR(-ENOENT); | |
3f8ff0e7 | 1105 | } |
9cd300e0 JN |
1106 | lvds_connector->base.edid = edid; |
1107 | ||
1108 | if (IS_ERR_OR_NULL(edid)) { | |
788319d4 CW |
1109 | /* Didn't get an EDID, so |
1110 | * Set wide sync ranges so we get all modes | |
1111 | * handed to valid_mode for checking | |
1112 | */ | |
1113 | connector->display_info.min_vfreq = 0; | |
1114 | connector->display_info.max_vfreq = 200; | |
1115 | connector->display_info.min_hfreq = 0; | |
1116 | connector->display_info.max_hfreq = 200; | |
1117 | } | |
79e53945 JB |
1118 | |
1119 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
79e53945 | 1120 | if (scan->type & DRM_MODE_TYPE_PREFERRED) { |
6a9d51b7 CW |
1121 | DRM_DEBUG_KMS("using preferred mode from EDID: "); |
1122 | drm_mode_debug_printmodeline(scan); | |
1123 | ||
dd06f90e | 1124 | fixed_mode = drm_mode_duplicate(dev, scan); |
c329a4ec | 1125 | if (fixed_mode) |
6a9d51b7 | 1126 | goto out; |
79e53945 | 1127 | } |
79e53945 JB |
1128 | } |
1129 | ||
1130 | /* Failed to get EDID, what about VBT? */ | |
41aa3448 | 1131 | if (dev_priv->vbt.lfp_lvds_vbt_mode) { |
6a9d51b7 | 1132 | DRM_DEBUG_KMS("using mode from VBT: "); |
41aa3448 | 1133 | drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode); |
6a9d51b7 | 1134 | |
41aa3448 | 1135 | fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode); |
dd06f90e JN |
1136 | if (fixed_mode) { |
1137 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
e285f3cd JB |
1138 | goto out; |
1139 | } | |
79e53945 JB |
1140 | } |
1141 | ||
1142 | /* | |
1143 | * If we didn't get EDID, try checking if the panel is already turned | |
1144 | * on. If so, assume that whatever is currently programmed is the | |
1145 | * correct mode. | |
1146 | */ | |
541998a1 | 1147 | |
f2b115e6 | 1148 | /* Ironlake: FIXME if still fail, not try pipe mode now */ |
c619eed4 | 1149 | if (HAS_PCH_SPLIT(dev)) |
541998a1 ZW |
1150 | goto failed; |
1151 | ||
79e53945 | 1152 | pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; |
f875c15a | 1153 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
79e53945 JB |
1154 | |
1155 | if (crtc && (lvds & LVDS_PORT_EN)) { | |
dd06f90e JN |
1156 | fixed_mode = intel_crtc_mode_get(dev, crtc); |
1157 | if (fixed_mode) { | |
6a9d51b7 CW |
1158 | DRM_DEBUG_KMS("using current (BIOS) mode: "); |
1159 | drm_mode_debug_printmodeline(fixed_mode); | |
dd06f90e | 1160 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
565dcd46 | 1161 | goto out; |
79e53945 JB |
1162 | } |
1163 | } | |
1164 | ||
1165 | /* If we still don't have a mode after all that, give up. */ | |
dd06f90e | 1166 | if (!fixed_mode) |
79e53945 JB |
1167 | goto failed; |
1168 | ||
79e53945 | 1169 | out: |
4da98541 DV |
1170 | mutex_unlock(&dev->mode_config.mutex); |
1171 | ||
6f317cfe LW |
1172 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
1173 | ||
7dec0606 | 1174 | lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); |
13c7d870 DV |
1175 | DRM_DEBUG_KMS("detected %s-link lvds configuration\n", |
1176 | lvds_encoder->is_dual_link ? "dual" : "single"); | |
1177 | ||
af9b9c19 | 1178 | lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK; |
1f835a77 | 1179 | |
db1740a0 JN |
1180 | lvds_connector->lid_notifier.notifier_call = intel_lid_notify; |
1181 | if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) { | |
28c97730 | 1182 | DRM_DEBUG_KMS("lid notifier registration failed\n"); |
db1740a0 | 1183 | lvds_connector->lid_notifier.notifier_call = NULL; |
c1c7af60 | 1184 | } |
34ea3d38 | 1185 | drm_connector_register(connector); |
aaa6fd2a | 1186 | |
6517d273 | 1187 | intel_panel_setup_backlight(connector, INVALID_PIPE); |
aaa6fd2a | 1188 | |
c9093354 | 1189 | return; |
79e53945 JB |
1190 | |
1191 | failed: | |
4da98541 DV |
1192 | mutex_unlock(&dev->mode_config.mutex); |
1193 | ||
8a4c47f3 | 1194 | DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); |
79e53945 | 1195 | drm_connector_cleanup(connector); |
1991bdfa | 1196 | drm_encoder_cleanup(encoder); |
29b99b48 | 1197 | kfree(lvds_encoder); |
c7362c4d | 1198 | kfree(lvds_connector); |
c9093354 | 1199 | return; |
79e53945 | 1200 | } |