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Merge branches 'amd-iommu/fixes' and 'dma-debug/fixes' into iommu/fixes
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_lvds.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 */
29
c1c7af60 30#include <acpi/button.h>
565dcd46 31#include <linux/dmi.h>
79e53945
JB		 32#include <linux/i2c.h>
33#include "drmP.h"
34#include "drm.h"
35#include "drm_crtc.h"
36#include "drm_edid.h"
37#include "intel_drv.h"
38#include "i915_drm.h"
39#include "i915_drv.h"
e99da35f 40#include <linux/acpi.h>
79e53945 41
3fbe18d6
ZY		 42/* Private structure for the integrated LVDS support */
43struct intel_lvds_priv {
44 int fitting_mode;
45 u32 pfit_control;
46 u32 pfit_pgm_ratios;
47};
48
79e53945
JB		 49/**
50 * Sets the backlight level.
51 *
52 * \param level backlight level, from 0 to intel_lvds_get_max_backlight().
53 */
54static void intel_lvds_set_backlight(struct drm_device *dev, int level)
55{
56 struct drm_i915_private *dev_priv = dev->dev_private;
541998a1 57 u32 blc_pwm_ctl, reg;
79e53945 58
f2b115e6 59 if (IS_IRONLAKE(dev))
541998a1
ZW		 60 reg = BLC_PWM_CPU_CTL;
61 else
62 reg = BLC_PWM_CTL;
79e53945 63
541998a1
ZW		 64 blc_pwm_ctl = I915_READ(reg) & ~BACKLIGHT_DUTY_CYCLE_MASK;
65 I915_WRITE(reg, (blc_pwm_ctl |
79e53945
JB		 66 (level << BACKLIGHT_DUTY_CYCLE_SHIFT)));
67}
68
69/**
70 * Returns the maximum level of the backlight duty cycle field.
71 */
72static u32 intel_lvds_get_max_backlight(struct drm_device *dev)
73{
74 struct drm_i915_private *dev_priv = dev->dev_private;
541998a1
ZW		 75 u32 reg;
76
f2b115e6 77 if (IS_IRONLAKE(dev))
541998a1
ZW		 78 reg = BLC_PWM_PCH_CTL2;
79 else
80 reg = BLC_PWM_CTL;
79e53945 81
541998a1 82 return ((I915_READ(reg) & BACKLIGHT_MODULATION_FREQ_MASK) >>
79e53945
JB		 83 BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
84}
85
86/**
87 * Sets the power state for the panel.
88 */
89static void intel_lvds_set_power(struct drm_device *dev, bool on)
90{
91 struct drm_i915_private *dev_priv = dev->dev_private;
541998a1
ZW		 92 u32 pp_status, ctl_reg, status_reg;
93
f2b115e6 94 if (IS_IRONLAKE(dev)) {
541998a1
ZW		 95 ctl_reg = PCH_PP_CONTROL;
96 status_reg = PCH_PP_STATUS;
97 } else {
98 ctl_reg = PP_CONTROL;
99 status_reg = PP_STATUS;
100 }
79e53945
JB		 101
102 if (on) {
541998a1 103 I915_WRITE(ctl_reg, I915_READ(ctl_reg) |
79e53945
JB		 104 POWER_TARGET_ON);
105 do {
541998a1 106 pp_status = I915_READ(status_reg);
79e53945
JB		 107 } while ((pp_status & PP_ON) == 0);
108
109 intel_lvds_set_backlight(dev, dev_priv->backlight_duty_cycle);
110 } else {
111 intel_lvds_set_backlight(dev, 0);
112
541998a1 113 I915_WRITE(ctl_reg, I915_READ(ctl_reg) &
79e53945
JB		 114 ~POWER_TARGET_ON);
115 do {
541998a1 116 pp_status = I915_READ(status_reg);
79e53945
JB		 117 } while (pp_status & PP_ON);
118 }
119}
120
121static void intel_lvds_dpms(struct drm_encoder *encoder, int mode)
122{
123 struct drm_device *dev = encoder->dev;
124
125 if (mode == DRM_MODE_DPMS_ON)
126 intel_lvds_set_power(dev, true);
127 else
128 intel_lvds_set_power(dev, false);
129
130 /* XXX: We never power down the LVDS pairs. */
131}
132
133static void intel_lvds_save(struct drm_connector *connector)
134{
135 struct drm_device *dev = connector->dev;
136 struct drm_i915_private *dev_priv = dev->dev_private;
541998a1
ZW		 137 u32 pp_on_reg, pp_off_reg, pp_ctl_reg, pp_div_reg;
138 u32 pwm_ctl_reg;
139
f2b115e6 140 if (IS_IRONLAKE(dev)) {
541998a1
ZW		 141 pp_on_reg = PCH_PP_ON_DELAYS;
142 pp_off_reg = PCH_PP_OFF_DELAYS;
143 pp_ctl_reg = PCH_PP_CONTROL;
144 pp_div_reg = PCH_PP_DIVISOR;
145 pwm_ctl_reg = BLC_PWM_CPU_CTL;
146 } else {
147 pp_on_reg = PP_ON_DELAYS;
148 pp_off_reg = PP_OFF_DELAYS;
149 pp_ctl_reg = PP_CONTROL;
150 pp_div_reg = PP_DIVISOR;
151 pwm_ctl_reg = BLC_PWM_CTL;
152 }
79e53945 153
541998a1
ZW		 154 dev_priv->savePP_ON = I915_READ(pp_on_reg);
155 dev_priv->savePP_OFF = I915_READ(pp_off_reg);
156 dev_priv->savePP_CONTROL = I915_READ(pp_ctl_reg);
157 dev_priv->savePP_DIVISOR = I915_READ(pp_div_reg);
158 dev_priv->saveBLC_PWM_CTL = I915_READ(pwm_ctl_reg);
79e53945
JB		 159 dev_priv->backlight_duty_cycle = (dev_priv->saveBLC_PWM_CTL &
160 BACKLIGHT_DUTY_CYCLE_MASK);
161
162 /*
163 * If the light is off at server startup, just make it full brightness
164 */
165 if (dev_priv->backlight_duty_cycle == 0)
166 dev_priv->backlight_duty_cycle =
167 intel_lvds_get_max_backlight(dev);
168}
169
170static void intel_lvds_restore(struct drm_connector *connector)
171{
172 struct drm_device *dev = connector->dev;
173 struct drm_i915_private *dev_priv = dev->dev_private;
541998a1
ZW		 174 u32 pp_on_reg, pp_off_reg, pp_ctl_reg, pp_div_reg;
175 u32 pwm_ctl_reg;
176
f2b115e6 177 if (IS_IRONLAKE(dev)) {
541998a1
ZW		 178 pp_on_reg = PCH_PP_ON_DELAYS;
179 pp_off_reg = PCH_PP_OFF_DELAYS;
180 pp_ctl_reg = PCH_PP_CONTROL;
181 pp_div_reg = PCH_PP_DIVISOR;
182 pwm_ctl_reg = BLC_PWM_CPU_CTL;
183 } else {
184 pp_on_reg = PP_ON_DELAYS;
185 pp_off_reg = PP_OFF_DELAYS;
186 pp_ctl_reg = PP_CONTROL;
187 pp_div_reg = PP_DIVISOR;
188 pwm_ctl_reg = BLC_PWM_CTL;
189 }
79e53945 190
541998a1
ZW		 191 I915_WRITE(pwm_ctl_reg, dev_priv->saveBLC_PWM_CTL);
192 I915_WRITE(pp_on_reg, dev_priv->savePP_ON);
193 I915_WRITE(pp_off_reg, dev_priv->savePP_OFF);
194 I915_WRITE(pp_div_reg, dev_priv->savePP_DIVISOR);
195 I915_WRITE(pp_ctl_reg, dev_priv->savePP_CONTROL);
79e53945
JB		 196 if (dev_priv->savePP_CONTROL & POWER_TARGET_ON)
197 intel_lvds_set_power(dev, true);
198 else
199 intel_lvds_set_power(dev, false);
200}
201
202static int intel_lvds_mode_valid(struct drm_connector *connector,
203 struct drm_display_mode *mode)
204{
205 struct drm_device *dev = connector->dev;
206 struct drm_i915_private *dev_priv = dev->dev_private;
207 struct drm_display_mode *fixed_mode = dev_priv->panel_fixed_mode;
208
209 if (fixed_mode) {
210 if (mode->hdisplay > fixed_mode->hdisplay)
211 return MODE_PANEL;
212 if (mode->vdisplay > fixed_mode->vdisplay)
213 return MODE_PANEL;
214 }
215
216 return MODE_OK;
217}
218
219static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
220 struct drm_display_mode *mode,
221 struct drm_display_mode *adjusted_mode)
222{
3fbe18d6
ZY		 223 /*
224 * float point operation is not supported . So the PANEL_RATIO_FACTOR
225 * is defined, which can avoid the float point computation when
226 * calculating the panel ratio.
227 */
228#define PANEL_RATIO_FACTOR 8192
79e53945
JB		 229 struct drm_device *dev = encoder->dev;
230 struct drm_i915_private *dev_priv = dev->dev_private;
231 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
232 struct drm_encoder *tmp_encoder;
3fbe18d6
ZY		 233 struct intel_output *intel_output = enc_to_intel_output(encoder);
234 struct intel_lvds_priv *lvds_priv = intel_output->dev_priv;
235 u32 pfit_control = 0, pfit_pgm_ratios = 0;
236 int left_border = 0, right_border = 0, top_border = 0;
237 int bottom_border = 0;
238 bool border = 0;
239 int panel_ratio, desired_ratio, vert_scale, horiz_scale;
240 int horiz_ratio, vert_ratio;
aa0261f2
ZY		 241 u32 hsync_width, vsync_width;
242 u32 hblank_width, vblank_width;
243 u32 hsync_pos, vsync_pos;
79e53945
JB		 244
245 /* Should never happen!! */
246 if (!IS_I965G(dev) && intel_crtc->pipe == 0) {
1ae8c0a5 247 DRM_ERROR("Can't support LVDS on pipe A\n");
79e53945
JB		 248 return false;
249 }
250
251 /* Should never happen!! */
252 list_for_each_entry(tmp_encoder, &dev->mode_config.encoder_list, head) {
253 if (tmp_encoder != encoder && tmp_encoder->crtc == encoder->crtc) {
1ae8c0a5 254 DRM_ERROR("Can't enable LVDS and another "
79e53945
JB		 255 "encoder on the same pipe\n");
256 return false;
257 }
258 }
3fbe18d6
ZY		 259 /* If we don't have a panel mode, there is nothing we can do */
260 if (dev_priv->panel_fixed_mode == NULL)
261 return true;
79e53945
JB		 262 /*
263 * If we have timings from the BIOS for the panel, put them in
264 * to the adjusted mode. The CRTC will be set up for this mode,
265 * with the panel scaling set up to source from the H/VDisplay
266 * of the original mode.
267 */
268 if (dev_priv->panel_fixed_mode != NULL) {
269 adjusted_mode->hdisplay = dev_priv->panel_fixed_mode->hdisplay;
270 adjusted_mode->hsync_start =
271 dev_priv->panel_fixed_mode->hsync_start;
272 adjusted_mode->hsync_end =
273 dev_priv->panel_fixed_mode->hsync_end;
274 adjusted_mode->htotal = dev_priv->panel_fixed_mode->htotal;
275 adjusted_mode->vdisplay = dev_priv->panel_fixed_mode->vdisplay;
276 adjusted_mode->vsync_start =
277 dev_priv->panel_fixed_mode->vsync_start;
278 adjusted_mode->vsync_end =
279 dev_priv->panel_fixed_mode->vsync_end;
280 adjusted_mode->vtotal = dev_priv->panel_fixed_mode->vtotal;
281 adjusted_mode->clock = dev_priv->panel_fixed_mode->clock;
282 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
283 }
284
3fbe18d6
ZY		 285 /* Make sure pre-965s set dither correctly */
286 if (!IS_I965G(dev)) {
287 if (dev_priv->panel_wants_dither || dev_priv->lvds_dither)
288 pfit_control |= PANEL_8TO6_DITHER_ENABLE;
289 }
290
291 /* Native modes don't need fitting */
292 if (adjusted_mode->hdisplay == mode->hdisplay &&
293 adjusted_mode->vdisplay == mode->vdisplay) {
294 pfit_pgm_ratios = 0;
295 border = 0;
296 goto out;
297 }
298
8dd81a38 299 /* full screen scale for now */
f2b115e6 300 if (IS_IRONLAKE(dev))
8dd81a38
ZW		 301 goto out;
302
3fbe18d6
ZY		 303 /* 965+ wants fuzzy fitting */
304 if (IS_I965G(dev))
305 pfit_control |= (intel_crtc->pipe << PFIT_PIPE_SHIFT) |
306 PFIT_FILTER_FUZZY;
307
aa0261f2
ZY		 308 hsync_width = adjusted_mode->crtc_hsync_end -
309 adjusted_mode->crtc_hsync_start;
310 vsync_width = adjusted_mode->crtc_vsync_end -
311 adjusted_mode->crtc_vsync_start;
312 hblank_width = adjusted_mode->crtc_hblank_end -
313 adjusted_mode->crtc_hblank_start;
314 vblank_width = adjusted_mode->crtc_vblank_end -
315 adjusted_mode->crtc_vblank_start;
3fbe18d6
ZY		 316 /*
317 * Deal with panel fitting options. Figure out how to stretch the
318 * image based on its aspect ratio & the current panel fitting mode.
319 */
320 panel_ratio = adjusted_mode->hdisplay * PANEL_RATIO_FACTOR /
321 adjusted_mode->vdisplay;
322 desired_ratio = mode->hdisplay * PANEL_RATIO_FACTOR /
323 mode->vdisplay;
324 /*
325 * Enable automatic panel scaling for non-native modes so that they fill
326 * the screen. Should be enabled before the pipe is enabled, according
327 * to register description and PRM.
328 * Change the value here to see the borders for debugging
329 */
f2b115e6 330 if (!IS_IRONLAKE(dev)) {
8dd81a38
ZW		 331 I915_WRITE(BCLRPAT_A, 0);
332 I915_WRITE(BCLRPAT_B, 0);
333 }
3fbe18d6
ZY		 334
335 switch (lvds_priv->fitting_mode) {
53bd8389 336 case DRM_MODE_SCALE_CENTER:
3fbe18d6
ZY		 337 /*
338 * For centered modes, we have to calculate border widths &
339 * heights and modify the values programmed into the CRTC.
340 */
341 left_border = (adjusted_mode->hdisplay - mode->hdisplay) / 2;
342 right_border = left_border;
343 if (mode->hdisplay & 1)
344 right_border++;
345 top_border = (adjusted_mode->vdisplay - mode->vdisplay) / 2;
346 bottom_border = top_border;
347 if (mode->vdisplay & 1)
348 bottom_border++;
349 /* Set active & border values */
350 adjusted_mode->crtc_hdisplay = mode->hdisplay;
aa0261f2
ZY		 351 /* Keep the boder be even */
352 if (right_border & 1)
353 right_border++;
354 /* use the border directly instead of border minuse one */
3fbe18d6 355 adjusted_mode->crtc_hblank_start = mode->hdisplay +
aa0261f2
ZY		 356 right_border;
357 /* keep the blank width constant */
358 adjusted_mode->crtc_hblank_end =
359 adjusted_mode->crtc_hblank_start + hblank_width;
360 /* get the hsync pos relative to hblank start */
361 hsync_pos = (hblank_width - hsync_width) / 2;
362 /* keep the hsync pos be even */
363 if (hsync_pos & 1)
364 hsync_pos++;
3fbe18d6 365 adjusted_mode->crtc_hsync_start =
aa0261f2
ZY		 366 adjusted_mode->crtc_hblank_start + hsync_pos;
367 /* keep the hsync width constant */
3fbe18d6 368 adjusted_mode->crtc_hsync_end =
aa0261f2 369 adjusted_mode->crtc_hsync_start + hsync_width;
3fbe18d6 370 adjusted_mode->crtc_vdisplay = mode->vdisplay;
aa0261f2 371 /* use the border instead of border minus one */
3fbe18d6 372 adjusted_mode->crtc_vblank_start = mode->vdisplay +
aa0261f2
ZY		 373 bottom_border;
374 /* keep the vblank width constant */
375 adjusted_mode->crtc_vblank_end =
376 adjusted_mode->crtc_vblank_start + vblank_width;
377 /* get the vsync start postion relative to vblank start */
378 vsync_pos = (vblank_width - vsync_width) / 2;
3fbe18d6 379 adjusted_mode->crtc_vsync_start =
aa0261f2
ZY		 380 adjusted_mode->crtc_vblank_start + vsync_pos;
381 /* keep the vsync width constant */
3fbe18d6 382 adjusted_mode->crtc_vsync_end =
a3e17eb8 383 adjusted_mode->crtc_vsync_start + vsync_width;
3fbe18d6
ZY		 384 border = 1;
385 break;
386 case DRM_MODE_SCALE_ASPECT:
387 /* Scale but preserve the spect ratio */
388 pfit_control |= PFIT_ENABLE;
389 if (IS_I965G(dev)) {
390 /* 965+ is easy, it does everything in hw */
391 if (panel_ratio > desired_ratio)
392 pfit_control |= PFIT_SCALING_PILLAR;
393 else if (panel_ratio < desired_ratio)
394 pfit_control |= PFIT_SCALING_LETTER;
395 else
396 pfit_control |= PFIT_SCALING_AUTO;
397 } else {
398 /*
399 * For earlier chips we have to calculate the scaling
400 * ratio by hand and program it into the
401 * PFIT_PGM_RATIO register
402 */
403 u32 horiz_bits, vert_bits, bits = 12;
404 horiz_ratio = mode->hdisplay * PANEL_RATIO_FACTOR/
405 adjusted_mode->hdisplay;
406 vert_ratio = mode->vdisplay * PANEL_RATIO_FACTOR/
407 adjusted_mode->vdisplay;
408 horiz_scale = adjusted_mode->hdisplay *
409 PANEL_RATIO_FACTOR / mode->hdisplay;
410 vert_scale = adjusted_mode->vdisplay *
411 PANEL_RATIO_FACTOR / mode->vdisplay;
412
413 /* retain aspect ratio */
414 if (panel_ratio > desired_ratio) { /* Pillar */
415 u32 scaled_width;
416 scaled_width = mode->hdisplay * vert_scale /
417 PANEL_RATIO_FACTOR;
418 horiz_ratio = vert_ratio;
419 pfit_control |= (VERT_AUTO_SCALE |
420 VERT_INTERP_BILINEAR |
421 HORIZ_INTERP_BILINEAR);
422 /* Pillar will have left/right borders */
423 left_border = (adjusted_mode->hdisplay -
424 scaled_width) / 2;
425 right_border = left_border;
426 if (mode->hdisplay & 1) /* odd resolutions */
427 right_border++;
aa0261f2
ZY		 428 /* keep the border be even */
429 if (right_border & 1)
430 right_border++;
3fbe18d6 431 adjusted_mode->crtc_hdisplay = scaled_width;
aa0261f2 432 /* use border instead of border minus one */
3fbe18d6 433 adjusted_mode->crtc_hblank_start =
aa0261f2
ZY		 434 scaled_width + right_border;
435 /* keep the hblank width constant */
3fbe18d6 436 adjusted_mode->crtc_hblank_end =
aa0261f2
ZY		 437 adjusted_mode->crtc_hblank_start +
438 hblank_width;
439 /*
440 * get the hsync start pos relative to
441 * hblank start
442 */
443 hsync_pos = (hblank_width - hsync_width) / 2;
444 /* keep the hsync_pos be even */
445 if (hsync_pos & 1)
446 hsync_pos++;
3fbe18d6 447 adjusted_mode->crtc_hsync_start =
aa0261f2
ZY		 448 adjusted_mode->crtc_hblank_start +
449 hsync_pos;
450 /* keept hsync width constant */
3fbe18d6 451 adjusted_mode->crtc_hsync_end =
aa0261f2
ZY		 452 adjusted_mode->crtc_hsync_start +
453 hsync_width;
3fbe18d6
ZY		 454 border = 1;
455 } else if (panel_ratio < desired_ratio) { /* letter */
456 u32 scaled_height = mode->vdisplay *
457 horiz_scale / PANEL_RATIO_FACTOR;
458 vert_ratio = horiz_ratio;
459 pfit_control |= (HORIZ_AUTO_SCALE |
460 VERT_INTERP_BILINEAR |
461 HORIZ_INTERP_BILINEAR);
462 /* Letterbox will have top/bottom border */
463 top_border = (adjusted_mode->vdisplay -
464 scaled_height) / 2;
465 bottom_border = top_border;
466 if (mode->vdisplay & 1)
467 bottom_border++;
468 adjusted_mode->crtc_vdisplay = scaled_height;
aa0261f2 469 /* use border instead of border minus one */
3fbe18d6 470 adjusted_mode->crtc_vblank_start =
aa0261f2
ZY		 471 scaled_height + bottom_border;
472 /* keep the vblank width constant */
3fbe18d6 473 adjusted_mode->crtc_vblank_end =
aa0261f2
ZY		 474 adjusted_mode->crtc_vblank_start +
475 vblank_width;
476 /*
477 * get the vsync start pos relative to
478 * vblank start
479 */
480 vsync_pos = (vblank_width - vsync_width) / 2;
3fbe18d6 481 adjusted_mode->crtc_vsync_start =
aa0261f2
ZY		 482 adjusted_mode->crtc_vblank_start +
483 vsync_pos;
484 /* keep the vsync width constant */
3fbe18d6 485 adjusted_mode->crtc_vsync_end =
aa0261f2
ZY		 486 adjusted_mode->crtc_vsync_start +
487 vsync_width;
3fbe18d6
ZY		 488 border = 1;
489 } else {
490 /* Aspects match, Let hw scale both directions */
491 pfit_control |= (VERT_AUTO_SCALE |
492 HORIZ_AUTO_SCALE |
493 VERT_INTERP_BILINEAR |
494 HORIZ_INTERP_BILINEAR);
495 }
496 horiz_bits = (1 << bits) * horiz_ratio /
497 PANEL_RATIO_FACTOR;
498 vert_bits = (1 << bits) * vert_ratio /
499 PANEL_RATIO_FACTOR;
500 pfit_pgm_ratios =
501 ((vert_bits << PFIT_VERT_SCALE_SHIFT) &
502 PFIT_VERT_SCALE_MASK) |
503 ((horiz_bits << PFIT_HORIZ_SCALE_SHIFT) &
504 PFIT_HORIZ_SCALE_MASK);
505 }
506 break;
507
508 case DRM_MODE_SCALE_FULLSCREEN:
509 /*
510 * Full scaling, even if it changes the aspect ratio.
511 * Fortunately this is all done for us in hw.
512 */
513 pfit_control |= PFIT_ENABLE;
514 if (IS_I965G(dev))
515 pfit_control |= PFIT_SCALING_AUTO;
516 else
517 pfit_control |= (VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
518 VERT_INTERP_BILINEAR |
519 HORIZ_INTERP_BILINEAR);
520 break;
521 default:
522 break;
523 }
524
525out:
526 lvds_priv->pfit_control = pfit_control;
527 lvds_priv->pfit_pgm_ratios = pfit_pgm_ratios;
a3e17eb8
ZY		 528 /*
529 * When there exists the border, it means that the LVDS_BORDR
530 * should be enabled.
531 */
532 if (border)
533 dev_priv->lvds_border_bits |= LVDS_BORDER_ENABLE;
534 else
535 dev_priv->lvds_border_bits &= ~(LVDS_BORDER_ENABLE);
79e53945
JB		 536 /*
537 * XXX: It would be nice to support lower refresh rates on the
538 * panels to reduce power consumption, and perhaps match the
539 * user's requested refresh rate.
540 */
541
542 return true;
543}
544
545static void intel_lvds_prepare(struct drm_encoder *encoder)
546{
547 struct drm_device *dev = encoder->dev;
548 struct drm_i915_private *dev_priv = dev->dev_private;
541998a1 549 u32 reg;
79e53945 550
f2b115e6 551 if (IS_IRONLAKE(dev))
541998a1
ZW		 552 reg = BLC_PWM_CPU_CTL;
553 else
554 reg = BLC_PWM_CTL;
79e53945 555
541998a1 556 dev_priv->saveBLC_PWM_CTL = I915_READ(reg);
79e53945
JB		 557 dev_priv->backlight_duty_cycle = (dev_priv->saveBLC_PWM_CTL &
558 BACKLIGHT_DUTY_CYCLE_MASK);
559
560 intel_lvds_set_power(dev, false);
561}
562
563static void intel_lvds_commit( struct drm_encoder *encoder)
564{
565 struct drm_device *dev = encoder->dev;
566 struct drm_i915_private *dev_priv = dev->dev_private;
567
568 if (dev_priv->backlight_duty_cycle == 0)
569 dev_priv->backlight_duty_cycle =
570 intel_lvds_get_max_backlight(dev);
571
572 intel_lvds_set_power(dev, true);
573}
574
575static void intel_lvds_mode_set(struct drm_encoder *encoder,
576 struct drm_display_mode *mode,
577 struct drm_display_mode *adjusted_mode)
578{
579 struct drm_device *dev = encoder->dev;
580 struct drm_i915_private *dev_priv = dev->dev_private;
3fbe18d6
ZY		 581 struct intel_output *intel_output = enc_to_intel_output(encoder);
582 struct intel_lvds_priv *lvds_priv = intel_output->dev_priv;
79e53945
JB		 583
584 /*
585 * The LVDS pin pair will already have been turned on in the
586 * intel_crtc_mode_set since it has a large impact on the DPLL
587 * settings.
588 */
589
f2b115e6 590 if (IS_IRONLAKE(dev))
541998a1
ZW		 591 return;
592
79e53945
JB		 593 /*
594 * Enable automatic panel scaling so that non-native modes fill the
595 * screen. Should be enabled before the pipe is enabled, according to
596 * register description and PRM.
597 */
3fbe18d6
ZY		 598 I915_WRITE(PFIT_PGM_RATIOS, lvds_priv->pfit_pgm_ratios);
599 I915_WRITE(PFIT_CONTROL, lvds_priv->pfit_control);
79e53945
JB		 600}
601
7121413f
JB		 602/* Some lid devices report incorrect lid status, assume they're connected */
603static const struct dmi_system_id bad_lid_status[] = {
40f33a92
ZY		 604 {
605 .ident = "Compaq nx9020",
606 .matches = {
607 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
608 DMI_MATCH(DMI_BOARD_NAME, "3084"),
609 },
610 },
611 {
612 .ident = "Samsung SX20S",
613 .matches = {
614 DMI_MATCH(DMI_SYS_VENDOR, "Phoenix Technologies LTD"),
615 DMI_MATCH(DMI_BOARD_NAME, "SX20S"),
616 },
617 },
7121413f
JB		 618 {
619 .ident = "Aspire One",
620 .matches = {
621 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
622 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire one"),
623 },
624 },
a3cb5195
ZY		 625 {
626 .ident = "PC-81005",
627 .matches = {
628 DMI_MATCH(DMI_SYS_VENDOR, "MALATA"),
629 DMI_MATCH(DMI_PRODUCT_NAME, "PC-81005"),
630 },
631 },
7121413f
JB		 632 { }
633};
634
79e53945
JB		 635/**
636 * Detect the LVDS connection.
637 *
b42d4c5c
JB		 638 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means
639 * connected and closed means disconnected. We also send hotplug events as
640 * needed, using lid status notification from the input layer.
79e53945
JB		 641 */
642static enum drm_connector_status intel_lvds_detect(struct drm_connector *connector)
643{
b42d4c5c
JB		 644 enum drm_connector_status status = connector_status_connected;
645
7121413f 646 if (!acpi_lid_open() && !dmi_check_system(bad_lid_status))
b42d4c5c
JB		 647 status = connector_status_disconnected;
648
649 return status;
79e53945
JB		 650}
651
652/**
653 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
654 */
655static int intel_lvds_get_modes(struct drm_connector *connector)
656{
657 struct drm_device *dev = connector->dev;
658 struct intel_output *intel_output = to_intel_output(connector);
659 struct drm_i915_private *dev_priv = dev->dev_private;
660 int ret = 0;
661
662 ret = intel_ddc_get_modes(intel_output);
663
664 if (ret)
665 return ret;
666
667 /* Didn't get an EDID, so
668 * Set wide sync ranges so we get all modes
669 * handed to valid_mode for checking
670 */
671 connector->display_info.min_vfreq = 0;
672 connector->display_info.max_vfreq = 200;
673 connector->display_info.min_hfreq = 0;
674 connector->display_info.max_hfreq = 200;
675
676 if (dev_priv->panel_fixed_mode != NULL) {
677 struct drm_display_mode *mode;
678
79e53945
JB		 679 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
680 drm_mode_probed_add(connector, mode);
79e53945
JB		 681
682 return 1;
683 }
684
685 return 0;
686}
687
c9354c85
LT		 688/*
689 * Lid events. Note the use of 'modeset_on_lid':
690 * - we set it on lid close, and reset it on open
691 * - we use it as a "only once" bit (ie we ignore
692 * duplicate events where it was already properly
693 * set/reset)
694 * - the suspend/resume paths will also set it to
695 * zero, since they restore the mode ("lid open").
696 */
c1c7af60
JB		 697static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
698 void *unused)
699{
700 struct drm_i915_private *dev_priv =
701 container_of(nb, struct drm_i915_private, lid_notifier);
702 struct drm_device *dev = dev_priv->dev;
a2565377 703 struct drm_connector *connector = dev_priv->int_lvds_connector;
c1c7af60 704
a2565377
ZY		 705 /*
706 * check and update the status of LVDS connector after receiving
707 * the LID nofication event.
708 */
709 if (connector)
710 connector->status = connector->funcs->detect(connector);
c9354c85
LT		 711 if (!acpi_lid_open()) {
712 dev_priv->modeset_on_lid = 1;
713 return NOTIFY_OK;
06891e27 714 }
c1c7af60 715
c9354c85
LT		 716 if (!dev_priv->modeset_on_lid)
717 return NOTIFY_OK;
718
719 dev_priv->modeset_on_lid = 0;
720
721 mutex_lock(&dev->mode_config.mutex);
722 drm_helper_resume_force_mode(dev);
723 mutex_unlock(&dev->mode_config.mutex);
06324194 724
c1c7af60
JB		 725 return NOTIFY_OK;
726}
727
79e53945
JB		 728/**
729 * intel_lvds_destroy - unregister and free LVDS structures
730 * @connector: connector to free
731 *
732 * Unregister the DDC bus for this connector then free the driver private
733 * structure.
734 */
735static void intel_lvds_destroy(struct drm_connector *connector)
736{
c1c7af60 737 struct drm_device *dev = connector->dev;
79e53945 738 struct intel_output *intel_output = to_intel_output(connector);
c1c7af60 739 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 740
741 if (intel_output->ddc_bus)
742 intel_i2c_destroy(intel_output->ddc_bus);
c1c7af60
JB		 743 if (dev_priv->lid_notifier.notifier_call)
744 acpi_lid_notifier_unregister(&dev_priv->lid_notifier);
79e53945
JB		 745 drm_sysfs_connector_remove(connector);
746 drm_connector_cleanup(connector);
747 kfree(connector);
748}
749
335041ed
JB		 750static int intel_lvds_set_property(struct drm_connector *connector,
751 struct drm_property *property,
752 uint64_t value)
753{
3fbe18d6
ZY		 754 struct drm_device *dev = connector->dev;
755 struct intel_output *intel_output =
756 to_intel_output(connector);
757
758 if (property == dev->mode_config.scaling_mode_property &&
759 connector->encoder) {
760 struct drm_crtc *crtc = connector->encoder->crtc;
761 struct intel_lvds_priv *lvds_priv = intel_output->dev_priv;
53bd8389
JB		 762 if (value == DRM_MODE_SCALE_NONE) {
763 DRM_DEBUG_KMS("no scaling not supported\n");
3fbe18d6
ZY		 764 return 0;
765 }
766 if (lvds_priv->fitting_mode == value) {
767 /* the LVDS scaling property is not changed */
768 return 0;
769 }
770 lvds_priv->fitting_mode = value;
771 if (crtc && crtc->enabled) {
772 /*
773 * If the CRTC is enabled, the display will be changed
774 * according to the new panel fitting mode.
775 */
776 drm_crtc_helper_set_mode(crtc, &crtc->mode,
777 crtc->x, crtc->y, crtc->fb);
778 }
779 }
780
335041ed
JB		 781 return 0;
782}
783
79e53945
JB		 784static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = {
785 .dpms = intel_lvds_dpms,
786 .mode_fixup = intel_lvds_mode_fixup,
787 .prepare = intel_lvds_prepare,
788 .mode_set = intel_lvds_mode_set,
789 .commit = intel_lvds_commit,
790};
791
792static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
793 .get_modes = intel_lvds_get_modes,
794 .mode_valid = intel_lvds_mode_valid,
795 .best_encoder = intel_best_encoder,
796};
797
798static const struct drm_connector_funcs intel_lvds_connector_funcs = {
c9fb15f6 799 .dpms = drm_helper_connector_dpms,
79e53945
JB		 800 .save = intel_lvds_save,
801 .restore = intel_lvds_restore,
802 .detect = intel_lvds_detect,
803 .fill_modes = drm_helper_probe_single_connector_modes,
335041ed 804 .set_property = intel_lvds_set_property,
79e53945
JB		 805 .destroy = intel_lvds_destroy,
806};
807
808
809static void intel_lvds_enc_destroy(struct drm_encoder *encoder)
810{
811 drm_encoder_cleanup(encoder);
812}
813
814static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
815 .destroy = intel_lvds_enc_destroy,
816};
817
425d244c
JW		 818static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
819{
8a4c47f3 820 DRM_DEBUG_KMS("Skipping LVDS initialization for %s\n", id->ident);
425d244c
JW		 821 return 1;
822}
79e53945 823
425d244c 824/* These systems claim to have LVDS, but really don't */
93c05f22 825static const struct dmi_system_id intel_no_lvds[] = {
425d244c
JW		 826 {
827 .callback = intel_no_lvds_dmi_callback,
828 .ident = "Apple Mac Mini (Core series)",
829 .matches = {
98acd46f 830 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW		 831 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
832 },
833 },
834 {
835 .callback = intel_no_lvds_dmi_callback,
836 .ident = "Apple Mac Mini (Core 2 series)",
837 .matches = {
98acd46f 838 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW		 839 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
840 },
841 },
842 {
843 .callback = intel_no_lvds_dmi_callback,
844 .ident = "MSI IM-945GSE-A",
845 .matches = {
846 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
847 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
848 },
849 },
850 {
851 .callback = intel_no_lvds_dmi_callback,
852 .ident = "Dell Studio Hybrid",
853 .matches = {
854 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
855 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
856 },
857 },
70aa96ca
JW		 858 {
859 .callback = intel_no_lvds_dmi_callback,
860 .ident = "AOpen Mini PC",
861 .matches = {
862 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
863 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
864 },
865 },
ed8c754b
TV		 866 {
867 .callback = intel_no_lvds_dmi_callback,
868 .ident = "AOpen Mini PC MP915",
869 .matches = {
870 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
871 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
872 },
873 },
fa0864b2
MC		 874 {
875 .callback = intel_no_lvds_dmi_callback,
876 .ident = "Aopen i945GTt-VFA",
877 .matches = {
878 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
879 },
880 },
425d244c
JW		 881
882 { } /* terminating entry */
883};
79e53945 884
18f9ed12
ZY		 885/**
886 * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID
887 * @dev: drm device
888 * @connector: LVDS connector
889 *
890 * Find the reduced downclock for LVDS in EDID.
891 */
892static void intel_find_lvds_downclock(struct drm_device *dev,
893 struct drm_connector *connector)
894{
895 struct drm_i915_private *dev_priv = dev->dev_private;
896 struct drm_display_mode *scan, *panel_fixed_mode;
897 int temp_downclock;
898
899 panel_fixed_mode = dev_priv->panel_fixed_mode;
900 temp_downclock = panel_fixed_mode->clock;
901
902 mutex_lock(&dev->mode_config.mutex);
903 list_for_each_entry(scan, &connector->probed_modes, head) {
904 /*
905 * If one mode has the same resolution with the fixed_panel
906 * mode while they have the different refresh rate, it means
907 * that the reduced downclock is found for the LVDS. In such
908 * case we can set the different FPx0/1 to dynamically select
909 * between low and high frequency.
910 */
911 if (scan->hdisplay == panel_fixed_mode->hdisplay &&
912 scan->hsync_start == panel_fixed_mode->hsync_start &&
913 scan->hsync_end == panel_fixed_mode->hsync_end &&
914 scan->htotal == panel_fixed_mode->htotal &&
915 scan->vdisplay == panel_fixed_mode->vdisplay &&
916 scan->vsync_start == panel_fixed_mode->vsync_start &&
917 scan->vsync_end == panel_fixed_mode->vsync_end &&
918 scan->vtotal == panel_fixed_mode->vtotal) {
919 if (scan->clock < temp_downclock) {
920 /*
921 * The downclock is already found. But we
922 * expect to find the lower downclock.
923 */
924 temp_downclock = scan->clock;
925 }
926 }
927 }
928 mutex_unlock(&dev->mode_config.mutex);
33814341
JB		 929 if (temp_downclock < panel_fixed_mode->clock &&
930 i915_lvds_downclock) {
18f9ed12
ZY		 931 /* We found the downclock for LVDS. */
932 dev_priv->lvds_downclock_avail = 1;
933 dev_priv->lvds_downclock = temp_downclock;
934 DRM_DEBUG_KMS("LVDS downclock is found in EDID. "
935 "Normal clock %dKhz, downclock %dKhz\n",
936 panel_fixed_mode->clock, temp_downclock);
937 }
938 return;
939}
940
7cf4f69d
ZY		 941/*
942 * Enumerate the child dev array parsed from VBT to check whether
943 * the LVDS is present.
944 * If it is present, return 1.
945 * If it is not present, return false.
946 * If no child dev is parsed from VBT, it assumes that the LVDS is present.
947 * Note: The addin_offset should also be checked for LVDS panel.
948 * Only when it is non-zero, it is assumed that it is present.
949 */
6e36595a 950static int lvds_is_present_in_vbt(struct drm_device *dev)
7cf4f69d
ZY		 951{
952 struct drm_i915_private *dev_priv = dev->dev_private;
953 struct child_device_config *p_child;
954 int i, ret;
955
956 if (!dev_priv->child_dev_num)
957 return 1;
958
959 ret = 0;
960 for (i = 0; i < dev_priv->child_dev_num; i++) {
961 p_child = dev_priv->child_dev + i;
962 /*
963 * If the device type is not LFP, continue.
964 * If the device type is 0x22, it is also regarded as LFP.
965 */
966 if (p_child->device_type != DEVICE_TYPE_INT_LFP &&
967 p_child->device_type != DEVICE_TYPE_LFP)
968 continue;
969
970 /* The addin_offset should be checked. Only when it is
971 * non-zero, it is regarded as present.
972 */
973 if (p_child->addin_offset) {
974 ret = 1;
975 break;
976 }
977 }
978 return ret;
979}
980
79e53945
JB		 981/**
982 * intel_lvds_init - setup LVDS connectors on this device
983 * @dev: drm device
984 *
985 * Create the connector, register the LVDS DDC bus, and try to figure out what
986 * modes we can display on the LVDS panel (if present).
987 */
988void intel_lvds_init(struct drm_device *dev)
989{
990 struct drm_i915_private *dev_priv = dev->dev_private;
991 struct intel_output *intel_output;
992 struct drm_connector *connector;
993 struct drm_encoder *encoder;
994 struct drm_display_mode *scan; /* *modes, *bios_mode; */
995 struct drm_crtc *crtc;
3fbe18d6 996 struct intel_lvds_priv *lvds_priv;
79e53945 997 u32 lvds;
541998a1 998 int pipe, gpio = GPIOC;
79e53945 999
425d244c
JW		 1000 /* Skip init on machines we know falsely report LVDS */
1001 if (dmi_check_system(intel_no_lvds))
565dcd46 1002 return;
565dcd46 1003
11ba1592
MG		 1004 if (!lvds_is_present_in_vbt(dev)) {
1005 DRM_DEBUG_KMS("LVDS is not present in VBT\n");
e99da35f 1006 return;
38b3037e 1007 }
e99da35f 1008
f2b115e6 1009 if (IS_IRONLAKE(dev)) {
541998a1
ZW		 1010 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
1011 return;
32f9d658 1012 if (dev_priv->edp_support) {
28c97730 1013 DRM_DEBUG_KMS("disable LVDS for eDP support\n");
32f9d658
ZW		 1014 return;
1015 }
541998a1
ZW		 1016 gpio = PCH_GPIOC;
1017 }
1018
3fbe18d6
ZY		 1019 intel_output = kzalloc(sizeof(struct intel_output) +
1020 sizeof(struct intel_lvds_priv), GFP_KERNEL);
79e53945
JB		 1021 if (!intel_output) {
1022 return;
1023 }
1024
1025 connector = &intel_output->base;
1026 encoder = &intel_output->enc;
1027 drm_connector_init(dev, &intel_output->base, &intel_lvds_connector_funcs,
1028 DRM_MODE_CONNECTOR_LVDS);
1029
1030 drm_encoder_init(dev, &intel_output->enc, &intel_lvds_enc_funcs,
1031 DRM_MODE_ENCODER_LVDS);
1032
1033 drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc);
1034 intel_output->type = INTEL_OUTPUT_LVDS;
1035
f8aed700
ML		 1036 intel_output->clone_mask = (1 << INTEL_LVDS_CLONE_BIT);
1037 intel_output->crtc_mask = (1 << 1);
79e53945
JB		 1038 drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs);
1039 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
1040 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1041 connector->interlace_allowed = false;
1042 connector->doublescan_allowed = false;
1043
3fbe18d6
ZY		 1044 lvds_priv = (struct intel_lvds_priv *)(intel_output + 1);
1045 intel_output->dev_priv = lvds_priv;
1046 /* create the scaling mode property */
1047 drm_mode_create_scaling_mode_property(dev);
1048 /*
1049 * the initial panel fitting mode will be FULL_SCREEN.
1050 */
79e53945 1051
3fbe18d6
ZY		 1052 drm_connector_attach_property(&intel_output->base,
1053 dev->mode_config.scaling_mode_property,
1054 DRM_MODE_SCALE_FULLSCREEN);
1055 lvds_priv->fitting_mode = DRM_MODE_SCALE_FULLSCREEN;
79e53945
JB		 1056 /*
1057 * LVDS discovery:
1058 * 1) check for EDID on DDC
1059 * 2) check for VBT data
1060 * 3) check to see if LVDS is already on
1061 * if none of the above, no panel
1062 * 4) make sure lid is open
1063 * if closed, act like it's not there for now
1064 */
1065
1066 /* Set up the DDC bus. */
541998a1 1067 intel_output->ddc_bus = intel_i2c_create(dev, gpio, "LVDSDDC_C");
79e53945
JB		 1068 if (!intel_output->ddc_bus) {
1069 dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration "
1070 "failed.\n");
1071 goto failed;
1072 }
1073
1074 /*
1075 * Attempt to get the fixed panel mode from DDC. Assume that the
1076 * preferred mode is the right one.
1077 */
1078 intel_ddc_get_modes(intel_output);
1079
1080 list_for_each_entry(scan, &connector->probed_modes, head) {
1081 mutex_lock(&dev->mode_config.mutex);
1082 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
1083 dev_priv->panel_fixed_mode =
1084 drm_mode_duplicate(dev, scan);
1085 mutex_unlock(&dev->mode_config.mutex);
18f9ed12 1086 intel_find_lvds_downclock(dev, connector);
565dcd46 1087 goto out;
79e53945
JB		 1088 }
1089 mutex_unlock(&dev->mode_config.mutex);
1090 }
1091
1092 /* Failed to get EDID, what about VBT? */
88631706 1093 if (dev_priv->lfp_lvds_vbt_mode) {
79e53945
JB		 1094 mutex_lock(&dev->mode_config.mutex);
1095 dev_priv->panel_fixed_mode =
88631706 1096 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
79e53945 1097 mutex_unlock(&dev->mode_config.mutex);
e285f3cd
JB		 1098 if (dev_priv->panel_fixed_mode) {
1099 dev_priv->panel_fixed_mode->type |=
1100 DRM_MODE_TYPE_PREFERRED;
e285f3cd
JB		 1101 goto out;
1102 }
79e53945
JB		 1103 }
1104
1105 /*
1106 * If we didn't get EDID, try checking if the panel is already turned
1107 * on. If so, assume that whatever is currently programmed is the
1108 * correct mode.
1109 */
541998a1 1110
f2b115e6
AJ		 1111 /* Ironlake: FIXME if still fail, not try pipe mode now */
1112 if (IS_IRONLAKE(dev))
541998a1
ZW		 1113 goto failed;
1114
79e53945
JB		 1115 lvds = I915_READ(LVDS);
1116 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
1117 crtc = intel_get_crtc_from_pipe(dev, pipe);
1118
1119 if (crtc && (lvds & LVDS_PORT_EN)) {
1120 dev_priv->panel_fixed_mode = intel_crtc_mode_get(dev, crtc);
1121 if (dev_priv->panel_fixed_mode) {
1122 dev_priv->panel_fixed_mode->type |=
1123 DRM_MODE_TYPE_PREFERRED;
565dcd46 1124 goto out;
79e53945
JB		 1125 }
1126 }
1127
1128 /* If we still don't have a mode after all that, give up. */
1129 if (!dev_priv->panel_fixed_mode)
1130 goto failed;
1131
79e53945 1132out:
f2b115e6 1133 if (IS_IRONLAKE(dev)) {
541998a1
ZW		 1134 u32 pwm;
1135 /* make sure PWM is enabled */
1136 pwm = I915_READ(BLC_PWM_CPU_CTL2);
1137 pwm |= (PWM_ENABLE | PWM_PIPE_B);
1138 I915_WRITE(BLC_PWM_CPU_CTL2, pwm);
1139
1140 pwm = I915_READ(BLC_PWM_PCH_CTL1);
1141 pwm |= PWM_PCH_ENABLE;
1142 I915_WRITE(BLC_PWM_PCH_CTL1, pwm);
1143 }
c1c7af60
JB		 1144 dev_priv->lid_notifier.notifier_call = intel_lid_notify;
1145 if (acpi_lid_notifier_register(&dev_priv->lid_notifier)) {
28c97730 1146 DRM_DEBUG_KMS("lid notifier registration failed\n");
c1c7af60
JB		 1147 dev_priv->lid_notifier.notifier_call = NULL;
1148 }
a2565377
ZY		 1149 /* keep the LVDS connector */
1150 dev_priv->int_lvds_connector = connector;
79e53945
JB		 1151 drm_sysfs_connector_add(connector);
1152 return;
1153
1154failed:
8a4c47f3 1155 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
79e53945
JB		 1156 if (intel_output->ddc_bus)
1157 intel_i2c_destroy(intel_output->ddc_bus);
1158 drm_connector_cleanup(connector);
1991bdfa 1159 drm_encoder_cleanup(encoder);
3fbe18d6 1160 kfree(intel_output);
79e53945 1161}
Linux 6.x block layer and io_uring tree(s)