drm/i915: Fix RC6VIDS encode/decode
[linux-block.git] / drivers / gpu / drm / i915 / intel_lvds.c
CommitLineData
79e53945
JB
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 */
29
c1c7af60 30#include <acpi/button.h>
565dcd46 31#include <linux/dmi.h>
79e53945 32#include <linux/i2c.h>
5a0e3ad6 33#include <linux/slab.h>
760285e7
DH
34#include <drm/drmP.h>
35#include <drm/drm_crtc.h>
36#include <drm/drm_edid.h>
79e53945 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
79e53945 39#include "i915_drv.h"
e99da35f 40#include <linux/acpi.h>
79e53945 41
3fbe18d6 42/* Private structure for the integrated LVDS support */
c7362c4d
JN
43struct intel_lvds_connector {
44 struct intel_connector base;
788319d4 45
db1740a0 46 struct notifier_block lid_notifier;
c7362c4d
JN
47};
48
29b99b48 49struct intel_lvds_encoder {
ea5b213a 50 struct intel_encoder base;
788319d4 51
3fbe18d6
ZY
52 u32 pfit_control;
53 u32 pfit_pgm_ratios;
e9e331a8 54 bool pfit_dirty;
13c7d870 55 bool is_dual_link;
7dec0606 56 u32 reg;
788319d4 57
62165e0d 58 struct intel_lvds_connector *attached_connector;
3fbe18d6
ZY
59};
60
29b99b48 61static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
ea5b213a 62{
29b99b48 63 return container_of(encoder, struct intel_lvds_encoder, base.base);
ea5b213a
CW
64}
65
c7362c4d 66static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector)
788319d4 67{
c7362c4d 68 return container_of(connector, struct intel_lvds_connector, base.base);
788319d4
CW
69}
70
b1dc332c
DV
71static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
72 enum pipe *pipe)
73{
74 struct drm_device *dev = encoder->base.dev;
75 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606
DV
76 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
77 u32 tmp;
b1dc332c 78
7dec0606 79 tmp = I915_READ(lvds_encoder->reg);
b1dc332c
DV
80
81 if (!(tmp & LVDS_PORT_EN))
82 return false;
83
84 if (HAS_PCH_CPT(dev))
85 *pipe = PORT_TO_PIPE_CPT(tmp);
86 else
87 *pipe = PORT_TO_PIPE(tmp);
88
89 return true;
90}
91
fc683091
DV
92/* The LVDS pin pair needs to be on before the DPLLs are enabled.
93 * This is an exception to the general rule that mode_set doesn't turn
94 * things on.
95 */
96static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder)
97{
98 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
99 struct drm_device *dev = encoder->base.dev;
100 struct drm_i915_private *dev_priv = dev->dev_private;
101 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
102 struct drm_display_mode *fixed_mode =
103 lvds_encoder->attached_connector->base.panel.fixed_mode;
104 int pipe = intel_crtc->pipe;
105 u32 temp;
106
fc683091
DV
107 temp = I915_READ(lvds_encoder->reg);
108 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
62810e5a
DV
109
110 if (HAS_PCH_CPT(dev)) {
111 temp &= ~PORT_TRANS_SEL_MASK;
112 temp |= PORT_TRANS_SEL_CPT(pipe);
fc683091 113 } else {
62810e5a
DV
114 if (pipe == 1) {
115 temp |= LVDS_PIPEB_SELECT;
116 } else {
117 temp &= ~LVDS_PIPEB_SELECT;
118 }
fc683091 119 }
62810e5a 120
fc683091
DV
121 /* set the corresponsding LVDS_BORDER bit */
122 temp |= dev_priv->lvds_border_bits;
123 /* Set the B0-B3 data pairs corresponding to whether we're going to
124 * set the DPLLs for dual-channel mode or not.
125 */
126 if (lvds_encoder->is_dual_link)
127 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
128 else
129 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
130
131 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
132 * appropriately here, but we need to look more thoroughly into how
133 * panels behave in the two modes.
134 */
62810e5a
DV
135
136 /* Set the dithering flag on LVDS as needed, note that there is no
137 * special lvds dither control bit on pch-split platforms, dithering is
138 * only controlled through the PIPECONF reg. */
139 if (INTEL_INFO(dev)->gen == 4) {
fc683091
DV
140 if (dev_priv->lvds_dither)
141 temp |= LVDS_ENABLE_DITHER;
142 else
143 temp &= ~LVDS_ENABLE_DITHER;
144 }
145 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
146 if (fixed_mode->flags & DRM_MODE_FLAG_NHSYNC)
147 temp |= LVDS_HSYNC_POLARITY;
148 if (fixed_mode->flags & DRM_MODE_FLAG_NVSYNC)
149 temp |= LVDS_VSYNC_POLARITY;
150
151 I915_WRITE(lvds_encoder->reg, temp);
152}
153
79e53945
JB
154/**
155 * Sets the power state for the panel.
156 */
c22834ec 157static void intel_enable_lvds(struct intel_encoder *encoder)
79e53945 158{
c22834ec 159 struct drm_device *dev = encoder->base.dev;
29b99b48 160 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
c22834ec 161 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 162 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606 163 u32 ctl_reg, stat_reg;
541998a1 164
c619eed4 165 if (HAS_PCH_SPLIT(dev)) {
541998a1 166 ctl_reg = PCH_PP_CONTROL;
de842eff 167 stat_reg = PCH_PP_STATUS;
541998a1
ZW
168 } else {
169 ctl_reg = PP_CONTROL;
de842eff 170 stat_reg = PP_STATUS;
541998a1 171 }
79e53945 172
7dec0606 173 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
e9e331a8 174
29b99b48 175 if (lvds_encoder->pfit_dirty) {
2a1292fd
CW
176 /*
177 * Enable automatic panel scaling so that non-native modes
178 * fill the screen. The panel fitter should only be
179 * adjusted whilst the pipe is disabled, according to
180 * register description and PRM.
181 */
182 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
29b99b48
JN
183 lvds_encoder->pfit_control,
184 lvds_encoder->pfit_pgm_ratios);
de842eff 185
29b99b48
JN
186 I915_WRITE(PFIT_PGM_RATIOS, lvds_encoder->pfit_pgm_ratios);
187 I915_WRITE(PFIT_CONTROL, lvds_encoder->pfit_control);
188 lvds_encoder->pfit_dirty = false;
2a1292fd
CW
189 }
190
191 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
7dec0606 192 POSTING_READ(lvds_encoder->reg);
de842eff
KP
193 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
194 DRM_ERROR("timed out waiting for panel to power on\n");
2a1292fd 195
24ded204 196 intel_panel_enable_backlight(dev, intel_crtc->pipe);
2a1292fd
CW
197}
198
c22834ec 199static void intel_disable_lvds(struct intel_encoder *encoder)
2a1292fd 200{
c22834ec 201 struct drm_device *dev = encoder->base.dev;
29b99b48 202 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
2a1292fd 203 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606 204 u32 ctl_reg, stat_reg;
2a1292fd
CW
205
206 if (HAS_PCH_SPLIT(dev)) {
207 ctl_reg = PCH_PP_CONTROL;
de842eff 208 stat_reg = PCH_PP_STATUS;
2a1292fd
CW
209 } else {
210 ctl_reg = PP_CONTROL;
de842eff 211 stat_reg = PP_STATUS;
2a1292fd
CW
212 }
213
47356eb6 214 intel_panel_disable_backlight(dev);
2a1292fd
CW
215
216 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
de842eff
KP
217 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
218 DRM_ERROR("timed out waiting for panel to power off\n");
2a1292fd 219
29b99b48 220 if (lvds_encoder->pfit_control) {
2a1292fd 221 I915_WRITE(PFIT_CONTROL, 0);
29b99b48 222 lvds_encoder->pfit_dirty = true;
79e53945 223 }
2a1292fd 224
7dec0606
DV
225 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
226 POSTING_READ(lvds_encoder->reg);
79e53945
JB
227}
228
79e53945
JB
229static int intel_lvds_mode_valid(struct drm_connector *connector,
230 struct drm_display_mode *mode)
231{
dd06f90e
JN
232 struct intel_connector *intel_connector = to_intel_connector(connector);
233 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
79e53945 234
788319d4
CW
235 if (mode->hdisplay > fixed_mode->hdisplay)
236 return MODE_PANEL;
237 if (mode->vdisplay > fixed_mode->vdisplay)
238 return MODE_PANEL;
79e53945
JB
239
240 return MODE_OK;
241}
242
49be663f
CW
243static void
244centre_horizontally(struct drm_display_mode *mode,
245 int width)
246{
247 u32 border, sync_pos, blank_width, sync_width;
248
249 /* keep the hsync and hblank widths constant */
250 sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start;
251 blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start;
252 sync_pos = (blank_width - sync_width + 1) / 2;
253
254 border = (mode->hdisplay - width + 1) / 2;
255 border += border & 1; /* make the border even */
256
257 mode->crtc_hdisplay = width;
258 mode->crtc_hblank_start = width + border;
259 mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width;
260
261 mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos;
262 mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width;
f9bef081
DV
263
264 mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET;
49be663f
CW
265}
266
267static void
268centre_vertically(struct drm_display_mode *mode,
269 int height)
270{
271 u32 border, sync_pos, blank_width, sync_width;
272
273 /* keep the vsync and vblank widths constant */
274 sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start;
275 blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start;
276 sync_pos = (blank_width - sync_width + 1) / 2;
277
278 border = (mode->vdisplay - height + 1) / 2;
279
280 mode->crtc_vdisplay = height;
281 mode->crtc_vblank_start = height + border;
282 mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width;
283
284 mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos;
285 mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width;
f9bef081
DV
286
287 mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET;
49be663f
CW
288}
289
290static inline u32 panel_fitter_scaling(u32 source, u32 target)
291{
292 /*
293 * Floating point operation is not supported. So the FACTOR
294 * is defined, which can avoid the floating point computation
295 * when calculating the panel ratio.
296 */
297#define ACCURACY 12
298#define FACTOR (1 << ACCURACY)
299 u32 ratio = source * FACTOR / target;
300 return (FACTOR * ratio + FACTOR/2) / FACTOR;
301}
302
79e53945 303static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
e811f5ae 304 const struct drm_display_mode *mode,
79e53945
JB
305 struct drm_display_mode *adjusted_mode)
306{
307 struct drm_device *dev = encoder->dev;
308 struct drm_i915_private *dev_priv = dev->dev_private;
29b99b48 309 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
4d891523
JN
310 struct intel_connector *intel_connector =
311 &lvds_encoder->attached_connector->base;
29b99b48 312 struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc;
49be663f 313 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
9db4a9c7 314 int pipe;
79e53945
JB
315
316 /* Should never happen!! */
a6c45cf0 317 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
1ae8c0a5 318 DRM_ERROR("Can't support LVDS on pipe A\n");
79e53945
JB
319 return false;
320 }
321
29b99b48 322 if (intel_encoder_check_is_cloned(&lvds_encoder->base))
e24c5c29 323 return false;
1d8e1c75 324
79e53945 325 /*
71677043 326 * We have timings from the BIOS for the panel, put them in
79e53945
JB
327 * to the adjusted mode. The CRTC will be set up for this mode,
328 * with the panel scaling set up to source from the H/VDisplay
329 * of the original mode.
330 */
4d891523 331 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
dd06f90e 332 adjusted_mode);
1d8e1c75
CW
333
334 if (HAS_PCH_SPLIT(dev)) {
4d891523
JN
335 intel_pch_panel_fitting(dev,
336 intel_connector->panel.fitting_mode,
1d8e1c75
CW
337 mode, adjusted_mode);
338 return true;
339 }
79e53945 340
3fbe18d6
ZY
341 /* Native modes don't need fitting */
342 if (adjusted_mode->hdisplay == mode->hdisplay &&
49be663f 343 adjusted_mode->vdisplay == mode->vdisplay)
3fbe18d6 344 goto out;
3fbe18d6
ZY
345
346 /* 965+ wants fuzzy fitting */
a6c45cf0 347 if (INTEL_INFO(dev)->gen >= 4)
49be663f
CW
348 pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
349 PFIT_FILTER_FUZZY);
350
3fbe18d6
ZY
351 /*
352 * Enable automatic panel scaling for non-native modes so that they fill
353 * the screen. Should be enabled before the pipe is enabled, according
354 * to register description and PRM.
355 * Change the value here to see the borders for debugging
356 */
9db4a9c7
JB
357 for_each_pipe(pipe)
358 I915_WRITE(BCLRPAT(pipe), 0);
3fbe18d6 359
f9bef081
DV
360 drm_mode_set_crtcinfo(adjusted_mode, 0);
361
4d891523 362 switch (intel_connector->panel.fitting_mode) {
53bd8389 363 case DRM_MODE_SCALE_CENTER:
3fbe18d6
ZY
364 /*
365 * For centered modes, we have to calculate border widths &
366 * heights and modify the values programmed into the CRTC.
367 */
49be663f
CW
368 centre_horizontally(adjusted_mode, mode->hdisplay);
369 centre_vertically(adjusted_mode, mode->vdisplay);
370 border = LVDS_BORDER_ENABLE;
3fbe18d6 371 break;
49be663f 372
3fbe18d6 373 case DRM_MODE_SCALE_ASPECT:
49be663f 374 /* Scale but preserve the aspect ratio */
a6c45cf0 375 if (INTEL_INFO(dev)->gen >= 4) {
49be663f
CW
376 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
377 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
378
3fbe18d6 379 /* 965+ is easy, it does everything in hw */
49be663f 380 if (scaled_width > scaled_height)
257e48f1 381 pfit_control |= PFIT_ENABLE | PFIT_SCALING_PILLAR;
49be663f 382 else if (scaled_width < scaled_height)
257e48f1
CW
383 pfit_control |= PFIT_ENABLE | PFIT_SCALING_LETTER;
384 else if (adjusted_mode->hdisplay != mode->hdisplay)
385 pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
3fbe18d6 386 } else {
49be663f
CW
387 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
388 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
3fbe18d6
ZY
389 /*
390 * For earlier chips we have to calculate the scaling
391 * ratio by hand and program it into the
392 * PFIT_PGM_RATIO register
393 */
49be663f
CW
394 if (scaled_width > scaled_height) { /* pillar */
395 centre_horizontally(adjusted_mode, scaled_height / mode->vdisplay);
396
397 border = LVDS_BORDER_ENABLE;
398 if (mode->vdisplay != adjusted_mode->vdisplay) {
399 u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay);
400 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
401 bits << PFIT_VERT_SCALE_SHIFT);
402 pfit_control |= (PFIT_ENABLE |
403 VERT_INTERP_BILINEAR |
404 HORIZ_INTERP_BILINEAR);
405 }
406 } else if (scaled_width < scaled_height) { /* letter */
407 centre_vertically(adjusted_mode, scaled_width / mode->hdisplay);
408
409 border = LVDS_BORDER_ENABLE;
410 if (mode->hdisplay != adjusted_mode->hdisplay) {
411 u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay);
412 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
413 bits << PFIT_VERT_SCALE_SHIFT);
414 pfit_control |= (PFIT_ENABLE |
415 VERT_INTERP_BILINEAR |
416 HORIZ_INTERP_BILINEAR);
417 }
418 } else
419 /* Aspects match, Let hw scale both directions */
420 pfit_control |= (PFIT_ENABLE |
421 VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
3fbe18d6
ZY
422 VERT_INTERP_BILINEAR |
423 HORIZ_INTERP_BILINEAR);
3fbe18d6
ZY
424 }
425 break;
426
427 case DRM_MODE_SCALE_FULLSCREEN:
428 /*
429 * Full scaling, even if it changes the aspect ratio.
430 * Fortunately this is all done for us in hw.
431 */
257e48f1
CW
432 if (mode->vdisplay != adjusted_mode->vdisplay ||
433 mode->hdisplay != adjusted_mode->hdisplay) {
434 pfit_control |= PFIT_ENABLE;
435 if (INTEL_INFO(dev)->gen >= 4)
436 pfit_control |= PFIT_SCALING_AUTO;
437 else
438 pfit_control |= (VERT_AUTO_SCALE |
439 VERT_INTERP_BILINEAR |
440 HORIZ_AUTO_SCALE |
441 HORIZ_INTERP_BILINEAR);
442 }
3fbe18d6 443 break;
49be663f 444
3fbe18d6
ZY
445 default:
446 break;
447 }
448
449out:
72389a33 450 /* If not enabling scaling, be consistent and always use 0. */
bee17e5a
CW
451 if ((pfit_control & PFIT_ENABLE) == 0) {
452 pfit_control = 0;
453 pfit_pgm_ratios = 0;
454 }
72389a33
CW
455
456 /* Make sure pre-965 set dither correctly */
457 if (INTEL_INFO(dev)->gen < 4 && dev_priv->lvds_dither)
458 pfit_control |= PANEL_8TO6_DITHER_ENABLE;
459
29b99b48
JN
460 if (pfit_control != lvds_encoder->pfit_control ||
461 pfit_pgm_ratios != lvds_encoder->pfit_pgm_ratios) {
462 lvds_encoder->pfit_control = pfit_control;
463 lvds_encoder->pfit_pgm_ratios = pfit_pgm_ratios;
464 lvds_encoder->pfit_dirty = true;
e9e331a8 465 }
49be663f
CW
466 dev_priv->lvds_border_bits = border;
467
79e53945
JB
468 /*
469 * XXX: It would be nice to support lower refresh rates on the
470 * panels to reduce power consumption, and perhaps match the
471 * user's requested refresh rate.
472 */
473
474 return true;
475}
476
79e53945
JB
477static void intel_lvds_mode_set(struct drm_encoder *encoder,
478 struct drm_display_mode *mode,
479 struct drm_display_mode *adjusted_mode)
480{
79e53945
JB
481 /*
482 * The LVDS pin pair will already have been turned on in the
483 * intel_crtc_mode_set since it has a large impact on the DPLL
484 * settings.
485 */
79e53945
JB
486}
487
488/**
489 * Detect the LVDS connection.
490 *
b42d4c5c
JB
491 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means
492 * connected and closed means disconnected. We also send hotplug events as
493 * needed, using lid status notification from the input layer.
79e53945 494 */
7b334fcb 495static enum drm_connector_status
930a9e28 496intel_lvds_detect(struct drm_connector *connector, bool force)
79e53945 497{
7b9c5abe 498 struct drm_device *dev = connector->dev;
6ee3b5a1 499 enum drm_connector_status status;
b42d4c5c 500
fe16d949
CW
501 status = intel_panel_detect(dev);
502 if (status != connector_status_unknown)
503 return status;
01fe9dbd 504
6ee3b5a1 505 return connector_status_connected;
79e53945
JB
506}
507
508/**
509 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
510 */
511static int intel_lvds_get_modes(struct drm_connector *connector)
512{
62165e0d 513 struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);
79e53945 514 struct drm_device *dev = connector->dev;
788319d4 515 struct drm_display_mode *mode;
79e53945 516
9cd300e0 517 /* use cached edid if we have one */
2aa4f099 518 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
9cd300e0 519 return drm_add_edid_modes(connector, lvds_connector->base.edid);
79e53945 520
dd06f90e 521 mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode);
311bd68e 522 if (mode == NULL)
788319d4 523 return 0;
79e53945 524
788319d4
CW
525 drm_mode_probed_add(connector, mode);
526 return 1;
79e53945
JB
527}
528
0544edfd
TB
529static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
530{
bc0daf48 531 DRM_INFO("Skipping forced modeset for %s\n", id->ident);
0544edfd
TB
532 return 1;
533}
534
535/* The GPU hangs up on these systems if modeset is performed on LID open */
536static const struct dmi_system_id intel_no_modeset_on_lid[] = {
537 {
538 .callback = intel_no_modeset_on_lid_dmi_callback,
539 .ident = "Toshiba Tecra A11",
540 .matches = {
541 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
542 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
543 },
544 },
545
546 { } /* terminating entry */
547};
548
c9354c85
LT
549/*
550 * Lid events. Note the use of 'modeset_on_lid':
551 * - we set it on lid close, and reset it on open
552 * - we use it as a "only once" bit (ie we ignore
553 * duplicate events where it was already properly
554 * set/reset)
555 * - the suspend/resume paths will also set it to
556 * zero, since they restore the mode ("lid open").
557 */
c1c7af60
JB
558static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
559 void *unused)
560{
db1740a0
JN
561 struct intel_lvds_connector *lvds_connector =
562 container_of(nb, struct intel_lvds_connector, lid_notifier);
563 struct drm_connector *connector = &lvds_connector->base.base;
564 struct drm_device *dev = connector->dev;
565 struct drm_i915_private *dev_priv = dev->dev_private;
c1c7af60 566
2fb4e61d
AW
567 if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
568 return NOTIFY_OK;
569
a2565377
ZY
570 /*
571 * check and update the status of LVDS connector after receiving
572 * the LID nofication event.
573 */
db1740a0 574 connector->status = connector->funcs->detect(connector, false);
7b334fcb 575
0544edfd
TB
576 /* Don't force modeset on machines where it causes a GPU lockup */
577 if (dmi_check_system(intel_no_modeset_on_lid))
578 return NOTIFY_OK;
c9354c85
LT
579 if (!acpi_lid_open()) {
580 dev_priv->modeset_on_lid = 1;
581 return NOTIFY_OK;
06891e27 582 }
c1c7af60 583
c9354c85
LT
584 if (!dev_priv->modeset_on_lid)
585 return NOTIFY_OK;
586
587 dev_priv->modeset_on_lid = 0;
588
a0e99e68 589 drm_modeset_lock_all(dev);
45e2b5f6 590 intel_modeset_setup_hw_state(dev, true);
a0e99e68 591 drm_modeset_unlock_all(dev);
06324194 592
c1c7af60
JB
593 return NOTIFY_OK;
594}
595
79e53945
JB
596/**
597 * intel_lvds_destroy - unregister and free LVDS structures
598 * @connector: connector to free
599 *
600 * Unregister the DDC bus for this connector then free the driver private
601 * structure.
602 */
603static void intel_lvds_destroy(struct drm_connector *connector)
604{
db1740a0
JN
605 struct intel_lvds_connector *lvds_connector =
606 to_lvds_connector(connector);
79e53945 607
db1740a0
JN
608 if (lvds_connector->lid_notifier.notifier_call)
609 acpi_lid_notifier_unregister(&lvds_connector->lid_notifier);
79e53945 610
9cd300e0
JN
611 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
612 kfree(lvds_connector->base.edid);
613
db1740a0 614 intel_panel_destroy_backlight(connector->dev);
1d508706 615 intel_panel_fini(&lvds_connector->base.panel);
aaa6fd2a 616
79e53945
JB
617 drm_sysfs_connector_remove(connector);
618 drm_connector_cleanup(connector);
619 kfree(connector);
620}
621
335041ed
JB
622static int intel_lvds_set_property(struct drm_connector *connector,
623 struct drm_property *property,
624 uint64_t value)
625{
4d891523 626 struct intel_connector *intel_connector = to_intel_connector(connector);
3fbe18d6 627 struct drm_device *dev = connector->dev;
3fbe18d6 628
788319d4 629 if (property == dev->mode_config.scaling_mode_property) {
62165e0d 630 struct drm_crtc *crtc;
bb8a3560 631
53bd8389
JB
632 if (value == DRM_MODE_SCALE_NONE) {
633 DRM_DEBUG_KMS("no scaling not supported\n");
788319d4 634 return -EINVAL;
3fbe18d6 635 }
788319d4 636
4d891523 637 if (intel_connector->panel.fitting_mode == value) {
3fbe18d6
ZY
638 /* the LVDS scaling property is not changed */
639 return 0;
640 }
4d891523 641 intel_connector->panel.fitting_mode = value;
62165e0d
JN
642
643 crtc = intel_attached_encoder(connector)->base.crtc;
3fbe18d6
ZY
644 if (crtc && crtc->enabled) {
645 /*
646 * If the CRTC is enabled, the display will be changed
647 * according to the new panel fitting mode.
648 */
c0c36b94 649 intel_crtc_restore_mode(crtc);
3fbe18d6
ZY
650 }
651 }
652
335041ed
JB
653 return 0;
654}
655
79e53945 656static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = {
79e53945 657 .mode_fixup = intel_lvds_mode_fixup,
79e53945 658 .mode_set = intel_lvds_mode_set,
1f703855 659 .disable = intel_encoder_noop,
79e53945
JB
660};
661
662static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
663 .get_modes = intel_lvds_get_modes,
664 .mode_valid = intel_lvds_mode_valid,
df0e9248 665 .best_encoder = intel_best_encoder,
79e53945
JB
666};
667
668static const struct drm_connector_funcs intel_lvds_connector_funcs = {
c22834ec 669 .dpms = intel_connector_dpms,
79e53945
JB
670 .detect = intel_lvds_detect,
671 .fill_modes = drm_helper_probe_single_connector_modes,
335041ed 672 .set_property = intel_lvds_set_property,
79e53945
JB
673 .destroy = intel_lvds_destroy,
674};
675
79e53945 676static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
ea5b213a 677 .destroy = intel_encoder_destroy,
79e53945
JB
678};
679
425d244c
JW
680static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
681{
bc0daf48 682 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
425d244c
JW
683 return 1;
684}
79e53945 685
425d244c 686/* These systems claim to have LVDS, but really don't */
93c05f22 687static const struct dmi_system_id intel_no_lvds[] = {
425d244c
JW
688 {
689 .callback = intel_no_lvds_dmi_callback,
690 .ident = "Apple Mac Mini (Core series)",
691 .matches = {
98acd46f 692 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
693 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
694 },
695 },
696 {
697 .callback = intel_no_lvds_dmi_callback,
698 .ident = "Apple Mac Mini (Core 2 series)",
699 .matches = {
98acd46f 700 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
701 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
702 },
703 },
704 {
705 .callback = intel_no_lvds_dmi_callback,
706 .ident = "MSI IM-945GSE-A",
707 .matches = {
708 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
709 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
710 },
711 },
712 {
713 .callback = intel_no_lvds_dmi_callback,
714 .ident = "Dell Studio Hybrid",
715 .matches = {
716 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
717 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
718 },
719 },
70aa96ca
JW
720 {
721 .callback = intel_no_lvds_dmi_callback,
b066254f
PC
722 .ident = "Dell OptiPlex FX170",
723 .matches = {
724 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
725 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
726 },
727 },
728 {
729 .callback = intel_no_lvds_dmi_callback,
70aa96ca
JW
730 .ident = "AOpen Mini PC",
731 .matches = {
732 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
733 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
734 },
735 },
ed8c754b
TV
736 {
737 .callback = intel_no_lvds_dmi_callback,
738 .ident = "AOpen Mini PC MP915",
739 .matches = {
740 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
741 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
742 },
743 },
22ab70d3
KP
744 {
745 .callback = intel_no_lvds_dmi_callback,
746 .ident = "AOpen i915GMm-HFS",
747 .matches = {
748 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
749 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
750 },
751 },
e57b6886
DV
752 {
753 .callback = intel_no_lvds_dmi_callback,
754 .ident = "AOpen i45GMx-I",
755 .matches = {
756 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
757 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
758 },
759 },
fa0864b2
MC
760 {
761 .callback = intel_no_lvds_dmi_callback,
762 .ident = "Aopen i945GTt-VFA",
763 .matches = {
764 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
765 },
766 },
9875557e
SB
767 {
768 .callback = intel_no_lvds_dmi_callback,
769 .ident = "Clientron U800",
770 .matches = {
771 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
772 DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
773 },
774 },
6a574b5b 775 {
44306ab3
JS
776 .callback = intel_no_lvds_dmi_callback,
777 .ident = "Clientron E830",
778 .matches = {
779 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
780 DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
781 },
782 },
783 {
6a574b5b
HG
784 .callback = intel_no_lvds_dmi_callback,
785 .ident = "Asus EeeBox PC EB1007",
786 .matches = {
787 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
788 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
789 },
790 },
0999bbe0
AJ
791 {
792 .callback = intel_no_lvds_dmi_callback,
793 .ident = "Asus AT5NM10T-I",
794 .matches = {
795 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
796 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
797 },
798 },
33471119
JBG
799 {
800 .callback = intel_no_lvds_dmi_callback,
801 .ident = "Hewlett-Packard HP t5740e Thin Client",
802 .matches = {
803 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
804 DMI_MATCH(DMI_PRODUCT_NAME, "HP t5740e Thin Client"),
805 },
806 },
f5b8a7ed
MG
807 {
808 .callback = intel_no_lvds_dmi_callback,
809 .ident = "Hewlett-Packard t5745",
810 .matches = {
811 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 812 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
f5b8a7ed
MG
813 },
814 },
815 {
816 .callback = intel_no_lvds_dmi_callback,
817 .ident = "Hewlett-Packard st5747",
818 .matches = {
819 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 820 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
f5b8a7ed
MG
821 },
822 },
97effadb
AA
823 {
824 .callback = intel_no_lvds_dmi_callback,
825 .ident = "MSI Wind Box DC500",
826 .matches = {
827 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
828 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
829 },
830 },
a51d4ed0
CW
831 {
832 .callback = intel_no_lvds_dmi_callback,
833 .ident = "Gigabyte GA-D525TUD",
834 .matches = {
835 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
836 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
837 },
838 },
c31407a3
CW
839 {
840 .callback = intel_no_lvds_dmi_callback,
841 .ident = "Supermicro X7SPA-H",
842 .matches = {
843 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
844 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
845 },
846 },
425d244c
JW
847
848 { } /* terminating entry */
849};
79e53945 850
18f9ed12
ZY
851/**
852 * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID
853 * @dev: drm device
854 * @connector: LVDS connector
855 *
856 * Find the reduced downclock for LVDS in EDID.
857 */
858static void intel_find_lvds_downclock(struct drm_device *dev,
788319d4
CW
859 struct drm_display_mode *fixed_mode,
860 struct drm_connector *connector)
18f9ed12
ZY
861{
862 struct drm_i915_private *dev_priv = dev->dev_private;
788319d4 863 struct drm_display_mode *scan;
18f9ed12
ZY
864 int temp_downclock;
865
788319d4 866 temp_downclock = fixed_mode->clock;
18f9ed12
ZY
867 list_for_each_entry(scan, &connector->probed_modes, head) {
868 /*
869 * If one mode has the same resolution with the fixed_panel
870 * mode while they have the different refresh rate, it means
871 * that the reduced downclock is found for the LVDS. In such
872 * case we can set the different FPx0/1 to dynamically select
873 * between low and high frequency.
874 */
788319d4
CW
875 if (scan->hdisplay == fixed_mode->hdisplay &&
876 scan->hsync_start == fixed_mode->hsync_start &&
877 scan->hsync_end == fixed_mode->hsync_end &&
878 scan->htotal == fixed_mode->htotal &&
879 scan->vdisplay == fixed_mode->vdisplay &&
880 scan->vsync_start == fixed_mode->vsync_start &&
881 scan->vsync_end == fixed_mode->vsync_end &&
882 scan->vtotal == fixed_mode->vtotal) {
18f9ed12
ZY
883 if (scan->clock < temp_downclock) {
884 /*
885 * The downclock is already found. But we
886 * expect to find the lower downclock.
887 */
888 temp_downclock = scan->clock;
889 }
890 }
891 }
788319d4 892 if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) {
18f9ed12
ZY
893 /* We found the downclock for LVDS. */
894 dev_priv->lvds_downclock_avail = 1;
895 dev_priv->lvds_downclock = temp_downclock;
896 DRM_DEBUG_KMS("LVDS downclock is found in EDID. "
788319d4
CW
897 "Normal clock %dKhz, downclock %dKhz\n",
898 fixed_mode->clock, temp_downclock);
18f9ed12 899 }
18f9ed12
ZY
900}
901
7cf4f69d
ZY
902/*
903 * Enumerate the child dev array parsed from VBT to check whether
904 * the LVDS is present.
905 * If it is present, return 1.
906 * If it is not present, return false.
907 * If no child dev is parsed from VBT, it assumes that the LVDS is present.
7cf4f69d 908 */
270eea0f
CW
909static bool lvds_is_present_in_vbt(struct drm_device *dev,
910 u8 *i2c_pin)
7cf4f69d
ZY
911{
912 struct drm_i915_private *dev_priv = dev->dev_private;
425904dd 913 int i;
7cf4f69d
ZY
914
915 if (!dev_priv->child_dev_num)
425904dd 916 return true;
7cf4f69d 917
7cf4f69d 918 for (i = 0; i < dev_priv->child_dev_num; i++) {
425904dd
CW
919 struct child_device_config *child = dev_priv->child_dev + i;
920
921 /* If the device type is not LFP, continue.
922 * We have to check both the new identifiers as well as the
923 * old for compatibility with some BIOSes.
7cf4f69d 924 */
425904dd
CW
925 if (child->device_type != DEVICE_TYPE_INT_LFP &&
926 child->device_type != DEVICE_TYPE_LFP)
7cf4f69d
ZY
927 continue;
928
3bd7d909
DK
929 if (intel_gmbus_is_port_valid(child->i2c_pin))
930 *i2c_pin = child->i2c_pin;
270eea0f 931
425904dd
CW
932 /* However, we cannot trust the BIOS writers to populate
933 * the VBT correctly. Since LVDS requires additional
934 * information from AIM blocks, a non-zero addin offset is
935 * a good indicator that the LVDS is actually present.
7cf4f69d 936 */
425904dd
CW
937 if (child->addin_offset)
938 return true;
939
940 /* But even then some BIOS writers perform some black magic
941 * and instantiate the device without reference to any
942 * additional data. Trust that if the VBT was written into
943 * the OpRegion then they have validated the LVDS's existence.
944 */
945 if (dev_priv->opregion.vbt)
946 return true;
7cf4f69d 947 }
425904dd
CW
948
949 return false;
7cf4f69d
ZY
950}
951
1974cad0
DV
952static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
953{
954 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
955 return 1;
956}
957
958static const struct dmi_system_id intel_dual_link_lvds[] = {
959 {
960 .callback = intel_dual_link_lvds_callback,
961 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
962 .matches = {
963 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
964 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
965 },
966 },
967 { } /* terminating entry */
968};
969
970bool intel_is_dual_link_lvds(struct drm_device *dev)
13c7d870
DV
971{
972 struct intel_encoder *encoder;
973 struct intel_lvds_encoder *lvds_encoder;
974
975 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
976 base.head) {
977 if (encoder->type == INTEL_OUTPUT_LVDS) {
978 lvds_encoder = to_lvds_encoder(&encoder->base);
979
980 return lvds_encoder->is_dual_link;
981 }
982 }
983
984 return false;
985}
986
7dec0606 987static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
1974cad0 988{
7dec0606 989 struct drm_device *dev = lvds_encoder->base.base.dev;
1974cad0
DV
990 unsigned int val;
991 struct drm_i915_private *dev_priv = dev->dev_private;
1974cad0
DV
992
993 /* use the module option value if specified */
994 if (i915_lvds_channel_mode > 0)
995 return i915_lvds_channel_mode == 2;
996
997 if (dmi_check_system(intel_dual_link_lvds))
998 return true;
999
13c7d870
DV
1000 /* BIOS should set the proper LVDS register value at boot, but
1001 * in reality, it doesn't set the value when the lid is closed;
1002 * we need to check "the value to be set" in VBT when LVDS
1003 * register is uninitialized.
1004 */
7dec0606 1005 val = I915_READ(lvds_encoder->reg);
13c7d870
DV
1006 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
1007 val = dev_priv->bios_lvds_val;
1008
1974cad0
DV
1009 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
1010}
1011
f3cfcba6
CW
1012static bool intel_lvds_supported(struct drm_device *dev)
1013{
1014 /* With the introduction of the PCH we gained a dedicated
1015 * LVDS presence pin, use it. */
1016 if (HAS_PCH_SPLIT(dev))
1017 return true;
1018
1019 /* Otherwise LVDS was only attached to mobile products,
1020 * except for the inglorious 830gm */
1021 return IS_MOBILE(dev) && !IS_I830(dev);
1022}
1023
79e53945
JB
1024/**
1025 * intel_lvds_init - setup LVDS connectors on this device
1026 * @dev: drm device
1027 *
1028 * Create the connector, register the LVDS DDC bus, and try to figure out what
1029 * modes we can display on the LVDS panel (if present).
1030 */
c5d1b51d 1031bool intel_lvds_init(struct drm_device *dev)
79e53945
JB
1032{
1033 struct drm_i915_private *dev_priv = dev->dev_private;
29b99b48 1034 struct intel_lvds_encoder *lvds_encoder;
21d40d37 1035 struct intel_encoder *intel_encoder;
c7362c4d 1036 struct intel_lvds_connector *lvds_connector;
bb8a3560 1037 struct intel_connector *intel_connector;
79e53945
JB
1038 struct drm_connector *connector;
1039 struct drm_encoder *encoder;
1040 struct drm_display_mode *scan; /* *modes, *bios_mode; */
dd06f90e 1041 struct drm_display_mode *fixed_mode = NULL;
9cd300e0 1042 struct edid *edid;
79e53945
JB
1043 struct drm_crtc *crtc;
1044 u32 lvds;
270eea0f
CW
1045 int pipe;
1046 u8 pin;
79e53945 1047
f3cfcba6
CW
1048 if (!intel_lvds_supported(dev))
1049 return false;
1050
425d244c
JW
1051 /* Skip init on machines we know falsely report LVDS */
1052 if (dmi_check_system(intel_no_lvds))
c5d1b51d 1053 return false;
565dcd46 1054
270eea0f
CW
1055 pin = GMBUS_PORT_PANEL;
1056 if (!lvds_is_present_in_vbt(dev, &pin)) {
11ba1592 1057 DRM_DEBUG_KMS("LVDS is not present in VBT\n");
c5d1b51d 1058 return false;
38b3037e 1059 }
e99da35f 1060
c619eed4 1061 if (HAS_PCH_SPLIT(dev)) {
541998a1 1062 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
c5d1b51d 1063 return false;
5ceb0f9b 1064 if (dev_priv->edp.support) {
28c97730 1065 DRM_DEBUG_KMS("disable LVDS for eDP support\n");
c5d1b51d 1066 return false;
32f9d658 1067 }
541998a1
ZW
1068 }
1069
29b99b48
JN
1070 lvds_encoder = kzalloc(sizeof(struct intel_lvds_encoder), GFP_KERNEL);
1071 if (!lvds_encoder)
c5d1b51d 1072 return false;
79e53945 1073
c7362c4d
JN
1074 lvds_connector = kzalloc(sizeof(struct intel_lvds_connector), GFP_KERNEL);
1075 if (!lvds_connector) {
29b99b48 1076 kfree(lvds_encoder);
c5d1b51d 1077 return false;
bb8a3560
ZW
1078 }
1079
62165e0d
JN
1080 lvds_encoder->attached_connector = lvds_connector;
1081
e9e331a8 1082 if (!HAS_PCH_SPLIT(dev)) {
29b99b48 1083 lvds_encoder->pfit_control = I915_READ(PFIT_CONTROL);
e9e331a8
CW
1084 }
1085
29b99b48 1086 intel_encoder = &lvds_encoder->base;
4ef69c7a 1087 encoder = &intel_encoder->base;
c7362c4d 1088 intel_connector = &lvds_connector->base;
ea5b213a 1089 connector = &intel_connector->base;
bb8a3560 1090 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
79e53945
JB
1091 DRM_MODE_CONNECTOR_LVDS);
1092
4ef69c7a 1093 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
79e53945
JB
1094 DRM_MODE_ENCODER_LVDS);
1095
c22834ec 1096 intel_encoder->enable = intel_enable_lvds;
fc683091 1097 intel_encoder->pre_pll_enable = intel_pre_pll_enable_lvds;
c22834ec 1098 intel_encoder->disable = intel_disable_lvds;
b1dc332c
DV
1099 intel_encoder->get_hw_state = intel_lvds_get_hw_state;
1100 intel_connector->get_hw_state = intel_connector_get_hw_state;
c22834ec 1101
df0e9248 1102 intel_connector_attach_encoder(intel_connector, intel_encoder);
21d40d37 1103 intel_encoder->type = INTEL_OUTPUT_LVDS;
79e53945 1104
66a9278e 1105 intel_encoder->cloneable = false;
27f8227b
JB
1106 if (HAS_PCH_SPLIT(dev))
1107 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
0b9f43a0
DV
1108 else if (IS_GEN4(dev))
1109 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
27f8227b
JB
1110 else
1111 intel_encoder->crtc_mask = (1 << 1);
1112
79e53945
JB
1113 drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs);
1114 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
1115 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1116 connector->interlace_allowed = false;
1117 connector->doublescan_allowed = false;
1118
7dec0606
DV
1119 if (HAS_PCH_SPLIT(dev)) {
1120 lvds_encoder->reg = PCH_LVDS;
1121 } else {
1122 lvds_encoder->reg = LVDS;
1123 }
1124
3fbe18d6
ZY
1125 /* create the scaling mode property */
1126 drm_mode_create_scaling_mode_property(dev);
662595df 1127 drm_object_attach_property(&connector->base,
3fbe18d6 1128 dev->mode_config.scaling_mode_property,
dd1ea37d 1129 DRM_MODE_SCALE_ASPECT);
4d891523 1130 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
79e53945
JB
1131 /*
1132 * LVDS discovery:
1133 * 1) check for EDID on DDC
1134 * 2) check for VBT data
1135 * 3) check to see if LVDS is already on
1136 * if none of the above, no panel
1137 * 4) make sure lid is open
1138 * if closed, act like it's not there for now
1139 */
1140
79e53945
JB
1141 /*
1142 * Attempt to get the fixed panel mode from DDC. Assume that the
1143 * preferred mode is the right one.
1144 */
9cd300e0
JN
1145 edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv, pin));
1146 if (edid) {
1147 if (drm_add_edid_modes(connector, edid)) {
3f8ff0e7 1148 drm_mode_connector_update_edid_property(connector,
9cd300e0 1149 edid);
3f8ff0e7 1150 } else {
9cd300e0
JN
1151 kfree(edid);
1152 edid = ERR_PTR(-EINVAL);
3f8ff0e7 1153 }
9cd300e0
JN
1154 } else {
1155 edid = ERR_PTR(-ENOENT);
3f8ff0e7 1156 }
9cd300e0
JN
1157 lvds_connector->base.edid = edid;
1158
1159 if (IS_ERR_OR_NULL(edid)) {
788319d4
CW
1160 /* Didn't get an EDID, so
1161 * Set wide sync ranges so we get all modes
1162 * handed to valid_mode for checking
1163 */
1164 connector->display_info.min_vfreq = 0;
1165 connector->display_info.max_vfreq = 200;
1166 connector->display_info.min_hfreq = 0;
1167 connector->display_info.max_hfreq = 200;
1168 }
79e53945
JB
1169
1170 list_for_each_entry(scan, &connector->probed_modes, head) {
79e53945 1171 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
6a9d51b7
CW
1172 DRM_DEBUG_KMS("using preferred mode from EDID: ");
1173 drm_mode_debug_printmodeline(scan);
1174
dd06f90e 1175 fixed_mode = drm_mode_duplicate(dev, scan);
6a9d51b7
CW
1176 if (fixed_mode) {
1177 intel_find_lvds_downclock(dev, fixed_mode,
1178 connector);
1179 goto out;
1180 }
79e53945 1181 }
79e53945
JB
1182 }
1183
1184 /* Failed to get EDID, what about VBT? */
88631706 1185 if (dev_priv->lfp_lvds_vbt_mode) {
6a9d51b7
CW
1186 DRM_DEBUG_KMS("using mode from VBT: ");
1187 drm_mode_debug_printmodeline(dev_priv->lfp_lvds_vbt_mode);
1188
dd06f90e
JN
1189 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1190 if (fixed_mode) {
1191 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
e285f3cd
JB
1192 goto out;
1193 }
79e53945
JB
1194 }
1195
1196 /*
1197 * If we didn't get EDID, try checking if the panel is already turned
1198 * on. If so, assume that whatever is currently programmed is the
1199 * correct mode.
1200 */
541998a1 1201
f2b115e6 1202 /* Ironlake: FIXME if still fail, not try pipe mode now */
c619eed4 1203 if (HAS_PCH_SPLIT(dev))
541998a1
ZW
1204 goto failed;
1205
79e53945
JB
1206 lvds = I915_READ(LVDS);
1207 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
f875c15a 1208 crtc = intel_get_crtc_for_pipe(dev, pipe);
79e53945
JB
1209
1210 if (crtc && (lvds & LVDS_PORT_EN)) {
dd06f90e
JN
1211 fixed_mode = intel_crtc_mode_get(dev, crtc);
1212 if (fixed_mode) {
6a9d51b7
CW
1213 DRM_DEBUG_KMS("using current (BIOS) mode: ");
1214 drm_mode_debug_printmodeline(fixed_mode);
dd06f90e 1215 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
565dcd46 1216 goto out;
79e53945
JB
1217 }
1218 }
1219
1220 /* If we still don't have a mode after all that, give up. */
dd06f90e 1221 if (!fixed_mode)
79e53945
JB
1222 goto failed;
1223
79e53945 1224out:
7dec0606 1225 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
13c7d870
DV
1226 DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
1227 lvds_encoder->is_dual_link ? "dual" : "single");
1228
24ded204
DV
1229 /*
1230 * Unlock registers and just
1231 * leave them unlocked
1232 */
c619eed4 1233 if (HAS_PCH_SPLIT(dev)) {
ed10fca9
KP
1234 I915_WRITE(PCH_PP_CONTROL,
1235 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
1236 } else {
ed10fca9
KP
1237 I915_WRITE(PP_CONTROL,
1238 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
541998a1 1239 }
db1740a0
JN
1240 lvds_connector->lid_notifier.notifier_call = intel_lid_notify;
1241 if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) {
28c97730 1242 DRM_DEBUG_KMS("lid notifier registration failed\n");
db1740a0 1243 lvds_connector->lid_notifier.notifier_call = NULL;
c1c7af60 1244 }
79e53945 1245 drm_sysfs_connector_add(connector);
aaa6fd2a 1246
dd06f90e 1247 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 1248 intel_panel_setup_backlight(connector);
aaa6fd2a 1249
c5d1b51d 1250 return true;
79e53945
JB
1251
1252failed:
8a4c47f3 1253 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
79e53945 1254 drm_connector_cleanup(connector);
1991bdfa 1255 drm_encoder_cleanup(encoder);
dd06f90e
JN
1256 if (fixed_mode)
1257 drm_mode_destroy(dev, fixed_mode);
29b99b48 1258 kfree(lvds_encoder);
c7362c4d 1259 kfree(lvds_connector);
c5d1b51d 1260 return false;
79e53945 1261}