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b20385f1 OM |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * Michel Thierry <michel.thierry@intel.com> | |
26 | * Thomas Daniel <thomas.daniel@intel.com> | |
27 | * Oscar Mateo <oscar.mateo@intel.com> | |
28 | * | |
29 | */ | |
30 | ||
73e4d07f OM |
31 | /** |
32 | * DOC: Logical Rings, Logical Ring Contexts and Execlists | |
33 | * | |
34 | * Motivation: | |
b20385f1 OM |
35 | * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". |
36 | * These expanded contexts enable a number of new abilities, especially | |
37 | * "Execlists" (also implemented in this file). | |
38 | * | |
73e4d07f OM |
39 | * One of the main differences with the legacy HW contexts is that logical |
40 | * ring contexts incorporate many more things to the context's state, like | |
41 | * PDPs or ringbuffer control registers: | |
42 | * | |
43 | * The reason why PDPs are included in the context is straightforward: as | |
44 | * PPGTTs (per-process GTTs) are actually per-context, having the PDPs | |
45 | * contained there mean you don't need to do a ppgtt->switch_mm yourself, | |
46 | * instead, the GPU will do it for you on the context switch. | |
47 | * | |
48 | * But, what about the ringbuffer control registers (head, tail, etc..)? | |
49 | * shouldn't we just need a set of those per engine command streamer? This is | |
50 | * where the name "Logical Rings" starts to make sense: by virtualizing the | |
51 | * rings, the engine cs shifts to a new "ring buffer" with every context | |
52 | * switch. When you want to submit a workload to the GPU you: A) choose your | |
53 | * context, B) find its appropriate virtualized ring, C) write commands to it | |
54 | * and then, finally, D) tell the GPU to switch to that context. | |
55 | * | |
56 | * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch | |
57 | * to a contexts is via a context execution list, ergo "Execlists". | |
58 | * | |
59 | * LRC implementation: | |
60 | * Regarding the creation of contexts, we have: | |
61 | * | |
62 | * - One global default context. | |
63 | * - One local default context for each opened fd. | |
64 | * - One local extra context for each context create ioctl call. | |
65 | * | |
66 | * Now that ringbuffers belong per-context (and not per-engine, like before) | |
67 | * and that contexts are uniquely tied to a given engine (and not reusable, | |
68 | * like before) we need: | |
69 | * | |
70 | * - One ringbuffer per-engine inside each context. | |
71 | * - One backing object per-engine inside each context. | |
72 | * | |
73 | * The global default context starts its life with these new objects fully | |
74 | * allocated and populated. The local default context for each opened fd is | |
75 | * more complex, because we don't know at creation time which engine is going | |
76 | * to use them. To handle this, we have implemented a deferred creation of LR | |
77 | * contexts: | |
78 | * | |
79 | * The local context starts its life as a hollow or blank holder, that only | |
80 | * gets populated for a given engine once we receive an execbuffer. If later | |
81 | * on we receive another execbuffer ioctl for the same context but a different | |
82 | * engine, we allocate/populate a new ringbuffer and context backing object and | |
83 | * so on. | |
84 | * | |
85 | * Finally, regarding local contexts created using the ioctl call: as they are | |
86 | * only allowed with the render ring, we can allocate & populate them right | |
87 | * away (no need to defer anything, at least for now). | |
88 | * | |
89 | * Execlists implementation: | |
b20385f1 OM |
90 | * Execlists are the new method by which, on gen8+ hardware, workloads are |
91 | * submitted for execution (as opposed to the legacy, ringbuffer-based, method). | |
73e4d07f OM |
92 | * This method works as follows: |
93 | * | |
94 | * When a request is committed, its commands (the BB start and any leading or | |
95 | * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer | |
96 | * for the appropriate context. The tail pointer in the hardware context is not | |
97 | * updated at this time, but instead, kept by the driver in the ringbuffer | |
98 | * structure. A structure representing this request is added to a request queue | |
99 | * for the appropriate engine: this structure contains a copy of the context's | |
100 | * tail after the request was written to the ring buffer and a pointer to the | |
101 | * context itself. | |
102 | * | |
103 | * If the engine's request queue was empty before the request was added, the | |
104 | * queue is processed immediately. Otherwise the queue will be processed during | |
105 | * a context switch interrupt. In any case, elements on the queue will get sent | |
106 | * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a | |
107 | * globally unique 20-bits submission ID. | |
108 | * | |
109 | * When execution of a request completes, the GPU updates the context status | |
110 | * buffer with a context complete event and generates a context switch interrupt. | |
111 | * During the interrupt handling, the driver examines the events in the buffer: | |
112 | * for each context complete event, if the announced ID matches that on the head | |
113 | * of the request queue, then that request is retired and removed from the queue. | |
114 | * | |
115 | * After processing, if any requests were retired and the queue is not empty | |
116 | * then a new execution list can be submitted. The two requests at the front of | |
117 | * the queue are next to be submitted but since a context may not occur twice in | |
118 | * an execution list, if subsequent requests have the same ID as the first then | |
119 | * the two requests must be combined. This is done simply by discarding requests | |
120 | * at the head of the queue until either only one requests is left (in which case | |
121 | * we use a NULL second context) or the first two requests have unique IDs. | |
122 | * | |
123 | * By always executing the first two requests in the queue the driver ensures | |
124 | * that the GPU is kept as busy as possible. In the case where a single context | |
125 | * completes but a second context is still executing, the request for this second | |
126 | * context will be at the head of the queue when we remove the first one. This | |
127 | * request will then be resubmitted along with a new request for a different context, | |
128 | * which will cause the hardware to continue executing the second request and queue | |
129 | * the new request (the GPU detects the condition of a context getting preempted | |
130 | * with the same context and optimizes the context switch flow by not doing | |
131 | * preemption, but just sampling the new tail pointer). | |
132 | * | |
b20385f1 | 133 | */ |
27af5eea | 134 | #include <linux/interrupt.h> |
b20385f1 OM |
135 | |
136 | #include <drm/drmP.h> | |
137 | #include <drm/i915_drm.h> | |
138 | #include "i915_drv.h" | |
3bbaba0c | 139 | #include "intel_mocs.h" |
127f1003 | 140 | |
e981e7b1 TD |
141 | #define RING_EXECLIST_QFULL (1 << 0x2) |
142 | #define RING_EXECLIST1_VALID (1 << 0x3) | |
143 | #define RING_EXECLIST0_VALID (1 << 0x4) | |
144 | #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) | |
145 | #define RING_EXECLIST1_ACTIVE (1 << 0x11) | |
146 | #define RING_EXECLIST0_ACTIVE (1 << 0x12) | |
147 | ||
148 | #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) | |
149 | #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) | |
150 | #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) | |
151 | #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) | |
152 | #define GEN8_CTX_STATUS_COMPLETE (1 << 4) | |
153 | #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) | |
8670d6f9 | 154 | |
70c2a24d CW |
155 | #define GEN8_CTX_STATUS_COMPLETED_MASK \ |
156 | (GEN8_CTX_STATUS_ACTIVE_IDLE | \ | |
157 | GEN8_CTX_STATUS_PREEMPTED | \ | |
158 | GEN8_CTX_STATUS_ELEMENT_SWITCH) | |
159 | ||
8670d6f9 OM |
160 | #define CTX_LRI_HEADER_0 0x01 |
161 | #define CTX_CONTEXT_CONTROL 0x02 | |
162 | #define CTX_RING_HEAD 0x04 | |
163 | #define CTX_RING_TAIL 0x06 | |
164 | #define CTX_RING_BUFFER_START 0x08 | |
165 | #define CTX_RING_BUFFER_CONTROL 0x0a | |
166 | #define CTX_BB_HEAD_U 0x0c | |
167 | #define CTX_BB_HEAD_L 0x0e | |
168 | #define CTX_BB_STATE 0x10 | |
169 | #define CTX_SECOND_BB_HEAD_U 0x12 | |
170 | #define CTX_SECOND_BB_HEAD_L 0x14 | |
171 | #define CTX_SECOND_BB_STATE 0x16 | |
172 | #define CTX_BB_PER_CTX_PTR 0x18 | |
173 | #define CTX_RCS_INDIRECT_CTX 0x1a | |
174 | #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c | |
175 | #define CTX_LRI_HEADER_1 0x21 | |
176 | #define CTX_CTX_TIMESTAMP 0x22 | |
177 | #define CTX_PDP3_UDW 0x24 | |
178 | #define CTX_PDP3_LDW 0x26 | |
179 | #define CTX_PDP2_UDW 0x28 | |
180 | #define CTX_PDP2_LDW 0x2a | |
181 | #define CTX_PDP1_UDW 0x2c | |
182 | #define CTX_PDP1_LDW 0x2e | |
183 | #define CTX_PDP0_UDW 0x30 | |
184 | #define CTX_PDP0_LDW 0x32 | |
185 | #define CTX_LRI_HEADER_2 0x41 | |
186 | #define CTX_R_PWR_CLK_STATE 0x42 | |
187 | #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 | |
188 | ||
56e51bf0 | 189 | #define CTX_REG(reg_state, pos, reg, val) do { \ |
f0f59a00 | 190 | (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \ |
0d925ea0 VS |
191 | (reg_state)[(pos)+1] = (val); \ |
192 | } while (0) | |
193 | ||
194 | #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \ | |
d852c7bf | 195 | const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \ |
e5815a2e MT |
196 | reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \ |
197 | reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \ | |
9244a817 | 198 | } while (0) |
e5815a2e | 199 | |
9244a817 | 200 | #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \ |
2dba3239 MT |
201 | reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \ |
202 | reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \ | |
9244a817 | 203 | } while (0) |
2dba3239 | 204 | |
71562919 MT |
205 | #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 |
206 | #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26 | |
7bd0a2c6 | 207 | #define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x19 |
84b790f8 | 208 | |
0e93cdd4 CW |
209 | /* Typical size of the average request (2 pipecontrols and a MI_BB) */ |
210 | #define EXECLISTS_REQUEST_SIZE 64 /* bytes */ | |
211 | ||
a3aabe86 CW |
212 | #define WA_TAIL_DWORDS 2 |
213 | ||
e2efd130 | 214 | static int execlists_context_deferred_alloc(struct i915_gem_context *ctx, |
978f1e09 | 215 | struct intel_engine_cs *engine); |
a3aabe86 CW |
216 | static void execlists_init_reg_state(u32 *reg_state, |
217 | struct i915_gem_context *ctx, | |
218 | struct intel_engine_cs *engine, | |
219 | struct intel_ring *ring); | |
7ba717cf | 220 | |
73e4d07f OM |
221 | /** |
222 | * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists | |
14bb2c11 | 223 | * @dev_priv: i915 device private |
73e4d07f OM |
224 | * @enable_execlists: value of i915.enable_execlists module parameter. |
225 | * | |
226 | * Only certain platforms support Execlists (the prerequisites being | |
27401d12 | 227 | * support for Logical Ring Contexts and Aliasing PPGTT or better). |
73e4d07f OM |
228 | * |
229 | * Return: 1 if Execlists is supported and has to be enabled. | |
230 | */ | |
c033666a | 231 | int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv, int enable_execlists) |
127f1003 | 232 | { |
a0bd6c31 ZL |
233 | /* On platforms with execlist available, vGPU will only |
234 | * support execlist mode, no ring buffer mode. | |
235 | */ | |
c033666a | 236 | if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && intel_vgpu_active(dev_priv)) |
a0bd6c31 ZL |
237 | return 1; |
238 | ||
c033666a | 239 | if (INTEL_GEN(dev_priv) >= 9) |
70ee45e1 DL |
240 | return 1; |
241 | ||
127f1003 OM |
242 | if (enable_execlists == 0) |
243 | return 0; | |
244 | ||
5a21b665 DV |
245 | if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && |
246 | USES_PPGTT(dev_priv) && | |
247 | i915.use_mmio_flip >= 0) | |
127f1003 OM |
248 | return 1; |
249 | ||
250 | return 0; | |
251 | } | |
ede7d42b | 252 | |
73e4d07f | 253 | /** |
ca82580c TU |
254 | * intel_lr_context_descriptor_update() - calculate & cache the descriptor |
255 | * descriptor for a pinned context | |
ca82580c | 256 | * @ctx: Context to work on |
9021ad03 | 257 | * @engine: Engine the descriptor will be used with |
73e4d07f | 258 | * |
ca82580c TU |
259 | * The context descriptor encodes various attributes of a context, |
260 | * including its GTT address and some flags. Because it's fairly | |
261 | * expensive to calculate, we'll just do it once and cache the result, | |
262 | * which remains valid until the context is unpinned. | |
263 | * | |
6e5248b5 DV |
264 | * This is what a descriptor looks like, from LSB to MSB:: |
265 | * | |
2355cf08 | 266 | * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template) |
6e5248b5 DV |
267 | * bits 12-31: LRCA, GTT address of (the HWSP of) this context |
268 | * bits 32-52: ctx ID, a globally unique tag | |
269 | * bits 53-54: mbz, reserved for use by hardware | |
270 | * bits 55-63: group ID, currently unused and set to 0 | |
73e4d07f | 271 | */ |
ca82580c | 272 | static void |
e2efd130 | 273 | intel_lr_context_descriptor_update(struct i915_gem_context *ctx, |
0bc40be8 | 274 | struct intel_engine_cs *engine) |
84b790f8 | 275 | { |
9021ad03 | 276 | struct intel_context *ce = &ctx->engine[engine->id]; |
7069b144 | 277 | u64 desc; |
84b790f8 | 278 | |
7069b144 | 279 | BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH)); |
84b790f8 | 280 | |
2355cf08 | 281 | desc = ctx->desc_template; /* bits 0-11 */ |
bde13ebd | 282 | desc |= i915_ggtt_offset(ce->state) + LRC_PPHWSP_PN * PAGE_SIZE; |
9021ad03 | 283 | /* bits 12-31 */ |
7069b144 | 284 | desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */ |
5af05fef | 285 | |
9021ad03 | 286 | ce->lrc_desc = desc; |
5af05fef MT |
287 | } |
288 | ||
e2efd130 | 289 | uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx, |
0bc40be8 | 290 | struct intel_engine_cs *engine) |
84b790f8 | 291 | { |
0bc40be8 | 292 | return ctx->engine[engine->id].lrc_desc; |
ca82580c | 293 | } |
203a571b | 294 | |
bbd6c47e CW |
295 | static inline void |
296 | execlists_context_status_change(struct drm_i915_gem_request *rq, | |
297 | unsigned long status) | |
84b790f8 | 298 | { |
bbd6c47e CW |
299 | /* |
300 | * Only used when GVT-g is enabled now. When GVT-g is disabled, | |
301 | * The compiler should eliminate this function as dead-code. | |
302 | */ | |
303 | if (!IS_ENABLED(CONFIG_DRM_I915_GVT)) | |
304 | return; | |
6daccb0b | 305 | |
3fc03069 CD |
306 | atomic_notifier_call_chain(&rq->engine->context_status_notifier, |
307 | status, rq); | |
84b790f8 BW |
308 | } |
309 | ||
c6a2ac71 TU |
310 | static void |
311 | execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state) | |
312 | { | |
313 | ASSIGN_CTX_PDP(ppgtt, reg_state, 3); | |
314 | ASSIGN_CTX_PDP(ppgtt, reg_state, 2); | |
315 | ASSIGN_CTX_PDP(ppgtt, reg_state, 1); | |
316 | ASSIGN_CTX_PDP(ppgtt, reg_state, 0); | |
317 | } | |
318 | ||
70c2a24d | 319 | static u64 execlists_update_context(struct drm_i915_gem_request *rq) |
ae1250b9 | 320 | { |
70c2a24d | 321 | struct intel_context *ce = &rq->ctx->engine[rq->engine->id]; |
04da811b ZW |
322 | struct i915_hw_ppgtt *ppgtt = |
323 | rq->ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt; | |
70c2a24d | 324 | u32 *reg_state = ce->lrc_reg_state; |
ae1250b9 | 325 | |
e6ba9992 | 326 | reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail); |
ae1250b9 | 327 | |
c6a2ac71 TU |
328 | /* True 32b PPGTT with dynamic page allocation: update PDP |
329 | * registers and point the unallocated PDPs to scratch page. | |
330 | * PML4 is allocated during ppgtt init, so this is not needed | |
331 | * in 48-bit mode. | |
332 | */ | |
949e8ab3 | 333 | if (ppgtt && !i915_vm_is_48bit(&ppgtt->base)) |
c6a2ac71 | 334 | execlists_update_context_pdps(ppgtt, reg_state); |
70c2a24d CW |
335 | |
336 | return ce->lrc_desc; | |
ae1250b9 OM |
337 | } |
338 | ||
70c2a24d | 339 | static void execlists_submit_ports(struct intel_engine_cs *engine) |
bbd6c47e | 340 | { |
70c2a24d | 341 | struct execlist_port *port = engine->execlist_port; |
bbd6c47e | 342 | u32 __iomem *elsp = |
77f0d0e9 CW |
343 | engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine)); |
344 | unsigned int n; | |
bbd6c47e | 345 | |
77f0d0e9 CW |
346 | for (n = ARRAY_SIZE(engine->execlist_port); n--; ) { |
347 | struct drm_i915_gem_request *rq; | |
348 | unsigned int count; | |
349 | u64 desc; | |
350 | ||
351 | rq = port_unpack(&port[n], &count); | |
352 | if (rq) { | |
353 | GEM_BUG_ON(count > !n); | |
354 | if (!count++) | |
355 | execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN); | |
356 | port_set(&port[n], port_pack(rq, count)); | |
357 | desc = execlists_update_context(rq); | |
358 | GEM_DEBUG_EXEC(port[n].context_id = upper_32_bits(desc)); | |
359 | } else { | |
360 | GEM_BUG_ON(!n); | |
361 | desc = 0; | |
362 | } | |
bbd6c47e | 363 | |
77f0d0e9 CW |
364 | writel(upper_32_bits(desc), elsp); |
365 | writel(lower_32_bits(desc), elsp); | |
366 | } | |
bbd6c47e CW |
367 | } |
368 | ||
70c2a24d | 369 | static bool ctx_single_port_submission(const struct i915_gem_context *ctx) |
84b790f8 | 370 | { |
70c2a24d | 371 | return (IS_ENABLED(CONFIG_DRM_I915_GVT) && |
6095868a | 372 | i915_gem_context_force_single_submission(ctx)); |
70c2a24d | 373 | } |
84b790f8 | 374 | |
70c2a24d CW |
375 | static bool can_merge_ctx(const struct i915_gem_context *prev, |
376 | const struct i915_gem_context *next) | |
377 | { | |
378 | if (prev != next) | |
379 | return false; | |
26720ab9 | 380 | |
70c2a24d CW |
381 | if (ctx_single_port_submission(prev)) |
382 | return false; | |
26720ab9 | 383 | |
70c2a24d | 384 | return true; |
84b790f8 BW |
385 | } |
386 | ||
77f0d0e9 CW |
387 | static void port_assign(struct execlist_port *port, |
388 | struct drm_i915_gem_request *rq) | |
389 | { | |
390 | GEM_BUG_ON(rq == port_request(port)); | |
391 | ||
392 | if (port_isset(port)) | |
393 | i915_gem_request_put(port_request(port)); | |
394 | ||
395 | port_set(port, port_pack(i915_gem_request_get(rq), port_count(port))); | |
396 | } | |
397 | ||
70c2a24d | 398 | static void execlists_dequeue(struct intel_engine_cs *engine) |
acdd884a | 399 | { |
20311bd3 | 400 | struct drm_i915_gem_request *last; |
70c2a24d | 401 | struct execlist_port *port = engine->execlist_port; |
20311bd3 | 402 | struct rb_node *rb; |
70c2a24d CW |
403 | bool submit = false; |
404 | ||
77f0d0e9 | 405 | last = port_request(port); |
70c2a24d CW |
406 | if (last) |
407 | /* WaIdleLiteRestore:bdw,skl | |
408 | * Apply the wa NOOPs to prevent ring:HEAD == req:TAIL | |
9b81d556 | 409 | * as we resubmit the request. See gen8_emit_breadcrumb() |
70c2a24d CW |
410 | * for where we prepare the padding after the end of the |
411 | * request. | |
412 | */ | |
413 | last->tail = last->wa_tail; | |
e981e7b1 | 414 | |
77f0d0e9 | 415 | GEM_BUG_ON(port_isset(&port[1])); |
acdd884a | 416 | |
70c2a24d CW |
417 | /* Hardware submission is through 2 ports. Conceptually each port |
418 | * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is | |
419 | * static for a context, and unique to each, so we only execute | |
420 | * requests belonging to a single context from each ring. RING_HEAD | |
421 | * is maintained by the CS in the context image, it marks the place | |
422 | * where it got up to last time, and through RING_TAIL we tell the CS | |
423 | * where we want to execute up to this time. | |
424 | * | |
425 | * In this list the requests are in order of execution. Consecutive | |
426 | * requests from the same context are adjacent in the ringbuffer. We | |
427 | * can combine these requests into a single RING_TAIL update: | |
428 | * | |
429 | * RING_HEAD...req1...req2 | |
430 | * ^- RING_TAIL | |
431 | * since to execute req2 the CS must first execute req1. | |
432 | * | |
433 | * Our goal then is to point each port to the end of a consecutive | |
434 | * sequence of requests as being the most optimal (fewest wake ups | |
435 | * and context switches) submission. | |
779949f4 | 436 | */ |
acdd884a | 437 | |
9f7886d0 | 438 | spin_lock_irq(&engine->timeline->lock); |
20311bd3 | 439 | rb = engine->execlist_first; |
6c067579 | 440 | GEM_BUG_ON(rb_first(&engine->execlist_queue) != rb); |
20311bd3 | 441 | while (rb) { |
6c067579 CW |
442 | struct i915_priolist *p = rb_entry(rb, typeof(*p), node); |
443 | struct drm_i915_gem_request *rq, *rn; | |
444 | ||
445 | list_for_each_entry_safe(rq, rn, &p->requests, priotree.link) { | |
446 | /* | |
447 | * Can we combine this request with the current port? | |
448 | * It has to be the same context/ringbuffer and not | |
449 | * have any exceptions (e.g. GVT saying never to | |
450 | * combine contexts). | |
451 | * | |
452 | * If we can combine the requests, we can execute both | |
453 | * by updating the RING_TAIL to point to the end of the | |
454 | * second request, and so we never need to tell the | |
455 | * hardware about the first. | |
70c2a24d | 456 | */ |
6c067579 CW |
457 | if (last && !can_merge_ctx(rq->ctx, last->ctx)) { |
458 | /* | |
459 | * If we are on the second port and cannot | |
460 | * combine this request with the last, then we | |
461 | * are done. | |
462 | */ | |
463 | if (port != engine->execlist_port) { | |
464 | __list_del_many(&p->requests, | |
465 | &rq->priotree.link); | |
466 | goto done; | |
467 | } | |
468 | ||
469 | /* | |
470 | * If GVT overrides us we only ever submit | |
471 | * port[0], leaving port[1] empty. Note that we | |
472 | * also have to be careful that we don't queue | |
473 | * the same context (even though a different | |
474 | * request) to the second port. | |
475 | */ | |
476 | if (ctx_single_port_submission(last->ctx) || | |
477 | ctx_single_port_submission(rq->ctx)) { | |
478 | __list_del_many(&p->requests, | |
479 | &rq->priotree.link); | |
480 | goto done; | |
481 | } | |
482 | ||
483 | GEM_BUG_ON(last->ctx == rq->ctx); | |
484 | ||
485 | if (submit) | |
486 | port_assign(port, last); | |
487 | port++; | |
488 | } | |
70c2a24d | 489 | |
6c067579 CW |
490 | INIT_LIST_HEAD(&rq->priotree.link); |
491 | rq->priotree.priority = INT_MAX; | |
70c2a24d | 492 | |
6c067579 CW |
493 | __i915_gem_request_submit(rq); |
494 | trace_i915_gem_request_in(rq, port_index(port, engine)); | |
495 | last = rq; | |
496 | submit = true; | |
70c2a24d | 497 | } |
d55ac5bf | 498 | |
20311bd3 | 499 | rb = rb_next(rb); |
6c067579 CW |
500 | rb_erase(&p->node, &engine->execlist_queue); |
501 | INIT_LIST_HEAD(&p->requests); | |
502 | if (p->priority != I915_PRIORITY_NORMAL) | |
c5cf9a91 | 503 | kmem_cache_free(engine->i915->priorities, p); |
70c2a24d | 504 | } |
6c067579 CW |
505 | done: |
506 | engine->execlist_first = rb; | |
507 | if (submit) | |
77f0d0e9 | 508 | port_assign(port, last); |
9f7886d0 | 509 | spin_unlock_irq(&engine->timeline->lock); |
53292cdb | 510 | |
70c2a24d CW |
511 | if (submit) |
512 | execlists_submit_ports(engine); | |
acdd884a MT |
513 | } |
514 | ||
816ee798 | 515 | static bool execlists_elsp_ready(const struct intel_engine_cs *engine) |
91a41032 | 516 | { |
816ee798 | 517 | const struct execlist_port *port = engine->execlist_port; |
91a41032 | 518 | |
77f0d0e9 | 519 | return port_count(&port[0]) + port_count(&port[1]) < 2; |
91a41032 BW |
520 | } |
521 | ||
6e5248b5 | 522 | /* |
73e4d07f OM |
523 | * Check the unread Context Status Buffers and manage the submission of new |
524 | * contexts to the ELSP accordingly. | |
525 | */ | |
27af5eea | 526 | static void intel_lrc_irq_handler(unsigned long data) |
e981e7b1 | 527 | { |
27af5eea | 528 | struct intel_engine_cs *engine = (struct intel_engine_cs *)data; |
70c2a24d | 529 | struct execlist_port *port = engine->execlist_port; |
c033666a | 530 | struct drm_i915_private *dev_priv = engine->i915; |
c6a2ac71 | 531 | |
48921260 CW |
532 | /* We can skip acquiring intel_runtime_pm_get() here as it was taken |
533 | * on our behalf by the request (see i915_gem_mark_busy()) and it will | |
534 | * not be relinquished until the device is idle (see | |
535 | * i915_gem_idle_work_handler()). As a precaution, we make sure | |
536 | * that all ELSP are drained i.e. we have processed the CSB, | |
537 | * before allowing ourselves to idle and calling intel_runtime_pm_put(). | |
538 | */ | |
539 | GEM_BUG_ON(!dev_priv->gt.awake); | |
540 | ||
3756685a | 541 | intel_uncore_forcewake_get(dev_priv, engine->fw_domains); |
c6a2ac71 | 542 | |
899f6204 CW |
543 | /* Prefer doing test_and_clear_bit() as a two stage operation to avoid |
544 | * imposing the cost of a locked atomic transaction when submitting a | |
545 | * new request (outside of the context-switch interrupt). | |
546 | */ | |
547 | while (test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) { | |
70c2a24d CW |
548 | u32 __iomem *csb_mmio = |
549 | dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)); | |
550 | u32 __iomem *buf = | |
551 | dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)); | |
4af0d727 | 552 | unsigned int head, tail; |
70c2a24d | 553 | |
2e70b8c6 CW |
554 | /* The write will be ordered by the uncached read (itself |
555 | * a memory barrier), so we do not need another in the form | |
556 | * of a locked instruction. The race between the interrupt | |
557 | * handler and the split test/clear is harmless as we order | |
558 | * our clear before the CSB read. If the interrupt arrived | |
559 | * first between the test and the clear, we read the updated | |
560 | * CSB and clear the bit. If the interrupt arrives as we read | |
561 | * the CSB or later (i.e. after we had cleared the bit) the bit | |
562 | * is set and we do a new loop. | |
563 | */ | |
564 | __clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); | |
4af0d727 CW |
565 | head = readl(csb_mmio); |
566 | tail = GEN8_CSB_WRITE_PTR(head); | |
567 | head = GEN8_CSB_READ_PTR(head); | |
568 | while (head != tail) { | |
77f0d0e9 | 569 | struct drm_i915_gem_request *rq; |
4af0d727 | 570 | unsigned int status; |
77f0d0e9 | 571 | unsigned int count; |
4af0d727 CW |
572 | |
573 | if (++head == GEN8_CSB_ENTRIES) | |
574 | head = 0; | |
70c2a24d | 575 | |
2ffe80aa CW |
576 | /* We are flying near dragons again. |
577 | * | |
578 | * We hold a reference to the request in execlist_port[] | |
579 | * but no more than that. We are operating in softirq | |
580 | * context and so cannot hold any mutex or sleep. That | |
581 | * prevents us stopping the requests we are processing | |
582 | * in port[] from being retired simultaneously (the | |
583 | * breadcrumb will be complete before we see the | |
584 | * context-switch). As we only hold the reference to the | |
585 | * request, any pointer chasing underneath the request | |
586 | * is subject to a potential use-after-free. Thus we | |
587 | * store all of the bookkeeping within port[] as | |
588 | * required, and avoid using unguarded pointers beneath | |
589 | * request itself. The same applies to the atomic | |
590 | * status notifier. | |
591 | */ | |
592 | ||
4af0d727 | 593 | status = readl(buf + 2 * head); |
70c2a24d CW |
594 | if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK)) |
595 | continue; | |
596 | ||
86aa7e76 | 597 | /* Check the context/desc id for this event matches */ |
4af0d727 | 598 | GEM_DEBUG_BUG_ON(readl(buf + 2 * head + 1) != |
77f0d0e9 | 599 | port->context_id); |
86aa7e76 | 600 | |
77f0d0e9 CW |
601 | rq = port_unpack(port, &count); |
602 | GEM_BUG_ON(count == 0); | |
603 | if (--count == 0) { | |
70c2a24d | 604 | GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED); |
77f0d0e9 CW |
605 | GEM_BUG_ON(!i915_gem_request_completed(rq)); |
606 | execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT); | |
607 | ||
608 | trace_i915_gem_request_out(rq); | |
609 | i915_gem_request_put(rq); | |
70c2a24d | 610 | |
70c2a24d CW |
611 | port[0] = port[1]; |
612 | memset(&port[1], 0, sizeof(port[1])); | |
77f0d0e9 CW |
613 | } else { |
614 | port_set(port, port_pack(rq, count)); | |
70c2a24d | 615 | } |
26720ab9 | 616 | |
77f0d0e9 CW |
617 | /* After the final element, the hw should be idle */ |
618 | GEM_BUG_ON(port_count(port) == 0 && | |
70c2a24d | 619 | !(status & GEN8_CTX_STATUS_ACTIVE_IDLE)); |
4af0d727 | 620 | } |
e1fee72c | 621 | |
4af0d727 | 622 | writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, head << 8), |
70c2a24d | 623 | csb_mmio); |
e981e7b1 TD |
624 | } |
625 | ||
70c2a24d CW |
626 | if (execlists_elsp_ready(engine)) |
627 | execlists_dequeue(engine); | |
c6a2ac71 | 628 | |
70c2a24d | 629 | intel_uncore_forcewake_put(dev_priv, engine->fw_domains); |
e981e7b1 TD |
630 | } |
631 | ||
6c067579 CW |
632 | static bool |
633 | insert_request(struct intel_engine_cs *engine, | |
634 | struct i915_priotree *pt, | |
635 | int prio) | |
20311bd3 | 636 | { |
6c067579 CW |
637 | struct i915_priolist *p; |
638 | struct rb_node **parent, *rb; | |
20311bd3 CW |
639 | bool first = true; |
640 | ||
6c067579 CW |
641 | if (unlikely(engine->no_priolist)) |
642 | prio = I915_PRIORITY_NORMAL; | |
643 | ||
644 | find_priolist: | |
20311bd3 CW |
645 | /* most positive priority is scheduled first, equal priorities fifo */ |
646 | rb = NULL; | |
6c067579 CW |
647 | parent = &engine->execlist_queue.rb_node; |
648 | while (*parent) { | |
649 | rb = *parent; | |
650 | p = rb_entry(rb, typeof(*p), node); | |
651 | if (prio > p->priority) { | |
652 | parent = &rb->rb_left; | |
653 | } else if (prio < p->priority) { | |
654 | parent = &rb->rb_right; | |
20311bd3 | 655 | first = false; |
6c067579 CW |
656 | } else { |
657 | list_add_tail(&pt->link, &p->requests); | |
658 | return false; | |
20311bd3 CW |
659 | } |
660 | } | |
6c067579 CW |
661 | |
662 | if (prio == I915_PRIORITY_NORMAL) { | |
663 | p = &engine->default_priolist; | |
664 | } else { | |
c5cf9a91 | 665 | p = kmem_cache_alloc(engine->i915->priorities, GFP_ATOMIC); |
6c067579 CW |
666 | /* Convert an allocation failure to a priority bump */ |
667 | if (unlikely(!p)) { | |
668 | prio = I915_PRIORITY_NORMAL; /* recurses just once */ | |
669 | ||
670 | /* To maintain ordering with all rendering, after an | |
671 | * allocation failure we have to disable all scheduling. | |
672 | * Requests will then be executed in fifo, and schedule | |
673 | * will ensure that dependencies are emitted in fifo. | |
674 | * There will be still some reordering with existing | |
675 | * requests, so if userspace lied about their | |
676 | * dependencies that reordering may be visible. | |
677 | */ | |
678 | engine->no_priolist = true; | |
679 | goto find_priolist; | |
680 | } | |
681 | } | |
682 | ||
683 | p->priority = prio; | |
684 | rb_link_node(&p->node, rb, parent); | |
685 | rb_insert_color(&p->node, &engine->execlist_queue); | |
686 | ||
687 | INIT_LIST_HEAD(&p->requests); | |
688 | list_add_tail(&pt->link, &p->requests); | |
689 | ||
690 | if (first) | |
691 | engine->execlist_first = &p->node; | |
20311bd3 CW |
692 | |
693 | return first; | |
694 | } | |
695 | ||
f4ea6bdd | 696 | static void execlists_submit_request(struct drm_i915_gem_request *request) |
acdd884a | 697 | { |
4a570db5 | 698 | struct intel_engine_cs *engine = request->engine; |
5590af3e | 699 | unsigned long flags; |
acdd884a | 700 | |
663f71e7 CW |
701 | /* Will be called from irq-context when using foreign fences. */ |
702 | spin_lock_irqsave(&engine->timeline->lock, flags); | |
acdd884a | 703 | |
6c067579 CW |
704 | if (insert_request(engine, |
705 | &request->priotree, | |
706 | request->priotree.priority)) { | |
48ea2554 | 707 | if (execlists_elsp_ready(engine)) |
3833281a CW |
708 | tasklet_hi_schedule(&engine->irq_tasklet); |
709 | } | |
acdd884a | 710 | |
6c067579 CW |
711 | GEM_BUG_ON(!engine->execlist_first); |
712 | GEM_BUG_ON(list_empty(&request->priotree.link)); | |
713 | ||
663f71e7 | 714 | spin_unlock_irqrestore(&engine->timeline->lock, flags); |
acdd884a MT |
715 | } |
716 | ||
20311bd3 CW |
717 | static struct intel_engine_cs * |
718 | pt_lock_engine(struct i915_priotree *pt, struct intel_engine_cs *locked) | |
719 | { | |
a79a524e CW |
720 | struct intel_engine_cs *engine = |
721 | container_of(pt, struct drm_i915_gem_request, priotree)->engine; | |
722 | ||
723 | GEM_BUG_ON(!locked); | |
20311bd3 | 724 | |
20311bd3 | 725 | if (engine != locked) { |
a79a524e CW |
726 | spin_unlock(&locked->timeline->lock); |
727 | spin_lock(&engine->timeline->lock); | |
20311bd3 CW |
728 | } |
729 | ||
730 | return engine; | |
731 | } | |
732 | ||
733 | static void execlists_schedule(struct drm_i915_gem_request *request, int prio) | |
734 | { | |
a79a524e | 735 | struct intel_engine_cs *engine; |
20311bd3 CW |
736 | struct i915_dependency *dep, *p; |
737 | struct i915_dependency stack; | |
738 | LIST_HEAD(dfs); | |
739 | ||
740 | if (prio <= READ_ONCE(request->priotree.priority)) | |
741 | return; | |
742 | ||
70cd1476 CW |
743 | /* Need BKL in order to use the temporary link inside i915_dependency */ |
744 | lockdep_assert_held(&request->i915->drm.struct_mutex); | |
20311bd3 CW |
745 | |
746 | stack.signaler = &request->priotree; | |
747 | list_add(&stack.dfs_link, &dfs); | |
748 | ||
749 | /* Recursively bump all dependent priorities to match the new request. | |
750 | * | |
751 | * A naive approach would be to use recursion: | |
752 | * static void update_priorities(struct i915_priotree *pt, prio) { | |
753 | * list_for_each_entry(dep, &pt->signalers_list, signal_link) | |
754 | * update_priorities(dep->signal, prio) | |
755 | * insert_request(pt); | |
756 | * } | |
757 | * but that may have unlimited recursion depth and so runs a very | |
758 | * real risk of overunning the kernel stack. Instead, we build | |
759 | * a flat list of all dependencies starting with the current request. | |
760 | * As we walk the list of dependencies, we add all of its dependencies | |
761 | * to the end of the list (this may include an already visited | |
762 | * request) and continue to walk onwards onto the new dependencies. The | |
763 | * end result is a topological list of requests in reverse order, the | |
764 | * last element in the list is the request we must execute first. | |
765 | */ | |
766 | list_for_each_entry_safe(dep, p, &dfs, dfs_link) { | |
767 | struct i915_priotree *pt = dep->signaler; | |
768 | ||
a79a524e CW |
769 | /* Within an engine, there can be no cycle, but we may |
770 | * refer to the same dependency chain multiple times | |
771 | * (redundant dependencies are not eliminated) and across | |
772 | * engines. | |
773 | */ | |
774 | list_for_each_entry(p, &pt->signalers_list, signal_link) { | |
775 | GEM_BUG_ON(p->signaler->priority < pt->priority); | |
20311bd3 CW |
776 | if (prio > READ_ONCE(p->signaler->priority)) |
777 | list_move_tail(&p->dfs_link, &dfs); | |
a79a524e | 778 | } |
20311bd3 | 779 | |
0798cff4 | 780 | list_safe_reset_next(dep, p, dfs_link); |
20311bd3 CW |
781 | } |
782 | ||
349bdb68 CW |
783 | /* If we didn't need to bump any existing priorities, and we haven't |
784 | * yet submitted this request (i.e. there is no potential race with | |
785 | * execlists_submit_request()), we can set our own priority and skip | |
786 | * acquiring the engine locks. | |
787 | */ | |
788 | if (request->priotree.priority == INT_MIN) { | |
789 | GEM_BUG_ON(!list_empty(&request->priotree.link)); | |
790 | request->priotree.priority = prio; | |
791 | if (stack.dfs_link.next == stack.dfs_link.prev) | |
792 | return; | |
793 | __list_del_entry(&stack.dfs_link); | |
794 | } | |
795 | ||
a79a524e CW |
796 | engine = request->engine; |
797 | spin_lock_irq(&engine->timeline->lock); | |
798 | ||
20311bd3 CW |
799 | /* Fifo and depth-first replacement ensure our deps execute before us */ |
800 | list_for_each_entry_safe_reverse(dep, p, &dfs, dfs_link) { | |
801 | struct i915_priotree *pt = dep->signaler; | |
802 | ||
803 | INIT_LIST_HEAD(&dep->dfs_link); | |
804 | ||
805 | engine = pt_lock_engine(pt, engine); | |
806 | ||
807 | if (prio <= pt->priority) | |
808 | continue; | |
809 | ||
20311bd3 | 810 | pt->priority = prio; |
6c067579 CW |
811 | if (!list_empty(&pt->link)) { |
812 | __list_del_entry(&pt->link); | |
813 | insert_request(engine, pt, prio); | |
a79a524e | 814 | } |
20311bd3 CW |
815 | } |
816 | ||
a79a524e | 817 | spin_unlock_irq(&engine->timeline->lock); |
20311bd3 CW |
818 | |
819 | /* XXX Do we need to preempt to make room for us and our deps? */ | |
820 | } | |
821 | ||
266a240b CW |
822 | static struct intel_ring * |
823 | execlists_context_pin(struct intel_engine_cs *engine, | |
824 | struct i915_gem_context *ctx) | |
dcb4c12a | 825 | { |
9021ad03 | 826 | struct intel_context *ce = &ctx->engine[engine->id]; |
2947e408 | 827 | unsigned int flags; |
7d774cac | 828 | void *vaddr; |
ca82580c | 829 | int ret; |
dcb4c12a | 830 | |
91c8a326 | 831 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
ca82580c | 832 | |
266a240b CW |
833 | if (likely(ce->pin_count++)) |
834 | goto out; | |
a533b4ba | 835 | GEM_BUG_ON(!ce->pin_count); /* no overflow please! */ |
24f1d3cc | 836 | |
e8a9c58f CW |
837 | if (!ce->state) { |
838 | ret = execlists_context_deferred_alloc(ctx, engine); | |
839 | if (ret) | |
840 | goto err; | |
841 | } | |
56f6e0a7 | 842 | GEM_BUG_ON(!ce->state); |
e8a9c58f | 843 | |
72b72ae4 | 844 | flags = PIN_GLOBAL | PIN_HIGH; |
feef2a7c DCS |
845 | if (ctx->ggtt_offset_bias) |
846 | flags |= PIN_OFFSET_BIAS | ctx->ggtt_offset_bias; | |
2947e408 CW |
847 | |
848 | ret = i915_vma_pin(ce->state, 0, GEN8_LR_CONTEXT_ALIGN, flags); | |
e84fe803 | 849 | if (ret) |
24f1d3cc | 850 | goto err; |
7ba717cf | 851 | |
bf3783e5 | 852 | vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB); |
7d774cac TU |
853 | if (IS_ERR(vaddr)) { |
854 | ret = PTR_ERR(vaddr); | |
bf3783e5 | 855 | goto unpin_vma; |
82352e90 TU |
856 | } |
857 | ||
d822bb18 | 858 | ret = intel_ring_pin(ce->ring, ctx->i915, ctx->ggtt_offset_bias); |
e84fe803 | 859 | if (ret) |
7d774cac | 860 | goto unpin_map; |
d1675198 | 861 | |
0bc40be8 | 862 | intel_lr_context_descriptor_update(ctx, engine); |
9021ad03 | 863 | |
a3aabe86 CW |
864 | ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; |
865 | ce->lrc_reg_state[CTX_RING_BUFFER_START+1] = | |
bde13ebd | 866 | i915_ggtt_offset(ce->ring->vma); |
a3aabe86 | 867 | |
a4f5ea64 | 868 | ce->state->obj->mm.dirty = true; |
e93c28f3 | 869 | |
9a6feaf0 | 870 | i915_gem_context_get(ctx); |
266a240b CW |
871 | out: |
872 | return ce->ring; | |
7ba717cf | 873 | |
7d774cac | 874 | unpin_map: |
bf3783e5 CW |
875 | i915_gem_object_unpin_map(ce->state->obj); |
876 | unpin_vma: | |
877 | __i915_vma_unpin(ce->state); | |
24f1d3cc | 878 | err: |
9021ad03 | 879 | ce->pin_count = 0; |
266a240b | 880 | return ERR_PTR(ret); |
e84fe803 NH |
881 | } |
882 | ||
e8a9c58f CW |
883 | static void execlists_context_unpin(struct intel_engine_cs *engine, |
884 | struct i915_gem_context *ctx) | |
e84fe803 | 885 | { |
9021ad03 | 886 | struct intel_context *ce = &ctx->engine[engine->id]; |
e84fe803 | 887 | |
91c8a326 | 888 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
9021ad03 | 889 | GEM_BUG_ON(ce->pin_count == 0); |
321fe304 | 890 | |
9021ad03 | 891 | if (--ce->pin_count) |
24f1d3cc | 892 | return; |
e84fe803 | 893 | |
aad29fbb | 894 | intel_ring_unpin(ce->ring); |
dcb4c12a | 895 | |
bf3783e5 CW |
896 | i915_gem_object_unpin_map(ce->state->obj); |
897 | i915_vma_unpin(ce->state); | |
321fe304 | 898 | |
9a6feaf0 | 899 | i915_gem_context_put(ctx); |
dcb4c12a OM |
900 | } |
901 | ||
f73e7399 | 902 | static int execlists_request_alloc(struct drm_i915_gem_request *request) |
ef11c01d CW |
903 | { |
904 | struct intel_engine_cs *engine = request->engine; | |
905 | struct intel_context *ce = &request->ctx->engine[engine->id]; | |
73dec95e | 906 | u32 *cs; |
ef11c01d CW |
907 | int ret; |
908 | ||
e8a9c58f CW |
909 | GEM_BUG_ON(!ce->pin_count); |
910 | ||
ef11c01d CW |
911 | /* Flush enough space to reduce the likelihood of waiting after |
912 | * we start building the request - in which case we will just | |
913 | * have to repeat work. | |
914 | */ | |
915 | request->reserved_space += EXECLISTS_REQUEST_SIZE; | |
916 | ||
ef11c01d CW |
917 | if (i915.enable_guc_submission) { |
918 | /* | |
919 | * Check that the GuC has space for the request before | |
920 | * going any further, as the i915_add_request() call | |
921 | * later on mustn't fail ... | |
922 | */ | |
923 | ret = i915_guc_wq_reserve(request); | |
924 | if (ret) | |
e8a9c58f | 925 | goto err; |
ef11c01d CW |
926 | } |
927 | ||
73dec95e TU |
928 | cs = intel_ring_begin(request, 0); |
929 | if (IS_ERR(cs)) { | |
930 | ret = PTR_ERR(cs); | |
ef11c01d | 931 | goto err_unreserve; |
73dec95e | 932 | } |
ef11c01d CW |
933 | |
934 | if (!ce->initialised) { | |
935 | ret = engine->init_context(request); | |
936 | if (ret) | |
937 | goto err_unreserve; | |
938 | ||
939 | ce->initialised = true; | |
940 | } | |
941 | ||
942 | /* Note that after this point, we have committed to using | |
943 | * this request as it is being used to both track the | |
944 | * state of engine initialisation and liveness of the | |
945 | * golden renderstate above. Think twice before you try | |
946 | * to cancel/unwind this request now. | |
947 | */ | |
948 | ||
949 | request->reserved_space -= EXECLISTS_REQUEST_SIZE; | |
950 | return 0; | |
951 | ||
952 | err_unreserve: | |
953 | if (i915.enable_guc_submission) | |
954 | i915_guc_wq_unreserve(request); | |
e8a9c58f | 955 | err: |
ef11c01d CW |
956 | return ret; |
957 | } | |
958 | ||
9e000847 AS |
959 | /* |
960 | * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after | |
961 | * PIPE_CONTROL instruction. This is required for the flush to happen correctly | |
962 | * but there is a slight complication as this is applied in WA batch where the | |
963 | * values are only initialized once so we cannot take register value at the | |
964 | * beginning and reuse it further; hence we save its value to memory, upload a | |
965 | * constant value with bit21 set and then we restore it back with the saved value. | |
966 | * To simplify the WA, a constant value is formed by using the default value | |
967 | * of this register. This shouldn't be a problem because we are only modifying | |
968 | * it for a short period and this batch in non-premptible. We can ofcourse | |
969 | * use additional instructions that read the actual value of the register | |
970 | * at that time and set our bit of interest but it makes the WA complicated. | |
971 | * | |
972 | * This WA is also required for Gen9 so extracting as a function avoids | |
973 | * code duplication. | |
974 | */ | |
097d4f1c TU |
975 | static u32 * |
976 | gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch) | |
17ee950d | 977 | { |
097d4f1c TU |
978 | *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; |
979 | *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); | |
980 | *batch++ = i915_ggtt_offset(engine->scratch) + 256; | |
981 | *batch++ = 0; | |
982 | ||
983 | *batch++ = MI_LOAD_REGISTER_IMM(1); | |
984 | *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); | |
985 | *batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES; | |
986 | ||
9f235dfa TU |
987 | batch = gen8_emit_pipe_control(batch, |
988 | PIPE_CONTROL_CS_STALL | | |
989 | PIPE_CONTROL_DC_FLUSH_ENABLE, | |
990 | 0); | |
097d4f1c TU |
991 | |
992 | *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; | |
993 | *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); | |
994 | *batch++ = i915_ggtt_offset(engine->scratch) + 256; | |
995 | *batch++ = 0; | |
996 | ||
997 | return batch; | |
17ee950d AS |
998 | } |
999 | ||
6e5248b5 DV |
1000 | /* |
1001 | * Typically we only have one indirect_ctx and per_ctx batch buffer which are | |
1002 | * initialized at the beginning and shared across all contexts but this field | |
1003 | * helps us to have multiple batches at different offsets and select them based | |
1004 | * on a criteria. At the moment this batch always start at the beginning of the page | |
1005 | * and at this point we don't have multiple wa_ctx batch buffers. | |
4d78c8dc | 1006 | * |
6e5248b5 DV |
1007 | * The number of WA applied are not known at the beginning; we use this field |
1008 | * to return the no of DWORDS written. | |
17ee950d | 1009 | * |
6e5248b5 DV |
1010 | * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END |
1011 | * so it adds NOOPs as padding to make it cacheline aligned. | |
1012 | * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together | |
1013 | * makes a complete batch buffer. | |
17ee950d | 1014 | */ |
097d4f1c | 1015 | static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) |
17ee950d | 1016 | { |
7ad00d1a | 1017 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
097d4f1c | 1018 | *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; |
17ee950d | 1019 | |
c82435bb | 1020 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */ |
097d4f1c TU |
1021 | if (IS_BROADWELL(engine->i915)) |
1022 | batch = gen8_emit_flush_coherentl3_wa(engine, batch); | |
c82435bb | 1023 | |
0160f055 AS |
1024 | /* WaClearSlmSpaceAtContextSwitch:bdw,chv */ |
1025 | /* Actual scratch location is at 128 bytes offset */ | |
9f235dfa TU |
1026 | batch = gen8_emit_pipe_control(batch, |
1027 | PIPE_CONTROL_FLUSH_L3 | | |
1028 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1029 | PIPE_CONTROL_CS_STALL | | |
1030 | PIPE_CONTROL_QW_WRITE, | |
1031 | i915_ggtt_offset(engine->scratch) + | |
1032 | 2 * CACHELINE_BYTES); | |
0160f055 | 1033 | |
17ee950d | 1034 | /* Pad to end of cacheline */ |
097d4f1c TU |
1035 | while ((unsigned long)batch % CACHELINE_BYTES) |
1036 | *batch++ = MI_NOOP; | |
17ee950d AS |
1037 | |
1038 | /* | |
1039 | * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because | |
1040 | * execution depends on the length specified in terms of cache lines | |
1041 | * in the register CTX_RCS_INDIRECT_CTX | |
1042 | */ | |
1043 | ||
097d4f1c | 1044 | return batch; |
17ee950d AS |
1045 | } |
1046 | ||
6e5248b5 DV |
1047 | /* |
1048 | * This batch is started immediately after indirect_ctx batch. Since we ensure | |
1049 | * that indirect_ctx ends on a cacheline this batch is aligned automatically. | |
17ee950d | 1050 | * |
6e5248b5 | 1051 | * The number of DWORDS written are returned using this field. |
17ee950d AS |
1052 | * |
1053 | * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding | |
1054 | * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant. | |
1055 | */ | |
097d4f1c | 1056 | static u32 *gen8_init_perctx_bb(struct intel_engine_cs *engine, u32 *batch) |
17ee950d | 1057 | { |
7ad00d1a | 1058 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
097d4f1c TU |
1059 | *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; |
1060 | *batch++ = MI_BATCH_BUFFER_END; | |
17ee950d | 1061 | |
097d4f1c | 1062 | return batch; |
17ee950d AS |
1063 | } |
1064 | ||
097d4f1c | 1065 | static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) |
0504cffc | 1066 | { |
9fb5026f | 1067 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */ |
097d4f1c | 1068 | batch = gen8_emit_flush_coherentl3_wa(engine, batch); |
a4106a78 | 1069 | |
9fb5026f | 1070 | /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */ |
097d4f1c TU |
1071 | *batch++ = MI_LOAD_REGISTER_IMM(1); |
1072 | *batch++ = i915_mmio_reg_offset(COMMON_SLICE_CHICKEN2); | |
1073 | *batch++ = _MASKED_BIT_DISABLE( | |
1074 | GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE); | |
1075 | *batch++ = MI_NOOP; | |
873e8171 | 1076 | |
066d4628 MK |
1077 | /* WaClearSlmSpaceAtContextSwitch:kbl */ |
1078 | /* Actual scratch location is at 128 bytes offset */ | |
097d4f1c | 1079 | if (IS_KBL_REVID(engine->i915, 0, KBL_REVID_A0)) { |
9f235dfa TU |
1080 | batch = gen8_emit_pipe_control(batch, |
1081 | PIPE_CONTROL_FLUSH_L3 | | |
1082 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1083 | PIPE_CONTROL_CS_STALL | | |
1084 | PIPE_CONTROL_QW_WRITE, | |
1085 | i915_ggtt_offset(engine->scratch) | |
1086 | + 2 * CACHELINE_BYTES); | |
066d4628 | 1087 | } |
3485d99e | 1088 | |
9fb5026f | 1089 | /* WaMediaPoolStateCmdInWABB:bxt,glk */ |
3485d99e TG |
1090 | if (HAS_POOLED_EU(engine->i915)) { |
1091 | /* | |
1092 | * EU pool configuration is setup along with golden context | |
1093 | * during context initialization. This value depends on | |
1094 | * device type (2x6 or 3x6) and needs to be updated based | |
1095 | * on which subslice is disabled especially for 2x6 | |
1096 | * devices, however it is safe to load default | |
1097 | * configuration of 3x6 device instead of masking off | |
1098 | * corresponding bits because HW ignores bits of a disabled | |
1099 | * subslice and drops down to appropriate config. Please | |
1100 | * see render_state_setup() in i915_gem_render_state.c for | |
1101 | * possible configurations, to avoid duplication they are | |
1102 | * not shown here again. | |
1103 | */ | |
097d4f1c TU |
1104 | *batch++ = GEN9_MEDIA_POOL_STATE; |
1105 | *batch++ = GEN9_MEDIA_POOL_ENABLE; | |
1106 | *batch++ = 0x00777000; | |
1107 | *batch++ = 0; | |
1108 | *batch++ = 0; | |
1109 | *batch++ = 0; | |
3485d99e TG |
1110 | } |
1111 | ||
0504cffc | 1112 | /* Pad to end of cacheline */ |
097d4f1c TU |
1113 | while ((unsigned long)batch % CACHELINE_BYTES) |
1114 | *batch++ = MI_NOOP; | |
0504cffc | 1115 | |
097d4f1c | 1116 | return batch; |
0504cffc AS |
1117 | } |
1118 | ||
097d4f1c | 1119 | static u32 *gen9_init_perctx_bb(struct intel_engine_cs *engine, u32 *batch) |
0504cffc | 1120 | { |
097d4f1c | 1121 | *batch++ = MI_BATCH_BUFFER_END; |
0504cffc | 1122 | |
097d4f1c | 1123 | return batch; |
0504cffc AS |
1124 | } |
1125 | ||
097d4f1c TU |
1126 | #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE) |
1127 | ||
1128 | static int lrc_setup_wa_ctx(struct intel_engine_cs *engine) | |
17ee950d | 1129 | { |
48bb74e4 CW |
1130 | struct drm_i915_gem_object *obj; |
1131 | struct i915_vma *vma; | |
1132 | int err; | |
17ee950d | 1133 | |
097d4f1c | 1134 | obj = i915_gem_object_create(engine->i915, CTX_WA_BB_OBJ_SIZE); |
48bb74e4 CW |
1135 | if (IS_ERR(obj)) |
1136 | return PTR_ERR(obj); | |
17ee950d | 1137 | |
a01cb37a | 1138 | vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL); |
48bb74e4 CW |
1139 | if (IS_ERR(vma)) { |
1140 | err = PTR_ERR(vma); | |
1141 | goto err; | |
17ee950d AS |
1142 | } |
1143 | ||
48bb74e4 CW |
1144 | err = i915_vma_pin(vma, 0, PAGE_SIZE, PIN_GLOBAL | PIN_HIGH); |
1145 | if (err) | |
1146 | goto err; | |
1147 | ||
1148 | engine->wa_ctx.vma = vma; | |
17ee950d | 1149 | return 0; |
48bb74e4 CW |
1150 | |
1151 | err: | |
1152 | i915_gem_object_put(obj); | |
1153 | return err; | |
17ee950d AS |
1154 | } |
1155 | ||
097d4f1c | 1156 | static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine) |
17ee950d | 1157 | { |
19880c4a | 1158 | i915_vma_unpin_and_release(&engine->wa_ctx.vma); |
17ee950d AS |
1159 | } |
1160 | ||
097d4f1c TU |
1161 | typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch); |
1162 | ||
0bc40be8 | 1163 | static int intel_init_workaround_bb(struct intel_engine_cs *engine) |
17ee950d | 1164 | { |
48bb74e4 | 1165 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; |
097d4f1c TU |
1166 | struct i915_wa_ctx_bb *wa_bb[2] = { &wa_ctx->indirect_ctx, |
1167 | &wa_ctx->per_ctx }; | |
1168 | wa_bb_func_t wa_bb_fn[2]; | |
17ee950d | 1169 | struct page *page; |
097d4f1c TU |
1170 | void *batch, *batch_ptr; |
1171 | unsigned int i; | |
48bb74e4 | 1172 | int ret; |
17ee950d | 1173 | |
097d4f1c TU |
1174 | if (WARN_ON(engine->id != RCS || !engine->scratch)) |
1175 | return -EINVAL; | |
17ee950d | 1176 | |
097d4f1c TU |
1177 | switch (INTEL_GEN(engine->i915)) { |
1178 | case 9: | |
1179 | wa_bb_fn[0] = gen9_init_indirectctx_bb; | |
1180 | wa_bb_fn[1] = gen9_init_perctx_bb; | |
1181 | break; | |
1182 | case 8: | |
1183 | wa_bb_fn[0] = gen8_init_indirectctx_bb; | |
1184 | wa_bb_fn[1] = gen8_init_perctx_bb; | |
1185 | break; | |
1186 | default: | |
1187 | MISSING_CASE(INTEL_GEN(engine->i915)); | |
5e60d790 | 1188 | return 0; |
0504cffc | 1189 | } |
5e60d790 | 1190 | |
097d4f1c | 1191 | ret = lrc_setup_wa_ctx(engine); |
17ee950d AS |
1192 | if (ret) { |
1193 | DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret); | |
1194 | return ret; | |
1195 | } | |
1196 | ||
48bb74e4 | 1197 | page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0); |
097d4f1c | 1198 | batch = batch_ptr = kmap_atomic(page); |
17ee950d | 1199 | |
097d4f1c TU |
1200 | /* |
1201 | * Emit the two workaround batch buffers, recording the offset from the | |
1202 | * start of the workaround batch buffer object for each and their | |
1203 | * respective sizes. | |
1204 | */ | |
1205 | for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) { | |
1206 | wa_bb[i]->offset = batch_ptr - batch; | |
1207 | if (WARN_ON(!IS_ALIGNED(wa_bb[i]->offset, CACHELINE_BYTES))) { | |
1208 | ret = -EINVAL; | |
1209 | break; | |
1210 | } | |
1211 | batch_ptr = wa_bb_fn[i](engine, batch_ptr); | |
1212 | wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset); | |
17ee950d AS |
1213 | } |
1214 | ||
097d4f1c TU |
1215 | BUG_ON(batch_ptr - batch > CTX_WA_BB_OBJ_SIZE); |
1216 | ||
17ee950d AS |
1217 | kunmap_atomic(batch); |
1218 | if (ret) | |
097d4f1c | 1219 | lrc_destroy_wa_ctx(engine); |
17ee950d AS |
1220 | |
1221 | return ret; | |
1222 | } | |
1223 | ||
0bc40be8 | 1224 | static int gen8_init_common_ring(struct intel_engine_cs *engine) |
9b1136d5 | 1225 | { |
c033666a | 1226 | struct drm_i915_private *dev_priv = engine->i915; |
6b764a59 CW |
1227 | struct execlist_port *port = engine->execlist_port; |
1228 | unsigned int n; | |
77f0d0e9 | 1229 | bool submit; |
821ed7df CW |
1230 | int ret; |
1231 | ||
1232 | ret = intel_mocs_init_engine(engine); | |
1233 | if (ret) | |
1234 | return ret; | |
9b1136d5 | 1235 | |
ad07dfcd | 1236 | intel_engine_reset_breadcrumbs(engine); |
f3b8f912 | 1237 | intel_engine_init_hangcheck(engine); |
821ed7df | 1238 | |
0bc40be8 | 1239 | I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff); |
0bc40be8 | 1240 | I915_WRITE(RING_MODE_GEN7(engine), |
9b1136d5 | 1241 | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); |
f3b8f912 CW |
1242 | I915_WRITE(RING_HWS_PGA(engine->mmio_base), |
1243 | engine->status_page.ggtt_offset); | |
1244 | POSTING_READ(RING_HWS_PGA(engine->mmio_base)); | |
dfc53c5e | 1245 | |
0bc40be8 | 1246 | DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name); |
9b1136d5 | 1247 | |
c87d50cc | 1248 | /* After a GPU reset, we may have requests to replay */ |
f747026c | 1249 | clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); |
6b764a59 | 1250 | |
77f0d0e9 | 1251 | submit = false; |
6b764a59 | 1252 | for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++) { |
77f0d0e9 | 1253 | if (!port_isset(&port[n])) |
6b764a59 CW |
1254 | break; |
1255 | ||
1256 | DRM_DEBUG_DRIVER("Restarting %s:%d from 0x%x\n", | |
1257 | engine->name, n, | |
77f0d0e9 | 1258 | port_request(&port[n])->global_seqno); |
6b764a59 CW |
1259 | |
1260 | /* Discard the current inflight count */ | |
77f0d0e9 CW |
1261 | port_set(&port[n], port_request(&port[n])); |
1262 | submit = true; | |
c87d50cc | 1263 | } |
821ed7df | 1264 | |
77f0d0e9 | 1265 | if (submit && !i915.enable_guc_submission) |
6b764a59 CW |
1266 | execlists_submit_ports(engine); |
1267 | ||
821ed7df | 1268 | return 0; |
9b1136d5 OM |
1269 | } |
1270 | ||
0bc40be8 | 1271 | static int gen8_init_render_ring(struct intel_engine_cs *engine) |
9b1136d5 | 1272 | { |
c033666a | 1273 | struct drm_i915_private *dev_priv = engine->i915; |
9b1136d5 OM |
1274 | int ret; |
1275 | ||
0bc40be8 | 1276 | ret = gen8_init_common_ring(engine); |
9b1136d5 OM |
1277 | if (ret) |
1278 | return ret; | |
1279 | ||
1280 | /* We need to disable the AsyncFlip performance optimisations in order | |
1281 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1282 | * programmed to '1' on all products. | |
1283 | * | |
1284 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv | |
1285 | */ | |
1286 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
1287 | ||
9b1136d5 OM |
1288 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
1289 | ||
0bc40be8 | 1290 | return init_workarounds_ring(engine); |
9b1136d5 OM |
1291 | } |
1292 | ||
0bc40be8 | 1293 | static int gen9_init_render_ring(struct intel_engine_cs *engine) |
82ef822e DL |
1294 | { |
1295 | int ret; | |
1296 | ||
0bc40be8 | 1297 | ret = gen8_init_common_ring(engine); |
82ef822e DL |
1298 | if (ret) |
1299 | return ret; | |
1300 | ||
0bc40be8 | 1301 | return init_workarounds_ring(engine); |
82ef822e DL |
1302 | } |
1303 | ||
821ed7df CW |
1304 | static void reset_common_ring(struct intel_engine_cs *engine, |
1305 | struct drm_i915_gem_request *request) | |
1306 | { | |
821ed7df | 1307 | struct execlist_port *port = engine->execlist_port; |
c0dcb203 | 1308 | struct intel_context *ce; |
cdb6ded4 CW |
1309 | unsigned int n; |
1310 | ||
1311 | /* | |
1312 | * Catch up with any missed context-switch interrupts. | |
1313 | * | |
1314 | * Ideally we would just read the remaining CSB entries now that we | |
1315 | * know the gpu is idle. However, the CSB registers are sometimes^W | |
1316 | * often trashed across a GPU reset! Instead we have to rely on | |
1317 | * guessing the missed context-switch events by looking at what | |
1318 | * requests were completed. | |
1319 | */ | |
1320 | if (!request) { | |
1321 | for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++) | |
1322 | i915_gem_request_put(port_request(&port[n])); | |
1323 | memset(engine->execlist_port, 0, sizeof(engine->execlist_port)); | |
1324 | return; | |
1325 | } | |
1326 | ||
1327 | if (request->ctx != port_request(port)->ctx) { | |
1328 | i915_gem_request_put(port_request(port)); | |
1329 | port[0] = port[1]; | |
1330 | memset(&port[1], 0, sizeof(port[1])); | |
1331 | } | |
1332 | ||
1333 | GEM_BUG_ON(request->ctx != port_request(port)->ctx); | |
c0dcb203 CW |
1334 | |
1335 | /* If the request was innocent, we leave the request in the ELSP | |
1336 | * and will try to replay it on restarting. The context image may | |
1337 | * have been corrupted by the reset, in which case we may have | |
1338 | * to service a new GPU hang, but more likely we can continue on | |
1339 | * without impact. | |
1340 | * | |
1341 | * If the request was guilty, we presume the context is corrupt | |
1342 | * and have to at least restore the RING register in the context | |
1343 | * image back to the expected values to skip over the guilty request. | |
1344 | */ | |
cdb6ded4 | 1345 | if (request->fence.error != -EIO) |
c0dcb203 | 1346 | return; |
821ed7df | 1347 | |
a3aabe86 CW |
1348 | /* We want a simple context + ring to execute the breadcrumb update. |
1349 | * We cannot rely on the context being intact across the GPU hang, | |
1350 | * so clear it and rebuild just what we need for the breadcrumb. | |
1351 | * All pending requests for this context will be zapped, and any | |
1352 | * future request will be after userspace has had the opportunity | |
1353 | * to recreate its own state. | |
1354 | */ | |
c0dcb203 | 1355 | ce = &request->ctx->engine[engine->id]; |
a3aabe86 CW |
1356 | execlists_init_reg_state(ce->lrc_reg_state, |
1357 | request->ctx, engine, ce->ring); | |
1358 | ||
821ed7df | 1359 | /* Move the RING_HEAD onto the breadcrumb, past the hanging batch */ |
a3aabe86 CW |
1360 | ce->lrc_reg_state[CTX_RING_BUFFER_START+1] = |
1361 | i915_ggtt_offset(ce->ring->vma); | |
821ed7df | 1362 | ce->lrc_reg_state[CTX_RING_HEAD+1] = request->postfix; |
a3aabe86 | 1363 | |
821ed7df | 1364 | request->ring->head = request->postfix; |
821ed7df CW |
1365 | intel_ring_update_space(request->ring); |
1366 | ||
a3aabe86 | 1367 | /* Reset WaIdleLiteRestore:bdw,skl as well */ |
450362d3 CW |
1368 | request->tail = |
1369 | intel_ring_wrap(request->ring, | |
1370 | request->wa_tail - WA_TAIL_DWORDS*sizeof(u32)); | |
ed1501d4 | 1371 | assert_ring_tail_valid(request->ring, request->tail); |
821ed7df CW |
1372 | } |
1373 | ||
7a01a0a2 MT |
1374 | static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req) |
1375 | { | |
1376 | struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt; | |
4a570db5 | 1377 | struct intel_engine_cs *engine = req->engine; |
e7167769 | 1378 | const int num_lri_cmds = GEN8_3LVL_PDPES * 2; |
73dec95e TU |
1379 | u32 *cs; |
1380 | int i; | |
7a01a0a2 | 1381 | |
73dec95e TU |
1382 | cs = intel_ring_begin(req, num_lri_cmds * 2 + 2); |
1383 | if (IS_ERR(cs)) | |
1384 | return PTR_ERR(cs); | |
7a01a0a2 | 1385 | |
73dec95e | 1386 | *cs++ = MI_LOAD_REGISTER_IMM(num_lri_cmds); |
e7167769 | 1387 | for (i = GEN8_3LVL_PDPES - 1; i >= 0; i--) { |
7a01a0a2 MT |
1388 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); |
1389 | ||
73dec95e TU |
1390 | *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i)); |
1391 | *cs++ = upper_32_bits(pd_daddr); | |
1392 | *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i)); | |
1393 | *cs++ = lower_32_bits(pd_daddr); | |
7a01a0a2 MT |
1394 | } |
1395 | ||
73dec95e TU |
1396 | *cs++ = MI_NOOP; |
1397 | intel_ring_advance(req, cs); | |
7a01a0a2 MT |
1398 | |
1399 | return 0; | |
1400 | } | |
1401 | ||
be795fc1 | 1402 | static int gen8_emit_bb_start(struct drm_i915_gem_request *req, |
803688ba | 1403 | u64 offset, u32 len, |
54af56db | 1404 | const unsigned int flags) |
15648585 | 1405 | { |
73dec95e | 1406 | u32 *cs; |
15648585 OM |
1407 | int ret; |
1408 | ||
7a01a0a2 MT |
1409 | /* Don't rely in hw updating PDPs, specially in lite-restore. |
1410 | * Ideally, we should set Force PD Restore in ctx descriptor, | |
1411 | * but we can't. Force Restore would be a second option, but | |
1412 | * it is unsafe in case of lite-restore (because the ctx is | |
2dba3239 MT |
1413 | * not idle). PML4 is allocated during ppgtt init so this is |
1414 | * not needed in 48-bit.*/ | |
7a01a0a2 | 1415 | if (req->ctx->ppgtt && |
54af56db MK |
1416 | (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings) && |
1417 | !i915_vm_is_48bit(&req->ctx->ppgtt->base) && | |
1418 | !intel_vgpu_active(req->i915)) { | |
1419 | ret = intel_logical_ring_emit_pdps(req); | |
1420 | if (ret) | |
1421 | return ret; | |
7a01a0a2 | 1422 | |
666796da | 1423 | req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine); |
7a01a0a2 MT |
1424 | } |
1425 | ||
73dec95e TU |
1426 | cs = intel_ring_begin(req, 4); |
1427 | if (IS_ERR(cs)) | |
1428 | return PTR_ERR(cs); | |
15648585 OM |
1429 | |
1430 | /* FIXME(BDW): Address space and security selectors. */ | |
54af56db MK |
1431 | *cs++ = MI_BATCH_BUFFER_START_GEN8 | |
1432 | (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)) | | |
1433 | (flags & I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0); | |
73dec95e TU |
1434 | *cs++ = lower_32_bits(offset); |
1435 | *cs++ = upper_32_bits(offset); | |
1436 | *cs++ = MI_NOOP; | |
1437 | intel_ring_advance(req, cs); | |
15648585 OM |
1438 | |
1439 | return 0; | |
1440 | } | |
1441 | ||
31bb59cc | 1442 | static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine) |
73d477f6 | 1443 | { |
c033666a | 1444 | struct drm_i915_private *dev_priv = engine->i915; |
31bb59cc CW |
1445 | I915_WRITE_IMR(engine, |
1446 | ~(engine->irq_enable_mask | engine->irq_keep_mask)); | |
1447 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
73d477f6 OM |
1448 | } |
1449 | ||
31bb59cc | 1450 | static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine) |
73d477f6 | 1451 | { |
c033666a | 1452 | struct drm_i915_private *dev_priv = engine->i915; |
31bb59cc | 1453 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
73d477f6 OM |
1454 | } |
1455 | ||
7c9cf4e3 | 1456 | static int gen8_emit_flush(struct drm_i915_gem_request *request, u32 mode) |
4712274c | 1457 | { |
73dec95e | 1458 | u32 cmd, *cs; |
4712274c | 1459 | |
73dec95e TU |
1460 | cs = intel_ring_begin(request, 4); |
1461 | if (IS_ERR(cs)) | |
1462 | return PTR_ERR(cs); | |
4712274c OM |
1463 | |
1464 | cmd = MI_FLUSH_DW + 1; | |
1465 | ||
f0a1fb10 CW |
1466 | /* We always require a command barrier so that subsequent |
1467 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1468 | * wrt the contents of the write cache being flushed to memory | |
1469 | * (and thus being coherent from the CPU). | |
1470 | */ | |
1471 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1472 | ||
7c9cf4e3 | 1473 | if (mode & EMIT_INVALIDATE) { |
f0a1fb10 | 1474 | cmd |= MI_INVALIDATE_TLB; |
1dae2dfb | 1475 | if (request->engine->id == VCS) |
f0a1fb10 | 1476 | cmd |= MI_INVALIDATE_BSD; |
4712274c OM |
1477 | } |
1478 | ||
73dec95e TU |
1479 | *cs++ = cmd; |
1480 | *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; | |
1481 | *cs++ = 0; /* upper addr */ | |
1482 | *cs++ = 0; /* value */ | |
1483 | intel_ring_advance(request, cs); | |
4712274c OM |
1484 | |
1485 | return 0; | |
1486 | } | |
1487 | ||
7deb4d39 | 1488 | static int gen8_emit_flush_render(struct drm_i915_gem_request *request, |
7c9cf4e3 | 1489 | u32 mode) |
4712274c | 1490 | { |
b5321f30 | 1491 | struct intel_engine_cs *engine = request->engine; |
bde13ebd CW |
1492 | u32 scratch_addr = |
1493 | i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES; | |
0b2d0934 | 1494 | bool vf_flush_wa = false, dc_flush_wa = false; |
73dec95e | 1495 | u32 *cs, flags = 0; |
0b2d0934 | 1496 | int len; |
4712274c OM |
1497 | |
1498 | flags |= PIPE_CONTROL_CS_STALL; | |
1499 | ||
7c9cf4e3 | 1500 | if (mode & EMIT_FLUSH) { |
4712274c OM |
1501 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
1502 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 1503 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 1504 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4712274c OM |
1505 | } |
1506 | ||
7c9cf4e3 | 1507 | if (mode & EMIT_INVALIDATE) { |
4712274c OM |
1508 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
1509 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
1510 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
1511 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
1512 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
1513 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
1514 | flags |= PIPE_CONTROL_QW_WRITE; | |
1515 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
4712274c | 1516 | |
1a5a9ce7 BW |
1517 | /* |
1518 | * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL | |
1519 | * pipe control. | |
1520 | */ | |
c033666a | 1521 | if (IS_GEN9(request->i915)) |
1a5a9ce7 | 1522 | vf_flush_wa = true; |
0b2d0934 MK |
1523 | |
1524 | /* WaForGAMHang:kbl */ | |
1525 | if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0)) | |
1526 | dc_flush_wa = true; | |
1a5a9ce7 | 1527 | } |
9647ff36 | 1528 | |
0b2d0934 MK |
1529 | len = 6; |
1530 | ||
1531 | if (vf_flush_wa) | |
1532 | len += 6; | |
1533 | ||
1534 | if (dc_flush_wa) | |
1535 | len += 12; | |
1536 | ||
73dec95e TU |
1537 | cs = intel_ring_begin(request, len); |
1538 | if (IS_ERR(cs)) | |
1539 | return PTR_ERR(cs); | |
4712274c | 1540 | |
9f235dfa TU |
1541 | if (vf_flush_wa) |
1542 | cs = gen8_emit_pipe_control(cs, 0, 0); | |
9647ff36 | 1543 | |
9f235dfa TU |
1544 | if (dc_flush_wa) |
1545 | cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE, | |
1546 | 0); | |
0b2d0934 | 1547 | |
9f235dfa | 1548 | cs = gen8_emit_pipe_control(cs, flags, scratch_addr); |
0b2d0934 | 1549 | |
9f235dfa TU |
1550 | if (dc_flush_wa) |
1551 | cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0); | |
0b2d0934 | 1552 | |
73dec95e | 1553 | intel_ring_advance(request, cs); |
4712274c OM |
1554 | |
1555 | return 0; | |
1556 | } | |
1557 | ||
7c17d377 CW |
1558 | /* |
1559 | * Reserve space for 2 NOOPs at the end of each request to be | |
1560 | * used as a workaround for not being allowed to do lite | |
1561 | * restore with HEAD==TAIL (WaIdleLiteRestore). | |
1562 | */ | |
73dec95e | 1563 | static void gen8_emit_wa_tail(struct drm_i915_gem_request *request, u32 *cs) |
4da46e1e | 1564 | { |
73dec95e TU |
1565 | *cs++ = MI_NOOP; |
1566 | *cs++ = MI_NOOP; | |
1567 | request->wa_tail = intel_ring_offset(request, cs); | |
caddfe71 | 1568 | } |
4da46e1e | 1569 | |
73dec95e | 1570 | static void gen8_emit_breadcrumb(struct drm_i915_gem_request *request, u32 *cs) |
caddfe71 | 1571 | { |
7c17d377 CW |
1572 | /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */ |
1573 | BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5)); | |
4da46e1e | 1574 | |
73dec95e TU |
1575 | *cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW; |
1576 | *cs++ = intel_hws_seqno_address(request->engine) | MI_FLUSH_DW_USE_GTT; | |
1577 | *cs++ = 0; | |
1578 | *cs++ = request->global_seqno; | |
1579 | *cs++ = MI_USER_INTERRUPT; | |
1580 | *cs++ = MI_NOOP; | |
1581 | request->tail = intel_ring_offset(request, cs); | |
ed1501d4 | 1582 | assert_ring_tail_valid(request->ring, request->tail); |
caddfe71 | 1583 | |
73dec95e | 1584 | gen8_emit_wa_tail(request, cs); |
7c17d377 | 1585 | } |
4da46e1e | 1586 | |
98f29e8d CW |
1587 | static const int gen8_emit_breadcrumb_sz = 6 + WA_TAIL_DWORDS; |
1588 | ||
caddfe71 | 1589 | static void gen8_emit_breadcrumb_render(struct drm_i915_gem_request *request, |
73dec95e | 1590 | u32 *cs) |
7c17d377 | 1591 | { |
ce81a65c MW |
1592 | /* We're using qword write, seqno should be aligned to 8 bytes. */ |
1593 | BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1); | |
1594 | ||
7c17d377 CW |
1595 | /* w/a for post sync ops following a GPGPU operation we |
1596 | * need a prior CS_STALL, which is emitted by the flush | |
1597 | * following the batch. | |
1598 | */ | |
73dec95e TU |
1599 | *cs++ = GFX_OP_PIPE_CONTROL(6); |
1600 | *cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_CS_STALL | | |
1601 | PIPE_CONTROL_QW_WRITE; | |
1602 | *cs++ = intel_hws_seqno_address(request->engine); | |
1603 | *cs++ = 0; | |
1604 | *cs++ = request->global_seqno; | |
ce81a65c | 1605 | /* We're thrashing one dword of HWS. */ |
73dec95e TU |
1606 | *cs++ = 0; |
1607 | *cs++ = MI_USER_INTERRUPT; | |
1608 | *cs++ = MI_NOOP; | |
1609 | request->tail = intel_ring_offset(request, cs); | |
ed1501d4 | 1610 | assert_ring_tail_valid(request->ring, request->tail); |
caddfe71 | 1611 | |
73dec95e | 1612 | gen8_emit_wa_tail(request, cs); |
4da46e1e OM |
1613 | } |
1614 | ||
98f29e8d CW |
1615 | static const int gen8_emit_breadcrumb_render_sz = 8 + WA_TAIL_DWORDS; |
1616 | ||
8753181e | 1617 | static int gen8_init_rcs_context(struct drm_i915_gem_request *req) |
e7778be1 TD |
1618 | { |
1619 | int ret; | |
1620 | ||
4ac9659e | 1621 | ret = intel_ring_workarounds_emit(req); |
e7778be1 TD |
1622 | if (ret) |
1623 | return ret; | |
1624 | ||
3bbaba0c PA |
1625 | ret = intel_rcs_context_init_mocs(req); |
1626 | /* | |
1627 | * Failing to program the MOCS is non-fatal.The system will not | |
1628 | * run at peak performance. So generate an error and carry on. | |
1629 | */ | |
1630 | if (ret) | |
1631 | DRM_ERROR("MOCS failed to program: expect performance issues.\n"); | |
1632 | ||
4e50f082 | 1633 | return i915_gem_render_state_emit(req); |
e7778be1 TD |
1634 | } |
1635 | ||
73e4d07f OM |
1636 | /** |
1637 | * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer | |
14bb2c11 | 1638 | * @engine: Engine Command Streamer. |
73e4d07f | 1639 | */ |
0bc40be8 | 1640 | void intel_logical_ring_cleanup(struct intel_engine_cs *engine) |
454afebd | 1641 | { |
6402c330 | 1642 | struct drm_i915_private *dev_priv; |
9832b9da | 1643 | |
27af5eea TU |
1644 | /* |
1645 | * Tasklet cannot be active at this point due intel_mark_active/idle | |
1646 | * so this is just for documentation. | |
1647 | */ | |
1648 | if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state))) | |
1649 | tasklet_kill(&engine->irq_tasklet); | |
1650 | ||
c033666a | 1651 | dev_priv = engine->i915; |
6402c330 | 1652 | |
0bc40be8 | 1653 | if (engine->buffer) { |
0bc40be8 | 1654 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
b0366a54 | 1655 | } |
48d82387 | 1656 | |
0bc40be8 TU |
1657 | if (engine->cleanup) |
1658 | engine->cleanup(engine); | |
48d82387 | 1659 | |
57e88531 CW |
1660 | if (engine->status_page.vma) { |
1661 | i915_gem_object_unpin_map(engine->status_page.vma->obj); | |
1662 | engine->status_page.vma = NULL; | |
48d82387 | 1663 | } |
e8a9c58f CW |
1664 | |
1665 | intel_engine_cleanup_common(engine); | |
17ee950d | 1666 | |
097d4f1c | 1667 | lrc_destroy_wa_ctx(engine); |
c033666a | 1668 | engine->i915 = NULL; |
3b3f1650 AG |
1669 | dev_priv->engine[engine->id] = NULL; |
1670 | kfree(engine); | |
454afebd OM |
1671 | } |
1672 | ||
ff44ad51 | 1673 | static void execlists_set_default_submission(struct intel_engine_cs *engine) |
ddd66c51 | 1674 | { |
ff44ad51 CW |
1675 | engine->submit_request = execlists_submit_request; |
1676 | engine->schedule = execlists_schedule; | |
c9203e82 | 1677 | engine->irq_tasklet.func = intel_lrc_irq_handler; |
ddd66c51 CW |
1678 | } |
1679 | ||
c9cacf93 | 1680 | static void |
e1382efb | 1681 | logical_ring_default_vfuncs(struct intel_engine_cs *engine) |
c9cacf93 TU |
1682 | { |
1683 | /* Default vfuncs which can be overriden by each engine. */ | |
0bc40be8 | 1684 | engine->init_hw = gen8_init_common_ring; |
821ed7df | 1685 | engine->reset_hw = reset_common_ring; |
e8a9c58f CW |
1686 | |
1687 | engine->context_pin = execlists_context_pin; | |
1688 | engine->context_unpin = execlists_context_unpin; | |
1689 | ||
f73e7399 CW |
1690 | engine->request_alloc = execlists_request_alloc; |
1691 | ||
0bc40be8 | 1692 | engine->emit_flush = gen8_emit_flush; |
9b81d556 | 1693 | engine->emit_breadcrumb = gen8_emit_breadcrumb; |
98f29e8d | 1694 | engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz; |
ff44ad51 CW |
1695 | |
1696 | engine->set_default_submission = execlists_set_default_submission; | |
ddd66c51 | 1697 | |
31bb59cc CW |
1698 | engine->irq_enable = gen8_logical_ring_enable_irq; |
1699 | engine->irq_disable = gen8_logical_ring_disable_irq; | |
0bc40be8 | 1700 | engine->emit_bb_start = gen8_emit_bb_start; |
c9cacf93 TU |
1701 | } |
1702 | ||
d9f3af96 | 1703 | static inline void |
c2c7f240 | 1704 | logical_ring_default_irqs(struct intel_engine_cs *engine) |
d9f3af96 | 1705 | { |
c2c7f240 | 1706 | unsigned shift = engine->irq_shift; |
0bc40be8 TU |
1707 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift; |
1708 | engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift; | |
d9f3af96 TU |
1709 | } |
1710 | ||
7d774cac | 1711 | static int |
bf3783e5 | 1712 | lrc_setup_hws(struct intel_engine_cs *engine, struct i915_vma *vma) |
04794adb | 1713 | { |
57e88531 | 1714 | const int hws_offset = LRC_PPHWSP_PN * PAGE_SIZE; |
7d774cac | 1715 | void *hws; |
04794adb TU |
1716 | |
1717 | /* The HWSP is part of the default context object in LRC mode. */ | |
bf3783e5 | 1718 | hws = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); |
7d774cac TU |
1719 | if (IS_ERR(hws)) |
1720 | return PTR_ERR(hws); | |
57e88531 CW |
1721 | |
1722 | engine->status_page.page_addr = hws + hws_offset; | |
bde13ebd | 1723 | engine->status_page.ggtt_offset = i915_ggtt_offset(vma) + hws_offset; |
57e88531 | 1724 | engine->status_page.vma = vma; |
7d774cac TU |
1725 | |
1726 | return 0; | |
04794adb TU |
1727 | } |
1728 | ||
bb45438f TU |
1729 | static void |
1730 | logical_ring_setup(struct intel_engine_cs *engine) | |
1731 | { | |
1732 | struct drm_i915_private *dev_priv = engine->i915; | |
1733 | enum forcewake_domains fw_domains; | |
1734 | ||
019bf277 TU |
1735 | intel_engine_setup_common(engine); |
1736 | ||
bb45438f TU |
1737 | /* Intentionally left blank. */ |
1738 | engine->buffer = NULL; | |
1739 | ||
1740 | fw_domains = intel_uncore_forcewake_for_reg(dev_priv, | |
1741 | RING_ELSP(engine), | |
1742 | FW_REG_WRITE); | |
1743 | ||
1744 | fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, | |
1745 | RING_CONTEXT_STATUS_PTR(engine), | |
1746 | FW_REG_READ | FW_REG_WRITE); | |
1747 | ||
1748 | fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, | |
1749 | RING_CONTEXT_STATUS_BUF_BASE(engine), | |
1750 | FW_REG_READ); | |
1751 | ||
1752 | engine->fw_domains = fw_domains; | |
1753 | ||
bb45438f TU |
1754 | tasklet_init(&engine->irq_tasklet, |
1755 | intel_lrc_irq_handler, (unsigned long)engine); | |
1756 | ||
bb45438f TU |
1757 | logical_ring_default_vfuncs(engine); |
1758 | logical_ring_default_irqs(engine); | |
bb45438f TU |
1759 | } |
1760 | ||
a19d6ff2 TU |
1761 | static int |
1762 | logical_ring_init(struct intel_engine_cs *engine) | |
1763 | { | |
1764 | struct i915_gem_context *dctx = engine->i915->kernel_context; | |
1765 | int ret; | |
1766 | ||
019bf277 | 1767 | ret = intel_engine_init_common(engine); |
a19d6ff2 TU |
1768 | if (ret) |
1769 | goto error; | |
1770 | ||
a19d6ff2 TU |
1771 | /* And setup the hardware status page. */ |
1772 | ret = lrc_setup_hws(engine, dctx->engine[engine->id].state); | |
1773 | if (ret) { | |
1774 | DRM_ERROR("Failed to set up hws %s: %d\n", engine->name, ret); | |
1775 | goto error; | |
1776 | } | |
1777 | ||
1778 | return 0; | |
1779 | ||
1780 | error: | |
1781 | intel_logical_ring_cleanup(engine); | |
1782 | return ret; | |
1783 | } | |
1784 | ||
88d2ba2e | 1785 | int logical_render_ring_init(struct intel_engine_cs *engine) |
a19d6ff2 TU |
1786 | { |
1787 | struct drm_i915_private *dev_priv = engine->i915; | |
1788 | int ret; | |
1789 | ||
bb45438f TU |
1790 | logical_ring_setup(engine); |
1791 | ||
a19d6ff2 TU |
1792 | if (HAS_L3_DPF(dev_priv)) |
1793 | engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
1794 | ||
1795 | /* Override some for render ring. */ | |
1796 | if (INTEL_GEN(dev_priv) >= 9) | |
1797 | engine->init_hw = gen9_init_render_ring; | |
1798 | else | |
1799 | engine->init_hw = gen8_init_render_ring; | |
1800 | engine->init_context = gen8_init_rcs_context; | |
a19d6ff2 | 1801 | engine->emit_flush = gen8_emit_flush_render; |
9b81d556 | 1802 | engine->emit_breadcrumb = gen8_emit_breadcrumb_render; |
98f29e8d | 1803 | engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_render_sz; |
a19d6ff2 | 1804 | |
f51455d4 | 1805 | ret = intel_engine_create_scratch(engine, PAGE_SIZE); |
a19d6ff2 TU |
1806 | if (ret) |
1807 | return ret; | |
1808 | ||
1809 | ret = intel_init_workaround_bb(engine); | |
1810 | if (ret) { | |
1811 | /* | |
1812 | * We continue even if we fail to initialize WA batch | |
1813 | * because we only expect rare glitches but nothing | |
1814 | * critical to prevent us from using GPU | |
1815 | */ | |
1816 | DRM_ERROR("WA batch buffer initialization failed: %d\n", | |
1817 | ret); | |
1818 | } | |
1819 | ||
d038fc7e | 1820 | return logical_ring_init(engine); |
a19d6ff2 TU |
1821 | } |
1822 | ||
88d2ba2e | 1823 | int logical_xcs_ring_init(struct intel_engine_cs *engine) |
bb45438f TU |
1824 | { |
1825 | logical_ring_setup(engine); | |
1826 | ||
1827 | return logical_ring_init(engine); | |
454afebd OM |
1828 | } |
1829 | ||
0cea6502 | 1830 | static u32 |
c033666a | 1831 | make_rpcs(struct drm_i915_private *dev_priv) |
0cea6502 JM |
1832 | { |
1833 | u32 rpcs = 0; | |
1834 | ||
1835 | /* | |
1836 | * No explicit RPCS request is needed to ensure full | |
1837 | * slice/subslice/EU enablement prior to Gen9. | |
1838 | */ | |
c033666a | 1839 | if (INTEL_GEN(dev_priv) < 9) |
0cea6502 JM |
1840 | return 0; |
1841 | ||
1842 | /* | |
1843 | * Starting in Gen9, render power gating can leave | |
1844 | * slice/subslice/EU in a partially enabled state. We | |
1845 | * must make an explicit request through RPCS for full | |
1846 | * enablement. | |
1847 | */ | |
43b67998 | 1848 | if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) { |
0cea6502 | 1849 | rpcs |= GEN8_RPCS_S_CNT_ENABLE; |
f08a0c92 | 1850 | rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) << |
0cea6502 JM |
1851 | GEN8_RPCS_S_CNT_SHIFT; |
1852 | rpcs |= GEN8_RPCS_ENABLE; | |
1853 | } | |
1854 | ||
43b67998 | 1855 | if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) { |
0cea6502 | 1856 | rpcs |= GEN8_RPCS_SS_CNT_ENABLE; |
57ec171e | 1857 | rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask) << |
0cea6502 JM |
1858 | GEN8_RPCS_SS_CNT_SHIFT; |
1859 | rpcs |= GEN8_RPCS_ENABLE; | |
1860 | } | |
1861 | ||
43b67998 ID |
1862 | if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) { |
1863 | rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice << | |
0cea6502 | 1864 | GEN8_RPCS_EU_MIN_SHIFT; |
43b67998 | 1865 | rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice << |
0cea6502 JM |
1866 | GEN8_RPCS_EU_MAX_SHIFT; |
1867 | rpcs |= GEN8_RPCS_ENABLE; | |
1868 | } | |
1869 | ||
1870 | return rpcs; | |
1871 | } | |
1872 | ||
0bc40be8 | 1873 | static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine) |
71562919 MT |
1874 | { |
1875 | u32 indirect_ctx_offset; | |
1876 | ||
c033666a | 1877 | switch (INTEL_GEN(engine->i915)) { |
71562919 | 1878 | default: |
c033666a | 1879 | MISSING_CASE(INTEL_GEN(engine->i915)); |
71562919 | 1880 | /* fall through */ |
7bd0a2c6 MT |
1881 | case 10: |
1882 | indirect_ctx_offset = | |
1883 | GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
1884 | break; | |
71562919 MT |
1885 | case 9: |
1886 | indirect_ctx_offset = | |
1887 | GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
1888 | break; | |
1889 | case 8: | |
1890 | indirect_ctx_offset = | |
1891 | GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
1892 | break; | |
1893 | } | |
1894 | ||
1895 | return indirect_ctx_offset; | |
1896 | } | |
1897 | ||
56e51bf0 | 1898 | static void execlists_init_reg_state(u32 *regs, |
a3aabe86 CW |
1899 | struct i915_gem_context *ctx, |
1900 | struct intel_engine_cs *engine, | |
1901 | struct intel_ring *ring) | |
8670d6f9 | 1902 | { |
a3aabe86 CW |
1903 | struct drm_i915_private *dev_priv = engine->i915; |
1904 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv->mm.aliasing_ppgtt; | |
56e51bf0 TU |
1905 | u32 base = engine->mmio_base; |
1906 | bool rcs = engine->id == RCS; | |
1907 | ||
1908 | /* A context is actually a big batch buffer with several | |
1909 | * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The | |
1910 | * values we are setting here are only for the first context restore: | |
1911 | * on a subsequent save, the GPU will recreate this batchbuffer with new | |
1912 | * values (including all the missing MI_LOAD_REGISTER_IMM commands that | |
1913 | * we are not initializing here). | |
1914 | */ | |
1915 | regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) | | |
1916 | MI_LRI_FORCE_POSTED; | |
1917 | ||
1918 | CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(engine), | |
1919 | _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | | |
1920 | CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | | |
1921 | (HAS_RESOURCE_STREAMER(dev_priv) ? | |
1922 | CTX_CTRL_RS_CTX_ENABLE : 0))); | |
1923 | CTX_REG(regs, CTX_RING_HEAD, RING_HEAD(base), 0); | |
1924 | CTX_REG(regs, CTX_RING_TAIL, RING_TAIL(base), 0); | |
1925 | CTX_REG(regs, CTX_RING_BUFFER_START, RING_START(base), 0); | |
1926 | CTX_REG(regs, CTX_RING_BUFFER_CONTROL, RING_CTL(base), | |
1927 | RING_CTL_SIZE(ring->size) | RING_VALID); | |
1928 | CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0); | |
1929 | CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0); | |
1930 | CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT); | |
1931 | CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0); | |
1932 | CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0); | |
1933 | CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0); | |
1934 | if (rcs) { | |
1935 | CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0); | |
1936 | CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0); | |
1937 | CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET, | |
1938 | RING_INDIRECT_CTX_OFFSET(base), 0); | |
8670d6f9 | 1939 | |
48bb74e4 | 1940 | if (engine->wa_ctx.vma) { |
0bc40be8 | 1941 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; |
bde13ebd | 1942 | u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); |
17ee950d | 1943 | |
56e51bf0 | 1944 | regs[CTX_RCS_INDIRECT_CTX + 1] = |
097d4f1c TU |
1945 | (ggtt_offset + wa_ctx->indirect_ctx.offset) | |
1946 | (wa_ctx->indirect_ctx.size / CACHELINE_BYTES); | |
17ee950d | 1947 | |
56e51bf0 | 1948 | regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] = |
0bc40be8 | 1949 | intel_lr_indirect_ctx_offset(engine) << 6; |
17ee950d | 1950 | |
56e51bf0 | 1951 | regs[CTX_BB_PER_CTX_PTR + 1] = |
097d4f1c | 1952 | (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01; |
17ee950d | 1953 | } |
8670d6f9 | 1954 | } |
56e51bf0 TU |
1955 | |
1956 | regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED; | |
1957 | ||
1958 | CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0); | |
0d925ea0 | 1959 | /* PDP values well be assigned later if needed */ |
56e51bf0 TU |
1960 | CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), 0); |
1961 | CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), 0); | |
1962 | CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), 0); | |
1963 | CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), 0); | |
1964 | CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), 0); | |
1965 | CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), 0); | |
1966 | CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0); | |
1967 | CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0); | |
d7b2633d | 1968 | |
949e8ab3 | 1969 | if (ppgtt && i915_vm_is_48bit(&ppgtt->base)) { |
2dba3239 MT |
1970 | /* 64b PPGTT (48bit canonical) |
1971 | * PDP0_DESCRIPTOR contains the base address to PML4 and | |
1972 | * other PDP Descriptors are ignored. | |
1973 | */ | |
56e51bf0 | 1974 | ASSIGN_CTX_PML4(ppgtt, regs); |
2dba3239 MT |
1975 | } |
1976 | ||
56e51bf0 TU |
1977 | if (rcs) { |
1978 | regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); | |
1979 | CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, | |
1980 | make_rpcs(dev_priv)); | |
19f81df2 RB |
1981 | |
1982 | i915_oa_init_reg_state(engine, ctx, regs); | |
8670d6f9 | 1983 | } |
a3aabe86 CW |
1984 | } |
1985 | ||
1986 | static int | |
1987 | populate_lr_context(struct i915_gem_context *ctx, | |
1988 | struct drm_i915_gem_object *ctx_obj, | |
1989 | struct intel_engine_cs *engine, | |
1990 | struct intel_ring *ring) | |
1991 | { | |
1992 | void *vaddr; | |
1993 | int ret; | |
1994 | ||
1995 | ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); | |
1996 | if (ret) { | |
1997 | DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); | |
1998 | return ret; | |
1999 | } | |
2000 | ||
2001 | vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB); | |
2002 | if (IS_ERR(vaddr)) { | |
2003 | ret = PTR_ERR(vaddr); | |
2004 | DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret); | |
2005 | return ret; | |
2006 | } | |
a4f5ea64 | 2007 | ctx_obj->mm.dirty = true; |
a3aabe86 CW |
2008 | |
2009 | /* The second page of the context object contains some fields which must | |
2010 | * be set up prior to the first execution. */ | |
2011 | ||
2012 | execlists_init_reg_state(vaddr + LRC_STATE_PN * PAGE_SIZE, | |
2013 | ctx, engine, ring); | |
8670d6f9 | 2014 | |
7d774cac | 2015 | i915_gem_object_unpin_map(ctx_obj); |
8670d6f9 OM |
2016 | |
2017 | return 0; | |
2018 | } | |
2019 | ||
e2efd130 | 2020 | static int execlists_context_deferred_alloc(struct i915_gem_context *ctx, |
978f1e09 | 2021 | struct intel_engine_cs *engine) |
ede7d42b | 2022 | { |
8c857917 | 2023 | struct drm_i915_gem_object *ctx_obj; |
9021ad03 | 2024 | struct intel_context *ce = &ctx->engine[engine->id]; |
bf3783e5 | 2025 | struct i915_vma *vma; |
8c857917 | 2026 | uint32_t context_size; |
7e37f889 | 2027 | struct intel_ring *ring; |
8c857917 OM |
2028 | int ret; |
2029 | ||
9021ad03 | 2030 | WARN_ON(ce->state); |
ede7d42b | 2031 | |
63ffbcda | 2032 | context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE); |
8c857917 | 2033 | |
d1675198 AD |
2034 | /* One extra page as the sharing data between driver and GuC */ |
2035 | context_size += PAGE_SIZE * LRC_PPHWSP_PN; | |
2036 | ||
12d79d78 | 2037 | ctx_obj = i915_gem_object_create(ctx->i915, context_size); |
fe3db79b | 2038 | if (IS_ERR(ctx_obj)) { |
3126a660 | 2039 | DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n"); |
fe3db79b | 2040 | return PTR_ERR(ctx_obj); |
8c857917 OM |
2041 | } |
2042 | ||
a01cb37a | 2043 | vma = i915_vma_instance(ctx_obj, &ctx->i915->ggtt.base, NULL); |
bf3783e5 CW |
2044 | if (IS_ERR(vma)) { |
2045 | ret = PTR_ERR(vma); | |
2046 | goto error_deref_obj; | |
2047 | } | |
2048 | ||
7e37f889 | 2049 | ring = intel_engine_create_ring(engine, ctx->ring_size); |
dca33ecc CW |
2050 | if (IS_ERR(ring)) { |
2051 | ret = PTR_ERR(ring); | |
e84fe803 | 2052 | goto error_deref_obj; |
8670d6f9 OM |
2053 | } |
2054 | ||
dca33ecc | 2055 | ret = populate_lr_context(ctx, ctx_obj, engine, ring); |
8670d6f9 OM |
2056 | if (ret) { |
2057 | DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); | |
dca33ecc | 2058 | goto error_ring_free; |
84c2377f OM |
2059 | } |
2060 | ||
dca33ecc | 2061 | ce->ring = ring; |
bf3783e5 | 2062 | ce->state = vma; |
0d402a24 | 2063 | ce->initialised |= engine->init_context == NULL; |
ede7d42b OM |
2064 | |
2065 | return 0; | |
8670d6f9 | 2066 | |
dca33ecc | 2067 | error_ring_free: |
7e37f889 | 2068 | intel_ring_free(ring); |
e84fe803 | 2069 | error_deref_obj: |
f8c417cd | 2070 | i915_gem_object_put(ctx_obj); |
8670d6f9 | 2071 | return ret; |
ede7d42b | 2072 | } |
3e5b6f05 | 2073 | |
821ed7df | 2074 | void intel_lr_context_resume(struct drm_i915_private *dev_priv) |
3e5b6f05 | 2075 | { |
e2f80391 | 2076 | struct intel_engine_cs *engine; |
bafb2f7d | 2077 | struct i915_gem_context *ctx; |
3b3f1650 | 2078 | enum intel_engine_id id; |
bafb2f7d CW |
2079 | |
2080 | /* Because we emit WA_TAIL_DWORDS there may be a disparity | |
2081 | * between our bookkeeping in ce->ring->head and ce->ring->tail and | |
2082 | * that stored in context. As we only write new commands from | |
2083 | * ce->ring->tail onwards, everything before that is junk. If the GPU | |
2084 | * starts reading from its RING_HEAD from the context, it may try to | |
2085 | * execute that junk and die. | |
2086 | * | |
2087 | * So to avoid that we reset the context images upon resume. For | |
2088 | * simplicity, we just zero everything out. | |
2089 | */ | |
829a0af2 | 2090 | list_for_each_entry(ctx, &dev_priv->contexts.list, link) { |
3b3f1650 | 2091 | for_each_engine(engine, dev_priv, id) { |
bafb2f7d CW |
2092 | struct intel_context *ce = &ctx->engine[engine->id]; |
2093 | u32 *reg; | |
3e5b6f05 | 2094 | |
bafb2f7d CW |
2095 | if (!ce->state) |
2096 | continue; | |
7d774cac | 2097 | |
bafb2f7d CW |
2098 | reg = i915_gem_object_pin_map(ce->state->obj, |
2099 | I915_MAP_WB); | |
2100 | if (WARN_ON(IS_ERR(reg))) | |
2101 | continue; | |
3e5b6f05 | 2102 | |
bafb2f7d CW |
2103 | reg += LRC_STATE_PN * PAGE_SIZE / sizeof(*reg); |
2104 | reg[CTX_RING_HEAD+1] = 0; | |
2105 | reg[CTX_RING_TAIL+1] = 0; | |
3e5b6f05 | 2106 | |
a4f5ea64 | 2107 | ce->state->obj->mm.dirty = true; |
bafb2f7d | 2108 | i915_gem_object_unpin_map(ce->state->obj); |
3e5b6f05 | 2109 | |
e6ba9992 | 2110 | intel_ring_reset(ce->ring, 0); |
bafb2f7d | 2111 | } |
3e5b6f05 TD |
2112 | } |
2113 | } |