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b20385f1 OM |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * Michel Thierry <michel.thierry@intel.com> | |
26 | * Thomas Daniel <thomas.daniel@intel.com> | |
27 | * Oscar Mateo <oscar.mateo@intel.com> | |
28 | * | |
29 | */ | |
30 | ||
73e4d07f OM |
31 | /** |
32 | * DOC: Logical Rings, Logical Ring Contexts and Execlists | |
33 | * | |
34 | * Motivation: | |
b20385f1 OM |
35 | * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". |
36 | * These expanded contexts enable a number of new abilities, especially | |
37 | * "Execlists" (also implemented in this file). | |
38 | * | |
73e4d07f OM |
39 | * One of the main differences with the legacy HW contexts is that logical |
40 | * ring contexts incorporate many more things to the context's state, like | |
41 | * PDPs or ringbuffer control registers: | |
42 | * | |
43 | * The reason why PDPs are included in the context is straightforward: as | |
44 | * PPGTTs (per-process GTTs) are actually per-context, having the PDPs | |
45 | * contained there mean you don't need to do a ppgtt->switch_mm yourself, | |
46 | * instead, the GPU will do it for you on the context switch. | |
47 | * | |
48 | * But, what about the ringbuffer control registers (head, tail, etc..)? | |
49 | * shouldn't we just need a set of those per engine command streamer? This is | |
50 | * where the name "Logical Rings" starts to make sense: by virtualizing the | |
51 | * rings, the engine cs shifts to a new "ring buffer" with every context | |
52 | * switch. When you want to submit a workload to the GPU you: A) choose your | |
53 | * context, B) find its appropriate virtualized ring, C) write commands to it | |
54 | * and then, finally, D) tell the GPU to switch to that context. | |
55 | * | |
56 | * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch | |
57 | * to a contexts is via a context execution list, ergo "Execlists". | |
58 | * | |
59 | * LRC implementation: | |
60 | * Regarding the creation of contexts, we have: | |
61 | * | |
62 | * - One global default context. | |
63 | * - One local default context for each opened fd. | |
64 | * - One local extra context for each context create ioctl call. | |
65 | * | |
66 | * Now that ringbuffers belong per-context (and not per-engine, like before) | |
67 | * and that contexts are uniquely tied to a given engine (and not reusable, | |
68 | * like before) we need: | |
69 | * | |
70 | * - One ringbuffer per-engine inside each context. | |
71 | * - One backing object per-engine inside each context. | |
72 | * | |
73 | * The global default context starts its life with these new objects fully | |
74 | * allocated and populated. The local default context for each opened fd is | |
75 | * more complex, because we don't know at creation time which engine is going | |
76 | * to use them. To handle this, we have implemented a deferred creation of LR | |
77 | * contexts: | |
78 | * | |
79 | * The local context starts its life as a hollow or blank holder, that only | |
80 | * gets populated for a given engine once we receive an execbuffer. If later | |
81 | * on we receive another execbuffer ioctl for the same context but a different | |
82 | * engine, we allocate/populate a new ringbuffer and context backing object and | |
83 | * so on. | |
84 | * | |
85 | * Finally, regarding local contexts created using the ioctl call: as they are | |
86 | * only allowed with the render ring, we can allocate & populate them right | |
87 | * away (no need to defer anything, at least for now). | |
88 | * | |
89 | * Execlists implementation: | |
b20385f1 OM |
90 | * Execlists are the new method by which, on gen8+ hardware, workloads are |
91 | * submitted for execution (as opposed to the legacy, ringbuffer-based, method). | |
73e4d07f OM |
92 | * This method works as follows: |
93 | * | |
94 | * When a request is committed, its commands (the BB start and any leading or | |
95 | * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer | |
96 | * for the appropriate context. The tail pointer in the hardware context is not | |
97 | * updated at this time, but instead, kept by the driver in the ringbuffer | |
98 | * structure. A structure representing this request is added to a request queue | |
99 | * for the appropriate engine: this structure contains a copy of the context's | |
100 | * tail after the request was written to the ring buffer and a pointer to the | |
101 | * context itself. | |
102 | * | |
103 | * If the engine's request queue was empty before the request was added, the | |
104 | * queue is processed immediately. Otherwise the queue will be processed during | |
105 | * a context switch interrupt. In any case, elements on the queue will get sent | |
106 | * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a | |
107 | * globally unique 20-bits submission ID. | |
108 | * | |
109 | * When execution of a request completes, the GPU updates the context status | |
110 | * buffer with a context complete event and generates a context switch interrupt. | |
111 | * During the interrupt handling, the driver examines the events in the buffer: | |
112 | * for each context complete event, if the announced ID matches that on the head | |
113 | * of the request queue, then that request is retired and removed from the queue. | |
114 | * | |
115 | * After processing, if any requests were retired and the queue is not empty | |
116 | * then a new execution list can be submitted. The two requests at the front of | |
117 | * the queue are next to be submitted but since a context may not occur twice in | |
118 | * an execution list, if subsequent requests have the same ID as the first then | |
119 | * the two requests must be combined. This is done simply by discarding requests | |
120 | * at the head of the queue until either only one requests is left (in which case | |
121 | * we use a NULL second context) or the first two requests have unique IDs. | |
122 | * | |
123 | * By always executing the first two requests in the queue the driver ensures | |
124 | * that the GPU is kept as busy as possible. In the case where a single context | |
125 | * completes but a second context is still executing, the request for this second | |
126 | * context will be at the head of the queue when we remove the first one. This | |
127 | * request will then be resubmitted along with a new request for a different context, | |
128 | * which will cause the hardware to continue executing the second request and queue | |
129 | * the new request (the GPU detects the condition of a context getting preempted | |
130 | * with the same context and optimizes the context switch flow by not doing | |
131 | * preemption, but just sampling the new tail pointer). | |
132 | * | |
b20385f1 | 133 | */ |
27af5eea | 134 | #include <linux/interrupt.h> |
b20385f1 | 135 | |
b20385f1 OM |
136 | #include <drm/i915_drm.h> |
137 | #include "i915_drv.h" | |
7c2fa7fa | 138 | #include "i915_gem_render_state.h" |
eb8d0f5a | 139 | #include "i915_reset.h" |
bc4237ec | 140 | #include "i915_vgpu.h" |
578f1ac6 | 141 | #include "intel_lrc_reg.h" |
3bbaba0c | 142 | #include "intel_mocs.h" |
7d3c425f | 143 | #include "intel_workarounds.h" |
127f1003 | 144 | |
e981e7b1 TD |
145 | #define RING_EXECLIST_QFULL (1 << 0x2) |
146 | #define RING_EXECLIST1_VALID (1 << 0x3) | |
147 | #define RING_EXECLIST0_VALID (1 << 0x4) | |
148 | #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) | |
149 | #define RING_EXECLIST1_ACTIVE (1 << 0x11) | |
150 | #define RING_EXECLIST0_ACTIVE (1 << 0x12) | |
151 | ||
152 | #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) | |
153 | #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) | |
154 | #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) | |
155 | #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) | |
156 | #define GEN8_CTX_STATUS_COMPLETE (1 << 4) | |
157 | #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) | |
8670d6f9 | 158 | |
70c2a24d | 159 | #define GEN8_CTX_STATUS_COMPLETED_MASK \ |
d8747afb | 160 | (GEN8_CTX_STATUS_COMPLETE | GEN8_CTX_STATUS_PREEMPTED) |
70c2a24d | 161 | |
0e93cdd4 CW |
162 | /* Typical size of the average request (2 pipecontrols and a MI_BB) */ |
163 | #define EXECLISTS_REQUEST_SIZE 64 /* bytes */ | |
a3aabe86 | 164 | #define WA_TAIL_DWORDS 2 |
7e4992ac | 165 | #define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS) |
a3aabe86 | 166 | |
e2efd130 | 167 | static int execlists_context_deferred_alloc(struct i915_gem_context *ctx, |
1fc44d9b CW |
168 | struct intel_engine_cs *engine, |
169 | struct intel_context *ce); | |
a3aabe86 CW |
170 | static void execlists_init_reg_state(u32 *reg_state, |
171 | struct i915_gem_context *ctx, | |
172 | struct intel_engine_cs *engine, | |
173 | struct intel_ring *ring); | |
7ba717cf | 174 | |
0ca88ba0 CW |
175 | static inline u32 intel_hws_seqno_address(struct intel_engine_cs *engine) |
176 | { | |
177 | return (i915_ggtt_offset(engine->status_page.vma) + | |
178 | I915_GEM_HWS_INDEX_ADDR); | |
179 | } | |
180 | ||
f6322edd CW |
181 | static inline struct i915_priolist *to_priolist(struct rb_node *rb) |
182 | { | |
183 | return rb_entry(rb, struct i915_priolist, node); | |
184 | } | |
185 | ||
186 | static inline int rq_prio(const struct i915_request *rq) | |
187 | { | |
b7268c5e | 188 | return rq->sched.attr.priority; |
f6322edd CW |
189 | } |
190 | ||
191 | static inline bool need_preempt(const struct intel_engine_cs *engine, | |
192 | const struct i915_request *last, | |
193 | int prio) | |
194 | { | |
2a694feb | 195 | return (intel_engine_has_preemption(engine) && |
c5ce3b8d CW |
196 | __execlists_need_preempt(prio, rq_prio(last)) && |
197 | !i915_request_completed(last)); | |
f6322edd CW |
198 | } |
199 | ||
1fc44d9b | 200 | /* |
ca82580c TU |
201 | * The context descriptor encodes various attributes of a context, |
202 | * including its GTT address and some flags. Because it's fairly | |
203 | * expensive to calculate, we'll just do it once and cache the result, | |
204 | * which remains valid until the context is unpinned. | |
205 | * | |
6e5248b5 DV |
206 | * This is what a descriptor looks like, from LSB to MSB:: |
207 | * | |
2355cf08 | 208 | * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template) |
6e5248b5 | 209 | * bits 12-31: LRCA, GTT address of (the HWSP of) this context |
218b5000 | 210 | * bits 32-52: ctx ID, a globally unique tag (highest bit used by GuC) |
6e5248b5 DV |
211 | * bits 53-54: mbz, reserved for use by hardware |
212 | * bits 55-63: group ID, currently unused and set to 0 | |
ac52da6a DCS |
213 | * |
214 | * Starting from Gen11, the upper dword of the descriptor has a new format: | |
215 | * | |
216 | * bits 32-36: reserved | |
217 | * bits 37-47: SW context ID | |
218 | * bits 48:53: engine instance | |
219 | * bit 54: mbz, reserved for use by hardware | |
220 | * bits 55-60: SW counter | |
221 | * bits 61-63: engine class | |
222 | * | |
223 | * engine info, SW context ID and SW counter need to form a unique number | |
224 | * (Context ID) per lrc. | |
73e4d07f | 225 | */ |
ca82580c | 226 | static void |
e2efd130 | 227 | intel_lr_context_descriptor_update(struct i915_gem_context *ctx, |
1fc44d9b CW |
228 | struct intel_engine_cs *engine, |
229 | struct intel_context *ce) | |
84b790f8 | 230 | { |
7069b144 | 231 | u64 desc; |
84b790f8 | 232 | |
ac52da6a DCS |
233 | BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (BIT(GEN8_CTX_ID_WIDTH))); |
234 | BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > (BIT(GEN11_SW_CTX_ID_WIDTH))); | |
84b790f8 | 235 | |
2355cf08 | 236 | desc = ctx->desc_template; /* bits 0-11 */ |
ac52da6a DCS |
237 | GEM_BUG_ON(desc & GENMASK_ULL(63, 12)); |
238 | ||
0b29c75a | 239 | desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE; |
9021ad03 | 240 | /* bits 12-31 */ |
ac52da6a DCS |
241 | GEM_BUG_ON(desc & GENMASK_ULL(63, 32)); |
242 | ||
61d5676b LL |
243 | /* |
244 | * The following 32bits are copied into the OA reports (dword 2). | |
245 | * Consider updating oa_get_render_ctx_id in i915_perf.c when changing | |
246 | * anything below. | |
247 | */ | |
ac52da6a DCS |
248 | if (INTEL_GEN(ctx->i915) >= 11) { |
249 | GEM_BUG_ON(ctx->hw_id >= BIT(GEN11_SW_CTX_ID_WIDTH)); | |
250 | desc |= (u64)ctx->hw_id << GEN11_SW_CTX_ID_SHIFT; | |
251 | /* bits 37-47 */ | |
252 | ||
253 | desc |= (u64)engine->instance << GEN11_ENGINE_INSTANCE_SHIFT; | |
254 | /* bits 48-53 */ | |
255 | ||
256 | /* TODO: decide what to do with SW counter (bits 55-60) */ | |
257 | ||
258 | desc |= (u64)engine->class << GEN11_ENGINE_CLASS_SHIFT; | |
259 | /* bits 61-63 */ | |
260 | } else { | |
261 | GEM_BUG_ON(ctx->hw_id >= BIT(GEN8_CTX_ID_WIDTH)); | |
262 | desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */ | |
263 | } | |
5af05fef | 264 | |
9021ad03 | 265 | ce->lrc_desc = desc; |
5af05fef MT |
266 | } |
267 | ||
e61e0f51 | 268 | static void unwind_wa_tail(struct i915_request *rq) |
7e4992ac CW |
269 | { |
270 | rq->tail = intel_ring_wrap(rq->ring, rq->wa_tail - WA_TAIL_BYTES); | |
271 | assert_ring_tail_valid(rq->ring, rq->tail); | |
272 | } | |
273 | ||
eb8d0f5a CW |
274 | static struct i915_request * |
275 | __unwind_incomplete_requests(struct intel_engine_cs *engine) | |
7e4992ac | 276 | { |
b16c7651 | 277 | struct i915_request *rq, *rn, *active = NULL; |
85f5e1f3 | 278 | struct list_head *uninitialized_var(pl); |
b16c7651 | 279 | int prio = I915_PRIORITY_INVALID | I915_PRIORITY_NEWCLIENT; |
7e4992ac | 280 | |
a89d1f92 | 281 | lockdep_assert_held(&engine->timeline.lock); |
7e4992ac CW |
282 | |
283 | list_for_each_entry_safe_reverse(rq, rn, | |
a89d1f92 | 284 | &engine->timeline.requests, |
7e4992ac | 285 | link) { |
e61e0f51 | 286 | if (i915_request_completed(rq)) |
b16c7651 | 287 | break; |
7e4992ac | 288 | |
e61e0f51 | 289 | __i915_request_unsubmit(rq); |
7e4992ac CW |
290 | unwind_wa_tail(rq); |
291 | ||
bc2477f7 CW |
292 | GEM_BUG_ON(rq->hw_context->active); |
293 | ||
f6322edd | 294 | GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID); |
b16c7651 CW |
295 | if (rq_prio(rq) != prio) { |
296 | prio = rq_prio(rq); | |
e2f3496e | 297 | pl = i915_sched_lookup_priolist(engine, prio); |
097a9481 | 298 | } |
8db05f59 | 299 | GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); |
097a9481 | 300 | |
85f5e1f3 | 301 | list_add(&rq->sched.link, pl); |
b16c7651 CW |
302 | |
303 | active = rq; | |
304 | } | |
305 | ||
306 | /* | |
307 | * The active request is now effectively the start of a new client | |
308 | * stream, so give it the equivalent small priority bump to prevent | |
309 | * it being gazumped a second time by another peer. | |
310 | */ | |
311 | if (!(prio & I915_PRIORITY_NEWCLIENT)) { | |
312 | prio |= I915_PRIORITY_NEWCLIENT; | |
6e062b60 | 313 | active->sched.attr.priority = prio; |
b16c7651 | 314 | list_move_tail(&active->sched.link, |
e2f3496e | 315 | i915_sched_lookup_priolist(engine, prio)); |
7e4992ac | 316 | } |
eb8d0f5a CW |
317 | |
318 | return active; | |
7e4992ac CW |
319 | } |
320 | ||
c41937fd | 321 | void |
a4598d17 MW |
322 | execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists) |
323 | { | |
324 | struct intel_engine_cs *engine = | |
325 | container_of(execlists, typeof(*engine), execlists); | |
326 | ||
a4598d17 | 327 | __unwind_incomplete_requests(engine); |
a4598d17 MW |
328 | } |
329 | ||
bbd6c47e | 330 | static inline void |
e61e0f51 | 331 | execlists_context_status_change(struct i915_request *rq, unsigned long status) |
84b790f8 | 332 | { |
bbd6c47e CW |
333 | /* |
334 | * Only used when GVT-g is enabled now. When GVT-g is disabled, | |
335 | * The compiler should eliminate this function as dead-code. | |
336 | */ | |
337 | if (!IS_ENABLED(CONFIG_DRM_I915_GVT)) | |
338 | return; | |
6daccb0b | 339 | |
3fc03069 CD |
340 | atomic_notifier_call_chain(&rq->engine->context_status_notifier, |
341 | status, rq); | |
84b790f8 BW |
342 | } |
343 | ||
f2605207 CW |
344 | inline void |
345 | execlists_user_begin(struct intel_engine_execlists *execlists, | |
346 | const struct execlist_port *port) | |
347 | { | |
348 | execlists_set_active_once(execlists, EXECLISTS_ACTIVE_USER); | |
349 | } | |
350 | ||
351 | inline void | |
352 | execlists_user_end(struct intel_engine_execlists *execlists) | |
353 | { | |
354 | execlists_clear_active(execlists, EXECLISTS_ACTIVE_USER); | |
355 | } | |
356 | ||
73fd9d38 | 357 | static inline void |
e61e0f51 | 358 | execlists_context_schedule_in(struct i915_request *rq) |
73fd9d38 | 359 | { |
bc2477f7 CW |
360 | GEM_BUG_ON(rq->hw_context->active); |
361 | ||
73fd9d38 | 362 | execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN); |
30e17b78 | 363 | intel_engine_context_in(rq->engine); |
bc2477f7 | 364 | rq->hw_context->active = rq->engine; |
73fd9d38 TU |
365 | } |
366 | ||
367 | static inline void | |
b9b77426 | 368 | execlists_context_schedule_out(struct i915_request *rq, unsigned long status) |
73fd9d38 | 369 | { |
bc2477f7 | 370 | rq->hw_context->active = NULL; |
30e17b78 | 371 | intel_engine_context_out(rq->engine); |
b9b77426 CW |
372 | execlists_context_status_change(rq, status); |
373 | trace_i915_request_out(rq); | |
73fd9d38 TU |
374 | } |
375 | ||
e61e0f51 | 376 | static u64 execlists_update_context(struct i915_request *rq) |
ae1250b9 | 377 | { |
1fc44d9b | 378 | struct intel_context *ce = rq->hw_context; |
ae1250b9 | 379 | |
e8894267 CW |
380 | ce->lrc_reg_state[CTX_RING_TAIL + 1] = |
381 | intel_ring_set_tail(rq->ring, rq->tail); | |
70c2a24d | 382 | |
987abd5c CW |
383 | /* |
384 | * Make sure the context image is complete before we submit it to HW. | |
385 | * | |
386 | * Ostensibly, writes (including the WCB) should be flushed prior to | |
387 | * an uncached write such as our mmio register access, the empirical | |
388 | * evidence (esp. on Braswell) suggests that the WC write into memory | |
389 | * may not be visible to the HW prior to the completion of the UC | |
390 | * register write and that we may begin execution from the context | |
391 | * before its image is complete leading to invalid PD chasing. | |
490b8c65 CW |
392 | * |
393 | * Furthermore, Braswell, at least, wants a full mb to be sure that | |
394 | * the writes are coherent in memory (visible to the GPU) prior to | |
395 | * execution, and not just visible to other CPUs (as is the result of | |
396 | * wmb). | |
987abd5c | 397 | */ |
490b8c65 | 398 | mb(); |
70c2a24d | 399 | return ce->lrc_desc; |
ae1250b9 OM |
400 | } |
401 | ||
05f0addd | 402 | static inline void write_desc(struct intel_engine_execlists *execlists, u64 desc, u32 port) |
beecec90 | 403 | { |
05f0addd TD |
404 | if (execlists->ctrl_reg) { |
405 | writel(lower_32_bits(desc), execlists->submit_reg + port * 2); | |
406 | writel(upper_32_bits(desc), execlists->submit_reg + port * 2 + 1); | |
407 | } else { | |
408 | writel(upper_32_bits(desc), execlists->submit_reg); | |
409 | writel(lower_32_bits(desc), execlists->submit_reg); | |
410 | } | |
beecec90 CW |
411 | } |
412 | ||
70c2a24d | 413 | static void execlists_submit_ports(struct intel_engine_cs *engine) |
bbd6c47e | 414 | { |
05f0addd TD |
415 | struct intel_engine_execlists *execlists = &engine->execlists; |
416 | struct execlist_port *port = execlists->port; | |
77f0d0e9 | 417 | unsigned int n; |
bbd6c47e | 418 | |
d78d3343 CW |
419 | /* |
420 | * We can skip acquiring intel_runtime_pm_get() here as it was taken | |
421 | * on our behalf by the request (see i915_gem_mark_busy()) and it will | |
422 | * not be relinquished until the device is idle (see | |
423 | * i915_gem_idle_work_handler()). As a precaution, we make sure | |
424 | * that all ELSP are drained i.e. we have processed the CSB, | |
425 | * before allowing ourselves to idle and calling intel_runtime_pm_put(). | |
426 | */ | |
427 | GEM_BUG_ON(!engine->i915->gt.awake); | |
428 | ||
05f0addd TD |
429 | /* |
430 | * ELSQ note: the submit queue is not cleared after being submitted | |
431 | * to the HW so we need to make sure we always clean it up. This is | |
432 | * currently ensured by the fact that we always write the same number | |
433 | * of elsq entries, keep this in mind before changing the loop below. | |
434 | */ | |
435 | for (n = execlists_num_ports(execlists); n--; ) { | |
e61e0f51 | 436 | struct i915_request *rq; |
77f0d0e9 CW |
437 | unsigned int count; |
438 | u64 desc; | |
439 | ||
440 | rq = port_unpack(&port[n], &count); | |
441 | if (rq) { | |
442 | GEM_BUG_ON(count > !n); | |
443 | if (!count++) | |
73fd9d38 | 444 | execlists_context_schedule_in(rq); |
77f0d0e9 CW |
445 | port_set(&port[n], port_pack(rq, count)); |
446 | desc = execlists_update_context(rq); | |
447 | GEM_DEBUG_EXEC(port[n].context_id = upper_32_bits(desc)); | |
bccd3b83 | 448 | |
3adac468 | 449 | GEM_TRACE("%s in[%d]: ctx=%d.%d, global=%d (fence %llx:%lld) (current %d:%d), prio=%d\n", |
bccd3b83 | 450 | engine->name, n, |
16c8619a | 451 | port[n].context_id, count, |
f6322edd | 452 | rq->global_seqno, |
0c5c7df3 | 453 | rq->fence.context, rq->fence.seqno, |
3adac468 | 454 | hwsp_seqno(rq), |
e7702760 | 455 | intel_engine_get_seqno(engine), |
f6322edd | 456 | rq_prio(rq)); |
77f0d0e9 CW |
457 | } else { |
458 | GEM_BUG_ON(!n); | |
459 | desc = 0; | |
460 | } | |
bbd6c47e | 461 | |
05f0addd | 462 | write_desc(execlists, desc, n); |
77f0d0e9 | 463 | } |
05f0addd TD |
464 | |
465 | /* we need to manually load the submit queue */ | |
466 | if (execlists->ctrl_reg) | |
467 | writel(EL_CTRL_LOAD, execlists->ctrl_reg); | |
468 | ||
469 | execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK); | |
bbd6c47e CW |
470 | } |
471 | ||
1fc44d9b | 472 | static bool ctx_single_port_submission(const struct intel_context *ce) |
84b790f8 | 473 | { |
70c2a24d | 474 | return (IS_ENABLED(CONFIG_DRM_I915_GVT) && |
1fc44d9b | 475 | i915_gem_context_force_single_submission(ce->gem_context)); |
70c2a24d | 476 | } |
84b790f8 | 477 | |
1fc44d9b CW |
478 | static bool can_merge_ctx(const struct intel_context *prev, |
479 | const struct intel_context *next) | |
70c2a24d CW |
480 | { |
481 | if (prev != next) | |
482 | return false; | |
26720ab9 | 483 | |
70c2a24d CW |
484 | if (ctx_single_port_submission(prev)) |
485 | return false; | |
26720ab9 | 486 | |
70c2a24d | 487 | return true; |
84b790f8 BW |
488 | } |
489 | ||
e61e0f51 | 490 | static void port_assign(struct execlist_port *port, struct i915_request *rq) |
77f0d0e9 CW |
491 | { |
492 | GEM_BUG_ON(rq == port_request(port)); | |
493 | ||
494 | if (port_isset(port)) | |
e61e0f51 | 495 | i915_request_put(port_request(port)); |
77f0d0e9 | 496 | |
e61e0f51 | 497 | port_set(port, port_pack(i915_request_get(rq), port_count(port))); |
77f0d0e9 CW |
498 | } |
499 | ||
beecec90 CW |
500 | static void inject_preempt_context(struct intel_engine_cs *engine) |
501 | { | |
05f0addd | 502 | struct intel_engine_execlists *execlists = &engine->execlists; |
beecec90 | 503 | struct intel_context *ce = |
ab82a063 | 504 | to_intel_context(engine->i915->preempt_context, engine); |
beecec90 CW |
505 | unsigned int n; |
506 | ||
05f0addd | 507 | GEM_BUG_ON(execlists->preempt_complete_status != |
d6376374 | 508 | upper_32_bits(ce->lrc_desc)); |
09b1a4e4 | 509 | |
f6322edd CW |
510 | /* |
511 | * Switch to our empty preempt context so | |
512 | * the state of the GPU is known (idle). | |
513 | */ | |
16a87394 | 514 | GEM_TRACE("%s\n", engine->name); |
05f0addd TD |
515 | for (n = execlists_num_ports(execlists); --n; ) |
516 | write_desc(execlists, 0, n); | |
517 | ||
518 | write_desc(execlists, ce->lrc_desc, n); | |
519 | ||
520 | /* we need to manually load the submit queue */ | |
521 | if (execlists->ctrl_reg) | |
522 | writel(EL_CTRL_LOAD, execlists->ctrl_reg); | |
beecec90 | 523 | |
ef2fb720 CW |
524 | execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK); |
525 | execlists_set_active(execlists, EXECLISTS_ACTIVE_PREEMPT); | |
526 | } | |
527 | ||
528 | static void complete_preempt_context(struct intel_engine_execlists *execlists) | |
529 | { | |
530 | GEM_BUG_ON(!execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT)); | |
531 | ||
0f6b79fa CW |
532 | if (inject_preempt_hang(execlists)) |
533 | return; | |
534 | ||
ef2fb720 | 535 | execlists_cancel_port_requests(execlists); |
9512f985 CW |
536 | __unwind_incomplete_requests(container_of(execlists, |
537 | struct intel_engine_cs, | |
538 | execlists)); | |
beecec90 CW |
539 | } |
540 | ||
9512f985 | 541 | static void execlists_dequeue(struct intel_engine_cs *engine) |
acdd884a | 542 | { |
7a62cc61 MK |
543 | struct intel_engine_execlists * const execlists = &engine->execlists; |
544 | struct execlist_port *port = execlists->port; | |
76e70087 MK |
545 | const struct execlist_port * const last_port = |
546 | &execlists->port[execlists->port_mask]; | |
e61e0f51 | 547 | struct i915_request *last = port_request(port); |
20311bd3 | 548 | struct rb_node *rb; |
70c2a24d CW |
549 | bool submit = false; |
550 | ||
9512f985 CW |
551 | /* |
552 | * Hardware submission is through 2 ports. Conceptually each port | |
70c2a24d CW |
553 | * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is |
554 | * static for a context, and unique to each, so we only execute | |
555 | * requests belonging to a single context from each ring. RING_HEAD | |
556 | * is maintained by the CS in the context image, it marks the place | |
557 | * where it got up to last time, and through RING_TAIL we tell the CS | |
558 | * where we want to execute up to this time. | |
559 | * | |
560 | * In this list the requests are in order of execution. Consecutive | |
561 | * requests from the same context are adjacent in the ringbuffer. We | |
562 | * can combine these requests into a single RING_TAIL update: | |
563 | * | |
564 | * RING_HEAD...req1...req2 | |
565 | * ^- RING_TAIL | |
566 | * since to execute req2 the CS must first execute req1. | |
567 | * | |
568 | * Our goal then is to point each port to the end of a consecutive | |
569 | * sequence of requests as being the most optimal (fewest wake ups | |
570 | * and context switches) submission. | |
779949f4 | 571 | */ |
acdd884a | 572 | |
beecec90 CW |
573 | if (last) { |
574 | /* | |
575 | * Don't resubmit or switch until all outstanding | |
576 | * preemptions (lite-restore) are seen. Then we | |
577 | * know the next preemption status we see corresponds | |
578 | * to this ELSP update. | |
579 | */ | |
eed7ec52 CW |
580 | GEM_BUG_ON(!execlists_is_active(execlists, |
581 | EXECLISTS_ACTIVE_USER)); | |
ba74cb10 | 582 | GEM_BUG_ON(!port_count(&port[0])); |
beecec90 | 583 | |
ba74cb10 MT |
584 | /* |
585 | * If we write to ELSP a second time before the HW has had | |
586 | * a chance to respond to the previous write, we can confuse | |
587 | * the HW and hit "undefined behaviour". After writing to ELSP, | |
588 | * we must then wait until we see a context-switch event from | |
589 | * the HW to indicate that it has had a chance to respond. | |
590 | */ | |
591 | if (!execlists_is_active(execlists, EXECLISTS_ACTIVE_HWACK)) | |
0b02befa | 592 | return; |
ba74cb10 | 593 | |
f6322edd | 594 | if (need_preempt(engine, last, execlists->queue_priority)) { |
beecec90 | 595 | inject_preempt_context(engine); |
0b02befa | 596 | return; |
beecec90 | 597 | } |
f6322edd CW |
598 | |
599 | /* | |
600 | * In theory, we could coalesce more requests onto | |
601 | * the second port (the first port is active, with | |
602 | * no preemptions pending). However, that means we | |
603 | * then have to deal with the possible lite-restore | |
604 | * of the second port (as we submit the ELSP, there | |
605 | * may be a context-switch) but also we may complete | |
606 | * the resubmission before the context-switch. Ergo, | |
607 | * coalescing onto the second port will cause a | |
608 | * preemption event, but we cannot predict whether | |
609 | * that will affect port[0] or port[1]. | |
610 | * | |
611 | * If the second port is already active, we can wait | |
612 | * until the next context-switch before contemplating | |
613 | * new requests. The GPU will be busy and we should be | |
614 | * able to resubmit the new ELSP before it idles, | |
615 | * avoiding pipeline bubbles (momentary pauses where | |
616 | * the driver is unable to keep up the supply of new | |
617 | * work). However, we have to double check that the | |
618 | * priorities of the ports haven't been switch. | |
619 | */ | |
620 | if (port_count(&port[1])) | |
0b02befa | 621 | return; |
f6322edd CW |
622 | |
623 | /* | |
624 | * WaIdleLiteRestore:bdw,skl | |
625 | * Apply the wa NOOPs to prevent | |
626 | * ring:HEAD == rq:TAIL as we resubmit the | |
85474441 | 627 | * request. See gen8_emit_fini_breadcrumb() for |
f6322edd CW |
628 | * where we prepare the padding after the |
629 | * end of the request. | |
630 | */ | |
631 | last->tail = last->wa_tail; | |
beecec90 CW |
632 | } |
633 | ||
655250a8 | 634 | while ((rb = rb_first_cached(&execlists->queue))) { |
f6322edd | 635 | struct i915_priolist *p = to_priolist(rb); |
e61e0f51 | 636 | struct i915_request *rq, *rn; |
85f5e1f3 | 637 | int i; |
6c067579 | 638 | |
85f5e1f3 | 639 | priolist_for_each_request_consume(rq, rn, p, i) { |
6e062b60 CW |
640 | GEM_BUG_ON(last && |
641 | need_preempt(engine, last, rq_prio(rq))); | |
642 | ||
6c067579 CW |
643 | /* |
644 | * Can we combine this request with the current port? | |
645 | * It has to be the same context/ringbuffer and not | |
646 | * have any exceptions (e.g. GVT saying never to | |
647 | * combine contexts). | |
648 | * | |
649 | * If we can combine the requests, we can execute both | |
650 | * by updating the RING_TAIL to point to the end of the | |
651 | * second request, and so we never need to tell the | |
652 | * hardware about the first. | |
70c2a24d | 653 | */ |
1fc44d9b CW |
654 | if (last && |
655 | !can_merge_ctx(rq->hw_context, last->hw_context)) { | |
6c067579 CW |
656 | /* |
657 | * If we are on the second port and cannot | |
658 | * combine this request with the last, then we | |
659 | * are done. | |
660 | */ | |
85f5e1f3 | 661 | if (port == last_port) |
6c067579 | 662 | goto done; |
6c067579 CW |
663 | |
664 | /* | |
665 | * If GVT overrides us we only ever submit | |
666 | * port[0], leaving port[1] empty. Note that we | |
667 | * also have to be careful that we don't queue | |
668 | * the same context (even though a different | |
669 | * request) to the second port. | |
670 | */ | |
1fc44d9b | 671 | if (ctx_single_port_submission(last->hw_context) || |
85f5e1f3 | 672 | ctx_single_port_submission(rq->hw_context)) |
6c067579 | 673 | goto done; |
6c067579 | 674 | |
1fc44d9b | 675 | GEM_BUG_ON(last->hw_context == rq->hw_context); |
6c067579 CW |
676 | |
677 | if (submit) | |
678 | port_assign(port, last); | |
679 | port++; | |
7a62cc61 MK |
680 | |
681 | GEM_BUG_ON(port_isset(port)); | |
6c067579 | 682 | } |
70c2a24d | 683 | |
85f5e1f3 CW |
684 | list_del_init(&rq->sched.link); |
685 | ||
e61e0f51 CW |
686 | __i915_request_submit(rq); |
687 | trace_i915_request_in(rq, port_index(port, execlists)); | |
85f5e1f3 | 688 | |
6c067579 CW |
689 | last = rq; |
690 | submit = true; | |
70c2a24d | 691 | } |
d55ac5bf | 692 | |
655250a8 | 693 | rb_erase_cached(&p->node, &execlists->queue); |
6c067579 | 694 | if (p->priority != I915_PRIORITY_NORMAL) |
c5cf9a91 | 695 | kmem_cache_free(engine->i915->priorities, p); |
f6322edd | 696 | } |
15c83c43 | 697 | |
6c067579 | 698 | done: |
15c83c43 CW |
699 | /* |
700 | * Here be a bit of magic! Or sleight-of-hand, whichever you prefer. | |
701 | * | |
702 | * We choose queue_priority such that if we add a request of greater | |
703 | * priority than this, we kick the submission tasklet to decide on | |
704 | * the right order of submitting the requests to hardware. We must | |
705 | * also be prepared to reorder requests as they are in-flight on the | |
706 | * HW. We derive the queue_priority then as the first "hole" in | |
707 | * the HW submission ports and if there are no available slots, | |
708 | * the priority of the lowest executing request, i.e. last. | |
709 | * | |
710 | * When we do receive a higher priority request ready to run from the | |
711 | * user, see queue_request(), the queue_priority is bumped to that | |
712 | * request triggering preemption on the next dequeue (or subsequent | |
713 | * interrupt for secondary ports). | |
714 | */ | |
715 | execlists->queue_priority = | |
716 | port != execlists->port ? rq_prio(last) : INT_MIN; | |
717 | ||
0b02befa | 718 | if (submit) { |
77f0d0e9 | 719 | port_assign(port, last); |
0b02befa CW |
720 | execlists_submit_ports(engine); |
721 | } | |
339ccd35 CW |
722 | |
723 | /* We must always keep the beast fed if we have work piled up */ | |
655250a8 CW |
724 | GEM_BUG_ON(rb_first_cached(&execlists->queue) && |
725 | !port_isset(execlists->port)); | |
339ccd35 | 726 | |
4413c474 CW |
727 | /* Re-evaluate the executing context setup after each preemptive kick */ |
728 | if (last) | |
f2605207 | 729 | execlists_user_begin(execlists, execlists->port); |
4413c474 | 730 | |
0b02befa CW |
731 | /* If the engine is now idle, so should be the flag; and vice versa. */ |
732 | GEM_BUG_ON(execlists_is_active(&engine->execlists, | |
733 | EXECLISTS_ACTIVE_USER) == | |
734 | !port_isset(engine->execlists.port)); | |
4413c474 CW |
735 | } |
736 | ||
c41937fd | 737 | void |
a4598d17 | 738 | execlists_cancel_port_requests(struct intel_engine_execlists * const execlists) |
cf4591d1 | 739 | { |
3f9e6cd8 | 740 | struct execlist_port *port = execlists->port; |
dc2279e1 | 741 | unsigned int num_ports = execlists_num_ports(execlists); |
cf4591d1 | 742 | |
3f9e6cd8 | 743 | while (num_ports-- && port_isset(port)) { |
e61e0f51 | 744 | struct i915_request *rq = port_request(port); |
7e44fc28 | 745 | |
3adac468 | 746 | GEM_TRACE("%s:port%u global=%d (fence %llx:%lld), (current %d:%d)\n", |
0c5c7df3 TU |
747 | rq->engine->name, |
748 | (unsigned int)(port - execlists->port), | |
749 | rq->global_seqno, | |
750 | rq->fence.context, rq->fence.seqno, | |
3adac468 | 751 | hwsp_seqno(rq), |
0c5c7df3 TU |
752 | intel_engine_get_seqno(rq->engine)); |
753 | ||
4a118ecb | 754 | GEM_BUG_ON(!execlists->active); |
b9b77426 CW |
755 | execlists_context_schedule_out(rq, |
756 | i915_request_completed(rq) ? | |
757 | INTEL_CONTEXT_SCHEDULE_OUT : | |
758 | INTEL_CONTEXT_SCHEDULE_PREEMPTED); | |
702791f7 | 759 | |
e61e0f51 | 760 | i915_request_put(rq); |
7e44fc28 | 761 | |
3f9e6cd8 CW |
762 | memset(port, 0, sizeof(*port)); |
763 | port++; | |
764 | } | |
eed7ec52 | 765 | |
0051163a | 766 | execlists_clear_all_active(execlists); |
cf4591d1 MK |
767 | } |
768 | ||
d8f50531 MK |
769 | static inline void |
770 | invalidate_csb_entries(const u32 *first, const u32 *last) | |
771 | { | |
772 | clflush((void *)first); | |
773 | clflush((void *)last); | |
774 | } | |
775 | ||
f4b58f04 CW |
776 | static void reset_csb_pointers(struct intel_engine_execlists *execlists) |
777 | { | |
46592892 CW |
778 | const unsigned int reset_value = GEN8_CSB_ENTRIES - 1; |
779 | ||
f4b58f04 CW |
780 | /* |
781 | * After a reset, the HW starts writing into CSB entry [0]. We | |
782 | * therefore have to set our HEAD pointer back one entry so that | |
783 | * the *first* entry we check is entry 0. To complicate this further, | |
784 | * as we don't wait for the first interrupt after reset, we have to | |
785 | * fake the HW write to point back to the last entry so that our | |
786 | * inline comparison of our cached head position against the last HW | |
787 | * write works even before the first interrupt. | |
788 | */ | |
46592892 CW |
789 | execlists->csb_head = reset_value; |
790 | WRITE_ONCE(*execlists->csb_write, reset_value); | |
d8f50531 MK |
791 | |
792 | invalidate_csb_entries(&execlists->csb_status[0], | |
793 | &execlists->csb_status[GEN8_CSB_ENTRIES - 1]); | |
f4b58f04 CW |
794 | } |
795 | ||
f1a498fa CW |
796 | static void nop_submission_tasklet(unsigned long data) |
797 | { | |
798 | /* The driver is wedged; don't process any more events. */ | |
799 | } | |
800 | ||
27a5f61b CW |
801 | static void execlists_cancel_requests(struct intel_engine_cs *engine) |
802 | { | |
b620e870 | 803 | struct intel_engine_execlists * const execlists = &engine->execlists; |
e61e0f51 | 804 | struct i915_request *rq, *rn; |
27a5f61b CW |
805 | struct rb_node *rb; |
806 | unsigned long flags; | |
27a5f61b | 807 | |
0c5c7df3 TU |
808 | GEM_TRACE("%s current %d\n", |
809 | engine->name, intel_engine_get_seqno(engine)); | |
963ddd63 | 810 | |
a3e38836 CW |
811 | /* |
812 | * Before we call engine->cancel_requests(), we should have exclusive | |
813 | * access to the submission state. This is arranged for us by the | |
814 | * caller disabling the interrupt generation, the tasklet and other | |
815 | * threads that may then access the same state, giving us a free hand | |
816 | * to reset state. However, we still need to let lockdep be aware that | |
817 | * we know this state may be accessed in hardirq context, so we | |
818 | * disable the irq around this manipulation and we want to keep | |
819 | * the spinlock focused on its duties and not accidentally conflate | |
820 | * coverage to the submission's irq state. (Similarly, although we | |
821 | * shouldn't need to disable irq around the manipulation of the | |
822 | * submission's irq state, we also wish to remind ourselves that | |
823 | * it is irq state.) | |
824 | */ | |
d8857d54 | 825 | spin_lock_irqsave(&engine->timeline.lock, flags); |
27a5f61b CW |
826 | |
827 | /* Cancel the requests on the HW and clear the ELSP tracker. */ | |
a4598d17 | 828 | execlists_cancel_port_requests(execlists); |
0051163a | 829 | execlists_user_end(execlists); |
27a5f61b CW |
830 | |
831 | /* Mark all executing requests as skipped. */ | |
a89d1f92 | 832 | list_for_each_entry(rq, &engine->timeline.requests, link) { |
27a5f61b | 833 | GEM_BUG_ON(!rq->global_seqno); |
3800960a | 834 | |
5013eb8c CW |
835 | if (!i915_request_signaled(rq)) |
836 | dma_fence_set_error(&rq->fence, -EIO); | |
3800960a | 837 | |
5013eb8c | 838 | i915_request_mark_complete(rq); |
27a5f61b CW |
839 | } |
840 | ||
841 | /* Flush the queued requests to the timeline list (for retiring). */ | |
655250a8 | 842 | while ((rb = rb_first_cached(&execlists->queue))) { |
f6322edd | 843 | struct i915_priolist *p = to_priolist(rb); |
85f5e1f3 | 844 | int i; |
27a5f61b | 845 | |
85f5e1f3 CW |
846 | priolist_for_each_request_consume(rq, rn, p, i) { |
847 | list_del_init(&rq->sched.link); | |
e61e0f51 | 848 | __i915_request_submit(rq); |
5013eb8c CW |
849 | dma_fence_set_error(&rq->fence, -EIO); |
850 | i915_request_mark_complete(rq); | |
27a5f61b CW |
851 | } |
852 | ||
655250a8 | 853 | rb_erase_cached(&p->node, &execlists->queue); |
27a5f61b CW |
854 | if (p->priority != I915_PRIORITY_NORMAL) |
855 | kmem_cache_free(engine->i915->priorities, p); | |
856 | } | |
857 | ||
3800960a CW |
858 | intel_write_status_page(engine, |
859 | I915_GEM_HWS_INDEX, | |
860 | intel_engine_last_submit(engine)); | |
861 | ||
27a5f61b CW |
862 | /* Remaining _unready_ requests will be nop'ed when submitted */ |
863 | ||
f6322edd | 864 | execlists->queue_priority = INT_MIN; |
655250a8 | 865 | execlists->queue = RB_ROOT_CACHED; |
3f9e6cd8 | 866 | GEM_BUG_ON(port_isset(execlists->port)); |
27a5f61b | 867 | |
f1a498fa CW |
868 | GEM_BUG_ON(__tasklet_is_enabled(&execlists->tasklet)); |
869 | execlists->tasklet.func = nop_submission_tasklet; | |
870 | ||
d8857d54 | 871 | spin_unlock_irqrestore(&engine->timeline.lock, flags); |
27a5f61b CW |
872 | } |
873 | ||
9512f985 CW |
874 | static inline bool |
875 | reset_in_progress(const struct intel_engine_execlists *execlists) | |
876 | { | |
877 | return unlikely(!__tasklet_is_enabled(&execlists->tasklet)); | |
878 | } | |
879 | ||
73377dbc | 880 | static void process_csb(struct intel_engine_cs *engine) |
e981e7b1 | 881 | { |
b620e870 | 882 | struct intel_engine_execlists * const execlists = &engine->execlists; |
f2605207 | 883 | struct execlist_port *port = execlists->port; |
bc4237ec CW |
884 | const u32 * const buf = execlists->csb_status; |
885 | u8 head, tail; | |
c6a2ac71 | 886 | |
bc4237ec CW |
887 | /* |
888 | * Note that csb_write, csb_status may be either in HWSP or mmio. | |
889 | * When reading from the csb_write mmio register, we have to be | |
890 | * careful to only use the GEN8_CSB_WRITE_PTR portion, which is | |
891 | * the low 4bits. As it happens we know the next 4bits are always | |
892 | * zero and so we can simply masked off the low u8 of the register | |
893 | * and treat it identically to reading from the HWSP (without having | |
894 | * to use explicit shifting and masking, and probably bifurcating | |
895 | * the code to handle the legacy mmio read). | |
896 | */ | |
897 | head = execlists->csb_head; | |
898 | tail = READ_ONCE(*execlists->csb_write); | |
899 | GEM_TRACE("%s cs-irq head=%d, tail=%d\n", engine->name, head, tail); | |
900 | if (unlikely(head == tail)) | |
901 | return; | |
b2209e62 | 902 | |
bc4237ec CW |
903 | /* |
904 | * Hopefully paired with a wmb() in HW! | |
905 | * | |
906 | * We must complete the read of the write pointer before any reads | |
907 | * from the CSB, so that we do not see stale values. Without an rmb | |
908 | * (lfence) the HW may speculatively perform the CSB[] reads *before* | |
909 | * we perform the READ_ONCE(*csb_write). | |
910 | */ | |
911 | rmb(); | |
767a983a | 912 | |
bc4237ec | 913 | do { |
8ea397fa CW |
914 | struct i915_request *rq; |
915 | unsigned int status; | |
916 | unsigned int count; | |
917 | ||
918 | if (++head == GEN8_CSB_ENTRIES) | |
919 | head = 0; | |
920 | ||
921 | /* | |
922 | * We are flying near dragons again. | |
923 | * | |
924 | * We hold a reference to the request in execlist_port[] | |
925 | * but no more than that. We are operating in softirq | |
926 | * context and so cannot hold any mutex or sleep. That | |
927 | * prevents us stopping the requests we are processing | |
928 | * in port[] from being retired simultaneously (the | |
929 | * breadcrumb will be complete before we see the | |
930 | * context-switch). As we only hold the reference to the | |
931 | * request, any pointer chasing underneath the request | |
932 | * is subject to a potential use-after-free. Thus we | |
933 | * store all of the bookkeeping within port[] as | |
934 | * required, and avoid using unguarded pointers beneath | |
935 | * request itself. The same applies to the atomic | |
936 | * status notifier. | |
937 | */ | |
938 | ||
8ea397fa CW |
939 | GEM_TRACE("%s csb[%d]: status=0x%08x:0x%08x, active=0x%x\n", |
940 | engine->name, head, | |
bc4237ec | 941 | buf[2 * head + 0], buf[2 * head + 1], |
8ea397fa CW |
942 | execlists->active); |
943 | ||
bc4237ec | 944 | status = buf[2 * head]; |
8ea397fa CW |
945 | if (status & (GEN8_CTX_STATUS_IDLE_ACTIVE | |
946 | GEN8_CTX_STATUS_PREEMPTED)) | |
947 | execlists_set_active(execlists, | |
948 | EXECLISTS_ACTIVE_HWACK); | |
949 | if (status & GEN8_CTX_STATUS_ACTIVE_IDLE) | |
950 | execlists_clear_active(execlists, | |
951 | EXECLISTS_ACTIVE_HWACK); | |
952 | ||
953 | if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK)) | |
954 | continue; | |
955 | ||
956 | /* We should never get a COMPLETED | IDLE_ACTIVE! */ | |
957 | GEM_BUG_ON(status & GEN8_CTX_STATUS_IDLE_ACTIVE); | |
958 | ||
959 | if (status & GEN8_CTX_STATUS_COMPLETE && | |
960 | buf[2*head + 1] == execlists->preempt_complete_status) { | |
961 | GEM_TRACE("%s preempt-idle\n", engine->name); | |
962 | complete_preempt_context(execlists); | |
963 | continue; | |
767a983a | 964 | } |
b620e870 | 965 | |
8ea397fa CW |
966 | if (status & GEN8_CTX_STATUS_PREEMPTED && |
967 | execlists_is_active(execlists, | |
968 | EXECLISTS_ACTIVE_PREEMPT)) | |
969 | continue; | |
4af0d727 | 970 | |
8ea397fa CW |
971 | GEM_BUG_ON(!execlists_is_active(execlists, |
972 | EXECLISTS_ACTIVE_USER)); | |
70c2a24d | 973 | |
8ea397fa | 974 | rq = port_unpack(port, &count); |
3adac468 | 975 | GEM_TRACE("%s out[0]: ctx=%d.%d, global=%d (fence %llx:%lld) (current %d:%d), prio=%d\n", |
8ea397fa CW |
976 | engine->name, |
977 | port->context_id, count, | |
978 | rq ? rq->global_seqno : 0, | |
979 | rq ? rq->fence.context : 0, | |
980 | rq ? rq->fence.seqno : 0, | |
3adac468 | 981 | rq ? hwsp_seqno(rq) : 0, |
8ea397fa CW |
982 | intel_engine_get_seqno(engine), |
983 | rq ? rq_prio(rq) : 0); | |
984 | ||
985 | /* Check the context/desc id for this event matches */ | |
986 | GEM_DEBUG_BUG_ON(buf[2 * head + 1] != port->context_id); | |
987 | ||
988 | GEM_BUG_ON(count == 0); | |
989 | if (--count == 0) { | |
73377dbc | 990 | /* |
8ea397fa CW |
991 | * On the final event corresponding to the |
992 | * submission of this context, we expect either | |
993 | * an element-switch event or a completion | |
994 | * event (and on completion, the active-idle | |
995 | * marker). No more preemptions, lite-restore | |
996 | * or otherwise. | |
2ffe80aa | 997 | */ |
8ea397fa CW |
998 | GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED); |
999 | GEM_BUG_ON(port_isset(&port[1]) && | |
1000 | !(status & GEN8_CTX_STATUS_ELEMENT_SWITCH)); | |
1001 | GEM_BUG_ON(!port_isset(&port[1]) && | |
1002 | !(status & GEN8_CTX_STATUS_ACTIVE_IDLE)); | |
2ffe80aa | 1003 | |
8ea397fa CW |
1004 | /* |
1005 | * We rely on the hardware being strongly | |
1006 | * ordered, that the breadcrumb write is | |
1007 | * coherent (visible from the CPU) before the | |
1008 | * user interrupt and CSB is processed. | |
1009 | */ | |
1010 | GEM_BUG_ON(!i915_request_completed(rq)); | |
beecec90 | 1011 | |
8ea397fa CW |
1012 | execlists_context_schedule_out(rq, |
1013 | INTEL_CONTEXT_SCHEDULE_OUT); | |
1014 | i915_request_put(rq); | |
e084039b | 1015 | |
8ea397fa CW |
1016 | GEM_TRACE("%s completed ctx=%d\n", |
1017 | engine->name, port->context_id); | |
e084039b | 1018 | |
8ea397fa CW |
1019 | port = execlists_port_complete(execlists, port); |
1020 | if (port_isset(port)) | |
1021 | execlists_user_begin(execlists, port); | |
1022 | else | |
1023 | execlists_user_end(execlists); | |
1024 | } else { | |
1025 | port_set(port, port_pack(rq, count)); | |
4af0d727 | 1026 | } |
bc4237ec | 1027 | } while (head != tail); |
e981e7b1 | 1028 | |
bc4237ec | 1029 | execlists->csb_head = head; |
d8f50531 MK |
1030 | |
1031 | /* | |
1032 | * Gen11 has proven to fail wrt global observation point between | |
1033 | * entry and tail update, failing on the ordering and thus | |
1034 | * we see an old entry in the context status buffer. | |
1035 | * | |
1036 | * Forcibly evict out entries for the next gpu csb update, | |
1037 | * to increase the odds that we get a fresh entries with non | |
1038 | * working hardware. The cost for doing so comes out mostly with | |
1039 | * the wash as hardware, working or not, will need to do the | |
1040 | * invalidation before. | |
1041 | */ | |
1042 | invalidate_csb_entries(&buf[0], &buf[GEN8_CSB_ENTRIES - 1]); | |
73377dbc | 1043 | } |
c6a2ac71 | 1044 | |
9512f985 | 1045 | static void __execlists_submission_tasklet(struct intel_engine_cs *const engine) |
73377dbc | 1046 | { |
9512f985 | 1047 | lockdep_assert_held(&engine->timeline.lock); |
73377dbc | 1048 | |
fd8526e5 | 1049 | process_csb(engine); |
73377dbc CW |
1050 | if (!execlists_is_active(&engine->execlists, EXECLISTS_ACTIVE_PREEMPT)) |
1051 | execlists_dequeue(engine); | |
e981e7b1 TD |
1052 | } |
1053 | ||
9512f985 CW |
1054 | /* |
1055 | * Check the unread Context Status Buffers and manage the submission of new | |
1056 | * contexts to the ELSP accordingly. | |
1057 | */ | |
1058 | static void execlists_submission_tasklet(unsigned long data) | |
1059 | { | |
1060 | struct intel_engine_cs * const engine = (struct intel_engine_cs *)data; | |
1061 | unsigned long flags; | |
1062 | ||
1063 | GEM_TRACE("%s awake?=%d, active=%x\n", | |
1064 | engine->name, | |
8d761e77 | 1065 | !!engine->i915->gt.awake, |
9512f985 CW |
1066 | engine->execlists.active); |
1067 | ||
1068 | spin_lock_irqsave(&engine->timeline.lock, flags); | |
d78d3343 | 1069 | __execlists_submission_tasklet(engine); |
9512f985 CW |
1070 | spin_unlock_irqrestore(&engine->timeline.lock, flags); |
1071 | } | |
1072 | ||
f6322edd | 1073 | static void queue_request(struct intel_engine_cs *engine, |
0c7112a0 | 1074 | struct i915_sched_node *node, |
f6322edd | 1075 | int prio) |
27606fd8 | 1076 | { |
e2f3496e | 1077 | list_add_tail(&node->link, i915_sched_lookup_priolist(engine, prio)); |
9512f985 CW |
1078 | } |
1079 | ||
1080 | static void __submit_queue_imm(struct intel_engine_cs *engine) | |
1081 | { | |
1082 | struct intel_engine_execlists * const execlists = &engine->execlists; | |
1083 | ||
1084 | if (reset_in_progress(execlists)) | |
1085 | return; /* defer until we restart the engine following reset */ | |
1086 | ||
1087 | if (execlists->tasklet.func == execlists_submission_tasklet) | |
1088 | __execlists_submission_tasklet(engine); | |
1089 | else | |
1090 | tasklet_hi_schedule(&execlists->tasklet); | |
ae2f5c00 CW |
1091 | } |
1092 | ||
f6322edd CW |
1093 | static void submit_queue(struct intel_engine_cs *engine, int prio) |
1094 | { | |
9512f985 | 1095 | if (prio > engine->execlists.queue_priority) { |
e2f3496e | 1096 | engine->execlists.queue_priority = prio; |
9512f985 CW |
1097 | __submit_queue_imm(engine); |
1098 | } | |
27606fd8 CW |
1099 | } |
1100 | ||
e61e0f51 | 1101 | static void execlists_submit_request(struct i915_request *request) |
acdd884a | 1102 | { |
4a570db5 | 1103 | struct intel_engine_cs *engine = request->engine; |
5590af3e | 1104 | unsigned long flags; |
acdd884a | 1105 | |
663f71e7 | 1106 | /* Will be called from irq-context when using foreign fences. */ |
a89d1f92 | 1107 | spin_lock_irqsave(&engine->timeline.lock, flags); |
acdd884a | 1108 | |
0c7112a0 | 1109 | queue_request(engine, &request->sched, rq_prio(request)); |
acdd884a | 1110 | |
655250a8 | 1111 | GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); |
0c7112a0 | 1112 | GEM_BUG_ON(list_empty(&request->sched.link)); |
6c067579 | 1113 | |
9512f985 CW |
1114 | submit_queue(engine, rq_prio(request)); |
1115 | ||
a89d1f92 | 1116 | spin_unlock_irqrestore(&engine->timeline.lock, flags); |
acdd884a MT |
1117 | } |
1118 | ||
1fc44d9b CW |
1119 | static void execlists_context_destroy(struct intel_context *ce) |
1120 | { | |
1fc44d9b CW |
1121 | GEM_BUG_ON(ce->pin_count); |
1122 | ||
dd12c6ca CW |
1123 | if (!ce->state) |
1124 | return; | |
1125 | ||
1fc44d9b | 1126 | intel_ring_free(ce->ring); |
efe79d48 CW |
1127 | |
1128 | GEM_BUG_ON(i915_gem_object_is_active(ce->state->obj)); | |
1129 | i915_gem_object_put(ce->state->obj); | |
1fc44d9b CW |
1130 | } |
1131 | ||
867985d4 | 1132 | static void execlists_context_unpin(struct intel_context *ce) |
1fc44d9b | 1133 | { |
bc2477f7 CW |
1134 | struct intel_engine_cs *engine; |
1135 | ||
1136 | /* | |
1137 | * The tasklet may still be using a pointer to our state, via an | |
1138 | * old request. However, since we know we only unpin the context | |
1139 | * on retirement of the following request, we know that the last | |
1140 | * request referencing us will have had a completion CS interrupt. | |
1141 | * If we see that it is still active, it means that the tasklet hasn't | |
1142 | * had the chance to run yet; let it run before we teardown the | |
1143 | * reference it may use. | |
1144 | */ | |
1145 | engine = READ_ONCE(ce->active); | |
1146 | if (unlikely(engine)) { | |
1147 | unsigned long flags; | |
1148 | ||
1149 | spin_lock_irqsave(&engine->timeline.lock, flags); | |
1150 | process_csb(engine); | |
1151 | spin_unlock_irqrestore(&engine->timeline.lock, flags); | |
1152 | ||
1153 | GEM_BUG_ON(READ_ONCE(ce->active)); | |
1154 | } | |
1155 | ||
288f1ced CW |
1156 | i915_gem_context_unpin_hw_id(ce->gem_context); |
1157 | ||
1fc44d9b CW |
1158 | intel_ring_unpin(ce->ring); |
1159 | ||
1160 | ce->state->obj->pin_global--; | |
1161 | i915_gem_object_unpin_map(ce->state->obj); | |
1162 | i915_vma_unpin(ce->state); | |
1163 | ||
1164 | i915_gem_context_put(ce->gem_context); | |
1165 | } | |
1166 | ||
f4e15af7 CW |
1167 | static int __context_pin(struct i915_gem_context *ctx, struct i915_vma *vma) |
1168 | { | |
1169 | unsigned int flags; | |
1170 | int err; | |
1171 | ||
1172 | /* | |
1173 | * Clear this page out of any CPU caches for coherent swap-in/out. | |
1174 | * We only want to do this on the first bind so that we do not stall | |
1175 | * on an active context (which by nature is already on the GPU). | |
1176 | */ | |
1177 | if (!(vma->flags & I915_VMA_GLOBAL_BIND)) { | |
666424ab | 1178 | err = i915_gem_object_set_to_wc_domain(vma->obj, true); |
f4e15af7 CW |
1179 | if (err) |
1180 | return err; | |
1181 | } | |
1182 | ||
1183 | flags = PIN_GLOBAL | PIN_HIGH; | |
496bcce3 | 1184 | flags |= PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma); |
f4e15af7 | 1185 | |
c00db496 | 1186 | return i915_vma_pin(vma, 0, 0, flags); |
f4e15af7 CW |
1187 | } |
1188 | ||
8e525cb4 TU |
1189 | static u32 make_rpcs(struct drm_i915_private *dev_priv); |
1190 | ||
1191 | static void | |
1192 | __execlists_update_reg_state(struct intel_engine_cs *engine, | |
1193 | struct intel_context *ce) | |
1194 | { | |
1195 | u32 *regs = ce->lrc_reg_state; | |
1196 | struct intel_ring *ring = ce->ring; | |
1197 | ||
1198 | regs[CTX_RING_BUFFER_START + 1] = i915_ggtt_offset(ring->vma); | |
1199 | regs[CTX_RING_HEAD + 1] = ring->head; | |
1200 | regs[CTX_RING_TAIL + 1] = ring->tail; | |
1201 | ||
1202 | /* RPCS */ | |
1203 | if (engine->class == RENDER_CLASS) | |
1204 | regs[CTX_R_PWR_CLK_STATE + 1] = make_rpcs(engine->i915); | |
1205 | } | |
1206 | ||
1fc44d9b CW |
1207 | static struct intel_context * |
1208 | __execlists_context_pin(struct intel_engine_cs *engine, | |
1209 | struct i915_gem_context *ctx, | |
1210 | struct intel_context *ce) | |
dcb4c12a | 1211 | { |
7d774cac | 1212 | void *vaddr; |
ca82580c | 1213 | int ret; |
dcb4c12a | 1214 | |
1fc44d9b | 1215 | ret = execlists_context_deferred_alloc(ctx, engine, ce); |
1d2a19c2 CW |
1216 | if (ret) |
1217 | goto err; | |
56f6e0a7 | 1218 | GEM_BUG_ON(!ce->state); |
e8a9c58f | 1219 | |
f4e15af7 | 1220 | ret = __context_pin(ctx, ce->state); |
e84fe803 | 1221 | if (ret) |
24f1d3cc | 1222 | goto err; |
7ba717cf | 1223 | |
666424ab CW |
1224 | vaddr = i915_gem_object_pin_map(ce->state->obj, |
1225 | i915_coherent_map_type(ctx->i915) | | |
1226 | I915_MAP_OVERRIDE); | |
7d774cac TU |
1227 | if (IS_ERR(vaddr)) { |
1228 | ret = PTR_ERR(vaddr); | |
bf3783e5 | 1229 | goto unpin_vma; |
82352e90 TU |
1230 | } |
1231 | ||
5503cb0d | 1232 | ret = intel_ring_pin(ce->ring); |
e84fe803 | 1233 | if (ret) |
7d774cac | 1234 | goto unpin_map; |
d1675198 | 1235 | |
288f1ced CW |
1236 | ret = i915_gem_context_pin_hw_id(ctx); |
1237 | if (ret) | |
1238 | goto unpin_ring; | |
1239 | ||
1fc44d9b | 1240 | intel_lr_context_descriptor_update(ctx, engine, ce); |
9021ad03 | 1241 | |
dee60ca1 CW |
1242 | GEM_BUG_ON(!intel_ring_offset_valid(ce->ring, ce->ring->head)); |
1243 | ||
a3aabe86 | 1244 | ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; |
8e525cb4 TU |
1245 | |
1246 | __execlists_update_reg_state(engine, ce); | |
a3aabe86 | 1247 | |
3d574a6b | 1248 | ce->state->obj->pin_global++; |
9a6feaf0 | 1249 | i915_gem_context_get(ctx); |
1fc44d9b | 1250 | return ce; |
7ba717cf | 1251 | |
288f1ced CW |
1252 | unpin_ring: |
1253 | intel_ring_unpin(ce->ring); | |
7d774cac | 1254 | unpin_map: |
bf3783e5 CW |
1255 | i915_gem_object_unpin_map(ce->state->obj); |
1256 | unpin_vma: | |
1257 | __i915_vma_unpin(ce->state); | |
24f1d3cc | 1258 | err: |
9021ad03 | 1259 | ce->pin_count = 0; |
266a240b | 1260 | return ERR_PTR(ret); |
e84fe803 NH |
1261 | } |
1262 | ||
1fc44d9b CW |
1263 | static const struct intel_context_ops execlists_context_ops = { |
1264 | .unpin = execlists_context_unpin, | |
1265 | .destroy = execlists_context_destroy, | |
1266 | }; | |
1267 | ||
1268 | static struct intel_context * | |
1269 | execlists_context_pin(struct intel_engine_cs *engine, | |
1270 | struct i915_gem_context *ctx) | |
e84fe803 | 1271 | { |
ab82a063 | 1272 | struct intel_context *ce = to_intel_context(ctx, engine); |
e84fe803 | 1273 | |
91c8a326 | 1274 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
4bdafb9d | 1275 | GEM_BUG_ON(!ctx->ppgtt); |
321fe304 | 1276 | |
1fc44d9b CW |
1277 | if (likely(ce->pin_count++)) |
1278 | return ce; | |
1279 | GEM_BUG_ON(!ce->pin_count); /* no overflow please! */ | |
dcb4c12a | 1280 | |
1fc44d9b | 1281 | ce->ops = &execlists_context_ops; |
321fe304 | 1282 | |
1fc44d9b | 1283 | return __execlists_context_pin(engine, ctx, ce); |
dcb4c12a OM |
1284 | } |
1285 | ||
85474441 CW |
1286 | static int gen8_emit_init_breadcrumb(struct i915_request *rq) |
1287 | { | |
1288 | u32 *cs; | |
1289 | ||
1290 | GEM_BUG_ON(!rq->timeline->has_initial_breadcrumb); | |
1291 | ||
1292 | cs = intel_ring_begin(rq, 6); | |
1293 | if (IS_ERR(cs)) | |
1294 | return PTR_ERR(cs); | |
1295 | ||
1296 | /* | |
1297 | * Check if we have been preempted before we even get started. | |
1298 | * | |
1299 | * After this point i915_request_started() reports true, even if | |
1300 | * we get preempted and so are no longer running. | |
1301 | */ | |
1302 | *cs++ = MI_ARB_CHECK; | |
1303 | *cs++ = MI_NOOP; | |
1304 | ||
1305 | *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; | |
1306 | *cs++ = rq->timeline->hwsp_offset; | |
1307 | *cs++ = 0; | |
1308 | *cs++ = rq->fence.seqno - 1; | |
1309 | ||
1310 | intel_ring_advance(rq, cs); | |
1311 | return 0; | |
1312 | } | |
1313 | ||
e8894267 CW |
1314 | static int emit_pdps(struct i915_request *rq) |
1315 | { | |
1316 | const struct intel_engine_cs * const engine = rq->engine; | |
1317 | struct i915_hw_ppgtt * const ppgtt = rq->gem_context->ppgtt; | |
1318 | int err, i; | |
1319 | u32 *cs; | |
1320 | ||
1321 | GEM_BUG_ON(intel_vgpu_active(rq->i915)); | |
1322 | ||
1323 | /* | |
1324 | * Beware ye of the dragons, this sequence is magic! | |
1325 | * | |
1326 | * Small changes to this sequence can cause anything from | |
1327 | * GPU hangs to forcewake errors and machine lockups! | |
1328 | */ | |
1329 | ||
1330 | /* Flush any residual operations from the context load */ | |
1331 | err = engine->emit_flush(rq, EMIT_FLUSH); | |
1332 | if (err) | |
1333 | return err; | |
1334 | ||
1335 | /* Magic required to prevent forcewake errors! */ | |
1336 | err = engine->emit_flush(rq, EMIT_INVALIDATE); | |
1337 | if (err) | |
1338 | return err; | |
1339 | ||
1340 | cs = intel_ring_begin(rq, 4 * GEN8_3LVL_PDPES + 2); | |
1341 | if (IS_ERR(cs)) | |
1342 | return PTR_ERR(cs); | |
1343 | ||
1344 | /* Ensure the LRI have landed before we invalidate & continue */ | |
1345 | *cs++ = MI_LOAD_REGISTER_IMM(2 * GEN8_3LVL_PDPES) | MI_LRI_FORCE_POSTED; | |
1346 | for (i = GEN8_3LVL_PDPES; i--; ) { | |
1347 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); | |
1348 | ||
1349 | *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i)); | |
1350 | *cs++ = upper_32_bits(pd_daddr); | |
1351 | *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i)); | |
1352 | *cs++ = lower_32_bits(pd_daddr); | |
1353 | } | |
1354 | *cs++ = MI_NOOP; | |
1355 | ||
1356 | intel_ring_advance(rq, cs); | |
1357 | ||
1358 | /* Be doubly sure the LRI have landed before proceeding */ | |
1359 | err = engine->emit_flush(rq, EMIT_FLUSH); | |
1360 | if (err) | |
1361 | return err; | |
1362 | ||
1363 | /* Re-invalidate the TLB for luck */ | |
1364 | return engine->emit_flush(rq, EMIT_INVALIDATE); | |
1365 | } | |
1366 | ||
e61e0f51 | 1367 | static int execlists_request_alloc(struct i915_request *request) |
ef11c01d | 1368 | { |
fd138212 | 1369 | int ret; |
ef11c01d | 1370 | |
1fc44d9b | 1371 | GEM_BUG_ON(!request->hw_context->pin_count); |
e8a9c58f | 1372 | |
5f5800a7 CW |
1373 | /* |
1374 | * Flush enough space to reduce the likelihood of waiting after | |
ef11c01d CW |
1375 | * we start building the request - in which case we will just |
1376 | * have to repeat work. | |
1377 | */ | |
1378 | request->reserved_space += EXECLISTS_REQUEST_SIZE; | |
1379 | ||
5f5800a7 CW |
1380 | /* |
1381 | * Note that after this point, we have committed to using | |
ef11c01d CW |
1382 | * this request as it is being used to both track the |
1383 | * state of engine initialisation and liveness of the | |
1384 | * golden renderstate above. Think twice before you try | |
1385 | * to cancel/unwind this request now. | |
1386 | */ | |
1387 | ||
e8894267 CW |
1388 | /* Unconditionally invalidate GPU caches and TLBs. */ |
1389 | if (i915_vm_is_48bit(&request->gem_context->ppgtt->vm)) | |
1390 | ret = request->engine->emit_flush(request, EMIT_INVALIDATE); | |
1391 | else | |
1392 | ret = emit_pdps(request); | |
1393 | if (ret) | |
1394 | return ret; | |
1395 | ||
ef11c01d CW |
1396 | request->reserved_space -= EXECLISTS_REQUEST_SIZE; |
1397 | return 0; | |
ef11c01d CW |
1398 | } |
1399 | ||
9e000847 AS |
1400 | /* |
1401 | * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after | |
1402 | * PIPE_CONTROL instruction. This is required for the flush to happen correctly | |
1403 | * but there is a slight complication as this is applied in WA batch where the | |
1404 | * values are only initialized once so we cannot take register value at the | |
1405 | * beginning and reuse it further; hence we save its value to memory, upload a | |
1406 | * constant value with bit21 set and then we restore it back with the saved value. | |
1407 | * To simplify the WA, a constant value is formed by using the default value | |
1408 | * of this register. This shouldn't be a problem because we are only modifying | |
1409 | * it for a short period and this batch in non-premptible. We can ofcourse | |
1410 | * use additional instructions that read the actual value of the register | |
1411 | * at that time and set our bit of interest but it makes the WA complicated. | |
1412 | * | |
1413 | * This WA is also required for Gen9 so extracting as a function avoids | |
1414 | * code duplication. | |
1415 | */ | |
097d4f1c TU |
1416 | static u32 * |
1417 | gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch) | |
17ee950d | 1418 | { |
51797499 | 1419 | /* NB no one else is allowed to scribble over scratch + 256! */ |
097d4f1c TU |
1420 | *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; |
1421 | *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); | |
51797499 | 1422 | *batch++ = i915_scratch_offset(engine->i915) + 256; |
097d4f1c TU |
1423 | *batch++ = 0; |
1424 | ||
1425 | *batch++ = MI_LOAD_REGISTER_IMM(1); | |
1426 | *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); | |
1427 | *batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES; | |
1428 | ||
9f235dfa TU |
1429 | batch = gen8_emit_pipe_control(batch, |
1430 | PIPE_CONTROL_CS_STALL | | |
1431 | PIPE_CONTROL_DC_FLUSH_ENABLE, | |
1432 | 0); | |
097d4f1c TU |
1433 | |
1434 | *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; | |
1435 | *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); | |
51797499 | 1436 | *batch++ = i915_scratch_offset(engine->i915) + 256; |
097d4f1c TU |
1437 | *batch++ = 0; |
1438 | ||
1439 | return batch; | |
17ee950d AS |
1440 | } |
1441 | ||
6e5248b5 DV |
1442 | /* |
1443 | * Typically we only have one indirect_ctx and per_ctx batch buffer which are | |
1444 | * initialized at the beginning and shared across all contexts but this field | |
1445 | * helps us to have multiple batches at different offsets and select them based | |
1446 | * on a criteria. At the moment this batch always start at the beginning of the page | |
1447 | * and at this point we don't have multiple wa_ctx batch buffers. | |
4d78c8dc | 1448 | * |
6e5248b5 DV |
1449 | * The number of WA applied are not known at the beginning; we use this field |
1450 | * to return the no of DWORDS written. | |
17ee950d | 1451 | * |
6e5248b5 DV |
1452 | * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END |
1453 | * so it adds NOOPs as padding to make it cacheline aligned. | |
1454 | * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together | |
1455 | * makes a complete batch buffer. | |
17ee950d | 1456 | */ |
097d4f1c | 1457 | static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) |
17ee950d | 1458 | { |
7ad00d1a | 1459 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
097d4f1c | 1460 | *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; |
17ee950d | 1461 | |
c82435bb | 1462 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */ |
097d4f1c TU |
1463 | if (IS_BROADWELL(engine->i915)) |
1464 | batch = gen8_emit_flush_coherentl3_wa(engine, batch); | |
c82435bb | 1465 | |
0160f055 AS |
1466 | /* WaClearSlmSpaceAtContextSwitch:bdw,chv */ |
1467 | /* Actual scratch location is at 128 bytes offset */ | |
9f235dfa TU |
1468 | batch = gen8_emit_pipe_control(batch, |
1469 | PIPE_CONTROL_FLUSH_L3 | | |
1470 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1471 | PIPE_CONTROL_CS_STALL | | |
1472 | PIPE_CONTROL_QW_WRITE, | |
51797499 | 1473 | i915_scratch_offset(engine->i915) + |
9f235dfa | 1474 | 2 * CACHELINE_BYTES); |
0160f055 | 1475 | |
beecec90 CW |
1476 | *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; |
1477 | ||
17ee950d | 1478 | /* Pad to end of cacheline */ |
097d4f1c TU |
1479 | while ((unsigned long)batch % CACHELINE_BYTES) |
1480 | *batch++ = MI_NOOP; | |
17ee950d AS |
1481 | |
1482 | /* | |
1483 | * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because | |
1484 | * execution depends on the length specified in terms of cache lines | |
1485 | * in the register CTX_RCS_INDIRECT_CTX | |
1486 | */ | |
1487 | ||
097d4f1c | 1488 | return batch; |
17ee950d AS |
1489 | } |
1490 | ||
5ee4a7a6 CW |
1491 | struct lri { |
1492 | i915_reg_t reg; | |
1493 | u32 value; | |
1494 | }; | |
1495 | ||
1496 | static u32 *emit_lri(u32 *batch, const struct lri *lri, unsigned int count) | |
0504cffc | 1497 | { |
5ee4a7a6 | 1498 | GEM_BUG_ON(!count || count > 63); |
beecec90 | 1499 | |
5ee4a7a6 CW |
1500 | *batch++ = MI_LOAD_REGISTER_IMM(count); |
1501 | do { | |
1502 | *batch++ = i915_mmio_reg_offset(lri->reg); | |
1503 | *batch++ = lri->value; | |
1504 | } while (lri++, --count); | |
1505 | *batch++ = MI_NOOP; | |
a4106a78 | 1506 | |
5ee4a7a6 CW |
1507 | return batch; |
1508 | } | |
b77422f8 | 1509 | |
5ee4a7a6 CW |
1510 | static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) |
1511 | { | |
1512 | static const struct lri lri[] = { | |
1513 | /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */ | |
1514 | { | |
1515 | COMMON_SLICE_CHICKEN2, | |
1516 | __MASKED_FIELD(GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE, | |
1517 | 0), | |
1518 | }, | |
1519 | ||
1520 | /* BSpec: 11391 */ | |
1521 | { | |
1522 | FF_SLICE_CHICKEN, | |
1523 | __MASKED_FIELD(FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX, | |
1524 | FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX), | |
1525 | }, | |
1526 | ||
1527 | /* BSpec: 11299 */ | |
1528 | { | |
1529 | _3D_CHICKEN3, | |
1530 | __MASKED_FIELD(_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX, | |
1531 | _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX), | |
1532 | } | |
1533 | }; | |
b77422f8 | 1534 | |
5ee4a7a6 | 1535 | *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; |
b77422f8 | 1536 | |
5ee4a7a6 CW |
1537 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */ |
1538 | batch = gen8_emit_flush_coherentl3_wa(engine, batch); | |
b77422f8 | 1539 | |
5ee4a7a6 | 1540 | batch = emit_lri(batch, lri, ARRAY_SIZE(lri)); |
873e8171 | 1541 | |
9fb5026f | 1542 | /* WaMediaPoolStateCmdInWABB:bxt,glk */ |
3485d99e TG |
1543 | if (HAS_POOLED_EU(engine->i915)) { |
1544 | /* | |
1545 | * EU pool configuration is setup along with golden context | |
1546 | * during context initialization. This value depends on | |
1547 | * device type (2x6 or 3x6) and needs to be updated based | |
1548 | * on which subslice is disabled especially for 2x6 | |
1549 | * devices, however it is safe to load default | |
1550 | * configuration of 3x6 device instead of masking off | |
1551 | * corresponding bits because HW ignores bits of a disabled | |
1552 | * subslice and drops down to appropriate config. Please | |
1553 | * see render_state_setup() in i915_gem_render_state.c for | |
1554 | * possible configurations, to avoid duplication they are | |
1555 | * not shown here again. | |
1556 | */ | |
097d4f1c TU |
1557 | *batch++ = GEN9_MEDIA_POOL_STATE; |
1558 | *batch++ = GEN9_MEDIA_POOL_ENABLE; | |
1559 | *batch++ = 0x00777000; | |
1560 | *batch++ = 0; | |
1561 | *batch++ = 0; | |
1562 | *batch++ = 0; | |
3485d99e TG |
1563 | } |
1564 | ||
beecec90 CW |
1565 | *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; |
1566 | ||
0504cffc | 1567 | /* Pad to end of cacheline */ |
097d4f1c TU |
1568 | while ((unsigned long)batch % CACHELINE_BYTES) |
1569 | *batch++ = MI_NOOP; | |
0504cffc | 1570 | |
097d4f1c | 1571 | return batch; |
0504cffc AS |
1572 | } |
1573 | ||
4b6ce681 RA |
1574 | static u32 * |
1575 | gen10_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) | |
1576 | { | |
1577 | int i; | |
1578 | ||
1579 | /* | |
1580 | * WaPipeControlBefore3DStateSamplePattern: cnl | |
1581 | * | |
1582 | * Ensure the engine is idle prior to programming a | |
1583 | * 3DSTATE_SAMPLE_PATTERN during a context restore. | |
1584 | */ | |
1585 | batch = gen8_emit_pipe_control(batch, | |
1586 | PIPE_CONTROL_CS_STALL, | |
1587 | 0); | |
1588 | /* | |
1589 | * WaPipeControlBefore3DStateSamplePattern says we need 4 dwords for | |
1590 | * the PIPE_CONTROL followed by 12 dwords of 0x0, so 16 dwords in | |
1591 | * total. However, a PIPE_CONTROL is 6 dwords long, not 4, which is | |
1592 | * confusing. Since gen8_emit_pipe_control() already advances the | |
1593 | * batch by 6 dwords, we advance the other 10 here, completing a | |
1594 | * cacheline. It's not clear if the workaround requires this padding | |
1595 | * before other commands, or if it's just the regular padding we would | |
1596 | * already have for the workaround bb, so leave it here for now. | |
1597 | */ | |
1598 | for (i = 0; i < 10; i++) | |
1599 | *batch++ = MI_NOOP; | |
1600 | ||
1601 | /* Pad to end of cacheline */ | |
1602 | while ((unsigned long)batch % CACHELINE_BYTES) | |
1603 | *batch++ = MI_NOOP; | |
1604 | ||
1605 | return batch; | |
1606 | } | |
1607 | ||
097d4f1c TU |
1608 | #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE) |
1609 | ||
1610 | static int lrc_setup_wa_ctx(struct intel_engine_cs *engine) | |
17ee950d | 1611 | { |
48bb74e4 CW |
1612 | struct drm_i915_gem_object *obj; |
1613 | struct i915_vma *vma; | |
1614 | int err; | |
17ee950d | 1615 | |
097d4f1c | 1616 | obj = i915_gem_object_create(engine->i915, CTX_WA_BB_OBJ_SIZE); |
48bb74e4 CW |
1617 | if (IS_ERR(obj)) |
1618 | return PTR_ERR(obj); | |
17ee950d | 1619 | |
82ad6443 | 1620 | vma = i915_vma_instance(obj, &engine->i915->ggtt.vm, NULL); |
48bb74e4 CW |
1621 | if (IS_ERR(vma)) { |
1622 | err = PTR_ERR(vma); | |
1623 | goto err; | |
17ee950d AS |
1624 | } |
1625 | ||
7a859c65 | 1626 | err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH); |
48bb74e4 CW |
1627 | if (err) |
1628 | goto err; | |
1629 | ||
1630 | engine->wa_ctx.vma = vma; | |
17ee950d | 1631 | return 0; |
48bb74e4 CW |
1632 | |
1633 | err: | |
1634 | i915_gem_object_put(obj); | |
1635 | return err; | |
17ee950d AS |
1636 | } |
1637 | ||
097d4f1c | 1638 | static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine) |
17ee950d | 1639 | { |
6a2f59e4 | 1640 | i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0); |
17ee950d AS |
1641 | } |
1642 | ||
097d4f1c TU |
1643 | typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch); |
1644 | ||
0bc40be8 | 1645 | static int intel_init_workaround_bb(struct intel_engine_cs *engine) |
17ee950d | 1646 | { |
48bb74e4 | 1647 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; |
097d4f1c TU |
1648 | struct i915_wa_ctx_bb *wa_bb[2] = { &wa_ctx->indirect_ctx, |
1649 | &wa_ctx->per_ctx }; | |
1650 | wa_bb_func_t wa_bb_fn[2]; | |
17ee950d | 1651 | struct page *page; |
097d4f1c TU |
1652 | void *batch, *batch_ptr; |
1653 | unsigned int i; | |
48bb74e4 | 1654 | int ret; |
17ee950d | 1655 | |
bbb8a9d7 | 1656 | if (GEM_DEBUG_WARN_ON(engine->id != RCS)) |
097d4f1c | 1657 | return -EINVAL; |
17ee950d | 1658 | |
097d4f1c | 1659 | switch (INTEL_GEN(engine->i915)) { |
cc38cae7 OM |
1660 | case 11: |
1661 | return 0; | |
90007bca | 1662 | case 10: |
4b6ce681 RA |
1663 | wa_bb_fn[0] = gen10_init_indirectctx_bb; |
1664 | wa_bb_fn[1] = NULL; | |
1665 | break; | |
097d4f1c TU |
1666 | case 9: |
1667 | wa_bb_fn[0] = gen9_init_indirectctx_bb; | |
b8aa2233 | 1668 | wa_bb_fn[1] = NULL; |
097d4f1c TU |
1669 | break; |
1670 | case 8: | |
1671 | wa_bb_fn[0] = gen8_init_indirectctx_bb; | |
3ad7b52d | 1672 | wa_bb_fn[1] = NULL; |
097d4f1c TU |
1673 | break; |
1674 | default: | |
1675 | MISSING_CASE(INTEL_GEN(engine->i915)); | |
5e60d790 | 1676 | return 0; |
0504cffc | 1677 | } |
5e60d790 | 1678 | |
097d4f1c | 1679 | ret = lrc_setup_wa_ctx(engine); |
17ee950d AS |
1680 | if (ret) { |
1681 | DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret); | |
1682 | return ret; | |
1683 | } | |
1684 | ||
48bb74e4 | 1685 | page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0); |
097d4f1c | 1686 | batch = batch_ptr = kmap_atomic(page); |
17ee950d | 1687 | |
097d4f1c TU |
1688 | /* |
1689 | * Emit the two workaround batch buffers, recording the offset from the | |
1690 | * start of the workaround batch buffer object for each and their | |
1691 | * respective sizes. | |
1692 | */ | |
1693 | for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) { | |
1694 | wa_bb[i]->offset = batch_ptr - batch; | |
bbb8a9d7 TU |
1695 | if (GEM_DEBUG_WARN_ON(!IS_ALIGNED(wa_bb[i]->offset, |
1696 | CACHELINE_BYTES))) { | |
097d4f1c TU |
1697 | ret = -EINVAL; |
1698 | break; | |
1699 | } | |
604a8f6f CW |
1700 | if (wa_bb_fn[i]) |
1701 | batch_ptr = wa_bb_fn[i](engine, batch_ptr); | |
097d4f1c | 1702 | wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset); |
17ee950d AS |
1703 | } |
1704 | ||
097d4f1c TU |
1705 | BUG_ON(batch_ptr - batch > CTX_WA_BB_OBJ_SIZE); |
1706 | ||
17ee950d AS |
1707 | kunmap_atomic(batch); |
1708 | if (ret) | |
097d4f1c | 1709 | lrc_destroy_wa_ctx(engine); |
17ee950d AS |
1710 | |
1711 | return ret; | |
1712 | } | |
1713 | ||
f3c9d407 | 1714 | static void enable_execlists(struct intel_engine_cs *engine) |
9b1136d5 | 1715 | { |
c033666a | 1716 | struct drm_i915_private *dev_priv = engine->i915; |
f3c9d407 | 1717 | |
060f2322 | 1718 | intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */ |
225701fc KG |
1719 | |
1720 | /* | |
1721 | * Make sure we're not enabling the new 12-deep CSB | |
1722 | * FIFO as that requires a slightly updated handling | |
1723 | * in the ctx switch irq. Since we're currently only | |
1724 | * using only 2 elements of the enhanced execlists the | |
1725 | * deeper FIFO it's not needed and it's not worth adding | |
1726 | * more statements to the irq handler to support it. | |
1727 | */ | |
1728 | if (INTEL_GEN(dev_priv) >= 11) | |
1729 | I915_WRITE(RING_MODE_GEN7(engine), | |
1730 | _MASKED_BIT_DISABLE(GEN11_GFX_DISABLE_LEGACY_MODE)); | |
1731 | else | |
1732 | I915_WRITE(RING_MODE_GEN7(engine), | |
1733 | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); | |
1734 | ||
9a4dc803 CW |
1735 | I915_WRITE(RING_MI_MODE(engine->mmio_base), |
1736 | _MASKED_BIT_DISABLE(STOP_RING)); | |
1737 | ||
f3c9d407 | 1738 | I915_WRITE(RING_HWS_PGA(engine->mmio_base), |
0ca88ba0 | 1739 | i915_ggtt_offset(engine->status_page.vma)); |
f3c9d407 CW |
1740 | POSTING_READ(RING_HWS_PGA(engine->mmio_base)); |
1741 | } | |
1742 | ||
9a4dc803 CW |
1743 | static bool unexpected_starting_state(struct intel_engine_cs *engine) |
1744 | { | |
1745 | struct drm_i915_private *dev_priv = engine->i915; | |
1746 | bool unexpected = false; | |
1747 | ||
1748 | if (I915_READ(RING_MI_MODE(engine->mmio_base)) & STOP_RING) { | |
1749 | DRM_DEBUG_DRIVER("STOP_RING still set in RING_MI_MODE\n"); | |
1750 | unexpected = true; | |
1751 | } | |
1752 | ||
1753 | return unexpected; | |
1754 | } | |
1755 | ||
f3c9d407 CW |
1756 | static int gen8_init_common_ring(struct intel_engine_cs *engine) |
1757 | { | |
4a15c75c | 1758 | intel_engine_apply_workarounds(engine); |
5a688ee3 | 1759 | intel_engine_apply_whitelist(engine); |
4a15c75c | 1760 | |
805615da | 1761 | intel_mocs_init_engine(engine); |
9b1136d5 | 1762 | |
ad07dfcd | 1763 | intel_engine_reset_breadcrumbs(engine); |
821ed7df | 1764 | |
9a4dc803 CW |
1765 | if (GEM_SHOW_DEBUG() && unexpected_starting_state(engine)) { |
1766 | struct drm_printer p = drm_debug_printer(__func__); | |
1767 | ||
1768 | intel_engine_dump(engine, &p, NULL); | |
1769 | } | |
1770 | ||
f3c9d407 | 1771 | enable_execlists(engine); |
9b1136d5 | 1772 | |
821ed7df | 1773 | return 0; |
9b1136d5 OM |
1774 | } |
1775 | ||
eb8d0f5a | 1776 | static void execlists_reset_prepare(struct intel_engine_cs *engine) |
5adfb772 CW |
1777 | { |
1778 | struct intel_engine_execlists * const execlists = &engine->execlists; | |
9512f985 | 1779 | unsigned long flags; |
5adfb772 | 1780 | |
66fc8296 CW |
1781 | GEM_TRACE("%s: depth<-%d\n", engine->name, |
1782 | atomic_read(&execlists->tasklet.count)); | |
5adfb772 CW |
1783 | |
1784 | /* | |
1785 | * Prevent request submission to the hardware until we have | |
1786 | * completed the reset in i915_gem_reset_finish(). If a request | |
1787 | * is completed by one engine, it may then queue a request | |
1788 | * to a second via its execlists->tasklet *just* as we are | |
1789 | * calling engine->init_hw() and also writing the ELSP. | |
1790 | * Turning off the execlists->tasklet until the reset is over | |
1791 | * prevents the race. | |
1792 | */ | |
1793 | __tasklet_disable_sync_once(&execlists->tasklet); | |
eb8d0f5a | 1794 | GEM_BUG_ON(!reset_in_progress(execlists)); |
5adfb772 | 1795 | |
eb8d0f5a | 1796 | /* And flush any current direct submission. */ |
9512f985 | 1797 | spin_lock_irqsave(&engine->timeline.lock, flags); |
eb8d0f5a | 1798 | process_csb(engine); /* drain preemption events */ |
9512f985 | 1799 | spin_unlock_irqrestore(&engine->timeline.lock, flags); |
5adfb772 CW |
1800 | } |
1801 | ||
eb8d0f5a | 1802 | static void execlists_reset(struct intel_engine_cs *engine, bool stalled) |
821ed7df | 1803 | { |
b620e870 | 1804 | struct intel_engine_execlists * const execlists = &engine->execlists; |
eb8d0f5a | 1805 | struct i915_request *rq; |
221ab971 | 1806 | unsigned long flags; |
5692251c | 1807 | u32 *regs; |
cdb6ded4 | 1808 | |
d8857d54 | 1809 | spin_lock_irqsave(&engine->timeline.lock, flags); |
221ab971 | 1810 | |
cdb6ded4 CW |
1811 | /* |
1812 | * Catch up with any missed context-switch interrupts. | |
1813 | * | |
1814 | * Ideally we would just read the remaining CSB entries now that we | |
1815 | * know the gpu is idle. However, the CSB registers are sometimes^W | |
1816 | * often trashed across a GPU reset! Instead we have to rely on | |
1817 | * guessing the missed context-switch events by looking at what | |
1818 | * requests were completed. | |
1819 | */ | |
a4598d17 | 1820 | execlists_cancel_port_requests(execlists); |
cdb6ded4 | 1821 | |
221ab971 | 1822 | /* Push back any incomplete requests for replay after the reset. */ |
eb8d0f5a | 1823 | rq = __unwind_incomplete_requests(engine); |
cdb6ded4 | 1824 | |
c3160da9 | 1825 | /* Following the reset, we need to reload the CSB read/write pointers */ |
f4b58f04 | 1826 | reset_csb_pointers(&engine->execlists); |
c3160da9 | 1827 | |
eb8d0f5a CW |
1828 | GEM_TRACE("%s seqno=%d, current=%d, stalled? %s\n", |
1829 | engine->name, | |
1830 | rq ? rq->global_seqno : 0, | |
1831 | intel_engine_get_seqno(engine), | |
1832 | yesno(stalled)); | |
1833 | if (!rq) | |
1834 | goto out_unlock; | |
aebbc2d7 | 1835 | |
a3e38836 CW |
1836 | /* |
1837 | * If the request was innocent, we leave the request in the ELSP | |
c0dcb203 CW |
1838 | * and will try to replay it on restarting. The context image may |
1839 | * have been corrupted by the reset, in which case we may have | |
1840 | * to service a new GPU hang, but more likely we can continue on | |
1841 | * without impact. | |
1842 | * | |
1843 | * If the request was guilty, we presume the context is corrupt | |
1844 | * and have to at least restore the RING register in the context | |
1845 | * image back to the expected values to skip over the guilty request. | |
1846 | */ | |
eb8d0f5a CW |
1847 | i915_reset_request(rq, stalled); |
1848 | if (!stalled) | |
1849 | goto out_unlock; | |
821ed7df | 1850 | |
a3e38836 CW |
1851 | /* |
1852 | * We want a simple context + ring to execute the breadcrumb update. | |
a3aabe86 CW |
1853 | * We cannot rely on the context being intact across the GPU hang, |
1854 | * so clear it and rebuild just what we need for the breadcrumb. | |
1855 | * All pending requests for this context will be zapped, and any | |
1856 | * future request will be after userspace has had the opportunity | |
1857 | * to recreate its own state. | |
1858 | */ | |
eb8d0f5a | 1859 | regs = rq->hw_context->lrc_reg_state; |
fe0c4935 CW |
1860 | if (engine->pinned_default_state) { |
1861 | memcpy(regs, /* skip restoring the vanilla PPHWSP */ | |
1862 | engine->pinned_default_state + LRC_STATE_PN * PAGE_SIZE, | |
1863 | engine->context_size - PAGE_SIZE); | |
5692251c | 1864 | } |
a3aabe86 | 1865 | |
821ed7df | 1866 | /* Move the RING_HEAD onto the breadcrumb, past the hanging batch */ |
eb8d0f5a CW |
1867 | rq->ring->head = intel_ring_wrap(rq->ring, rq->postfix); |
1868 | intel_ring_update_space(rq->ring); | |
8e525cb4 | 1869 | |
eb8d0f5a CW |
1870 | execlists_init_reg_state(regs, rq->gem_context, engine, rq->ring); |
1871 | __execlists_update_reg_state(engine, rq->hw_context); | |
8e525cb4 | 1872 | |
eb8d0f5a CW |
1873 | out_unlock: |
1874 | spin_unlock_irqrestore(&engine->timeline.lock, flags); | |
821ed7df CW |
1875 | } |
1876 | ||
5adfb772 CW |
1877 | static void execlists_reset_finish(struct intel_engine_cs *engine) |
1878 | { | |
5db1d4ea CW |
1879 | struct intel_engine_execlists * const execlists = &engine->execlists; |
1880 | ||
fe25f304 | 1881 | /* |
9e4fa012 CW |
1882 | * After a GPU reset, we may have requests to replay. Do so now while |
1883 | * we still have the forcewake to be sure that the GPU is not allowed | |
1884 | * to sleep before we restart and reload a context. | |
fe25f304 | 1885 | * |
fe25f304 | 1886 | */ |
eb8d0f5a | 1887 | GEM_BUG_ON(!reset_in_progress(execlists)); |
9e4fa012 CW |
1888 | if (!RB_EMPTY_ROOT(&execlists->queue.rb_root)) |
1889 | execlists->tasklet.func(execlists->tasklet.data); | |
5adfb772 | 1890 | |
9e4fa012 | 1891 | tasklet_enable(&execlists->tasklet); |
66fc8296 CW |
1892 | GEM_TRACE("%s: depth->%d\n", engine->name, |
1893 | atomic_read(&execlists->tasklet.count)); | |
5adfb772 CW |
1894 | } |
1895 | ||
e61e0f51 | 1896 | static int gen8_emit_bb_start(struct i915_request *rq, |
803688ba | 1897 | u64 offset, u32 len, |
54af56db | 1898 | const unsigned int flags) |
15648585 | 1899 | { |
73dec95e | 1900 | u32 *cs; |
7a01a0a2 | 1901 | |
74f94741 | 1902 | cs = intel_ring_begin(rq, 6); |
73dec95e TU |
1903 | if (IS_ERR(cs)) |
1904 | return PTR_ERR(cs); | |
15648585 | 1905 | |
279f5a00 CW |
1906 | /* |
1907 | * WaDisableCtxRestoreArbitration:bdw,chv | |
1908 | * | |
1909 | * We don't need to perform MI_ARB_ENABLE as often as we do (in | |
1910 | * particular all the gen that do not need the w/a at all!), if we | |
1911 | * took care to make sure that on every switch into this context | |
1912 | * (both ordinary and for preemption) that arbitrartion was enabled | |
1913 | * we would be fine. However, there doesn't seem to be a downside to | |
1914 | * being paranoid and making sure it is set before each batch and | |
1915 | * every context-switch. | |
1916 | * | |
1917 | * Note that if we fail to enable arbitration before the request | |
1918 | * is complete, then we do not see the context-switch interrupt and | |
1919 | * the engine hangs (with RING_HEAD == RING_TAIL). | |
1920 | * | |
1921 | * That satisfies both the GPGPU w/a and our heavy-handed paranoia. | |
1922 | */ | |
3ad7b52d CW |
1923 | *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; |
1924 | ||
15648585 | 1925 | /* FIXME(BDW): Address space and security selectors. */ |
54af56db | 1926 | *cs++ = MI_BATCH_BUFFER_START_GEN8 | |
08e3e21a | 1927 | (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)); |
73dec95e TU |
1928 | *cs++ = lower_32_bits(offset); |
1929 | *cs++ = upper_32_bits(offset); | |
74f94741 CW |
1930 | |
1931 | *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; | |
1932 | *cs++ = MI_NOOP; | |
e8894267 | 1933 | |
e61e0f51 | 1934 | intel_ring_advance(rq, cs); |
15648585 OM |
1935 | |
1936 | return 0; | |
1937 | } | |
1938 | ||
31bb59cc | 1939 | static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine) |
73d477f6 | 1940 | { |
c033666a | 1941 | struct drm_i915_private *dev_priv = engine->i915; |
31bb59cc CW |
1942 | I915_WRITE_IMR(engine, |
1943 | ~(engine->irq_enable_mask | engine->irq_keep_mask)); | |
1944 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
73d477f6 OM |
1945 | } |
1946 | ||
31bb59cc | 1947 | static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine) |
73d477f6 | 1948 | { |
c033666a | 1949 | struct drm_i915_private *dev_priv = engine->i915; |
31bb59cc | 1950 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
73d477f6 OM |
1951 | } |
1952 | ||
e61e0f51 | 1953 | static int gen8_emit_flush(struct i915_request *request, u32 mode) |
4712274c | 1954 | { |
73dec95e | 1955 | u32 cmd, *cs; |
4712274c | 1956 | |
73dec95e TU |
1957 | cs = intel_ring_begin(request, 4); |
1958 | if (IS_ERR(cs)) | |
1959 | return PTR_ERR(cs); | |
4712274c OM |
1960 | |
1961 | cmd = MI_FLUSH_DW + 1; | |
1962 | ||
f0a1fb10 CW |
1963 | /* We always require a command barrier so that subsequent |
1964 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1965 | * wrt the contents of the write cache being flushed to memory | |
1966 | * (and thus being coherent from the CPU). | |
1967 | */ | |
1968 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1969 | ||
7c9cf4e3 | 1970 | if (mode & EMIT_INVALIDATE) { |
f0a1fb10 | 1971 | cmd |= MI_INVALIDATE_TLB; |
5fc2805b | 1972 | if (request->engine->class == VIDEO_DECODE_CLASS) |
f0a1fb10 | 1973 | cmd |= MI_INVALIDATE_BSD; |
4712274c OM |
1974 | } |
1975 | ||
73dec95e TU |
1976 | *cs++ = cmd; |
1977 | *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; | |
1978 | *cs++ = 0; /* upper addr */ | |
1979 | *cs++ = 0; /* value */ | |
1980 | intel_ring_advance(request, cs); | |
4712274c OM |
1981 | |
1982 | return 0; | |
1983 | } | |
1984 | ||
e61e0f51 | 1985 | static int gen8_emit_flush_render(struct i915_request *request, |
7c9cf4e3 | 1986 | u32 mode) |
4712274c | 1987 | { |
b5321f30 | 1988 | struct intel_engine_cs *engine = request->engine; |
bde13ebd | 1989 | u32 scratch_addr = |
51797499 | 1990 | i915_scratch_offset(engine->i915) + 2 * CACHELINE_BYTES; |
0b2d0934 | 1991 | bool vf_flush_wa = false, dc_flush_wa = false; |
73dec95e | 1992 | u32 *cs, flags = 0; |
0b2d0934 | 1993 | int len; |
4712274c OM |
1994 | |
1995 | flags |= PIPE_CONTROL_CS_STALL; | |
1996 | ||
7c9cf4e3 | 1997 | if (mode & EMIT_FLUSH) { |
4712274c OM |
1998 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
1999 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 2000 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 2001 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4712274c OM |
2002 | } |
2003 | ||
7c9cf4e3 | 2004 | if (mode & EMIT_INVALIDATE) { |
4712274c OM |
2005 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
2006 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
2007 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
2008 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
2009 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
2010 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
2011 | flags |= PIPE_CONTROL_QW_WRITE; | |
2012 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
4712274c | 2013 | |
1a5a9ce7 BW |
2014 | /* |
2015 | * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL | |
2016 | * pipe control. | |
2017 | */ | |
cf819eff | 2018 | if (IS_GEN(request->i915, 9)) |
1a5a9ce7 | 2019 | vf_flush_wa = true; |
0b2d0934 MK |
2020 | |
2021 | /* WaForGAMHang:kbl */ | |
2022 | if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0)) | |
2023 | dc_flush_wa = true; | |
1a5a9ce7 | 2024 | } |
9647ff36 | 2025 | |
0b2d0934 MK |
2026 | len = 6; |
2027 | ||
2028 | if (vf_flush_wa) | |
2029 | len += 6; | |
2030 | ||
2031 | if (dc_flush_wa) | |
2032 | len += 12; | |
2033 | ||
73dec95e TU |
2034 | cs = intel_ring_begin(request, len); |
2035 | if (IS_ERR(cs)) | |
2036 | return PTR_ERR(cs); | |
4712274c | 2037 | |
9f235dfa TU |
2038 | if (vf_flush_wa) |
2039 | cs = gen8_emit_pipe_control(cs, 0, 0); | |
9647ff36 | 2040 | |
9f235dfa TU |
2041 | if (dc_flush_wa) |
2042 | cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE, | |
2043 | 0); | |
0b2d0934 | 2044 | |
9f235dfa | 2045 | cs = gen8_emit_pipe_control(cs, flags, scratch_addr); |
0b2d0934 | 2046 | |
9f235dfa TU |
2047 | if (dc_flush_wa) |
2048 | cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0); | |
0b2d0934 | 2049 | |
73dec95e | 2050 | intel_ring_advance(request, cs); |
4712274c OM |
2051 | |
2052 | return 0; | |
2053 | } | |
2054 | ||
7c17d377 CW |
2055 | /* |
2056 | * Reserve space for 2 NOOPs at the end of each request to be | |
2057 | * used as a workaround for not being allowed to do lite | |
2058 | * restore with HEAD==TAIL (WaIdleLiteRestore). | |
2059 | */ | |
e1a73a54 | 2060 | static u32 *gen8_emit_wa_tail(struct i915_request *request, u32 *cs) |
4da46e1e | 2061 | { |
beecec90 CW |
2062 | /* Ensure there's always at least one preemption point per-request. */ |
2063 | *cs++ = MI_ARB_CHECK; | |
73dec95e TU |
2064 | *cs++ = MI_NOOP; |
2065 | request->wa_tail = intel_ring_offset(request, cs); | |
e1a73a54 CW |
2066 | |
2067 | return cs; | |
caddfe71 | 2068 | } |
4da46e1e | 2069 | |
85474441 | 2070 | static u32 *gen8_emit_fini_breadcrumb(struct i915_request *request, u32 *cs) |
caddfe71 | 2071 | { |
7c17d377 CW |
2072 | /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */ |
2073 | BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5)); | |
4da46e1e | 2074 | |
5013eb8c CW |
2075 | cs = gen8_emit_ggtt_write(cs, |
2076 | request->fence.seqno, | |
2077 | request->timeline->hwsp_offset); | |
2078 | ||
2079 | cs = gen8_emit_ggtt_write(cs, | |
2080 | request->global_seqno, | |
df77cd83 | 2081 | intel_hws_seqno_address(request->engine)); |
5013eb8c | 2082 | |
73dec95e | 2083 | *cs++ = MI_USER_INTERRUPT; |
74f94741 | 2084 | *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; |
5013eb8c | 2085 | |
73dec95e | 2086 | request->tail = intel_ring_offset(request, cs); |
ed1501d4 | 2087 | assert_ring_tail_valid(request->ring, request->tail); |
caddfe71 | 2088 | |
e1a73a54 | 2089 | return gen8_emit_wa_tail(request, cs); |
7c17d377 | 2090 | } |
98f29e8d | 2091 | |
85474441 | 2092 | static u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs) |
7c17d377 | 2093 | { |
6a623729 | 2094 | cs = gen8_emit_ggtt_write_rcs(cs, |
5013eb8c CW |
2095 | request->fence.seqno, |
2096 | request->timeline->hwsp_offset, | |
6a623729 CW |
2097 | PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | |
2098 | PIPE_CONTROL_DEPTH_CACHE_FLUSH | | |
2099 | PIPE_CONTROL_DC_FLUSH_ENABLE | | |
2100 | PIPE_CONTROL_FLUSH_ENABLE | | |
2101 | PIPE_CONTROL_CS_STALL); | |
2102 | ||
5013eb8c CW |
2103 | cs = gen8_emit_ggtt_write_rcs(cs, |
2104 | request->global_seqno, | |
2105 | intel_hws_seqno_address(request->engine), | |
2106 | PIPE_CONTROL_CS_STALL); | |
2107 | ||
73dec95e | 2108 | *cs++ = MI_USER_INTERRUPT; |
74f94741 | 2109 | *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; |
6a623729 | 2110 | |
73dec95e | 2111 | request->tail = intel_ring_offset(request, cs); |
ed1501d4 | 2112 | assert_ring_tail_valid(request->ring, request->tail); |
caddfe71 | 2113 | |
e1a73a54 | 2114 | return gen8_emit_wa_tail(request, cs); |
4da46e1e | 2115 | } |
98f29e8d | 2116 | |
e61e0f51 | 2117 | static int gen8_init_rcs_context(struct i915_request *rq) |
e7778be1 TD |
2118 | { |
2119 | int ret; | |
2120 | ||
452420d2 | 2121 | ret = intel_engine_emit_ctx_wa(rq); |
e7778be1 TD |
2122 | if (ret) |
2123 | return ret; | |
2124 | ||
e61e0f51 | 2125 | ret = intel_rcs_context_init_mocs(rq); |
3bbaba0c PA |
2126 | /* |
2127 | * Failing to program the MOCS is non-fatal.The system will not | |
2128 | * run at peak performance. So generate an error and carry on. | |
2129 | */ | |
2130 | if (ret) | |
2131 | DRM_ERROR("MOCS failed to program: expect performance issues.\n"); | |
2132 | ||
e61e0f51 | 2133 | return i915_gem_render_state_emit(rq); |
e7778be1 TD |
2134 | } |
2135 | ||
73e4d07f OM |
2136 | /** |
2137 | * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer | |
14bb2c11 | 2138 | * @engine: Engine Command Streamer. |
73e4d07f | 2139 | */ |
0bc40be8 | 2140 | void intel_logical_ring_cleanup(struct intel_engine_cs *engine) |
454afebd | 2141 | { |
6402c330 | 2142 | struct drm_i915_private *dev_priv; |
9832b9da | 2143 | |
27af5eea TU |
2144 | /* |
2145 | * Tasklet cannot be active at this point due intel_mark_active/idle | |
2146 | * so this is just for documentation. | |
2147 | */ | |
c6dce8f1 SAK |
2148 | if (WARN_ON(test_bit(TASKLET_STATE_SCHED, |
2149 | &engine->execlists.tasklet.state))) | |
2150 | tasklet_kill(&engine->execlists.tasklet); | |
27af5eea | 2151 | |
c033666a | 2152 | dev_priv = engine->i915; |
6402c330 | 2153 | |
0bc40be8 | 2154 | if (engine->buffer) { |
0bc40be8 | 2155 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
b0366a54 | 2156 | } |
48d82387 | 2157 | |
0bc40be8 TU |
2158 | if (engine->cleanup) |
2159 | engine->cleanup(engine); | |
48d82387 | 2160 | |
e8a9c58f | 2161 | intel_engine_cleanup_common(engine); |
17ee950d | 2162 | |
097d4f1c | 2163 | lrc_destroy_wa_ctx(engine); |
f3c9d407 | 2164 | |
c033666a | 2165 | engine->i915 = NULL; |
3b3f1650 AG |
2166 | dev_priv->engine[engine->id] = NULL; |
2167 | kfree(engine); | |
454afebd OM |
2168 | } |
2169 | ||
209b7955 | 2170 | void intel_execlists_set_default_submission(struct intel_engine_cs *engine) |
ddd66c51 | 2171 | { |
ff44ad51 | 2172 | engine->submit_request = execlists_submit_request; |
27a5f61b | 2173 | engine->cancel_requests = execlists_cancel_requests; |
e2f3496e | 2174 | engine->schedule = i915_schedule; |
c6dce8f1 | 2175 | engine->execlists.tasklet.func = execlists_submission_tasklet; |
aba5e278 | 2176 | |
1329115c CW |
2177 | engine->reset.prepare = execlists_reset_prepare; |
2178 | ||
aba5e278 CW |
2179 | engine->park = NULL; |
2180 | engine->unpark = NULL; | |
cf669b4e TU |
2181 | |
2182 | engine->flags |= I915_ENGINE_SUPPORTS_STATS; | |
2a694feb CW |
2183 | if (engine->i915->preempt_context) |
2184 | engine->flags |= I915_ENGINE_HAS_PREEMPTION; | |
3fed1808 CW |
2185 | |
2186 | engine->i915->caps.scheduler = | |
2187 | I915_SCHEDULER_CAP_ENABLED | | |
2188 | I915_SCHEDULER_CAP_PRIORITY; | |
2a694feb | 2189 | if (intel_engine_has_preemption(engine)) |
3fed1808 | 2190 | engine->i915->caps.scheduler |= I915_SCHEDULER_CAP_PREEMPTION; |
ddd66c51 CW |
2191 | } |
2192 | ||
c9cacf93 | 2193 | static void |
e1382efb | 2194 | logical_ring_default_vfuncs(struct intel_engine_cs *engine) |
c9cacf93 TU |
2195 | { |
2196 | /* Default vfuncs which can be overriden by each engine. */ | |
0bc40be8 | 2197 | engine->init_hw = gen8_init_common_ring; |
5adfb772 CW |
2198 | |
2199 | engine->reset.prepare = execlists_reset_prepare; | |
2200 | engine->reset.reset = execlists_reset; | |
2201 | engine->reset.finish = execlists_reset_finish; | |
e8a9c58f CW |
2202 | |
2203 | engine->context_pin = execlists_context_pin; | |
f73e7399 CW |
2204 | engine->request_alloc = execlists_request_alloc; |
2205 | ||
0bc40be8 | 2206 | engine->emit_flush = gen8_emit_flush; |
85474441 CW |
2207 | engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb; |
2208 | engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb; | |
ff44ad51 | 2209 | |
209b7955 | 2210 | engine->set_default_submission = intel_execlists_set_default_submission; |
ddd66c51 | 2211 | |
d4ccceb0 TU |
2212 | if (INTEL_GEN(engine->i915) < 11) { |
2213 | engine->irq_enable = gen8_logical_ring_enable_irq; | |
2214 | engine->irq_disable = gen8_logical_ring_disable_irq; | |
2215 | } else { | |
2216 | /* | |
2217 | * TODO: On Gen11 interrupt masks need to be clear | |
2218 | * to allow C6 entry. Keep interrupts enabled at | |
2219 | * and take the hit of generating extra interrupts | |
2220 | * until a more refined solution exists. | |
2221 | */ | |
2222 | } | |
0bc40be8 | 2223 | engine->emit_bb_start = gen8_emit_bb_start; |
c9cacf93 TU |
2224 | } |
2225 | ||
d9f3af96 | 2226 | static inline void |
c2c7f240 | 2227 | logical_ring_default_irqs(struct intel_engine_cs *engine) |
d9f3af96 | 2228 | { |
fa6f071d DCS |
2229 | unsigned int shift = 0; |
2230 | ||
2231 | if (INTEL_GEN(engine->i915) < 11) { | |
2232 | const u8 irq_shifts[] = { | |
2233 | [RCS] = GEN8_RCS_IRQ_SHIFT, | |
2234 | [BCS] = GEN8_BCS_IRQ_SHIFT, | |
2235 | [VCS] = GEN8_VCS1_IRQ_SHIFT, | |
2236 | [VCS2] = GEN8_VCS2_IRQ_SHIFT, | |
2237 | [VECS] = GEN8_VECS_IRQ_SHIFT, | |
2238 | }; | |
2239 | ||
2240 | shift = irq_shifts[engine->id]; | |
2241 | } | |
2242 | ||
0bc40be8 TU |
2243 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift; |
2244 | engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift; | |
d9f3af96 TU |
2245 | } |
2246 | ||
52954edd | 2247 | static int |
bb45438f TU |
2248 | logical_ring_setup(struct intel_engine_cs *engine) |
2249 | { | |
52954edd CW |
2250 | int err; |
2251 | ||
2252 | err = intel_engine_setup_common(engine); | |
2253 | if (err) | |
2254 | return err; | |
019bf277 | 2255 | |
bb45438f TU |
2256 | /* Intentionally left blank. */ |
2257 | engine->buffer = NULL; | |
2258 | ||
c6dce8f1 SAK |
2259 | tasklet_init(&engine->execlists.tasklet, |
2260 | execlists_submission_tasklet, (unsigned long)engine); | |
bb45438f | 2261 | |
bb45438f TU |
2262 | logical_ring_default_vfuncs(engine); |
2263 | logical_ring_default_irqs(engine); | |
52954edd CW |
2264 | |
2265 | return 0; | |
bb45438f TU |
2266 | } |
2267 | ||
486e93f7 | 2268 | static int logical_ring_init(struct intel_engine_cs *engine) |
a19d6ff2 | 2269 | { |
bc4237ec CW |
2270 | struct drm_i915_private *i915 = engine->i915; |
2271 | struct intel_engine_execlists * const execlists = &engine->execlists; | |
a19d6ff2 TU |
2272 | int ret; |
2273 | ||
019bf277 | 2274 | ret = intel_engine_init_common(engine); |
a19d6ff2 | 2275 | if (ret) |
b2164e48 | 2276 | return ret; |
a19d6ff2 | 2277 | |
a60acb22 DCS |
2278 | intel_engine_init_workarounds(engine); |
2279 | ||
bc4237ec CW |
2280 | if (HAS_LOGICAL_RING_ELSQ(i915)) { |
2281 | execlists->submit_reg = i915->regs + | |
05f0addd | 2282 | i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(engine)); |
bc4237ec | 2283 | execlists->ctrl_reg = i915->regs + |
05f0addd TD |
2284 | i915_mmio_reg_offset(RING_EXECLIST_CONTROL(engine)); |
2285 | } else { | |
bc4237ec | 2286 | execlists->submit_reg = i915->regs + |
05f0addd TD |
2287 | i915_mmio_reg_offset(RING_ELSP(engine)); |
2288 | } | |
693cfbf0 | 2289 | |
bc4237ec CW |
2290 | execlists->preempt_complete_status = ~0u; |
2291 | if (i915->preempt_context) { | |
ab82a063 | 2292 | struct intel_context *ce = |
bc4237ec | 2293 | to_intel_context(i915->preempt_context, engine); |
ab82a063 | 2294 | |
bc4237ec | 2295 | execlists->preempt_complete_status = |
ab82a063 CW |
2296 | upper_32_bits(ce->lrc_desc); |
2297 | } | |
d6376374 | 2298 | |
46592892 | 2299 | execlists->csb_status = |
0ca88ba0 | 2300 | &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX]; |
bc4237ec | 2301 | |
46592892 | 2302 | execlists->csb_write = |
0ca88ba0 | 2303 | &engine->status_page.addr[intel_hws_csb_write_index(i915)]; |
bc4237ec | 2304 | |
f4b58f04 | 2305 | reset_csb_pointers(execlists); |
c3160da9 | 2306 | |
a19d6ff2 | 2307 | return 0; |
a19d6ff2 TU |
2308 | } |
2309 | ||
88d2ba2e | 2310 | int logical_render_ring_init(struct intel_engine_cs *engine) |
a19d6ff2 | 2311 | { |
a19d6ff2 TU |
2312 | int ret; |
2313 | ||
52954edd CW |
2314 | ret = logical_ring_setup(engine); |
2315 | if (ret) | |
2316 | return ret; | |
bb45438f | 2317 | |
a19d6ff2 | 2318 | /* Override some for render ring. */ |
a19d6ff2 | 2319 | engine->init_context = gen8_init_rcs_context; |
a19d6ff2 | 2320 | engine->emit_flush = gen8_emit_flush_render; |
85474441 | 2321 | engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs; |
a19d6ff2 | 2322 | |
b2164e48 | 2323 | ret = logical_ring_init(engine); |
a19d6ff2 TU |
2324 | if (ret) |
2325 | return ret; | |
2326 | ||
2327 | ret = intel_init_workaround_bb(engine); | |
2328 | if (ret) { | |
2329 | /* | |
2330 | * We continue even if we fail to initialize WA batch | |
2331 | * because we only expect rare glitches but nothing | |
2332 | * critical to prevent us from using GPU | |
2333 | */ | |
2334 | DRM_ERROR("WA batch buffer initialization failed: %d\n", | |
2335 | ret); | |
2336 | } | |
2337 | ||
69bcdecf | 2338 | intel_engine_init_whitelist(engine); |
4a15c75c | 2339 | |
b2164e48 | 2340 | return 0; |
a19d6ff2 TU |
2341 | } |
2342 | ||
88d2ba2e | 2343 | int logical_xcs_ring_init(struct intel_engine_cs *engine) |
bb45438f | 2344 | { |
52954edd CW |
2345 | int err; |
2346 | ||
2347 | err = logical_ring_setup(engine); | |
2348 | if (err) | |
2349 | return err; | |
bb45438f TU |
2350 | |
2351 | return logical_ring_init(engine); | |
454afebd OM |
2352 | } |
2353 | ||
0cea6502 | 2354 | static u32 |
c033666a | 2355 | make_rpcs(struct drm_i915_private *dev_priv) |
0cea6502 | 2356 | { |
0258404f JN |
2357 | bool subslice_pg = RUNTIME_INFO(dev_priv)->sseu.has_subslice_pg; |
2358 | u8 slices = hweight8(RUNTIME_INFO(dev_priv)->sseu.slice_mask); | |
2359 | u8 subslices = hweight8(RUNTIME_INFO(dev_priv)->sseu.subslice_mask[0]); | |
0cea6502 JM |
2360 | u32 rpcs = 0; |
2361 | ||
2362 | /* | |
2363 | * No explicit RPCS request is needed to ensure full | |
2364 | * slice/subslice/EU enablement prior to Gen9. | |
2365 | */ | |
c033666a | 2366 | if (INTEL_GEN(dev_priv) < 9) |
0cea6502 JM |
2367 | return 0; |
2368 | ||
b212f0a4 TU |
2369 | /* |
2370 | * Since the SScount bitfield in GEN8_R_PWR_CLK_STATE is only three bits | |
2371 | * wide and Icelake has up to eight subslices, specfial programming is | |
2372 | * needed in order to correctly enable all subslices. | |
2373 | * | |
2374 | * According to documentation software must consider the configuration | |
2375 | * as 2x4x8 and hardware will translate this to 1x8x8. | |
2376 | * | |
2377 | * Furthemore, even though SScount is three bits, maximum documented | |
2378 | * value for it is four. From this some rules/restrictions follow: | |
2379 | * | |
2380 | * 1. | |
2381 | * If enabled subslice count is greater than four, two whole slices must | |
2382 | * be enabled instead. | |
2383 | * | |
2384 | * 2. | |
2385 | * When more than one slice is enabled, hardware ignores the subslice | |
2386 | * count altogether. | |
2387 | * | |
2388 | * From these restrictions it follows that it is not possible to enable | |
2389 | * a count of subslices between the SScount maximum of four restriction, | |
2390 | * and the maximum available number on a particular SKU. Either all | |
2391 | * subslices are enabled, or a count between one and four on the first | |
2392 | * slice. | |
2393 | */ | |
cf819eff | 2394 | if (IS_GEN(dev_priv, 11) && slices == 1 && subslices >= 4) { |
b212f0a4 TU |
2395 | GEM_BUG_ON(subslices & 1); |
2396 | ||
2397 | subslice_pg = false; | |
2398 | slices *= 2; | |
2399 | } | |
2400 | ||
0cea6502 JM |
2401 | /* |
2402 | * Starting in Gen9, render power gating can leave | |
2403 | * slice/subslice/EU in a partially enabled state. We | |
2404 | * must make an explicit request through RPCS for full | |
2405 | * enablement. | |
2406 | */ | |
0258404f | 2407 | if (RUNTIME_INFO(dev_priv)->sseu.has_slice_pg) { |
b212f0a4 TU |
2408 | u32 mask, val = slices; |
2409 | ||
2410 | if (INTEL_GEN(dev_priv) >= 11) { | |
2411 | mask = GEN11_RPCS_S_CNT_MASK; | |
2412 | val <<= GEN11_RPCS_S_CNT_SHIFT; | |
2413 | } else { | |
2414 | mask = GEN8_RPCS_S_CNT_MASK; | |
2415 | val <<= GEN8_RPCS_S_CNT_SHIFT; | |
2416 | } | |
2417 | ||
2418 | GEM_BUG_ON(val & ~mask); | |
2419 | val &= mask; | |
2420 | ||
2421 | rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_S_CNT_ENABLE | val; | |
0cea6502 JM |
2422 | } |
2423 | ||
b212f0a4 TU |
2424 | if (subslice_pg) { |
2425 | u32 val = subslices; | |
2426 | ||
2427 | val <<= GEN8_RPCS_SS_CNT_SHIFT; | |
2428 | ||
2429 | GEM_BUG_ON(val & ~GEN8_RPCS_SS_CNT_MASK); | |
2430 | val &= GEN8_RPCS_SS_CNT_MASK; | |
2431 | ||
2432 | rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_SS_CNT_ENABLE | val; | |
0cea6502 JM |
2433 | } |
2434 | ||
0258404f | 2435 | if (RUNTIME_INFO(dev_priv)->sseu.has_eu_pg) { |
b212f0a4 TU |
2436 | u32 val; |
2437 | ||
0258404f | 2438 | val = RUNTIME_INFO(dev_priv)->sseu.eu_per_subslice << |
b212f0a4 TU |
2439 | GEN8_RPCS_EU_MIN_SHIFT; |
2440 | GEM_BUG_ON(val & ~GEN8_RPCS_EU_MIN_MASK); | |
2441 | val &= GEN8_RPCS_EU_MIN_MASK; | |
2442 | ||
2443 | rpcs |= val; | |
2444 | ||
0258404f | 2445 | val = RUNTIME_INFO(dev_priv)->sseu.eu_per_subslice << |
b212f0a4 TU |
2446 | GEN8_RPCS_EU_MAX_SHIFT; |
2447 | GEM_BUG_ON(val & ~GEN8_RPCS_EU_MAX_MASK); | |
2448 | val &= GEN8_RPCS_EU_MAX_MASK; | |
2449 | ||
2450 | rpcs |= val; | |
2451 | ||
0cea6502 JM |
2452 | rpcs |= GEN8_RPCS_ENABLE; |
2453 | } | |
2454 | ||
2455 | return rpcs; | |
2456 | } | |
2457 | ||
0bc40be8 | 2458 | static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine) |
71562919 MT |
2459 | { |
2460 | u32 indirect_ctx_offset; | |
2461 | ||
c033666a | 2462 | switch (INTEL_GEN(engine->i915)) { |
71562919 | 2463 | default: |
c033666a | 2464 | MISSING_CASE(INTEL_GEN(engine->i915)); |
71562919 | 2465 | /* fall through */ |
fd034c77 MT |
2466 | case 11: |
2467 | indirect_ctx_offset = | |
2468 | GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
2469 | break; | |
7bd0a2c6 MT |
2470 | case 10: |
2471 | indirect_ctx_offset = | |
2472 | GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
2473 | break; | |
71562919 MT |
2474 | case 9: |
2475 | indirect_ctx_offset = | |
2476 | GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
2477 | break; | |
2478 | case 8: | |
2479 | indirect_ctx_offset = | |
2480 | GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
2481 | break; | |
2482 | } | |
2483 | ||
2484 | return indirect_ctx_offset; | |
2485 | } | |
2486 | ||
56e51bf0 | 2487 | static void execlists_init_reg_state(u32 *regs, |
a3aabe86 CW |
2488 | struct i915_gem_context *ctx, |
2489 | struct intel_engine_cs *engine, | |
2490 | struct intel_ring *ring) | |
8670d6f9 | 2491 | { |
a3aabe86 | 2492 | struct drm_i915_private *dev_priv = engine->i915; |
56e51bf0 | 2493 | u32 base = engine->mmio_base; |
1fc44d9b | 2494 | bool rcs = engine->class == RENDER_CLASS; |
56e51bf0 TU |
2495 | |
2496 | /* A context is actually a big batch buffer with several | |
2497 | * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The | |
2498 | * values we are setting here are only for the first context restore: | |
2499 | * on a subsequent save, the GPU will recreate this batchbuffer with new | |
2500 | * values (including all the missing MI_LOAD_REGISTER_IMM commands that | |
2501 | * we are not initializing here). | |
2502 | */ | |
2503 | regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) | | |
2504 | MI_LRI_FORCE_POSTED; | |
2505 | ||
2506 | CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(engine), | |
ee435831 | 2507 | _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) | |
08e3e21a | 2508 | _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH)); |
ee435831 PZ |
2509 | if (INTEL_GEN(dev_priv) < 11) { |
2510 | regs[CTX_CONTEXT_CONTROL + 1] |= | |
2511 | _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT | | |
2512 | CTX_CTRL_RS_CTX_ENABLE); | |
2513 | } | |
56e51bf0 TU |
2514 | CTX_REG(regs, CTX_RING_HEAD, RING_HEAD(base), 0); |
2515 | CTX_REG(regs, CTX_RING_TAIL, RING_TAIL(base), 0); | |
2516 | CTX_REG(regs, CTX_RING_BUFFER_START, RING_START(base), 0); | |
2517 | CTX_REG(regs, CTX_RING_BUFFER_CONTROL, RING_CTL(base), | |
2518 | RING_CTL_SIZE(ring->size) | RING_VALID); | |
2519 | CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0); | |
2520 | CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0); | |
2521 | CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT); | |
2522 | CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0); | |
2523 | CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0); | |
2524 | CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0); | |
2525 | if (rcs) { | |
604a8f6f CW |
2526 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; |
2527 | ||
56e51bf0 TU |
2528 | CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0); |
2529 | CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET, | |
2530 | RING_INDIRECT_CTX_OFFSET(base), 0); | |
604a8f6f | 2531 | if (wa_ctx->indirect_ctx.size) { |
bde13ebd | 2532 | u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); |
17ee950d | 2533 | |
56e51bf0 | 2534 | regs[CTX_RCS_INDIRECT_CTX + 1] = |
097d4f1c TU |
2535 | (ggtt_offset + wa_ctx->indirect_ctx.offset) | |
2536 | (wa_ctx->indirect_ctx.size / CACHELINE_BYTES); | |
17ee950d | 2537 | |
56e51bf0 | 2538 | regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] = |
0bc40be8 | 2539 | intel_lr_indirect_ctx_offset(engine) << 6; |
604a8f6f CW |
2540 | } |
2541 | ||
2542 | CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0); | |
2543 | if (wa_ctx->per_ctx.size) { | |
2544 | u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); | |
17ee950d | 2545 | |
56e51bf0 | 2546 | regs[CTX_BB_PER_CTX_PTR + 1] = |
097d4f1c | 2547 | (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01; |
17ee950d | 2548 | } |
8670d6f9 | 2549 | } |
56e51bf0 TU |
2550 | |
2551 | regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED; | |
2552 | ||
2553 | CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0); | |
0d925ea0 | 2554 | /* PDP values well be assigned later if needed */ |
56e51bf0 TU |
2555 | CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), 0); |
2556 | CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), 0); | |
2557 | CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), 0); | |
2558 | CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), 0); | |
2559 | CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), 0); | |
2560 | CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), 0); | |
2561 | CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0); | |
2562 | CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0); | |
d7b2633d | 2563 | |
4bdafb9d | 2564 | if (i915_vm_is_48bit(&ctx->ppgtt->vm)) { |
2dba3239 MT |
2565 | /* 64b PPGTT (48bit canonical) |
2566 | * PDP0_DESCRIPTOR contains the base address to PML4 and | |
2567 | * other PDP Descriptors are ignored. | |
2568 | */ | |
4bdafb9d | 2569 | ASSIGN_CTX_PML4(ctx->ppgtt, regs); |
e8894267 CW |
2570 | } else { |
2571 | ASSIGN_CTX_PDP(ctx->ppgtt, regs, 3); | |
2572 | ASSIGN_CTX_PDP(ctx->ppgtt, regs, 2); | |
2573 | ASSIGN_CTX_PDP(ctx->ppgtt, regs, 1); | |
2574 | ASSIGN_CTX_PDP(ctx->ppgtt, regs, 0); | |
2dba3239 MT |
2575 | } |
2576 | ||
56e51bf0 TU |
2577 | if (rcs) { |
2578 | regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); | |
8e525cb4 | 2579 | CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, 0); |
19f81df2 RB |
2580 | |
2581 | i915_oa_init_reg_state(engine, ctx, regs); | |
8670d6f9 | 2582 | } |
d0f5cc5d CW |
2583 | |
2584 | regs[CTX_END] = MI_BATCH_BUFFER_END; | |
2585 | if (INTEL_GEN(dev_priv) >= 10) | |
2586 | regs[CTX_END] |= BIT(0); | |
a3aabe86 CW |
2587 | } |
2588 | ||
2589 | static int | |
2590 | populate_lr_context(struct i915_gem_context *ctx, | |
2591 | struct drm_i915_gem_object *ctx_obj, | |
2592 | struct intel_engine_cs *engine, | |
2593 | struct intel_ring *ring) | |
2594 | { | |
2595 | void *vaddr; | |
d2b4b979 | 2596 | u32 *regs; |
a3aabe86 CW |
2597 | int ret; |
2598 | ||
2599 | ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); | |
2600 | if (ret) { | |
2601 | DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); | |
2602 | return ret; | |
2603 | } | |
2604 | ||
2605 | vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB); | |
2606 | if (IS_ERR(vaddr)) { | |
2607 | ret = PTR_ERR(vaddr); | |
2608 | DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret); | |
2609 | return ret; | |
2610 | } | |
a4f5ea64 | 2611 | ctx_obj->mm.dirty = true; |
a3aabe86 | 2612 | |
d2b4b979 CW |
2613 | if (engine->default_state) { |
2614 | /* | |
2615 | * We only want to copy over the template context state; | |
2616 | * skipping over the headers reserved for GuC communication, | |
2617 | * leaving those as zero. | |
2618 | */ | |
2619 | const unsigned long start = LRC_HEADER_PAGES * PAGE_SIZE; | |
2620 | void *defaults; | |
2621 | ||
2622 | defaults = i915_gem_object_pin_map(engine->default_state, | |
2623 | I915_MAP_WB); | |
aaefa06a MA |
2624 | if (IS_ERR(defaults)) { |
2625 | ret = PTR_ERR(defaults); | |
2626 | goto err_unpin_ctx; | |
2627 | } | |
d2b4b979 CW |
2628 | |
2629 | memcpy(vaddr + start, defaults + start, engine->context_size); | |
2630 | i915_gem_object_unpin_map(engine->default_state); | |
2631 | } | |
2632 | ||
a3aabe86 CW |
2633 | /* The second page of the context object contains some fields which must |
2634 | * be set up prior to the first execution. */ | |
d2b4b979 CW |
2635 | regs = vaddr + LRC_STATE_PN * PAGE_SIZE; |
2636 | execlists_init_reg_state(regs, ctx, engine, ring); | |
2637 | if (!engine->default_state) | |
2638 | regs[CTX_CONTEXT_CONTROL + 1] |= | |
2639 | _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); | |
05f0addd | 2640 | if (ctx == ctx->i915->preempt_context && INTEL_GEN(engine->i915) < 11) |
517aaffe CW |
2641 | regs[CTX_CONTEXT_CONTROL + 1] |= |
2642 | _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | | |
2643 | CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT); | |
8670d6f9 | 2644 | |
aaefa06a | 2645 | err_unpin_ctx: |
7d774cac | 2646 | i915_gem_object_unpin_map(ctx_obj); |
aaefa06a | 2647 | return ret; |
8670d6f9 OM |
2648 | } |
2649 | ||
e2efd130 | 2650 | static int execlists_context_deferred_alloc(struct i915_gem_context *ctx, |
1fc44d9b CW |
2651 | struct intel_engine_cs *engine, |
2652 | struct intel_context *ce) | |
ede7d42b | 2653 | { |
8c857917 | 2654 | struct drm_i915_gem_object *ctx_obj; |
bf3783e5 | 2655 | struct i915_vma *vma; |
739f3abd | 2656 | u32 context_size; |
7e37f889 | 2657 | struct intel_ring *ring; |
a89d1f92 | 2658 | struct i915_timeline *timeline; |
8c857917 OM |
2659 | int ret; |
2660 | ||
1d2a19c2 CW |
2661 | if (ce->state) |
2662 | return 0; | |
ede7d42b | 2663 | |
63ffbcda | 2664 | context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE); |
8c857917 | 2665 | |
0b29c75a MT |
2666 | /* |
2667 | * Before the actual start of the context image, we insert a few pages | |
2668 | * for our own use and for sharing with the GuC. | |
2669 | */ | |
2670 | context_size += LRC_HEADER_PAGES * PAGE_SIZE; | |
d1675198 | 2671 | |
12d79d78 | 2672 | ctx_obj = i915_gem_object_create(ctx->i915, context_size); |
467d3578 CW |
2673 | if (IS_ERR(ctx_obj)) |
2674 | return PTR_ERR(ctx_obj); | |
8c857917 | 2675 | |
82ad6443 | 2676 | vma = i915_vma_instance(ctx_obj, &ctx->i915->ggtt.vm, NULL); |
bf3783e5 CW |
2677 | if (IS_ERR(vma)) { |
2678 | ret = PTR_ERR(vma); | |
2679 | goto error_deref_obj; | |
2680 | } | |
2681 | ||
52954edd | 2682 | timeline = i915_timeline_create(ctx->i915, ctx->name, NULL); |
a89d1f92 CW |
2683 | if (IS_ERR(timeline)) { |
2684 | ret = PTR_ERR(timeline); | |
2685 | goto error_deref_obj; | |
2686 | } | |
2687 | ||
2688 | ring = intel_engine_create_ring(engine, timeline, ctx->ring_size); | |
2689 | i915_timeline_put(timeline); | |
dca33ecc CW |
2690 | if (IS_ERR(ring)) { |
2691 | ret = PTR_ERR(ring); | |
e84fe803 | 2692 | goto error_deref_obj; |
8670d6f9 OM |
2693 | } |
2694 | ||
dca33ecc | 2695 | ret = populate_lr_context(ctx, ctx_obj, engine, ring); |
8670d6f9 OM |
2696 | if (ret) { |
2697 | DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); | |
dca33ecc | 2698 | goto error_ring_free; |
84c2377f OM |
2699 | } |
2700 | ||
dca33ecc | 2701 | ce->ring = ring; |
bf3783e5 | 2702 | ce->state = vma; |
ede7d42b OM |
2703 | |
2704 | return 0; | |
8670d6f9 | 2705 | |
dca33ecc | 2706 | error_ring_free: |
7e37f889 | 2707 | intel_ring_free(ring); |
e84fe803 | 2708 | error_deref_obj: |
f8c417cd | 2709 | i915_gem_object_put(ctx_obj); |
8670d6f9 | 2710 | return ret; |
ede7d42b | 2711 | } |
3e5b6f05 | 2712 | |
dee60ca1 | 2713 | void intel_lr_context_resume(struct drm_i915_private *i915) |
3e5b6f05 | 2714 | { |
e2f80391 | 2715 | struct intel_engine_cs *engine; |
bafb2f7d | 2716 | struct i915_gem_context *ctx; |
3b3f1650 | 2717 | enum intel_engine_id id; |
bafb2f7d | 2718 | |
dee60ca1 CW |
2719 | /* |
2720 | * Because we emit WA_TAIL_DWORDS there may be a disparity | |
bafb2f7d CW |
2721 | * between our bookkeeping in ce->ring->head and ce->ring->tail and |
2722 | * that stored in context. As we only write new commands from | |
2723 | * ce->ring->tail onwards, everything before that is junk. If the GPU | |
2724 | * starts reading from its RING_HEAD from the context, it may try to | |
2725 | * execute that junk and die. | |
2726 | * | |
2727 | * So to avoid that we reset the context images upon resume. For | |
2728 | * simplicity, we just zero everything out. | |
2729 | */ | |
dee60ca1 CW |
2730 | list_for_each_entry(ctx, &i915->contexts.list, link) { |
2731 | for_each_engine(engine, i915, id) { | |
ab82a063 CW |
2732 | struct intel_context *ce = |
2733 | to_intel_context(ctx, engine); | |
3e5b6f05 | 2734 | |
bafb2f7d CW |
2735 | if (!ce->state) |
2736 | continue; | |
7d774cac | 2737 | |
dee60ca1 | 2738 | intel_ring_reset(ce->ring, 0); |
3e5b6f05 | 2739 | |
8e525cb4 TU |
2740 | if (ce->pin_count) /* otherwise done in context_pin */ |
2741 | __execlists_update_reg_state(engine, ce); | |
bafb2f7d | 2742 | } |
3e5b6f05 TD |
2743 | } |
2744 | } | |
2c66555e | 2745 | |
0212bdef CW |
2746 | void intel_execlists_show_requests(struct intel_engine_cs *engine, |
2747 | struct drm_printer *m, | |
2748 | void (*show_request)(struct drm_printer *m, | |
2749 | struct i915_request *rq, | |
2750 | const char *prefix), | |
2751 | unsigned int max) | |
2752 | { | |
2753 | const struct intel_engine_execlists *execlists = &engine->execlists; | |
2754 | struct i915_request *rq, *last; | |
2755 | unsigned long flags; | |
2756 | unsigned int count; | |
2757 | struct rb_node *rb; | |
2758 | ||
2759 | spin_lock_irqsave(&engine->timeline.lock, flags); | |
2760 | ||
2761 | last = NULL; | |
2762 | count = 0; | |
2763 | list_for_each_entry(rq, &engine->timeline.requests, link) { | |
2764 | if (count++ < max - 1) | |
2765 | show_request(m, rq, "\t\tE "); | |
2766 | else | |
2767 | last = rq; | |
2768 | } | |
2769 | if (last) { | |
2770 | if (count > max) { | |
2771 | drm_printf(m, | |
2772 | "\t\t...skipping %d executing requests...\n", | |
2773 | count - max); | |
2774 | } | |
2775 | show_request(m, last, "\t\tE "); | |
2776 | } | |
2777 | ||
2778 | last = NULL; | |
2779 | count = 0; | |
2780 | drm_printf(m, "\t\tQueue priority: %d\n", execlists->queue_priority); | |
2781 | for (rb = rb_first_cached(&execlists->queue); rb; rb = rb_next(rb)) { | |
2782 | struct i915_priolist *p = rb_entry(rb, typeof(*p), node); | |
2783 | int i; | |
2784 | ||
2785 | priolist_for_each_request(rq, p, i) { | |
2786 | if (count++ < max - 1) | |
2787 | show_request(m, rq, "\t\tQ "); | |
2788 | else | |
2789 | last = rq; | |
2790 | } | |
2791 | } | |
2792 | if (last) { | |
2793 | if (count > max) { | |
2794 | drm_printf(m, | |
2795 | "\t\t...skipping %d queued requests...\n", | |
2796 | count - max); | |
2797 | } | |
2798 | show_request(m, last, "\t\tQ "); | |
2799 | } | |
2800 | ||
2801 | spin_unlock_irqrestore(&engine->timeline.lock, flags); | |
2802 | } | |
2803 | ||
2c66555e CW |
2804 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) |
2805 | #include "selftests/intel_lrc.c" | |
2806 | #endif |