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b20385f1 OM |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * Michel Thierry <michel.thierry@intel.com> | |
26 | * Thomas Daniel <thomas.daniel@intel.com> | |
27 | * Oscar Mateo <oscar.mateo@intel.com> | |
28 | * | |
29 | */ | |
30 | ||
73e4d07f OM |
31 | /** |
32 | * DOC: Logical Rings, Logical Ring Contexts and Execlists | |
33 | * | |
34 | * Motivation: | |
b20385f1 OM |
35 | * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". |
36 | * These expanded contexts enable a number of new abilities, especially | |
37 | * "Execlists" (also implemented in this file). | |
38 | * | |
73e4d07f OM |
39 | * One of the main differences with the legacy HW contexts is that logical |
40 | * ring contexts incorporate many more things to the context's state, like | |
41 | * PDPs or ringbuffer control registers: | |
42 | * | |
43 | * The reason why PDPs are included in the context is straightforward: as | |
44 | * PPGTTs (per-process GTTs) are actually per-context, having the PDPs | |
45 | * contained there mean you don't need to do a ppgtt->switch_mm yourself, | |
46 | * instead, the GPU will do it for you on the context switch. | |
47 | * | |
48 | * But, what about the ringbuffer control registers (head, tail, etc..)? | |
49 | * shouldn't we just need a set of those per engine command streamer? This is | |
50 | * where the name "Logical Rings" starts to make sense: by virtualizing the | |
51 | * rings, the engine cs shifts to a new "ring buffer" with every context | |
52 | * switch. When you want to submit a workload to the GPU you: A) choose your | |
53 | * context, B) find its appropriate virtualized ring, C) write commands to it | |
54 | * and then, finally, D) tell the GPU to switch to that context. | |
55 | * | |
56 | * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch | |
57 | * to a contexts is via a context execution list, ergo "Execlists". | |
58 | * | |
59 | * LRC implementation: | |
60 | * Regarding the creation of contexts, we have: | |
61 | * | |
62 | * - One global default context. | |
63 | * - One local default context for each opened fd. | |
64 | * - One local extra context for each context create ioctl call. | |
65 | * | |
66 | * Now that ringbuffers belong per-context (and not per-engine, like before) | |
67 | * and that contexts are uniquely tied to a given engine (and not reusable, | |
68 | * like before) we need: | |
69 | * | |
70 | * - One ringbuffer per-engine inside each context. | |
71 | * - One backing object per-engine inside each context. | |
72 | * | |
73 | * The global default context starts its life with these new objects fully | |
74 | * allocated and populated. The local default context for each opened fd is | |
75 | * more complex, because we don't know at creation time which engine is going | |
76 | * to use them. To handle this, we have implemented a deferred creation of LR | |
77 | * contexts: | |
78 | * | |
79 | * The local context starts its life as a hollow or blank holder, that only | |
80 | * gets populated for a given engine once we receive an execbuffer. If later | |
81 | * on we receive another execbuffer ioctl for the same context but a different | |
82 | * engine, we allocate/populate a new ringbuffer and context backing object and | |
83 | * so on. | |
84 | * | |
85 | * Finally, regarding local contexts created using the ioctl call: as they are | |
86 | * only allowed with the render ring, we can allocate & populate them right | |
87 | * away (no need to defer anything, at least for now). | |
88 | * | |
89 | * Execlists implementation: | |
b20385f1 OM |
90 | * Execlists are the new method by which, on gen8+ hardware, workloads are |
91 | * submitted for execution (as opposed to the legacy, ringbuffer-based, method). | |
73e4d07f OM |
92 | * This method works as follows: |
93 | * | |
94 | * When a request is committed, its commands (the BB start and any leading or | |
95 | * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer | |
96 | * for the appropriate context. The tail pointer in the hardware context is not | |
97 | * updated at this time, but instead, kept by the driver in the ringbuffer | |
98 | * structure. A structure representing this request is added to a request queue | |
99 | * for the appropriate engine: this structure contains a copy of the context's | |
100 | * tail after the request was written to the ring buffer and a pointer to the | |
101 | * context itself. | |
102 | * | |
103 | * If the engine's request queue was empty before the request was added, the | |
104 | * queue is processed immediately. Otherwise the queue will be processed during | |
105 | * a context switch interrupt. In any case, elements on the queue will get sent | |
106 | * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a | |
107 | * globally unique 20-bits submission ID. | |
108 | * | |
109 | * When execution of a request completes, the GPU updates the context status | |
110 | * buffer with a context complete event and generates a context switch interrupt. | |
111 | * During the interrupt handling, the driver examines the events in the buffer: | |
112 | * for each context complete event, if the announced ID matches that on the head | |
113 | * of the request queue, then that request is retired and removed from the queue. | |
114 | * | |
115 | * After processing, if any requests were retired and the queue is not empty | |
116 | * then a new execution list can be submitted. The two requests at the front of | |
117 | * the queue are next to be submitted but since a context may not occur twice in | |
118 | * an execution list, if subsequent requests have the same ID as the first then | |
119 | * the two requests must be combined. This is done simply by discarding requests | |
120 | * at the head of the queue until either only one requests is left (in which case | |
121 | * we use a NULL second context) or the first two requests have unique IDs. | |
122 | * | |
123 | * By always executing the first two requests in the queue the driver ensures | |
124 | * that the GPU is kept as busy as possible. In the case where a single context | |
125 | * completes but a second context is still executing, the request for this second | |
126 | * context will be at the head of the queue when we remove the first one. This | |
127 | * request will then be resubmitted along with a new request for a different context, | |
128 | * which will cause the hardware to continue executing the second request and queue | |
129 | * the new request (the GPU detects the condition of a context getting preempted | |
130 | * with the same context and optimizes the context switch flow by not doing | |
131 | * preemption, but just sampling the new tail pointer). | |
132 | * | |
b20385f1 | 133 | */ |
27af5eea | 134 | #include <linux/interrupt.h> |
b20385f1 OM |
135 | |
136 | #include <drm/drmP.h> | |
137 | #include <drm/i915_drm.h> | |
138 | #include "i915_drv.h" | |
3bbaba0c | 139 | #include "intel_mocs.h" |
127f1003 | 140 | |
468c6816 | 141 | #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) |
8c857917 OM |
142 | #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) |
143 | #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) | |
144 | ||
e981e7b1 TD |
145 | #define RING_EXECLIST_QFULL (1 << 0x2) |
146 | #define RING_EXECLIST1_VALID (1 << 0x3) | |
147 | #define RING_EXECLIST0_VALID (1 << 0x4) | |
148 | #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) | |
149 | #define RING_EXECLIST1_ACTIVE (1 << 0x11) | |
150 | #define RING_EXECLIST0_ACTIVE (1 << 0x12) | |
151 | ||
152 | #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) | |
153 | #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) | |
154 | #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) | |
155 | #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) | |
156 | #define GEN8_CTX_STATUS_COMPLETE (1 << 4) | |
157 | #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) | |
8670d6f9 | 158 | |
70c2a24d CW |
159 | #define GEN8_CTX_STATUS_COMPLETED_MASK \ |
160 | (GEN8_CTX_STATUS_ACTIVE_IDLE | \ | |
161 | GEN8_CTX_STATUS_PREEMPTED | \ | |
162 | GEN8_CTX_STATUS_ELEMENT_SWITCH) | |
163 | ||
8670d6f9 OM |
164 | #define CTX_LRI_HEADER_0 0x01 |
165 | #define CTX_CONTEXT_CONTROL 0x02 | |
166 | #define CTX_RING_HEAD 0x04 | |
167 | #define CTX_RING_TAIL 0x06 | |
168 | #define CTX_RING_BUFFER_START 0x08 | |
169 | #define CTX_RING_BUFFER_CONTROL 0x0a | |
170 | #define CTX_BB_HEAD_U 0x0c | |
171 | #define CTX_BB_HEAD_L 0x0e | |
172 | #define CTX_BB_STATE 0x10 | |
173 | #define CTX_SECOND_BB_HEAD_U 0x12 | |
174 | #define CTX_SECOND_BB_HEAD_L 0x14 | |
175 | #define CTX_SECOND_BB_STATE 0x16 | |
176 | #define CTX_BB_PER_CTX_PTR 0x18 | |
177 | #define CTX_RCS_INDIRECT_CTX 0x1a | |
178 | #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c | |
179 | #define CTX_LRI_HEADER_1 0x21 | |
180 | #define CTX_CTX_TIMESTAMP 0x22 | |
181 | #define CTX_PDP3_UDW 0x24 | |
182 | #define CTX_PDP3_LDW 0x26 | |
183 | #define CTX_PDP2_UDW 0x28 | |
184 | #define CTX_PDP2_LDW 0x2a | |
185 | #define CTX_PDP1_UDW 0x2c | |
186 | #define CTX_PDP1_LDW 0x2e | |
187 | #define CTX_PDP0_UDW 0x30 | |
188 | #define CTX_PDP0_LDW 0x32 | |
189 | #define CTX_LRI_HEADER_2 0x41 | |
190 | #define CTX_R_PWR_CLK_STATE 0x42 | |
191 | #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 | |
192 | ||
0d925ea0 | 193 | #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \ |
f0f59a00 | 194 | (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \ |
0d925ea0 VS |
195 | (reg_state)[(pos)+1] = (val); \ |
196 | } while (0) | |
197 | ||
198 | #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \ | |
d852c7bf | 199 | const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \ |
e5815a2e MT |
200 | reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \ |
201 | reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \ | |
9244a817 | 202 | } while (0) |
e5815a2e | 203 | |
9244a817 | 204 | #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \ |
2dba3239 MT |
205 | reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \ |
206 | reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \ | |
9244a817 | 207 | } while (0) |
2dba3239 | 208 | |
71562919 MT |
209 | #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 |
210 | #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26 | |
84b790f8 | 211 | |
0e93cdd4 CW |
212 | /* Typical size of the average request (2 pipecontrols and a MI_BB) */ |
213 | #define EXECLISTS_REQUEST_SIZE 64 /* bytes */ | |
214 | ||
a3aabe86 CW |
215 | #define WA_TAIL_DWORDS 2 |
216 | ||
e2efd130 | 217 | static int execlists_context_deferred_alloc(struct i915_gem_context *ctx, |
978f1e09 | 218 | struct intel_engine_cs *engine); |
a3aabe86 CW |
219 | static void execlists_init_reg_state(u32 *reg_state, |
220 | struct i915_gem_context *ctx, | |
221 | struct intel_engine_cs *engine, | |
222 | struct intel_ring *ring); | |
7ba717cf | 223 | |
73e4d07f OM |
224 | /** |
225 | * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists | |
14bb2c11 | 226 | * @dev_priv: i915 device private |
73e4d07f OM |
227 | * @enable_execlists: value of i915.enable_execlists module parameter. |
228 | * | |
229 | * Only certain platforms support Execlists (the prerequisites being | |
27401d12 | 230 | * support for Logical Ring Contexts and Aliasing PPGTT or better). |
73e4d07f OM |
231 | * |
232 | * Return: 1 if Execlists is supported and has to be enabled. | |
233 | */ | |
c033666a | 234 | int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv, int enable_execlists) |
127f1003 | 235 | { |
a0bd6c31 ZL |
236 | /* On platforms with execlist available, vGPU will only |
237 | * support execlist mode, no ring buffer mode. | |
238 | */ | |
c033666a | 239 | if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && intel_vgpu_active(dev_priv)) |
a0bd6c31 ZL |
240 | return 1; |
241 | ||
c033666a | 242 | if (INTEL_GEN(dev_priv) >= 9) |
70ee45e1 DL |
243 | return 1; |
244 | ||
127f1003 OM |
245 | if (enable_execlists == 0) |
246 | return 0; | |
247 | ||
5a21b665 DV |
248 | if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && |
249 | USES_PPGTT(dev_priv) && | |
250 | i915.use_mmio_flip >= 0) | |
127f1003 OM |
251 | return 1; |
252 | ||
253 | return 0; | |
254 | } | |
ede7d42b | 255 | |
73e4d07f | 256 | /** |
ca82580c TU |
257 | * intel_lr_context_descriptor_update() - calculate & cache the descriptor |
258 | * descriptor for a pinned context | |
ca82580c | 259 | * @ctx: Context to work on |
9021ad03 | 260 | * @engine: Engine the descriptor will be used with |
73e4d07f | 261 | * |
ca82580c TU |
262 | * The context descriptor encodes various attributes of a context, |
263 | * including its GTT address and some flags. Because it's fairly | |
264 | * expensive to calculate, we'll just do it once and cache the result, | |
265 | * which remains valid until the context is unpinned. | |
266 | * | |
6e5248b5 DV |
267 | * This is what a descriptor looks like, from LSB to MSB:: |
268 | * | |
2355cf08 | 269 | * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template) |
6e5248b5 DV |
270 | * bits 12-31: LRCA, GTT address of (the HWSP of) this context |
271 | * bits 32-52: ctx ID, a globally unique tag | |
272 | * bits 53-54: mbz, reserved for use by hardware | |
273 | * bits 55-63: group ID, currently unused and set to 0 | |
73e4d07f | 274 | */ |
ca82580c | 275 | static void |
e2efd130 | 276 | intel_lr_context_descriptor_update(struct i915_gem_context *ctx, |
0bc40be8 | 277 | struct intel_engine_cs *engine) |
84b790f8 | 278 | { |
9021ad03 | 279 | struct intel_context *ce = &ctx->engine[engine->id]; |
7069b144 | 280 | u64 desc; |
84b790f8 | 281 | |
7069b144 | 282 | BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH)); |
84b790f8 | 283 | |
2355cf08 | 284 | desc = ctx->desc_template; /* bits 0-11 */ |
bde13ebd | 285 | desc |= i915_ggtt_offset(ce->state) + LRC_PPHWSP_PN * PAGE_SIZE; |
9021ad03 | 286 | /* bits 12-31 */ |
7069b144 | 287 | desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */ |
5af05fef | 288 | |
9021ad03 | 289 | ce->lrc_desc = desc; |
5af05fef MT |
290 | } |
291 | ||
e2efd130 | 292 | uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx, |
0bc40be8 | 293 | struct intel_engine_cs *engine) |
84b790f8 | 294 | { |
0bc40be8 | 295 | return ctx->engine[engine->id].lrc_desc; |
ca82580c | 296 | } |
203a571b | 297 | |
bbd6c47e CW |
298 | static inline void |
299 | execlists_context_status_change(struct drm_i915_gem_request *rq, | |
300 | unsigned long status) | |
84b790f8 | 301 | { |
bbd6c47e CW |
302 | /* |
303 | * Only used when GVT-g is enabled now. When GVT-g is disabled, | |
304 | * The compiler should eliminate this function as dead-code. | |
305 | */ | |
306 | if (!IS_ENABLED(CONFIG_DRM_I915_GVT)) | |
307 | return; | |
6daccb0b | 308 | |
bbd6c47e | 309 | atomic_notifier_call_chain(&rq->ctx->status_notifier, status, rq); |
84b790f8 BW |
310 | } |
311 | ||
c6a2ac71 TU |
312 | static void |
313 | execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state) | |
314 | { | |
315 | ASSIGN_CTX_PDP(ppgtt, reg_state, 3); | |
316 | ASSIGN_CTX_PDP(ppgtt, reg_state, 2); | |
317 | ASSIGN_CTX_PDP(ppgtt, reg_state, 1); | |
318 | ASSIGN_CTX_PDP(ppgtt, reg_state, 0); | |
319 | } | |
320 | ||
70c2a24d | 321 | static u64 execlists_update_context(struct drm_i915_gem_request *rq) |
ae1250b9 | 322 | { |
70c2a24d | 323 | struct intel_context *ce = &rq->ctx->engine[rq->engine->id]; |
04da811b ZW |
324 | struct i915_hw_ppgtt *ppgtt = |
325 | rq->ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt; | |
70c2a24d | 326 | u32 *reg_state = ce->lrc_reg_state; |
ae1250b9 | 327 | |
caddfe71 | 328 | reg_state[CTX_RING_TAIL+1] = rq->tail; |
ae1250b9 | 329 | |
c6a2ac71 TU |
330 | /* True 32b PPGTT with dynamic page allocation: update PDP |
331 | * registers and point the unallocated PDPs to scratch page. | |
332 | * PML4 is allocated during ppgtt init, so this is not needed | |
333 | * in 48-bit mode. | |
334 | */ | |
335 | if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) | |
336 | execlists_update_context_pdps(ppgtt, reg_state); | |
70c2a24d CW |
337 | |
338 | return ce->lrc_desc; | |
ae1250b9 OM |
339 | } |
340 | ||
70c2a24d | 341 | static void execlists_submit_ports(struct intel_engine_cs *engine) |
bbd6c47e | 342 | { |
70c2a24d CW |
343 | struct drm_i915_private *dev_priv = engine->i915; |
344 | struct execlist_port *port = engine->execlist_port; | |
bbd6c47e CW |
345 | u32 __iomem *elsp = |
346 | dev_priv->regs + i915_mmio_reg_offset(RING_ELSP(engine)); | |
347 | u64 desc[2]; | |
348 | ||
c816e605 | 349 | GEM_BUG_ON(port[0].count > 1); |
70c2a24d CW |
350 | if (!port[0].count) |
351 | execlists_context_status_change(port[0].request, | |
352 | INTEL_CONTEXT_SCHEDULE_IN); | |
353 | desc[0] = execlists_update_context(port[0].request); | |
2ffe80aa | 354 | GEM_BUG_ONLY(port[0].context_id = upper_32_bits(desc[0])); |
816ee798 | 355 | port[0].count++; |
70c2a24d CW |
356 | |
357 | if (port[1].request) { | |
358 | GEM_BUG_ON(port[1].count); | |
359 | execlists_context_status_change(port[1].request, | |
360 | INTEL_CONTEXT_SCHEDULE_IN); | |
361 | desc[1] = execlists_update_context(port[1].request); | |
2ffe80aa | 362 | GEM_BUG_ONLY(port[1].context_id = upper_32_bits(desc[1])); |
70c2a24d | 363 | port[1].count = 1; |
bbd6c47e CW |
364 | } else { |
365 | desc[1] = 0; | |
366 | } | |
70c2a24d | 367 | GEM_BUG_ON(desc[0] == desc[1]); |
bbd6c47e CW |
368 | |
369 | /* You must always write both descriptors in the order below. */ | |
370 | writel(upper_32_bits(desc[1]), elsp); | |
371 | writel(lower_32_bits(desc[1]), elsp); | |
372 | ||
373 | writel(upper_32_bits(desc[0]), elsp); | |
374 | /* The context is automatically loaded after the following */ | |
375 | writel(lower_32_bits(desc[0]), elsp); | |
376 | } | |
377 | ||
70c2a24d | 378 | static bool ctx_single_port_submission(const struct i915_gem_context *ctx) |
84b790f8 | 379 | { |
70c2a24d | 380 | return (IS_ENABLED(CONFIG_DRM_I915_GVT) && |
6095868a | 381 | i915_gem_context_force_single_submission(ctx)); |
70c2a24d | 382 | } |
84b790f8 | 383 | |
70c2a24d CW |
384 | static bool can_merge_ctx(const struct i915_gem_context *prev, |
385 | const struct i915_gem_context *next) | |
386 | { | |
387 | if (prev != next) | |
388 | return false; | |
26720ab9 | 389 | |
70c2a24d CW |
390 | if (ctx_single_port_submission(prev)) |
391 | return false; | |
26720ab9 | 392 | |
70c2a24d | 393 | return true; |
84b790f8 BW |
394 | } |
395 | ||
70c2a24d | 396 | static void execlists_dequeue(struct intel_engine_cs *engine) |
acdd884a | 397 | { |
20311bd3 | 398 | struct drm_i915_gem_request *last; |
70c2a24d | 399 | struct execlist_port *port = engine->execlist_port; |
d55ac5bf | 400 | unsigned long flags; |
20311bd3 | 401 | struct rb_node *rb; |
70c2a24d CW |
402 | bool submit = false; |
403 | ||
404 | last = port->request; | |
405 | if (last) | |
406 | /* WaIdleLiteRestore:bdw,skl | |
407 | * Apply the wa NOOPs to prevent ring:HEAD == req:TAIL | |
9b81d556 | 408 | * as we resubmit the request. See gen8_emit_breadcrumb() |
70c2a24d CW |
409 | * for where we prepare the padding after the end of the |
410 | * request. | |
411 | */ | |
412 | last->tail = last->wa_tail; | |
e981e7b1 | 413 | |
70c2a24d | 414 | GEM_BUG_ON(port[1].request); |
acdd884a | 415 | |
70c2a24d CW |
416 | /* Hardware submission is through 2 ports. Conceptually each port |
417 | * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is | |
418 | * static for a context, and unique to each, so we only execute | |
419 | * requests belonging to a single context from each ring. RING_HEAD | |
420 | * is maintained by the CS in the context image, it marks the place | |
421 | * where it got up to last time, and through RING_TAIL we tell the CS | |
422 | * where we want to execute up to this time. | |
423 | * | |
424 | * In this list the requests are in order of execution. Consecutive | |
425 | * requests from the same context are adjacent in the ringbuffer. We | |
426 | * can combine these requests into a single RING_TAIL update: | |
427 | * | |
428 | * RING_HEAD...req1...req2 | |
429 | * ^- RING_TAIL | |
430 | * since to execute req2 the CS must first execute req1. | |
431 | * | |
432 | * Our goal then is to point each port to the end of a consecutive | |
433 | * sequence of requests as being the most optimal (fewest wake ups | |
434 | * and context switches) submission. | |
779949f4 | 435 | */ |
acdd884a | 436 | |
d55ac5bf | 437 | spin_lock_irqsave(&engine->timeline->lock, flags); |
20311bd3 CW |
438 | rb = engine->execlist_first; |
439 | while (rb) { | |
440 | struct drm_i915_gem_request *cursor = | |
441 | rb_entry(rb, typeof(*cursor), priotree.node); | |
442 | ||
70c2a24d CW |
443 | /* Can we combine this request with the current port? It has to |
444 | * be the same context/ringbuffer and not have any exceptions | |
445 | * (e.g. GVT saying never to combine contexts). | |
c6a2ac71 | 446 | * |
70c2a24d CW |
447 | * If we can combine the requests, we can execute both by |
448 | * updating the RING_TAIL to point to the end of the second | |
449 | * request, and so we never need to tell the hardware about | |
450 | * the first. | |
53292cdb | 451 | */ |
70c2a24d CW |
452 | if (last && !can_merge_ctx(cursor->ctx, last->ctx)) { |
453 | /* If we are on the second port and cannot combine | |
454 | * this request with the last, then we are done. | |
455 | */ | |
456 | if (port != engine->execlist_port) | |
457 | break; | |
458 | ||
459 | /* If GVT overrides us we only ever submit port[0], | |
460 | * leaving port[1] empty. Note that we also have | |
461 | * to be careful that we don't queue the same | |
462 | * context (even though a different request) to | |
463 | * the second port. | |
464 | */ | |
d7ab992c MH |
465 | if (ctx_single_port_submission(last->ctx) || |
466 | ctx_single_port_submission(cursor->ctx)) | |
70c2a24d CW |
467 | break; |
468 | ||
469 | GEM_BUG_ON(last->ctx == cursor->ctx); | |
470 | ||
471 | i915_gem_request_assign(&port->request, last); | |
472 | port++; | |
473 | } | |
d55ac5bf | 474 | |
20311bd3 CW |
475 | rb = rb_next(rb); |
476 | rb_erase(&cursor->priotree.node, &engine->execlist_queue); | |
477 | RB_CLEAR_NODE(&cursor->priotree.node); | |
478 | cursor->priotree.priority = INT_MAX; | |
479 | ||
d55ac5bf | 480 | __i915_gem_request_submit(cursor); |
70c2a24d CW |
481 | last = cursor; |
482 | submit = true; | |
483 | } | |
484 | if (submit) { | |
70c2a24d | 485 | i915_gem_request_assign(&port->request, last); |
20311bd3 | 486 | engine->execlist_first = rb; |
53292cdb | 487 | } |
d55ac5bf | 488 | spin_unlock_irqrestore(&engine->timeline->lock, flags); |
53292cdb | 489 | |
70c2a24d CW |
490 | if (submit) |
491 | execlists_submit_ports(engine); | |
acdd884a MT |
492 | } |
493 | ||
70c2a24d | 494 | static bool execlists_elsp_idle(struct intel_engine_cs *engine) |
e981e7b1 | 495 | { |
70c2a24d | 496 | return !engine->execlist_port[0].request; |
e981e7b1 TD |
497 | } |
498 | ||
0cb5670b ID |
499 | /** |
500 | * intel_execlists_idle() - Determine if all engine submission ports are idle | |
501 | * @dev_priv: i915 device private | |
502 | * | |
503 | * Return true if there are no requests pending on any of the submission ports | |
504 | * of any engines. | |
505 | */ | |
506 | bool intel_execlists_idle(struct drm_i915_private *dev_priv) | |
507 | { | |
508 | struct intel_engine_cs *engine; | |
509 | enum intel_engine_id id; | |
510 | ||
511 | if (!i915.enable_execlists) | |
512 | return true; | |
513 | ||
453cfe21 CW |
514 | for_each_engine(engine, dev_priv, id) { |
515 | /* Interrupt/tasklet pending? */ | |
516 | if (test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) | |
517 | return false; | |
518 | ||
519 | /* Both ports drained, no more ELSP submission? */ | |
0cb5670b ID |
520 | if (!execlists_elsp_idle(engine)) |
521 | return false; | |
453cfe21 | 522 | } |
0cb5670b ID |
523 | |
524 | return true; | |
525 | } | |
526 | ||
816ee798 | 527 | static bool execlists_elsp_ready(const struct intel_engine_cs *engine) |
91a41032 | 528 | { |
816ee798 | 529 | const struct execlist_port *port = engine->execlist_port; |
91a41032 | 530 | |
816ee798 | 531 | return port[0].count + port[1].count < 2; |
91a41032 BW |
532 | } |
533 | ||
6e5248b5 | 534 | /* |
73e4d07f OM |
535 | * Check the unread Context Status Buffers and manage the submission of new |
536 | * contexts to the ELSP accordingly. | |
537 | */ | |
27af5eea | 538 | static void intel_lrc_irq_handler(unsigned long data) |
e981e7b1 | 539 | { |
27af5eea | 540 | struct intel_engine_cs *engine = (struct intel_engine_cs *)data; |
70c2a24d | 541 | struct execlist_port *port = engine->execlist_port; |
c033666a | 542 | struct drm_i915_private *dev_priv = engine->i915; |
c6a2ac71 | 543 | |
3756685a | 544 | intel_uncore_forcewake_get(dev_priv, engine->fw_domains); |
c6a2ac71 | 545 | |
f747026c | 546 | while (test_and_clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) { |
70c2a24d CW |
547 | u32 __iomem *csb_mmio = |
548 | dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)); | |
549 | u32 __iomem *buf = | |
550 | dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)); | |
551 | unsigned int csb, head, tail; | |
552 | ||
553 | csb = readl(csb_mmio); | |
554 | head = GEN8_CSB_READ_PTR(csb); | |
555 | tail = GEN8_CSB_WRITE_PTR(csb); | |
a37951ac CW |
556 | if (head == tail) |
557 | break; | |
558 | ||
70c2a24d CW |
559 | if (tail < head) |
560 | tail += GEN8_CSB_ENTRIES; | |
a37951ac | 561 | do { |
70c2a24d CW |
562 | unsigned int idx = ++head % GEN8_CSB_ENTRIES; |
563 | unsigned int status = readl(buf + 2 * idx); | |
564 | ||
2ffe80aa CW |
565 | /* We are flying near dragons again. |
566 | * | |
567 | * We hold a reference to the request in execlist_port[] | |
568 | * but no more than that. We are operating in softirq | |
569 | * context and so cannot hold any mutex or sleep. That | |
570 | * prevents us stopping the requests we are processing | |
571 | * in port[] from being retired simultaneously (the | |
572 | * breadcrumb will be complete before we see the | |
573 | * context-switch). As we only hold the reference to the | |
574 | * request, any pointer chasing underneath the request | |
575 | * is subject to a potential use-after-free. Thus we | |
576 | * store all of the bookkeeping within port[] as | |
577 | * required, and avoid using unguarded pointers beneath | |
578 | * request itself. The same applies to the atomic | |
579 | * status notifier. | |
580 | */ | |
581 | ||
70c2a24d CW |
582 | if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK)) |
583 | continue; | |
584 | ||
86aa7e76 | 585 | /* Check the context/desc id for this event matches */ |
2ffe80aa CW |
586 | GEM_BUG_ONLY_ON(readl(buf + 2 * idx + 1) != |
587 | port[0].context_id); | |
86aa7e76 | 588 | |
70c2a24d CW |
589 | GEM_BUG_ON(port[0].count == 0); |
590 | if (--port[0].count == 0) { | |
591 | GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED); | |
592 | execlists_context_status_change(port[0].request, | |
593 | INTEL_CONTEXT_SCHEDULE_OUT); | |
594 | ||
595 | i915_gem_request_put(port[0].request); | |
596 | port[0] = port[1]; | |
597 | memset(&port[1], 0, sizeof(port[1])); | |
70c2a24d | 598 | } |
26720ab9 | 599 | |
70c2a24d CW |
600 | GEM_BUG_ON(port[0].count == 0 && |
601 | !(status & GEN8_CTX_STATUS_ACTIVE_IDLE)); | |
a37951ac | 602 | } while (head < tail); |
e1fee72c | 603 | |
70c2a24d CW |
604 | writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, |
605 | GEN8_CSB_WRITE_PTR(csb) << 8), | |
606 | csb_mmio); | |
e981e7b1 TD |
607 | } |
608 | ||
70c2a24d CW |
609 | if (execlists_elsp_ready(engine)) |
610 | execlists_dequeue(engine); | |
c6a2ac71 | 611 | |
70c2a24d | 612 | intel_uncore_forcewake_put(dev_priv, engine->fw_domains); |
e981e7b1 TD |
613 | } |
614 | ||
20311bd3 CW |
615 | static bool insert_request(struct i915_priotree *pt, struct rb_root *root) |
616 | { | |
617 | struct rb_node **p, *rb; | |
618 | bool first = true; | |
619 | ||
620 | /* most positive priority is scheduled first, equal priorities fifo */ | |
621 | rb = NULL; | |
622 | p = &root->rb_node; | |
623 | while (*p) { | |
624 | struct i915_priotree *pos; | |
625 | ||
626 | rb = *p; | |
627 | pos = rb_entry(rb, typeof(*pos), node); | |
628 | if (pt->priority > pos->priority) { | |
629 | p = &rb->rb_left; | |
630 | } else { | |
631 | p = &rb->rb_right; | |
632 | first = false; | |
633 | } | |
634 | } | |
635 | rb_link_node(&pt->node, rb, p); | |
636 | rb_insert_color(&pt->node, root); | |
637 | ||
638 | return first; | |
639 | } | |
640 | ||
f4ea6bdd | 641 | static void execlists_submit_request(struct drm_i915_gem_request *request) |
acdd884a | 642 | { |
4a570db5 | 643 | struct intel_engine_cs *engine = request->engine; |
5590af3e | 644 | unsigned long flags; |
acdd884a | 645 | |
663f71e7 CW |
646 | /* Will be called from irq-context when using foreign fences. */ |
647 | spin_lock_irqsave(&engine->timeline->lock, flags); | |
acdd884a | 648 | |
3833281a | 649 | if (insert_request(&request->priotree, &engine->execlist_queue)) { |
20311bd3 | 650 | engine->execlist_first = &request->priotree.node; |
48ea2554 | 651 | if (execlists_elsp_ready(engine)) |
3833281a CW |
652 | tasklet_hi_schedule(&engine->irq_tasklet); |
653 | } | |
acdd884a | 654 | |
663f71e7 | 655 | spin_unlock_irqrestore(&engine->timeline->lock, flags); |
acdd884a MT |
656 | } |
657 | ||
20311bd3 CW |
658 | static struct intel_engine_cs * |
659 | pt_lock_engine(struct i915_priotree *pt, struct intel_engine_cs *locked) | |
660 | { | |
661 | struct intel_engine_cs *engine; | |
662 | ||
663 | engine = container_of(pt, | |
664 | struct drm_i915_gem_request, | |
665 | priotree)->engine; | |
666 | if (engine != locked) { | |
667 | if (locked) | |
668 | spin_unlock_irq(&locked->timeline->lock); | |
669 | spin_lock_irq(&engine->timeline->lock); | |
670 | } | |
671 | ||
672 | return engine; | |
673 | } | |
674 | ||
675 | static void execlists_schedule(struct drm_i915_gem_request *request, int prio) | |
676 | { | |
677 | struct intel_engine_cs *engine = NULL; | |
678 | struct i915_dependency *dep, *p; | |
679 | struct i915_dependency stack; | |
680 | LIST_HEAD(dfs); | |
681 | ||
682 | if (prio <= READ_ONCE(request->priotree.priority)) | |
683 | return; | |
684 | ||
70cd1476 CW |
685 | /* Need BKL in order to use the temporary link inside i915_dependency */ |
686 | lockdep_assert_held(&request->i915->drm.struct_mutex); | |
20311bd3 CW |
687 | |
688 | stack.signaler = &request->priotree; | |
689 | list_add(&stack.dfs_link, &dfs); | |
690 | ||
691 | /* Recursively bump all dependent priorities to match the new request. | |
692 | * | |
693 | * A naive approach would be to use recursion: | |
694 | * static void update_priorities(struct i915_priotree *pt, prio) { | |
695 | * list_for_each_entry(dep, &pt->signalers_list, signal_link) | |
696 | * update_priorities(dep->signal, prio) | |
697 | * insert_request(pt); | |
698 | * } | |
699 | * but that may have unlimited recursion depth and so runs a very | |
700 | * real risk of overunning the kernel stack. Instead, we build | |
701 | * a flat list of all dependencies starting with the current request. | |
702 | * As we walk the list of dependencies, we add all of its dependencies | |
703 | * to the end of the list (this may include an already visited | |
704 | * request) and continue to walk onwards onto the new dependencies. The | |
705 | * end result is a topological list of requests in reverse order, the | |
706 | * last element in the list is the request we must execute first. | |
707 | */ | |
708 | list_for_each_entry_safe(dep, p, &dfs, dfs_link) { | |
709 | struct i915_priotree *pt = dep->signaler; | |
710 | ||
711 | list_for_each_entry(p, &pt->signalers_list, signal_link) | |
712 | if (prio > READ_ONCE(p->signaler->priority)) | |
713 | list_move_tail(&p->dfs_link, &dfs); | |
714 | ||
0798cff4 | 715 | list_safe_reset_next(dep, p, dfs_link); |
20311bd3 CW |
716 | if (!RB_EMPTY_NODE(&pt->node)) |
717 | continue; | |
718 | ||
719 | engine = pt_lock_engine(pt, engine); | |
720 | ||
721 | /* If it is not already in the rbtree, we can update the | |
722 | * priority inplace and skip over it (and its dependencies) | |
723 | * if it is referenced *again* as we descend the dfs. | |
724 | */ | |
725 | if (prio > pt->priority && RB_EMPTY_NODE(&pt->node)) { | |
726 | pt->priority = prio; | |
727 | list_del_init(&dep->dfs_link); | |
728 | } | |
729 | } | |
730 | ||
731 | /* Fifo and depth-first replacement ensure our deps execute before us */ | |
732 | list_for_each_entry_safe_reverse(dep, p, &dfs, dfs_link) { | |
733 | struct i915_priotree *pt = dep->signaler; | |
734 | ||
735 | INIT_LIST_HEAD(&dep->dfs_link); | |
736 | ||
737 | engine = pt_lock_engine(pt, engine); | |
738 | ||
739 | if (prio <= pt->priority) | |
740 | continue; | |
741 | ||
742 | GEM_BUG_ON(RB_EMPTY_NODE(&pt->node)); | |
743 | ||
744 | pt->priority = prio; | |
745 | rb_erase(&pt->node, &engine->execlist_queue); | |
746 | if (insert_request(pt, &engine->execlist_queue)) | |
747 | engine->execlist_first = &pt->node; | |
748 | } | |
749 | ||
750 | if (engine) | |
751 | spin_unlock_irq(&engine->timeline->lock); | |
752 | ||
753 | /* XXX Do we need to preempt to make room for us and our deps? */ | |
754 | } | |
755 | ||
e8a9c58f CW |
756 | static int execlists_context_pin(struct intel_engine_cs *engine, |
757 | struct i915_gem_context *ctx) | |
dcb4c12a | 758 | { |
9021ad03 | 759 | struct intel_context *ce = &ctx->engine[engine->id]; |
2947e408 | 760 | unsigned int flags; |
7d774cac | 761 | void *vaddr; |
ca82580c | 762 | int ret; |
dcb4c12a | 763 | |
91c8a326 | 764 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
ca82580c | 765 | |
9021ad03 | 766 | if (ce->pin_count++) |
24f1d3cc CW |
767 | return 0; |
768 | ||
e8a9c58f CW |
769 | if (!ce->state) { |
770 | ret = execlists_context_deferred_alloc(ctx, engine); | |
771 | if (ret) | |
772 | goto err; | |
773 | } | |
56f6e0a7 | 774 | GEM_BUG_ON(!ce->state); |
e8a9c58f | 775 | |
feef2a7c DCS |
776 | flags = PIN_GLOBAL; |
777 | if (ctx->ggtt_offset_bias) | |
778 | flags |= PIN_OFFSET_BIAS | ctx->ggtt_offset_bias; | |
984ff29f | 779 | if (i915_gem_context_is_kernel(ctx)) |
2947e408 CW |
780 | flags |= PIN_HIGH; |
781 | ||
782 | ret = i915_vma_pin(ce->state, 0, GEN8_LR_CONTEXT_ALIGN, flags); | |
e84fe803 | 783 | if (ret) |
24f1d3cc | 784 | goto err; |
7ba717cf | 785 | |
bf3783e5 | 786 | vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB); |
7d774cac TU |
787 | if (IS_ERR(vaddr)) { |
788 | ret = PTR_ERR(vaddr); | |
bf3783e5 | 789 | goto unpin_vma; |
82352e90 TU |
790 | } |
791 | ||
d3ef1af6 | 792 | ret = intel_ring_pin(ce->ring, ctx->ggtt_offset_bias); |
e84fe803 | 793 | if (ret) |
7d774cac | 794 | goto unpin_map; |
d1675198 | 795 | |
0bc40be8 | 796 | intel_lr_context_descriptor_update(ctx, engine); |
9021ad03 | 797 | |
a3aabe86 CW |
798 | ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; |
799 | ce->lrc_reg_state[CTX_RING_BUFFER_START+1] = | |
bde13ebd | 800 | i915_ggtt_offset(ce->ring->vma); |
a3aabe86 | 801 | |
a4f5ea64 | 802 | ce->state->obj->mm.dirty = true; |
e93c28f3 | 803 | |
9a6feaf0 | 804 | i915_gem_context_get(ctx); |
24f1d3cc | 805 | return 0; |
7ba717cf | 806 | |
7d774cac | 807 | unpin_map: |
bf3783e5 CW |
808 | i915_gem_object_unpin_map(ce->state->obj); |
809 | unpin_vma: | |
810 | __i915_vma_unpin(ce->state); | |
24f1d3cc | 811 | err: |
9021ad03 | 812 | ce->pin_count = 0; |
e84fe803 NH |
813 | return ret; |
814 | } | |
815 | ||
e8a9c58f CW |
816 | static void execlists_context_unpin(struct intel_engine_cs *engine, |
817 | struct i915_gem_context *ctx) | |
e84fe803 | 818 | { |
9021ad03 | 819 | struct intel_context *ce = &ctx->engine[engine->id]; |
e84fe803 | 820 | |
91c8a326 | 821 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
9021ad03 | 822 | GEM_BUG_ON(ce->pin_count == 0); |
321fe304 | 823 | |
9021ad03 | 824 | if (--ce->pin_count) |
24f1d3cc | 825 | return; |
e84fe803 | 826 | |
aad29fbb | 827 | intel_ring_unpin(ce->ring); |
dcb4c12a | 828 | |
bf3783e5 CW |
829 | i915_gem_object_unpin_map(ce->state->obj); |
830 | i915_vma_unpin(ce->state); | |
321fe304 | 831 | |
9a6feaf0 | 832 | i915_gem_context_put(ctx); |
dcb4c12a OM |
833 | } |
834 | ||
f73e7399 | 835 | static int execlists_request_alloc(struct drm_i915_gem_request *request) |
ef11c01d CW |
836 | { |
837 | struct intel_engine_cs *engine = request->engine; | |
838 | struct intel_context *ce = &request->ctx->engine[engine->id]; | |
839 | int ret; | |
840 | ||
e8a9c58f CW |
841 | GEM_BUG_ON(!ce->pin_count); |
842 | ||
ef11c01d CW |
843 | /* Flush enough space to reduce the likelihood of waiting after |
844 | * we start building the request - in which case we will just | |
845 | * have to repeat work. | |
846 | */ | |
847 | request->reserved_space += EXECLISTS_REQUEST_SIZE; | |
848 | ||
e8a9c58f | 849 | GEM_BUG_ON(!ce->ring); |
ef11c01d CW |
850 | request->ring = ce->ring; |
851 | ||
ef11c01d CW |
852 | if (i915.enable_guc_submission) { |
853 | /* | |
854 | * Check that the GuC has space for the request before | |
855 | * going any further, as the i915_add_request() call | |
856 | * later on mustn't fail ... | |
857 | */ | |
858 | ret = i915_guc_wq_reserve(request); | |
859 | if (ret) | |
e8a9c58f | 860 | goto err; |
ef11c01d CW |
861 | } |
862 | ||
863 | ret = intel_ring_begin(request, 0); | |
864 | if (ret) | |
865 | goto err_unreserve; | |
866 | ||
867 | if (!ce->initialised) { | |
868 | ret = engine->init_context(request); | |
869 | if (ret) | |
870 | goto err_unreserve; | |
871 | ||
872 | ce->initialised = true; | |
873 | } | |
874 | ||
875 | /* Note that after this point, we have committed to using | |
876 | * this request as it is being used to both track the | |
877 | * state of engine initialisation and liveness of the | |
878 | * golden renderstate above. Think twice before you try | |
879 | * to cancel/unwind this request now. | |
880 | */ | |
881 | ||
882 | request->reserved_space -= EXECLISTS_REQUEST_SIZE; | |
883 | return 0; | |
884 | ||
885 | err_unreserve: | |
886 | if (i915.enable_guc_submission) | |
887 | i915_guc_wq_unreserve(request); | |
e8a9c58f | 888 | err: |
ef11c01d CW |
889 | return ret; |
890 | } | |
891 | ||
e2be4faf | 892 | static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req) |
771b9a53 MT |
893 | { |
894 | int ret, i; | |
7e37f889 | 895 | struct intel_ring *ring = req->ring; |
c033666a | 896 | struct i915_workarounds *w = &req->i915->workarounds; |
771b9a53 | 897 | |
cd7feaaa | 898 | if (w->count == 0) |
771b9a53 MT |
899 | return 0; |
900 | ||
7c9cf4e3 | 901 | ret = req->engine->emit_flush(req, EMIT_BARRIER); |
771b9a53 MT |
902 | if (ret) |
903 | return ret; | |
904 | ||
987046ad | 905 | ret = intel_ring_begin(req, w->count * 2 + 2); |
771b9a53 MT |
906 | if (ret) |
907 | return ret; | |
908 | ||
1dae2dfb | 909 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count)); |
771b9a53 | 910 | for (i = 0; i < w->count; i++) { |
1dae2dfb CW |
911 | intel_ring_emit_reg(ring, w->reg[i].addr); |
912 | intel_ring_emit(ring, w->reg[i].value); | |
771b9a53 | 913 | } |
1dae2dfb | 914 | intel_ring_emit(ring, MI_NOOP); |
771b9a53 | 915 | |
1dae2dfb | 916 | intel_ring_advance(ring); |
771b9a53 | 917 | |
7c9cf4e3 | 918 | ret = req->engine->emit_flush(req, EMIT_BARRIER); |
771b9a53 MT |
919 | if (ret) |
920 | return ret; | |
921 | ||
922 | return 0; | |
923 | } | |
924 | ||
83b8a982 | 925 | #define wa_ctx_emit(batch, index, cmd) \ |
17ee950d | 926 | do { \ |
83b8a982 AS |
927 | int __index = (index)++; \ |
928 | if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \ | |
17ee950d AS |
929 | return -ENOSPC; \ |
930 | } \ | |
83b8a982 | 931 | batch[__index] = (cmd); \ |
17ee950d AS |
932 | } while (0) |
933 | ||
8f40db77 | 934 | #define wa_ctx_emit_reg(batch, index, reg) \ |
f0f59a00 | 935 | wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg)) |
9e000847 AS |
936 | |
937 | /* | |
938 | * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after | |
939 | * PIPE_CONTROL instruction. This is required for the flush to happen correctly | |
940 | * but there is a slight complication as this is applied in WA batch where the | |
941 | * values are only initialized once so we cannot take register value at the | |
942 | * beginning and reuse it further; hence we save its value to memory, upload a | |
943 | * constant value with bit21 set and then we restore it back with the saved value. | |
944 | * To simplify the WA, a constant value is formed by using the default value | |
945 | * of this register. This shouldn't be a problem because we are only modifying | |
946 | * it for a short period and this batch in non-premptible. We can ofcourse | |
947 | * use additional instructions that read the actual value of the register | |
948 | * at that time and set our bit of interest but it makes the WA complicated. | |
949 | * | |
950 | * This WA is also required for Gen9 so extracting as a function avoids | |
951 | * code duplication. | |
952 | */ | |
0bc40be8 | 953 | static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, |
6e5248b5 | 954 | uint32_t *batch, |
9e000847 AS |
955 | uint32_t index) |
956 | { | |
957 | uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES); | |
958 | ||
f1afe24f | 959 | wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 | |
83b8a982 | 960 | MI_SRM_LRM_GLOBAL_GTT)); |
8f40db77 | 961 | wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); |
bde13ebd | 962 | wa_ctx_emit(batch, index, i915_ggtt_offset(engine->scratch) + 256); |
83b8a982 AS |
963 | wa_ctx_emit(batch, index, 0); |
964 | ||
965 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); | |
8f40db77 | 966 | wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); |
83b8a982 AS |
967 | wa_ctx_emit(batch, index, l3sqc4_flush); |
968 | ||
969 | wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); | |
970 | wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL | | |
971 | PIPE_CONTROL_DC_FLUSH_ENABLE)); | |
972 | wa_ctx_emit(batch, index, 0); | |
973 | wa_ctx_emit(batch, index, 0); | |
974 | wa_ctx_emit(batch, index, 0); | |
975 | wa_ctx_emit(batch, index, 0); | |
976 | ||
f1afe24f | 977 | wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 | |
83b8a982 | 978 | MI_SRM_LRM_GLOBAL_GTT)); |
8f40db77 | 979 | wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); |
bde13ebd | 980 | wa_ctx_emit(batch, index, i915_ggtt_offset(engine->scratch) + 256); |
83b8a982 | 981 | wa_ctx_emit(batch, index, 0); |
9e000847 AS |
982 | |
983 | return index; | |
984 | } | |
985 | ||
17ee950d AS |
986 | static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx, |
987 | uint32_t offset, | |
988 | uint32_t start_alignment) | |
989 | { | |
990 | return wa_ctx->offset = ALIGN(offset, start_alignment); | |
991 | } | |
992 | ||
993 | static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx, | |
994 | uint32_t offset, | |
995 | uint32_t size_alignment) | |
996 | { | |
997 | wa_ctx->size = offset - wa_ctx->offset; | |
998 | ||
999 | WARN(wa_ctx->size % size_alignment, | |
1000 | "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n", | |
1001 | wa_ctx->size, size_alignment); | |
1002 | return 0; | |
1003 | } | |
1004 | ||
6e5248b5 DV |
1005 | /* |
1006 | * Typically we only have one indirect_ctx and per_ctx batch buffer which are | |
1007 | * initialized at the beginning and shared across all contexts but this field | |
1008 | * helps us to have multiple batches at different offsets and select them based | |
1009 | * on a criteria. At the moment this batch always start at the beginning of the page | |
1010 | * and at this point we don't have multiple wa_ctx batch buffers. | |
4d78c8dc | 1011 | * |
6e5248b5 DV |
1012 | * The number of WA applied are not known at the beginning; we use this field |
1013 | * to return the no of DWORDS written. | |
17ee950d | 1014 | * |
6e5248b5 DV |
1015 | * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END |
1016 | * so it adds NOOPs as padding to make it cacheline aligned. | |
1017 | * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together | |
1018 | * makes a complete batch buffer. | |
17ee950d | 1019 | */ |
0bc40be8 | 1020 | static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine, |
17ee950d | 1021 | struct i915_wa_ctx_bb *wa_ctx, |
6e5248b5 | 1022 | uint32_t *batch, |
17ee950d AS |
1023 | uint32_t *offset) |
1024 | { | |
0160f055 | 1025 | uint32_t scratch_addr; |
17ee950d AS |
1026 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
1027 | ||
7ad00d1a | 1028 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
83b8a982 | 1029 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
17ee950d | 1030 | |
c82435bb | 1031 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */ |
c033666a | 1032 | if (IS_BROADWELL(engine->i915)) { |
0bc40be8 | 1033 | int rc = gen8_emit_flush_coherentl3_wa(engine, batch, index); |
604ef734 AH |
1034 | if (rc < 0) |
1035 | return rc; | |
1036 | index = rc; | |
c82435bb AS |
1037 | } |
1038 | ||
0160f055 AS |
1039 | /* WaClearSlmSpaceAtContextSwitch:bdw,chv */ |
1040 | /* Actual scratch location is at 128 bytes offset */ | |
bde13ebd | 1041 | scratch_addr = i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES; |
0160f055 | 1042 | |
83b8a982 AS |
1043 | wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); |
1044 | wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 | | |
1045 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1046 | PIPE_CONTROL_CS_STALL | | |
1047 | PIPE_CONTROL_QW_WRITE)); | |
1048 | wa_ctx_emit(batch, index, scratch_addr); | |
1049 | wa_ctx_emit(batch, index, 0); | |
1050 | wa_ctx_emit(batch, index, 0); | |
1051 | wa_ctx_emit(batch, index, 0); | |
0160f055 | 1052 | |
17ee950d AS |
1053 | /* Pad to end of cacheline */ |
1054 | while (index % CACHELINE_DWORDS) | |
83b8a982 | 1055 | wa_ctx_emit(batch, index, MI_NOOP); |
17ee950d AS |
1056 | |
1057 | /* | |
1058 | * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because | |
1059 | * execution depends on the length specified in terms of cache lines | |
1060 | * in the register CTX_RCS_INDIRECT_CTX | |
1061 | */ | |
1062 | ||
1063 | return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); | |
1064 | } | |
1065 | ||
6e5248b5 DV |
1066 | /* |
1067 | * This batch is started immediately after indirect_ctx batch. Since we ensure | |
1068 | * that indirect_ctx ends on a cacheline this batch is aligned automatically. | |
17ee950d | 1069 | * |
6e5248b5 | 1070 | * The number of DWORDS written are returned using this field. |
17ee950d AS |
1071 | * |
1072 | * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding | |
1073 | * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant. | |
1074 | */ | |
0bc40be8 | 1075 | static int gen8_init_perctx_bb(struct intel_engine_cs *engine, |
17ee950d | 1076 | struct i915_wa_ctx_bb *wa_ctx, |
6e5248b5 | 1077 | uint32_t *batch, |
17ee950d AS |
1078 | uint32_t *offset) |
1079 | { | |
1080 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); | |
1081 | ||
7ad00d1a | 1082 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
83b8a982 | 1083 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
7ad00d1a | 1084 | |
83b8a982 | 1085 | wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); |
17ee950d AS |
1086 | |
1087 | return wa_ctx_end(wa_ctx, *offset = index, 1); | |
1088 | } | |
1089 | ||
0bc40be8 | 1090 | static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine, |
0504cffc | 1091 | struct i915_wa_ctx_bb *wa_ctx, |
6e5248b5 | 1092 | uint32_t *batch, |
0504cffc AS |
1093 | uint32_t *offset) |
1094 | { | |
a4106a78 | 1095 | int ret; |
5e580523 | 1096 | struct drm_i915_private *dev_priv = engine->i915; |
0504cffc AS |
1097 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
1098 | ||
9fb5026f | 1099 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */ |
0bc40be8 | 1100 | ret = gen8_emit_flush_coherentl3_wa(engine, batch, index); |
a4106a78 AS |
1101 | if (ret < 0) |
1102 | return ret; | |
1103 | index = ret; | |
1104 | ||
9fb5026f | 1105 | /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */ |
873e8171 MK |
1106 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); |
1107 | wa_ctx_emit_reg(batch, index, COMMON_SLICE_CHICKEN2); | |
1108 | wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE( | |
1109 | GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE)); | |
1110 | wa_ctx_emit(batch, index, MI_NOOP); | |
1111 | ||
066d4628 MK |
1112 | /* WaClearSlmSpaceAtContextSwitch:kbl */ |
1113 | /* Actual scratch location is at 128 bytes offset */ | |
703d1282 | 1114 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0)) { |
56c0f1a7 | 1115 | u32 scratch_addr = |
bde13ebd | 1116 | i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES; |
066d4628 MK |
1117 | |
1118 | wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); | |
1119 | wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 | | |
1120 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1121 | PIPE_CONTROL_CS_STALL | | |
1122 | PIPE_CONTROL_QW_WRITE)); | |
1123 | wa_ctx_emit(batch, index, scratch_addr); | |
1124 | wa_ctx_emit(batch, index, 0); | |
1125 | wa_ctx_emit(batch, index, 0); | |
1126 | wa_ctx_emit(batch, index, 0); | |
1127 | } | |
3485d99e | 1128 | |
9fb5026f | 1129 | /* WaMediaPoolStateCmdInWABB:bxt,glk */ |
3485d99e TG |
1130 | if (HAS_POOLED_EU(engine->i915)) { |
1131 | /* | |
1132 | * EU pool configuration is setup along with golden context | |
1133 | * during context initialization. This value depends on | |
1134 | * device type (2x6 or 3x6) and needs to be updated based | |
1135 | * on which subslice is disabled especially for 2x6 | |
1136 | * devices, however it is safe to load default | |
1137 | * configuration of 3x6 device instead of masking off | |
1138 | * corresponding bits because HW ignores bits of a disabled | |
1139 | * subslice and drops down to appropriate config. Please | |
1140 | * see render_state_setup() in i915_gem_render_state.c for | |
1141 | * possible configurations, to avoid duplication they are | |
1142 | * not shown here again. | |
1143 | */ | |
1144 | u32 eu_pool_config = 0x00777000; | |
1145 | wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_STATE); | |
1146 | wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_ENABLE); | |
1147 | wa_ctx_emit(batch, index, eu_pool_config); | |
1148 | wa_ctx_emit(batch, index, 0); | |
1149 | wa_ctx_emit(batch, index, 0); | |
1150 | wa_ctx_emit(batch, index, 0); | |
1151 | } | |
1152 | ||
0504cffc AS |
1153 | /* Pad to end of cacheline */ |
1154 | while (index % CACHELINE_DWORDS) | |
1155 | wa_ctx_emit(batch, index, MI_NOOP); | |
1156 | ||
1157 | return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); | |
1158 | } | |
1159 | ||
0bc40be8 | 1160 | static int gen9_init_perctx_bb(struct intel_engine_cs *engine, |
0504cffc | 1161 | struct i915_wa_ctx_bb *wa_ctx, |
6e5248b5 | 1162 | uint32_t *batch, |
0504cffc AS |
1163 | uint32_t *offset) |
1164 | { | |
1165 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); | |
1166 | ||
1167 | wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); | |
1168 | ||
1169 | return wa_ctx_end(wa_ctx, *offset = index, 1); | |
1170 | } | |
1171 | ||
0bc40be8 | 1172 | static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *engine, u32 size) |
17ee950d | 1173 | { |
48bb74e4 CW |
1174 | struct drm_i915_gem_object *obj; |
1175 | struct i915_vma *vma; | |
1176 | int err; | |
17ee950d | 1177 | |
12d79d78 | 1178 | obj = i915_gem_object_create(engine->i915, PAGE_ALIGN(size)); |
48bb74e4 CW |
1179 | if (IS_ERR(obj)) |
1180 | return PTR_ERR(obj); | |
17ee950d | 1181 | |
a01cb37a | 1182 | vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL); |
48bb74e4 CW |
1183 | if (IS_ERR(vma)) { |
1184 | err = PTR_ERR(vma); | |
1185 | goto err; | |
17ee950d AS |
1186 | } |
1187 | ||
48bb74e4 CW |
1188 | err = i915_vma_pin(vma, 0, PAGE_SIZE, PIN_GLOBAL | PIN_HIGH); |
1189 | if (err) | |
1190 | goto err; | |
1191 | ||
1192 | engine->wa_ctx.vma = vma; | |
17ee950d | 1193 | return 0; |
48bb74e4 CW |
1194 | |
1195 | err: | |
1196 | i915_gem_object_put(obj); | |
1197 | return err; | |
17ee950d AS |
1198 | } |
1199 | ||
0bc40be8 | 1200 | static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *engine) |
17ee950d | 1201 | { |
19880c4a | 1202 | i915_vma_unpin_and_release(&engine->wa_ctx.vma); |
17ee950d AS |
1203 | } |
1204 | ||
0bc40be8 | 1205 | static int intel_init_workaround_bb(struct intel_engine_cs *engine) |
17ee950d | 1206 | { |
48bb74e4 | 1207 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; |
17ee950d AS |
1208 | uint32_t *batch; |
1209 | uint32_t offset; | |
1210 | struct page *page; | |
48bb74e4 | 1211 | int ret; |
17ee950d | 1212 | |
0bc40be8 | 1213 | WARN_ON(engine->id != RCS); |
17ee950d | 1214 | |
5e60d790 | 1215 | /* update this when WA for higher Gen are added */ |
c033666a | 1216 | if (INTEL_GEN(engine->i915) > 9) { |
0504cffc | 1217 | DRM_ERROR("WA batch buffer is not initialized for Gen%d\n", |
c033666a | 1218 | INTEL_GEN(engine->i915)); |
5e60d790 | 1219 | return 0; |
0504cffc | 1220 | } |
5e60d790 | 1221 | |
c4db7599 | 1222 | /* some WA perform writes to scratch page, ensure it is valid */ |
56c0f1a7 | 1223 | if (!engine->scratch) { |
0bc40be8 | 1224 | DRM_ERROR("scratch page not allocated for %s\n", engine->name); |
c4db7599 AS |
1225 | return -EINVAL; |
1226 | } | |
1227 | ||
0bc40be8 | 1228 | ret = lrc_setup_wa_ctx_obj(engine, PAGE_SIZE); |
17ee950d AS |
1229 | if (ret) { |
1230 | DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret); | |
1231 | return ret; | |
1232 | } | |
1233 | ||
48bb74e4 | 1234 | page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0); |
17ee950d AS |
1235 | batch = kmap_atomic(page); |
1236 | offset = 0; | |
1237 | ||
c033666a | 1238 | if (IS_GEN8(engine->i915)) { |
0bc40be8 | 1239 | ret = gen8_init_indirectctx_bb(engine, |
17ee950d AS |
1240 | &wa_ctx->indirect_ctx, |
1241 | batch, | |
1242 | &offset); | |
1243 | if (ret) | |
1244 | goto out; | |
1245 | ||
0bc40be8 | 1246 | ret = gen8_init_perctx_bb(engine, |
17ee950d AS |
1247 | &wa_ctx->per_ctx, |
1248 | batch, | |
1249 | &offset); | |
1250 | if (ret) | |
1251 | goto out; | |
c033666a | 1252 | } else if (IS_GEN9(engine->i915)) { |
0bc40be8 | 1253 | ret = gen9_init_indirectctx_bb(engine, |
0504cffc AS |
1254 | &wa_ctx->indirect_ctx, |
1255 | batch, | |
1256 | &offset); | |
1257 | if (ret) | |
1258 | goto out; | |
1259 | ||
0bc40be8 | 1260 | ret = gen9_init_perctx_bb(engine, |
0504cffc AS |
1261 | &wa_ctx->per_ctx, |
1262 | batch, | |
1263 | &offset); | |
1264 | if (ret) | |
1265 | goto out; | |
17ee950d AS |
1266 | } |
1267 | ||
1268 | out: | |
1269 | kunmap_atomic(batch); | |
1270 | if (ret) | |
0bc40be8 | 1271 | lrc_destroy_wa_ctx_obj(engine); |
17ee950d AS |
1272 | |
1273 | return ret; | |
1274 | } | |
1275 | ||
22cc440e CW |
1276 | static u32 port_seqno(struct execlist_port *port) |
1277 | { | |
1278 | return port->request ? port->request->global_seqno : 0; | |
1279 | } | |
1280 | ||
0bc40be8 | 1281 | static int gen8_init_common_ring(struct intel_engine_cs *engine) |
9b1136d5 | 1282 | { |
c033666a | 1283 | struct drm_i915_private *dev_priv = engine->i915; |
821ed7df CW |
1284 | int ret; |
1285 | ||
1286 | ret = intel_mocs_init_engine(engine); | |
1287 | if (ret) | |
1288 | return ret; | |
9b1136d5 | 1289 | |
ad07dfcd | 1290 | intel_engine_reset_breadcrumbs(engine); |
f3b8f912 | 1291 | intel_engine_init_hangcheck(engine); |
821ed7df | 1292 | |
0bc40be8 | 1293 | I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff); |
0bc40be8 | 1294 | I915_WRITE(RING_MODE_GEN7(engine), |
9b1136d5 OM |
1295 | _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) | |
1296 | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); | |
f3b8f912 CW |
1297 | I915_WRITE(RING_HWS_PGA(engine->mmio_base), |
1298 | engine->status_page.ggtt_offset); | |
1299 | POSTING_READ(RING_HWS_PGA(engine->mmio_base)); | |
dfc53c5e | 1300 | |
0bc40be8 | 1301 | DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name); |
9b1136d5 | 1302 | |
c87d50cc | 1303 | /* After a GPU reset, we may have requests to replay */ |
f747026c | 1304 | clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); |
c87d50cc | 1305 | if (!execlists_elsp_idle(engine)) { |
22cc440e CW |
1306 | DRM_DEBUG_DRIVER("Restarting %s from requests [0x%x, 0x%x]\n", |
1307 | engine->name, | |
1308 | port_seqno(&engine->execlist_port[0]), | |
1309 | port_seqno(&engine->execlist_port[1])); | |
c87d50cc CW |
1310 | engine->execlist_port[0].count = 0; |
1311 | engine->execlist_port[1].count = 0; | |
821ed7df | 1312 | execlists_submit_ports(engine); |
c87d50cc | 1313 | } |
821ed7df CW |
1314 | |
1315 | return 0; | |
9b1136d5 OM |
1316 | } |
1317 | ||
0bc40be8 | 1318 | static int gen8_init_render_ring(struct intel_engine_cs *engine) |
9b1136d5 | 1319 | { |
c033666a | 1320 | struct drm_i915_private *dev_priv = engine->i915; |
9b1136d5 OM |
1321 | int ret; |
1322 | ||
0bc40be8 | 1323 | ret = gen8_init_common_ring(engine); |
9b1136d5 OM |
1324 | if (ret) |
1325 | return ret; | |
1326 | ||
1327 | /* We need to disable the AsyncFlip performance optimisations in order | |
1328 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1329 | * programmed to '1' on all products. | |
1330 | * | |
1331 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv | |
1332 | */ | |
1333 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
1334 | ||
9b1136d5 OM |
1335 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
1336 | ||
0bc40be8 | 1337 | return init_workarounds_ring(engine); |
9b1136d5 OM |
1338 | } |
1339 | ||
0bc40be8 | 1340 | static int gen9_init_render_ring(struct intel_engine_cs *engine) |
82ef822e DL |
1341 | { |
1342 | int ret; | |
1343 | ||
0bc40be8 | 1344 | ret = gen8_init_common_ring(engine); |
82ef822e DL |
1345 | if (ret) |
1346 | return ret; | |
1347 | ||
0bc40be8 | 1348 | return init_workarounds_ring(engine); |
82ef822e DL |
1349 | } |
1350 | ||
821ed7df CW |
1351 | static void reset_common_ring(struct intel_engine_cs *engine, |
1352 | struct drm_i915_gem_request *request) | |
1353 | { | |
821ed7df CW |
1354 | struct execlist_port *port = engine->execlist_port; |
1355 | struct intel_context *ce = &request->ctx->engine[engine->id]; | |
1356 | ||
a3aabe86 CW |
1357 | /* We want a simple context + ring to execute the breadcrumb update. |
1358 | * We cannot rely on the context being intact across the GPU hang, | |
1359 | * so clear it and rebuild just what we need for the breadcrumb. | |
1360 | * All pending requests for this context will be zapped, and any | |
1361 | * future request will be after userspace has had the opportunity | |
1362 | * to recreate its own state. | |
1363 | */ | |
1364 | execlists_init_reg_state(ce->lrc_reg_state, | |
1365 | request->ctx, engine, ce->ring); | |
1366 | ||
821ed7df | 1367 | /* Move the RING_HEAD onto the breadcrumb, past the hanging batch */ |
a3aabe86 CW |
1368 | ce->lrc_reg_state[CTX_RING_BUFFER_START+1] = |
1369 | i915_ggtt_offset(ce->ring->vma); | |
821ed7df | 1370 | ce->lrc_reg_state[CTX_RING_HEAD+1] = request->postfix; |
a3aabe86 | 1371 | |
821ed7df CW |
1372 | request->ring->head = request->postfix; |
1373 | request->ring->last_retired_head = -1; | |
1374 | intel_ring_update_space(request->ring); | |
1375 | ||
1376 | if (i915.enable_guc_submission) | |
1377 | return; | |
1378 | ||
1379 | /* Catch up with any missed context-switch interrupts */ | |
821ed7df CW |
1380 | if (request->ctx != port[0].request->ctx) { |
1381 | i915_gem_request_put(port[0].request); | |
1382 | port[0] = port[1]; | |
1383 | memset(&port[1], 0, sizeof(port[1])); | |
1384 | } | |
1385 | ||
821ed7df | 1386 | GEM_BUG_ON(request->ctx != port[0].request->ctx); |
a3aabe86 CW |
1387 | |
1388 | /* Reset WaIdleLiteRestore:bdw,skl as well */ | |
1389 | request->tail = request->wa_tail - WA_TAIL_DWORDS * sizeof(u32); | |
821ed7df CW |
1390 | } |
1391 | ||
7a01a0a2 MT |
1392 | static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req) |
1393 | { | |
1394 | struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt; | |
7e37f889 | 1395 | struct intel_ring *ring = req->ring; |
4a570db5 | 1396 | struct intel_engine_cs *engine = req->engine; |
7a01a0a2 MT |
1397 | const int num_lri_cmds = GEN8_LEGACY_PDPES * 2; |
1398 | int i, ret; | |
1399 | ||
987046ad | 1400 | ret = intel_ring_begin(req, num_lri_cmds * 2 + 2); |
7a01a0a2 MT |
1401 | if (ret) |
1402 | return ret; | |
1403 | ||
b5321f30 | 1404 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_lri_cmds)); |
7a01a0a2 MT |
1405 | for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { |
1406 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); | |
1407 | ||
b5321f30 CW |
1408 | intel_ring_emit_reg(ring, GEN8_RING_PDP_UDW(engine, i)); |
1409 | intel_ring_emit(ring, upper_32_bits(pd_daddr)); | |
1410 | intel_ring_emit_reg(ring, GEN8_RING_PDP_LDW(engine, i)); | |
1411 | intel_ring_emit(ring, lower_32_bits(pd_daddr)); | |
7a01a0a2 MT |
1412 | } |
1413 | ||
b5321f30 CW |
1414 | intel_ring_emit(ring, MI_NOOP); |
1415 | intel_ring_advance(ring); | |
7a01a0a2 MT |
1416 | |
1417 | return 0; | |
1418 | } | |
1419 | ||
be795fc1 | 1420 | static int gen8_emit_bb_start(struct drm_i915_gem_request *req, |
803688ba CW |
1421 | u64 offset, u32 len, |
1422 | unsigned int dispatch_flags) | |
15648585 | 1423 | { |
7e37f889 | 1424 | struct intel_ring *ring = req->ring; |
8e004efc | 1425 | bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE); |
15648585 OM |
1426 | int ret; |
1427 | ||
7a01a0a2 MT |
1428 | /* Don't rely in hw updating PDPs, specially in lite-restore. |
1429 | * Ideally, we should set Force PD Restore in ctx descriptor, | |
1430 | * but we can't. Force Restore would be a second option, but | |
1431 | * it is unsafe in case of lite-restore (because the ctx is | |
2dba3239 MT |
1432 | * not idle). PML4 is allocated during ppgtt init so this is |
1433 | * not needed in 48-bit.*/ | |
7a01a0a2 | 1434 | if (req->ctx->ppgtt && |
666796da | 1435 | (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) { |
331f38e7 | 1436 | if (!USES_FULL_48BIT_PPGTT(req->i915) && |
c033666a | 1437 | !intel_vgpu_active(req->i915)) { |
2dba3239 MT |
1438 | ret = intel_logical_ring_emit_pdps(req); |
1439 | if (ret) | |
1440 | return ret; | |
1441 | } | |
7a01a0a2 | 1442 | |
666796da | 1443 | req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine); |
7a01a0a2 MT |
1444 | } |
1445 | ||
987046ad | 1446 | ret = intel_ring_begin(req, 4); |
15648585 OM |
1447 | if (ret) |
1448 | return ret; | |
1449 | ||
1450 | /* FIXME(BDW): Address space and security selectors. */ | |
b5321f30 CW |
1451 | intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | |
1452 | (ppgtt<<8) | | |
1453 | (dispatch_flags & I915_DISPATCH_RS ? | |
1454 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
1455 | intel_ring_emit(ring, lower_32_bits(offset)); | |
1456 | intel_ring_emit(ring, upper_32_bits(offset)); | |
1457 | intel_ring_emit(ring, MI_NOOP); | |
1458 | intel_ring_advance(ring); | |
15648585 OM |
1459 | |
1460 | return 0; | |
1461 | } | |
1462 | ||
31bb59cc | 1463 | static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine) |
73d477f6 | 1464 | { |
c033666a | 1465 | struct drm_i915_private *dev_priv = engine->i915; |
31bb59cc CW |
1466 | I915_WRITE_IMR(engine, |
1467 | ~(engine->irq_enable_mask | engine->irq_keep_mask)); | |
1468 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
73d477f6 OM |
1469 | } |
1470 | ||
31bb59cc | 1471 | static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine) |
73d477f6 | 1472 | { |
c033666a | 1473 | struct drm_i915_private *dev_priv = engine->i915; |
31bb59cc | 1474 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
73d477f6 OM |
1475 | } |
1476 | ||
7c9cf4e3 | 1477 | static int gen8_emit_flush(struct drm_i915_gem_request *request, u32 mode) |
4712274c | 1478 | { |
7e37f889 CW |
1479 | struct intel_ring *ring = request->ring; |
1480 | u32 cmd; | |
4712274c OM |
1481 | int ret; |
1482 | ||
987046ad | 1483 | ret = intel_ring_begin(request, 4); |
4712274c OM |
1484 | if (ret) |
1485 | return ret; | |
1486 | ||
1487 | cmd = MI_FLUSH_DW + 1; | |
1488 | ||
f0a1fb10 CW |
1489 | /* We always require a command barrier so that subsequent |
1490 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1491 | * wrt the contents of the write cache being flushed to memory | |
1492 | * (and thus being coherent from the CPU). | |
1493 | */ | |
1494 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1495 | ||
7c9cf4e3 | 1496 | if (mode & EMIT_INVALIDATE) { |
f0a1fb10 | 1497 | cmd |= MI_INVALIDATE_TLB; |
1dae2dfb | 1498 | if (request->engine->id == VCS) |
f0a1fb10 | 1499 | cmd |= MI_INVALIDATE_BSD; |
4712274c OM |
1500 | } |
1501 | ||
b5321f30 CW |
1502 | intel_ring_emit(ring, cmd); |
1503 | intel_ring_emit(ring, | |
1504 | I915_GEM_HWS_SCRATCH_ADDR | | |
1505 | MI_FLUSH_DW_USE_GTT); | |
1506 | intel_ring_emit(ring, 0); /* upper addr */ | |
1507 | intel_ring_emit(ring, 0); /* value */ | |
1508 | intel_ring_advance(ring); | |
4712274c OM |
1509 | |
1510 | return 0; | |
1511 | } | |
1512 | ||
7deb4d39 | 1513 | static int gen8_emit_flush_render(struct drm_i915_gem_request *request, |
7c9cf4e3 | 1514 | u32 mode) |
4712274c | 1515 | { |
7e37f889 | 1516 | struct intel_ring *ring = request->ring; |
b5321f30 | 1517 | struct intel_engine_cs *engine = request->engine; |
bde13ebd CW |
1518 | u32 scratch_addr = |
1519 | i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES; | |
0b2d0934 | 1520 | bool vf_flush_wa = false, dc_flush_wa = false; |
4712274c OM |
1521 | u32 flags = 0; |
1522 | int ret; | |
0b2d0934 | 1523 | int len; |
4712274c OM |
1524 | |
1525 | flags |= PIPE_CONTROL_CS_STALL; | |
1526 | ||
7c9cf4e3 | 1527 | if (mode & EMIT_FLUSH) { |
4712274c OM |
1528 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
1529 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 1530 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 1531 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4712274c OM |
1532 | } |
1533 | ||
7c9cf4e3 | 1534 | if (mode & EMIT_INVALIDATE) { |
4712274c OM |
1535 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
1536 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
1537 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
1538 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
1539 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
1540 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
1541 | flags |= PIPE_CONTROL_QW_WRITE; | |
1542 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
4712274c | 1543 | |
1a5a9ce7 BW |
1544 | /* |
1545 | * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL | |
1546 | * pipe control. | |
1547 | */ | |
c033666a | 1548 | if (IS_GEN9(request->i915)) |
1a5a9ce7 | 1549 | vf_flush_wa = true; |
0b2d0934 MK |
1550 | |
1551 | /* WaForGAMHang:kbl */ | |
1552 | if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0)) | |
1553 | dc_flush_wa = true; | |
1a5a9ce7 | 1554 | } |
9647ff36 | 1555 | |
0b2d0934 MK |
1556 | len = 6; |
1557 | ||
1558 | if (vf_flush_wa) | |
1559 | len += 6; | |
1560 | ||
1561 | if (dc_flush_wa) | |
1562 | len += 12; | |
1563 | ||
1564 | ret = intel_ring_begin(request, len); | |
4712274c OM |
1565 | if (ret) |
1566 | return ret; | |
1567 | ||
9647ff36 | 1568 | if (vf_flush_wa) { |
b5321f30 CW |
1569 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
1570 | intel_ring_emit(ring, 0); | |
1571 | intel_ring_emit(ring, 0); | |
1572 | intel_ring_emit(ring, 0); | |
1573 | intel_ring_emit(ring, 0); | |
1574 | intel_ring_emit(ring, 0); | |
9647ff36 ID |
1575 | } |
1576 | ||
0b2d0934 | 1577 | if (dc_flush_wa) { |
b5321f30 CW |
1578 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
1579 | intel_ring_emit(ring, PIPE_CONTROL_DC_FLUSH_ENABLE); | |
1580 | intel_ring_emit(ring, 0); | |
1581 | intel_ring_emit(ring, 0); | |
1582 | intel_ring_emit(ring, 0); | |
1583 | intel_ring_emit(ring, 0); | |
0b2d0934 MK |
1584 | } |
1585 | ||
b5321f30 CW |
1586 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
1587 | intel_ring_emit(ring, flags); | |
1588 | intel_ring_emit(ring, scratch_addr); | |
1589 | intel_ring_emit(ring, 0); | |
1590 | intel_ring_emit(ring, 0); | |
1591 | intel_ring_emit(ring, 0); | |
0b2d0934 MK |
1592 | |
1593 | if (dc_flush_wa) { | |
b5321f30 CW |
1594 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
1595 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL); | |
1596 | intel_ring_emit(ring, 0); | |
1597 | intel_ring_emit(ring, 0); | |
1598 | intel_ring_emit(ring, 0); | |
1599 | intel_ring_emit(ring, 0); | |
0b2d0934 MK |
1600 | } |
1601 | ||
b5321f30 | 1602 | intel_ring_advance(ring); |
4712274c OM |
1603 | |
1604 | return 0; | |
1605 | } | |
1606 | ||
7c17d377 CW |
1607 | /* |
1608 | * Reserve space for 2 NOOPs at the end of each request to be | |
1609 | * used as a workaround for not being allowed to do lite | |
1610 | * restore with HEAD==TAIL (WaIdleLiteRestore). | |
1611 | */ | |
caddfe71 | 1612 | static void gen8_emit_wa_tail(struct drm_i915_gem_request *request, u32 *out) |
4da46e1e | 1613 | { |
caddfe71 CW |
1614 | *out++ = MI_NOOP; |
1615 | *out++ = MI_NOOP; | |
1616 | request->wa_tail = intel_ring_offset(request->ring, out); | |
1617 | } | |
4da46e1e | 1618 | |
caddfe71 CW |
1619 | static void gen8_emit_breadcrumb(struct drm_i915_gem_request *request, |
1620 | u32 *out) | |
1621 | { | |
7c17d377 CW |
1622 | /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */ |
1623 | BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5)); | |
4da46e1e | 1624 | |
caddfe71 CW |
1625 | *out++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW; |
1626 | *out++ = intel_hws_seqno_address(request->engine) | MI_FLUSH_DW_USE_GTT; | |
1627 | *out++ = 0; | |
1628 | *out++ = request->global_seqno; | |
1629 | *out++ = MI_USER_INTERRUPT; | |
1630 | *out++ = MI_NOOP; | |
1631 | request->tail = intel_ring_offset(request->ring, out); | |
1632 | ||
1633 | gen8_emit_wa_tail(request, out); | |
7c17d377 | 1634 | } |
4da46e1e | 1635 | |
98f29e8d CW |
1636 | static const int gen8_emit_breadcrumb_sz = 6 + WA_TAIL_DWORDS; |
1637 | ||
caddfe71 CW |
1638 | static void gen8_emit_breadcrumb_render(struct drm_i915_gem_request *request, |
1639 | u32 *out) | |
7c17d377 | 1640 | { |
ce81a65c MW |
1641 | /* We're using qword write, seqno should be aligned to 8 bytes. */ |
1642 | BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1); | |
1643 | ||
7c17d377 CW |
1644 | /* w/a for post sync ops following a GPGPU operation we |
1645 | * need a prior CS_STALL, which is emitted by the flush | |
1646 | * following the batch. | |
1647 | */ | |
caddfe71 CW |
1648 | *out++ = GFX_OP_PIPE_CONTROL(6); |
1649 | *out++ = (PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1650 | PIPE_CONTROL_CS_STALL | | |
1651 | PIPE_CONTROL_QW_WRITE); | |
1652 | *out++ = intel_hws_seqno_address(request->engine); | |
1653 | *out++ = 0; | |
1654 | *out++ = request->global_seqno; | |
ce81a65c | 1655 | /* We're thrashing one dword of HWS. */ |
caddfe71 CW |
1656 | *out++ = 0; |
1657 | *out++ = MI_USER_INTERRUPT; | |
1658 | *out++ = MI_NOOP; | |
1659 | request->tail = intel_ring_offset(request->ring, out); | |
1660 | ||
1661 | gen8_emit_wa_tail(request, out); | |
4da46e1e OM |
1662 | } |
1663 | ||
98f29e8d CW |
1664 | static const int gen8_emit_breadcrumb_render_sz = 8 + WA_TAIL_DWORDS; |
1665 | ||
8753181e | 1666 | static int gen8_init_rcs_context(struct drm_i915_gem_request *req) |
e7778be1 TD |
1667 | { |
1668 | int ret; | |
1669 | ||
e2be4faf | 1670 | ret = intel_logical_ring_workarounds_emit(req); |
e7778be1 TD |
1671 | if (ret) |
1672 | return ret; | |
1673 | ||
3bbaba0c PA |
1674 | ret = intel_rcs_context_init_mocs(req); |
1675 | /* | |
1676 | * Failing to program the MOCS is non-fatal.The system will not | |
1677 | * run at peak performance. So generate an error and carry on. | |
1678 | */ | |
1679 | if (ret) | |
1680 | DRM_ERROR("MOCS failed to program: expect performance issues.\n"); | |
1681 | ||
4e50f082 | 1682 | return i915_gem_render_state_emit(req); |
e7778be1 TD |
1683 | } |
1684 | ||
73e4d07f OM |
1685 | /** |
1686 | * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer | |
14bb2c11 | 1687 | * @engine: Engine Command Streamer. |
73e4d07f | 1688 | */ |
0bc40be8 | 1689 | void intel_logical_ring_cleanup(struct intel_engine_cs *engine) |
454afebd | 1690 | { |
6402c330 | 1691 | struct drm_i915_private *dev_priv; |
9832b9da | 1692 | |
27af5eea TU |
1693 | /* |
1694 | * Tasklet cannot be active at this point due intel_mark_active/idle | |
1695 | * so this is just for documentation. | |
1696 | */ | |
1697 | if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state))) | |
1698 | tasklet_kill(&engine->irq_tasklet); | |
1699 | ||
c033666a | 1700 | dev_priv = engine->i915; |
6402c330 | 1701 | |
0bc40be8 | 1702 | if (engine->buffer) { |
0bc40be8 | 1703 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
b0366a54 | 1704 | } |
48d82387 | 1705 | |
0bc40be8 TU |
1706 | if (engine->cleanup) |
1707 | engine->cleanup(engine); | |
48d82387 | 1708 | |
57e88531 CW |
1709 | if (engine->status_page.vma) { |
1710 | i915_gem_object_unpin_map(engine->status_page.vma->obj); | |
1711 | engine->status_page.vma = NULL; | |
48d82387 | 1712 | } |
e8a9c58f CW |
1713 | |
1714 | intel_engine_cleanup_common(engine); | |
17ee950d | 1715 | |
0bc40be8 | 1716 | lrc_destroy_wa_ctx_obj(engine); |
c033666a | 1717 | engine->i915 = NULL; |
3b3f1650 AG |
1718 | dev_priv->engine[engine->id] = NULL; |
1719 | kfree(engine); | |
454afebd OM |
1720 | } |
1721 | ||
ddd66c51 CW |
1722 | void intel_execlists_enable_submission(struct drm_i915_private *dev_priv) |
1723 | { | |
1724 | struct intel_engine_cs *engine; | |
3b3f1650 | 1725 | enum intel_engine_id id; |
ddd66c51 | 1726 | |
20311bd3 | 1727 | for_each_engine(engine, dev_priv, id) { |
f4ea6bdd | 1728 | engine->submit_request = execlists_submit_request; |
20311bd3 CW |
1729 | engine->schedule = execlists_schedule; |
1730 | } | |
ddd66c51 CW |
1731 | } |
1732 | ||
c9cacf93 | 1733 | static void |
e1382efb | 1734 | logical_ring_default_vfuncs(struct intel_engine_cs *engine) |
c9cacf93 TU |
1735 | { |
1736 | /* Default vfuncs which can be overriden by each engine. */ | |
0bc40be8 | 1737 | engine->init_hw = gen8_init_common_ring; |
821ed7df | 1738 | engine->reset_hw = reset_common_ring; |
e8a9c58f CW |
1739 | |
1740 | engine->context_pin = execlists_context_pin; | |
1741 | engine->context_unpin = execlists_context_unpin; | |
1742 | ||
f73e7399 CW |
1743 | engine->request_alloc = execlists_request_alloc; |
1744 | ||
0bc40be8 | 1745 | engine->emit_flush = gen8_emit_flush; |
9b81d556 | 1746 | engine->emit_breadcrumb = gen8_emit_breadcrumb; |
98f29e8d | 1747 | engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz; |
f4ea6bdd | 1748 | engine->submit_request = execlists_submit_request; |
20311bd3 | 1749 | engine->schedule = execlists_schedule; |
ddd66c51 | 1750 | |
31bb59cc CW |
1751 | engine->irq_enable = gen8_logical_ring_enable_irq; |
1752 | engine->irq_disable = gen8_logical_ring_disable_irq; | |
0bc40be8 | 1753 | engine->emit_bb_start = gen8_emit_bb_start; |
c9cacf93 TU |
1754 | } |
1755 | ||
d9f3af96 | 1756 | static inline void |
c2c7f240 | 1757 | logical_ring_default_irqs(struct intel_engine_cs *engine) |
d9f3af96 | 1758 | { |
c2c7f240 | 1759 | unsigned shift = engine->irq_shift; |
0bc40be8 TU |
1760 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift; |
1761 | engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift; | |
d9f3af96 TU |
1762 | } |
1763 | ||
7d774cac | 1764 | static int |
bf3783e5 | 1765 | lrc_setup_hws(struct intel_engine_cs *engine, struct i915_vma *vma) |
04794adb | 1766 | { |
57e88531 | 1767 | const int hws_offset = LRC_PPHWSP_PN * PAGE_SIZE; |
7d774cac | 1768 | void *hws; |
04794adb TU |
1769 | |
1770 | /* The HWSP is part of the default context object in LRC mode. */ | |
bf3783e5 | 1771 | hws = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); |
7d774cac TU |
1772 | if (IS_ERR(hws)) |
1773 | return PTR_ERR(hws); | |
57e88531 CW |
1774 | |
1775 | engine->status_page.page_addr = hws + hws_offset; | |
bde13ebd | 1776 | engine->status_page.ggtt_offset = i915_ggtt_offset(vma) + hws_offset; |
57e88531 | 1777 | engine->status_page.vma = vma; |
7d774cac TU |
1778 | |
1779 | return 0; | |
04794adb TU |
1780 | } |
1781 | ||
bb45438f TU |
1782 | static void |
1783 | logical_ring_setup(struct intel_engine_cs *engine) | |
1784 | { | |
1785 | struct drm_i915_private *dev_priv = engine->i915; | |
1786 | enum forcewake_domains fw_domains; | |
1787 | ||
019bf277 TU |
1788 | intel_engine_setup_common(engine); |
1789 | ||
bb45438f TU |
1790 | /* Intentionally left blank. */ |
1791 | engine->buffer = NULL; | |
1792 | ||
1793 | fw_domains = intel_uncore_forcewake_for_reg(dev_priv, | |
1794 | RING_ELSP(engine), | |
1795 | FW_REG_WRITE); | |
1796 | ||
1797 | fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, | |
1798 | RING_CONTEXT_STATUS_PTR(engine), | |
1799 | FW_REG_READ | FW_REG_WRITE); | |
1800 | ||
1801 | fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, | |
1802 | RING_CONTEXT_STATUS_BUF_BASE(engine), | |
1803 | FW_REG_READ); | |
1804 | ||
1805 | engine->fw_domains = fw_domains; | |
1806 | ||
bb45438f TU |
1807 | tasklet_init(&engine->irq_tasklet, |
1808 | intel_lrc_irq_handler, (unsigned long)engine); | |
1809 | ||
bb45438f TU |
1810 | logical_ring_default_vfuncs(engine); |
1811 | logical_ring_default_irqs(engine); | |
bb45438f TU |
1812 | } |
1813 | ||
a19d6ff2 TU |
1814 | static int |
1815 | logical_ring_init(struct intel_engine_cs *engine) | |
1816 | { | |
1817 | struct i915_gem_context *dctx = engine->i915->kernel_context; | |
1818 | int ret; | |
1819 | ||
019bf277 | 1820 | ret = intel_engine_init_common(engine); |
a19d6ff2 TU |
1821 | if (ret) |
1822 | goto error; | |
1823 | ||
a19d6ff2 TU |
1824 | /* And setup the hardware status page. */ |
1825 | ret = lrc_setup_hws(engine, dctx->engine[engine->id].state); | |
1826 | if (ret) { | |
1827 | DRM_ERROR("Failed to set up hws %s: %d\n", engine->name, ret); | |
1828 | goto error; | |
1829 | } | |
1830 | ||
1831 | return 0; | |
1832 | ||
1833 | error: | |
1834 | intel_logical_ring_cleanup(engine); | |
1835 | return ret; | |
1836 | } | |
1837 | ||
88d2ba2e | 1838 | int logical_render_ring_init(struct intel_engine_cs *engine) |
a19d6ff2 TU |
1839 | { |
1840 | struct drm_i915_private *dev_priv = engine->i915; | |
1841 | int ret; | |
1842 | ||
bb45438f TU |
1843 | logical_ring_setup(engine); |
1844 | ||
a19d6ff2 TU |
1845 | if (HAS_L3_DPF(dev_priv)) |
1846 | engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
1847 | ||
1848 | /* Override some for render ring. */ | |
1849 | if (INTEL_GEN(dev_priv) >= 9) | |
1850 | engine->init_hw = gen9_init_render_ring; | |
1851 | else | |
1852 | engine->init_hw = gen8_init_render_ring; | |
1853 | engine->init_context = gen8_init_rcs_context; | |
a19d6ff2 | 1854 | engine->emit_flush = gen8_emit_flush_render; |
9b81d556 | 1855 | engine->emit_breadcrumb = gen8_emit_breadcrumb_render; |
98f29e8d | 1856 | engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_render_sz; |
a19d6ff2 | 1857 | |
f51455d4 | 1858 | ret = intel_engine_create_scratch(engine, PAGE_SIZE); |
a19d6ff2 TU |
1859 | if (ret) |
1860 | return ret; | |
1861 | ||
1862 | ret = intel_init_workaround_bb(engine); | |
1863 | if (ret) { | |
1864 | /* | |
1865 | * We continue even if we fail to initialize WA batch | |
1866 | * because we only expect rare glitches but nothing | |
1867 | * critical to prevent us from using GPU | |
1868 | */ | |
1869 | DRM_ERROR("WA batch buffer initialization failed: %d\n", | |
1870 | ret); | |
1871 | } | |
1872 | ||
d038fc7e | 1873 | return logical_ring_init(engine); |
a19d6ff2 TU |
1874 | } |
1875 | ||
88d2ba2e | 1876 | int logical_xcs_ring_init(struct intel_engine_cs *engine) |
bb45438f TU |
1877 | { |
1878 | logical_ring_setup(engine); | |
1879 | ||
1880 | return logical_ring_init(engine); | |
454afebd OM |
1881 | } |
1882 | ||
0cea6502 | 1883 | static u32 |
c033666a | 1884 | make_rpcs(struct drm_i915_private *dev_priv) |
0cea6502 JM |
1885 | { |
1886 | u32 rpcs = 0; | |
1887 | ||
1888 | /* | |
1889 | * No explicit RPCS request is needed to ensure full | |
1890 | * slice/subslice/EU enablement prior to Gen9. | |
1891 | */ | |
c033666a | 1892 | if (INTEL_GEN(dev_priv) < 9) |
0cea6502 JM |
1893 | return 0; |
1894 | ||
1895 | /* | |
1896 | * Starting in Gen9, render power gating can leave | |
1897 | * slice/subslice/EU in a partially enabled state. We | |
1898 | * must make an explicit request through RPCS for full | |
1899 | * enablement. | |
1900 | */ | |
43b67998 | 1901 | if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) { |
0cea6502 | 1902 | rpcs |= GEN8_RPCS_S_CNT_ENABLE; |
f08a0c92 | 1903 | rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) << |
0cea6502 JM |
1904 | GEN8_RPCS_S_CNT_SHIFT; |
1905 | rpcs |= GEN8_RPCS_ENABLE; | |
1906 | } | |
1907 | ||
43b67998 | 1908 | if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) { |
0cea6502 | 1909 | rpcs |= GEN8_RPCS_SS_CNT_ENABLE; |
57ec171e | 1910 | rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask) << |
0cea6502 JM |
1911 | GEN8_RPCS_SS_CNT_SHIFT; |
1912 | rpcs |= GEN8_RPCS_ENABLE; | |
1913 | } | |
1914 | ||
43b67998 ID |
1915 | if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) { |
1916 | rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice << | |
0cea6502 | 1917 | GEN8_RPCS_EU_MIN_SHIFT; |
43b67998 | 1918 | rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice << |
0cea6502 JM |
1919 | GEN8_RPCS_EU_MAX_SHIFT; |
1920 | rpcs |= GEN8_RPCS_ENABLE; | |
1921 | } | |
1922 | ||
1923 | return rpcs; | |
1924 | } | |
1925 | ||
0bc40be8 | 1926 | static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine) |
71562919 MT |
1927 | { |
1928 | u32 indirect_ctx_offset; | |
1929 | ||
c033666a | 1930 | switch (INTEL_GEN(engine->i915)) { |
71562919 | 1931 | default: |
c033666a | 1932 | MISSING_CASE(INTEL_GEN(engine->i915)); |
71562919 MT |
1933 | /* fall through */ |
1934 | case 9: | |
1935 | indirect_ctx_offset = | |
1936 | GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
1937 | break; | |
1938 | case 8: | |
1939 | indirect_ctx_offset = | |
1940 | GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
1941 | break; | |
1942 | } | |
1943 | ||
1944 | return indirect_ctx_offset; | |
1945 | } | |
1946 | ||
a3aabe86 CW |
1947 | static void execlists_init_reg_state(u32 *reg_state, |
1948 | struct i915_gem_context *ctx, | |
1949 | struct intel_engine_cs *engine, | |
1950 | struct intel_ring *ring) | |
8670d6f9 | 1951 | { |
a3aabe86 CW |
1952 | struct drm_i915_private *dev_priv = engine->i915; |
1953 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv->mm.aliasing_ppgtt; | |
8670d6f9 OM |
1954 | |
1955 | /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM | |
1956 | * commands followed by (reg, value) pairs. The values we are setting here are | |
1957 | * only for the first context restore: on a subsequent save, the GPU will | |
1958 | * recreate this batchbuffer with new values (including all the missing | |
1959 | * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */ | |
0d925ea0 | 1960 | reg_state[CTX_LRI_HEADER_0] = |
0bc40be8 TU |
1961 | MI_LOAD_REGISTER_IMM(engine->id == RCS ? 14 : 11) | MI_LRI_FORCE_POSTED; |
1962 | ASSIGN_CTX_REG(reg_state, CTX_CONTEXT_CONTROL, | |
1963 | RING_CONTEXT_CONTROL(engine), | |
0d925ea0 VS |
1964 | _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | |
1965 | CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | | |
c033666a | 1966 | (HAS_RESOURCE_STREAMER(dev_priv) ? |
a3aabe86 | 1967 | CTX_CTRL_RS_CTX_ENABLE : 0))); |
0bc40be8 TU |
1968 | ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(engine->mmio_base), |
1969 | 0); | |
1970 | ASSIGN_CTX_REG(reg_state, CTX_RING_TAIL, RING_TAIL(engine->mmio_base), | |
1971 | 0); | |
0bc40be8 TU |
1972 | ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_START, |
1973 | RING_START(engine->mmio_base), 0); | |
1974 | ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_CONTROL, | |
1975 | RING_CTL(engine->mmio_base), | |
62ae14b1 | 1976 | RING_CTL_SIZE(ring->size) | RING_VALID); |
0bc40be8 TU |
1977 | ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_U, |
1978 | RING_BBADDR_UDW(engine->mmio_base), 0); | |
1979 | ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_L, | |
1980 | RING_BBADDR(engine->mmio_base), 0); | |
1981 | ASSIGN_CTX_REG(reg_state, CTX_BB_STATE, | |
1982 | RING_BBSTATE(engine->mmio_base), | |
0d925ea0 | 1983 | RING_BB_PPGTT); |
0bc40be8 TU |
1984 | ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_U, |
1985 | RING_SBBADDR_UDW(engine->mmio_base), 0); | |
1986 | ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_L, | |
1987 | RING_SBBADDR(engine->mmio_base), 0); | |
1988 | ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_STATE, | |
1989 | RING_SBBSTATE(engine->mmio_base), 0); | |
1990 | if (engine->id == RCS) { | |
1991 | ASSIGN_CTX_REG(reg_state, CTX_BB_PER_CTX_PTR, | |
1992 | RING_BB_PER_CTX_PTR(engine->mmio_base), 0); | |
1993 | ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX, | |
1994 | RING_INDIRECT_CTX(engine->mmio_base), 0); | |
1995 | ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX_OFFSET, | |
1996 | RING_INDIRECT_CTX_OFFSET(engine->mmio_base), 0); | |
48bb74e4 | 1997 | if (engine->wa_ctx.vma) { |
0bc40be8 | 1998 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; |
bde13ebd | 1999 | u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); |
17ee950d AS |
2000 | |
2001 | reg_state[CTX_RCS_INDIRECT_CTX+1] = | |
2002 | (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) | | |
2003 | (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS); | |
2004 | ||
2005 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = | |
0bc40be8 | 2006 | intel_lr_indirect_ctx_offset(engine) << 6; |
17ee950d AS |
2007 | |
2008 | reg_state[CTX_BB_PER_CTX_PTR+1] = | |
2009 | (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) | | |
2010 | 0x01; | |
2011 | } | |
8670d6f9 | 2012 | } |
0d925ea0 | 2013 | reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED; |
0bc40be8 TU |
2014 | ASSIGN_CTX_REG(reg_state, CTX_CTX_TIMESTAMP, |
2015 | RING_CTX_TIMESTAMP(engine->mmio_base), 0); | |
0d925ea0 | 2016 | /* PDP values well be assigned later if needed */ |
0bc40be8 TU |
2017 | ASSIGN_CTX_REG(reg_state, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), |
2018 | 0); | |
2019 | ASSIGN_CTX_REG(reg_state, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), | |
2020 | 0); | |
2021 | ASSIGN_CTX_REG(reg_state, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), | |
2022 | 0); | |
2023 | ASSIGN_CTX_REG(reg_state, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), | |
2024 | 0); | |
2025 | ASSIGN_CTX_REG(reg_state, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), | |
2026 | 0); | |
2027 | ASSIGN_CTX_REG(reg_state, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), | |
2028 | 0); | |
2029 | ASSIGN_CTX_REG(reg_state, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), | |
2030 | 0); | |
2031 | ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), | |
2032 | 0); | |
d7b2633d | 2033 | |
34869776 | 2034 | if (ppgtt && USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) { |
2dba3239 MT |
2035 | /* 64b PPGTT (48bit canonical) |
2036 | * PDP0_DESCRIPTOR contains the base address to PML4 and | |
2037 | * other PDP Descriptors are ignored. | |
2038 | */ | |
2039 | ASSIGN_CTX_PML4(ppgtt, reg_state); | |
2dba3239 MT |
2040 | } |
2041 | ||
0bc40be8 | 2042 | if (engine->id == RCS) { |
8670d6f9 | 2043 | reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); |
0d925ea0 | 2044 | ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, |
c033666a | 2045 | make_rpcs(dev_priv)); |
8670d6f9 | 2046 | } |
a3aabe86 CW |
2047 | } |
2048 | ||
2049 | static int | |
2050 | populate_lr_context(struct i915_gem_context *ctx, | |
2051 | struct drm_i915_gem_object *ctx_obj, | |
2052 | struct intel_engine_cs *engine, | |
2053 | struct intel_ring *ring) | |
2054 | { | |
2055 | void *vaddr; | |
2056 | int ret; | |
2057 | ||
2058 | ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); | |
2059 | if (ret) { | |
2060 | DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); | |
2061 | return ret; | |
2062 | } | |
2063 | ||
2064 | vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB); | |
2065 | if (IS_ERR(vaddr)) { | |
2066 | ret = PTR_ERR(vaddr); | |
2067 | DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret); | |
2068 | return ret; | |
2069 | } | |
a4f5ea64 | 2070 | ctx_obj->mm.dirty = true; |
a3aabe86 CW |
2071 | |
2072 | /* The second page of the context object contains some fields which must | |
2073 | * be set up prior to the first execution. */ | |
2074 | ||
2075 | execlists_init_reg_state(vaddr + LRC_STATE_PN * PAGE_SIZE, | |
2076 | ctx, engine, ring); | |
8670d6f9 | 2077 | |
7d774cac | 2078 | i915_gem_object_unpin_map(ctx_obj); |
8670d6f9 OM |
2079 | |
2080 | return 0; | |
2081 | } | |
2082 | ||
c5d46ee2 DG |
2083 | /** |
2084 | * intel_lr_context_size() - return the size of the context for an engine | |
14bb2c11 | 2085 | * @engine: which engine to find the context size for |
c5d46ee2 DG |
2086 | * |
2087 | * Each engine may require a different amount of space for a context image, | |
2088 | * so when allocating (or copying) an image, this function can be used to | |
2089 | * find the right size for the specific engine. | |
2090 | * | |
2091 | * Return: size (in bytes) of an engine-specific context image | |
2092 | * | |
2093 | * Note: this size includes the HWSP, which is part of the context image | |
2094 | * in LRC mode, but does not include the "shared data page" used with | |
2095 | * GuC submission. The caller should account for this if using the GuC. | |
2096 | */ | |
0bc40be8 | 2097 | uint32_t intel_lr_context_size(struct intel_engine_cs *engine) |
8c857917 OM |
2098 | { |
2099 | int ret = 0; | |
2100 | ||
c033666a | 2101 | WARN_ON(INTEL_GEN(engine->i915) < 8); |
8c857917 | 2102 | |
0bc40be8 | 2103 | switch (engine->id) { |
8c857917 | 2104 | case RCS: |
c033666a | 2105 | if (INTEL_GEN(engine->i915) >= 9) |
468c6816 MN |
2106 | ret = GEN9_LR_CONTEXT_RENDER_SIZE; |
2107 | else | |
2108 | ret = GEN8_LR_CONTEXT_RENDER_SIZE; | |
8c857917 OM |
2109 | break; |
2110 | case VCS: | |
2111 | case BCS: | |
2112 | case VECS: | |
2113 | case VCS2: | |
2114 | ret = GEN8_LR_CONTEXT_OTHER_SIZE; | |
2115 | break; | |
2116 | } | |
2117 | ||
2118 | return ret; | |
ede7d42b OM |
2119 | } |
2120 | ||
e2efd130 | 2121 | static int execlists_context_deferred_alloc(struct i915_gem_context *ctx, |
978f1e09 | 2122 | struct intel_engine_cs *engine) |
ede7d42b | 2123 | { |
8c857917 | 2124 | struct drm_i915_gem_object *ctx_obj; |
9021ad03 | 2125 | struct intel_context *ce = &ctx->engine[engine->id]; |
bf3783e5 | 2126 | struct i915_vma *vma; |
8c857917 | 2127 | uint32_t context_size; |
7e37f889 | 2128 | struct intel_ring *ring; |
8c857917 OM |
2129 | int ret; |
2130 | ||
9021ad03 | 2131 | WARN_ON(ce->state); |
ede7d42b | 2132 | |
f51455d4 CW |
2133 | context_size = round_up(intel_lr_context_size(engine), |
2134 | I915_GTT_PAGE_SIZE); | |
8c857917 | 2135 | |
d1675198 AD |
2136 | /* One extra page as the sharing data between driver and GuC */ |
2137 | context_size += PAGE_SIZE * LRC_PPHWSP_PN; | |
2138 | ||
12d79d78 | 2139 | ctx_obj = i915_gem_object_create(ctx->i915, context_size); |
fe3db79b | 2140 | if (IS_ERR(ctx_obj)) { |
3126a660 | 2141 | DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n"); |
fe3db79b | 2142 | return PTR_ERR(ctx_obj); |
8c857917 OM |
2143 | } |
2144 | ||
a01cb37a | 2145 | vma = i915_vma_instance(ctx_obj, &ctx->i915->ggtt.base, NULL); |
bf3783e5 CW |
2146 | if (IS_ERR(vma)) { |
2147 | ret = PTR_ERR(vma); | |
2148 | goto error_deref_obj; | |
2149 | } | |
2150 | ||
7e37f889 | 2151 | ring = intel_engine_create_ring(engine, ctx->ring_size); |
dca33ecc CW |
2152 | if (IS_ERR(ring)) { |
2153 | ret = PTR_ERR(ring); | |
e84fe803 | 2154 | goto error_deref_obj; |
8670d6f9 OM |
2155 | } |
2156 | ||
dca33ecc | 2157 | ret = populate_lr_context(ctx, ctx_obj, engine, ring); |
8670d6f9 OM |
2158 | if (ret) { |
2159 | DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); | |
dca33ecc | 2160 | goto error_ring_free; |
84c2377f OM |
2161 | } |
2162 | ||
dca33ecc | 2163 | ce->ring = ring; |
bf3783e5 | 2164 | ce->state = vma; |
9021ad03 | 2165 | ce->initialised = engine->init_context == NULL; |
ede7d42b OM |
2166 | |
2167 | return 0; | |
8670d6f9 | 2168 | |
dca33ecc | 2169 | error_ring_free: |
7e37f889 | 2170 | intel_ring_free(ring); |
e84fe803 | 2171 | error_deref_obj: |
f8c417cd | 2172 | i915_gem_object_put(ctx_obj); |
8670d6f9 | 2173 | return ret; |
ede7d42b | 2174 | } |
3e5b6f05 | 2175 | |
821ed7df | 2176 | void intel_lr_context_resume(struct drm_i915_private *dev_priv) |
3e5b6f05 | 2177 | { |
e2f80391 | 2178 | struct intel_engine_cs *engine; |
bafb2f7d | 2179 | struct i915_gem_context *ctx; |
3b3f1650 | 2180 | enum intel_engine_id id; |
bafb2f7d CW |
2181 | |
2182 | /* Because we emit WA_TAIL_DWORDS there may be a disparity | |
2183 | * between our bookkeeping in ce->ring->head and ce->ring->tail and | |
2184 | * that stored in context. As we only write new commands from | |
2185 | * ce->ring->tail onwards, everything before that is junk. If the GPU | |
2186 | * starts reading from its RING_HEAD from the context, it may try to | |
2187 | * execute that junk and die. | |
2188 | * | |
2189 | * So to avoid that we reset the context images upon resume. For | |
2190 | * simplicity, we just zero everything out. | |
2191 | */ | |
2192 | list_for_each_entry(ctx, &dev_priv->context_list, link) { | |
3b3f1650 | 2193 | for_each_engine(engine, dev_priv, id) { |
bafb2f7d CW |
2194 | struct intel_context *ce = &ctx->engine[engine->id]; |
2195 | u32 *reg; | |
3e5b6f05 | 2196 | |
bafb2f7d CW |
2197 | if (!ce->state) |
2198 | continue; | |
7d774cac | 2199 | |
bafb2f7d CW |
2200 | reg = i915_gem_object_pin_map(ce->state->obj, |
2201 | I915_MAP_WB); | |
2202 | if (WARN_ON(IS_ERR(reg))) | |
2203 | continue; | |
3e5b6f05 | 2204 | |
bafb2f7d CW |
2205 | reg += LRC_STATE_PN * PAGE_SIZE / sizeof(*reg); |
2206 | reg[CTX_RING_HEAD+1] = 0; | |
2207 | reg[CTX_RING_TAIL+1] = 0; | |
3e5b6f05 | 2208 | |
a4f5ea64 | 2209 | ce->state->obj->mm.dirty = true; |
bafb2f7d | 2210 | i915_gem_object_unpin_map(ce->state->obj); |
3e5b6f05 | 2211 | |
bafb2f7d CW |
2212 | ce->ring->head = ce->ring->tail = 0; |
2213 | ce->ring->last_retired_head = -1; | |
2214 | intel_ring_update_space(ce->ring); | |
2215 | } | |
3e5b6f05 TD |
2216 | } |
2217 | } |