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b20385f1 OM |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * Michel Thierry <michel.thierry@intel.com> | |
26 | * Thomas Daniel <thomas.daniel@intel.com> | |
27 | * Oscar Mateo <oscar.mateo@intel.com> | |
28 | * | |
29 | */ | |
30 | ||
73e4d07f OM |
31 | /** |
32 | * DOC: Logical Rings, Logical Ring Contexts and Execlists | |
33 | * | |
34 | * Motivation: | |
b20385f1 OM |
35 | * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". |
36 | * These expanded contexts enable a number of new abilities, especially | |
37 | * "Execlists" (also implemented in this file). | |
38 | * | |
73e4d07f OM |
39 | * One of the main differences with the legacy HW contexts is that logical |
40 | * ring contexts incorporate many more things to the context's state, like | |
41 | * PDPs or ringbuffer control registers: | |
42 | * | |
43 | * The reason why PDPs are included in the context is straightforward: as | |
44 | * PPGTTs (per-process GTTs) are actually per-context, having the PDPs | |
45 | * contained there mean you don't need to do a ppgtt->switch_mm yourself, | |
46 | * instead, the GPU will do it for you on the context switch. | |
47 | * | |
48 | * But, what about the ringbuffer control registers (head, tail, etc..)? | |
49 | * shouldn't we just need a set of those per engine command streamer? This is | |
50 | * where the name "Logical Rings" starts to make sense: by virtualizing the | |
51 | * rings, the engine cs shifts to a new "ring buffer" with every context | |
52 | * switch. When you want to submit a workload to the GPU you: A) choose your | |
53 | * context, B) find its appropriate virtualized ring, C) write commands to it | |
54 | * and then, finally, D) tell the GPU to switch to that context. | |
55 | * | |
56 | * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch | |
57 | * to a contexts is via a context execution list, ergo "Execlists". | |
58 | * | |
59 | * LRC implementation: | |
60 | * Regarding the creation of contexts, we have: | |
61 | * | |
62 | * - One global default context. | |
63 | * - One local default context for each opened fd. | |
64 | * - One local extra context for each context create ioctl call. | |
65 | * | |
66 | * Now that ringbuffers belong per-context (and not per-engine, like before) | |
67 | * and that contexts are uniquely tied to a given engine (and not reusable, | |
68 | * like before) we need: | |
69 | * | |
70 | * - One ringbuffer per-engine inside each context. | |
71 | * - One backing object per-engine inside each context. | |
72 | * | |
73 | * The global default context starts its life with these new objects fully | |
74 | * allocated and populated. The local default context for each opened fd is | |
75 | * more complex, because we don't know at creation time which engine is going | |
76 | * to use them. To handle this, we have implemented a deferred creation of LR | |
77 | * contexts: | |
78 | * | |
79 | * The local context starts its life as a hollow or blank holder, that only | |
80 | * gets populated for a given engine once we receive an execbuffer. If later | |
81 | * on we receive another execbuffer ioctl for the same context but a different | |
82 | * engine, we allocate/populate a new ringbuffer and context backing object and | |
83 | * so on. | |
84 | * | |
85 | * Finally, regarding local contexts created using the ioctl call: as they are | |
86 | * only allowed with the render ring, we can allocate & populate them right | |
87 | * away (no need to defer anything, at least for now). | |
88 | * | |
89 | * Execlists implementation: | |
b20385f1 OM |
90 | * Execlists are the new method by which, on gen8+ hardware, workloads are |
91 | * submitted for execution (as opposed to the legacy, ringbuffer-based, method). | |
73e4d07f OM |
92 | * This method works as follows: |
93 | * | |
94 | * When a request is committed, its commands (the BB start and any leading or | |
95 | * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer | |
96 | * for the appropriate context. The tail pointer in the hardware context is not | |
97 | * updated at this time, but instead, kept by the driver in the ringbuffer | |
98 | * structure. A structure representing this request is added to a request queue | |
99 | * for the appropriate engine: this structure contains a copy of the context's | |
100 | * tail after the request was written to the ring buffer and a pointer to the | |
101 | * context itself. | |
102 | * | |
103 | * If the engine's request queue was empty before the request was added, the | |
104 | * queue is processed immediately. Otherwise the queue will be processed during | |
105 | * a context switch interrupt. In any case, elements on the queue will get sent | |
106 | * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a | |
107 | * globally unique 20-bits submission ID. | |
108 | * | |
109 | * When execution of a request completes, the GPU updates the context status | |
110 | * buffer with a context complete event and generates a context switch interrupt. | |
111 | * During the interrupt handling, the driver examines the events in the buffer: | |
112 | * for each context complete event, if the announced ID matches that on the head | |
113 | * of the request queue, then that request is retired and removed from the queue. | |
114 | * | |
115 | * After processing, if any requests were retired and the queue is not empty | |
116 | * then a new execution list can be submitted. The two requests at the front of | |
117 | * the queue are next to be submitted but since a context may not occur twice in | |
118 | * an execution list, if subsequent requests have the same ID as the first then | |
119 | * the two requests must be combined. This is done simply by discarding requests | |
120 | * at the head of the queue until either only one requests is left (in which case | |
121 | * we use a NULL second context) or the first two requests have unique IDs. | |
122 | * | |
123 | * By always executing the first two requests in the queue the driver ensures | |
124 | * that the GPU is kept as busy as possible. In the case where a single context | |
125 | * completes but a second context is still executing, the request for this second | |
126 | * context will be at the head of the queue when we remove the first one. This | |
127 | * request will then be resubmitted along with a new request for a different context, | |
128 | * which will cause the hardware to continue executing the second request and queue | |
129 | * the new request (the GPU detects the condition of a context getting preempted | |
130 | * with the same context and optimizes the context switch flow by not doing | |
131 | * preemption, but just sampling the new tail pointer). | |
132 | * | |
b20385f1 | 133 | */ |
27af5eea | 134 | #include <linux/interrupt.h> |
b20385f1 OM |
135 | |
136 | #include <drm/drmP.h> | |
137 | #include <drm/i915_drm.h> | |
138 | #include "i915_drv.h" | |
3bbaba0c | 139 | #include "intel_mocs.h" |
127f1003 | 140 | |
e981e7b1 TD |
141 | #define RING_EXECLIST_QFULL (1 << 0x2) |
142 | #define RING_EXECLIST1_VALID (1 << 0x3) | |
143 | #define RING_EXECLIST0_VALID (1 << 0x4) | |
144 | #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) | |
145 | #define RING_EXECLIST1_ACTIVE (1 << 0x11) | |
146 | #define RING_EXECLIST0_ACTIVE (1 << 0x12) | |
147 | ||
148 | #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) | |
149 | #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) | |
150 | #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) | |
151 | #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) | |
152 | #define GEN8_CTX_STATUS_COMPLETE (1 << 4) | |
153 | #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) | |
8670d6f9 | 154 | |
70c2a24d CW |
155 | #define GEN8_CTX_STATUS_COMPLETED_MASK \ |
156 | (GEN8_CTX_STATUS_ACTIVE_IDLE | \ | |
157 | GEN8_CTX_STATUS_PREEMPTED | \ | |
158 | GEN8_CTX_STATUS_ELEMENT_SWITCH) | |
159 | ||
8670d6f9 OM |
160 | #define CTX_LRI_HEADER_0 0x01 |
161 | #define CTX_CONTEXT_CONTROL 0x02 | |
162 | #define CTX_RING_HEAD 0x04 | |
163 | #define CTX_RING_TAIL 0x06 | |
164 | #define CTX_RING_BUFFER_START 0x08 | |
165 | #define CTX_RING_BUFFER_CONTROL 0x0a | |
166 | #define CTX_BB_HEAD_U 0x0c | |
167 | #define CTX_BB_HEAD_L 0x0e | |
168 | #define CTX_BB_STATE 0x10 | |
169 | #define CTX_SECOND_BB_HEAD_U 0x12 | |
170 | #define CTX_SECOND_BB_HEAD_L 0x14 | |
171 | #define CTX_SECOND_BB_STATE 0x16 | |
172 | #define CTX_BB_PER_CTX_PTR 0x18 | |
173 | #define CTX_RCS_INDIRECT_CTX 0x1a | |
174 | #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c | |
175 | #define CTX_LRI_HEADER_1 0x21 | |
176 | #define CTX_CTX_TIMESTAMP 0x22 | |
177 | #define CTX_PDP3_UDW 0x24 | |
178 | #define CTX_PDP3_LDW 0x26 | |
179 | #define CTX_PDP2_UDW 0x28 | |
180 | #define CTX_PDP2_LDW 0x2a | |
181 | #define CTX_PDP1_UDW 0x2c | |
182 | #define CTX_PDP1_LDW 0x2e | |
183 | #define CTX_PDP0_UDW 0x30 | |
184 | #define CTX_PDP0_LDW 0x32 | |
185 | #define CTX_LRI_HEADER_2 0x41 | |
186 | #define CTX_R_PWR_CLK_STATE 0x42 | |
187 | #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 | |
188 | ||
56e51bf0 | 189 | #define CTX_REG(reg_state, pos, reg, val) do { \ |
f0f59a00 | 190 | (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \ |
0d925ea0 VS |
191 | (reg_state)[(pos)+1] = (val); \ |
192 | } while (0) | |
193 | ||
194 | #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \ | |
d852c7bf | 195 | const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \ |
e5815a2e MT |
196 | reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \ |
197 | reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \ | |
9244a817 | 198 | } while (0) |
e5815a2e | 199 | |
9244a817 | 200 | #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \ |
2dba3239 MT |
201 | reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \ |
202 | reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \ | |
9244a817 | 203 | } while (0) |
2dba3239 | 204 | |
71562919 MT |
205 | #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 |
206 | #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26 | |
7bd0a2c6 | 207 | #define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x19 |
84b790f8 | 208 | |
0e93cdd4 CW |
209 | /* Typical size of the average request (2 pipecontrols and a MI_BB) */ |
210 | #define EXECLISTS_REQUEST_SIZE 64 /* bytes */ | |
211 | ||
a3aabe86 CW |
212 | #define WA_TAIL_DWORDS 2 |
213 | ||
e2efd130 | 214 | static int execlists_context_deferred_alloc(struct i915_gem_context *ctx, |
978f1e09 | 215 | struct intel_engine_cs *engine); |
a3aabe86 CW |
216 | static void execlists_init_reg_state(u32 *reg_state, |
217 | struct i915_gem_context *ctx, | |
218 | struct intel_engine_cs *engine, | |
219 | struct intel_ring *ring); | |
7ba717cf | 220 | |
73e4d07f OM |
221 | /** |
222 | * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists | |
14bb2c11 | 223 | * @dev_priv: i915 device private |
73e4d07f OM |
224 | * @enable_execlists: value of i915.enable_execlists module parameter. |
225 | * | |
226 | * Only certain platforms support Execlists (the prerequisites being | |
27401d12 | 227 | * support for Logical Ring Contexts and Aliasing PPGTT or better). |
73e4d07f OM |
228 | * |
229 | * Return: 1 if Execlists is supported and has to be enabled. | |
230 | */ | |
c033666a | 231 | int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv, int enable_execlists) |
127f1003 | 232 | { |
a0bd6c31 ZL |
233 | /* On platforms with execlist available, vGPU will only |
234 | * support execlist mode, no ring buffer mode. | |
235 | */ | |
c033666a | 236 | if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && intel_vgpu_active(dev_priv)) |
a0bd6c31 ZL |
237 | return 1; |
238 | ||
c033666a | 239 | if (INTEL_GEN(dev_priv) >= 9) |
70ee45e1 DL |
240 | return 1; |
241 | ||
127f1003 OM |
242 | if (enable_execlists == 0) |
243 | return 0; | |
244 | ||
5a21b665 DV |
245 | if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && |
246 | USES_PPGTT(dev_priv) && | |
247 | i915.use_mmio_flip >= 0) | |
127f1003 OM |
248 | return 1; |
249 | ||
250 | return 0; | |
251 | } | |
ede7d42b | 252 | |
73e4d07f | 253 | /** |
ca82580c TU |
254 | * intel_lr_context_descriptor_update() - calculate & cache the descriptor |
255 | * descriptor for a pinned context | |
ca82580c | 256 | * @ctx: Context to work on |
9021ad03 | 257 | * @engine: Engine the descriptor will be used with |
73e4d07f | 258 | * |
ca82580c TU |
259 | * The context descriptor encodes various attributes of a context, |
260 | * including its GTT address and some flags. Because it's fairly | |
261 | * expensive to calculate, we'll just do it once and cache the result, | |
262 | * which remains valid until the context is unpinned. | |
263 | * | |
6e5248b5 DV |
264 | * This is what a descriptor looks like, from LSB to MSB:: |
265 | * | |
2355cf08 | 266 | * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template) |
6e5248b5 DV |
267 | * bits 12-31: LRCA, GTT address of (the HWSP of) this context |
268 | * bits 32-52: ctx ID, a globally unique tag | |
269 | * bits 53-54: mbz, reserved for use by hardware | |
270 | * bits 55-63: group ID, currently unused and set to 0 | |
73e4d07f | 271 | */ |
ca82580c | 272 | static void |
e2efd130 | 273 | intel_lr_context_descriptor_update(struct i915_gem_context *ctx, |
0bc40be8 | 274 | struct intel_engine_cs *engine) |
84b790f8 | 275 | { |
9021ad03 | 276 | struct intel_context *ce = &ctx->engine[engine->id]; |
7069b144 | 277 | u64 desc; |
84b790f8 | 278 | |
7069b144 | 279 | BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH)); |
84b790f8 | 280 | |
2355cf08 | 281 | desc = ctx->desc_template; /* bits 0-11 */ |
0b29c75a | 282 | desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE; |
9021ad03 | 283 | /* bits 12-31 */ |
7069b144 | 284 | desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */ |
5af05fef | 285 | |
9021ad03 | 286 | ce->lrc_desc = desc; |
5af05fef MT |
287 | } |
288 | ||
bbd6c47e CW |
289 | static inline void |
290 | execlists_context_status_change(struct drm_i915_gem_request *rq, | |
291 | unsigned long status) | |
84b790f8 | 292 | { |
bbd6c47e CW |
293 | /* |
294 | * Only used when GVT-g is enabled now. When GVT-g is disabled, | |
295 | * The compiler should eliminate this function as dead-code. | |
296 | */ | |
297 | if (!IS_ENABLED(CONFIG_DRM_I915_GVT)) | |
298 | return; | |
6daccb0b | 299 | |
3fc03069 CD |
300 | atomic_notifier_call_chain(&rq->engine->context_status_notifier, |
301 | status, rq); | |
84b790f8 BW |
302 | } |
303 | ||
c6a2ac71 TU |
304 | static void |
305 | execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state) | |
306 | { | |
307 | ASSIGN_CTX_PDP(ppgtt, reg_state, 3); | |
308 | ASSIGN_CTX_PDP(ppgtt, reg_state, 2); | |
309 | ASSIGN_CTX_PDP(ppgtt, reg_state, 1); | |
310 | ASSIGN_CTX_PDP(ppgtt, reg_state, 0); | |
311 | } | |
312 | ||
70c2a24d | 313 | static u64 execlists_update_context(struct drm_i915_gem_request *rq) |
ae1250b9 | 314 | { |
70c2a24d | 315 | struct intel_context *ce = &rq->ctx->engine[rq->engine->id]; |
04da811b ZW |
316 | struct i915_hw_ppgtt *ppgtt = |
317 | rq->ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt; | |
70c2a24d | 318 | u32 *reg_state = ce->lrc_reg_state; |
ae1250b9 | 319 | |
e6ba9992 | 320 | reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail); |
ae1250b9 | 321 | |
c6a2ac71 TU |
322 | /* True 32b PPGTT with dynamic page allocation: update PDP |
323 | * registers and point the unallocated PDPs to scratch page. | |
324 | * PML4 is allocated during ppgtt init, so this is not needed | |
325 | * in 48-bit mode. | |
326 | */ | |
949e8ab3 | 327 | if (ppgtt && !i915_vm_is_48bit(&ppgtt->base)) |
c6a2ac71 | 328 | execlists_update_context_pdps(ppgtt, reg_state); |
70c2a24d CW |
329 | |
330 | return ce->lrc_desc; | |
ae1250b9 OM |
331 | } |
332 | ||
70c2a24d | 333 | static void execlists_submit_ports(struct intel_engine_cs *engine) |
bbd6c47e | 334 | { |
70c2a24d | 335 | struct execlist_port *port = engine->execlist_port; |
bbd6c47e | 336 | u32 __iomem *elsp = |
77f0d0e9 CW |
337 | engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine)); |
338 | unsigned int n; | |
bbd6c47e | 339 | |
77f0d0e9 CW |
340 | for (n = ARRAY_SIZE(engine->execlist_port); n--; ) { |
341 | struct drm_i915_gem_request *rq; | |
342 | unsigned int count; | |
343 | u64 desc; | |
344 | ||
345 | rq = port_unpack(&port[n], &count); | |
346 | if (rq) { | |
347 | GEM_BUG_ON(count > !n); | |
348 | if (!count++) | |
349 | execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN); | |
350 | port_set(&port[n], port_pack(rq, count)); | |
351 | desc = execlists_update_context(rq); | |
352 | GEM_DEBUG_EXEC(port[n].context_id = upper_32_bits(desc)); | |
353 | } else { | |
354 | GEM_BUG_ON(!n); | |
355 | desc = 0; | |
356 | } | |
bbd6c47e | 357 | |
77f0d0e9 CW |
358 | writel(upper_32_bits(desc), elsp); |
359 | writel(lower_32_bits(desc), elsp); | |
360 | } | |
bbd6c47e CW |
361 | } |
362 | ||
70c2a24d | 363 | static bool ctx_single_port_submission(const struct i915_gem_context *ctx) |
84b790f8 | 364 | { |
70c2a24d | 365 | return (IS_ENABLED(CONFIG_DRM_I915_GVT) && |
6095868a | 366 | i915_gem_context_force_single_submission(ctx)); |
70c2a24d | 367 | } |
84b790f8 | 368 | |
70c2a24d CW |
369 | static bool can_merge_ctx(const struct i915_gem_context *prev, |
370 | const struct i915_gem_context *next) | |
371 | { | |
372 | if (prev != next) | |
373 | return false; | |
26720ab9 | 374 | |
70c2a24d CW |
375 | if (ctx_single_port_submission(prev)) |
376 | return false; | |
26720ab9 | 377 | |
70c2a24d | 378 | return true; |
84b790f8 BW |
379 | } |
380 | ||
77f0d0e9 CW |
381 | static void port_assign(struct execlist_port *port, |
382 | struct drm_i915_gem_request *rq) | |
383 | { | |
384 | GEM_BUG_ON(rq == port_request(port)); | |
385 | ||
386 | if (port_isset(port)) | |
387 | i915_gem_request_put(port_request(port)); | |
388 | ||
389 | port_set(port, port_pack(i915_gem_request_get(rq), port_count(port))); | |
390 | } | |
391 | ||
70c2a24d | 392 | static void execlists_dequeue(struct intel_engine_cs *engine) |
acdd884a | 393 | { |
20311bd3 | 394 | struct drm_i915_gem_request *last; |
70c2a24d | 395 | struct execlist_port *port = engine->execlist_port; |
20311bd3 | 396 | struct rb_node *rb; |
70c2a24d CW |
397 | bool submit = false; |
398 | ||
77f0d0e9 | 399 | last = port_request(port); |
70c2a24d CW |
400 | if (last) |
401 | /* WaIdleLiteRestore:bdw,skl | |
402 | * Apply the wa NOOPs to prevent ring:HEAD == req:TAIL | |
9b81d556 | 403 | * as we resubmit the request. See gen8_emit_breadcrumb() |
70c2a24d CW |
404 | * for where we prepare the padding after the end of the |
405 | * request. | |
406 | */ | |
407 | last->tail = last->wa_tail; | |
e981e7b1 | 408 | |
77f0d0e9 | 409 | GEM_BUG_ON(port_isset(&port[1])); |
acdd884a | 410 | |
70c2a24d CW |
411 | /* Hardware submission is through 2 ports. Conceptually each port |
412 | * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is | |
413 | * static for a context, and unique to each, so we only execute | |
414 | * requests belonging to a single context from each ring. RING_HEAD | |
415 | * is maintained by the CS in the context image, it marks the place | |
416 | * where it got up to last time, and through RING_TAIL we tell the CS | |
417 | * where we want to execute up to this time. | |
418 | * | |
419 | * In this list the requests are in order of execution. Consecutive | |
420 | * requests from the same context are adjacent in the ringbuffer. We | |
421 | * can combine these requests into a single RING_TAIL update: | |
422 | * | |
423 | * RING_HEAD...req1...req2 | |
424 | * ^- RING_TAIL | |
425 | * since to execute req2 the CS must first execute req1. | |
426 | * | |
427 | * Our goal then is to point each port to the end of a consecutive | |
428 | * sequence of requests as being the most optimal (fewest wake ups | |
429 | * and context switches) submission. | |
779949f4 | 430 | */ |
acdd884a | 431 | |
9f7886d0 | 432 | spin_lock_irq(&engine->timeline->lock); |
20311bd3 | 433 | rb = engine->execlist_first; |
6c067579 | 434 | GEM_BUG_ON(rb_first(&engine->execlist_queue) != rb); |
20311bd3 | 435 | while (rb) { |
6c067579 CW |
436 | struct i915_priolist *p = rb_entry(rb, typeof(*p), node); |
437 | struct drm_i915_gem_request *rq, *rn; | |
438 | ||
439 | list_for_each_entry_safe(rq, rn, &p->requests, priotree.link) { | |
440 | /* | |
441 | * Can we combine this request with the current port? | |
442 | * It has to be the same context/ringbuffer and not | |
443 | * have any exceptions (e.g. GVT saying never to | |
444 | * combine contexts). | |
445 | * | |
446 | * If we can combine the requests, we can execute both | |
447 | * by updating the RING_TAIL to point to the end of the | |
448 | * second request, and so we never need to tell the | |
449 | * hardware about the first. | |
70c2a24d | 450 | */ |
6c067579 CW |
451 | if (last && !can_merge_ctx(rq->ctx, last->ctx)) { |
452 | /* | |
453 | * If we are on the second port and cannot | |
454 | * combine this request with the last, then we | |
455 | * are done. | |
456 | */ | |
457 | if (port != engine->execlist_port) { | |
458 | __list_del_many(&p->requests, | |
459 | &rq->priotree.link); | |
460 | goto done; | |
461 | } | |
462 | ||
463 | /* | |
464 | * If GVT overrides us we only ever submit | |
465 | * port[0], leaving port[1] empty. Note that we | |
466 | * also have to be careful that we don't queue | |
467 | * the same context (even though a different | |
468 | * request) to the second port. | |
469 | */ | |
470 | if (ctx_single_port_submission(last->ctx) || | |
471 | ctx_single_port_submission(rq->ctx)) { | |
472 | __list_del_many(&p->requests, | |
473 | &rq->priotree.link); | |
474 | goto done; | |
475 | } | |
476 | ||
477 | GEM_BUG_ON(last->ctx == rq->ctx); | |
478 | ||
479 | if (submit) | |
480 | port_assign(port, last); | |
481 | port++; | |
482 | } | |
70c2a24d | 483 | |
6c067579 CW |
484 | INIT_LIST_HEAD(&rq->priotree.link); |
485 | rq->priotree.priority = INT_MAX; | |
70c2a24d | 486 | |
6c067579 CW |
487 | __i915_gem_request_submit(rq); |
488 | trace_i915_gem_request_in(rq, port_index(port, engine)); | |
489 | last = rq; | |
490 | submit = true; | |
70c2a24d | 491 | } |
d55ac5bf | 492 | |
20311bd3 | 493 | rb = rb_next(rb); |
6c067579 CW |
494 | rb_erase(&p->node, &engine->execlist_queue); |
495 | INIT_LIST_HEAD(&p->requests); | |
496 | if (p->priority != I915_PRIORITY_NORMAL) | |
c5cf9a91 | 497 | kmem_cache_free(engine->i915->priorities, p); |
70c2a24d | 498 | } |
6c067579 CW |
499 | done: |
500 | engine->execlist_first = rb; | |
501 | if (submit) | |
77f0d0e9 | 502 | port_assign(port, last); |
9f7886d0 | 503 | spin_unlock_irq(&engine->timeline->lock); |
53292cdb | 504 | |
70c2a24d CW |
505 | if (submit) |
506 | execlists_submit_ports(engine); | |
acdd884a MT |
507 | } |
508 | ||
27a5f61b CW |
509 | static void execlists_cancel_requests(struct intel_engine_cs *engine) |
510 | { | |
511 | struct execlist_port *port = engine->execlist_port; | |
512 | struct drm_i915_gem_request *rq, *rn; | |
513 | struct rb_node *rb; | |
514 | unsigned long flags; | |
515 | unsigned long n; | |
516 | ||
517 | spin_lock_irqsave(&engine->timeline->lock, flags); | |
518 | ||
519 | /* Cancel the requests on the HW and clear the ELSP tracker. */ | |
520 | for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++) | |
521 | i915_gem_request_put(port_request(&port[n])); | |
522 | memset(engine->execlist_port, 0, sizeof(engine->execlist_port)); | |
523 | ||
524 | /* Mark all executing requests as skipped. */ | |
525 | list_for_each_entry(rq, &engine->timeline->requests, link) { | |
526 | GEM_BUG_ON(!rq->global_seqno); | |
527 | if (!i915_gem_request_completed(rq)) | |
528 | dma_fence_set_error(&rq->fence, -EIO); | |
529 | } | |
530 | ||
531 | /* Flush the queued requests to the timeline list (for retiring). */ | |
532 | rb = engine->execlist_first; | |
533 | while (rb) { | |
534 | struct i915_priolist *p = rb_entry(rb, typeof(*p), node); | |
535 | ||
536 | list_for_each_entry_safe(rq, rn, &p->requests, priotree.link) { | |
537 | INIT_LIST_HEAD(&rq->priotree.link); | |
538 | rq->priotree.priority = INT_MAX; | |
539 | ||
540 | dma_fence_set_error(&rq->fence, -EIO); | |
541 | __i915_gem_request_submit(rq); | |
542 | } | |
543 | ||
544 | rb = rb_next(rb); | |
545 | rb_erase(&p->node, &engine->execlist_queue); | |
546 | INIT_LIST_HEAD(&p->requests); | |
547 | if (p->priority != I915_PRIORITY_NORMAL) | |
548 | kmem_cache_free(engine->i915->priorities, p); | |
549 | } | |
550 | ||
551 | /* Remaining _unready_ requests will be nop'ed when submitted */ | |
552 | ||
553 | engine->execlist_queue = RB_ROOT; | |
554 | engine->execlist_first = NULL; | |
555 | GEM_BUG_ON(port_isset(&port[0])); | |
556 | ||
557 | /* | |
558 | * The port is checked prior to scheduling a tasklet, but | |
559 | * just in case we have suspended the tasklet to do the | |
560 | * wedging make sure that when it wakes, it decides there | |
561 | * is no work to do by clearing the irq_posted bit. | |
562 | */ | |
563 | clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); | |
564 | ||
565 | spin_unlock_irqrestore(&engine->timeline->lock, flags); | |
566 | } | |
567 | ||
816ee798 | 568 | static bool execlists_elsp_ready(const struct intel_engine_cs *engine) |
91a41032 | 569 | { |
816ee798 | 570 | const struct execlist_port *port = engine->execlist_port; |
91a41032 | 571 | |
77f0d0e9 | 572 | return port_count(&port[0]) + port_count(&port[1]) < 2; |
91a41032 BW |
573 | } |
574 | ||
6e5248b5 | 575 | /* |
73e4d07f OM |
576 | * Check the unread Context Status Buffers and manage the submission of new |
577 | * contexts to the ELSP accordingly. | |
578 | */ | |
27af5eea | 579 | static void intel_lrc_irq_handler(unsigned long data) |
e981e7b1 | 580 | { |
27af5eea | 581 | struct intel_engine_cs *engine = (struct intel_engine_cs *)data; |
70c2a24d | 582 | struct execlist_port *port = engine->execlist_port; |
c033666a | 583 | struct drm_i915_private *dev_priv = engine->i915; |
c6a2ac71 | 584 | |
48921260 CW |
585 | /* We can skip acquiring intel_runtime_pm_get() here as it was taken |
586 | * on our behalf by the request (see i915_gem_mark_busy()) and it will | |
587 | * not be relinquished until the device is idle (see | |
588 | * i915_gem_idle_work_handler()). As a precaution, we make sure | |
589 | * that all ELSP are drained i.e. we have processed the CSB, | |
590 | * before allowing ourselves to idle and calling intel_runtime_pm_put(). | |
591 | */ | |
592 | GEM_BUG_ON(!dev_priv->gt.awake); | |
593 | ||
3756685a | 594 | intel_uncore_forcewake_get(dev_priv, engine->fw_domains); |
c6a2ac71 | 595 | |
899f6204 CW |
596 | /* Prefer doing test_and_clear_bit() as a two stage operation to avoid |
597 | * imposing the cost of a locked atomic transaction when submitting a | |
598 | * new request (outside of the context-switch interrupt). | |
599 | */ | |
600 | while (test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) { | |
6d2cb5aa CW |
601 | /* The HWSP contains a (cacheable) mirror of the CSB */ |
602 | const u32 *buf = | |
603 | &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX]; | |
4af0d727 | 604 | unsigned int head, tail; |
70c2a24d | 605 | |
6d2cb5aa CW |
606 | /* However GVT emulation depends upon intercepting CSB mmio */ |
607 | if (unlikely(engine->csb_use_mmio)) { | |
608 | buf = (u32 * __force) | |
609 | (dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0))); | |
767a983a | 610 | engine->csb_head = -1; /* force mmio read of CSB ptrs */ |
6d2cb5aa CW |
611 | } |
612 | ||
2e70b8c6 CW |
613 | /* The write will be ordered by the uncached read (itself |
614 | * a memory barrier), so we do not need another in the form | |
615 | * of a locked instruction. The race between the interrupt | |
616 | * handler and the split test/clear is harmless as we order | |
617 | * our clear before the CSB read. If the interrupt arrived | |
618 | * first between the test and the clear, we read the updated | |
619 | * CSB and clear the bit. If the interrupt arrives as we read | |
620 | * the CSB or later (i.e. after we had cleared the bit) the bit | |
621 | * is set and we do a new loop. | |
622 | */ | |
623 | __clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); | |
767a983a CW |
624 | if (unlikely(engine->csb_head == -1)) { /* following a reset */ |
625 | head = readl(dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine))); | |
626 | tail = GEN8_CSB_WRITE_PTR(head); | |
627 | head = GEN8_CSB_READ_PTR(head); | |
628 | engine->csb_head = head; | |
629 | } else { | |
630 | const int write_idx = | |
631 | intel_hws_csb_write_index(dev_priv) - | |
632 | I915_HWS_CSB_BUF0_INDEX; | |
633 | ||
634 | head = engine->csb_head; | |
635 | tail = READ_ONCE(buf[write_idx]); | |
636 | } | |
4af0d727 | 637 | while (head != tail) { |
77f0d0e9 | 638 | struct drm_i915_gem_request *rq; |
4af0d727 | 639 | unsigned int status; |
77f0d0e9 | 640 | unsigned int count; |
4af0d727 CW |
641 | |
642 | if (++head == GEN8_CSB_ENTRIES) | |
643 | head = 0; | |
70c2a24d | 644 | |
2ffe80aa CW |
645 | /* We are flying near dragons again. |
646 | * | |
647 | * We hold a reference to the request in execlist_port[] | |
648 | * but no more than that. We are operating in softirq | |
649 | * context and so cannot hold any mutex or sleep. That | |
650 | * prevents us stopping the requests we are processing | |
651 | * in port[] from being retired simultaneously (the | |
652 | * breadcrumb will be complete before we see the | |
653 | * context-switch). As we only hold the reference to the | |
654 | * request, any pointer chasing underneath the request | |
655 | * is subject to a potential use-after-free. Thus we | |
656 | * store all of the bookkeeping within port[] as | |
657 | * required, and avoid using unguarded pointers beneath | |
658 | * request itself. The same applies to the atomic | |
659 | * status notifier. | |
660 | */ | |
661 | ||
6d2cb5aa | 662 | status = READ_ONCE(buf[2 * head]); /* maybe mmio! */ |
70c2a24d CW |
663 | if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK)) |
664 | continue; | |
665 | ||
86aa7e76 | 666 | /* Check the context/desc id for this event matches */ |
6d2cb5aa | 667 | GEM_DEBUG_BUG_ON(buf[2 * head + 1] != port->context_id); |
86aa7e76 | 668 | |
77f0d0e9 CW |
669 | rq = port_unpack(port, &count); |
670 | GEM_BUG_ON(count == 0); | |
671 | if (--count == 0) { | |
70c2a24d | 672 | GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED); |
77f0d0e9 CW |
673 | GEM_BUG_ON(!i915_gem_request_completed(rq)); |
674 | execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT); | |
675 | ||
676 | trace_i915_gem_request_out(rq); | |
677 | i915_gem_request_put(rq); | |
70c2a24d | 678 | |
70c2a24d CW |
679 | port[0] = port[1]; |
680 | memset(&port[1], 0, sizeof(port[1])); | |
77f0d0e9 CW |
681 | } else { |
682 | port_set(port, port_pack(rq, count)); | |
70c2a24d | 683 | } |
26720ab9 | 684 | |
77f0d0e9 CW |
685 | /* After the final element, the hw should be idle */ |
686 | GEM_BUG_ON(port_count(port) == 0 && | |
70c2a24d | 687 | !(status & GEN8_CTX_STATUS_ACTIVE_IDLE)); |
4af0d727 | 688 | } |
e1fee72c | 689 | |
767a983a CW |
690 | if (head != engine->csb_head) { |
691 | engine->csb_head = head; | |
692 | writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, head << 8), | |
693 | dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine))); | |
694 | } | |
e981e7b1 TD |
695 | } |
696 | ||
70c2a24d CW |
697 | if (execlists_elsp_ready(engine)) |
698 | execlists_dequeue(engine); | |
c6a2ac71 | 699 | |
70c2a24d | 700 | intel_uncore_forcewake_put(dev_priv, engine->fw_domains); |
e981e7b1 TD |
701 | } |
702 | ||
6c067579 CW |
703 | static bool |
704 | insert_request(struct intel_engine_cs *engine, | |
705 | struct i915_priotree *pt, | |
706 | int prio) | |
20311bd3 | 707 | { |
6c067579 CW |
708 | struct i915_priolist *p; |
709 | struct rb_node **parent, *rb; | |
20311bd3 CW |
710 | bool first = true; |
711 | ||
6c067579 CW |
712 | if (unlikely(engine->no_priolist)) |
713 | prio = I915_PRIORITY_NORMAL; | |
714 | ||
715 | find_priolist: | |
20311bd3 CW |
716 | /* most positive priority is scheduled first, equal priorities fifo */ |
717 | rb = NULL; | |
6c067579 CW |
718 | parent = &engine->execlist_queue.rb_node; |
719 | while (*parent) { | |
720 | rb = *parent; | |
721 | p = rb_entry(rb, typeof(*p), node); | |
722 | if (prio > p->priority) { | |
723 | parent = &rb->rb_left; | |
724 | } else if (prio < p->priority) { | |
725 | parent = &rb->rb_right; | |
20311bd3 | 726 | first = false; |
6c067579 CW |
727 | } else { |
728 | list_add_tail(&pt->link, &p->requests); | |
729 | return false; | |
20311bd3 CW |
730 | } |
731 | } | |
6c067579 CW |
732 | |
733 | if (prio == I915_PRIORITY_NORMAL) { | |
734 | p = &engine->default_priolist; | |
735 | } else { | |
c5cf9a91 | 736 | p = kmem_cache_alloc(engine->i915->priorities, GFP_ATOMIC); |
6c067579 CW |
737 | /* Convert an allocation failure to a priority bump */ |
738 | if (unlikely(!p)) { | |
739 | prio = I915_PRIORITY_NORMAL; /* recurses just once */ | |
740 | ||
741 | /* To maintain ordering with all rendering, after an | |
742 | * allocation failure we have to disable all scheduling. | |
743 | * Requests will then be executed in fifo, and schedule | |
744 | * will ensure that dependencies are emitted in fifo. | |
745 | * There will be still some reordering with existing | |
746 | * requests, so if userspace lied about their | |
747 | * dependencies that reordering may be visible. | |
748 | */ | |
749 | engine->no_priolist = true; | |
750 | goto find_priolist; | |
751 | } | |
752 | } | |
753 | ||
754 | p->priority = prio; | |
755 | rb_link_node(&p->node, rb, parent); | |
756 | rb_insert_color(&p->node, &engine->execlist_queue); | |
757 | ||
758 | INIT_LIST_HEAD(&p->requests); | |
759 | list_add_tail(&pt->link, &p->requests); | |
760 | ||
761 | if (first) | |
762 | engine->execlist_first = &p->node; | |
20311bd3 CW |
763 | |
764 | return first; | |
765 | } | |
766 | ||
f4ea6bdd | 767 | static void execlists_submit_request(struct drm_i915_gem_request *request) |
acdd884a | 768 | { |
4a570db5 | 769 | struct intel_engine_cs *engine = request->engine; |
5590af3e | 770 | unsigned long flags; |
acdd884a | 771 | |
663f71e7 CW |
772 | /* Will be called from irq-context when using foreign fences. */ |
773 | spin_lock_irqsave(&engine->timeline->lock, flags); | |
acdd884a | 774 | |
6c067579 CW |
775 | if (insert_request(engine, |
776 | &request->priotree, | |
777 | request->priotree.priority)) { | |
48ea2554 | 778 | if (execlists_elsp_ready(engine)) |
3833281a CW |
779 | tasklet_hi_schedule(&engine->irq_tasklet); |
780 | } | |
acdd884a | 781 | |
6c067579 CW |
782 | GEM_BUG_ON(!engine->execlist_first); |
783 | GEM_BUG_ON(list_empty(&request->priotree.link)); | |
784 | ||
663f71e7 | 785 | spin_unlock_irqrestore(&engine->timeline->lock, flags); |
acdd884a MT |
786 | } |
787 | ||
20311bd3 CW |
788 | static struct intel_engine_cs * |
789 | pt_lock_engine(struct i915_priotree *pt, struct intel_engine_cs *locked) | |
790 | { | |
a79a524e CW |
791 | struct intel_engine_cs *engine = |
792 | container_of(pt, struct drm_i915_gem_request, priotree)->engine; | |
793 | ||
794 | GEM_BUG_ON(!locked); | |
20311bd3 | 795 | |
20311bd3 | 796 | if (engine != locked) { |
a79a524e CW |
797 | spin_unlock(&locked->timeline->lock); |
798 | spin_lock(&engine->timeline->lock); | |
20311bd3 CW |
799 | } |
800 | ||
801 | return engine; | |
802 | } | |
803 | ||
804 | static void execlists_schedule(struct drm_i915_gem_request *request, int prio) | |
805 | { | |
a79a524e | 806 | struct intel_engine_cs *engine; |
20311bd3 CW |
807 | struct i915_dependency *dep, *p; |
808 | struct i915_dependency stack; | |
809 | LIST_HEAD(dfs); | |
810 | ||
811 | if (prio <= READ_ONCE(request->priotree.priority)) | |
812 | return; | |
813 | ||
70cd1476 CW |
814 | /* Need BKL in order to use the temporary link inside i915_dependency */ |
815 | lockdep_assert_held(&request->i915->drm.struct_mutex); | |
20311bd3 CW |
816 | |
817 | stack.signaler = &request->priotree; | |
818 | list_add(&stack.dfs_link, &dfs); | |
819 | ||
820 | /* Recursively bump all dependent priorities to match the new request. | |
821 | * | |
822 | * A naive approach would be to use recursion: | |
823 | * static void update_priorities(struct i915_priotree *pt, prio) { | |
824 | * list_for_each_entry(dep, &pt->signalers_list, signal_link) | |
825 | * update_priorities(dep->signal, prio) | |
826 | * insert_request(pt); | |
827 | * } | |
828 | * but that may have unlimited recursion depth and so runs a very | |
829 | * real risk of overunning the kernel stack. Instead, we build | |
830 | * a flat list of all dependencies starting with the current request. | |
831 | * As we walk the list of dependencies, we add all of its dependencies | |
832 | * to the end of the list (this may include an already visited | |
833 | * request) and continue to walk onwards onto the new dependencies. The | |
834 | * end result is a topological list of requests in reverse order, the | |
835 | * last element in the list is the request we must execute first. | |
836 | */ | |
837 | list_for_each_entry_safe(dep, p, &dfs, dfs_link) { | |
838 | struct i915_priotree *pt = dep->signaler; | |
839 | ||
a79a524e CW |
840 | /* Within an engine, there can be no cycle, but we may |
841 | * refer to the same dependency chain multiple times | |
842 | * (redundant dependencies are not eliminated) and across | |
843 | * engines. | |
844 | */ | |
845 | list_for_each_entry(p, &pt->signalers_list, signal_link) { | |
846 | GEM_BUG_ON(p->signaler->priority < pt->priority); | |
20311bd3 CW |
847 | if (prio > READ_ONCE(p->signaler->priority)) |
848 | list_move_tail(&p->dfs_link, &dfs); | |
a79a524e | 849 | } |
20311bd3 | 850 | |
0798cff4 | 851 | list_safe_reset_next(dep, p, dfs_link); |
20311bd3 CW |
852 | } |
853 | ||
349bdb68 CW |
854 | /* If we didn't need to bump any existing priorities, and we haven't |
855 | * yet submitted this request (i.e. there is no potential race with | |
856 | * execlists_submit_request()), we can set our own priority and skip | |
857 | * acquiring the engine locks. | |
858 | */ | |
859 | if (request->priotree.priority == INT_MIN) { | |
860 | GEM_BUG_ON(!list_empty(&request->priotree.link)); | |
861 | request->priotree.priority = prio; | |
862 | if (stack.dfs_link.next == stack.dfs_link.prev) | |
863 | return; | |
864 | __list_del_entry(&stack.dfs_link); | |
865 | } | |
866 | ||
a79a524e CW |
867 | engine = request->engine; |
868 | spin_lock_irq(&engine->timeline->lock); | |
869 | ||
20311bd3 CW |
870 | /* Fifo and depth-first replacement ensure our deps execute before us */ |
871 | list_for_each_entry_safe_reverse(dep, p, &dfs, dfs_link) { | |
872 | struct i915_priotree *pt = dep->signaler; | |
873 | ||
874 | INIT_LIST_HEAD(&dep->dfs_link); | |
875 | ||
876 | engine = pt_lock_engine(pt, engine); | |
877 | ||
878 | if (prio <= pt->priority) | |
879 | continue; | |
880 | ||
20311bd3 | 881 | pt->priority = prio; |
6c067579 CW |
882 | if (!list_empty(&pt->link)) { |
883 | __list_del_entry(&pt->link); | |
884 | insert_request(engine, pt, prio); | |
a79a524e | 885 | } |
20311bd3 CW |
886 | } |
887 | ||
a79a524e | 888 | spin_unlock_irq(&engine->timeline->lock); |
20311bd3 CW |
889 | |
890 | /* XXX Do we need to preempt to make room for us and our deps? */ | |
891 | } | |
892 | ||
266a240b CW |
893 | static struct intel_ring * |
894 | execlists_context_pin(struct intel_engine_cs *engine, | |
895 | struct i915_gem_context *ctx) | |
dcb4c12a | 896 | { |
9021ad03 | 897 | struct intel_context *ce = &ctx->engine[engine->id]; |
2947e408 | 898 | unsigned int flags; |
7d774cac | 899 | void *vaddr; |
ca82580c | 900 | int ret; |
dcb4c12a | 901 | |
91c8a326 | 902 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
ca82580c | 903 | |
266a240b CW |
904 | if (likely(ce->pin_count++)) |
905 | goto out; | |
a533b4ba | 906 | GEM_BUG_ON(!ce->pin_count); /* no overflow please! */ |
24f1d3cc | 907 | |
e8a9c58f CW |
908 | if (!ce->state) { |
909 | ret = execlists_context_deferred_alloc(ctx, engine); | |
910 | if (ret) | |
911 | goto err; | |
912 | } | |
56f6e0a7 | 913 | GEM_BUG_ON(!ce->state); |
e8a9c58f | 914 | |
72b72ae4 | 915 | flags = PIN_GLOBAL | PIN_HIGH; |
feef2a7c DCS |
916 | if (ctx->ggtt_offset_bias) |
917 | flags |= PIN_OFFSET_BIAS | ctx->ggtt_offset_bias; | |
2947e408 CW |
918 | |
919 | ret = i915_vma_pin(ce->state, 0, GEN8_LR_CONTEXT_ALIGN, flags); | |
e84fe803 | 920 | if (ret) |
24f1d3cc | 921 | goto err; |
7ba717cf | 922 | |
bf3783e5 | 923 | vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB); |
7d774cac TU |
924 | if (IS_ERR(vaddr)) { |
925 | ret = PTR_ERR(vaddr); | |
bf3783e5 | 926 | goto unpin_vma; |
82352e90 TU |
927 | } |
928 | ||
d822bb18 | 929 | ret = intel_ring_pin(ce->ring, ctx->i915, ctx->ggtt_offset_bias); |
e84fe803 | 930 | if (ret) |
7d774cac | 931 | goto unpin_map; |
d1675198 | 932 | |
0bc40be8 | 933 | intel_lr_context_descriptor_update(ctx, engine); |
9021ad03 | 934 | |
a3aabe86 CW |
935 | ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; |
936 | ce->lrc_reg_state[CTX_RING_BUFFER_START+1] = | |
bde13ebd | 937 | i915_ggtt_offset(ce->ring->vma); |
a3aabe86 | 938 | |
a4f5ea64 | 939 | ce->state->obj->mm.dirty = true; |
e93c28f3 | 940 | |
9a6feaf0 | 941 | i915_gem_context_get(ctx); |
266a240b CW |
942 | out: |
943 | return ce->ring; | |
7ba717cf | 944 | |
7d774cac | 945 | unpin_map: |
bf3783e5 CW |
946 | i915_gem_object_unpin_map(ce->state->obj); |
947 | unpin_vma: | |
948 | __i915_vma_unpin(ce->state); | |
24f1d3cc | 949 | err: |
9021ad03 | 950 | ce->pin_count = 0; |
266a240b | 951 | return ERR_PTR(ret); |
e84fe803 NH |
952 | } |
953 | ||
e8a9c58f CW |
954 | static void execlists_context_unpin(struct intel_engine_cs *engine, |
955 | struct i915_gem_context *ctx) | |
e84fe803 | 956 | { |
9021ad03 | 957 | struct intel_context *ce = &ctx->engine[engine->id]; |
e84fe803 | 958 | |
91c8a326 | 959 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
9021ad03 | 960 | GEM_BUG_ON(ce->pin_count == 0); |
321fe304 | 961 | |
9021ad03 | 962 | if (--ce->pin_count) |
24f1d3cc | 963 | return; |
e84fe803 | 964 | |
aad29fbb | 965 | intel_ring_unpin(ce->ring); |
dcb4c12a | 966 | |
bf3783e5 CW |
967 | i915_gem_object_unpin_map(ce->state->obj); |
968 | i915_vma_unpin(ce->state); | |
321fe304 | 969 | |
9a6feaf0 | 970 | i915_gem_context_put(ctx); |
dcb4c12a OM |
971 | } |
972 | ||
f73e7399 | 973 | static int execlists_request_alloc(struct drm_i915_gem_request *request) |
ef11c01d CW |
974 | { |
975 | struct intel_engine_cs *engine = request->engine; | |
976 | struct intel_context *ce = &request->ctx->engine[engine->id]; | |
73dec95e | 977 | u32 *cs; |
ef11c01d CW |
978 | int ret; |
979 | ||
e8a9c58f CW |
980 | GEM_BUG_ON(!ce->pin_count); |
981 | ||
ef11c01d CW |
982 | /* Flush enough space to reduce the likelihood of waiting after |
983 | * we start building the request - in which case we will just | |
984 | * have to repeat work. | |
985 | */ | |
986 | request->reserved_space += EXECLISTS_REQUEST_SIZE; | |
987 | ||
ef11c01d CW |
988 | if (i915.enable_guc_submission) { |
989 | /* | |
990 | * Check that the GuC has space for the request before | |
991 | * going any further, as the i915_add_request() call | |
992 | * later on mustn't fail ... | |
993 | */ | |
994 | ret = i915_guc_wq_reserve(request); | |
995 | if (ret) | |
e8a9c58f | 996 | goto err; |
ef11c01d CW |
997 | } |
998 | ||
73dec95e TU |
999 | cs = intel_ring_begin(request, 0); |
1000 | if (IS_ERR(cs)) { | |
1001 | ret = PTR_ERR(cs); | |
ef11c01d | 1002 | goto err_unreserve; |
73dec95e | 1003 | } |
ef11c01d CW |
1004 | |
1005 | if (!ce->initialised) { | |
1006 | ret = engine->init_context(request); | |
1007 | if (ret) | |
1008 | goto err_unreserve; | |
1009 | ||
1010 | ce->initialised = true; | |
1011 | } | |
1012 | ||
1013 | /* Note that after this point, we have committed to using | |
1014 | * this request as it is being used to both track the | |
1015 | * state of engine initialisation and liveness of the | |
1016 | * golden renderstate above. Think twice before you try | |
1017 | * to cancel/unwind this request now. | |
1018 | */ | |
1019 | ||
1020 | request->reserved_space -= EXECLISTS_REQUEST_SIZE; | |
1021 | return 0; | |
1022 | ||
1023 | err_unreserve: | |
1024 | if (i915.enable_guc_submission) | |
1025 | i915_guc_wq_unreserve(request); | |
e8a9c58f | 1026 | err: |
ef11c01d CW |
1027 | return ret; |
1028 | } | |
1029 | ||
9e000847 AS |
1030 | /* |
1031 | * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after | |
1032 | * PIPE_CONTROL instruction. This is required for the flush to happen correctly | |
1033 | * but there is a slight complication as this is applied in WA batch where the | |
1034 | * values are only initialized once so we cannot take register value at the | |
1035 | * beginning and reuse it further; hence we save its value to memory, upload a | |
1036 | * constant value with bit21 set and then we restore it back with the saved value. | |
1037 | * To simplify the WA, a constant value is formed by using the default value | |
1038 | * of this register. This shouldn't be a problem because we are only modifying | |
1039 | * it for a short period and this batch in non-premptible. We can ofcourse | |
1040 | * use additional instructions that read the actual value of the register | |
1041 | * at that time and set our bit of interest but it makes the WA complicated. | |
1042 | * | |
1043 | * This WA is also required for Gen9 so extracting as a function avoids | |
1044 | * code duplication. | |
1045 | */ | |
097d4f1c TU |
1046 | static u32 * |
1047 | gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch) | |
17ee950d | 1048 | { |
097d4f1c TU |
1049 | *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; |
1050 | *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); | |
1051 | *batch++ = i915_ggtt_offset(engine->scratch) + 256; | |
1052 | *batch++ = 0; | |
1053 | ||
1054 | *batch++ = MI_LOAD_REGISTER_IMM(1); | |
1055 | *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); | |
1056 | *batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES; | |
1057 | ||
9f235dfa TU |
1058 | batch = gen8_emit_pipe_control(batch, |
1059 | PIPE_CONTROL_CS_STALL | | |
1060 | PIPE_CONTROL_DC_FLUSH_ENABLE, | |
1061 | 0); | |
097d4f1c TU |
1062 | |
1063 | *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; | |
1064 | *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); | |
1065 | *batch++ = i915_ggtt_offset(engine->scratch) + 256; | |
1066 | *batch++ = 0; | |
1067 | ||
1068 | return batch; | |
17ee950d AS |
1069 | } |
1070 | ||
6e5248b5 DV |
1071 | /* |
1072 | * Typically we only have one indirect_ctx and per_ctx batch buffer which are | |
1073 | * initialized at the beginning and shared across all contexts but this field | |
1074 | * helps us to have multiple batches at different offsets and select them based | |
1075 | * on a criteria. At the moment this batch always start at the beginning of the page | |
1076 | * and at this point we don't have multiple wa_ctx batch buffers. | |
4d78c8dc | 1077 | * |
6e5248b5 DV |
1078 | * The number of WA applied are not known at the beginning; we use this field |
1079 | * to return the no of DWORDS written. | |
17ee950d | 1080 | * |
6e5248b5 DV |
1081 | * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END |
1082 | * so it adds NOOPs as padding to make it cacheline aligned. | |
1083 | * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together | |
1084 | * makes a complete batch buffer. | |
17ee950d | 1085 | */ |
097d4f1c | 1086 | static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) |
17ee950d | 1087 | { |
7ad00d1a | 1088 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
097d4f1c | 1089 | *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; |
17ee950d | 1090 | |
c82435bb | 1091 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */ |
097d4f1c TU |
1092 | if (IS_BROADWELL(engine->i915)) |
1093 | batch = gen8_emit_flush_coherentl3_wa(engine, batch); | |
c82435bb | 1094 | |
0160f055 AS |
1095 | /* WaClearSlmSpaceAtContextSwitch:bdw,chv */ |
1096 | /* Actual scratch location is at 128 bytes offset */ | |
9f235dfa TU |
1097 | batch = gen8_emit_pipe_control(batch, |
1098 | PIPE_CONTROL_FLUSH_L3 | | |
1099 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1100 | PIPE_CONTROL_CS_STALL | | |
1101 | PIPE_CONTROL_QW_WRITE, | |
1102 | i915_ggtt_offset(engine->scratch) + | |
1103 | 2 * CACHELINE_BYTES); | |
0160f055 | 1104 | |
17ee950d | 1105 | /* Pad to end of cacheline */ |
097d4f1c TU |
1106 | while ((unsigned long)batch % CACHELINE_BYTES) |
1107 | *batch++ = MI_NOOP; | |
17ee950d AS |
1108 | |
1109 | /* | |
1110 | * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because | |
1111 | * execution depends on the length specified in terms of cache lines | |
1112 | * in the register CTX_RCS_INDIRECT_CTX | |
1113 | */ | |
1114 | ||
097d4f1c | 1115 | return batch; |
17ee950d AS |
1116 | } |
1117 | ||
6e5248b5 DV |
1118 | /* |
1119 | * This batch is started immediately after indirect_ctx batch. Since we ensure | |
1120 | * that indirect_ctx ends on a cacheline this batch is aligned automatically. | |
17ee950d | 1121 | * |
6e5248b5 | 1122 | * The number of DWORDS written are returned using this field. |
17ee950d AS |
1123 | * |
1124 | * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding | |
1125 | * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant. | |
1126 | */ | |
097d4f1c | 1127 | static u32 *gen8_init_perctx_bb(struct intel_engine_cs *engine, u32 *batch) |
17ee950d | 1128 | { |
7ad00d1a | 1129 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
097d4f1c TU |
1130 | *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; |
1131 | *batch++ = MI_BATCH_BUFFER_END; | |
17ee950d | 1132 | |
097d4f1c | 1133 | return batch; |
17ee950d AS |
1134 | } |
1135 | ||
097d4f1c | 1136 | static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) |
0504cffc | 1137 | { |
9fb5026f | 1138 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */ |
097d4f1c | 1139 | batch = gen8_emit_flush_coherentl3_wa(engine, batch); |
a4106a78 | 1140 | |
9fb5026f | 1141 | /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */ |
097d4f1c TU |
1142 | *batch++ = MI_LOAD_REGISTER_IMM(1); |
1143 | *batch++ = i915_mmio_reg_offset(COMMON_SLICE_CHICKEN2); | |
1144 | *batch++ = _MASKED_BIT_DISABLE( | |
1145 | GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE); | |
1146 | *batch++ = MI_NOOP; | |
873e8171 | 1147 | |
066d4628 MK |
1148 | /* WaClearSlmSpaceAtContextSwitch:kbl */ |
1149 | /* Actual scratch location is at 128 bytes offset */ | |
097d4f1c | 1150 | if (IS_KBL_REVID(engine->i915, 0, KBL_REVID_A0)) { |
9f235dfa TU |
1151 | batch = gen8_emit_pipe_control(batch, |
1152 | PIPE_CONTROL_FLUSH_L3 | | |
1153 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1154 | PIPE_CONTROL_CS_STALL | | |
1155 | PIPE_CONTROL_QW_WRITE, | |
1156 | i915_ggtt_offset(engine->scratch) | |
1157 | + 2 * CACHELINE_BYTES); | |
066d4628 | 1158 | } |
3485d99e | 1159 | |
9fb5026f | 1160 | /* WaMediaPoolStateCmdInWABB:bxt,glk */ |
3485d99e TG |
1161 | if (HAS_POOLED_EU(engine->i915)) { |
1162 | /* | |
1163 | * EU pool configuration is setup along with golden context | |
1164 | * during context initialization. This value depends on | |
1165 | * device type (2x6 or 3x6) and needs to be updated based | |
1166 | * on which subslice is disabled especially for 2x6 | |
1167 | * devices, however it is safe to load default | |
1168 | * configuration of 3x6 device instead of masking off | |
1169 | * corresponding bits because HW ignores bits of a disabled | |
1170 | * subslice and drops down to appropriate config. Please | |
1171 | * see render_state_setup() in i915_gem_render_state.c for | |
1172 | * possible configurations, to avoid duplication they are | |
1173 | * not shown here again. | |
1174 | */ | |
097d4f1c TU |
1175 | *batch++ = GEN9_MEDIA_POOL_STATE; |
1176 | *batch++ = GEN9_MEDIA_POOL_ENABLE; | |
1177 | *batch++ = 0x00777000; | |
1178 | *batch++ = 0; | |
1179 | *batch++ = 0; | |
1180 | *batch++ = 0; | |
3485d99e TG |
1181 | } |
1182 | ||
0504cffc | 1183 | /* Pad to end of cacheline */ |
097d4f1c TU |
1184 | while ((unsigned long)batch % CACHELINE_BYTES) |
1185 | *batch++ = MI_NOOP; | |
0504cffc | 1186 | |
097d4f1c | 1187 | return batch; |
0504cffc AS |
1188 | } |
1189 | ||
097d4f1c | 1190 | static u32 *gen9_init_perctx_bb(struct intel_engine_cs *engine, u32 *batch) |
0504cffc | 1191 | { |
097d4f1c | 1192 | *batch++ = MI_BATCH_BUFFER_END; |
0504cffc | 1193 | |
097d4f1c | 1194 | return batch; |
0504cffc AS |
1195 | } |
1196 | ||
097d4f1c TU |
1197 | #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE) |
1198 | ||
1199 | static int lrc_setup_wa_ctx(struct intel_engine_cs *engine) | |
17ee950d | 1200 | { |
48bb74e4 CW |
1201 | struct drm_i915_gem_object *obj; |
1202 | struct i915_vma *vma; | |
1203 | int err; | |
17ee950d | 1204 | |
097d4f1c | 1205 | obj = i915_gem_object_create(engine->i915, CTX_WA_BB_OBJ_SIZE); |
48bb74e4 CW |
1206 | if (IS_ERR(obj)) |
1207 | return PTR_ERR(obj); | |
17ee950d | 1208 | |
a01cb37a | 1209 | vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL); |
48bb74e4 CW |
1210 | if (IS_ERR(vma)) { |
1211 | err = PTR_ERR(vma); | |
1212 | goto err; | |
17ee950d AS |
1213 | } |
1214 | ||
48bb74e4 CW |
1215 | err = i915_vma_pin(vma, 0, PAGE_SIZE, PIN_GLOBAL | PIN_HIGH); |
1216 | if (err) | |
1217 | goto err; | |
1218 | ||
1219 | engine->wa_ctx.vma = vma; | |
17ee950d | 1220 | return 0; |
48bb74e4 CW |
1221 | |
1222 | err: | |
1223 | i915_gem_object_put(obj); | |
1224 | return err; | |
17ee950d AS |
1225 | } |
1226 | ||
097d4f1c | 1227 | static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine) |
17ee950d | 1228 | { |
19880c4a | 1229 | i915_vma_unpin_and_release(&engine->wa_ctx.vma); |
17ee950d AS |
1230 | } |
1231 | ||
097d4f1c TU |
1232 | typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch); |
1233 | ||
0bc40be8 | 1234 | static int intel_init_workaround_bb(struct intel_engine_cs *engine) |
17ee950d | 1235 | { |
48bb74e4 | 1236 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; |
097d4f1c TU |
1237 | struct i915_wa_ctx_bb *wa_bb[2] = { &wa_ctx->indirect_ctx, |
1238 | &wa_ctx->per_ctx }; | |
1239 | wa_bb_func_t wa_bb_fn[2]; | |
17ee950d | 1240 | struct page *page; |
097d4f1c TU |
1241 | void *batch, *batch_ptr; |
1242 | unsigned int i; | |
48bb74e4 | 1243 | int ret; |
17ee950d | 1244 | |
097d4f1c TU |
1245 | if (WARN_ON(engine->id != RCS || !engine->scratch)) |
1246 | return -EINVAL; | |
17ee950d | 1247 | |
097d4f1c | 1248 | switch (INTEL_GEN(engine->i915)) { |
90007bca RV |
1249 | case 10: |
1250 | return 0; | |
097d4f1c TU |
1251 | case 9: |
1252 | wa_bb_fn[0] = gen9_init_indirectctx_bb; | |
1253 | wa_bb_fn[1] = gen9_init_perctx_bb; | |
1254 | break; | |
1255 | case 8: | |
1256 | wa_bb_fn[0] = gen8_init_indirectctx_bb; | |
1257 | wa_bb_fn[1] = gen8_init_perctx_bb; | |
1258 | break; | |
1259 | default: | |
1260 | MISSING_CASE(INTEL_GEN(engine->i915)); | |
5e60d790 | 1261 | return 0; |
0504cffc | 1262 | } |
5e60d790 | 1263 | |
097d4f1c | 1264 | ret = lrc_setup_wa_ctx(engine); |
17ee950d AS |
1265 | if (ret) { |
1266 | DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret); | |
1267 | return ret; | |
1268 | } | |
1269 | ||
48bb74e4 | 1270 | page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0); |
097d4f1c | 1271 | batch = batch_ptr = kmap_atomic(page); |
17ee950d | 1272 | |
097d4f1c TU |
1273 | /* |
1274 | * Emit the two workaround batch buffers, recording the offset from the | |
1275 | * start of the workaround batch buffer object for each and their | |
1276 | * respective sizes. | |
1277 | */ | |
1278 | for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) { | |
1279 | wa_bb[i]->offset = batch_ptr - batch; | |
1280 | if (WARN_ON(!IS_ALIGNED(wa_bb[i]->offset, CACHELINE_BYTES))) { | |
1281 | ret = -EINVAL; | |
1282 | break; | |
1283 | } | |
1284 | batch_ptr = wa_bb_fn[i](engine, batch_ptr); | |
1285 | wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset); | |
17ee950d AS |
1286 | } |
1287 | ||
097d4f1c TU |
1288 | BUG_ON(batch_ptr - batch > CTX_WA_BB_OBJ_SIZE); |
1289 | ||
17ee950d AS |
1290 | kunmap_atomic(batch); |
1291 | if (ret) | |
097d4f1c | 1292 | lrc_destroy_wa_ctx(engine); |
17ee950d AS |
1293 | |
1294 | return ret; | |
1295 | } | |
1296 | ||
64f09f00 CW |
1297 | static u8 gtiir[] = { |
1298 | [RCS] = 0, | |
1299 | [BCS] = 0, | |
1300 | [VCS] = 1, | |
1301 | [VCS2] = 1, | |
1302 | [VECS] = 3, | |
1303 | }; | |
1304 | ||
0bc40be8 | 1305 | static int gen8_init_common_ring(struct intel_engine_cs *engine) |
9b1136d5 | 1306 | { |
c033666a | 1307 | struct drm_i915_private *dev_priv = engine->i915; |
6b764a59 CW |
1308 | struct execlist_port *port = engine->execlist_port; |
1309 | unsigned int n; | |
77f0d0e9 | 1310 | bool submit; |
821ed7df CW |
1311 | int ret; |
1312 | ||
1313 | ret = intel_mocs_init_engine(engine); | |
1314 | if (ret) | |
1315 | return ret; | |
9b1136d5 | 1316 | |
ad07dfcd | 1317 | intel_engine_reset_breadcrumbs(engine); |
f3b8f912 | 1318 | intel_engine_init_hangcheck(engine); |
821ed7df | 1319 | |
0bc40be8 | 1320 | I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff); |
0bc40be8 | 1321 | I915_WRITE(RING_MODE_GEN7(engine), |
9b1136d5 | 1322 | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); |
f3b8f912 CW |
1323 | I915_WRITE(RING_HWS_PGA(engine->mmio_base), |
1324 | engine->status_page.ggtt_offset); | |
1325 | POSTING_READ(RING_HWS_PGA(engine->mmio_base)); | |
dfc53c5e | 1326 | |
0bc40be8 | 1327 | DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name); |
9b1136d5 | 1328 | |
64f09f00 CW |
1329 | GEM_BUG_ON(engine->id >= ARRAY_SIZE(gtiir)); |
1330 | ||
1331 | /* | |
1332 | * Clear any pending interrupt state. | |
1333 | * | |
1334 | * We do it twice out of paranoia that some of the IIR are double | |
1335 | * buffered, and if we only reset it once there may still be | |
1336 | * an interrupt pending. | |
1337 | */ | |
1338 | I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]), | |
1339 | GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift); | |
1340 | I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]), | |
1341 | GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift); | |
f747026c | 1342 | clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); |
767a983a | 1343 | engine->csb_head = -1; |
6b764a59 | 1344 | |
64f09f00 | 1345 | /* After a GPU reset, we may have requests to replay */ |
77f0d0e9 | 1346 | submit = false; |
6b764a59 | 1347 | for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++) { |
77f0d0e9 | 1348 | if (!port_isset(&port[n])) |
6b764a59 CW |
1349 | break; |
1350 | ||
1351 | DRM_DEBUG_DRIVER("Restarting %s:%d from 0x%x\n", | |
1352 | engine->name, n, | |
77f0d0e9 | 1353 | port_request(&port[n])->global_seqno); |
6b764a59 CW |
1354 | |
1355 | /* Discard the current inflight count */ | |
77f0d0e9 CW |
1356 | port_set(&port[n], port_request(&port[n])); |
1357 | submit = true; | |
c87d50cc | 1358 | } |
821ed7df | 1359 | |
523e7c92 CW |
1360 | if (!i915.enable_guc_submission) { |
1361 | if (submit) | |
1362 | execlists_submit_ports(engine); | |
1363 | else if (engine->execlist_first) | |
1364 | tasklet_schedule(&engine->irq_tasklet); | |
1365 | } | |
6b764a59 | 1366 | |
821ed7df | 1367 | return 0; |
9b1136d5 OM |
1368 | } |
1369 | ||
0bc40be8 | 1370 | static int gen8_init_render_ring(struct intel_engine_cs *engine) |
9b1136d5 | 1371 | { |
c033666a | 1372 | struct drm_i915_private *dev_priv = engine->i915; |
9b1136d5 OM |
1373 | int ret; |
1374 | ||
0bc40be8 | 1375 | ret = gen8_init_common_ring(engine); |
9b1136d5 OM |
1376 | if (ret) |
1377 | return ret; | |
1378 | ||
1379 | /* We need to disable the AsyncFlip performance optimisations in order | |
1380 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1381 | * programmed to '1' on all products. | |
1382 | * | |
1383 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv | |
1384 | */ | |
1385 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
1386 | ||
9b1136d5 OM |
1387 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
1388 | ||
0bc40be8 | 1389 | return init_workarounds_ring(engine); |
9b1136d5 OM |
1390 | } |
1391 | ||
0bc40be8 | 1392 | static int gen9_init_render_ring(struct intel_engine_cs *engine) |
82ef822e DL |
1393 | { |
1394 | int ret; | |
1395 | ||
0bc40be8 | 1396 | ret = gen8_init_common_ring(engine); |
82ef822e DL |
1397 | if (ret) |
1398 | return ret; | |
1399 | ||
0bc40be8 | 1400 | return init_workarounds_ring(engine); |
82ef822e DL |
1401 | } |
1402 | ||
821ed7df CW |
1403 | static void reset_common_ring(struct intel_engine_cs *engine, |
1404 | struct drm_i915_gem_request *request) | |
1405 | { | |
821ed7df | 1406 | struct execlist_port *port = engine->execlist_port; |
c0dcb203 | 1407 | struct intel_context *ce; |
cdb6ded4 CW |
1408 | unsigned int n; |
1409 | ||
1410 | /* | |
1411 | * Catch up with any missed context-switch interrupts. | |
1412 | * | |
1413 | * Ideally we would just read the remaining CSB entries now that we | |
1414 | * know the gpu is idle. However, the CSB registers are sometimes^W | |
1415 | * often trashed across a GPU reset! Instead we have to rely on | |
1416 | * guessing the missed context-switch events by looking at what | |
1417 | * requests were completed. | |
1418 | */ | |
1419 | if (!request) { | |
1420 | for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++) | |
1421 | i915_gem_request_put(port_request(&port[n])); | |
1422 | memset(engine->execlist_port, 0, sizeof(engine->execlist_port)); | |
1423 | return; | |
1424 | } | |
1425 | ||
1426 | if (request->ctx != port_request(port)->ctx) { | |
1427 | i915_gem_request_put(port_request(port)); | |
1428 | port[0] = port[1]; | |
1429 | memset(&port[1], 0, sizeof(port[1])); | |
1430 | } | |
1431 | ||
1432 | GEM_BUG_ON(request->ctx != port_request(port)->ctx); | |
c0dcb203 CW |
1433 | |
1434 | /* If the request was innocent, we leave the request in the ELSP | |
1435 | * and will try to replay it on restarting. The context image may | |
1436 | * have been corrupted by the reset, in which case we may have | |
1437 | * to service a new GPU hang, but more likely we can continue on | |
1438 | * without impact. | |
1439 | * | |
1440 | * If the request was guilty, we presume the context is corrupt | |
1441 | * and have to at least restore the RING register in the context | |
1442 | * image back to the expected values to skip over the guilty request. | |
1443 | */ | |
cdb6ded4 | 1444 | if (request->fence.error != -EIO) |
c0dcb203 | 1445 | return; |
821ed7df | 1446 | |
a3aabe86 CW |
1447 | /* We want a simple context + ring to execute the breadcrumb update. |
1448 | * We cannot rely on the context being intact across the GPU hang, | |
1449 | * so clear it and rebuild just what we need for the breadcrumb. | |
1450 | * All pending requests for this context will be zapped, and any | |
1451 | * future request will be after userspace has had the opportunity | |
1452 | * to recreate its own state. | |
1453 | */ | |
c0dcb203 | 1454 | ce = &request->ctx->engine[engine->id]; |
a3aabe86 CW |
1455 | execlists_init_reg_state(ce->lrc_reg_state, |
1456 | request->ctx, engine, ce->ring); | |
1457 | ||
821ed7df | 1458 | /* Move the RING_HEAD onto the breadcrumb, past the hanging batch */ |
a3aabe86 CW |
1459 | ce->lrc_reg_state[CTX_RING_BUFFER_START+1] = |
1460 | i915_ggtt_offset(ce->ring->vma); | |
821ed7df | 1461 | ce->lrc_reg_state[CTX_RING_HEAD+1] = request->postfix; |
a3aabe86 | 1462 | |
821ed7df | 1463 | request->ring->head = request->postfix; |
821ed7df CW |
1464 | intel_ring_update_space(request->ring); |
1465 | ||
a3aabe86 | 1466 | /* Reset WaIdleLiteRestore:bdw,skl as well */ |
450362d3 CW |
1467 | request->tail = |
1468 | intel_ring_wrap(request->ring, | |
1469 | request->wa_tail - WA_TAIL_DWORDS*sizeof(u32)); | |
ed1501d4 | 1470 | assert_ring_tail_valid(request->ring, request->tail); |
821ed7df CW |
1471 | } |
1472 | ||
7a01a0a2 MT |
1473 | static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req) |
1474 | { | |
1475 | struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt; | |
4a570db5 | 1476 | struct intel_engine_cs *engine = req->engine; |
e7167769 | 1477 | const int num_lri_cmds = GEN8_3LVL_PDPES * 2; |
73dec95e TU |
1478 | u32 *cs; |
1479 | int i; | |
7a01a0a2 | 1480 | |
73dec95e TU |
1481 | cs = intel_ring_begin(req, num_lri_cmds * 2 + 2); |
1482 | if (IS_ERR(cs)) | |
1483 | return PTR_ERR(cs); | |
7a01a0a2 | 1484 | |
73dec95e | 1485 | *cs++ = MI_LOAD_REGISTER_IMM(num_lri_cmds); |
e7167769 | 1486 | for (i = GEN8_3LVL_PDPES - 1; i >= 0; i--) { |
7a01a0a2 MT |
1487 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); |
1488 | ||
73dec95e TU |
1489 | *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i)); |
1490 | *cs++ = upper_32_bits(pd_daddr); | |
1491 | *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i)); | |
1492 | *cs++ = lower_32_bits(pd_daddr); | |
7a01a0a2 MT |
1493 | } |
1494 | ||
73dec95e TU |
1495 | *cs++ = MI_NOOP; |
1496 | intel_ring_advance(req, cs); | |
7a01a0a2 MT |
1497 | |
1498 | return 0; | |
1499 | } | |
1500 | ||
be795fc1 | 1501 | static int gen8_emit_bb_start(struct drm_i915_gem_request *req, |
803688ba | 1502 | u64 offset, u32 len, |
54af56db | 1503 | const unsigned int flags) |
15648585 | 1504 | { |
73dec95e | 1505 | u32 *cs; |
15648585 OM |
1506 | int ret; |
1507 | ||
7a01a0a2 MT |
1508 | /* Don't rely in hw updating PDPs, specially in lite-restore. |
1509 | * Ideally, we should set Force PD Restore in ctx descriptor, | |
1510 | * but we can't. Force Restore would be a second option, but | |
1511 | * it is unsafe in case of lite-restore (because the ctx is | |
2dba3239 MT |
1512 | * not idle). PML4 is allocated during ppgtt init so this is |
1513 | * not needed in 48-bit.*/ | |
7a01a0a2 | 1514 | if (req->ctx->ppgtt && |
54af56db MK |
1515 | (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings) && |
1516 | !i915_vm_is_48bit(&req->ctx->ppgtt->base) && | |
1517 | !intel_vgpu_active(req->i915)) { | |
1518 | ret = intel_logical_ring_emit_pdps(req); | |
1519 | if (ret) | |
1520 | return ret; | |
7a01a0a2 | 1521 | |
666796da | 1522 | req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine); |
7a01a0a2 MT |
1523 | } |
1524 | ||
73dec95e TU |
1525 | cs = intel_ring_begin(req, 4); |
1526 | if (IS_ERR(cs)) | |
1527 | return PTR_ERR(cs); | |
15648585 OM |
1528 | |
1529 | /* FIXME(BDW): Address space and security selectors. */ | |
54af56db MK |
1530 | *cs++ = MI_BATCH_BUFFER_START_GEN8 | |
1531 | (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)) | | |
1532 | (flags & I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0); | |
73dec95e TU |
1533 | *cs++ = lower_32_bits(offset); |
1534 | *cs++ = upper_32_bits(offset); | |
1535 | *cs++ = MI_NOOP; | |
1536 | intel_ring_advance(req, cs); | |
15648585 OM |
1537 | |
1538 | return 0; | |
1539 | } | |
1540 | ||
31bb59cc | 1541 | static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine) |
73d477f6 | 1542 | { |
c033666a | 1543 | struct drm_i915_private *dev_priv = engine->i915; |
31bb59cc CW |
1544 | I915_WRITE_IMR(engine, |
1545 | ~(engine->irq_enable_mask | engine->irq_keep_mask)); | |
1546 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
73d477f6 OM |
1547 | } |
1548 | ||
31bb59cc | 1549 | static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine) |
73d477f6 | 1550 | { |
c033666a | 1551 | struct drm_i915_private *dev_priv = engine->i915; |
31bb59cc | 1552 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
73d477f6 OM |
1553 | } |
1554 | ||
7c9cf4e3 | 1555 | static int gen8_emit_flush(struct drm_i915_gem_request *request, u32 mode) |
4712274c | 1556 | { |
73dec95e | 1557 | u32 cmd, *cs; |
4712274c | 1558 | |
73dec95e TU |
1559 | cs = intel_ring_begin(request, 4); |
1560 | if (IS_ERR(cs)) | |
1561 | return PTR_ERR(cs); | |
4712274c OM |
1562 | |
1563 | cmd = MI_FLUSH_DW + 1; | |
1564 | ||
f0a1fb10 CW |
1565 | /* We always require a command barrier so that subsequent |
1566 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1567 | * wrt the contents of the write cache being flushed to memory | |
1568 | * (and thus being coherent from the CPU). | |
1569 | */ | |
1570 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1571 | ||
7c9cf4e3 | 1572 | if (mode & EMIT_INVALIDATE) { |
f0a1fb10 | 1573 | cmd |= MI_INVALIDATE_TLB; |
1dae2dfb | 1574 | if (request->engine->id == VCS) |
f0a1fb10 | 1575 | cmd |= MI_INVALIDATE_BSD; |
4712274c OM |
1576 | } |
1577 | ||
73dec95e TU |
1578 | *cs++ = cmd; |
1579 | *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; | |
1580 | *cs++ = 0; /* upper addr */ | |
1581 | *cs++ = 0; /* value */ | |
1582 | intel_ring_advance(request, cs); | |
4712274c OM |
1583 | |
1584 | return 0; | |
1585 | } | |
1586 | ||
7deb4d39 | 1587 | static int gen8_emit_flush_render(struct drm_i915_gem_request *request, |
7c9cf4e3 | 1588 | u32 mode) |
4712274c | 1589 | { |
b5321f30 | 1590 | struct intel_engine_cs *engine = request->engine; |
bde13ebd CW |
1591 | u32 scratch_addr = |
1592 | i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES; | |
0b2d0934 | 1593 | bool vf_flush_wa = false, dc_flush_wa = false; |
73dec95e | 1594 | u32 *cs, flags = 0; |
0b2d0934 | 1595 | int len; |
4712274c OM |
1596 | |
1597 | flags |= PIPE_CONTROL_CS_STALL; | |
1598 | ||
7c9cf4e3 | 1599 | if (mode & EMIT_FLUSH) { |
4712274c OM |
1600 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
1601 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 1602 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 1603 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4712274c OM |
1604 | } |
1605 | ||
7c9cf4e3 | 1606 | if (mode & EMIT_INVALIDATE) { |
4712274c OM |
1607 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
1608 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
1609 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
1610 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
1611 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
1612 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
1613 | flags |= PIPE_CONTROL_QW_WRITE; | |
1614 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
4712274c | 1615 | |
1a5a9ce7 BW |
1616 | /* |
1617 | * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL | |
1618 | * pipe control. | |
1619 | */ | |
c033666a | 1620 | if (IS_GEN9(request->i915)) |
1a5a9ce7 | 1621 | vf_flush_wa = true; |
0b2d0934 MK |
1622 | |
1623 | /* WaForGAMHang:kbl */ | |
1624 | if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0)) | |
1625 | dc_flush_wa = true; | |
1a5a9ce7 | 1626 | } |
9647ff36 | 1627 | |
0b2d0934 MK |
1628 | len = 6; |
1629 | ||
1630 | if (vf_flush_wa) | |
1631 | len += 6; | |
1632 | ||
1633 | if (dc_flush_wa) | |
1634 | len += 12; | |
1635 | ||
73dec95e TU |
1636 | cs = intel_ring_begin(request, len); |
1637 | if (IS_ERR(cs)) | |
1638 | return PTR_ERR(cs); | |
4712274c | 1639 | |
9f235dfa TU |
1640 | if (vf_flush_wa) |
1641 | cs = gen8_emit_pipe_control(cs, 0, 0); | |
9647ff36 | 1642 | |
9f235dfa TU |
1643 | if (dc_flush_wa) |
1644 | cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE, | |
1645 | 0); | |
0b2d0934 | 1646 | |
9f235dfa | 1647 | cs = gen8_emit_pipe_control(cs, flags, scratch_addr); |
0b2d0934 | 1648 | |
9f235dfa TU |
1649 | if (dc_flush_wa) |
1650 | cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0); | |
0b2d0934 | 1651 | |
73dec95e | 1652 | intel_ring_advance(request, cs); |
4712274c OM |
1653 | |
1654 | return 0; | |
1655 | } | |
1656 | ||
7c17d377 CW |
1657 | /* |
1658 | * Reserve space for 2 NOOPs at the end of each request to be | |
1659 | * used as a workaround for not being allowed to do lite | |
1660 | * restore with HEAD==TAIL (WaIdleLiteRestore). | |
1661 | */ | |
73dec95e | 1662 | static void gen8_emit_wa_tail(struct drm_i915_gem_request *request, u32 *cs) |
4da46e1e | 1663 | { |
73dec95e TU |
1664 | *cs++ = MI_NOOP; |
1665 | *cs++ = MI_NOOP; | |
1666 | request->wa_tail = intel_ring_offset(request, cs); | |
caddfe71 | 1667 | } |
4da46e1e | 1668 | |
73dec95e | 1669 | static void gen8_emit_breadcrumb(struct drm_i915_gem_request *request, u32 *cs) |
caddfe71 | 1670 | { |
7c17d377 CW |
1671 | /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */ |
1672 | BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5)); | |
4da46e1e | 1673 | |
73dec95e TU |
1674 | *cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW; |
1675 | *cs++ = intel_hws_seqno_address(request->engine) | MI_FLUSH_DW_USE_GTT; | |
1676 | *cs++ = 0; | |
1677 | *cs++ = request->global_seqno; | |
1678 | *cs++ = MI_USER_INTERRUPT; | |
1679 | *cs++ = MI_NOOP; | |
1680 | request->tail = intel_ring_offset(request, cs); | |
ed1501d4 | 1681 | assert_ring_tail_valid(request->ring, request->tail); |
caddfe71 | 1682 | |
73dec95e | 1683 | gen8_emit_wa_tail(request, cs); |
7c17d377 | 1684 | } |
4da46e1e | 1685 | |
98f29e8d CW |
1686 | static const int gen8_emit_breadcrumb_sz = 6 + WA_TAIL_DWORDS; |
1687 | ||
caddfe71 | 1688 | static void gen8_emit_breadcrumb_render(struct drm_i915_gem_request *request, |
73dec95e | 1689 | u32 *cs) |
7c17d377 | 1690 | { |
ce81a65c MW |
1691 | /* We're using qword write, seqno should be aligned to 8 bytes. */ |
1692 | BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1); | |
1693 | ||
7c17d377 CW |
1694 | /* w/a for post sync ops following a GPGPU operation we |
1695 | * need a prior CS_STALL, which is emitted by the flush | |
1696 | * following the batch. | |
1697 | */ | |
73dec95e TU |
1698 | *cs++ = GFX_OP_PIPE_CONTROL(6); |
1699 | *cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_CS_STALL | | |
1700 | PIPE_CONTROL_QW_WRITE; | |
1701 | *cs++ = intel_hws_seqno_address(request->engine); | |
1702 | *cs++ = 0; | |
1703 | *cs++ = request->global_seqno; | |
ce81a65c | 1704 | /* We're thrashing one dword of HWS. */ |
73dec95e TU |
1705 | *cs++ = 0; |
1706 | *cs++ = MI_USER_INTERRUPT; | |
1707 | *cs++ = MI_NOOP; | |
1708 | request->tail = intel_ring_offset(request, cs); | |
ed1501d4 | 1709 | assert_ring_tail_valid(request->ring, request->tail); |
caddfe71 | 1710 | |
73dec95e | 1711 | gen8_emit_wa_tail(request, cs); |
4da46e1e OM |
1712 | } |
1713 | ||
98f29e8d CW |
1714 | static const int gen8_emit_breadcrumb_render_sz = 8 + WA_TAIL_DWORDS; |
1715 | ||
8753181e | 1716 | static int gen8_init_rcs_context(struct drm_i915_gem_request *req) |
e7778be1 TD |
1717 | { |
1718 | int ret; | |
1719 | ||
4ac9659e | 1720 | ret = intel_ring_workarounds_emit(req); |
e7778be1 TD |
1721 | if (ret) |
1722 | return ret; | |
1723 | ||
3bbaba0c PA |
1724 | ret = intel_rcs_context_init_mocs(req); |
1725 | /* | |
1726 | * Failing to program the MOCS is non-fatal.The system will not | |
1727 | * run at peak performance. So generate an error and carry on. | |
1728 | */ | |
1729 | if (ret) | |
1730 | DRM_ERROR("MOCS failed to program: expect performance issues.\n"); | |
1731 | ||
4e50f082 | 1732 | return i915_gem_render_state_emit(req); |
e7778be1 TD |
1733 | } |
1734 | ||
73e4d07f OM |
1735 | /** |
1736 | * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer | |
14bb2c11 | 1737 | * @engine: Engine Command Streamer. |
73e4d07f | 1738 | */ |
0bc40be8 | 1739 | void intel_logical_ring_cleanup(struct intel_engine_cs *engine) |
454afebd | 1740 | { |
6402c330 | 1741 | struct drm_i915_private *dev_priv; |
9832b9da | 1742 | |
27af5eea TU |
1743 | /* |
1744 | * Tasklet cannot be active at this point due intel_mark_active/idle | |
1745 | * so this is just for documentation. | |
1746 | */ | |
1747 | if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state))) | |
1748 | tasklet_kill(&engine->irq_tasklet); | |
1749 | ||
c033666a | 1750 | dev_priv = engine->i915; |
6402c330 | 1751 | |
0bc40be8 | 1752 | if (engine->buffer) { |
0bc40be8 | 1753 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
b0366a54 | 1754 | } |
48d82387 | 1755 | |
0bc40be8 TU |
1756 | if (engine->cleanup) |
1757 | engine->cleanup(engine); | |
48d82387 | 1758 | |
e8a9c58f | 1759 | intel_engine_cleanup_common(engine); |
17ee950d | 1760 | |
097d4f1c | 1761 | lrc_destroy_wa_ctx(engine); |
c033666a | 1762 | engine->i915 = NULL; |
3b3f1650 AG |
1763 | dev_priv->engine[engine->id] = NULL; |
1764 | kfree(engine); | |
454afebd OM |
1765 | } |
1766 | ||
ff44ad51 | 1767 | static void execlists_set_default_submission(struct intel_engine_cs *engine) |
ddd66c51 | 1768 | { |
ff44ad51 | 1769 | engine->submit_request = execlists_submit_request; |
27a5f61b | 1770 | engine->cancel_requests = execlists_cancel_requests; |
ff44ad51 | 1771 | engine->schedule = execlists_schedule; |
c9203e82 | 1772 | engine->irq_tasklet.func = intel_lrc_irq_handler; |
ddd66c51 CW |
1773 | } |
1774 | ||
c9cacf93 | 1775 | static void |
e1382efb | 1776 | logical_ring_default_vfuncs(struct intel_engine_cs *engine) |
c9cacf93 TU |
1777 | { |
1778 | /* Default vfuncs which can be overriden by each engine. */ | |
0bc40be8 | 1779 | engine->init_hw = gen8_init_common_ring; |
821ed7df | 1780 | engine->reset_hw = reset_common_ring; |
e8a9c58f CW |
1781 | |
1782 | engine->context_pin = execlists_context_pin; | |
1783 | engine->context_unpin = execlists_context_unpin; | |
1784 | ||
f73e7399 CW |
1785 | engine->request_alloc = execlists_request_alloc; |
1786 | ||
0bc40be8 | 1787 | engine->emit_flush = gen8_emit_flush; |
9b81d556 | 1788 | engine->emit_breadcrumb = gen8_emit_breadcrumb; |
98f29e8d | 1789 | engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz; |
ff44ad51 CW |
1790 | |
1791 | engine->set_default_submission = execlists_set_default_submission; | |
ddd66c51 | 1792 | |
31bb59cc CW |
1793 | engine->irq_enable = gen8_logical_ring_enable_irq; |
1794 | engine->irq_disable = gen8_logical_ring_disable_irq; | |
0bc40be8 | 1795 | engine->emit_bb_start = gen8_emit_bb_start; |
c9cacf93 TU |
1796 | } |
1797 | ||
d9f3af96 | 1798 | static inline void |
c2c7f240 | 1799 | logical_ring_default_irqs(struct intel_engine_cs *engine) |
d9f3af96 | 1800 | { |
c2c7f240 | 1801 | unsigned shift = engine->irq_shift; |
0bc40be8 TU |
1802 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift; |
1803 | engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift; | |
d9f3af96 TU |
1804 | } |
1805 | ||
6d2cb5aa CW |
1806 | static bool irq_handler_force_mmio(struct drm_i915_private *i915) |
1807 | { | |
1808 | /* GVT emulation depends upon intercepting CSB mmio */ | |
1809 | if (intel_vgpu_active(i915)) | |
1810 | return true; | |
1811 | ||
1812 | /* | |
1813 | * IOMMU adds unpredictable latency causing the CSB write (from the | |
1814 | * GPU into the HWSP) to only be visible some time after the interrupt | |
1815 | * (missed breadcrumb syndrome). | |
1816 | */ | |
1817 | if (intel_vtd_active()) | |
1818 | return true; | |
1819 | ||
1820 | return false; | |
1821 | } | |
1822 | ||
bb45438f TU |
1823 | static void |
1824 | logical_ring_setup(struct intel_engine_cs *engine) | |
1825 | { | |
1826 | struct drm_i915_private *dev_priv = engine->i915; | |
1827 | enum forcewake_domains fw_domains; | |
1828 | ||
019bf277 TU |
1829 | intel_engine_setup_common(engine); |
1830 | ||
bb45438f TU |
1831 | /* Intentionally left blank. */ |
1832 | engine->buffer = NULL; | |
1833 | ||
6d2cb5aa CW |
1834 | engine->csb_use_mmio = irq_handler_force_mmio(dev_priv); |
1835 | ||
bb45438f TU |
1836 | fw_domains = intel_uncore_forcewake_for_reg(dev_priv, |
1837 | RING_ELSP(engine), | |
1838 | FW_REG_WRITE); | |
1839 | ||
1840 | fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, | |
1841 | RING_CONTEXT_STATUS_PTR(engine), | |
1842 | FW_REG_READ | FW_REG_WRITE); | |
1843 | ||
1844 | fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, | |
1845 | RING_CONTEXT_STATUS_BUF_BASE(engine), | |
1846 | FW_REG_READ); | |
1847 | ||
1848 | engine->fw_domains = fw_domains; | |
1849 | ||
bb45438f TU |
1850 | tasklet_init(&engine->irq_tasklet, |
1851 | intel_lrc_irq_handler, (unsigned long)engine); | |
1852 | ||
bb45438f TU |
1853 | logical_ring_default_vfuncs(engine); |
1854 | logical_ring_default_irqs(engine); | |
bb45438f TU |
1855 | } |
1856 | ||
486e93f7 | 1857 | static int logical_ring_init(struct intel_engine_cs *engine) |
a19d6ff2 | 1858 | { |
a19d6ff2 TU |
1859 | int ret; |
1860 | ||
019bf277 | 1861 | ret = intel_engine_init_common(engine); |
a19d6ff2 TU |
1862 | if (ret) |
1863 | goto error; | |
1864 | ||
a19d6ff2 TU |
1865 | return 0; |
1866 | ||
1867 | error: | |
1868 | intel_logical_ring_cleanup(engine); | |
1869 | return ret; | |
1870 | } | |
1871 | ||
88d2ba2e | 1872 | int logical_render_ring_init(struct intel_engine_cs *engine) |
a19d6ff2 TU |
1873 | { |
1874 | struct drm_i915_private *dev_priv = engine->i915; | |
1875 | int ret; | |
1876 | ||
bb45438f TU |
1877 | logical_ring_setup(engine); |
1878 | ||
a19d6ff2 TU |
1879 | if (HAS_L3_DPF(dev_priv)) |
1880 | engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
1881 | ||
1882 | /* Override some for render ring. */ | |
1883 | if (INTEL_GEN(dev_priv) >= 9) | |
1884 | engine->init_hw = gen9_init_render_ring; | |
1885 | else | |
1886 | engine->init_hw = gen8_init_render_ring; | |
1887 | engine->init_context = gen8_init_rcs_context; | |
a19d6ff2 | 1888 | engine->emit_flush = gen8_emit_flush_render; |
9b81d556 | 1889 | engine->emit_breadcrumb = gen8_emit_breadcrumb_render; |
98f29e8d | 1890 | engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_render_sz; |
a19d6ff2 | 1891 | |
f51455d4 | 1892 | ret = intel_engine_create_scratch(engine, PAGE_SIZE); |
a19d6ff2 TU |
1893 | if (ret) |
1894 | return ret; | |
1895 | ||
1896 | ret = intel_init_workaround_bb(engine); | |
1897 | if (ret) { | |
1898 | /* | |
1899 | * We continue even if we fail to initialize WA batch | |
1900 | * because we only expect rare glitches but nothing | |
1901 | * critical to prevent us from using GPU | |
1902 | */ | |
1903 | DRM_ERROR("WA batch buffer initialization failed: %d\n", | |
1904 | ret); | |
1905 | } | |
1906 | ||
d038fc7e | 1907 | return logical_ring_init(engine); |
a19d6ff2 TU |
1908 | } |
1909 | ||
88d2ba2e | 1910 | int logical_xcs_ring_init(struct intel_engine_cs *engine) |
bb45438f TU |
1911 | { |
1912 | logical_ring_setup(engine); | |
1913 | ||
1914 | return logical_ring_init(engine); | |
454afebd OM |
1915 | } |
1916 | ||
0cea6502 | 1917 | static u32 |
c033666a | 1918 | make_rpcs(struct drm_i915_private *dev_priv) |
0cea6502 JM |
1919 | { |
1920 | u32 rpcs = 0; | |
1921 | ||
1922 | /* | |
1923 | * No explicit RPCS request is needed to ensure full | |
1924 | * slice/subslice/EU enablement prior to Gen9. | |
1925 | */ | |
c033666a | 1926 | if (INTEL_GEN(dev_priv) < 9) |
0cea6502 JM |
1927 | return 0; |
1928 | ||
1929 | /* | |
1930 | * Starting in Gen9, render power gating can leave | |
1931 | * slice/subslice/EU in a partially enabled state. We | |
1932 | * must make an explicit request through RPCS for full | |
1933 | * enablement. | |
1934 | */ | |
43b67998 | 1935 | if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) { |
0cea6502 | 1936 | rpcs |= GEN8_RPCS_S_CNT_ENABLE; |
f08a0c92 | 1937 | rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) << |
0cea6502 JM |
1938 | GEN8_RPCS_S_CNT_SHIFT; |
1939 | rpcs |= GEN8_RPCS_ENABLE; | |
1940 | } | |
1941 | ||
43b67998 | 1942 | if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) { |
0cea6502 | 1943 | rpcs |= GEN8_RPCS_SS_CNT_ENABLE; |
57ec171e | 1944 | rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask) << |
0cea6502 JM |
1945 | GEN8_RPCS_SS_CNT_SHIFT; |
1946 | rpcs |= GEN8_RPCS_ENABLE; | |
1947 | } | |
1948 | ||
43b67998 ID |
1949 | if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) { |
1950 | rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice << | |
0cea6502 | 1951 | GEN8_RPCS_EU_MIN_SHIFT; |
43b67998 | 1952 | rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice << |
0cea6502 JM |
1953 | GEN8_RPCS_EU_MAX_SHIFT; |
1954 | rpcs |= GEN8_RPCS_ENABLE; | |
1955 | } | |
1956 | ||
1957 | return rpcs; | |
1958 | } | |
1959 | ||
0bc40be8 | 1960 | static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine) |
71562919 MT |
1961 | { |
1962 | u32 indirect_ctx_offset; | |
1963 | ||
c033666a | 1964 | switch (INTEL_GEN(engine->i915)) { |
71562919 | 1965 | default: |
c033666a | 1966 | MISSING_CASE(INTEL_GEN(engine->i915)); |
71562919 | 1967 | /* fall through */ |
7bd0a2c6 MT |
1968 | case 10: |
1969 | indirect_ctx_offset = | |
1970 | GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
1971 | break; | |
71562919 MT |
1972 | case 9: |
1973 | indirect_ctx_offset = | |
1974 | GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
1975 | break; | |
1976 | case 8: | |
1977 | indirect_ctx_offset = | |
1978 | GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
1979 | break; | |
1980 | } | |
1981 | ||
1982 | return indirect_ctx_offset; | |
1983 | } | |
1984 | ||
56e51bf0 | 1985 | static void execlists_init_reg_state(u32 *regs, |
a3aabe86 CW |
1986 | struct i915_gem_context *ctx, |
1987 | struct intel_engine_cs *engine, | |
1988 | struct intel_ring *ring) | |
8670d6f9 | 1989 | { |
a3aabe86 CW |
1990 | struct drm_i915_private *dev_priv = engine->i915; |
1991 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv->mm.aliasing_ppgtt; | |
56e51bf0 TU |
1992 | u32 base = engine->mmio_base; |
1993 | bool rcs = engine->id == RCS; | |
1994 | ||
1995 | /* A context is actually a big batch buffer with several | |
1996 | * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The | |
1997 | * values we are setting here are only for the first context restore: | |
1998 | * on a subsequent save, the GPU will recreate this batchbuffer with new | |
1999 | * values (including all the missing MI_LOAD_REGISTER_IMM commands that | |
2000 | * we are not initializing here). | |
2001 | */ | |
2002 | regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) | | |
2003 | MI_LRI_FORCE_POSTED; | |
2004 | ||
2005 | CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(engine), | |
2006 | _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | | |
2007 | CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | | |
2008 | (HAS_RESOURCE_STREAMER(dev_priv) ? | |
2009 | CTX_CTRL_RS_CTX_ENABLE : 0))); | |
2010 | CTX_REG(regs, CTX_RING_HEAD, RING_HEAD(base), 0); | |
2011 | CTX_REG(regs, CTX_RING_TAIL, RING_TAIL(base), 0); | |
2012 | CTX_REG(regs, CTX_RING_BUFFER_START, RING_START(base), 0); | |
2013 | CTX_REG(regs, CTX_RING_BUFFER_CONTROL, RING_CTL(base), | |
2014 | RING_CTL_SIZE(ring->size) | RING_VALID); | |
2015 | CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0); | |
2016 | CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0); | |
2017 | CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT); | |
2018 | CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0); | |
2019 | CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0); | |
2020 | CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0); | |
2021 | if (rcs) { | |
2022 | CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0); | |
2023 | CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0); | |
2024 | CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET, | |
2025 | RING_INDIRECT_CTX_OFFSET(base), 0); | |
8670d6f9 | 2026 | |
48bb74e4 | 2027 | if (engine->wa_ctx.vma) { |
0bc40be8 | 2028 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; |
bde13ebd | 2029 | u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); |
17ee950d | 2030 | |
56e51bf0 | 2031 | regs[CTX_RCS_INDIRECT_CTX + 1] = |
097d4f1c TU |
2032 | (ggtt_offset + wa_ctx->indirect_ctx.offset) | |
2033 | (wa_ctx->indirect_ctx.size / CACHELINE_BYTES); | |
17ee950d | 2034 | |
56e51bf0 | 2035 | regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] = |
0bc40be8 | 2036 | intel_lr_indirect_ctx_offset(engine) << 6; |
17ee950d | 2037 | |
56e51bf0 | 2038 | regs[CTX_BB_PER_CTX_PTR + 1] = |
097d4f1c | 2039 | (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01; |
17ee950d | 2040 | } |
8670d6f9 | 2041 | } |
56e51bf0 TU |
2042 | |
2043 | regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED; | |
2044 | ||
2045 | CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0); | |
0d925ea0 | 2046 | /* PDP values well be assigned later if needed */ |
56e51bf0 TU |
2047 | CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), 0); |
2048 | CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), 0); | |
2049 | CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), 0); | |
2050 | CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), 0); | |
2051 | CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), 0); | |
2052 | CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), 0); | |
2053 | CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0); | |
2054 | CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0); | |
d7b2633d | 2055 | |
949e8ab3 | 2056 | if (ppgtt && i915_vm_is_48bit(&ppgtt->base)) { |
2dba3239 MT |
2057 | /* 64b PPGTT (48bit canonical) |
2058 | * PDP0_DESCRIPTOR contains the base address to PML4 and | |
2059 | * other PDP Descriptors are ignored. | |
2060 | */ | |
56e51bf0 | 2061 | ASSIGN_CTX_PML4(ppgtt, regs); |
2dba3239 MT |
2062 | } |
2063 | ||
56e51bf0 TU |
2064 | if (rcs) { |
2065 | regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); | |
2066 | CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, | |
2067 | make_rpcs(dev_priv)); | |
19f81df2 RB |
2068 | |
2069 | i915_oa_init_reg_state(engine, ctx, regs); | |
8670d6f9 | 2070 | } |
a3aabe86 CW |
2071 | } |
2072 | ||
2073 | static int | |
2074 | populate_lr_context(struct i915_gem_context *ctx, | |
2075 | struct drm_i915_gem_object *ctx_obj, | |
2076 | struct intel_engine_cs *engine, | |
2077 | struct intel_ring *ring) | |
2078 | { | |
2079 | void *vaddr; | |
2080 | int ret; | |
2081 | ||
2082 | ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); | |
2083 | if (ret) { | |
2084 | DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); | |
2085 | return ret; | |
2086 | } | |
2087 | ||
2088 | vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB); | |
2089 | if (IS_ERR(vaddr)) { | |
2090 | ret = PTR_ERR(vaddr); | |
2091 | DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret); | |
2092 | return ret; | |
2093 | } | |
a4f5ea64 | 2094 | ctx_obj->mm.dirty = true; |
a3aabe86 CW |
2095 | |
2096 | /* The second page of the context object contains some fields which must | |
2097 | * be set up prior to the first execution. */ | |
2098 | ||
2099 | execlists_init_reg_state(vaddr + LRC_STATE_PN * PAGE_SIZE, | |
2100 | ctx, engine, ring); | |
8670d6f9 | 2101 | |
7d774cac | 2102 | i915_gem_object_unpin_map(ctx_obj); |
8670d6f9 OM |
2103 | |
2104 | return 0; | |
2105 | } | |
2106 | ||
e2efd130 | 2107 | static int execlists_context_deferred_alloc(struct i915_gem_context *ctx, |
978f1e09 | 2108 | struct intel_engine_cs *engine) |
ede7d42b | 2109 | { |
8c857917 | 2110 | struct drm_i915_gem_object *ctx_obj; |
9021ad03 | 2111 | struct intel_context *ce = &ctx->engine[engine->id]; |
bf3783e5 | 2112 | struct i915_vma *vma; |
8c857917 | 2113 | uint32_t context_size; |
7e37f889 | 2114 | struct intel_ring *ring; |
8c857917 OM |
2115 | int ret; |
2116 | ||
9021ad03 | 2117 | WARN_ON(ce->state); |
ede7d42b | 2118 | |
63ffbcda | 2119 | context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE); |
8c857917 | 2120 | |
0b29c75a MT |
2121 | /* |
2122 | * Before the actual start of the context image, we insert a few pages | |
2123 | * for our own use and for sharing with the GuC. | |
2124 | */ | |
2125 | context_size += LRC_HEADER_PAGES * PAGE_SIZE; | |
d1675198 | 2126 | |
12d79d78 | 2127 | ctx_obj = i915_gem_object_create(ctx->i915, context_size); |
fe3db79b | 2128 | if (IS_ERR(ctx_obj)) { |
3126a660 | 2129 | DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n"); |
fe3db79b | 2130 | return PTR_ERR(ctx_obj); |
8c857917 OM |
2131 | } |
2132 | ||
a01cb37a | 2133 | vma = i915_vma_instance(ctx_obj, &ctx->i915->ggtt.base, NULL); |
bf3783e5 CW |
2134 | if (IS_ERR(vma)) { |
2135 | ret = PTR_ERR(vma); | |
2136 | goto error_deref_obj; | |
2137 | } | |
2138 | ||
7e37f889 | 2139 | ring = intel_engine_create_ring(engine, ctx->ring_size); |
dca33ecc CW |
2140 | if (IS_ERR(ring)) { |
2141 | ret = PTR_ERR(ring); | |
e84fe803 | 2142 | goto error_deref_obj; |
8670d6f9 OM |
2143 | } |
2144 | ||
dca33ecc | 2145 | ret = populate_lr_context(ctx, ctx_obj, engine, ring); |
8670d6f9 OM |
2146 | if (ret) { |
2147 | DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); | |
dca33ecc | 2148 | goto error_ring_free; |
84c2377f OM |
2149 | } |
2150 | ||
dca33ecc | 2151 | ce->ring = ring; |
bf3783e5 | 2152 | ce->state = vma; |
0d402a24 | 2153 | ce->initialised |= engine->init_context == NULL; |
ede7d42b OM |
2154 | |
2155 | return 0; | |
8670d6f9 | 2156 | |
dca33ecc | 2157 | error_ring_free: |
7e37f889 | 2158 | intel_ring_free(ring); |
e84fe803 | 2159 | error_deref_obj: |
f8c417cd | 2160 | i915_gem_object_put(ctx_obj); |
8670d6f9 | 2161 | return ret; |
ede7d42b | 2162 | } |
3e5b6f05 | 2163 | |
821ed7df | 2164 | void intel_lr_context_resume(struct drm_i915_private *dev_priv) |
3e5b6f05 | 2165 | { |
e2f80391 | 2166 | struct intel_engine_cs *engine; |
bafb2f7d | 2167 | struct i915_gem_context *ctx; |
3b3f1650 | 2168 | enum intel_engine_id id; |
bafb2f7d CW |
2169 | |
2170 | /* Because we emit WA_TAIL_DWORDS there may be a disparity | |
2171 | * between our bookkeeping in ce->ring->head and ce->ring->tail and | |
2172 | * that stored in context. As we only write new commands from | |
2173 | * ce->ring->tail onwards, everything before that is junk. If the GPU | |
2174 | * starts reading from its RING_HEAD from the context, it may try to | |
2175 | * execute that junk and die. | |
2176 | * | |
2177 | * So to avoid that we reset the context images upon resume. For | |
2178 | * simplicity, we just zero everything out. | |
2179 | */ | |
829a0af2 | 2180 | list_for_each_entry(ctx, &dev_priv->contexts.list, link) { |
3b3f1650 | 2181 | for_each_engine(engine, dev_priv, id) { |
bafb2f7d CW |
2182 | struct intel_context *ce = &ctx->engine[engine->id]; |
2183 | u32 *reg; | |
3e5b6f05 | 2184 | |
bafb2f7d CW |
2185 | if (!ce->state) |
2186 | continue; | |
7d774cac | 2187 | |
bafb2f7d CW |
2188 | reg = i915_gem_object_pin_map(ce->state->obj, |
2189 | I915_MAP_WB); | |
2190 | if (WARN_ON(IS_ERR(reg))) | |
2191 | continue; | |
3e5b6f05 | 2192 | |
bafb2f7d CW |
2193 | reg += LRC_STATE_PN * PAGE_SIZE / sizeof(*reg); |
2194 | reg[CTX_RING_HEAD+1] = 0; | |
2195 | reg[CTX_RING_TAIL+1] = 0; | |
3e5b6f05 | 2196 | |
a4f5ea64 | 2197 | ce->state->obj->mm.dirty = true; |
bafb2f7d | 2198 | i915_gem_object_unpin_map(ce->state->obj); |
3e5b6f05 | 2199 | |
e6ba9992 | 2200 | intel_ring_reset(ce->ring, 0); |
bafb2f7d | 2201 | } |
3e5b6f05 TD |
2202 | } |
2203 | } |