Commit | Line | Data |
---|---|---|
b20385f1 OM |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * Michel Thierry <michel.thierry@intel.com> | |
26 | * Thomas Daniel <thomas.daniel@intel.com> | |
27 | * Oscar Mateo <oscar.mateo@intel.com> | |
28 | * | |
29 | */ | |
30 | ||
73e4d07f OM |
31 | /** |
32 | * DOC: Logical Rings, Logical Ring Contexts and Execlists | |
33 | * | |
34 | * Motivation: | |
b20385f1 OM |
35 | * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". |
36 | * These expanded contexts enable a number of new abilities, especially | |
37 | * "Execlists" (also implemented in this file). | |
38 | * | |
73e4d07f OM |
39 | * One of the main differences with the legacy HW contexts is that logical |
40 | * ring contexts incorporate many more things to the context's state, like | |
41 | * PDPs or ringbuffer control registers: | |
42 | * | |
43 | * The reason why PDPs are included in the context is straightforward: as | |
44 | * PPGTTs (per-process GTTs) are actually per-context, having the PDPs | |
45 | * contained there mean you don't need to do a ppgtt->switch_mm yourself, | |
46 | * instead, the GPU will do it for you on the context switch. | |
47 | * | |
48 | * But, what about the ringbuffer control registers (head, tail, etc..)? | |
49 | * shouldn't we just need a set of those per engine command streamer? This is | |
50 | * where the name "Logical Rings" starts to make sense: by virtualizing the | |
51 | * rings, the engine cs shifts to a new "ring buffer" with every context | |
52 | * switch. When you want to submit a workload to the GPU you: A) choose your | |
53 | * context, B) find its appropriate virtualized ring, C) write commands to it | |
54 | * and then, finally, D) tell the GPU to switch to that context. | |
55 | * | |
56 | * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch | |
57 | * to a contexts is via a context execution list, ergo "Execlists". | |
58 | * | |
59 | * LRC implementation: | |
60 | * Regarding the creation of contexts, we have: | |
61 | * | |
62 | * - One global default context. | |
63 | * - One local default context for each opened fd. | |
64 | * - One local extra context for each context create ioctl call. | |
65 | * | |
66 | * Now that ringbuffers belong per-context (and not per-engine, like before) | |
67 | * and that contexts are uniquely tied to a given engine (and not reusable, | |
68 | * like before) we need: | |
69 | * | |
70 | * - One ringbuffer per-engine inside each context. | |
71 | * - One backing object per-engine inside each context. | |
72 | * | |
73 | * The global default context starts its life with these new objects fully | |
74 | * allocated and populated. The local default context for each opened fd is | |
75 | * more complex, because we don't know at creation time which engine is going | |
76 | * to use them. To handle this, we have implemented a deferred creation of LR | |
77 | * contexts: | |
78 | * | |
79 | * The local context starts its life as a hollow or blank holder, that only | |
80 | * gets populated for a given engine once we receive an execbuffer. If later | |
81 | * on we receive another execbuffer ioctl for the same context but a different | |
82 | * engine, we allocate/populate a new ringbuffer and context backing object and | |
83 | * so on. | |
84 | * | |
85 | * Finally, regarding local contexts created using the ioctl call: as they are | |
86 | * only allowed with the render ring, we can allocate & populate them right | |
87 | * away (no need to defer anything, at least for now). | |
88 | * | |
89 | * Execlists implementation: | |
b20385f1 OM |
90 | * Execlists are the new method by which, on gen8+ hardware, workloads are |
91 | * submitted for execution (as opposed to the legacy, ringbuffer-based, method). | |
73e4d07f OM |
92 | * This method works as follows: |
93 | * | |
94 | * When a request is committed, its commands (the BB start and any leading or | |
95 | * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer | |
96 | * for the appropriate context. The tail pointer in the hardware context is not | |
97 | * updated at this time, but instead, kept by the driver in the ringbuffer | |
98 | * structure. A structure representing this request is added to a request queue | |
99 | * for the appropriate engine: this structure contains a copy of the context's | |
100 | * tail after the request was written to the ring buffer and a pointer to the | |
101 | * context itself. | |
102 | * | |
103 | * If the engine's request queue was empty before the request was added, the | |
104 | * queue is processed immediately. Otherwise the queue will be processed during | |
105 | * a context switch interrupt. In any case, elements on the queue will get sent | |
106 | * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a | |
107 | * globally unique 20-bits submission ID. | |
108 | * | |
109 | * When execution of a request completes, the GPU updates the context status | |
110 | * buffer with a context complete event and generates a context switch interrupt. | |
111 | * During the interrupt handling, the driver examines the events in the buffer: | |
112 | * for each context complete event, if the announced ID matches that on the head | |
113 | * of the request queue, then that request is retired and removed from the queue. | |
114 | * | |
115 | * After processing, if any requests were retired and the queue is not empty | |
116 | * then a new execution list can be submitted. The two requests at the front of | |
117 | * the queue are next to be submitted but since a context may not occur twice in | |
118 | * an execution list, if subsequent requests have the same ID as the first then | |
119 | * the two requests must be combined. This is done simply by discarding requests | |
120 | * at the head of the queue until either only one requests is left (in which case | |
121 | * we use a NULL second context) or the first two requests have unique IDs. | |
122 | * | |
123 | * By always executing the first two requests in the queue the driver ensures | |
124 | * that the GPU is kept as busy as possible. In the case where a single context | |
125 | * completes but a second context is still executing, the request for this second | |
126 | * context will be at the head of the queue when we remove the first one. This | |
127 | * request will then be resubmitted along with a new request for a different context, | |
128 | * which will cause the hardware to continue executing the second request and queue | |
129 | * the new request (the GPU detects the condition of a context getting preempted | |
130 | * with the same context and optimizes the context switch flow by not doing | |
131 | * preemption, but just sampling the new tail pointer). | |
132 | * | |
b20385f1 | 133 | */ |
27af5eea | 134 | #include <linux/interrupt.h> |
b20385f1 OM |
135 | |
136 | #include <drm/drmP.h> | |
137 | #include <drm/i915_drm.h> | |
138 | #include "i915_drv.h" | |
3bbaba0c | 139 | #include "intel_mocs.h" |
127f1003 | 140 | |
468c6816 | 141 | #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) |
8c857917 OM |
142 | #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) |
143 | #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) | |
144 | ||
e981e7b1 TD |
145 | #define RING_EXECLIST_QFULL (1 << 0x2) |
146 | #define RING_EXECLIST1_VALID (1 << 0x3) | |
147 | #define RING_EXECLIST0_VALID (1 << 0x4) | |
148 | #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) | |
149 | #define RING_EXECLIST1_ACTIVE (1 << 0x11) | |
150 | #define RING_EXECLIST0_ACTIVE (1 << 0x12) | |
151 | ||
152 | #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) | |
153 | #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) | |
154 | #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) | |
155 | #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) | |
156 | #define GEN8_CTX_STATUS_COMPLETE (1 << 4) | |
157 | #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) | |
8670d6f9 OM |
158 | |
159 | #define CTX_LRI_HEADER_0 0x01 | |
160 | #define CTX_CONTEXT_CONTROL 0x02 | |
161 | #define CTX_RING_HEAD 0x04 | |
162 | #define CTX_RING_TAIL 0x06 | |
163 | #define CTX_RING_BUFFER_START 0x08 | |
164 | #define CTX_RING_BUFFER_CONTROL 0x0a | |
165 | #define CTX_BB_HEAD_U 0x0c | |
166 | #define CTX_BB_HEAD_L 0x0e | |
167 | #define CTX_BB_STATE 0x10 | |
168 | #define CTX_SECOND_BB_HEAD_U 0x12 | |
169 | #define CTX_SECOND_BB_HEAD_L 0x14 | |
170 | #define CTX_SECOND_BB_STATE 0x16 | |
171 | #define CTX_BB_PER_CTX_PTR 0x18 | |
172 | #define CTX_RCS_INDIRECT_CTX 0x1a | |
173 | #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c | |
174 | #define CTX_LRI_HEADER_1 0x21 | |
175 | #define CTX_CTX_TIMESTAMP 0x22 | |
176 | #define CTX_PDP3_UDW 0x24 | |
177 | #define CTX_PDP3_LDW 0x26 | |
178 | #define CTX_PDP2_UDW 0x28 | |
179 | #define CTX_PDP2_LDW 0x2a | |
180 | #define CTX_PDP1_UDW 0x2c | |
181 | #define CTX_PDP1_LDW 0x2e | |
182 | #define CTX_PDP0_UDW 0x30 | |
183 | #define CTX_PDP0_LDW 0x32 | |
184 | #define CTX_LRI_HEADER_2 0x41 | |
185 | #define CTX_R_PWR_CLK_STATE 0x42 | |
186 | #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 | |
187 | ||
84b790f8 BW |
188 | #define GEN8_CTX_VALID (1<<0) |
189 | #define GEN8_CTX_FORCE_PD_RESTORE (1<<1) | |
190 | #define GEN8_CTX_FORCE_RESTORE (1<<2) | |
191 | #define GEN8_CTX_L3LLC_COHERENT (1<<5) | |
192 | #define GEN8_CTX_PRIVILEGE (1<<8) | |
e5815a2e | 193 | |
0d925ea0 | 194 | #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \ |
f0f59a00 | 195 | (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \ |
0d925ea0 VS |
196 | (reg_state)[(pos)+1] = (val); \ |
197 | } while (0) | |
198 | ||
199 | #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \ | |
d852c7bf | 200 | const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \ |
e5815a2e MT |
201 | reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \ |
202 | reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \ | |
9244a817 | 203 | } while (0) |
e5815a2e | 204 | |
9244a817 | 205 | #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \ |
2dba3239 MT |
206 | reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \ |
207 | reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \ | |
9244a817 | 208 | } while (0) |
2dba3239 | 209 | |
84b790f8 BW |
210 | enum { |
211 | FAULT_AND_HANG = 0, | |
212 | FAULT_AND_HALT, /* Debug only */ | |
213 | FAULT_AND_STREAM, | |
214 | FAULT_AND_CONTINUE /* Unsupported */ | |
215 | }; | |
216 | #define GEN8_CTX_ID_SHIFT 32 | |
7069b144 | 217 | #define GEN8_CTX_ID_WIDTH 21 |
71562919 MT |
218 | #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 |
219 | #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26 | |
84b790f8 | 220 | |
0e93cdd4 CW |
221 | /* Typical size of the average request (2 pipecontrols and a MI_BB) */ |
222 | #define EXECLISTS_REQUEST_SIZE 64 /* bytes */ | |
223 | ||
e2efd130 | 224 | static int execlists_context_deferred_alloc(struct i915_gem_context *ctx, |
978f1e09 | 225 | struct intel_engine_cs *engine); |
e2efd130 | 226 | static int intel_lr_context_pin(struct i915_gem_context *ctx, |
e5292823 | 227 | struct intel_engine_cs *engine); |
7ba717cf | 228 | |
73e4d07f OM |
229 | /** |
230 | * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists | |
14bb2c11 | 231 | * @dev_priv: i915 device private |
73e4d07f OM |
232 | * @enable_execlists: value of i915.enable_execlists module parameter. |
233 | * | |
234 | * Only certain platforms support Execlists (the prerequisites being | |
27401d12 | 235 | * support for Logical Ring Contexts and Aliasing PPGTT or better). |
73e4d07f OM |
236 | * |
237 | * Return: 1 if Execlists is supported and has to be enabled. | |
238 | */ | |
c033666a | 239 | int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv, int enable_execlists) |
127f1003 | 240 | { |
a0bd6c31 ZL |
241 | /* On platforms with execlist available, vGPU will only |
242 | * support execlist mode, no ring buffer mode. | |
243 | */ | |
c033666a | 244 | if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && intel_vgpu_active(dev_priv)) |
a0bd6c31 ZL |
245 | return 1; |
246 | ||
c033666a | 247 | if (INTEL_GEN(dev_priv) >= 9) |
70ee45e1 DL |
248 | return 1; |
249 | ||
127f1003 OM |
250 | if (enable_execlists == 0) |
251 | return 0; | |
252 | ||
5a21b665 DV |
253 | if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && |
254 | USES_PPGTT(dev_priv) && | |
255 | i915.use_mmio_flip >= 0) | |
127f1003 OM |
256 | return 1; |
257 | ||
258 | return 0; | |
259 | } | |
ede7d42b | 260 | |
ca82580c | 261 | static void |
0bc40be8 | 262 | logical_ring_init_platform_invariants(struct intel_engine_cs *engine) |
ca82580c | 263 | { |
c033666a | 264 | struct drm_i915_private *dev_priv = engine->i915; |
ca82580c | 265 | |
c033666a | 266 | if (IS_GEN8(dev_priv) || IS_GEN9(dev_priv)) |
0bc40be8 | 267 | engine->idle_lite_restore_wa = ~0; |
c6a2ac71 | 268 | |
c033666a CW |
269 | engine->disable_lite_restore_wa = (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) || |
270 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) && | |
0bc40be8 | 271 | (engine->id == VCS || engine->id == VCS2); |
ca82580c | 272 | |
0bc40be8 | 273 | engine->ctx_desc_template = GEN8_CTX_VALID; |
c033666a | 274 | if (IS_GEN8(dev_priv)) |
0bc40be8 TU |
275 | engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT; |
276 | engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE; | |
ca82580c TU |
277 | |
278 | /* TODO: WaDisableLiteRestore when we start using semaphore | |
279 | * signalling between Command Streamers */ | |
280 | /* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */ | |
281 | ||
282 | /* WaEnableForceRestoreInCtxtDescForVCS:skl */ | |
283 | /* WaEnableForceRestoreInCtxtDescForVCS:bxt */ | |
0bc40be8 TU |
284 | if (engine->disable_lite_restore_wa) |
285 | engine->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; | |
ca82580c TU |
286 | } |
287 | ||
73e4d07f | 288 | /** |
ca82580c TU |
289 | * intel_lr_context_descriptor_update() - calculate & cache the descriptor |
290 | * descriptor for a pinned context | |
73e4d07f | 291 | * |
ca82580c | 292 | * @ctx: Context to work on |
9021ad03 | 293 | * @engine: Engine the descriptor will be used with |
73e4d07f | 294 | * |
ca82580c TU |
295 | * The context descriptor encodes various attributes of a context, |
296 | * including its GTT address and some flags. Because it's fairly | |
297 | * expensive to calculate, we'll just do it once and cache the result, | |
298 | * which remains valid until the context is unpinned. | |
299 | * | |
300 | * This is what a descriptor looks like, from LSB to MSB: | |
ef87bba8 | 301 | * bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template) |
ca82580c | 302 | * bits 12-31: LRCA, GTT address of (the HWSP of) this context |
7069b144 | 303 | * bits 32-52: ctx ID, a globally unique tag |
ef87bba8 CW |
304 | * bits 53-54: mbz, reserved for use by hardware |
305 | * bits 55-63: group ID, currently unused and set to 0 | |
73e4d07f | 306 | */ |
ca82580c | 307 | static void |
e2efd130 | 308 | intel_lr_context_descriptor_update(struct i915_gem_context *ctx, |
0bc40be8 | 309 | struct intel_engine_cs *engine) |
84b790f8 | 310 | { |
9021ad03 | 311 | struct intel_context *ce = &ctx->engine[engine->id]; |
7069b144 | 312 | u64 desc; |
84b790f8 | 313 | |
7069b144 | 314 | BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH)); |
84b790f8 | 315 | |
c01fc532 ZW |
316 | desc = ctx->desc_template; /* bits 3-4 */ |
317 | desc |= engine->ctx_desc_template; /* bits 0-11 */ | |
9021ad03 CW |
318 | desc |= ce->lrc_vma->node.start + LRC_PPHWSP_PN * PAGE_SIZE; |
319 | /* bits 12-31 */ | |
7069b144 | 320 | desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */ |
5af05fef | 321 | |
9021ad03 | 322 | ce->lrc_desc = desc; |
5af05fef MT |
323 | } |
324 | ||
e2efd130 | 325 | uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx, |
0bc40be8 | 326 | struct intel_engine_cs *engine) |
84b790f8 | 327 | { |
0bc40be8 | 328 | return ctx->engine[engine->id].lrc_desc; |
ca82580c | 329 | } |
203a571b | 330 | |
cc3c4253 MK |
331 | static void execlists_elsp_write(struct drm_i915_gem_request *rq0, |
332 | struct drm_i915_gem_request *rq1) | |
84b790f8 | 333 | { |
cc3c4253 | 334 | |
4a570db5 | 335 | struct intel_engine_cs *engine = rq0->engine; |
c033666a | 336 | struct drm_i915_private *dev_priv = rq0->i915; |
1cff8cc3 | 337 | uint64_t desc[2]; |
84b790f8 | 338 | |
1cff8cc3 | 339 | if (rq1) { |
4a570db5 | 340 | desc[1] = intel_lr_context_descriptor(rq1->ctx, rq1->engine); |
1cff8cc3 MK |
341 | rq1->elsp_submitted++; |
342 | } else { | |
343 | desc[1] = 0; | |
344 | } | |
84b790f8 | 345 | |
4a570db5 | 346 | desc[0] = intel_lr_context_descriptor(rq0->ctx, rq0->engine); |
1cff8cc3 | 347 | rq0->elsp_submitted++; |
84b790f8 | 348 | |
1cff8cc3 | 349 | /* You must always write both descriptors in the order below. */ |
e2f80391 TU |
350 | I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[1])); |
351 | I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[1])); | |
6daccb0b | 352 | |
e2f80391 | 353 | I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[0])); |
84b790f8 | 354 | /* The context is automatically loaded after the following */ |
e2f80391 | 355 | I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[0])); |
84b790f8 | 356 | |
1cff8cc3 | 357 | /* ELSP is a wo register, use another nearby reg for posting */ |
e2f80391 | 358 | POSTING_READ_FW(RING_EXECLIST_STATUS_LO(engine)); |
84b790f8 BW |
359 | } |
360 | ||
c6a2ac71 TU |
361 | static void |
362 | execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state) | |
363 | { | |
364 | ASSIGN_CTX_PDP(ppgtt, reg_state, 3); | |
365 | ASSIGN_CTX_PDP(ppgtt, reg_state, 2); | |
366 | ASSIGN_CTX_PDP(ppgtt, reg_state, 1); | |
367 | ASSIGN_CTX_PDP(ppgtt, reg_state, 0); | |
368 | } | |
369 | ||
370 | static void execlists_update_context(struct drm_i915_gem_request *rq) | |
ae1250b9 | 371 | { |
4a570db5 | 372 | struct intel_engine_cs *engine = rq->engine; |
05d9824b | 373 | struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt; |
e2f80391 | 374 | uint32_t *reg_state = rq->ctx->engine[engine->id].lrc_reg_state; |
ae1250b9 | 375 | |
05d9824b | 376 | reg_state[CTX_RING_TAIL+1] = rq->tail; |
ae1250b9 | 377 | |
c6a2ac71 TU |
378 | /* True 32b PPGTT with dynamic page allocation: update PDP |
379 | * registers and point the unallocated PDPs to scratch page. | |
380 | * PML4 is allocated during ppgtt init, so this is not needed | |
381 | * in 48-bit mode. | |
382 | */ | |
383 | if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) | |
384 | execlists_update_context_pdps(ppgtt, reg_state); | |
ae1250b9 OM |
385 | } |
386 | ||
d8cb8875 MK |
387 | static void execlists_submit_requests(struct drm_i915_gem_request *rq0, |
388 | struct drm_i915_gem_request *rq1) | |
84b790f8 | 389 | { |
26720ab9 | 390 | struct drm_i915_private *dev_priv = rq0->i915; |
3756685a | 391 | unsigned int fw_domains = rq0->engine->fw_domains; |
26720ab9 | 392 | |
05d9824b | 393 | execlists_update_context(rq0); |
d8cb8875 | 394 | |
cc3c4253 | 395 | if (rq1) |
05d9824b | 396 | execlists_update_context(rq1); |
84b790f8 | 397 | |
27af5eea | 398 | spin_lock_irq(&dev_priv->uncore.lock); |
3756685a | 399 | intel_uncore_forcewake_get__locked(dev_priv, fw_domains); |
26720ab9 | 400 | |
cc3c4253 | 401 | execlists_elsp_write(rq0, rq1); |
26720ab9 | 402 | |
3756685a | 403 | intel_uncore_forcewake_put__locked(dev_priv, fw_domains); |
27af5eea | 404 | spin_unlock_irq(&dev_priv->uncore.lock); |
84b790f8 BW |
405 | } |
406 | ||
3c7ba635 ZW |
407 | static inline void execlists_context_status_change( |
408 | struct drm_i915_gem_request *rq, | |
409 | unsigned long status) | |
410 | { | |
411 | /* | |
412 | * Only used when GVT-g is enabled now. When GVT-g is disabled, | |
413 | * The compiler should eliminate this function as dead-code. | |
414 | */ | |
415 | if (!IS_ENABLED(CONFIG_DRM_I915_GVT)) | |
416 | return; | |
417 | ||
418 | atomic_notifier_call_chain(&rq->ctx->status_notifier, status, rq); | |
419 | } | |
420 | ||
26720ab9 | 421 | static void execlists_context_unqueue(struct intel_engine_cs *engine) |
acdd884a | 422 | { |
6d3d8274 | 423 | struct drm_i915_gem_request *req0 = NULL, *req1 = NULL; |
c6a2ac71 | 424 | struct drm_i915_gem_request *cursor, *tmp; |
e981e7b1 | 425 | |
0bc40be8 | 426 | assert_spin_locked(&engine->execlist_lock); |
acdd884a | 427 | |
779949f4 PA |
428 | /* |
429 | * If irqs are not active generate a warning as batches that finish | |
430 | * without the irqs may get lost and a GPU Hang may occur. | |
431 | */ | |
c033666a | 432 | WARN_ON(!intel_irqs_enabled(engine->i915)); |
779949f4 | 433 | |
acdd884a | 434 | /* Try to read in pairs */ |
0bc40be8 | 435 | list_for_each_entry_safe(cursor, tmp, &engine->execlist_queue, |
acdd884a MT |
436 | execlist_link) { |
437 | if (!req0) { | |
438 | req0 = cursor; | |
6d3d8274 | 439 | } else if (req0->ctx == cursor->ctx) { |
acdd884a MT |
440 | /* Same ctx: ignore first request, as second request |
441 | * will update tail past first request's workload */ | |
e1fee72c | 442 | cursor->elsp_submitted = req0->elsp_submitted; |
e39d42fa TU |
443 | list_del(&req0->execlist_link); |
444 | i915_gem_request_unreference(req0); | |
acdd884a MT |
445 | req0 = cursor; |
446 | } else { | |
80a9a8db ZW |
447 | if (IS_ENABLED(CONFIG_DRM_I915_GVT)) { |
448 | /* | |
449 | * req0 (after merged) ctx requires single | |
450 | * submission, stop picking | |
451 | */ | |
452 | if (req0->ctx->execlists_force_single_submission) | |
453 | break; | |
454 | /* | |
455 | * req0 ctx doesn't require single submission, | |
456 | * but next req ctx requires, stop picking | |
457 | */ | |
458 | if (cursor->ctx->execlists_force_single_submission) | |
459 | break; | |
460 | } | |
acdd884a | 461 | req1 = cursor; |
c6a2ac71 | 462 | WARN_ON(req1->elsp_submitted); |
acdd884a MT |
463 | break; |
464 | } | |
465 | } | |
466 | ||
c6a2ac71 TU |
467 | if (unlikely(!req0)) |
468 | return; | |
469 | ||
3c7ba635 ZW |
470 | execlists_context_status_change(req0, INTEL_CONTEXT_SCHEDULE_IN); |
471 | ||
472 | if (req1) | |
473 | execlists_context_status_change(req1, | |
474 | INTEL_CONTEXT_SCHEDULE_IN); | |
475 | ||
0bc40be8 | 476 | if (req0->elsp_submitted & engine->idle_lite_restore_wa) { |
53292cdb | 477 | /* |
c6a2ac71 TU |
478 | * WaIdleLiteRestore: make sure we never cause a lite restore |
479 | * with HEAD==TAIL. | |
480 | * | |
481 | * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL as we | |
482 | * resubmit the request. See gen8_emit_request() for where we | |
483 | * prepare the padding after the end of the request. | |
53292cdb | 484 | */ |
c6a2ac71 | 485 | struct intel_ringbuffer *ringbuf; |
53292cdb | 486 | |
0bc40be8 | 487 | ringbuf = req0->ctx->engine[engine->id].ringbuf; |
c6a2ac71 TU |
488 | req0->tail += 8; |
489 | req0->tail &= ringbuf->size - 1; | |
53292cdb MT |
490 | } |
491 | ||
d8cb8875 | 492 | execlists_submit_requests(req0, req1); |
acdd884a MT |
493 | } |
494 | ||
c6a2ac71 | 495 | static unsigned int |
e39d42fa | 496 | execlists_check_remove_request(struct intel_engine_cs *engine, u32 ctx_id) |
e981e7b1 | 497 | { |
6d3d8274 | 498 | struct drm_i915_gem_request *head_req; |
e981e7b1 | 499 | |
0bc40be8 | 500 | assert_spin_locked(&engine->execlist_lock); |
e981e7b1 | 501 | |
0bc40be8 | 502 | head_req = list_first_entry_or_null(&engine->execlist_queue, |
6d3d8274 | 503 | struct drm_i915_gem_request, |
e981e7b1 TD |
504 | execlist_link); |
505 | ||
e39d42fa TU |
506 | if (WARN_ON(!head_req || (head_req->ctx_hw_id != ctx_id))) |
507 | return 0; | |
c6a2ac71 TU |
508 | |
509 | WARN(head_req->elsp_submitted == 0, "Never submitted head request\n"); | |
510 | ||
511 | if (--head_req->elsp_submitted > 0) | |
512 | return 0; | |
513 | ||
3c7ba635 ZW |
514 | execlists_context_status_change(head_req, INTEL_CONTEXT_SCHEDULE_OUT); |
515 | ||
e39d42fa TU |
516 | list_del(&head_req->execlist_link); |
517 | i915_gem_request_unreference(head_req); | |
e981e7b1 | 518 | |
c6a2ac71 | 519 | return 1; |
e981e7b1 TD |
520 | } |
521 | ||
c6a2ac71 | 522 | static u32 |
0bc40be8 | 523 | get_context_status(struct intel_engine_cs *engine, unsigned int read_pointer, |
c6a2ac71 | 524 | u32 *context_id) |
91a41032 | 525 | { |
c033666a | 526 | struct drm_i915_private *dev_priv = engine->i915; |
c6a2ac71 | 527 | u32 status; |
91a41032 | 528 | |
c6a2ac71 TU |
529 | read_pointer %= GEN8_CSB_ENTRIES; |
530 | ||
0bc40be8 | 531 | status = I915_READ_FW(RING_CONTEXT_STATUS_BUF_LO(engine, read_pointer)); |
c6a2ac71 TU |
532 | |
533 | if (status & GEN8_CTX_STATUS_IDLE_ACTIVE) | |
534 | return 0; | |
91a41032 | 535 | |
0bc40be8 | 536 | *context_id = I915_READ_FW(RING_CONTEXT_STATUS_BUF_HI(engine, |
c6a2ac71 TU |
537 | read_pointer)); |
538 | ||
539 | return status; | |
91a41032 BW |
540 | } |
541 | ||
73e4d07f | 542 | /** |
3f7531c3 | 543 | * intel_lrc_irq_handler() - handle Context Switch interrupts |
14bb2c11 | 544 | * @data: tasklet handler passed in unsigned long |
73e4d07f OM |
545 | * |
546 | * Check the unread Context Status Buffers and manage the submission of new | |
547 | * contexts to the ELSP accordingly. | |
548 | */ | |
27af5eea | 549 | static void intel_lrc_irq_handler(unsigned long data) |
e981e7b1 | 550 | { |
27af5eea | 551 | struct intel_engine_cs *engine = (struct intel_engine_cs *)data; |
c033666a | 552 | struct drm_i915_private *dev_priv = engine->i915; |
e981e7b1 | 553 | u32 status_pointer; |
c6a2ac71 | 554 | unsigned int read_pointer, write_pointer; |
26720ab9 TU |
555 | u32 csb[GEN8_CSB_ENTRIES][2]; |
556 | unsigned int csb_read = 0, i; | |
c6a2ac71 TU |
557 | unsigned int submit_contexts = 0; |
558 | ||
3756685a | 559 | intel_uncore_forcewake_get(dev_priv, engine->fw_domains); |
c6a2ac71 | 560 | |
0bc40be8 | 561 | status_pointer = I915_READ_FW(RING_CONTEXT_STATUS_PTR(engine)); |
e981e7b1 | 562 | |
0bc40be8 | 563 | read_pointer = engine->next_context_status_buffer; |
5590a5f0 | 564 | write_pointer = GEN8_CSB_WRITE_PTR(status_pointer); |
e981e7b1 | 565 | if (read_pointer > write_pointer) |
dfc53c5e | 566 | write_pointer += GEN8_CSB_ENTRIES; |
e981e7b1 | 567 | |
e981e7b1 | 568 | while (read_pointer < write_pointer) { |
26720ab9 TU |
569 | if (WARN_ON_ONCE(csb_read == GEN8_CSB_ENTRIES)) |
570 | break; | |
571 | csb[csb_read][0] = get_context_status(engine, ++read_pointer, | |
572 | &csb[csb_read][1]); | |
573 | csb_read++; | |
574 | } | |
91a41032 | 575 | |
26720ab9 TU |
576 | engine->next_context_status_buffer = write_pointer % GEN8_CSB_ENTRIES; |
577 | ||
578 | /* Update the read pointer to the old write pointer. Manual ringbuffer | |
579 | * management ftw </sarcasm> */ | |
580 | I915_WRITE_FW(RING_CONTEXT_STATUS_PTR(engine), | |
581 | _MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, | |
582 | engine->next_context_status_buffer << 8)); | |
583 | ||
3756685a | 584 | intel_uncore_forcewake_put(dev_priv, engine->fw_domains); |
26720ab9 TU |
585 | |
586 | spin_lock(&engine->execlist_lock); | |
587 | ||
588 | for (i = 0; i < csb_read; i++) { | |
589 | if (unlikely(csb[i][0] & GEN8_CTX_STATUS_PREEMPTED)) { | |
590 | if (csb[i][0] & GEN8_CTX_STATUS_LITE_RESTORE) { | |
591 | if (execlists_check_remove_request(engine, csb[i][1])) | |
e1fee72c OM |
592 | WARN(1, "Lite Restored request removed from queue\n"); |
593 | } else | |
594 | WARN(1, "Preemption without Lite Restore\n"); | |
595 | } | |
596 | ||
26720ab9 | 597 | if (csb[i][0] & (GEN8_CTX_STATUS_ACTIVE_IDLE | |
c6a2ac71 TU |
598 | GEN8_CTX_STATUS_ELEMENT_SWITCH)) |
599 | submit_contexts += | |
26720ab9 | 600 | execlists_check_remove_request(engine, csb[i][1]); |
e981e7b1 TD |
601 | } |
602 | ||
c6a2ac71 | 603 | if (submit_contexts) { |
0bc40be8 | 604 | if (!engine->disable_lite_restore_wa || |
26720ab9 TU |
605 | (csb[i][0] & GEN8_CTX_STATUS_ACTIVE_IDLE)) |
606 | execlists_context_unqueue(engine); | |
5af05fef | 607 | } |
e981e7b1 | 608 | |
0bc40be8 | 609 | spin_unlock(&engine->execlist_lock); |
c6a2ac71 TU |
610 | |
611 | if (unlikely(submit_contexts > 2)) | |
612 | DRM_ERROR("More than two context complete events?\n"); | |
e981e7b1 TD |
613 | } |
614 | ||
c6a2ac71 | 615 | static void execlists_context_queue(struct drm_i915_gem_request *request) |
acdd884a | 616 | { |
4a570db5 | 617 | struct intel_engine_cs *engine = request->engine; |
6d3d8274 | 618 | struct drm_i915_gem_request *cursor; |
f1ad5a1f | 619 | int num_elements = 0; |
acdd884a | 620 | |
27af5eea | 621 | spin_lock_bh(&engine->execlist_lock); |
acdd884a | 622 | |
e2f80391 | 623 | list_for_each_entry(cursor, &engine->execlist_queue, execlist_link) |
f1ad5a1f OM |
624 | if (++num_elements > 2) |
625 | break; | |
626 | ||
627 | if (num_elements > 2) { | |
6d3d8274 | 628 | struct drm_i915_gem_request *tail_req; |
f1ad5a1f | 629 | |
e2f80391 | 630 | tail_req = list_last_entry(&engine->execlist_queue, |
6d3d8274 | 631 | struct drm_i915_gem_request, |
f1ad5a1f OM |
632 | execlist_link); |
633 | ||
ae70797d | 634 | if (request->ctx == tail_req->ctx) { |
f1ad5a1f | 635 | WARN(tail_req->elsp_submitted != 0, |
7ba717cf | 636 | "More than 2 already-submitted reqs queued\n"); |
e39d42fa TU |
637 | list_del(&tail_req->execlist_link); |
638 | i915_gem_request_unreference(tail_req); | |
f1ad5a1f OM |
639 | } |
640 | } | |
641 | ||
e39d42fa | 642 | i915_gem_request_reference(request); |
e2f80391 | 643 | list_add_tail(&request->execlist_link, &engine->execlist_queue); |
a3d12761 | 644 | request->ctx_hw_id = request->ctx->hw_id; |
f1ad5a1f | 645 | if (num_elements == 0) |
e2f80391 | 646 | execlists_context_unqueue(engine); |
acdd884a | 647 | |
27af5eea | 648 | spin_unlock_bh(&engine->execlist_lock); |
acdd884a MT |
649 | } |
650 | ||
2f20055d | 651 | static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req) |
ba8b7ccb | 652 | { |
4a570db5 | 653 | struct intel_engine_cs *engine = req->engine; |
ba8b7ccb OM |
654 | uint32_t flush_domains; |
655 | int ret; | |
656 | ||
657 | flush_domains = 0; | |
e2f80391 | 658 | if (engine->gpu_caches_dirty) |
ba8b7ccb OM |
659 | flush_domains = I915_GEM_GPU_DOMAINS; |
660 | ||
e2f80391 | 661 | ret = engine->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
ba8b7ccb OM |
662 | if (ret) |
663 | return ret; | |
664 | ||
e2f80391 | 665 | engine->gpu_caches_dirty = false; |
ba8b7ccb OM |
666 | return 0; |
667 | } | |
668 | ||
535fbe82 | 669 | static int execlists_move_to_gpu(struct drm_i915_gem_request *req, |
ba8b7ccb OM |
670 | struct list_head *vmas) |
671 | { | |
666796da | 672 | const unsigned other_rings = ~intel_engine_flag(req->engine); |
ba8b7ccb OM |
673 | struct i915_vma *vma; |
674 | uint32_t flush_domains = 0; | |
675 | bool flush_chipset = false; | |
676 | int ret; | |
677 | ||
678 | list_for_each_entry(vma, vmas, exec_list) { | |
679 | struct drm_i915_gem_object *obj = vma->obj; | |
680 | ||
03ade511 | 681 | if (obj->active & other_rings) { |
4a570db5 | 682 | ret = i915_gem_object_sync(obj, req->engine, &req); |
03ade511 CW |
683 | if (ret) |
684 | return ret; | |
685 | } | |
ba8b7ccb OM |
686 | |
687 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
688 | flush_chipset |= i915_gem_clflush_object(obj, false); | |
689 | ||
690 | flush_domains |= obj->base.write_domain; | |
691 | } | |
692 | ||
693 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
694 | wmb(); | |
695 | ||
696 | /* Unconditionally invalidate gpu caches and ensure that we do flush | |
697 | * any residual writes from the previous batch. | |
698 | */ | |
2f20055d | 699 | return logical_ring_invalidate_all_caches(req); |
ba8b7ccb OM |
700 | } |
701 | ||
40e895ce | 702 | int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request) |
bc0dce3f | 703 | { |
24f1d3cc | 704 | struct intel_engine_cs *engine = request->engine; |
9021ad03 | 705 | struct intel_context *ce = &request->ctx->engine[engine->id]; |
bfa01200 | 706 | int ret; |
bc0dce3f | 707 | |
6310346e CW |
708 | /* Flush enough space to reduce the likelihood of waiting after |
709 | * we start building the request - in which case we will just | |
710 | * have to repeat work. | |
711 | */ | |
0e93cdd4 | 712 | request->reserved_space += EXECLISTS_REQUEST_SIZE; |
6310346e | 713 | |
9021ad03 | 714 | if (!ce->state) { |
978f1e09 CW |
715 | ret = execlists_context_deferred_alloc(request->ctx, engine); |
716 | if (ret) | |
717 | return ret; | |
718 | } | |
719 | ||
9021ad03 | 720 | request->ringbuf = ce->ringbuf; |
f3cc01f0 | 721 | |
a7e02199 AD |
722 | if (i915.enable_guc_submission) { |
723 | /* | |
724 | * Check that the GuC has space for the request before | |
725 | * going any further, as the i915_add_request() call | |
726 | * later on mustn't fail ... | |
727 | */ | |
7c2c270d | 728 | ret = i915_guc_wq_check_space(request); |
a7e02199 AD |
729 | if (ret) |
730 | return ret; | |
731 | } | |
732 | ||
24f1d3cc CW |
733 | ret = intel_lr_context_pin(request->ctx, engine); |
734 | if (ret) | |
735 | return ret; | |
e28e404c | 736 | |
bfa01200 CW |
737 | ret = intel_ring_begin(request, 0); |
738 | if (ret) | |
739 | goto err_unpin; | |
740 | ||
9021ad03 | 741 | if (!ce->initialised) { |
24f1d3cc CW |
742 | ret = engine->init_context(request); |
743 | if (ret) | |
744 | goto err_unpin; | |
745 | ||
9021ad03 | 746 | ce->initialised = true; |
24f1d3cc CW |
747 | } |
748 | ||
749 | /* Note that after this point, we have committed to using | |
750 | * this request as it is being used to both track the | |
751 | * state of engine initialisation and liveness of the | |
752 | * golden renderstate above. Think twice before you try | |
753 | * to cancel/unwind this request now. | |
754 | */ | |
755 | ||
0e93cdd4 | 756 | request->reserved_space -= EXECLISTS_REQUEST_SIZE; |
bfa01200 CW |
757 | return 0; |
758 | ||
759 | err_unpin: | |
24f1d3cc | 760 | intel_lr_context_unpin(request->ctx, engine); |
e28e404c | 761 | return ret; |
bc0dce3f JH |
762 | } |
763 | ||
bc0dce3f JH |
764 | /* |
765 | * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload | |
ae70797d | 766 | * @request: Request to advance the logical ringbuffer of. |
bc0dce3f JH |
767 | * |
768 | * The tail is updated in our logical ringbuffer struct, not in the actual context. What | |
769 | * really happens during submission is that the context and current tail will be placed | |
770 | * on a queue waiting for the ELSP to be ready to accept a new context submission. At that | |
771 | * point, the tail *inside* the context is updated and the ELSP written to. | |
772 | */ | |
7c17d377 | 773 | static int |
ae70797d | 774 | intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request) |
bc0dce3f | 775 | { |
7c17d377 | 776 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
4a570db5 | 777 | struct intel_engine_cs *engine = request->engine; |
bc0dce3f | 778 | |
7c17d377 CW |
779 | intel_logical_ring_advance(ringbuf); |
780 | request->tail = ringbuf->tail; | |
bc0dce3f | 781 | |
7c17d377 CW |
782 | /* |
783 | * Here we add two extra NOOPs as padding to avoid | |
784 | * lite restore of a context with HEAD==TAIL. | |
785 | * | |
786 | * Caller must reserve WA_TAIL_DWORDS for us! | |
787 | */ | |
788 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
789 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
790 | intel_logical_ring_advance(ringbuf); | |
d1675198 | 791 | |
a16a4052 CW |
792 | /* We keep the previous context alive until we retire the following |
793 | * request. This ensures that any the context object is still pinned | |
794 | * for any residual writes the HW makes into it on the context switch | |
795 | * into the next object following the breadcrumb. Otherwise, we may | |
796 | * retire the context too early. | |
797 | */ | |
798 | request->previous_context = engine->last_context; | |
799 | engine->last_context = request->ctx; | |
f4e2dece | 800 | |
7c2c270d DG |
801 | if (i915.enable_guc_submission) |
802 | i915_guc_submit(request); | |
d1675198 AD |
803 | else |
804 | execlists_context_queue(request); | |
7c17d377 CW |
805 | |
806 | return 0; | |
bc0dce3f JH |
807 | } |
808 | ||
73e4d07f OM |
809 | /** |
810 | * execlists_submission() - submit a batchbuffer for execution, Execlists style | |
14bb2c11 | 811 | * @params: execbuffer call parameters. |
73e4d07f OM |
812 | * @args: execbuffer call arguments. |
813 | * @vmas: list of vmas. | |
73e4d07f OM |
814 | * |
815 | * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts | |
816 | * away the submission details of the execbuffer ioctl call. | |
817 | * | |
818 | * Return: non-zero if the submission fails. | |
819 | */ | |
5f19e2bf | 820 | int intel_execlists_submission(struct i915_execbuffer_params *params, |
454afebd | 821 | struct drm_i915_gem_execbuffer2 *args, |
5f19e2bf | 822 | struct list_head *vmas) |
454afebd | 823 | { |
5f19e2bf | 824 | struct drm_device *dev = params->dev; |
4a570db5 | 825 | struct intel_engine_cs *engine = params->engine; |
fac5e23e | 826 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 827 | struct intel_ringbuffer *ringbuf = params->ctx->engine[engine->id].ringbuf; |
5f19e2bf | 828 | u64 exec_start; |
ba8b7ccb OM |
829 | int instp_mode; |
830 | u32 instp_mask; | |
831 | int ret; | |
832 | ||
833 | instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK; | |
834 | instp_mask = I915_EXEC_CONSTANTS_MASK; | |
835 | switch (instp_mode) { | |
836 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
837 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
838 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
4a570db5 | 839 | if (instp_mode != 0 && engine != &dev_priv->engine[RCS]) { |
ba8b7ccb OM |
840 | DRM_DEBUG("non-0 rel constants mode on non-RCS\n"); |
841 | return -EINVAL; | |
842 | } | |
843 | ||
844 | if (instp_mode != dev_priv->relative_constants_mode) { | |
845 | if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { | |
846 | DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); | |
847 | return -EINVAL; | |
848 | } | |
849 | ||
850 | /* The HW changed the meaning on this bit on gen6 */ | |
851 | instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
852 | } | |
853 | break; | |
854 | default: | |
855 | DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode); | |
856 | return -EINVAL; | |
857 | } | |
858 | ||
ba8b7ccb OM |
859 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { |
860 | DRM_DEBUG("sol reset is gen7 only\n"); | |
861 | return -EINVAL; | |
862 | } | |
863 | ||
535fbe82 | 864 | ret = execlists_move_to_gpu(params->request, vmas); |
ba8b7ccb OM |
865 | if (ret) |
866 | return ret; | |
867 | ||
4a570db5 | 868 | if (engine == &dev_priv->engine[RCS] && |
ba8b7ccb | 869 | instp_mode != dev_priv->relative_constants_mode) { |
987046ad | 870 | ret = intel_ring_begin(params->request, 4); |
ba8b7ccb OM |
871 | if (ret) |
872 | return ret; | |
873 | ||
874 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
875 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1)); | |
f92a9162 | 876 | intel_logical_ring_emit_reg(ringbuf, INSTPM); |
ba8b7ccb OM |
877 | intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode); |
878 | intel_logical_ring_advance(ringbuf); | |
879 | ||
880 | dev_priv->relative_constants_mode = instp_mode; | |
881 | } | |
882 | ||
5f19e2bf JH |
883 | exec_start = params->batch_obj_vm_offset + |
884 | args->batch_start_offset; | |
885 | ||
e2f80391 | 886 | ret = engine->emit_bb_start(params->request, exec_start, params->dispatch_flags); |
ba8b7ccb OM |
887 | if (ret) |
888 | return ret; | |
889 | ||
95c24161 | 890 | trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags); |
5e4be7bd | 891 | |
8a8edb59 | 892 | i915_gem_execbuffer_move_to_active(vmas, params->request); |
ba8b7ccb | 893 | |
454afebd OM |
894 | return 0; |
895 | } | |
896 | ||
e39d42fa | 897 | void intel_execlists_cancel_requests(struct intel_engine_cs *engine) |
c86ee3a9 | 898 | { |
6d3d8274 | 899 | struct drm_i915_gem_request *req, *tmp; |
e39d42fa | 900 | LIST_HEAD(cancel_list); |
c86ee3a9 | 901 | |
91c8a326 | 902 | WARN_ON(!mutex_is_locked(&engine->i915->drm.struct_mutex)); |
c86ee3a9 | 903 | |
27af5eea | 904 | spin_lock_bh(&engine->execlist_lock); |
e39d42fa | 905 | list_replace_init(&engine->execlist_queue, &cancel_list); |
27af5eea | 906 | spin_unlock_bh(&engine->execlist_lock); |
c86ee3a9 | 907 | |
e39d42fa | 908 | list_for_each_entry_safe(req, tmp, &cancel_list, execlist_link) { |
c86ee3a9 | 909 | list_del(&req->execlist_link); |
f8210795 | 910 | i915_gem_request_unreference(req); |
c86ee3a9 TD |
911 | } |
912 | } | |
913 | ||
0bc40be8 | 914 | void intel_logical_ring_stop(struct intel_engine_cs *engine) |
454afebd | 915 | { |
c033666a | 916 | struct drm_i915_private *dev_priv = engine->i915; |
9832b9da OM |
917 | int ret; |
918 | ||
117897f4 | 919 | if (!intel_engine_initialized(engine)) |
9832b9da OM |
920 | return; |
921 | ||
666796da | 922 | ret = intel_engine_idle(engine); |
f4457ae7 | 923 | if (ret) |
9832b9da | 924 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
0bc40be8 | 925 | engine->name, ret); |
9832b9da OM |
926 | |
927 | /* TODO: Is this correct with Execlists enabled? */ | |
0bc40be8 | 928 | I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); |
3e7941a1 CW |
929 | if (intel_wait_for_register(dev_priv, |
930 | RING_MI_MODE(engine->mmio_base), | |
931 | MODE_IDLE, MODE_IDLE, | |
932 | 1000)) { | |
0bc40be8 | 933 | DRM_ERROR("%s :timed out trying to stop ring\n", engine->name); |
9832b9da OM |
934 | return; |
935 | } | |
0bc40be8 | 936 | I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); |
454afebd OM |
937 | } |
938 | ||
4866d729 | 939 | int logical_ring_flush_all_caches(struct drm_i915_gem_request *req) |
48e29f55 | 940 | { |
4a570db5 | 941 | struct intel_engine_cs *engine = req->engine; |
48e29f55 OM |
942 | int ret; |
943 | ||
e2f80391 | 944 | if (!engine->gpu_caches_dirty) |
48e29f55 OM |
945 | return 0; |
946 | ||
e2f80391 | 947 | ret = engine->emit_flush(req, 0, I915_GEM_GPU_DOMAINS); |
48e29f55 OM |
948 | if (ret) |
949 | return ret; | |
950 | ||
e2f80391 | 951 | engine->gpu_caches_dirty = false; |
48e29f55 OM |
952 | return 0; |
953 | } | |
954 | ||
e2efd130 | 955 | static int intel_lr_context_pin(struct i915_gem_context *ctx, |
24f1d3cc | 956 | struct intel_engine_cs *engine) |
dcb4c12a | 957 | { |
24f1d3cc | 958 | struct drm_i915_private *dev_priv = ctx->i915; |
9021ad03 | 959 | struct intel_context *ce = &ctx->engine[engine->id]; |
7d774cac TU |
960 | void *vaddr; |
961 | u32 *lrc_reg_state; | |
ca82580c | 962 | int ret; |
dcb4c12a | 963 | |
91c8a326 | 964 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
ca82580c | 965 | |
9021ad03 | 966 | if (ce->pin_count++) |
24f1d3cc CW |
967 | return 0; |
968 | ||
9021ad03 CW |
969 | ret = i915_gem_obj_ggtt_pin(ce->state, GEN8_LR_CONTEXT_ALIGN, |
970 | PIN_OFFSET_BIAS | GUC_WOPCM_TOP); | |
e84fe803 | 971 | if (ret) |
24f1d3cc | 972 | goto err; |
7ba717cf | 973 | |
9021ad03 | 974 | vaddr = i915_gem_object_pin_map(ce->state); |
7d774cac TU |
975 | if (IS_ERR(vaddr)) { |
976 | ret = PTR_ERR(vaddr); | |
82352e90 TU |
977 | goto unpin_ctx_obj; |
978 | } | |
979 | ||
7d774cac TU |
980 | lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; |
981 | ||
9021ad03 | 982 | ret = intel_pin_and_map_ringbuffer_obj(dev_priv, ce->ringbuf); |
e84fe803 | 983 | if (ret) |
7d774cac | 984 | goto unpin_map; |
d1675198 | 985 | |
24f1d3cc | 986 | i915_gem_context_reference(ctx); |
9021ad03 | 987 | ce->lrc_vma = i915_gem_obj_to_ggtt(ce->state); |
0bc40be8 | 988 | intel_lr_context_descriptor_update(ctx, engine); |
9021ad03 CW |
989 | |
990 | lrc_reg_state[CTX_RING_BUFFER_START+1] = ce->ringbuf->vma->node.start; | |
991 | ce->lrc_reg_state = lrc_reg_state; | |
992 | ce->state->dirty = true; | |
e93c28f3 | 993 | |
e84fe803 NH |
994 | /* Invalidate GuC TLB. */ |
995 | if (i915.enable_guc_submission) | |
996 | I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); | |
dcb4c12a | 997 | |
24f1d3cc | 998 | return 0; |
7ba717cf | 999 | |
7d774cac | 1000 | unpin_map: |
9021ad03 | 1001 | i915_gem_object_unpin_map(ce->state); |
7ba717cf | 1002 | unpin_ctx_obj: |
9021ad03 | 1003 | i915_gem_object_ggtt_unpin(ce->state); |
24f1d3cc | 1004 | err: |
9021ad03 | 1005 | ce->pin_count = 0; |
e84fe803 NH |
1006 | return ret; |
1007 | } | |
1008 | ||
e2efd130 | 1009 | void intel_lr_context_unpin(struct i915_gem_context *ctx, |
24f1d3cc | 1010 | struct intel_engine_cs *engine) |
e84fe803 | 1011 | { |
9021ad03 | 1012 | struct intel_context *ce = &ctx->engine[engine->id]; |
e84fe803 | 1013 | |
91c8a326 | 1014 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
9021ad03 | 1015 | GEM_BUG_ON(ce->pin_count == 0); |
321fe304 | 1016 | |
9021ad03 | 1017 | if (--ce->pin_count) |
24f1d3cc | 1018 | return; |
e84fe803 | 1019 | |
9021ad03 | 1020 | intel_unpin_ringbuffer_obj(ce->ringbuf); |
dcb4c12a | 1021 | |
9021ad03 CW |
1022 | i915_gem_object_unpin_map(ce->state); |
1023 | i915_gem_object_ggtt_unpin(ce->state); | |
af3302b9 | 1024 | |
9021ad03 CW |
1025 | ce->lrc_vma = NULL; |
1026 | ce->lrc_desc = 0; | |
1027 | ce->lrc_reg_state = NULL; | |
321fe304 | 1028 | |
24f1d3cc | 1029 | i915_gem_context_unreference(ctx); |
dcb4c12a OM |
1030 | } |
1031 | ||
e2be4faf | 1032 | static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req) |
771b9a53 MT |
1033 | { |
1034 | int ret, i; | |
4a570db5 | 1035 | struct intel_engine_cs *engine = req->engine; |
e2be4faf | 1036 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
c033666a | 1037 | struct i915_workarounds *w = &req->i915->workarounds; |
771b9a53 | 1038 | |
cd7feaaa | 1039 | if (w->count == 0) |
771b9a53 MT |
1040 | return 0; |
1041 | ||
e2f80391 | 1042 | engine->gpu_caches_dirty = true; |
4866d729 | 1043 | ret = logical_ring_flush_all_caches(req); |
771b9a53 MT |
1044 | if (ret) |
1045 | return ret; | |
1046 | ||
987046ad | 1047 | ret = intel_ring_begin(req, w->count * 2 + 2); |
771b9a53 MT |
1048 | if (ret) |
1049 | return ret; | |
1050 | ||
1051 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count)); | |
1052 | for (i = 0; i < w->count; i++) { | |
f92a9162 | 1053 | intel_logical_ring_emit_reg(ringbuf, w->reg[i].addr); |
771b9a53 MT |
1054 | intel_logical_ring_emit(ringbuf, w->reg[i].value); |
1055 | } | |
1056 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1057 | ||
1058 | intel_logical_ring_advance(ringbuf); | |
1059 | ||
e2f80391 | 1060 | engine->gpu_caches_dirty = true; |
4866d729 | 1061 | ret = logical_ring_flush_all_caches(req); |
771b9a53 MT |
1062 | if (ret) |
1063 | return ret; | |
1064 | ||
1065 | return 0; | |
1066 | } | |
1067 | ||
83b8a982 | 1068 | #define wa_ctx_emit(batch, index, cmd) \ |
17ee950d | 1069 | do { \ |
83b8a982 AS |
1070 | int __index = (index)++; \ |
1071 | if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \ | |
17ee950d AS |
1072 | return -ENOSPC; \ |
1073 | } \ | |
83b8a982 | 1074 | batch[__index] = (cmd); \ |
17ee950d AS |
1075 | } while (0) |
1076 | ||
8f40db77 | 1077 | #define wa_ctx_emit_reg(batch, index, reg) \ |
f0f59a00 | 1078 | wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg)) |
9e000847 AS |
1079 | |
1080 | /* | |
1081 | * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after | |
1082 | * PIPE_CONTROL instruction. This is required for the flush to happen correctly | |
1083 | * but there is a slight complication as this is applied in WA batch where the | |
1084 | * values are only initialized once so we cannot take register value at the | |
1085 | * beginning and reuse it further; hence we save its value to memory, upload a | |
1086 | * constant value with bit21 set and then we restore it back with the saved value. | |
1087 | * To simplify the WA, a constant value is formed by using the default value | |
1088 | * of this register. This shouldn't be a problem because we are only modifying | |
1089 | * it for a short period and this batch in non-premptible. We can ofcourse | |
1090 | * use additional instructions that read the actual value of the register | |
1091 | * at that time and set our bit of interest but it makes the WA complicated. | |
1092 | * | |
1093 | * This WA is also required for Gen9 so extracting as a function avoids | |
1094 | * code duplication. | |
1095 | */ | |
0bc40be8 | 1096 | static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, |
9e000847 AS |
1097 | uint32_t *const batch, |
1098 | uint32_t index) | |
1099 | { | |
5e580523 | 1100 | struct drm_i915_private *dev_priv = engine->i915; |
9e000847 AS |
1101 | uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES); |
1102 | ||
a4106a78 | 1103 | /* |
fe905819 | 1104 | * WaDisableLSQCROPERFforOCL:skl,kbl |
a4106a78 AS |
1105 | * This WA is implemented in skl_init_clock_gating() but since |
1106 | * this batch updates GEN8_L3SQCREG4 with default value we need to | |
1107 | * set this bit here to retain the WA during flush. | |
1108 | */ | |
738fa1b3 MK |
1109 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0) || |
1110 | IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0)) | |
a4106a78 AS |
1111 | l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS; |
1112 | ||
f1afe24f | 1113 | wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 | |
83b8a982 | 1114 | MI_SRM_LRM_GLOBAL_GTT)); |
8f40db77 | 1115 | wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); |
0bc40be8 | 1116 | wa_ctx_emit(batch, index, engine->scratch.gtt_offset + 256); |
83b8a982 AS |
1117 | wa_ctx_emit(batch, index, 0); |
1118 | ||
1119 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); | |
8f40db77 | 1120 | wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); |
83b8a982 AS |
1121 | wa_ctx_emit(batch, index, l3sqc4_flush); |
1122 | ||
1123 | wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); | |
1124 | wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL | | |
1125 | PIPE_CONTROL_DC_FLUSH_ENABLE)); | |
1126 | wa_ctx_emit(batch, index, 0); | |
1127 | wa_ctx_emit(batch, index, 0); | |
1128 | wa_ctx_emit(batch, index, 0); | |
1129 | wa_ctx_emit(batch, index, 0); | |
1130 | ||
f1afe24f | 1131 | wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 | |
83b8a982 | 1132 | MI_SRM_LRM_GLOBAL_GTT)); |
8f40db77 | 1133 | wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); |
0bc40be8 | 1134 | wa_ctx_emit(batch, index, engine->scratch.gtt_offset + 256); |
83b8a982 | 1135 | wa_ctx_emit(batch, index, 0); |
9e000847 AS |
1136 | |
1137 | return index; | |
1138 | } | |
1139 | ||
17ee950d AS |
1140 | static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx, |
1141 | uint32_t offset, | |
1142 | uint32_t start_alignment) | |
1143 | { | |
1144 | return wa_ctx->offset = ALIGN(offset, start_alignment); | |
1145 | } | |
1146 | ||
1147 | static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx, | |
1148 | uint32_t offset, | |
1149 | uint32_t size_alignment) | |
1150 | { | |
1151 | wa_ctx->size = offset - wa_ctx->offset; | |
1152 | ||
1153 | WARN(wa_ctx->size % size_alignment, | |
1154 | "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n", | |
1155 | wa_ctx->size, size_alignment); | |
1156 | return 0; | |
1157 | } | |
1158 | ||
1159 | /** | |
1160 | * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA | |
1161 | * | |
14bb2c11 | 1162 | * @engine: only applicable for RCS |
17ee950d AS |
1163 | * @wa_ctx: structure representing wa_ctx |
1164 | * offset: specifies start of the batch, should be cache-aligned. This is updated | |
1165 | * with the offset value received as input. | |
1166 | * size: size of the batch in DWORDS but HW expects in terms of cachelines | |
1167 | * @batch: page in which WA are loaded | |
1168 | * @offset: This field specifies the start of the batch, it should be | |
1169 | * cache-aligned otherwise it is adjusted accordingly. | |
1170 | * Typically we only have one indirect_ctx and per_ctx batch buffer which are | |
1171 | * initialized at the beginning and shared across all contexts but this field | |
1172 | * helps us to have multiple batches at different offsets and select them based | |
1173 | * on a criteria. At the moment this batch always start at the beginning of the page | |
1174 | * and at this point we don't have multiple wa_ctx batch buffers. | |
1175 | * | |
1176 | * The number of WA applied are not known at the beginning; we use this field | |
1177 | * to return the no of DWORDS written. | |
4d78c8dc | 1178 | * |
17ee950d AS |
1179 | * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END |
1180 | * so it adds NOOPs as padding to make it cacheline aligned. | |
1181 | * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together | |
1182 | * makes a complete batch buffer. | |
1183 | * | |
1184 | * Return: non-zero if we exceed the PAGE_SIZE limit. | |
1185 | */ | |
1186 | ||
0bc40be8 | 1187 | static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine, |
17ee950d AS |
1188 | struct i915_wa_ctx_bb *wa_ctx, |
1189 | uint32_t *const batch, | |
1190 | uint32_t *offset) | |
1191 | { | |
0160f055 | 1192 | uint32_t scratch_addr; |
17ee950d AS |
1193 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
1194 | ||
7ad00d1a | 1195 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
83b8a982 | 1196 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
17ee950d | 1197 | |
c82435bb | 1198 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */ |
c033666a | 1199 | if (IS_BROADWELL(engine->i915)) { |
0bc40be8 | 1200 | int rc = gen8_emit_flush_coherentl3_wa(engine, batch, index); |
604ef734 AH |
1201 | if (rc < 0) |
1202 | return rc; | |
1203 | index = rc; | |
c82435bb AS |
1204 | } |
1205 | ||
0160f055 AS |
1206 | /* WaClearSlmSpaceAtContextSwitch:bdw,chv */ |
1207 | /* Actual scratch location is at 128 bytes offset */ | |
0bc40be8 | 1208 | scratch_addr = engine->scratch.gtt_offset + 2*CACHELINE_BYTES; |
0160f055 | 1209 | |
83b8a982 AS |
1210 | wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); |
1211 | wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 | | |
1212 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1213 | PIPE_CONTROL_CS_STALL | | |
1214 | PIPE_CONTROL_QW_WRITE)); | |
1215 | wa_ctx_emit(batch, index, scratch_addr); | |
1216 | wa_ctx_emit(batch, index, 0); | |
1217 | wa_ctx_emit(batch, index, 0); | |
1218 | wa_ctx_emit(batch, index, 0); | |
0160f055 | 1219 | |
17ee950d AS |
1220 | /* Pad to end of cacheline */ |
1221 | while (index % CACHELINE_DWORDS) | |
83b8a982 | 1222 | wa_ctx_emit(batch, index, MI_NOOP); |
17ee950d AS |
1223 | |
1224 | /* | |
1225 | * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because | |
1226 | * execution depends on the length specified in terms of cache lines | |
1227 | * in the register CTX_RCS_INDIRECT_CTX | |
1228 | */ | |
1229 | ||
1230 | return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); | |
1231 | } | |
1232 | ||
1233 | /** | |
1234 | * gen8_init_perctx_bb() - initialize per ctx batch with WA | |
1235 | * | |
14bb2c11 | 1236 | * @engine: only applicable for RCS |
17ee950d AS |
1237 | * @wa_ctx: structure representing wa_ctx |
1238 | * offset: specifies start of the batch, should be cache-aligned. | |
1239 | * size: size of the batch in DWORDS but HW expects in terms of cachelines | |
4d78c8dc | 1240 | * @batch: page in which WA are loaded |
17ee950d AS |
1241 | * @offset: This field specifies the start of this batch. |
1242 | * This batch is started immediately after indirect_ctx batch. Since we ensure | |
1243 | * that indirect_ctx ends on a cacheline this batch is aligned automatically. | |
1244 | * | |
1245 | * The number of DWORDS written are returned using this field. | |
1246 | * | |
1247 | * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding | |
1248 | * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant. | |
1249 | */ | |
0bc40be8 | 1250 | static int gen8_init_perctx_bb(struct intel_engine_cs *engine, |
17ee950d AS |
1251 | struct i915_wa_ctx_bb *wa_ctx, |
1252 | uint32_t *const batch, | |
1253 | uint32_t *offset) | |
1254 | { | |
1255 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); | |
1256 | ||
7ad00d1a | 1257 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
83b8a982 | 1258 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
7ad00d1a | 1259 | |
83b8a982 | 1260 | wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); |
17ee950d AS |
1261 | |
1262 | return wa_ctx_end(wa_ctx, *offset = index, 1); | |
1263 | } | |
1264 | ||
0bc40be8 | 1265 | static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine, |
0504cffc AS |
1266 | struct i915_wa_ctx_bb *wa_ctx, |
1267 | uint32_t *const batch, | |
1268 | uint32_t *offset) | |
1269 | { | |
a4106a78 | 1270 | int ret; |
5e580523 | 1271 | struct drm_i915_private *dev_priv = engine->i915; |
0504cffc AS |
1272 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
1273 | ||
0907c8f7 | 1274 | /* WaDisableCtxRestoreArbitration:skl,bxt */ |
5e580523 DA |
1275 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0) || |
1276 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) | |
0907c8f7 | 1277 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
0504cffc | 1278 | |
a4106a78 | 1279 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */ |
0bc40be8 | 1280 | ret = gen8_emit_flush_coherentl3_wa(engine, batch, index); |
a4106a78 AS |
1281 | if (ret < 0) |
1282 | return ret; | |
1283 | index = ret; | |
1284 | ||
066d4628 MK |
1285 | /* WaClearSlmSpaceAtContextSwitch:kbl */ |
1286 | /* Actual scratch location is at 128 bytes offset */ | |
703d1282 | 1287 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0)) { |
066d4628 MK |
1288 | uint32_t scratch_addr |
1289 | = engine->scratch.gtt_offset + 2*CACHELINE_BYTES; | |
1290 | ||
1291 | wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); | |
1292 | wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 | | |
1293 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1294 | PIPE_CONTROL_CS_STALL | | |
1295 | PIPE_CONTROL_QW_WRITE)); | |
1296 | wa_ctx_emit(batch, index, scratch_addr); | |
1297 | wa_ctx_emit(batch, index, 0); | |
1298 | wa_ctx_emit(batch, index, 0); | |
1299 | wa_ctx_emit(batch, index, 0); | |
1300 | } | |
3485d99e TG |
1301 | |
1302 | /* WaMediaPoolStateCmdInWABB:bxt */ | |
1303 | if (HAS_POOLED_EU(engine->i915)) { | |
1304 | /* | |
1305 | * EU pool configuration is setup along with golden context | |
1306 | * during context initialization. This value depends on | |
1307 | * device type (2x6 or 3x6) and needs to be updated based | |
1308 | * on which subslice is disabled especially for 2x6 | |
1309 | * devices, however it is safe to load default | |
1310 | * configuration of 3x6 device instead of masking off | |
1311 | * corresponding bits because HW ignores bits of a disabled | |
1312 | * subslice and drops down to appropriate config. Please | |
1313 | * see render_state_setup() in i915_gem_render_state.c for | |
1314 | * possible configurations, to avoid duplication they are | |
1315 | * not shown here again. | |
1316 | */ | |
1317 | u32 eu_pool_config = 0x00777000; | |
1318 | wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_STATE); | |
1319 | wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_ENABLE); | |
1320 | wa_ctx_emit(batch, index, eu_pool_config); | |
1321 | wa_ctx_emit(batch, index, 0); | |
1322 | wa_ctx_emit(batch, index, 0); | |
1323 | wa_ctx_emit(batch, index, 0); | |
1324 | } | |
1325 | ||
0504cffc AS |
1326 | /* Pad to end of cacheline */ |
1327 | while (index % CACHELINE_DWORDS) | |
1328 | wa_ctx_emit(batch, index, MI_NOOP); | |
1329 | ||
1330 | return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); | |
1331 | } | |
1332 | ||
0bc40be8 | 1333 | static int gen9_init_perctx_bb(struct intel_engine_cs *engine, |
0504cffc AS |
1334 | struct i915_wa_ctx_bb *wa_ctx, |
1335 | uint32_t *const batch, | |
1336 | uint32_t *offset) | |
1337 | { | |
1338 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); | |
1339 | ||
9b01435d | 1340 | /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ |
c033666a CW |
1341 | if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_B0) || |
1342 | IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) { | |
9b01435d | 1343 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); |
8f40db77 | 1344 | wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0); |
9b01435d AS |
1345 | wa_ctx_emit(batch, index, |
1346 | _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING)); | |
1347 | wa_ctx_emit(batch, index, MI_NOOP); | |
1348 | } | |
1349 | ||
b1e429fe | 1350 | /* WaClearTdlStateAckDirtyBits:bxt */ |
c033666a | 1351 | if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_B0)) { |
b1e429fe TG |
1352 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(4)); |
1353 | ||
1354 | wa_ctx_emit_reg(batch, index, GEN8_STATE_ACK); | |
1355 | wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS)); | |
1356 | ||
1357 | wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE1); | |
1358 | wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS)); | |
1359 | ||
1360 | wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE2); | |
1361 | wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS)); | |
1362 | ||
1363 | wa_ctx_emit_reg(batch, index, GEN7_ROW_CHICKEN2); | |
1364 | /* dummy write to CS, mask bits are 0 to ensure the register is not modified */ | |
1365 | wa_ctx_emit(batch, index, 0x0); | |
1366 | wa_ctx_emit(batch, index, MI_NOOP); | |
1367 | } | |
1368 | ||
0907c8f7 | 1369 | /* WaDisableCtxRestoreArbitration:skl,bxt */ |
c033666a CW |
1370 | if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_D0) || |
1371 | IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) | |
0907c8f7 AS |
1372 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
1373 | ||
0504cffc AS |
1374 | wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); |
1375 | ||
1376 | return wa_ctx_end(wa_ctx, *offset = index, 1); | |
1377 | } | |
1378 | ||
0bc40be8 | 1379 | static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *engine, u32 size) |
17ee950d AS |
1380 | { |
1381 | int ret; | |
1382 | ||
91c8a326 CW |
1383 | engine->wa_ctx.obj = i915_gem_object_create(&engine->i915->drm, |
1384 | PAGE_ALIGN(size)); | |
fe3db79b | 1385 | if (IS_ERR(engine->wa_ctx.obj)) { |
17ee950d | 1386 | DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n"); |
fe3db79b CW |
1387 | ret = PTR_ERR(engine->wa_ctx.obj); |
1388 | engine->wa_ctx.obj = NULL; | |
1389 | return ret; | |
17ee950d AS |
1390 | } |
1391 | ||
0bc40be8 | 1392 | ret = i915_gem_obj_ggtt_pin(engine->wa_ctx.obj, PAGE_SIZE, 0); |
17ee950d AS |
1393 | if (ret) { |
1394 | DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n", | |
1395 | ret); | |
0bc40be8 | 1396 | drm_gem_object_unreference(&engine->wa_ctx.obj->base); |
17ee950d AS |
1397 | return ret; |
1398 | } | |
1399 | ||
1400 | return 0; | |
1401 | } | |
1402 | ||
0bc40be8 | 1403 | static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *engine) |
17ee950d | 1404 | { |
0bc40be8 TU |
1405 | if (engine->wa_ctx.obj) { |
1406 | i915_gem_object_ggtt_unpin(engine->wa_ctx.obj); | |
1407 | drm_gem_object_unreference(&engine->wa_ctx.obj->base); | |
1408 | engine->wa_ctx.obj = NULL; | |
17ee950d AS |
1409 | } |
1410 | } | |
1411 | ||
0bc40be8 | 1412 | static int intel_init_workaround_bb(struct intel_engine_cs *engine) |
17ee950d AS |
1413 | { |
1414 | int ret; | |
1415 | uint32_t *batch; | |
1416 | uint32_t offset; | |
1417 | struct page *page; | |
0bc40be8 | 1418 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; |
17ee950d | 1419 | |
0bc40be8 | 1420 | WARN_ON(engine->id != RCS); |
17ee950d | 1421 | |
5e60d790 | 1422 | /* update this when WA for higher Gen are added */ |
c033666a | 1423 | if (INTEL_GEN(engine->i915) > 9) { |
0504cffc | 1424 | DRM_ERROR("WA batch buffer is not initialized for Gen%d\n", |
c033666a | 1425 | INTEL_GEN(engine->i915)); |
5e60d790 | 1426 | return 0; |
0504cffc | 1427 | } |
5e60d790 | 1428 | |
c4db7599 | 1429 | /* some WA perform writes to scratch page, ensure it is valid */ |
0bc40be8 TU |
1430 | if (engine->scratch.obj == NULL) { |
1431 | DRM_ERROR("scratch page not allocated for %s\n", engine->name); | |
c4db7599 AS |
1432 | return -EINVAL; |
1433 | } | |
1434 | ||
0bc40be8 | 1435 | ret = lrc_setup_wa_ctx_obj(engine, PAGE_SIZE); |
17ee950d AS |
1436 | if (ret) { |
1437 | DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret); | |
1438 | return ret; | |
1439 | } | |
1440 | ||
033908ae | 1441 | page = i915_gem_object_get_dirty_page(wa_ctx->obj, 0); |
17ee950d AS |
1442 | batch = kmap_atomic(page); |
1443 | offset = 0; | |
1444 | ||
c033666a | 1445 | if (IS_GEN8(engine->i915)) { |
0bc40be8 | 1446 | ret = gen8_init_indirectctx_bb(engine, |
17ee950d AS |
1447 | &wa_ctx->indirect_ctx, |
1448 | batch, | |
1449 | &offset); | |
1450 | if (ret) | |
1451 | goto out; | |
1452 | ||
0bc40be8 | 1453 | ret = gen8_init_perctx_bb(engine, |
17ee950d AS |
1454 | &wa_ctx->per_ctx, |
1455 | batch, | |
1456 | &offset); | |
1457 | if (ret) | |
1458 | goto out; | |
c033666a | 1459 | } else if (IS_GEN9(engine->i915)) { |
0bc40be8 | 1460 | ret = gen9_init_indirectctx_bb(engine, |
0504cffc AS |
1461 | &wa_ctx->indirect_ctx, |
1462 | batch, | |
1463 | &offset); | |
1464 | if (ret) | |
1465 | goto out; | |
1466 | ||
0bc40be8 | 1467 | ret = gen9_init_perctx_bb(engine, |
0504cffc AS |
1468 | &wa_ctx->per_ctx, |
1469 | batch, | |
1470 | &offset); | |
1471 | if (ret) | |
1472 | goto out; | |
17ee950d AS |
1473 | } |
1474 | ||
1475 | out: | |
1476 | kunmap_atomic(batch); | |
1477 | if (ret) | |
0bc40be8 | 1478 | lrc_destroy_wa_ctx_obj(engine); |
17ee950d AS |
1479 | |
1480 | return ret; | |
1481 | } | |
1482 | ||
04794adb TU |
1483 | static void lrc_init_hws(struct intel_engine_cs *engine) |
1484 | { | |
c033666a | 1485 | struct drm_i915_private *dev_priv = engine->i915; |
04794adb TU |
1486 | |
1487 | I915_WRITE(RING_HWS_PGA(engine->mmio_base), | |
1488 | (u32)engine->status_page.gfx_addr); | |
1489 | POSTING_READ(RING_HWS_PGA(engine->mmio_base)); | |
1490 | } | |
1491 | ||
0bc40be8 | 1492 | static int gen8_init_common_ring(struct intel_engine_cs *engine) |
9b1136d5 | 1493 | { |
c033666a | 1494 | struct drm_i915_private *dev_priv = engine->i915; |
c6a2ac71 | 1495 | unsigned int next_context_status_buffer_hw; |
9b1136d5 | 1496 | |
04794adb | 1497 | lrc_init_hws(engine); |
e84fe803 | 1498 | |
0bc40be8 TU |
1499 | I915_WRITE_IMR(engine, |
1500 | ~(engine->irq_enable_mask | engine->irq_keep_mask)); | |
1501 | I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff); | |
73d477f6 | 1502 | |
0bc40be8 | 1503 | I915_WRITE(RING_MODE_GEN7(engine), |
9b1136d5 OM |
1504 | _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) | |
1505 | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); | |
0bc40be8 | 1506 | POSTING_READ(RING_MODE_GEN7(engine)); |
dfc53c5e MT |
1507 | |
1508 | /* | |
1509 | * Instead of resetting the Context Status Buffer (CSB) read pointer to | |
1510 | * zero, we need to read the write pointer from hardware and use its | |
1511 | * value because "this register is power context save restored". | |
1512 | * Effectively, these states have been observed: | |
1513 | * | |
1514 | * | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) | | |
1515 | * BDW | CSB regs not reset | CSB regs reset | | |
1516 | * CHT | CSB regs not reset | CSB regs not reset | | |
5590a5f0 BW |
1517 | * SKL | ? | ? | |
1518 | * BXT | ? | ? | | |
dfc53c5e | 1519 | */ |
5590a5f0 | 1520 | next_context_status_buffer_hw = |
0bc40be8 | 1521 | GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine))); |
dfc53c5e MT |
1522 | |
1523 | /* | |
1524 | * When the CSB registers are reset (also after power-up / gpu reset), | |
1525 | * CSB write pointer is set to all 1's, which is not valid, use '5' in | |
1526 | * this special case, so the first element read is CSB[0]. | |
1527 | */ | |
1528 | if (next_context_status_buffer_hw == GEN8_CSB_PTR_MASK) | |
1529 | next_context_status_buffer_hw = (GEN8_CSB_ENTRIES - 1); | |
1530 | ||
0bc40be8 TU |
1531 | engine->next_context_status_buffer = next_context_status_buffer_hw; |
1532 | DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name); | |
9b1136d5 | 1533 | |
fc0768ce | 1534 | intel_engine_init_hangcheck(engine); |
9b1136d5 | 1535 | |
0ccdacf6 | 1536 | return intel_mocs_init_engine(engine); |
9b1136d5 OM |
1537 | } |
1538 | ||
0bc40be8 | 1539 | static int gen8_init_render_ring(struct intel_engine_cs *engine) |
9b1136d5 | 1540 | { |
c033666a | 1541 | struct drm_i915_private *dev_priv = engine->i915; |
9b1136d5 OM |
1542 | int ret; |
1543 | ||
0bc40be8 | 1544 | ret = gen8_init_common_ring(engine); |
9b1136d5 OM |
1545 | if (ret) |
1546 | return ret; | |
1547 | ||
1548 | /* We need to disable the AsyncFlip performance optimisations in order | |
1549 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1550 | * programmed to '1' on all products. | |
1551 | * | |
1552 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv | |
1553 | */ | |
1554 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
1555 | ||
9b1136d5 OM |
1556 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
1557 | ||
0bc40be8 | 1558 | return init_workarounds_ring(engine); |
9b1136d5 OM |
1559 | } |
1560 | ||
0bc40be8 | 1561 | static int gen9_init_render_ring(struct intel_engine_cs *engine) |
82ef822e DL |
1562 | { |
1563 | int ret; | |
1564 | ||
0bc40be8 | 1565 | ret = gen8_init_common_ring(engine); |
82ef822e DL |
1566 | if (ret) |
1567 | return ret; | |
1568 | ||
0bc40be8 | 1569 | return init_workarounds_ring(engine); |
82ef822e DL |
1570 | } |
1571 | ||
7a01a0a2 MT |
1572 | static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req) |
1573 | { | |
1574 | struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt; | |
4a570db5 | 1575 | struct intel_engine_cs *engine = req->engine; |
7a01a0a2 MT |
1576 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
1577 | const int num_lri_cmds = GEN8_LEGACY_PDPES * 2; | |
1578 | int i, ret; | |
1579 | ||
987046ad | 1580 | ret = intel_ring_begin(req, num_lri_cmds * 2 + 2); |
7a01a0a2 MT |
1581 | if (ret) |
1582 | return ret; | |
1583 | ||
1584 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds)); | |
1585 | for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { | |
1586 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); | |
1587 | ||
e2f80391 TU |
1588 | intel_logical_ring_emit_reg(ringbuf, |
1589 | GEN8_RING_PDP_UDW(engine, i)); | |
7a01a0a2 | 1590 | intel_logical_ring_emit(ringbuf, upper_32_bits(pd_daddr)); |
e2f80391 TU |
1591 | intel_logical_ring_emit_reg(ringbuf, |
1592 | GEN8_RING_PDP_LDW(engine, i)); | |
7a01a0a2 MT |
1593 | intel_logical_ring_emit(ringbuf, lower_32_bits(pd_daddr)); |
1594 | } | |
1595 | ||
1596 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1597 | intel_logical_ring_advance(ringbuf); | |
1598 | ||
1599 | return 0; | |
1600 | } | |
1601 | ||
be795fc1 | 1602 | static int gen8_emit_bb_start(struct drm_i915_gem_request *req, |
8e004efc | 1603 | u64 offset, unsigned dispatch_flags) |
15648585 | 1604 | { |
be795fc1 | 1605 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
8e004efc | 1606 | bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE); |
15648585 OM |
1607 | int ret; |
1608 | ||
7a01a0a2 MT |
1609 | /* Don't rely in hw updating PDPs, specially in lite-restore. |
1610 | * Ideally, we should set Force PD Restore in ctx descriptor, | |
1611 | * but we can't. Force Restore would be a second option, but | |
1612 | * it is unsafe in case of lite-restore (because the ctx is | |
2dba3239 MT |
1613 | * not idle). PML4 is allocated during ppgtt init so this is |
1614 | * not needed in 48-bit.*/ | |
7a01a0a2 | 1615 | if (req->ctx->ppgtt && |
666796da | 1616 | (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) { |
331f38e7 | 1617 | if (!USES_FULL_48BIT_PPGTT(req->i915) && |
c033666a | 1618 | !intel_vgpu_active(req->i915)) { |
2dba3239 MT |
1619 | ret = intel_logical_ring_emit_pdps(req); |
1620 | if (ret) | |
1621 | return ret; | |
1622 | } | |
7a01a0a2 | 1623 | |
666796da | 1624 | req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine); |
7a01a0a2 MT |
1625 | } |
1626 | ||
987046ad | 1627 | ret = intel_ring_begin(req, 4); |
15648585 OM |
1628 | if (ret) |
1629 | return ret; | |
1630 | ||
1631 | /* FIXME(BDW): Address space and security selectors. */ | |
6922528a AJ |
1632 | intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | |
1633 | (ppgtt<<8) | | |
1634 | (dispatch_flags & I915_DISPATCH_RS ? | |
1635 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
15648585 OM |
1636 | intel_logical_ring_emit(ringbuf, lower_32_bits(offset)); |
1637 | intel_logical_ring_emit(ringbuf, upper_32_bits(offset)); | |
1638 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1639 | intel_logical_ring_advance(ringbuf); | |
1640 | ||
1641 | return 0; | |
1642 | } | |
1643 | ||
31bb59cc | 1644 | static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine) |
73d477f6 | 1645 | { |
c033666a | 1646 | struct drm_i915_private *dev_priv = engine->i915; |
31bb59cc CW |
1647 | I915_WRITE_IMR(engine, |
1648 | ~(engine->irq_enable_mask | engine->irq_keep_mask)); | |
1649 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
73d477f6 OM |
1650 | } |
1651 | ||
31bb59cc | 1652 | static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine) |
73d477f6 | 1653 | { |
c033666a | 1654 | struct drm_i915_private *dev_priv = engine->i915; |
31bb59cc | 1655 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
73d477f6 OM |
1656 | } |
1657 | ||
7deb4d39 | 1658 | static int gen8_emit_flush(struct drm_i915_gem_request *request, |
4712274c OM |
1659 | u32 invalidate_domains, |
1660 | u32 unused) | |
1661 | { | |
7deb4d39 | 1662 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
4a570db5 | 1663 | struct intel_engine_cs *engine = ringbuf->engine; |
c033666a | 1664 | struct drm_i915_private *dev_priv = request->i915; |
4712274c OM |
1665 | uint32_t cmd; |
1666 | int ret; | |
1667 | ||
987046ad | 1668 | ret = intel_ring_begin(request, 4); |
4712274c OM |
1669 | if (ret) |
1670 | return ret; | |
1671 | ||
1672 | cmd = MI_FLUSH_DW + 1; | |
1673 | ||
f0a1fb10 CW |
1674 | /* We always require a command barrier so that subsequent |
1675 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1676 | * wrt the contents of the write cache being flushed to memory | |
1677 | * (and thus being coherent from the CPU). | |
1678 | */ | |
1679 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1680 | ||
1681 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) { | |
1682 | cmd |= MI_INVALIDATE_TLB; | |
4a570db5 | 1683 | if (engine == &dev_priv->engine[VCS]) |
f0a1fb10 | 1684 | cmd |= MI_INVALIDATE_BSD; |
4712274c OM |
1685 | } |
1686 | ||
1687 | intel_logical_ring_emit(ringbuf, cmd); | |
1688 | intel_logical_ring_emit(ringbuf, | |
1689 | I915_GEM_HWS_SCRATCH_ADDR | | |
1690 | MI_FLUSH_DW_USE_GTT); | |
1691 | intel_logical_ring_emit(ringbuf, 0); /* upper addr */ | |
1692 | intel_logical_ring_emit(ringbuf, 0); /* value */ | |
1693 | intel_logical_ring_advance(ringbuf); | |
1694 | ||
1695 | return 0; | |
1696 | } | |
1697 | ||
7deb4d39 | 1698 | static int gen8_emit_flush_render(struct drm_i915_gem_request *request, |
4712274c OM |
1699 | u32 invalidate_domains, |
1700 | u32 flush_domains) | |
1701 | { | |
7deb4d39 | 1702 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
4a570db5 | 1703 | struct intel_engine_cs *engine = ringbuf->engine; |
e2f80391 | 1704 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
0b2d0934 | 1705 | bool vf_flush_wa = false, dc_flush_wa = false; |
4712274c OM |
1706 | u32 flags = 0; |
1707 | int ret; | |
0b2d0934 | 1708 | int len; |
4712274c OM |
1709 | |
1710 | flags |= PIPE_CONTROL_CS_STALL; | |
1711 | ||
1712 | if (flush_domains) { | |
1713 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
1714 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 1715 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 1716 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4712274c OM |
1717 | } |
1718 | ||
1719 | if (invalidate_domains) { | |
1720 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
1721 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
1722 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
1723 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
1724 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
1725 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
1726 | flags |= PIPE_CONTROL_QW_WRITE; | |
1727 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
4712274c | 1728 | |
1a5a9ce7 BW |
1729 | /* |
1730 | * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL | |
1731 | * pipe control. | |
1732 | */ | |
c033666a | 1733 | if (IS_GEN9(request->i915)) |
1a5a9ce7 | 1734 | vf_flush_wa = true; |
0b2d0934 MK |
1735 | |
1736 | /* WaForGAMHang:kbl */ | |
1737 | if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0)) | |
1738 | dc_flush_wa = true; | |
1a5a9ce7 | 1739 | } |
9647ff36 | 1740 | |
0b2d0934 MK |
1741 | len = 6; |
1742 | ||
1743 | if (vf_flush_wa) | |
1744 | len += 6; | |
1745 | ||
1746 | if (dc_flush_wa) | |
1747 | len += 12; | |
1748 | ||
1749 | ret = intel_ring_begin(request, len); | |
4712274c OM |
1750 | if (ret) |
1751 | return ret; | |
1752 | ||
9647ff36 ID |
1753 | if (vf_flush_wa) { |
1754 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); | |
1755 | intel_logical_ring_emit(ringbuf, 0); | |
1756 | intel_logical_ring_emit(ringbuf, 0); | |
1757 | intel_logical_ring_emit(ringbuf, 0); | |
1758 | intel_logical_ring_emit(ringbuf, 0); | |
1759 | intel_logical_ring_emit(ringbuf, 0); | |
1760 | } | |
1761 | ||
0b2d0934 MK |
1762 | if (dc_flush_wa) { |
1763 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); | |
1764 | intel_logical_ring_emit(ringbuf, PIPE_CONTROL_DC_FLUSH_ENABLE); | |
1765 | intel_logical_ring_emit(ringbuf, 0); | |
1766 | intel_logical_ring_emit(ringbuf, 0); | |
1767 | intel_logical_ring_emit(ringbuf, 0); | |
1768 | intel_logical_ring_emit(ringbuf, 0); | |
1769 | } | |
1770 | ||
4712274c OM |
1771 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); |
1772 | intel_logical_ring_emit(ringbuf, flags); | |
1773 | intel_logical_ring_emit(ringbuf, scratch_addr); | |
1774 | intel_logical_ring_emit(ringbuf, 0); | |
1775 | intel_logical_ring_emit(ringbuf, 0); | |
1776 | intel_logical_ring_emit(ringbuf, 0); | |
0b2d0934 MK |
1777 | |
1778 | if (dc_flush_wa) { | |
1779 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); | |
1780 | intel_logical_ring_emit(ringbuf, PIPE_CONTROL_CS_STALL); | |
1781 | intel_logical_ring_emit(ringbuf, 0); | |
1782 | intel_logical_ring_emit(ringbuf, 0); | |
1783 | intel_logical_ring_emit(ringbuf, 0); | |
1784 | intel_logical_ring_emit(ringbuf, 0); | |
1785 | } | |
1786 | ||
4712274c OM |
1787 | intel_logical_ring_advance(ringbuf); |
1788 | ||
1789 | return 0; | |
1790 | } | |
1791 | ||
c04e0f3b | 1792 | static void bxt_a_seqno_barrier(struct intel_engine_cs *engine) |
319404df | 1793 | { |
319404df ID |
1794 | /* |
1795 | * On BXT A steppings there is a HW coherency issue whereby the | |
1796 | * MI_STORE_DATA_IMM storing the completed request's seqno | |
1797 | * occasionally doesn't invalidate the CPU cache. Work around this by | |
1798 | * clflushing the corresponding cacheline whenever the caller wants | |
1799 | * the coherency to be guaranteed. Note that this cacheline is known | |
1800 | * to be clean at this point, since we only write it in | |
1801 | * bxt_a_set_seqno(), where we also do a clflush after the write. So | |
1802 | * this clflush in practice becomes an invalidate operation. | |
1803 | */ | |
c04e0f3b | 1804 | intel_flush_status_page(engine, I915_GEM_HWS_INDEX); |
319404df ID |
1805 | } |
1806 | ||
7c17d377 CW |
1807 | /* |
1808 | * Reserve space for 2 NOOPs at the end of each request to be | |
1809 | * used as a workaround for not being allowed to do lite | |
1810 | * restore with HEAD==TAIL (WaIdleLiteRestore). | |
1811 | */ | |
1812 | #define WA_TAIL_DWORDS 2 | |
1813 | ||
c4e76638 | 1814 | static int gen8_emit_request(struct drm_i915_gem_request *request) |
4da46e1e | 1815 | { |
c4e76638 | 1816 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
4da46e1e OM |
1817 | int ret; |
1818 | ||
987046ad | 1819 | ret = intel_ring_begin(request, 6 + WA_TAIL_DWORDS); |
4da46e1e OM |
1820 | if (ret) |
1821 | return ret; | |
1822 | ||
7c17d377 CW |
1823 | /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */ |
1824 | BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5)); | |
4da46e1e | 1825 | |
4da46e1e | 1826 | intel_logical_ring_emit(ringbuf, |
7c17d377 CW |
1827 | (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW); |
1828 | intel_logical_ring_emit(ringbuf, | |
a58c01aa | 1829 | intel_hws_seqno_address(request->engine) | |
7c17d377 | 1830 | MI_FLUSH_DW_USE_GTT); |
4da46e1e | 1831 | intel_logical_ring_emit(ringbuf, 0); |
1b7744e7 | 1832 | intel_logical_ring_emit(ringbuf, request->seqno); |
4da46e1e OM |
1833 | intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT); |
1834 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
7c17d377 CW |
1835 | return intel_logical_ring_advance_and_submit(request); |
1836 | } | |
4da46e1e | 1837 | |
7c17d377 CW |
1838 | static int gen8_emit_request_render(struct drm_i915_gem_request *request) |
1839 | { | |
1840 | struct intel_ringbuffer *ringbuf = request->ringbuf; | |
1841 | int ret; | |
53292cdb | 1842 | |
987046ad | 1843 | ret = intel_ring_begin(request, 8 + WA_TAIL_DWORDS); |
7c17d377 CW |
1844 | if (ret) |
1845 | return ret; | |
1846 | ||
ce81a65c MW |
1847 | /* We're using qword write, seqno should be aligned to 8 bytes. */ |
1848 | BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1); | |
1849 | ||
7c17d377 CW |
1850 | /* w/a for post sync ops following a GPGPU operation we |
1851 | * need a prior CS_STALL, which is emitted by the flush | |
1852 | * following the batch. | |
1853 | */ | |
ce81a65c | 1854 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); |
7c17d377 CW |
1855 | intel_logical_ring_emit(ringbuf, |
1856 | (PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1857 | PIPE_CONTROL_CS_STALL | | |
1858 | PIPE_CONTROL_QW_WRITE)); | |
a58c01aa CW |
1859 | intel_logical_ring_emit(ringbuf, |
1860 | intel_hws_seqno_address(request->engine)); | |
7c17d377 CW |
1861 | intel_logical_ring_emit(ringbuf, 0); |
1862 | intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request)); | |
ce81a65c MW |
1863 | /* We're thrashing one dword of HWS. */ |
1864 | intel_logical_ring_emit(ringbuf, 0); | |
7c17d377 | 1865 | intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT); |
ce81a65c | 1866 | intel_logical_ring_emit(ringbuf, MI_NOOP); |
7c17d377 | 1867 | return intel_logical_ring_advance_and_submit(request); |
4da46e1e OM |
1868 | } |
1869 | ||
be01363f | 1870 | static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req) |
cef437ad | 1871 | { |
cef437ad | 1872 | struct render_state so; |
cef437ad DL |
1873 | int ret; |
1874 | ||
4a570db5 | 1875 | ret = i915_gem_render_state_prepare(req->engine, &so); |
cef437ad DL |
1876 | if (ret) |
1877 | return ret; | |
1878 | ||
1879 | if (so.rodata == NULL) | |
1880 | return 0; | |
1881 | ||
4a570db5 | 1882 | ret = req->engine->emit_bb_start(req, so.ggtt_offset, |
be01363f | 1883 | I915_DISPATCH_SECURE); |
cef437ad DL |
1884 | if (ret) |
1885 | goto out; | |
1886 | ||
4a570db5 | 1887 | ret = req->engine->emit_bb_start(req, |
84e81020 AS |
1888 | (so.ggtt_offset + so.aux_batch_offset), |
1889 | I915_DISPATCH_SECURE); | |
1890 | if (ret) | |
1891 | goto out; | |
1892 | ||
b2af0376 | 1893 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req); |
cef437ad | 1894 | |
cef437ad DL |
1895 | out: |
1896 | i915_gem_render_state_fini(&so); | |
1897 | return ret; | |
1898 | } | |
1899 | ||
8753181e | 1900 | static int gen8_init_rcs_context(struct drm_i915_gem_request *req) |
e7778be1 TD |
1901 | { |
1902 | int ret; | |
1903 | ||
e2be4faf | 1904 | ret = intel_logical_ring_workarounds_emit(req); |
e7778be1 TD |
1905 | if (ret) |
1906 | return ret; | |
1907 | ||
3bbaba0c PA |
1908 | ret = intel_rcs_context_init_mocs(req); |
1909 | /* | |
1910 | * Failing to program the MOCS is non-fatal.The system will not | |
1911 | * run at peak performance. So generate an error and carry on. | |
1912 | */ | |
1913 | if (ret) | |
1914 | DRM_ERROR("MOCS failed to program: expect performance issues.\n"); | |
1915 | ||
be01363f | 1916 | return intel_lr_context_render_state_init(req); |
e7778be1 TD |
1917 | } |
1918 | ||
73e4d07f OM |
1919 | /** |
1920 | * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer | |
1921 | * | |
14bb2c11 | 1922 | * @engine: Engine Command Streamer. |
73e4d07f OM |
1923 | * |
1924 | */ | |
0bc40be8 | 1925 | void intel_logical_ring_cleanup(struct intel_engine_cs *engine) |
454afebd | 1926 | { |
6402c330 | 1927 | struct drm_i915_private *dev_priv; |
9832b9da | 1928 | |
117897f4 | 1929 | if (!intel_engine_initialized(engine)) |
48d82387 OM |
1930 | return; |
1931 | ||
27af5eea TU |
1932 | /* |
1933 | * Tasklet cannot be active at this point due intel_mark_active/idle | |
1934 | * so this is just for documentation. | |
1935 | */ | |
1936 | if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state))) | |
1937 | tasklet_kill(&engine->irq_tasklet); | |
1938 | ||
c033666a | 1939 | dev_priv = engine->i915; |
6402c330 | 1940 | |
0bc40be8 TU |
1941 | if (engine->buffer) { |
1942 | intel_logical_ring_stop(engine); | |
1943 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); | |
b0366a54 | 1944 | } |
48d82387 | 1945 | |
0bc40be8 TU |
1946 | if (engine->cleanup) |
1947 | engine->cleanup(engine); | |
48d82387 | 1948 | |
0bc40be8 TU |
1949 | i915_cmd_parser_fini_ring(engine); |
1950 | i915_gem_batch_pool_fini(&engine->batch_pool); | |
48d82387 | 1951 | |
688e6c72 CW |
1952 | intel_engine_fini_breadcrumbs(engine); |
1953 | ||
0bc40be8 | 1954 | if (engine->status_page.obj) { |
7d774cac | 1955 | i915_gem_object_unpin_map(engine->status_page.obj); |
0bc40be8 | 1956 | engine->status_page.obj = NULL; |
48d82387 | 1957 | } |
24f1d3cc | 1958 | intel_lr_context_unpin(dev_priv->kernel_context, engine); |
17ee950d | 1959 | |
0bc40be8 TU |
1960 | engine->idle_lite_restore_wa = 0; |
1961 | engine->disable_lite_restore_wa = false; | |
1962 | engine->ctx_desc_template = 0; | |
ca82580c | 1963 | |
0bc40be8 | 1964 | lrc_destroy_wa_ctx_obj(engine); |
c033666a | 1965 | engine->i915 = NULL; |
454afebd OM |
1966 | } |
1967 | ||
c9cacf93 | 1968 | static void |
e1382efb | 1969 | logical_ring_default_vfuncs(struct intel_engine_cs *engine) |
c9cacf93 TU |
1970 | { |
1971 | /* Default vfuncs which can be overriden by each engine. */ | |
0bc40be8 TU |
1972 | engine->init_hw = gen8_init_common_ring; |
1973 | engine->emit_request = gen8_emit_request; | |
1974 | engine->emit_flush = gen8_emit_flush; | |
31bb59cc CW |
1975 | engine->irq_enable = gen8_logical_ring_enable_irq; |
1976 | engine->irq_disable = gen8_logical_ring_disable_irq; | |
0bc40be8 | 1977 | engine->emit_bb_start = gen8_emit_bb_start; |
1b7744e7 | 1978 | if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) |
c04e0f3b | 1979 | engine->irq_seqno_barrier = bxt_a_seqno_barrier; |
c9cacf93 TU |
1980 | } |
1981 | ||
d9f3af96 | 1982 | static inline void |
0bc40be8 | 1983 | logical_ring_default_irqs(struct intel_engine_cs *engine, unsigned shift) |
d9f3af96 | 1984 | { |
0bc40be8 TU |
1985 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift; |
1986 | engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift; | |
d9f3af96 TU |
1987 | } |
1988 | ||
7d774cac | 1989 | static int |
04794adb TU |
1990 | lrc_setup_hws(struct intel_engine_cs *engine, |
1991 | struct drm_i915_gem_object *dctx_obj) | |
1992 | { | |
7d774cac | 1993 | void *hws; |
04794adb TU |
1994 | |
1995 | /* The HWSP is part of the default context object in LRC mode. */ | |
1996 | engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(dctx_obj) + | |
1997 | LRC_PPHWSP_PN * PAGE_SIZE; | |
7d774cac TU |
1998 | hws = i915_gem_object_pin_map(dctx_obj); |
1999 | if (IS_ERR(hws)) | |
2000 | return PTR_ERR(hws); | |
2001 | engine->status_page.page_addr = hws + LRC_PPHWSP_PN * PAGE_SIZE; | |
04794adb | 2002 | engine->status_page.obj = dctx_obj; |
7d774cac TU |
2003 | |
2004 | return 0; | |
04794adb TU |
2005 | } |
2006 | ||
a19d6ff2 TU |
2007 | static int |
2008 | logical_ring_init(struct intel_engine_cs *engine) | |
2009 | { | |
2010 | struct i915_gem_context *dctx = engine->i915->kernel_context; | |
2011 | int ret; | |
2012 | ||
688e6c72 CW |
2013 | ret = intel_engine_init_breadcrumbs(engine); |
2014 | if (ret) | |
2015 | goto error; | |
2016 | ||
a19d6ff2 TU |
2017 | ret = i915_cmd_parser_init_ring(engine); |
2018 | if (ret) | |
2019 | goto error; | |
2020 | ||
2021 | ret = execlists_context_deferred_alloc(dctx, engine); | |
2022 | if (ret) | |
2023 | goto error; | |
2024 | ||
2025 | /* As this is the default context, always pin it */ | |
2026 | ret = intel_lr_context_pin(dctx, engine); | |
2027 | if (ret) { | |
2028 | DRM_ERROR("Failed to pin context for %s: %d\n", | |
2029 | engine->name, ret); | |
2030 | goto error; | |
2031 | } | |
2032 | ||
2033 | /* And setup the hardware status page. */ | |
2034 | ret = lrc_setup_hws(engine, dctx->engine[engine->id].state); | |
2035 | if (ret) { | |
2036 | DRM_ERROR("Failed to set up hws %s: %d\n", engine->name, ret); | |
2037 | goto error; | |
2038 | } | |
2039 | ||
2040 | return 0; | |
2041 | ||
2042 | error: | |
2043 | intel_logical_ring_cleanup(engine); | |
2044 | return ret; | |
2045 | } | |
2046 | ||
2047 | static int logical_render_ring_init(struct intel_engine_cs *engine) | |
2048 | { | |
2049 | struct drm_i915_private *dev_priv = engine->i915; | |
2050 | int ret; | |
2051 | ||
2052 | if (HAS_L3_DPF(dev_priv)) | |
2053 | engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
2054 | ||
2055 | /* Override some for render ring. */ | |
2056 | if (INTEL_GEN(dev_priv) >= 9) | |
2057 | engine->init_hw = gen9_init_render_ring; | |
2058 | else | |
2059 | engine->init_hw = gen8_init_render_ring; | |
2060 | engine->init_context = gen8_init_rcs_context; | |
2061 | engine->cleanup = intel_fini_pipe_control; | |
2062 | engine->emit_flush = gen8_emit_flush_render; | |
2063 | engine->emit_request = gen8_emit_request_render; | |
2064 | ||
7d5ea807 | 2065 | ret = intel_init_pipe_control(engine, 4096); |
a19d6ff2 TU |
2066 | if (ret) |
2067 | return ret; | |
2068 | ||
2069 | ret = intel_init_workaround_bb(engine); | |
2070 | if (ret) { | |
2071 | /* | |
2072 | * We continue even if we fail to initialize WA batch | |
2073 | * because we only expect rare glitches but nothing | |
2074 | * critical to prevent us from using GPU | |
2075 | */ | |
2076 | DRM_ERROR("WA batch buffer initialization failed: %d\n", | |
2077 | ret); | |
2078 | } | |
2079 | ||
2080 | ret = logical_ring_init(engine); | |
2081 | if (ret) { | |
2082 | lrc_destroy_wa_ctx_obj(engine); | |
2083 | } | |
2084 | ||
2085 | return ret; | |
2086 | } | |
2087 | ||
e1382efb CW |
2088 | static const struct logical_ring_info { |
2089 | const char *name; | |
2090 | unsigned exec_id; | |
2091 | unsigned guc_id; | |
2092 | u32 mmio_base; | |
2093 | unsigned irq_shift; | |
a19d6ff2 | 2094 | int (*init)(struct intel_engine_cs *engine); |
e1382efb CW |
2095 | } logical_rings[] = { |
2096 | [RCS] = { | |
2097 | .name = "render ring", | |
2098 | .exec_id = I915_EXEC_RENDER, | |
2099 | .guc_id = GUC_RENDER_ENGINE, | |
2100 | .mmio_base = RENDER_RING_BASE, | |
2101 | .irq_shift = GEN8_RCS_IRQ_SHIFT, | |
a19d6ff2 | 2102 | .init = logical_render_ring_init, |
e1382efb CW |
2103 | }, |
2104 | [BCS] = { | |
2105 | .name = "blitter ring", | |
2106 | .exec_id = I915_EXEC_BLT, | |
2107 | .guc_id = GUC_BLITTER_ENGINE, | |
2108 | .mmio_base = BLT_RING_BASE, | |
2109 | .irq_shift = GEN8_BCS_IRQ_SHIFT, | |
a19d6ff2 | 2110 | .init = logical_ring_init, |
e1382efb CW |
2111 | }, |
2112 | [VCS] = { | |
2113 | .name = "bsd ring", | |
2114 | .exec_id = I915_EXEC_BSD, | |
2115 | .guc_id = GUC_VIDEO_ENGINE, | |
2116 | .mmio_base = GEN6_BSD_RING_BASE, | |
2117 | .irq_shift = GEN8_VCS1_IRQ_SHIFT, | |
a19d6ff2 | 2118 | .init = logical_ring_init, |
e1382efb CW |
2119 | }, |
2120 | [VCS2] = { | |
2121 | .name = "bsd2 ring", | |
2122 | .exec_id = I915_EXEC_BSD, | |
2123 | .guc_id = GUC_VIDEO_ENGINE2, | |
2124 | .mmio_base = GEN8_BSD2_RING_BASE, | |
2125 | .irq_shift = GEN8_VCS2_IRQ_SHIFT, | |
a19d6ff2 | 2126 | .init = logical_ring_init, |
e1382efb CW |
2127 | }, |
2128 | [VECS] = { | |
2129 | .name = "video enhancement ring", | |
2130 | .exec_id = I915_EXEC_VEBOX, | |
2131 | .guc_id = GUC_VIDEOENHANCE_ENGINE, | |
2132 | .mmio_base = VEBOX_RING_BASE, | |
2133 | .irq_shift = GEN8_VECS_IRQ_SHIFT, | |
a19d6ff2 | 2134 | .init = logical_ring_init, |
e1382efb CW |
2135 | }, |
2136 | }; | |
2137 | ||
2138 | static struct intel_engine_cs * | |
a19d6ff2 | 2139 | logical_ring_setup(struct drm_i915_private *dev_priv, enum intel_engine_id id) |
454afebd | 2140 | { |
e1382efb | 2141 | const struct logical_ring_info *info = &logical_rings[id]; |
e1382efb | 2142 | struct intel_engine_cs *engine = &dev_priv->engine[id]; |
3756685a | 2143 | enum forcewake_domains fw_domains; |
48d82387 | 2144 | |
e1382efb CW |
2145 | engine->id = id; |
2146 | engine->name = info->name; | |
2147 | engine->exec_id = info->exec_id; | |
2148 | engine->guc_id = info->guc_id; | |
2149 | engine->mmio_base = info->mmio_base; | |
48d82387 | 2150 | |
c033666a | 2151 | engine->i915 = dev_priv; |
acdd884a | 2152 | |
e1382efb CW |
2153 | /* Intentionally left blank. */ |
2154 | engine->buffer = NULL; | |
ca82580c | 2155 | |
3756685a TU |
2156 | fw_domains = intel_uncore_forcewake_for_reg(dev_priv, |
2157 | RING_ELSP(engine), | |
2158 | FW_REG_WRITE); | |
2159 | ||
2160 | fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, | |
2161 | RING_CONTEXT_STATUS_PTR(engine), | |
2162 | FW_REG_READ | FW_REG_WRITE); | |
2163 | ||
2164 | fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, | |
2165 | RING_CONTEXT_STATUS_BUF_BASE(engine), | |
2166 | FW_REG_READ); | |
2167 | ||
2168 | engine->fw_domains = fw_domains; | |
2169 | ||
e1382efb CW |
2170 | INIT_LIST_HEAD(&engine->active_list); |
2171 | INIT_LIST_HEAD(&engine->request_list); | |
2172 | INIT_LIST_HEAD(&engine->buffers); | |
2173 | INIT_LIST_HEAD(&engine->execlist_queue); | |
2174 | spin_lock_init(&engine->execlist_lock); | |
2175 | ||
2176 | tasklet_init(&engine->irq_tasklet, | |
2177 | intel_lrc_irq_handler, (unsigned long)engine); | |
2178 | ||
2179 | logical_ring_init_platform_invariants(engine); | |
2180 | logical_ring_default_vfuncs(engine); | |
2181 | logical_ring_default_irqs(engine, info->irq_shift); | |
2182 | ||
2183 | intel_engine_init_hangcheck(engine); | |
91c8a326 | 2184 | i915_gem_batch_pool_init(&dev_priv->drm, &engine->batch_pool); |
e1382efb CW |
2185 | |
2186 | return engine; | |
2187 | } | |
2188 | ||
73e4d07f OM |
2189 | /** |
2190 | * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers | |
2191 | * @dev: DRM device. | |
2192 | * | |
a19d6ff2 TU |
2193 | * This function inits the engines for an Execlists submission style (the |
2194 | * equivalent in the legacy ringbuffer submission world would be | |
2195 | * i915_gem_init_engines). It does it only for those engines that are present in | |
2196 | * the hardware. | |
73e4d07f OM |
2197 | * |
2198 | * Return: non-zero if the initialization failed. | |
2199 | */ | |
454afebd OM |
2200 | int intel_logical_rings_init(struct drm_device *dev) |
2201 | { | |
fac5e23e | 2202 | struct drm_i915_private *dev_priv = to_i915(dev); |
a19d6ff2 TU |
2203 | unsigned int mask = 0; |
2204 | unsigned int i; | |
454afebd OM |
2205 | int ret; |
2206 | ||
a19d6ff2 TU |
2207 | WARN_ON(INTEL_INFO(dev_priv)->ring_mask & |
2208 | GENMASK(sizeof(mask) * BITS_PER_BYTE - 1, I915_NUM_ENGINES)); | |
454afebd | 2209 | |
a19d6ff2 TU |
2210 | for (i = 0; i < ARRAY_SIZE(logical_rings); i++) { |
2211 | if (!HAS_ENGINE(dev_priv, i)) | |
2212 | continue; | |
454afebd | 2213 | |
a19d6ff2 TU |
2214 | if (!logical_rings[i].init) |
2215 | continue; | |
454afebd | 2216 | |
a19d6ff2 | 2217 | ret = logical_rings[i].init(logical_ring_setup(dev_priv, i)); |
454afebd | 2218 | if (ret) |
a19d6ff2 TU |
2219 | goto cleanup; |
2220 | ||
2221 | mask |= ENGINE_MASK(i); | |
454afebd OM |
2222 | } |
2223 | ||
a19d6ff2 TU |
2224 | /* |
2225 | * Catch failures to update logical_rings table when the new engines | |
2226 | * are added to the driver by a warning and disabling the forgotten | |
2227 | * engines. | |
2228 | */ | |
2229 | if (WARN_ON(mask != INTEL_INFO(dev_priv)->ring_mask)) { | |
2230 | struct intel_device_info *info = | |
2231 | (struct intel_device_info *)&dev_priv->info; | |
2232 | info->ring_mask = mask; | |
454afebd OM |
2233 | } |
2234 | ||
454afebd OM |
2235 | return 0; |
2236 | ||
a19d6ff2 TU |
2237 | cleanup: |
2238 | for (i = 0; i < I915_NUM_ENGINES; i++) | |
2239 | intel_logical_ring_cleanup(&dev_priv->engine[i]); | |
454afebd OM |
2240 | |
2241 | return ret; | |
2242 | } | |
2243 | ||
0cea6502 | 2244 | static u32 |
c033666a | 2245 | make_rpcs(struct drm_i915_private *dev_priv) |
0cea6502 JM |
2246 | { |
2247 | u32 rpcs = 0; | |
2248 | ||
2249 | /* | |
2250 | * No explicit RPCS request is needed to ensure full | |
2251 | * slice/subslice/EU enablement prior to Gen9. | |
2252 | */ | |
c033666a | 2253 | if (INTEL_GEN(dev_priv) < 9) |
0cea6502 JM |
2254 | return 0; |
2255 | ||
2256 | /* | |
2257 | * Starting in Gen9, render power gating can leave | |
2258 | * slice/subslice/EU in a partially enabled state. We | |
2259 | * must make an explicit request through RPCS for full | |
2260 | * enablement. | |
2261 | */ | |
c033666a | 2262 | if (INTEL_INFO(dev_priv)->has_slice_pg) { |
0cea6502 | 2263 | rpcs |= GEN8_RPCS_S_CNT_ENABLE; |
c033666a | 2264 | rpcs |= INTEL_INFO(dev_priv)->slice_total << |
0cea6502 JM |
2265 | GEN8_RPCS_S_CNT_SHIFT; |
2266 | rpcs |= GEN8_RPCS_ENABLE; | |
2267 | } | |
2268 | ||
c033666a | 2269 | if (INTEL_INFO(dev_priv)->has_subslice_pg) { |
0cea6502 | 2270 | rpcs |= GEN8_RPCS_SS_CNT_ENABLE; |
c033666a | 2271 | rpcs |= INTEL_INFO(dev_priv)->subslice_per_slice << |
0cea6502 JM |
2272 | GEN8_RPCS_SS_CNT_SHIFT; |
2273 | rpcs |= GEN8_RPCS_ENABLE; | |
2274 | } | |
2275 | ||
c033666a CW |
2276 | if (INTEL_INFO(dev_priv)->has_eu_pg) { |
2277 | rpcs |= INTEL_INFO(dev_priv)->eu_per_subslice << | |
0cea6502 | 2278 | GEN8_RPCS_EU_MIN_SHIFT; |
c033666a | 2279 | rpcs |= INTEL_INFO(dev_priv)->eu_per_subslice << |
0cea6502 JM |
2280 | GEN8_RPCS_EU_MAX_SHIFT; |
2281 | rpcs |= GEN8_RPCS_ENABLE; | |
2282 | } | |
2283 | ||
2284 | return rpcs; | |
2285 | } | |
2286 | ||
0bc40be8 | 2287 | static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine) |
71562919 MT |
2288 | { |
2289 | u32 indirect_ctx_offset; | |
2290 | ||
c033666a | 2291 | switch (INTEL_GEN(engine->i915)) { |
71562919 | 2292 | default: |
c033666a | 2293 | MISSING_CASE(INTEL_GEN(engine->i915)); |
71562919 MT |
2294 | /* fall through */ |
2295 | case 9: | |
2296 | indirect_ctx_offset = | |
2297 | GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
2298 | break; | |
2299 | case 8: | |
2300 | indirect_ctx_offset = | |
2301 | GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
2302 | break; | |
2303 | } | |
2304 | ||
2305 | return indirect_ctx_offset; | |
2306 | } | |
2307 | ||
8670d6f9 | 2308 | static int |
e2efd130 | 2309 | populate_lr_context(struct i915_gem_context *ctx, |
7d774cac | 2310 | struct drm_i915_gem_object *ctx_obj, |
0bc40be8 TU |
2311 | struct intel_engine_cs *engine, |
2312 | struct intel_ringbuffer *ringbuf) | |
8670d6f9 | 2313 | { |
c033666a | 2314 | struct drm_i915_private *dev_priv = ctx->i915; |
ae6c4806 | 2315 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
7d774cac TU |
2316 | void *vaddr; |
2317 | u32 *reg_state; | |
8670d6f9 OM |
2318 | int ret; |
2319 | ||
2d965536 TD |
2320 | if (!ppgtt) |
2321 | ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2322 | ||
8670d6f9 OM |
2323 | ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); |
2324 | if (ret) { | |
2325 | DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); | |
2326 | return ret; | |
2327 | } | |
2328 | ||
7d774cac TU |
2329 | vaddr = i915_gem_object_pin_map(ctx_obj); |
2330 | if (IS_ERR(vaddr)) { | |
2331 | ret = PTR_ERR(vaddr); | |
2332 | DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret); | |
8670d6f9 OM |
2333 | return ret; |
2334 | } | |
7d774cac | 2335 | ctx_obj->dirty = true; |
8670d6f9 OM |
2336 | |
2337 | /* The second page of the context object contains some fields which must | |
2338 | * be set up prior to the first execution. */ | |
7d774cac | 2339 | reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; |
8670d6f9 OM |
2340 | |
2341 | /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM | |
2342 | * commands followed by (reg, value) pairs. The values we are setting here are | |
2343 | * only for the first context restore: on a subsequent save, the GPU will | |
2344 | * recreate this batchbuffer with new values (including all the missing | |
2345 | * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */ | |
0d925ea0 | 2346 | reg_state[CTX_LRI_HEADER_0] = |
0bc40be8 TU |
2347 | MI_LOAD_REGISTER_IMM(engine->id == RCS ? 14 : 11) | MI_LRI_FORCE_POSTED; |
2348 | ASSIGN_CTX_REG(reg_state, CTX_CONTEXT_CONTROL, | |
2349 | RING_CONTEXT_CONTROL(engine), | |
0d925ea0 VS |
2350 | _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | |
2351 | CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | | |
c033666a | 2352 | (HAS_RESOURCE_STREAMER(dev_priv) ? |
99cf8ea1 | 2353 | CTX_CTRL_RS_CTX_ENABLE : 0))); |
0bc40be8 TU |
2354 | ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(engine->mmio_base), |
2355 | 0); | |
2356 | ASSIGN_CTX_REG(reg_state, CTX_RING_TAIL, RING_TAIL(engine->mmio_base), | |
2357 | 0); | |
7ba717cf TD |
2358 | /* Ring buffer start address is not known until the buffer is pinned. |
2359 | * It is written to the context image in execlists_update_context() | |
2360 | */ | |
0bc40be8 TU |
2361 | ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_START, |
2362 | RING_START(engine->mmio_base), 0); | |
2363 | ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_CONTROL, | |
2364 | RING_CTL(engine->mmio_base), | |
0d925ea0 | 2365 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID); |
0bc40be8 TU |
2366 | ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_U, |
2367 | RING_BBADDR_UDW(engine->mmio_base), 0); | |
2368 | ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_L, | |
2369 | RING_BBADDR(engine->mmio_base), 0); | |
2370 | ASSIGN_CTX_REG(reg_state, CTX_BB_STATE, | |
2371 | RING_BBSTATE(engine->mmio_base), | |
0d925ea0 | 2372 | RING_BB_PPGTT); |
0bc40be8 TU |
2373 | ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_U, |
2374 | RING_SBBADDR_UDW(engine->mmio_base), 0); | |
2375 | ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_L, | |
2376 | RING_SBBADDR(engine->mmio_base), 0); | |
2377 | ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_STATE, | |
2378 | RING_SBBSTATE(engine->mmio_base), 0); | |
2379 | if (engine->id == RCS) { | |
2380 | ASSIGN_CTX_REG(reg_state, CTX_BB_PER_CTX_PTR, | |
2381 | RING_BB_PER_CTX_PTR(engine->mmio_base), 0); | |
2382 | ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX, | |
2383 | RING_INDIRECT_CTX(engine->mmio_base), 0); | |
2384 | ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX_OFFSET, | |
2385 | RING_INDIRECT_CTX_OFFSET(engine->mmio_base), 0); | |
2386 | if (engine->wa_ctx.obj) { | |
2387 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; | |
17ee950d AS |
2388 | uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj); |
2389 | ||
2390 | reg_state[CTX_RCS_INDIRECT_CTX+1] = | |
2391 | (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) | | |
2392 | (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS); | |
2393 | ||
2394 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = | |
0bc40be8 | 2395 | intel_lr_indirect_ctx_offset(engine) << 6; |
17ee950d AS |
2396 | |
2397 | reg_state[CTX_BB_PER_CTX_PTR+1] = | |
2398 | (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) | | |
2399 | 0x01; | |
2400 | } | |
8670d6f9 | 2401 | } |
0d925ea0 | 2402 | reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED; |
0bc40be8 TU |
2403 | ASSIGN_CTX_REG(reg_state, CTX_CTX_TIMESTAMP, |
2404 | RING_CTX_TIMESTAMP(engine->mmio_base), 0); | |
0d925ea0 | 2405 | /* PDP values well be assigned later if needed */ |
0bc40be8 TU |
2406 | ASSIGN_CTX_REG(reg_state, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), |
2407 | 0); | |
2408 | ASSIGN_CTX_REG(reg_state, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), | |
2409 | 0); | |
2410 | ASSIGN_CTX_REG(reg_state, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), | |
2411 | 0); | |
2412 | ASSIGN_CTX_REG(reg_state, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), | |
2413 | 0); | |
2414 | ASSIGN_CTX_REG(reg_state, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), | |
2415 | 0); | |
2416 | ASSIGN_CTX_REG(reg_state, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), | |
2417 | 0); | |
2418 | ASSIGN_CTX_REG(reg_state, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), | |
2419 | 0); | |
2420 | ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), | |
2421 | 0); | |
d7b2633d | 2422 | |
2dba3239 MT |
2423 | if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) { |
2424 | /* 64b PPGTT (48bit canonical) | |
2425 | * PDP0_DESCRIPTOR contains the base address to PML4 and | |
2426 | * other PDP Descriptors are ignored. | |
2427 | */ | |
2428 | ASSIGN_CTX_PML4(ppgtt, reg_state); | |
2429 | } else { | |
2430 | /* 32b PPGTT | |
2431 | * PDP*_DESCRIPTOR contains the base address of space supported. | |
2432 | * With dynamic page allocation, PDPs may not be allocated at | |
2433 | * this point. Point the unallocated PDPs to the scratch page | |
2434 | */ | |
c6a2ac71 | 2435 | execlists_update_context_pdps(ppgtt, reg_state); |
2dba3239 MT |
2436 | } |
2437 | ||
0bc40be8 | 2438 | if (engine->id == RCS) { |
8670d6f9 | 2439 | reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); |
0d925ea0 | 2440 | ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, |
c033666a | 2441 | make_rpcs(dev_priv)); |
8670d6f9 OM |
2442 | } |
2443 | ||
7d774cac | 2444 | i915_gem_object_unpin_map(ctx_obj); |
8670d6f9 OM |
2445 | |
2446 | return 0; | |
2447 | } | |
2448 | ||
c5d46ee2 DG |
2449 | /** |
2450 | * intel_lr_context_size() - return the size of the context for an engine | |
14bb2c11 | 2451 | * @engine: which engine to find the context size for |
c5d46ee2 DG |
2452 | * |
2453 | * Each engine may require a different amount of space for a context image, | |
2454 | * so when allocating (or copying) an image, this function can be used to | |
2455 | * find the right size for the specific engine. | |
2456 | * | |
2457 | * Return: size (in bytes) of an engine-specific context image | |
2458 | * | |
2459 | * Note: this size includes the HWSP, which is part of the context image | |
2460 | * in LRC mode, but does not include the "shared data page" used with | |
2461 | * GuC submission. The caller should account for this if using the GuC. | |
2462 | */ | |
0bc40be8 | 2463 | uint32_t intel_lr_context_size(struct intel_engine_cs *engine) |
8c857917 OM |
2464 | { |
2465 | int ret = 0; | |
2466 | ||
c033666a | 2467 | WARN_ON(INTEL_GEN(engine->i915) < 8); |
8c857917 | 2468 | |
0bc40be8 | 2469 | switch (engine->id) { |
8c857917 | 2470 | case RCS: |
c033666a | 2471 | if (INTEL_GEN(engine->i915) >= 9) |
468c6816 MN |
2472 | ret = GEN9_LR_CONTEXT_RENDER_SIZE; |
2473 | else | |
2474 | ret = GEN8_LR_CONTEXT_RENDER_SIZE; | |
8c857917 OM |
2475 | break; |
2476 | case VCS: | |
2477 | case BCS: | |
2478 | case VECS: | |
2479 | case VCS2: | |
2480 | ret = GEN8_LR_CONTEXT_OTHER_SIZE; | |
2481 | break; | |
2482 | } | |
2483 | ||
2484 | return ret; | |
ede7d42b OM |
2485 | } |
2486 | ||
73e4d07f | 2487 | /** |
978f1e09 | 2488 | * execlists_context_deferred_alloc() - create the LRC specific bits of a context |
73e4d07f | 2489 | * @ctx: LR context to create. |
978f1e09 | 2490 | * @engine: engine to be used with the context. |
73e4d07f OM |
2491 | * |
2492 | * This function can be called more than once, with different engines, if we plan | |
2493 | * to use the context with them. The context backing objects and the ringbuffers | |
2494 | * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why | |
2495 | * the creation is a deferred call: it's better to make sure first that we need to use | |
2496 | * a given ring with the context. | |
2497 | * | |
32197aab | 2498 | * Return: non-zero on error. |
73e4d07f | 2499 | */ |
e2efd130 | 2500 | static int execlists_context_deferred_alloc(struct i915_gem_context *ctx, |
978f1e09 | 2501 | struct intel_engine_cs *engine) |
ede7d42b | 2502 | { |
8c857917 | 2503 | struct drm_i915_gem_object *ctx_obj; |
9021ad03 | 2504 | struct intel_context *ce = &ctx->engine[engine->id]; |
8c857917 | 2505 | uint32_t context_size; |
84c2377f | 2506 | struct intel_ringbuffer *ringbuf; |
8c857917 OM |
2507 | int ret; |
2508 | ||
9021ad03 | 2509 | WARN_ON(ce->state); |
ede7d42b | 2510 | |
0bc40be8 | 2511 | context_size = round_up(intel_lr_context_size(engine), 4096); |
8c857917 | 2512 | |
d1675198 AD |
2513 | /* One extra page as the sharing data between driver and GuC */ |
2514 | context_size += PAGE_SIZE * LRC_PPHWSP_PN; | |
2515 | ||
91c8a326 | 2516 | ctx_obj = i915_gem_object_create(&ctx->i915->drm, context_size); |
fe3db79b | 2517 | if (IS_ERR(ctx_obj)) { |
3126a660 | 2518 | DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n"); |
fe3db79b | 2519 | return PTR_ERR(ctx_obj); |
8c857917 OM |
2520 | } |
2521 | ||
bcd794c2 | 2522 | ringbuf = intel_engine_create_ringbuffer(engine, ctx->ring_size); |
01101fa7 CW |
2523 | if (IS_ERR(ringbuf)) { |
2524 | ret = PTR_ERR(ringbuf); | |
e84fe803 | 2525 | goto error_deref_obj; |
8670d6f9 OM |
2526 | } |
2527 | ||
0bc40be8 | 2528 | ret = populate_lr_context(ctx, ctx_obj, engine, ringbuf); |
8670d6f9 OM |
2529 | if (ret) { |
2530 | DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); | |
e84fe803 | 2531 | goto error_ringbuf; |
84c2377f OM |
2532 | } |
2533 | ||
9021ad03 CW |
2534 | ce->ringbuf = ringbuf; |
2535 | ce->state = ctx_obj; | |
2536 | ce->initialised = engine->init_context == NULL; | |
ede7d42b OM |
2537 | |
2538 | return 0; | |
8670d6f9 | 2539 | |
01101fa7 CW |
2540 | error_ringbuf: |
2541 | intel_ringbuffer_free(ringbuf); | |
e84fe803 | 2542 | error_deref_obj: |
8670d6f9 | 2543 | drm_gem_object_unreference(&ctx_obj->base); |
9021ad03 CW |
2544 | ce->ringbuf = NULL; |
2545 | ce->state = NULL; | |
8670d6f9 | 2546 | return ret; |
ede7d42b | 2547 | } |
3e5b6f05 | 2548 | |
7d774cac | 2549 | void intel_lr_context_reset(struct drm_i915_private *dev_priv, |
e2efd130 | 2550 | struct i915_gem_context *ctx) |
3e5b6f05 | 2551 | { |
e2f80391 | 2552 | struct intel_engine_cs *engine; |
3e5b6f05 | 2553 | |
b4ac5afc | 2554 | for_each_engine(engine, dev_priv) { |
9021ad03 CW |
2555 | struct intel_context *ce = &ctx->engine[engine->id]; |
2556 | struct drm_i915_gem_object *ctx_obj = ce->state; | |
7d774cac | 2557 | void *vaddr; |
3e5b6f05 | 2558 | uint32_t *reg_state; |
3e5b6f05 TD |
2559 | |
2560 | if (!ctx_obj) | |
2561 | continue; | |
2562 | ||
7d774cac TU |
2563 | vaddr = i915_gem_object_pin_map(ctx_obj); |
2564 | if (WARN_ON(IS_ERR(vaddr))) | |
3e5b6f05 | 2565 | continue; |
7d774cac TU |
2566 | |
2567 | reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; | |
2568 | ctx_obj->dirty = true; | |
3e5b6f05 TD |
2569 | |
2570 | reg_state[CTX_RING_HEAD+1] = 0; | |
2571 | reg_state[CTX_RING_TAIL+1] = 0; | |
2572 | ||
7d774cac | 2573 | i915_gem_object_unpin_map(ctx_obj); |
3e5b6f05 | 2574 | |
9021ad03 CW |
2575 | ce->ringbuf->head = 0; |
2576 | ce->ringbuf->tail = 0; | |
3e5b6f05 TD |
2577 | } |
2578 | } |