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79e53945 JB |
1 | /* |
2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
f899fc64 | 3 | * Copyright © 2006-2008,2010 Intel Corporation |
79e53945 JB |
4 | * Jesse Barnes <jesse.barnes@intel.com> |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
23 | * DEALINGS IN THE SOFTWARE. | |
24 | * | |
25 | * Authors: | |
26 | * Eric Anholt <eric@anholt.net> | |
f899fc64 | 27 | * Chris Wilson <chris@chris-wilson.co.uk> |
79e53945 JB |
28 | */ |
29 | #include <linux/i2c.h> | |
79e53945 | 30 | #include <linux/i2c-algo-bit.h> |
2d1a8a48 | 31 | #include <linux/export.h> |
760285e7 | 32 | #include <drm/drmP.h> |
79e53945 | 33 | #include "intel_drv.h" |
760285e7 | 34 | #include <drm/i915_drm.h> |
79e53945 JB |
35 | #include "i915_drv.h" |
36 | ||
5ea6e5e3 | 37 | struct gmbus_pin { |
2ed06c93 | 38 | const char *name; |
f0f59a00 | 39 | i915_reg_t reg; |
2ed06c93 DK |
40 | }; |
41 | ||
5ea6e5e3 JN |
42 | /* Map gmbus pin pairs to names and registers. */ |
43 | static const struct gmbus_pin gmbus_pins[] = { | |
44 | [GMBUS_PIN_SSC] = { "ssc", GPIOB }, | |
45 | [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, | |
46 | [GMBUS_PIN_PANEL] = { "panel", GPIOC }, | |
47 | [GMBUS_PIN_DPC] = { "dpc", GPIOD }, | |
48 | [GMBUS_PIN_DPB] = { "dpb", GPIOE }, | |
49 | [GMBUS_PIN_DPD] = { "dpd", GPIOF }, | |
2ed06c93 DK |
50 | }; |
51 | ||
c1bad5b6 JN |
52 | static const struct gmbus_pin gmbus_pins_bdw[] = { |
53 | [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, | |
54 | [GMBUS_PIN_DPC] = { "dpc", GPIOD }, | |
55 | [GMBUS_PIN_DPB] = { "dpb", GPIOE }, | |
56 | [GMBUS_PIN_DPD] = { "dpd", GPIOF }, | |
57 | }; | |
58 | ||
6364e67e JN |
59 | static const struct gmbus_pin gmbus_pins_skl[] = { |
60 | [GMBUS_PIN_DPC] = { "dpc", GPIOD }, | |
61 | [GMBUS_PIN_DPB] = { "dpb", GPIOE }, | |
62 | [GMBUS_PIN_DPD] = { "dpd", GPIOF }, | |
63 | }; | |
64 | ||
4c272834 | 65 | static const struct gmbus_pin gmbus_pins_bxt[] = { |
b2e8c6cd VS |
66 | [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, |
67 | [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, | |
68 | [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, | |
4c272834 JN |
69 | }; |
70 | ||
3d02352c RV |
71 | static const struct gmbus_pin gmbus_pins_cnp[] = { |
72 | [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, | |
73 | [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, | |
74 | [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, | |
75 | [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, | |
76 | }; | |
77 | ||
4c272834 JN |
78 | /* pin is expected to be valid */ |
79 | static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv, | |
80 | unsigned int pin) | |
81 | { | |
3d02352c RV |
82 | if (HAS_PCH_CNP(dev_priv)) |
83 | return &gmbus_pins_cnp[pin]; | |
84 | else if (IS_GEN9_LP(dev_priv)) | |
4c272834 | 85 | return &gmbus_pins_bxt[pin]; |
b976dc53 | 86 | else if (IS_GEN9_BC(dev_priv)) |
6364e67e | 87 | return &gmbus_pins_skl[pin]; |
c1bad5b6 JN |
88 | else if (IS_BROADWELL(dev_priv)) |
89 | return &gmbus_pins_bdw[pin]; | |
4c272834 JN |
90 | else |
91 | return &gmbus_pins[pin]; | |
92 | } | |
93 | ||
88ac7939 JN |
94 | bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, |
95 | unsigned int pin) | |
96 | { | |
4c272834 JN |
97 | unsigned int size; |
98 | ||
3d02352c RV |
99 | if (HAS_PCH_CNP(dev_priv)) |
100 | size = ARRAY_SIZE(gmbus_pins_cnp); | |
101 | else if (IS_GEN9_LP(dev_priv)) | |
4c272834 | 102 | size = ARRAY_SIZE(gmbus_pins_bxt); |
b976dc53 | 103 | else if (IS_GEN9_BC(dev_priv)) |
6364e67e | 104 | size = ARRAY_SIZE(gmbus_pins_skl); |
c1bad5b6 JN |
105 | else if (IS_BROADWELL(dev_priv)) |
106 | size = ARRAY_SIZE(gmbus_pins_bdw); | |
4c272834 JN |
107 | else |
108 | size = ARRAY_SIZE(gmbus_pins); | |
109 | ||
f0f59a00 VS |
110 | return pin < size && |
111 | i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg); | |
88ac7939 JN |
112 | } |
113 | ||
f899fc64 CW |
114 | /* Intel GPIO access functions */ |
115 | ||
1849ecb2 | 116 | #define I2C_RISEFALL_TIME 10 |
f899fc64 | 117 | |
e957d772 CW |
118 | static inline struct intel_gmbus * |
119 | to_intel_gmbus(struct i2c_adapter *i2c) | |
120 | { | |
121 | return container_of(i2c, struct intel_gmbus, adapter); | |
122 | } | |
123 | ||
f899fc64 | 124 | void |
af6dc742 | 125 | intel_i2c_reset(struct drm_i915_private *dev_priv) |
0ba0e9e1 | 126 | { |
699fc401 VS |
127 | I915_WRITE(GMBUS0, 0); |
128 | I915_WRITE(GMBUS4, 0); | |
f899fc64 CW |
129 | } |
130 | ||
ad8059cf VS |
131 | static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv, |
132 | bool enable) | |
f899fc64 | 133 | { |
b222f267 | 134 | u32 val; |
0ba0e9e1 SL |
135 | |
136 | /* When using bit bashing for I2C, this bit needs to be set to 1 */ | |
b222f267 | 137 | val = I915_READ(DSPCLK_GATE_D); |
ad8059cf VS |
138 | if (!enable) |
139 | val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; | |
0ba0e9e1 | 140 | else |
ad8059cf | 141 | val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; |
b222f267 | 142 | I915_WRITE(DSPCLK_GATE_D, val); |
0ba0e9e1 SL |
143 | } |
144 | ||
6481d5ed VS |
145 | static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv, |
146 | bool enable) | |
147 | { | |
148 | u32 val; | |
149 | ||
150 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
151 | if (!enable) | |
152 | val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; | |
153 | else | |
154 | val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; | |
155 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
156 | } | |
157 | ||
158 | static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv, | |
159 | bool enable) | |
160 | { | |
161 | u32 val; | |
162 | ||
163 | val = I915_READ(GEN9_CLKGATE_DIS_4); | |
164 | if (!enable) | |
165 | val |= BXT_GMBUS_GATING_DIS; | |
166 | else | |
167 | val &= ~BXT_GMBUS_GATING_DIS; | |
168 | I915_WRITE(GEN9_CLKGATE_DIS_4, val); | |
169 | } | |
170 | ||
36c785f0 | 171 | static u32 get_reserved(struct intel_gmbus *bus) |
e957d772 | 172 | { |
36c785f0 | 173 | struct drm_i915_private *dev_priv = bus->dev_priv; |
e957d772 CW |
174 | u32 reserved = 0; |
175 | ||
176 | /* On most chips, these bits must be preserved in software. */ | |
2a307c2e | 177 | if (!IS_I830(dev_priv) && !IS_I845G(dev_priv)) |
36c785f0 | 178 | reserved = I915_READ_NOTRACE(bus->gpio_reg) & |
db5e4172 YL |
179 | (GPIO_DATA_PULLUP_DISABLE | |
180 | GPIO_CLOCK_PULLUP_DISABLE); | |
e957d772 CW |
181 | |
182 | return reserved; | |
183 | } | |
184 | ||
79e53945 JB |
185 | static int get_clock(void *data) |
186 | { | |
36c785f0 DV |
187 | struct intel_gmbus *bus = data; |
188 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
189 | u32 reserved = get_reserved(bus); | |
190 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK); | |
191 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved); | |
192 | return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0; | |
79e53945 JB |
193 | } |
194 | ||
195 | static int get_data(void *data) | |
196 | { | |
36c785f0 DV |
197 | struct intel_gmbus *bus = data; |
198 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
199 | u32 reserved = get_reserved(bus); | |
200 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK); | |
201 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved); | |
202 | return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0; | |
79e53945 JB |
203 | } |
204 | ||
205 | static void set_clock(void *data, int state_high) | |
206 | { | |
36c785f0 DV |
207 | struct intel_gmbus *bus = data; |
208 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
209 | u32 reserved = get_reserved(bus); | |
e957d772 | 210 | u32 clock_bits; |
79e53945 JB |
211 | |
212 | if (state_high) | |
213 | clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; | |
214 | else | |
215 | clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | | |
216 | GPIO_CLOCK_VAL_MASK; | |
f899fc64 | 217 | |
36c785f0 DV |
218 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits); |
219 | POSTING_READ(bus->gpio_reg); | |
79e53945 JB |
220 | } |
221 | ||
222 | static void set_data(void *data, int state_high) | |
223 | { | |
36c785f0 DV |
224 | struct intel_gmbus *bus = data; |
225 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
226 | u32 reserved = get_reserved(bus); | |
e957d772 | 227 | u32 data_bits; |
79e53945 JB |
228 | |
229 | if (state_high) | |
230 | data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; | |
231 | else | |
232 | data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | | |
233 | GPIO_DATA_VAL_MASK; | |
234 | ||
36c785f0 DV |
235 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits); |
236 | POSTING_READ(bus->gpio_reg); | |
79e53945 JB |
237 | } |
238 | ||
489fbc10 DK |
239 | static int |
240 | intel_gpio_pre_xfer(struct i2c_adapter *adapter) | |
241 | { | |
242 | struct intel_gmbus *bus = container_of(adapter, | |
243 | struct intel_gmbus, | |
244 | adapter); | |
245 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
246 | ||
af6dc742 | 247 | intel_i2c_reset(dev_priv); |
ad8059cf VS |
248 | |
249 | if (IS_PINEVIEW(dev_priv)) | |
250 | pnv_gmbus_clock_gating(dev_priv, false); | |
251 | ||
489fbc10 DK |
252 | set_data(bus, 1); |
253 | set_clock(bus, 1); | |
254 | udelay(I2C_RISEFALL_TIME); | |
255 | return 0; | |
256 | } | |
257 | ||
258 | static void | |
259 | intel_gpio_post_xfer(struct i2c_adapter *adapter) | |
260 | { | |
261 | struct intel_gmbus *bus = container_of(adapter, | |
262 | struct intel_gmbus, | |
263 | adapter); | |
264 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
265 | ||
266 | set_data(bus, 1); | |
267 | set_clock(bus, 1); | |
ad8059cf VS |
268 | |
269 | if (IS_PINEVIEW(dev_priv)) | |
270 | pnv_gmbus_clock_gating(dev_priv, true); | |
489fbc10 DK |
271 | } |
272 | ||
2ed06c93 | 273 | static void |
5ea6e5e3 | 274 | intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin) |
f0217c42 | 275 | { |
36c785f0 | 276 | struct drm_i915_private *dev_priv = bus->dev_priv; |
36c785f0 | 277 | struct i2c_algo_bit_data *algo; |
f0217c42 | 278 | |
c167a6fc | 279 | algo = &bus->bit_algo; |
36c785f0 | 280 | |
f0f59a00 VS |
281 | bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base + |
282 | i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg)); | |
c167a6fc | 283 | bus->adapter.algo_data = algo; |
36c785f0 DV |
284 | algo->setsda = set_data; |
285 | algo->setscl = set_clock; | |
286 | algo->getsda = get_data; | |
287 | algo->getscl = get_clock; | |
489fbc10 DK |
288 | algo->pre_xfer = intel_gpio_pre_xfer; |
289 | algo->post_xfer = intel_gpio_post_xfer; | |
36c785f0 DV |
290 | algo->udelay = I2C_RISEFALL_TIME; |
291 | algo->timeout = usecs_to_jiffies(2200); | |
292 | algo->data = bus; | |
79e53945 JB |
293 | } |
294 | ||
4e6c2d58 | 295 | static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en) |
61168c53 | 296 | { |
28c70f16 | 297 | DEFINE_WAIT(wait); |
4e6c2d58 CW |
298 | u32 gmbus2; |
299 | int ret; | |
c12aba5a | 300 | |
28c70f16 DV |
301 | /* Important: The hw handles only the first bit, so set only one! Since |
302 | * we also need to check for NAKs besides the hw ready/idle signal, we | |
4e6c2d58 CW |
303 | * need to wake up periodically and check that ourselves. |
304 | */ | |
305 | if (!HAS_GMBUS_IRQ(dev_priv)) | |
306 | irq_en = 0; | |
28c70f16 | 307 | |
4e6c2d58 CW |
308 | add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); |
309 | I915_WRITE_FW(GMBUS4, irq_en); | |
61168c53 | 310 | |
4e6c2d58 CW |
311 | status |= GMBUS_SATOER; |
312 | ret = wait_for_us((gmbus2 = I915_READ_FW(GMBUS2)) & status, 2); | |
313 | if (ret) | |
314 | ret = wait_for((gmbus2 = I915_READ_FW(GMBUS2)) & status, 50); | |
28c70f16 | 315 | |
4e6c2d58 CW |
316 | I915_WRITE_FW(GMBUS4, 0); |
317 | remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); | |
61168c53 DV |
318 | |
319 | if (gmbus2 & GMBUS_SATOER) | |
320 | return -ENXIO; | |
4e6c2d58 CW |
321 | |
322 | return ret; | |
61168c53 DV |
323 | } |
324 | ||
2c438c02 DV |
325 | static int |
326 | gmbus_wait_idle(struct drm_i915_private *dev_priv) | |
327 | { | |
4e6c2d58 CW |
328 | DEFINE_WAIT(wait); |
329 | u32 irq_enable; | |
2c438c02 | 330 | int ret; |
2c438c02 | 331 | |
2c438c02 | 332 | /* Important: The hw handles only the first bit, so set only one! */ |
4e6c2d58 CW |
333 | irq_enable = 0; |
334 | if (HAS_GMBUS_IRQ(dev_priv)) | |
335 | irq_enable = GMBUS_IDLE_EN; | |
2c438c02 | 336 | |
4e6c2d58 CW |
337 | add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); |
338 | I915_WRITE_FW(GMBUS4, irq_enable); | |
2c438c02 | 339 | |
4e6c2d58 CW |
340 | ret = intel_wait_for_register_fw(dev_priv, |
341 | GMBUS2, GMBUS_ACTIVE, 0, | |
342 | 10); | |
2c438c02 | 343 | |
4e6c2d58 CW |
344 | I915_WRITE_FW(GMBUS4, 0); |
345 | remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); | |
346 | ||
347 | return ret; | |
2c438c02 DV |
348 | } |
349 | ||
924a93ed | 350 | static int |
9535c475 DT |
351 | gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, |
352 | unsigned short addr, u8 *buf, unsigned int len, | |
353 | u32 gmbus1_index) | |
924a93ed | 354 | { |
4e6c2d58 CW |
355 | I915_WRITE_FW(GMBUS1, |
356 | gmbus1_index | | |
357 | GMBUS_CYCLE_WAIT | | |
358 | (len << GMBUS_BYTE_COUNT_SHIFT) | | |
359 | (addr << GMBUS_SLAVE_ADDR_SHIFT) | | |
360 | GMBUS_SLAVE_READ | GMBUS_SW_RDY); | |
79985eee | 361 | while (len) { |
90e6b26d | 362 | int ret; |
924a93ed DK |
363 | u32 val, loop = 0; |
364 | ||
4e6c2d58 | 365 | ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); |
90e6b26d | 366 | if (ret) |
61168c53 | 367 | return ret; |
924a93ed | 368 | |
4e6c2d58 | 369 | val = I915_READ_FW(GMBUS3); |
924a93ed DK |
370 | do { |
371 | *buf++ = val & 0xff; | |
372 | val >>= 8; | |
373 | } while (--len && ++loop < 4); | |
79985eee | 374 | } |
924a93ed DK |
375 | |
376 | return 0; | |
377 | } | |
378 | ||
379 | static int | |
9535c475 DT |
380 | gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, |
381 | u32 gmbus1_index) | |
924a93ed | 382 | { |
924a93ed | 383 | u8 *buf = msg->buf; |
9535c475 DT |
384 | unsigned int rx_size = msg->len; |
385 | unsigned int len; | |
386 | int ret; | |
387 | ||
388 | do { | |
389 | len = min(rx_size, GMBUS_BYTE_COUNT_MAX); | |
390 | ||
391 | ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, | |
392 | buf, len, gmbus1_index); | |
393 | if (ret) | |
394 | return ret; | |
395 | ||
396 | rx_size -= len; | |
397 | buf += len; | |
398 | } while (rx_size != 0); | |
399 | ||
400 | return 0; | |
401 | } | |
402 | ||
403 | static int | |
404 | gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, | |
405 | unsigned short addr, u8 *buf, unsigned int len) | |
406 | { | |
9535c475 | 407 | unsigned int chunk_size = len; |
924a93ed DK |
408 | u32 val, loop; |
409 | ||
410 | val = loop = 0; | |
26883c31 DK |
411 | while (len && loop < 4) { |
412 | val |= *buf++ << (8 * loop++); | |
413 | len -= 1; | |
414 | } | |
924a93ed | 415 | |
4e6c2d58 CW |
416 | I915_WRITE_FW(GMBUS3, val); |
417 | I915_WRITE_FW(GMBUS1, | |
418 | GMBUS_CYCLE_WAIT | | |
419 | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | | |
420 | (addr << GMBUS_SLAVE_ADDR_SHIFT) | | |
421 | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); | |
924a93ed | 422 | while (len) { |
90e6b26d | 423 | int ret; |
90e6b26d | 424 | |
924a93ed DK |
425 | val = loop = 0; |
426 | do { | |
427 | val |= *buf++ << (8 * loop); | |
428 | } while (--len && ++loop < 4); | |
429 | ||
4e6c2d58 | 430 | I915_WRITE_FW(GMBUS3, val); |
7a39a9d4 | 431 | |
4e6c2d58 | 432 | ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); |
90e6b26d | 433 | if (ret) |
61168c53 | 434 | return ret; |
924a93ed | 435 | } |
9535c475 DT |
436 | |
437 | return 0; | |
438 | } | |
439 | ||
440 | static int | |
441 | gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) | |
442 | { | |
443 | u8 *buf = msg->buf; | |
444 | unsigned int tx_size = msg->len; | |
445 | unsigned int len; | |
446 | int ret; | |
447 | ||
448 | do { | |
449 | len = min(tx_size, GMBUS_BYTE_COUNT_MAX); | |
450 | ||
451 | ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len); | |
452 | if (ret) | |
453 | return ret; | |
454 | ||
455 | buf += len; | |
456 | tx_size -= len; | |
457 | } while (tx_size != 0); | |
458 | ||
924a93ed DK |
459 | return 0; |
460 | } | |
461 | ||
56f9eac0 DK |
462 | /* |
463 | * The gmbus controller can combine a 1 or 2 byte write with a read that | |
464 | * immediately follows it by using an "INDEX" cycle. | |
465 | */ | |
466 | static bool | |
467 | gmbus_is_index_read(struct i2c_msg *msgs, int i, int num) | |
468 | { | |
469 | return (i + 1 < num && | |
c4deb62d | 470 | msgs[i].addr == msgs[i + 1].addr && |
bb9e0d4b VS |
471 | !(msgs[i].flags & I2C_M_RD) && |
472 | (msgs[i].len == 1 || msgs[i].len == 2) && | |
56f9eac0 DK |
473 | (msgs[i + 1].flags & I2C_M_RD)); |
474 | } | |
475 | ||
476 | static int | |
477 | gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs) | |
478 | { | |
56f9eac0 DK |
479 | u32 gmbus1_index = 0; |
480 | u32 gmbus5 = 0; | |
481 | int ret; | |
482 | ||
483 | if (msgs[0].len == 2) | |
484 | gmbus5 = GMBUS_2BYTE_INDEX_EN | | |
485 | msgs[0].buf[1] | (msgs[0].buf[0] << 8); | |
486 | if (msgs[0].len == 1) | |
487 | gmbus1_index = GMBUS_CYCLE_INDEX | | |
488 | (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); | |
489 | ||
490 | /* GMBUS5 holds 16-bit index */ | |
491 | if (gmbus5) | |
4e6c2d58 | 492 | I915_WRITE_FW(GMBUS5, gmbus5); |
56f9eac0 DK |
493 | |
494 | ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index); | |
495 | ||
496 | /* Clear GMBUS5 after each index transfer */ | |
497 | if (gmbus5) | |
4e6c2d58 | 498 | I915_WRITE_FW(GMBUS5, 0); |
56f9eac0 DK |
499 | |
500 | return ret; | |
501 | } | |
502 | ||
f899fc64 | 503 | static int |
bffce907 | 504 | do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) |
f899fc64 CW |
505 | { |
506 | struct intel_gmbus *bus = container_of(adapter, | |
507 | struct intel_gmbus, | |
508 | adapter); | |
c2b9152f | 509 | struct drm_i915_private *dev_priv = bus->dev_priv; |
699fc401 | 510 | int i = 0, inc, try = 0; |
72d66afd | 511 | int ret = 0; |
f899fc64 | 512 | |
6481d5ed VS |
513 | /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */ |
514 | if (IS_GEN9_LP(dev_priv)) | |
515 | bxt_gmbus_clock_gating(dev_priv, false); | |
516 | else if (HAS_PCH_SPT(dev_priv) || | |
517 | HAS_PCH_KBP(dev_priv) || HAS_PCH_CNP(dev_priv)) | |
518 | pch_gmbus_clock_gating(dev_priv, false); | |
519 | ||
3f5f1554 | 520 | retry: |
4e6c2d58 | 521 | I915_WRITE_FW(GMBUS0, bus->reg0); |
f899fc64 | 522 | |
3f5f1554 JN |
523 | for (; i < num; i += inc) { |
524 | inc = 1; | |
56f9eac0 DK |
525 | if (gmbus_is_index_read(msgs, i, num)) { |
526 | ret = gmbus_xfer_index_read(dev_priv, &msgs[i]); | |
3f5f1554 | 527 | inc = 2; /* an index read is two msgs */ |
56f9eac0 DK |
528 | } else if (msgs[i].flags & I2C_M_RD) { |
529 | ret = gmbus_xfer_read(dev_priv, &msgs[i], 0); | |
530 | } else { | |
72d66afd | 531 | ret = gmbus_xfer_write(dev_priv, &msgs[i]); |
56f9eac0 | 532 | } |
924a93ed | 533 | |
0aeb9048 | 534 | if (!ret) |
4e6c2d58 CW |
535 | ret = gmbus_wait(dev_priv, |
536 | GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN); | |
924a93ed DK |
537 | if (ret == -ETIMEDOUT) |
538 | goto timeout; | |
0aeb9048 | 539 | else if (ret) |
924a93ed | 540 | goto clear_err; |
f899fc64 CW |
541 | } |
542 | ||
72d66afd DK |
543 | /* Generate a STOP condition on the bus. Note that gmbus can't generata |
544 | * a STOP on the very first cycle. To simplify the code we | |
545 | * unconditionally generate the STOP condition with an additional gmbus | |
546 | * cycle. */ | |
4e6c2d58 | 547 | I915_WRITE_FW(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); |
72d66afd | 548 | |
e646d577 DK |
549 | /* Mark the GMBUS interface as disabled after waiting for idle. |
550 | * We will re-enable it at the start of the next xfer, | |
551 | * till then let it sleep. | |
552 | */ | |
2c438c02 | 553 | if (gmbus_wait_idle(dev_priv)) { |
56fa6d6f | 554 | DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n", |
e646d577 | 555 | adapter->name); |
72d66afd DK |
556 | ret = -ETIMEDOUT; |
557 | } | |
4e6c2d58 | 558 | I915_WRITE_FW(GMBUS0, 0); |
72d66afd | 559 | ret = ret ?: i; |
e646d577 | 560 | goto out; |
7f58aabc CW |
561 | |
562 | clear_err: | |
e646d577 DK |
563 | /* |
564 | * Wait for bus to IDLE before clearing NAK. | |
565 | * If we clear the NAK while bus is still active, then it will stay | |
566 | * active and the next transaction may fail. | |
65e81866 DV |
567 | * |
568 | * If no ACK is received during the address phase of a transaction, the | |
569 | * adapter must report -ENXIO. It is not clear what to return if no ACK | |
570 | * is received at other times. But we have to be careful to not return | |
571 | * spurious -ENXIO because that will prevent i2c and drm edid functions | |
572 | * from retrying. So return -ENXIO only when gmbus properly quiescents - | |
573 | * timing out seems to happen when there _is_ a ddc chip present, but | |
574 | * it's slow responding and only answers on the 2nd retry. | |
e646d577 | 575 | */ |
65e81866 | 576 | ret = -ENXIO; |
2c438c02 | 577 | if (gmbus_wait_idle(dev_priv)) { |
56fa6d6f DK |
578 | DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n", |
579 | adapter->name); | |
65e81866 DV |
580 | ret = -ETIMEDOUT; |
581 | } | |
e646d577 | 582 | |
7f58aabc CW |
583 | /* Toggle the Software Clear Interrupt bit. This has the effect |
584 | * of resetting the GMBUS controller and so clearing the | |
585 | * BUS_ERROR raised by the slave's NAK. | |
586 | */ | |
4e6c2d58 CW |
587 | I915_WRITE_FW(GMBUS1, GMBUS_SW_CLR_INT); |
588 | I915_WRITE_FW(GMBUS1, 0); | |
589 | I915_WRITE_FW(GMBUS0, 0); | |
7f58aabc | 590 | |
56fa6d6f | 591 | DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n", |
e646d577 DK |
592 | adapter->name, msgs[i].addr, |
593 | (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); | |
594 | ||
3f5f1554 JN |
595 | /* |
596 | * Passive adapters sometimes NAK the first probe. Retry the first | |
597 | * message once on -ENXIO for GMBUS transfers; the bit banging algorithm | |
598 | * has retries internally. See also the retry loop in | |
599 | * drm_do_probe_ddc_edid, which bails out on the first -ENXIO. | |
600 | */ | |
601 | if (ret == -ENXIO && i == 0 && try++ == 0) { | |
602 | DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n", | |
603 | adapter->name); | |
604 | goto retry; | |
605 | } | |
606 | ||
8a8ed1f5 | 607 | goto out; |
f899fc64 CW |
608 | |
609 | timeout: | |
70677801 VS |
610 | DRM_DEBUG_KMS("GMBUS [%s] timed out, falling back to bit banging on pin %d\n", |
611 | bus->adapter.name, bus->reg0 & 0xff); | |
4e6c2d58 | 612 | I915_WRITE_FW(GMBUS0, 0); |
7f58aabc | 613 | |
bffce907 JN |
614 | /* |
615 | * Hardware may not support GMBUS over these pins? Try GPIO bitbanging | |
616 | * instead. Use EAGAIN to have i2c core retry. | |
617 | */ | |
bffce907 | 618 | ret = -EAGAIN; |
489fbc10 | 619 | |
8a8ed1f5 | 620 | out: |
6481d5ed VS |
621 | /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */ |
622 | if (IS_GEN9_LP(dev_priv)) | |
623 | bxt_gmbus_clock_gating(dev_priv, true); | |
624 | else if (HAS_PCH_SPT(dev_priv) || | |
625 | HAS_PCH_KBP(dev_priv) || HAS_PCH_CNP(dev_priv)) | |
626 | pch_gmbus_clock_gating(dev_priv, true); | |
627 | ||
bffce907 JN |
628 | return ret; |
629 | } | |
630 | ||
631 | static int | |
632 | gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) | |
633 | { | |
634 | struct intel_gmbus *bus = container_of(adapter, struct intel_gmbus, | |
635 | adapter); | |
636 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
637 | int ret; | |
638 | ||
639 | intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); | |
bffce907 | 640 | |
3e4d44e0 | 641 | if (bus->force_bit) { |
bffce907 | 642 | ret = i2c_bit_algo.master_xfer(adapter, msgs, num); |
3e4d44e0 VS |
643 | if (ret < 0) |
644 | bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY; | |
645 | } else { | |
bffce907 | 646 | ret = do_gmbus_xfer(adapter, msgs, num); |
3e4d44e0 VS |
647 | if (ret == -EAGAIN) |
648 | bus->force_bit |= GMBUS_FORCE_BIT_RETRY; | |
649 | } | |
f0ab43e6 VS |
650 | |
651 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); | |
652 | ||
8a8ed1f5 | 653 | return ret; |
f899fc64 CW |
654 | } |
655 | ||
656 | static u32 gmbus_func(struct i2c_adapter *adapter) | |
657 | { | |
f6f808c8 DV |
658 | return i2c_bit_algo.functionality(adapter) & |
659 | (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | | |
f899fc64 CW |
660 | /* I2C_FUNC_10BIT_ADDR | */ |
661 | I2C_FUNC_SMBUS_READ_BLOCK_DATA | | |
662 | I2C_FUNC_SMBUS_BLOCK_PROC_CALL); | |
663 | } | |
664 | ||
665 | static const struct i2c_algorithm gmbus_algorithm = { | |
666 | .master_xfer = gmbus_xfer, | |
667 | .functionality = gmbus_func | |
668 | }; | |
669 | ||
a8506684 DV |
670 | static void gmbus_lock_bus(struct i2c_adapter *adapter, |
671 | unsigned int flags) | |
672 | { | |
673 | struct intel_gmbus *bus = to_intel_gmbus(adapter); | |
674 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
675 | ||
676 | mutex_lock(&dev_priv->gmbus_mutex); | |
677 | } | |
678 | ||
679 | static int gmbus_trylock_bus(struct i2c_adapter *adapter, | |
680 | unsigned int flags) | |
681 | { | |
682 | struct intel_gmbus *bus = to_intel_gmbus(adapter); | |
683 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
684 | ||
685 | return mutex_trylock(&dev_priv->gmbus_mutex); | |
686 | } | |
687 | ||
688 | static void gmbus_unlock_bus(struct i2c_adapter *adapter, | |
689 | unsigned int flags) | |
690 | { | |
691 | struct intel_gmbus *bus = to_intel_gmbus(adapter); | |
692 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
693 | ||
694 | mutex_unlock(&dev_priv->gmbus_mutex); | |
695 | } | |
696 | ||
0db1aa42 | 697 | static const struct i2c_lock_operations gmbus_lock_ops = { |
a8506684 DV |
698 | .lock_bus = gmbus_lock_bus, |
699 | .trylock_bus = gmbus_trylock_bus, | |
700 | .unlock_bus = gmbus_unlock_bus, | |
701 | }; | |
702 | ||
79e53945 | 703 | /** |
f899fc64 | 704 | * intel_gmbus_setup - instantiate all Intel i2c GMBuses |
40196446 | 705 | * @dev_priv: i915 device private |
79e53945 | 706 | */ |
40196446 | 707 | int intel_setup_gmbus(struct drm_i915_private *dev_priv) |
f899fc64 | 708 | { |
52a05c30 | 709 | struct pci_dev *pdev = dev_priv->drm.pdev; |
5ea6e5e3 JN |
710 | struct intel_gmbus *bus; |
711 | unsigned int pin; | |
712 | int ret; | |
f899fc64 | 713 | |
6e266956 | 714 | if (HAS_PCH_NOP(dev_priv)) |
ab5c608b | 715 | return 0; |
b2e8c6cd | 716 | |
920a14b2 | 717 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
d8112150 | 718 | dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; |
f0f59a00 VS |
719 | else if (!HAS_GMCH_DISPLAY(dev_priv)) |
720 | dev_priv->gpio_mmio_base = | |
721 | i915_mmio_reg_offset(PCH_GPIOA) - | |
722 | i915_mmio_reg_offset(GPIOA); | |
110447fc | 723 | |
8a8ed1f5 | 724 | mutex_init(&dev_priv->gmbus_mutex); |
28c70f16 | 725 | init_waitqueue_head(&dev_priv->gmbus_wait_queue); |
8a8ed1f5 | 726 | |
5ea6e5e3 | 727 | for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { |
88ac7939 | 728 | if (!intel_gmbus_is_valid_pin(dev_priv, pin)) |
5ea6e5e3 JN |
729 | continue; |
730 | ||
731 | bus = &dev_priv->gmbus[pin]; | |
f899fc64 CW |
732 | |
733 | bus->adapter.owner = THIS_MODULE; | |
734 | bus->adapter.class = I2C_CLASS_DDC; | |
735 | snprintf(bus->adapter.name, | |
69669455 JD |
736 | sizeof(bus->adapter.name), |
737 | "i915 gmbus %s", | |
4c272834 | 738 | get_gmbus_pin(dev_priv, pin)->name); |
f899fc64 | 739 | |
52a05c30 | 740 | bus->adapter.dev.parent = &pdev->dev; |
c2b9152f | 741 | bus->dev_priv = dev_priv; |
f899fc64 CW |
742 | |
743 | bus->adapter.algo = &gmbus_algorithm; | |
a8506684 | 744 | bus->adapter.lock_ops = &gmbus_lock_ops; |
f899fc64 | 745 | |
8b1f165a VS |
746 | /* |
747 | * We wish to retry with bit banging | |
748 | * after a timed out GMBUS attempt. | |
749 | */ | |
750 | bus->adapter.retries = 1; | |
751 | ||
e957d772 | 752 | /* By default use a conservative clock rate */ |
5ea6e5e3 | 753 | bus->reg0 = pin | GMBUS_RATE_100KHZ; |
cb8ea752 | 754 | |
83ee9e64 | 755 | /* gmbus seems to be broken on i830 */ |
50a0bc90 | 756 | if (IS_I830(dev_priv)) |
f2ce9faf | 757 | bus->force_bit = 1; |
83ee9e64 | 758 | |
5ea6e5e3 | 759 | intel_gpio_setup(bus, pin); |
cee25168 JN |
760 | |
761 | ret = i2c_add_adapter(&bus->adapter); | |
762 | if (ret) | |
763 | goto err; | |
f899fc64 CW |
764 | } |
765 | ||
af6dc742 | 766 | intel_i2c_reset(dev_priv); |
f899fc64 CW |
767 | |
768 | return 0; | |
769 | ||
770 | err: | |
2417c8c0 | 771 | while (pin--) { |
88ac7939 | 772 | if (!intel_gmbus_is_valid_pin(dev_priv, pin)) |
5ea6e5e3 JN |
773 | continue; |
774 | ||
775 | bus = &dev_priv->gmbus[pin]; | |
f899fc64 CW |
776 | i2c_del_adapter(&bus->adapter); |
777 | } | |
f899fc64 CW |
778 | return ret; |
779 | } | |
780 | ||
3bd7d909 | 781 | struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, |
0184df46 | 782 | unsigned int pin) |
3bd7d909 | 783 | { |
88ac7939 | 784 | if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin))) |
5ea6e5e3 JN |
785 | return NULL; |
786 | ||
787 | return &dev_priv->gmbus[pin].adapter; | |
3bd7d909 DK |
788 | } |
789 | ||
e957d772 CW |
790 | void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed) |
791 | { | |
792 | struct intel_gmbus *bus = to_intel_gmbus(adapter); | |
793 | ||
d5090b96 | 794 | bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed; |
e957d772 CW |
795 | } |
796 | ||
797 | void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) | |
798 | { | |
799 | struct intel_gmbus *bus = to_intel_gmbus(adapter); | |
ade754ec VS |
800 | struct drm_i915_private *dev_priv = bus->dev_priv; |
801 | ||
802 | mutex_lock(&dev_priv->gmbus_mutex); | |
e957d772 | 803 | |
f2ce9faf CW |
804 | bus->force_bit += force_bit ? 1 : -1; |
805 | DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n", | |
806 | force_bit ? "en" : "dis", adapter->name, | |
807 | bus->force_bit); | |
ade754ec VS |
808 | |
809 | mutex_unlock(&dev_priv->gmbus_mutex); | |
e957d772 CW |
810 | } |
811 | ||
40196446 | 812 | void intel_teardown_gmbus(struct drm_i915_private *dev_priv) |
79e53945 | 813 | { |
5ea6e5e3 JN |
814 | struct intel_gmbus *bus; |
815 | unsigned int pin; | |
816 | ||
817 | for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { | |
88ac7939 | 818 | if (!intel_gmbus_is_valid_pin(dev_priv, pin)) |
5ea6e5e3 | 819 | continue; |
f9c10a9b | 820 | |
5ea6e5e3 | 821 | bus = &dev_priv->gmbus[pin]; |
f899fc64 CW |
822 | i2c_del_adapter(&bus->adapter); |
823 | } | |
79e53945 | 824 | } |