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79e53945 JB |
1 | /* |
2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
f899fc64 | 3 | * Copyright © 2006-2008,2010 Intel Corporation |
79e53945 JB |
4 | * Jesse Barnes <jesse.barnes@intel.com> |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
23 | * DEALINGS IN THE SOFTWARE. | |
24 | * | |
25 | * Authors: | |
26 | * Eric Anholt <eric@anholt.net> | |
f899fc64 | 27 | * Chris Wilson <chris@chris-wilson.co.uk> |
79e53945 JB |
28 | */ |
29 | #include <linux/i2c.h> | |
79e53945 | 30 | #include <linux/i2c-algo-bit.h> |
2d1a8a48 | 31 | #include <linux/export.h> |
760285e7 | 32 | #include <drm/drmP.h> |
79e53945 | 33 | #include "intel_drv.h" |
760285e7 | 34 | #include <drm/i915_drm.h> |
79e53945 JB |
35 | #include "i915_drv.h" |
36 | ||
5ea6e5e3 | 37 | struct gmbus_pin { |
2ed06c93 | 38 | const char *name; |
f0f59a00 | 39 | i915_reg_t reg; |
2ed06c93 DK |
40 | }; |
41 | ||
5ea6e5e3 JN |
42 | /* Map gmbus pin pairs to names and registers. */ |
43 | static const struct gmbus_pin gmbus_pins[] = { | |
44 | [GMBUS_PIN_SSC] = { "ssc", GPIOB }, | |
45 | [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, | |
46 | [GMBUS_PIN_PANEL] = { "panel", GPIOC }, | |
47 | [GMBUS_PIN_DPC] = { "dpc", GPIOD }, | |
48 | [GMBUS_PIN_DPB] = { "dpb", GPIOE }, | |
49 | [GMBUS_PIN_DPD] = { "dpd", GPIOF }, | |
2ed06c93 DK |
50 | }; |
51 | ||
c1bad5b6 JN |
52 | static const struct gmbus_pin gmbus_pins_bdw[] = { |
53 | [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, | |
54 | [GMBUS_PIN_DPC] = { "dpc", GPIOD }, | |
55 | [GMBUS_PIN_DPB] = { "dpb", GPIOE }, | |
56 | [GMBUS_PIN_DPD] = { "dpd", GPIOF }, | |
57 | }; | |
58 | ||
6364e67e JN |
59 | static const struct gmbus_pin gmbus_pins_skl[] = { |
60 | [GMBUS_PIN_DPC] = { "dpc", GPIOD }, | |
61 | [GMBUS_PIN_DPB] = { "dpb", GPIOE }, | |
62 | [GMBUS_PIN_DPD] = { "dpd", GPIOF }, | |
63 | }; | |
64 | ||
4c272834 | 65 | static const struct gmbus_pin gmbus_pins_bxt[] = { |
b2e8c6cd VS |
66 | [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, |
67 | [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, | |
68 | [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, | |
4c272834 JN |
69 | }; |
70 | ||
3d02352c RV |
71 | static const struct gmbus_pin gmbus_pins_cnp[] = { |
72 | [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, | |
73 | [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, | |
74 | [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, | |
75 | [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, | |
76 | }; | |
77 | ||
4c272834 JN |
78 | /* pin is expected to be valid */ |
79 | static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv, | |
80 | unsigned int pin) | |
81 | { | |
3d02352c RV |
82 | if (HAS_PCH_CNP(dev_priv)) |
83 | return &gmbus_pins_cnp[pin]; | |
84 | else if (IS_GEN9_LP(dev_priv)) | |
4c272834 | 85 | return &gmbus_pins_bxt[pin]; |
b976dc53 | 86 | else if (IS_GEN9_BC(dev_priv)) |
6364e67e | 87 | return &gmbus_pins_skl[pin]; |
c1bad5b6 JN |
88 | else if (IS_BROADWELL(dev_priv)) |
89 | return &gmbus_pins_bdw[pin]; | |
4c272834 JN |
90 | else |
91 | return &gmbus_pins[pin]; | |
92 | } | |
93 | ||
88ac7939 JN |
94 | bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, |
95 | unsigned int pin) | |
96 | { | |
4c272834 JN |
97 | unsigned int size; |
98 | ||
3d02352c RV |
99 | if (HAS_PCH_CNP(dev_priv)) |
100 | size = ARRAY_SIZE(gmbus_pins_cnp); | |
101 | else if (IS_GEN9_LP(dev_priv)) | |
4c272834 | 102 | size = ARRAY_SIZE(gmbus_pins_bxt); |
b976dc53 | 103 | else if (IS_GEN9_BC(dev_priv)) |
6364e67e | 104 | size = ARRAY_SIZE(gmbus_pins_skl); |
c1bad5b6 JN |
105 | else if (IS_BROADWELL(dev_priv)) |
106 | size = ARRAY_SIZE(gmbus_pins_bdw); | |
4c272834 JN |
107 | else |
108 | size = ARRAY_SIZE(gmbus_pins); | |
109 | ||
f0f59a00 VS |
110 | return pin < size && |
111 | i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg); | |
88ac7939 JN |
112 | } |
113 | ||
f899fc64 CW |
114 | /* Intel GPIO access functions */ |
115 | ||
1849ecb2 | 116 | #define I2C_RISEFALL_TIME 10 |
f899fc64 | 117 | |
e957d772 CW |
118 | static inline struct intel_gmbus * |
119 | to_intel_gmbus(struct i2c_adapter *i2c) | |
120 | { | |
121 | return container_of(i2c, struct intel_gmbus, adapter); | |
122 | } | |
123 | ||
f899fc64 | 124 | void |
af6dc742 | 125 | intel_i2c_reset(struct drm_i915_private *dev_priv) |
0ba0e9e1 | 126 | { |
699fc401 VS |
127 | I915_WRITE(GMBUS0, 0); |
128 | I915_WRITE(GMBUS4, 0); | |
f899fc64 CW |
129 | } |
130 | ||
131 | static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable) | |
132 | { | |
b222f267 | 133 | u32 val; |
0ba0e9e1 SL |
134 | |
135 | /* When using bit bashing for I2C, this bit needs to be set to 1 */ | |
2d1fe073 | 136 | if (!IS_PINEVIEW(dev_priv)) |
0ba0e9e1 | 137 | return; |
b222f267 CW |
138 | |
139 | val = I915_READ(DSPCLK_GATE_D); | |
0ba0e9e1 | 140 | if (enable) |
b222f267 | 141 | val |= DPCUNIT_CLOCK_GATE_DISABLE; |
0ba0e9e1 | 142 | else |
b222f267 CW |
143 | val &= ~DPCUNIT_CLOCK_GATE_DISABLE; |
144 | I915_WRITE(DSPCLK_GATE_D, val); | |
0ba0e9e1 SL |
145 | } |
146 | ||
36c785f0 | 147 | static u32 get_reserved(struct intel_gmbus *bus) |
e957d772 | 148 | { |
36c785f0 | 149 | struct drm_i915_private *dev_priv = bus->dev_priv; |
e957d772 CW |
150 | u32 reserved = 0; |
151 | ||
152 | /* On most chips, these bits must be preserved in software. */ | |
2a307c2e | 153 | if (!IS_I830(dev_priv) && !IS_I845G(dev_priv)) |
36c785f0 | 154 | reserved = I915_READ_NOTRACE(bus->gpio_reg) & |
db5e4172 YL |
155 | (GPIO_DATA_PULLUP_DISABLE | |
156 | GPIO_CLOCK_PULLUP_DISABLE); | |
e957d772 CW |
157 | |
158 | return reserved; | |
159 | } | |
160 | ||
79e53945 JB |
161 | static int get_clock(void *data) |
162 | { | |
36c785f0 DV |
163 | struct intel_gmbus *bus = data; |
164 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
165 | u32 reserved = get_reserved(bus); | |
166 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK); | |
167 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved); | |
168 | return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0; | |
79e53945 JB |
169 | } |
170 | ||
171 | static int get_data(void *data) | |
172 | { | |
36c785f0 DV |
173 | struct intel_gmbus *bus = data; |
174 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
175 | u32 reserved = get_reserved(bus); | |
176 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK); | |
177 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved); | |
178 | return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0; | |
79e53945 JB |
179 | } |
180 | ||
181 | static void set_clock(void *data, int state_high) | |
182 | { | |
36c785f0 DV |
183 | struct intel_gmbus *bus = data; |
184 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
185 | u32 reserved = get_reserved(bus); | |
e957d772 | 186 | u32 clock_bits; |
79e53945 JB |
187 | |
188 | if (state_high) | |
189 | clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; | |
190 | else | |
191 | clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | | |
192 | GPIO_CLOCK_VAL_MASK; | |
f899fc64 | 193 | |
36c785f0 DV |
194 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits); |
195 | POSTING_READ(bus->gpio_reg); | |
79e53945 JB |
196 | } |
197 | ||
198 | static void set_data(void *data, int state_high) | |
199 | { | |
36c785f0 DV |
200 | struct intel_gmbus *bus = data; |
201 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
202 | u32 reserved = get_reserved(bus); | |
e957d772 | 203 | u32 data_bits; |
79e53945 JB |
204 | |
205 | if (state_high) | |
206 | data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; | |
207 | else | |
208 | data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | | |
209 | GPIO_DATA_VAL_MASK; | |
210 | ||
36c785f0 DV |
211 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits); |
212 | POSTING_READ(bus->gpio_reg); | |
79e53945 JB |
213 | } |
214 | ||
489fbc10 DK |
215 | static int |
216 | intel_gpio_pre_xfer(struct i2c_adapter *adapter) | |
217 | { | |
218 | struct intel_gmbus *bus = container_of(adapter, | |
219 | struct intel_gmbus, | |
220 | adapter); | |
221 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
222 | ||
af6dc742 | 223 | intel_i2c_reset(dev_priv); |
489fbc10 DK |
224 | intel_i2c_quirk_set(dev_priv, true); |
225 | set_data(bus, 1); | |
226 | set_clock(bus, 1); | |
227 | udelay(I2C_RISEFALL_TIME); | |
228 | return 0; | |
229 | } | |
230 | ||
231 | static void | |
232 | intel_gpio_post_xfer(struct i2c_adapter *adapter) | |
233 | { | |
234 | struct intel_gmbus *bus = container_of(adapter, | |
235 | struct intel_gmbus, | |
236 | adapter); | |
237 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
238 | ||
239 | set_data(bus, 1); | |
240 | set_clock(bus, 1); | |
241 | intel_i2c_quirk_set(dev_priv, false); | |
242 | } | |
243 | ||
2ed06c93 | 244 | static void |
5ea6e5e3 | 245 | intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin) |
f0217c42 | 246 | { |
36c785f0 | 247 | struct drm_i915_private *dev_priv = bus->dev_priv; |
36c785f0 | 248 | struct i2c_algo_bit_data *algo; |
f0217c42 | 249 | |
c167a6fc | 250 | algo = &bus->bit_algo; |
36c785f0 | 251 | |
f0f59a00 VS |
252 | bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base + |
253 | i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg)); | |
c167a6fc | 254 | bus->adapter.algo_data = algo; |
36c785f0 DV |
255 | algo->setsda = set_data; |
256 | algo->setscl = set_clock; | |
257 | algo->getsda = get_data; | |
258 | algo->getscl = get_clock; | |
489fbc10 DK |
259 | algo->pre_xfer = intel_gpio_pre_xfer; |
260 | algo->post_xfer = intel_gpio_post_xfer; | |
36c785f0 DV |
261 | algo->udelay = I2C_RISEFALL_TIME; |
262 | algo->timeout = usecs_to_jiffies(2200); | |
263 | algo->data = bus; | |
79e53945 JB |
264 | } |
265 | ||
4e6c2d58 | 266 | static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en) |
61168c53 | 267 | { |
28c70f16 | 268 | DEFINE_WAIT(wait); |
4e6c2d58 CW |
269 | u32 gmbus2; |
270 | int ret; | |
c12aba5a | 271 | |
28c70f16 DV |
272 | /* Important: The hw handles only the first bit, so set only one! Since |
273 | * we also need to check for NAKs besides the hw ready/idle signal, we | |
4e6c2d58 CW |
274 | * need to wake up periodically and check that ourselves. |
275 | */ | |
276 | if (!HAS_GMBUS_IRQ(dev_priv)) | |
277 | irq_en = 0; | |
28c70f16 | 278 | |
4e6c2d58 CW |
279 | add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); |
280 | I915_WRITE_FW(GMBUS4, irq_en); | |
61168c53 | 281 | |
4e6c2d58 CW |
282 | status |= GMBUS_SATOER; |
283 | ret = wait_for_us((gmbus2 = I915_READ_FW(GMBUS2)) & status, 2); | |
284 | if (ret) | |
285 | ret = wait_for((gmbus2 = I915_READ_FW(GMBUS2)) & status, 50); | |
28c70f16 | 286 | |
4e6c2d58 CW |
287 | I915_WRITE_FW(GMBUS4, 0); |
288 | remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); | |
61168c53 DV |
289 | |
290 | if (gmbus2 & GMBUS_SATOER) | |
291 | return -ENXIO; | |
4e6c2d58 CW |
292 | |
293 | return ret; | |
61168c53 DV |
294 | } |
295 | ||
2c438c02 DV |
296 | static int |
297 | gmbus_wait_idle(struct drm_i915_private *dev_priv) | |
298 | { | |
4e6c2d58 CW |
299 | DEFINE_WAIT(wait); |
300 | u32 irq_enable; | |
2c438c02 | 301 | int ret; |
2c438c02 | 302 | |
2c438c02 | 303 | /* Important: The hw handles only the first bit, so set only one! */ |
4e6c2d58 CW |
304 | irq_enable = 0; |
305 | if (HAS_GMBUS_IRQ(dev_priv)) | |
306 | irq_enable = GMBUS_IDLE_EN; | |
2c438c02 | 307 | |
4e6c2d58 CW |
308 | add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); |
309 | I915_WRITE_FW(GMBUS4, irq_enable); | |
2c438c02 | 310 | |
4e6c2d58 CW |
311 | ret = intel_wait_for_register_fw(dev_priv, |
312 | GMBUS2, GMBUS_ACTIVE, 0, | |
313 | 10); | |
2c438c02 | 314 | |
4e6c2d58 CW |
315 | I915_WRITE_FW(GMBUS4, 0); |
316 | remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); | |
317 | ||
318 | return ret; | |
2c438c02 DV |
319 | } |
320 | ||
924a93ed | 321 | static int |
9535c475 DT |
322 | gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, |
323 | unsigned short addr, u8 *buf, unsigned int len, | |
324 | u32 gmbus1_index) | |
924a93ed | 325 | { |
4e6c2d58 CW |
326 | I915_WRITE_FW(GMBUS1, |
327 | gmbus1_index | | |
328 | GMBUS_CYCLE_WAIT | | |
329 | (len << GMBUS_BYTE_COUNT_SHIFT) | | |
330 | (addr << GMBUS_SLAVE_ADDR_SHIFT) | | |
331 | GMBUS_SLAVE_READ | GMBUS_SW_RDY); | |
79985eee | 332 | while (len) { |
90e6b26d | 333 | int ret; |
924a93ed DK |
334 | u32 val, loop = 0; |
335 | ||
4e6c2d58 | 336 | ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); |
90e6b26d | 337 | if (ret) |
61168c53 | 338 | return ret; |
924a93ed | 339 | |
4e6c2d58 | 340 | val = I915_READ_FW(GMBUS3); |
924a93ed DK |
341 | do { |
342 | *buf++ = val & 0xff; | |
343 | val >>= 8; | |
344 | } while (--len && ++loop < 4); | |
79985eee | 345 | } |
924a93ed DK |
346 | |
347 | return 0; | |
348 | } | |
349 | ||
350 | static int | |
9535c475 DT |
351 | gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, |
352 | u32 gmbus1_index) | |
924a93ed | 353 | { |
924a93ed | 354 | u8 *buf = msg->buf; |
9535c475 DT |
355 | unsigned int rx_size = msg->len; |
356 | unsigned int len; | |
357 | int ret; | |
358 | ||
359 | do { | |
360 | len = min(rx_size, GMBUS_BYTE_COUNT_MAX); | |
361 | ||
362 | ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, | |
363 | buf, len, gmbus1_index); | |
364 | if (ret) | |
365 | return ret; | |
366 | ||
367 | rx_size -= len; | |
368 | buf += len; | |
369 | } while (rx_size != 0); | |
370 | ||
371 | return 0; | |
372 | } | |
373 | ||
374 | static int | |
375 | gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, | |
376 | unsigned short addr, u8 *buf, unsigned int len) | |
377 | { | |
9535c475 | 378 | unsigned int chunk_size = len; |
924a93ed DK |
379 | u32 val, loop; |
380 | ||
381 | val = loop = 0; | |
26883c31 DK |
382 | while (len && loop < 4) { |
383 | val |= *buf++ << (8 * loop++); | |
384 | len -= 1; | |
385 | } | |
924a93ed | 386 | |
4e6c2d58 CW |
387 | I915_WRITE_FW(GMBUS3, val); |
388 | I915_WRITE_FW(GMBUS1, | |
389 | GMBUS_CYCLE_WAIT | | |
390 | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | | |
391 | (addr << GMBUS_SLAVE_ADDR_SHIFT) | | |
392 | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); | |
924a93ed | 393 | while (len) { |
90e6b26d | 394 | int ret; |
90e6b26d | 395 | |
924a93ed DK |
396 | val = loop = 0; |
397 | do { | |
398 | val |= *buf++ << (8 * loop); | |
399 | } while (--len && ++loop < 4); | |
400 | ||
4e6c2d58 | 401 | I915_WRITE_FW(GMBUS3, val); |
7a39a9d4 | 402 | |
4e6c2d58 | 403 | ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); |
90e6b26d | 404 | if (ret) |
61168c53 | 405 | return ret; |
924a93ed | 406 | } |
9535c475 DT |
407 | |
408 | return 0; | |
409 | } | |
410 | ||
411 | static int | |
412 | gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) | |
413 | { | |
414 | u8 *buf = msg->buf; | |
415 | unsigned int tx_size = msg->len; | |
416 | unsigned int len; | |
417 | int ret; | |
418 | ||
419 | do { | |
420 | len = min(tx_size, GMBUS_BYTE_COUNT_MAX); | |
421 | ||
422 | ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len); | |
423 | if (ret) | |
424 | return ret; | |
425 | ||
426 | buf += len; | |
427 | tx_size -= len; | |
428 | } while (tx_size != 0); | |
429 | ||
924a93ed DK |
430 | return 0; |
431 | } | |
432 | ||
56f9eac0 DK |
433 | /* |
434 | * The gmbus controller can combine a 1 or 2 byte write with a read that | |
435 | * immediately follows it by using an "INDEX" cycle. | |
436 | */ | |
437 | static bool | |
438 | gmbus_is_index_read(struct i2c_msg *msgs, int i, int num) | |
439 | { | |
440 | return (i + 1 < num && | |
441 | !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 && | |
442 | (msgs[i + 1].flags & I2C_M_RD)); | |
443 | } | |
444 | ||
445 | static int | |
446 | gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs) | |
447 | { | |
56f9eac0 DK |
448 | u32 gmbus1_index = 0; |
449 | u32 gmbus5 = 0; | |
450 | int ret; | |
451 | ||
452 | if (msgs[0].len == 2) | |
453 | gmbus5 = GMBUS_2BYTE_INDEX_EN | | |
454 | msgs[0].buf[1] | (msgs[0].buf[0] << 8); | |
455 | if (msgs[0].len == 1) | |
456 | gmbus1_index = GMBUS_CYCLE_INDEX | | |
457 | (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); | |
458 | ||
459 | /* GMBUS5 holds 16-bit index */ | |
460 | if (gmbus5) | |
4e6c2d58 | 461 | I915_WRITE_FW(GMBUS5, gmbus5); |
56f9eac0 DK |
462 | |
463 | ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index); | |
464 | ||
465 | /* Clear GMBUS5 after each index transfer */ | |
466 | if (gmbus5) | |
4e6c2d58 | 467 | I915_WRITE_FW(GMBUS5, 0); |
56f9eac0 DK |
468 | |
469 | return ret; | |
470 | } | |
471 | ||
f899fc64 | 472 | static int |
bffce907 | 473 | do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) |
f899fc64 CW |
474 | { |
475 | struct intel_gmbus *bus = container_of(adapter, | |
476 | struct intel_gmbus, | |
477 | adapter); | |
c2b9152f | 478 | struct drm_i915_private *dev_priv = bus->dev_priv; |
699fc401 | 479 | int i = 0, inc, try = 0; |
72d66afd | 480 | int ret = 0; |
f899fc64 | 481 | |
3f5f1554 | 482 | retry: |
4e6c2d58 | 483 | I915_WRITE_FW(GMBUS0, bus->reg0); |
f899fc64 | 484 | |
3f5f1554 JN |
485 | for (; i < num; i += inc) { |
486 | inc = 1; | |
56f9eac0 DK |
487 | if (gmbus_is_index_read(msgs, i, num)) { |
488 | ret = gmbus_xfer_index_read(dev_priv, &msgs[i]); | |
3f5f1554 | 489 | inc = 2; /* an index read is two msgs */ |
56f9eac0 DK |
490 | } else if (msgs[i].flags & I2C_M_RD) { |
491 | ret = gmbus_xfer_read(dev_priv, &msgs[i], 0); | |
492 | } else { | |
72d66afd | 493 | ret = gmbus_xfer_write(dev_priv, &msgs[i]); |
56f9eac0 | 494 | } |
924a93ed | 495 | |
0aeb9048 | 496 | if (!ret) |
4e6c2d58 CW |
497 | ret = gmbus_wait(dev_priv, |
498 | GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN); | |
924a93ed DK |
499 | if (ret == -ETIMEDOUT) |
500 | goto timeout; | |
0aeb9048 | 501 | else if (ret) |
924a93ed | 502 | goto clear_err; |
f899fc64 CW |
503 | } |
504 | ||
72d66afd DK |
505 | /* Generate a STOP condition on the bus. Note that gmbus can't generata |
506 | * a STOP on the very first cycle. To simplify the code we | |
507 | * unconditionally generate the STOP condition with an additional gmbus | |
508 | * cycle. */ | |
4e6c2d58 | 509 | I915_WRITE_FW(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); |
72d66afd | 510 | |
e646d577 DK |
511 | /* Mark the GMBUS interface as disabled after waiting for idle. |
512 | * We will re-enable it at the start of the next xfer, | |
513 | * till then let it sleep. | |
514 | */ | |
2c438c02 | 515 | if (gmbus_wait_idle(dev_priv)) { |
56fa6d6f | 516 | DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n", |
e646d577 | 517 | adapter->name); |
72d66afd DK |
518 | ret = -ETIMEDOUT; |
519 | } | |
4e6c2d58 | 520 | I915_WRITE_FW(GMBUS0, 0); |
72d66afd | 521 | ret = ret ?: i; |
e646d577 | 522 | goto out; |
7f58aabc CW |
523 | |
524 | clear_err: | |
e646d577 DK |
525 | /* |
526 | * Wait for bus to IDLE before clearing NAK. | |
527 | * If we clear the NAK while bus is still active, then it will stay | |
528 | * active and the next transaction may fail. | |
65e81866 DV |
529 | * |
530 | * If no ACK is received during the address phase of a transaction, the | |
531 | * adapter must report -ENXIO. It is not clear what to return if no ACK | |
532 | * is received at other times. But we have to be careful to not return | |
533 | * spurious -ENXIO because that will prevent i2c and drm edid functions | |
534 | * from retrying. So return -ENXIO only when gmbus properly quiescents - | |
535 | * timing out seems to happen when there _is_ a ddc chip present, but | |
536 | * it's slow responding and only answers on the 2nd retry. | |
e646d577 | 537 | */ |
65e81866 | 538 | ret = -ENXIO; |
2c438c02 | 539 | if (gmbus_wait_idle(dev_priv)) { |
56fa6d6f DK |
540 | DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n", |
541 | adapter->name); | |
65e81866 DV |
542 | ret = -ETIMEDOUT; |
543 | } | |
e646d577 | 544 | |
7f58aabc CW |
545 | /* Toggle the Software Clear Interrupt bit. This has the effect |
546 | * of resetting the GMBUS controller and so clearing the | |
547 | * BUS_ERROR raised by the slave's NAK. | |
548 | */ | |
4e6c2d58 CW |
549 | I915_WRITE_FW(GMBUS1, GMBUS_SW_CLR_INT); |
550 | I915_WRITE_FW(GMBUS1, 0); | |
551 | I915_WRITE_FW(GMBUS0, 0); | |
7f58aabc | 552 | |
56fa6d6f | 553 | DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n", |
e646d577 DK |
554 | adapter->name, msgs[i].addr, |
555 | (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); | |
556 | ||
3f5f1554 JN |
557 | /* |
558 | * Passive adapters sometimes NAK the first probe. Retry the first | |
559 | * message once on -ENXIO for GMBUS transfers; the bit banging algorithm | |
560 | * has retries internally. See also the retry loop in | |
561 | * drm_do_probe_ddc_edid, which bails out on the first -ENXIO. | |
562 | */ | |
563 | if (ret == -ENXIO && i == 0 && try++ == 0) { | |
564 | DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n", | |
565 | adapter->name); | |
566 | goto retry; | |
567 | } | |
568 | ||
8a8ed1f5 | 569 | goto out; |
f899fc64 CW |
570 | |
571 | timeout: | |
70677801 VS |
572 | DRM_DEBUG_KMS("GMBUS [%s] timed out, falling back to bit banging on pin %d\n", |
573 | bus->adapter.name, bus->reg0 & 0xff); | |
4e6c2d58 | 574 | I915_WRITE_FW(GMBUS0, 0); |
7f58aabc | 575 | |
bffce907 JN |
576 | /* |
577 | * Hardware may not support GMBUS over these pins? Try GPIO bitbanging | |
578 | * instead. Use EAGAIN to have i2c core retry. | |
579 | */ | |
bffce907 | 580 | ret = -EAGAIN; |
489fbc10 | 581 | |
8a8ed1f5 | 582 | out: |
bffce907 JN |
583 | return ret; |
584 | } | |
585 | ||
586 | static int | |
587 | gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) | |
588 | { | |
589 | struct intel_gmbus *bus = container_of(adapter, struct intel_gmbus, | |
590 | adapter); | |
591 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
592 | int ret; | |
593 | ||
594 | intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); | |
595 | mutex_lock(&dev_priv->gmbus_mutex); | |
596 | ||
3e4d44e0 | 597 | if (bus->force_bit) { |
bffce907 | 598 | ret = i2c_bit_algo.master_xfer(adapter, msgs, num); |
3e4d44e0 VS |
599 | if (ret < 0) |
600 | bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY; | |
601 | } else { | |
bffce907 | 602 | ret = do_gmbus_xfer(adapter, msgs, num); |
3e4d44e0 VS |
603 | if (ret == -EAGAIN) |
604 | bus->force_bit |= GMBUS_FORCE_BIT_RETRY; | |
605 | } | |
f0ab43e6 | 606 | |
bffce907 | 607 | mutex_unlock(&dev_priv->gmbus_mutex); |
f0ab43e6 VS |
608 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); |
609 | ||
8a8ed1f5 | 610 | return ret; |
f899fc64 CW |
611 | } |
612 | ||
613 | static u32 gmbus_func(struct i2c_adapter *adapter) | |
614 | { | |
f6f808c8 DV |
615 | return i2c_bit_algo.functionality(adapter) & |
616 | (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | | |
f899fc64 CW |
617 | /* I2C_FUNC_10BIT_ADDR | */ |
618 | I2C_FUNC_SMBUS_READ_BLOCK_DATA | | |
619 | I2C_FUNC_SMBUS_BLOCK_PROC_CALL); | |
620 | } | |
621 | ||
622 | static const struct i2c_algorithm gmbus_algorithm = { | |
623 | .master_xfer = gmbus_xfer, | |
624 | .functionality = gmbus_func | |
625 | }; | |
626 | ||
79e53945 | 627 | /** |
f899fc64 | 628 | * intel_gmbus_setup - instantiate all Intel i2c GMBuses |
40196446 | 629 | * @dev_priv: i915 device private |
79e53945 | 630 | */ |
40196446 | 631 | int intel_setup_gmbus(struct drm_i915_private *dev_priv) |
f899fc64 | 632 | { |
52a05c30 | 633 | struct pci_dev *pdev = dev_priv->drm.pdev; |
5ea6e5e3 JN |
634 | struct intel_gmbus *bus; |
635 | unsigned int pin; | |
636 | int ret; | |
f899fc64 | 637 | |
6e266956 | 638 | if (HAS_PCH_NOP(dev_priv)) |
ab5c608b | 639 | return 0; |
b2e8c6cd | 640 | |
920a14b2 | 641 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
d8112150 | 642 | dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; |
f0f59a00 VS |
643 | else if (!HAS_GMCH_DISPLAY(dev_priv)) |
644 | dev_priv->gpio_mmio_base = | |
645 | i915_mmio_reg_offset(PCH_GPIOA) - | |
646 | i915_mmio_reg_offset(GPIOA); | |
110447fc | 647 | |
8a8ed1f5 | 648 | mutex_init(&dev_priv->gmbus_mutex); |
28c70f16 | 649 | init_waitqueue_head(&dev_priv->gmbus_wait_queue); |
8a8ed1f5 | 650 | |
5ea6e5e3 | 651 | for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { |
88ac7939 | 652 | if (!intel_gmbus_is_valid_pin(dev_priv, pin)) |
5ea6e5e3 JN |
653 | continue; |
654 | ||
655 | bus = &dev_priv->gmbus[pin]; | |
f899fc64 CW |
656 | |
657 | bus->adapter.owner = THIS_MODULE; | |
658 | bus->adapter.class = I2C_CLASS_DDC; | |
659 | snprintf(bus->adapter.name, | |
69669455 JD |
660 | sizeof(bus->adapter.name), |
661 | "i915 gmbus %s", | |
4c272834 | 662 | get_gmbus_pin(dev_priv, pin)->name); |
f899fc64 | 663 | |
52a05c30 | 664 | bus->adapter.dev.parent = &pdev->dev; |
c2b9152f | 665 | bus->dev_priv = dev_priv; |
f899fc64 CW |
666 | |
667 | bus->adapter.algo = &gmbus_algorithm; | |
f899fc64 | 668 | |
8b1f165a VS |
669 | /* |
670 | * We wish to retry with bit banging | |
671 | * after a timed out GMBUS attempt. | |
672 | */ | |
673 | bus->adapter.retries = 1; | |
674 | ||
e957d772 | 675 | /* By default use a conservative clock rate */ |
5ea6e5e3 | 676 | bus->reg0 = pin | GMBUS_RATE_100KHZ; |
cb8ea752 | 677 | |
83ee9e64 | 678 | /* gmbus seems to be broken on i830 */ |
50a0bc90 | 679 | if (IS_I830(dev_priv)) |
f2ce9faf | 680 | bus->force_bit = 1; |
83ee9e64 | 681 | |
5ea6e5e3 | 682 | intel_gpio_setup(bus, pin); |
cee25168 JN |
683 | |
684 | ret = i2c_add_adapter(&bus->adapter); | |
685 | if (ret) | |
686 | goto err; | |
f899fc64 CW |
687 | } |
688 | ||
af6dc742 | 689 | intel_i2c_reset(dev_priv); |
f899fc64 CW |
690 | |
691 | return 0; | |
692 | ||
693 | err: | |
2417c8c0 | 694 | while (pin--) { |
88ac7939 | 695 | if (!intel_gmbus_is_valid_pin(dev_priv, pin)) |
5ea6e5e3 JN |
696 | continue; |
697 | ||
698 | bus = &dev_priv->gmbus[pin]; | |
f899fc64 CW |
699 | i2c_del_adapter(&bus->adapter); |
700 | } | |
f899fc64 CW |
701 | return ret; |
702 | } | |
703 | ||
3bd7d909 | 704 | struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, |
0184df46 | 705 | unsigned int pin) |
3bd7d909 | 706 | { |
88ac7939 | 707 | if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin))) |
5ea6e5e3 JN |
708 | return NULL; |
709 | ||
710 | return &dev_priv->gmbus[pin].adapter; | |
3bd7d909 DK |
711 | } |
712 | ||
e957d772 CW |
713 | void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed) |
714 | { | |
715 | struct intel_gmbus *bus = to_intel_gmbus(adapter); | |
716 | ||
d5090b96 | 717 | bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed; |
e957d772 CW |
718 | } |
719 | ||
720 | void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) | |
721 | { | |
722 | struct intel_gmbus *bus = to_intel_gmbus(adapter); | |
ade754ec VS |
723 | struct drm_i915_private *dev_priv = bus->dev_priv; |
724 | ||
725 | mutex_lock(&dev_priv->gmbus_mutex); | |
e957d772 | 726 | |
f2ce9faf CW |
727 | bus->force_bit += force_bit ? 1 : -1; |
728 | DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n", | |
729 | force_bit ? "en" : "dis", adapter->name, | |
730 | bus->force_bit); | |
ade754ec VS |
731 | |
732 | mutex_unlock(&dev_priv->gmbus_mutex); | |
e957d772 CW |
733 | } |
734 | ||
40196446 | 735 | void intel_teardown_gmbus(struct drm_i915_private *dev_priv) |
79e53945 | 736 | { |
5ea6e5e3 JN |
737 | struct intel_gmbus *bus; |
738 | unsigned int pin; | |
739 | ||
740 | for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { | |
88ac7939 | 741 | if (!intel_gmbus_is_valid_pin(dev_priv, pin)) |
5ea6e5e3 | 742 | continue; |
f9c10a9b | 743 | |
5ea6e5e3 | 744 | bus = &dev_priv->gmbus[pin]; |
f899fc64 CW |
745 | i2c_del_adapter(&bus->adapter); |
746 | } | |
79e53945 | 747 | } |