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Merge remote-tracking branches 'asoc/topic/fsl-spdif', 'asoc/topic/hdmi', 'asoc/topic...
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_hdmi.c
CommitLineData
7d57382e
EA		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
27 */
28
29#include <linux/i2c.h>
5a0e3ad6 30#include <linux/slab.h>
7d57382e 31#include <linux/delay.h>
178f736a 32#include <linux/hdmi.h>
760285e7 33#include <drm/drmP.h>
c6f95f27 34#include <drm/drm_atomic_helper.h>
760285e7
DH		 35#include <drm/drm_crtc.h>
36#include <drm/drm_edid.h>
7d57382e 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
7d57382e
EA		 39#include "i915_drv.h"
40
30add22d
PZ		 41static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
42{
da63a9f2 43 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
30add22d
PZ		 44}
45
afba0188
DV		 46static void
47assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
48{
30add22d 49 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
afba0188
DV		 50 struct drm_i915_private *dev_priv = dev->dev_private;
51 uint32_t enabled_bits;
52
affa9354 53 enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
afba0188 54
b242b7f7 55 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
afba0188
DV		 56 "HDMI port enabled, expecting disabled\n");
57}
58
f5bbfca3 59struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
ea5b213a 60{
da63a9f2
PZ		 61 struct intel_digital_port *intel_dig_port =
62 container_of(encoder, struct intel_digital_port, base.base);
63 return &intel_dig_port->hdmi;
ea5b213a
CW		 64}
65
df0e9248
CW		 66static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
67{
da63a9f2 68 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
df0e9248
CW		 69}
70
178f736a 71static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
3c17fe4b 72{
178f736a
DL		 73 switch (type) {
74 case HDMI_INFOFRAME_TYPE_AVI:
ed517fbb 75 return VIDEO_DIP_SELECT_AVI;
178f736a 76 case HDMI_INFOFRAME_TYPE_SPD:
ed517fbb 77 return VIDEO_DIP_SELECT_SPD;
c8bb75af
LD		 78 case HDMI_INFOFRAME_TYPE_VENDOR:
79 return VIDEO_DIP_SELECT_VENDOR;
45187ace 80 default:
ffc85dab 81 MISSING_CASE(type);
ed517fbb 82 return 0;
45187ace 83 }
45187ace
JB		 84}
85
178f736a 86static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
45187ace 87{
178f736a
DL		 88 switch (type) {
89 case HDMI_INFOFRAME_TYPE_AVI:
ed517fbb 90 return VIDEO_DIP_ENABLE_AVI;
178f736a 91 case HDMI_INFOFRAME_TYPE_SPD:
ed517fbb 92 return VIDEO_DIP_ENABLE_SPD;
c8bb75af
LD		 93 case HDMI_INFOFRAME_TYPE_VENDOR:
94 return VIDEO_DIP_ENABLE_VENDOR;
fa193ff7 95 default:
ffc85dab 96 MISSING_CASE(type);
ed517fbb 97 return 0;
fa193ff7 98 }
fa193ff7
PZ		 99}
100
178f736a 101static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
2da8af54 102{
178f736a
DL		 103 switch (type) {
104 case HDMI_INFOFRAME_TYPE_AVI:
2da8af54 105 return VIDEO_DIP_ENABLE_AVI_HSW;
178f736a 106 case HDMI_INFOFRAME_TYPE_SPD:
2da8af54 107 return VIDEO_DIP_ENABLE_SPD_HSW;
c8bb75af
LD		 108 case HDMI_INFOFRAME_TYPE_VENDOR:
109 return VIDEO_DIP_ENABLE_VS_HSW;
2da8af54 110 default:
ffc85dab 111 MISSING_CASE(type);
2da8af54
PZ		 112 return 0;
113 }
114}
115
f0f59a00
VS		 116static i915_reg_t
117hsw_dip_data_reg(struct drm_i915_private *dev_priv,
118 enum transcoder cpu_transcoder,
119 enum hdmi_infoframe_type type,
120 int i)
2da8af54 121{
178f736a
DL		 122 switch (type) {
123 case HDMI_INFOFRAME_TYPE_AVI:
436c6d4a 124 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
178f736a 125 case HDMI_INFOFRAME_TYPE_SPD:
436c6d4a 126 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
c8bb75af 127 case HDMI_INFOFRAME_TYPE_VENDOR:
436c6d4a 128 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
2da8af54 129 default:
ffc85dab 130 MISSING_CASE(type);
f0f59a00 131 return INVALID_MMIO_REG;
2da8af54
PZ		 132 }
133}
134
a3da1df7 135static void g4x_write_infoframe(struct drm_encoder *encoder,
178f736a 136 enum hdmi_infoframe_type type,
fff63867 137 const void *frame, ssize_t len)
45187ace 138{
fff63867 139 const uint32_t *data = frame;
3c17fe4b
DH		 140 struct drm_device *dev = encoder->dev;
141 struct drm_i915_private *dev_priv = dev->dev_private;
22509ec8 142 u32 val = I915_READ(VIDEO_DIP_CTL);
178f736a 143 int i;
3c17fe4b 144
822974ae
PZ		 145 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
146
1d4f85ac 147 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
178f736a 148 val |= g4x_infoframe_index(type);
22509ec8 149
178f736a 150 val &= ~g4x_infoframe_enable(type);
45187ace 151
22509ec8 152 I915_WRITE(VIDEO_DIP_CTL, val);
3c17fe4b 153
9d9740f0 154 mmiowb();
45187ace 155 for (i = 0; i < len; i += 4) {
3c17fe4b
DH		 156 I915_WRITE(VIDEO_DIP_DATA, *data);
157 data++;
158 }
adf00b26
PZ		 159 /* Write every possible data byte to force correct ECC calculation. */
160 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
161 I915_WRITE(VIDEO_DIP_DATA, 0);
9d9740f0 162 mmiowb();
3c17fe4b 163
178f736a 164 val |= g4x_infoframe_enable(type);
60c5ea2d 165 val &= ~VIDEO_DIP_FREQ_MASK;
4b24c933 166 val |= VIDEO_DIP_FREQ_VSYNC;
45187ace 167
22509ec8 168 I915_WRITE(VIDEO_DIP_CTL, val);
9d9740f0 169 POSTING_READ(VIDEO_DIP_CTL);
3c17fe4b
DH		 170}
171
cda0aaaf
VS		 172static bool g4x_infoframe_enabled(struct drm_encoder *encoder,
173 const struct intel_crtc_state *pipe_config)
e43823ec 174{
cda0aaaf 175 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
89a35ecd 176 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
e43823ec
JB		 177 u32 val = I915_READ(VIDEO_DIP_CTL);
178
ec1dc603
VS		 179 if ((val & VIDEO_DIP_ENABLE) == 0)
180 return false;
89a35ecd 181
ec1dc603
VS		 182 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
183 return false;
184
185 return val & (VIDEO_DIP_ENABLE_AVI |
186 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
e43823ec
JB		 187}
188
fdf1250a 189static void ibx_write_infoframe(struct drm_encoder *encoder,
178f736a 190 enum hdmi_infoframe_type type,
fff63867 191 const void *frame, ssize_t len)
fdf1250a 192{
fff63867 193 const uint32_t *data = frame;
fdf1250a
PZ		 194 struct drm_device *dev = encoder->dev;
195 struct drm_i915_private *dev_priv = dev->dev_private;
ed517fbb 196 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
f0f59a00 197 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
fdf1250a 198 u32 val = I915_READ(reg);
f0f59a00 199 int i;
fdf1250a 200
822974ae
PZ		 201 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
202
fdf1250a 203 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
178f736a 204 val |= g4x_infoframe_index(type);
fdf1250a 205
178f736a 206 val &= ~g4x_infoframe_enable(type);
fdf1250a
PZ		 207
208 I915_WRITE(reg, val);
209
9d9740f0 210 mmiowb();
fdf1250a
PZ		 211 for (i = 0; i < len; i += 4) {
212 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
213 data++;
214 }
adf00b26
PZ		 215 /* Write every possible data byte to force correct ECC calculation. */
216 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
217 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
9d9740f0 218 mmiowb();
fdf1250a 219
178f736a 220 val |= g4x_infoframe_enable(type);
fdf1250a 221 val &= ~VIDEO_DIP_FREQ_MASK;
4b24c933 222 val |= VIDEO_DIP_FREQ_VSYNC;
fdf1250a
PZ		 223
224 I915_WRITE(reg, val);
9d9740f0 225 POSTING_READ(reg);
fdf1250a
PZ		 226}
227
cda0aaaf
VS		 228static bool ibx_infoframe_enabled(struct drm_encoder *encoder,
229 const struct intel_crtc_state *pipe_config)
e43823ec 230{
cda0aaaf 231 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
052f62f7 232 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
cda0aaaf
VS		 233 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
234 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
e43823ec
JB		 235 u32 val = I915_READ(reg);
236
ec1dc603
VS		 237 if ((val & VIDEO_DIP_ENABLE) == 0)
238 return false;
239
240 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
241 return false;
052f62f7 242
ec1dc603
VS		 243 return val & (VIDEO_DIP_ENABLE_AVI |
244 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
245 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
e43823ec
JB		 246}
247
fdf1250a 248static void cpt_write_infoframe(struct drm_encoder *encoder,
178f736a 249 enum hdmi_infoframe_type type,
fff63867 250 const void *frame, ssize_t len)
b055c8f3 251{
fff63867 252 const uint32_t *data = frame;
b055c8f3
JB		 253 struct drm_device *dev = encoder->dev;
254 struct drm_i915_private *dev_priv = dev->dev_private;
ed517fbb 255 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
f0f59a00 256 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
22509ec8 257 u32 val = I915_READ(reg);
f0f59a00 258 int i;
b055c8f3 259
822974ae
PZ		 260 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
261
64a8fc01 262 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
178f736a 263 val |= g4x_infoframe_index(type);
45187ace 264
ecb97851
PZ		 265 /* The DIP control register spec says that we need to update the AVI
266 * infoframe without clearing its enable bit */
178f736a
DL		 267 if (type != HDMI_INFOFRAME_TYPE_AVI)
268 val &= ~g4x_infoframe_enable(type);
ecb97851 269
22509ec8 270 I915_WRITE(reg, val);
45187ace 271
9d9740f0 272 mmiowb();
45187ace 273 for (i = 0; i < len; i += 4) {
b055c8f3
JB		 274 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
275 data++;
276 }
adf00b26
PZ		 277 /* Write every possible data byte to force correct ECC calculation. */
278 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
279 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
9d9740f0 280 mmiowb();
b055c8f3 281
178f736a 282 val |= g4x_infoframe_enable(type);
60c5ea2d 283 val &= ~VIDEO_DIP_FREQ_MASK;
4b24c933 284 val |= VIDEO_DIP_FREQ_VSYNC;
45187ace 285
22509ec8 286 I915_WRITE(reg, val);
9d9740f0 287 POSTING_READ(reg);
45187ace 288}
90b107c8 289
cda0aaaf
VS		 290static bool cpt_infoframe_enabled(struct drm_encoder *encoder,
291 const struct intel_crtc_state *pipe_config)
e43823ec 292{
cda0aaaf
VS		 293 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
294 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
295 u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
e43823ec 296
ec1dc603
VS		 297 if ((val & VIDEO_DIP_ENABLE) == 0)
298 return false;
299
300 return val & (VIDEO_DIP_ENABLE_AVI |
301 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
302 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
e43823ec
JB		 303}
304
90b107c8 305static void vlv_write_infoframe(struct drm_encoder *encoder,
178f736a 306 enum hdmi_infoframe_type type,
fff63867 307 const void *frame, ssize_t len)
90b107c8 308{
fff63867 309 const uint32_t *data = frame;
90b107c8
SK		 310 struct drm_device *dev = encoder->dev;
311 struct drm_i915_private *dev_priv = dev->dev_private;
ed517fbb 312 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
f0f59a00 313 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
22509ec8 314 u32 val = I915_READ(reg);
f0f59a00 315 int i;
90b107c8 316
822974ae
PZ		 317 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
318
90b107c8 319 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
178f736a 320 val |= g4x_infoframe_index(type);
22509ec8 321
178f736a 322 val &= ~g4x_infoframe_enable(type);
90b107c8 323
22509ec8 324 I915_WRITE(reg, val);
90b107c8 325
9d9740f0 326 mmiowb();
90b107c8
SK		 327 for (i = 0; i < len; i += 4) {
328 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
329 data++;
330 }
adf00b26
PZ		 331 /* Write every possible data byte to force correct ECC calculation. */
332 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
333 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
9d9740f0 334 mmiowb();
90b107c8 335
178f736a 336 val |= g4x_infoframe_enable(type);
60c5ea2d 337 val &= ~VIDEO_DIP_FREQ_MASK;
4b24c933 338 val |= VIDEO_DIP_FREQ_VSYNC;
90b107c8 339
22509ec8 340 I915_WRITE(reg, val);
9d9740f0 341 POSTING_READ(reg);
90b107c8
SK		 342}
343
cda0aaaf
VS		 344static bool vlv_infoframe_enabled(struct drm_encoder *encoder,
345 const struct intel_crtc_state *pipe_config)
e43823ec 346{
cda0aaaf 347 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
535afa2e 348 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
cda0aaaf
VS		 349 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
350 u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
e43823ec 351
ec1dc603
VS		 352 if ((val & VIDEO_DIP_ENABLE) == 0)
353 return false;
354
355 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
356 return false;
535afa2e 357
ec1dc603
VS		 358 return val & (VIDEO_DIP_ENABLE_AVI |
359 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
360 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
e43823ec
JB		 361}
362
8c5f5f7c 363static void hsw_write_infoframe(struct drm_encoder *encoder,
178f736a 364 enum hdmi_infoframe_type type,
fff63867 365 const void *frame, ssize_t len)
8c5f5f7c 366{
fff63867 367 const uint32_t *data = frame;
2da8af54
PZ		 368 struct drm_device *dev = encoder->dev;
369 struct drm_i915_private *dev_priv = dev->dev_private;
370 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
436c6d4a 371 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
f0f59a00
VS		 372 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
373 i915_reg_t data_reg;
178f736a 374 int i;
2da8af54 375 u32 val = I915_READ(ctl_reg);
8c5f5f7c 376
436c6d4a 377 data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
2da8af54 378
178f736a 379 val &= ~hsw_infoframe_enable(type);
2da8af54
PZ		 380 I915_WRITE(ctl_reg, val);
381
9d9740f0 382 mmiowb();
2da8af54 383 for (i = 0; i < len; i += 4) {
436c6d4a
VS		 384 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
385 type, i >> 2), *data);
2da8af54
PZ		 386 data++;
387 }
adf00b26
PZ		 388 /* Write every possible data byte to force correct ECC calculation. */
389 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
436c6d4a
VS		 390 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
391 type, i >> 2), 0);
9d9740f0 392 mmiowb();
8c5f5f7c 393
178f736a 394 val |= hsw_infoframe_enable(type);
2da8af54 395 I915_WRITE(ctl_reg, val);
9d9740f0 396 POSTING_READ(ctl_reg);
8c5f5f7c
ED		 397}
398
cda0aaaf
VS		 399static bool hsw_infoframe_enabled(struct drm_encoder *encoder,
400 const struct intel_crtc_state *pipe_config)
e43823ec 401{
cda0aaaf
VS		 402 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
403 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
e43823ec 404
ec1dc603
VS		 405 return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
406 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
407 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
e43823ec
JB		 408}
409
5adaea79
DL		 410/*
411 * The data we write to the DIP data buffer registers is 1 byte bigger than the
412 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
413 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
414 * used for both technologies.
415 *
416 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
417 * DW1: DB3 | DB2 | DB1 | DB0
418 * DW2: DB7 | DB6 | DB5 | DB4
419 * DW3: ...
420 *
421 * (HB is Header Byte, DB is Data Byte)
422 *
423 * The hdmi pack() functions don't know about that hardware specific hole so we
424 * trick them by giving an offset into the buffer and moving back the header
425 * bytes by one.
426 */
9198ee5b
DL		 427static void intel_write_infoframe(struct drm_encoder *encoder,
428 union hdmi_infoframe *frame)
45187ace
JB		 429{
430 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
5adaea79
DL		 431 uint8_t buffer[VIDEO_DIP_DATA_SIZE];
432 ssize_t len;
45187ace 433
5adaea79
DL		 434 /* see comment above for the reason for this offset */
435 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
436 if (len < 0)
437 return;
438
439 /* Insert the 'hole' (see big comment above) at position 3 */
440 buffer[0] = buffer[1];
441 buffer[1] = buffer[2];
442 buffer[2] = buffer[3];
443 buffer[3] = 0;
444 len++;
45187ace 445
5adaea79 446 intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
45187ace
JB		 447}
448
687f4d06 449static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
7c5f93b0 450 const struct drm_display_mode *adjusted_mode)
45187ace 451{
abedc077 452 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
50f3b016 453 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
5adaea79
DL		 454 union hdmi_infoframe frame;
455 int ret;
45187ace 456
5adaea79
DL		 457 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
458 adjusted_mode);
459 if (ret < 0) {
460 DRM_ERROR("couldn't fill AVI infoframe\n");
461 return;
462 }
c846b619 463
abedc077 464 if (intel_hdmi->rgb_quant_range_selectable) {
6e3c9717 465 if (intel_crtc->config->limited_color_range)
5adaea79
DL		 466 frame.avi.quantization_range =
467 HDMI_QUANTIZATION_RANGE_LIMITED;
abedc077 468 else
5adaea79
DL		 469 frame.avi.quantization_range =
470 HDMI_QUANTIZATION_RANGE_FULL;
abedc077
VS		 471 }
472
9198ee5b 473 intel_write_infoframe(encoder, &frame);
b055c8f3
JB		 474}
475
687f4d06 476static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
c0864cb3 477{
5adaea79
DL		 478 union hdmi_infoframe frame;
479 int ret;
480
481 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
482 if (ret < 0) {
483 DRM_ERROR("couldn't fill SPD infoframe\n");
484 return;
485 }
c0864cb3 486
5adaea79 487 frame.spd.sdi = HDMI_SPD_SDI_PC;
c0864cb3 488
9198ee5b 489 intel_write_infoframe(encoder, &frame);
c0864cb3
JB		 490}
491
c8bb75af
LD		 492static void
493intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
7c5f93b0 494 const struct drm_display_mode *adjusted_mode)
c8bb75af
LD		 495{
496 union hdmi_infoframe frame;
497 int ret;
498
499 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
500 adjusted_mode);
501 if (ret < 0)
502 return;
503
504 intel_write_infoframe(encoder, &frame);
505}
506
687f4d06 507static void g4x_set_infoframes(struct drm_encoder *encoder,
6897b4b5 508 bool enable,
7c5f93b0 509 const struct drm_display_mode *adjusted_mode)
687f4d06 510{
0c14c7f9 511 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
69fde0a6
VS		 512 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
513 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
f0f59a00 514 i915_reg_t reg = VIDEO_DIP_CTL;
0c14c7f9 515 u32 val = I915_READ(reg);
822cdc52 516 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
0c14c7f9 517
afba0188
DV		 518 assert_hdmi_port_disabled(intel_hdmi);
519
0c14c7f9
PZ		 520 /* If the registers were not initialized yet, they might be zeroes,
521 * which means we're selecting the AVI DIP and we're setting its
522 * frequency to once. This seems to really confuse the HW and make
523 * things stop working (the register spec says the AVI always needs to
524 * be sent every VSync). So here we avoid writing to the register more
525 * than we need and also explicitly select the AVI DIP and explicitly
526 * set its frequency to every VSync. Avoiding to write it twice seems to
527 * be enough to solve the problem, but being defensive shouldn't hurt us
528 * either. */
529 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
530
6897b4b5 531 if (!enable) {
0c14c7f9
PZ		 532 if (!(val & VIDEO_DIP_ENABLE))
533 return;
0be6f0c8
VS		 534 if (port != (val & VIDEO_DIP_PORT_MASK)) {
535 DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
536 (val & VIDEO_DIP_PORT_MASK) >> 29);
537 return;
538 }
539 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
540 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
0c14c7f9 541 I915_WRITE(reg, val);
9d9740f0 542 POSTING_READ(reg);
0c14c7f9
PZ		 543 return;
544 }
545
72b78c9d
PZ		 546 if (port != (val & VIDEO_DIP_PORT_MASK)) {
547 if (val & VIDEO_DIP_ENABLE) {
0be6f0c8
VS		 548 DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
549 (val & VIDEO_DIP_PORT_MASK) >> 29);
550 return;
72b78c9d
PZ		 551 }
552 val &= ~VIDEO_DIP_PORT_MASK;
553 val |= port;
554 }
555
822974ae 556 val |= VIDEO_DIP_ENABLE;
0be6f0c8
VS		 557 val &= ~(VIDEO_DIP_ENABLE_AVI |
558 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
822974ae 559
f278d972 560 I915_WRITE(reg, val);
9d9740f0 561 POSTING_READ(reg);
f278d972 562
687f4d06
PZ		 563 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
564 intel_hdmi_set_spd_infoframe(encoder);
c8bb75af 565 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
687f4d06
PZ		 566}
567
6d67415f
VS		 568static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder)
569{
570 struct drm_device *dev = encoder->dev;
571 struct drm_connector *connector;
572
573 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
574
575 /*
576 * HDMI cloning is only supported on g4x which doesn't
577 * support deep color or GCP infoframes anyway so no
578 * need to worry about multiple HDMI sinks here.
579 */
580 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
581 if (connector->encoder == encoder)
582 return connector->display_info.bpc > 8;
583
584 return false;
585}
586
12aa3290
VS		 587/*
588 * Determine if default_phase=1 can be indicated in the GCP infoframe.
589 *
590 * From HDMI specification 1.4a:
591 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
592 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
593 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
594 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
595 * phase of 0
596 */
597static bool gcp_default_phase_possible(int pipe_bpp,
598 const struct drm_display_mode *mode)
599{
600 unsigned int pixels_per_group;
601
602 switch (pipe_bpp) {
603 case 30:
604 /* 4 pixels in 5 clocks */
605 pixels_per_group = 4;
606 break;
607 case 36:
608 /* 2 pixels in 3 clocks */
609 pixels_per_group = 2;
610 break;
611 case 48:
612 /* 1 pixel in 2 clocks */
613 pixels_per_group = 1;
614 break;
615 default:
616 /* phase information not relevant for 8bpc */
617 return false;
618 }
619
620 return mode->crtc_hdisplay % pixels_per_group == 0 &&
621 mode->crtc_htotal % pixels_per_group == 0 &&
622 mode->crtc_hblank_start % pixels_per_group == 0 &&
623 mode->crtc_hblank_end % pixels_per_group == 0 &&
624 mode->crtc_hsync_start % pixels_per_group == 0 &&
625 mode->crtc_hsync_end % pixels_per_group == 0 &&
626 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
627 mode->crtc_htotal/2 % pixels_per_group == 0);
628}
629
6d67415f
VS		 630static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
631{
632 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
633 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
f0f59a00
VS		 634 i915_reg_t reg;
635 u32 val = 0;
6d67415f
VS		 636
637 if (HAS_DDI(dev_priv))
638 reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
666a4537 639 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6d67415f 640 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
2d1fe073 641 else if (HAS_PCH_SPLIT(dev_priv))
6d67415f
VS		 642 reg = TVIDEO_DIP_GCP(crtc->pipe);
643 else
644 return false;
645
646 /* Indicate color depth whenever the sink supports deep color */
647 if (hdmi_sink_is_deep_color(encoder))
648 val |= GCP_COLOR_INDICATION;
649
12aa3290
VS		 650 /* Enable default_phase whenever the display mode is suitably aligned */
651 if (gcp_default_phase_possible(crtc->config->pipe_bpp,
652 &crtc->config->base.adjusted_mode))
653 val |= GCP_DEFAULT_PHASE_ENABLE;
654
6d67415f
VS		 655 I915_WRITE(reg, val);
656
657 return val != 0;
658}
659
687f4d06 660static void ibx_set_infoframes(struct drm_encoder *encoder,
6897b4b5 661 bool enable,
7c5f93b0 662 const struct drm_display_mode *adjusted_mode)
687f4d06 663{
0c14c7f9
PZ		 664 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
665 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
69fde0a6
VS		 666 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
667 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
f0f59a00 668 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
0c14c7f9 669 u32 val = I915_READ(reg);
822cdc52 670 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
0c14c7f9 671
afba0188
DV		 672 assert_hdmi_port_disabled(intel_hdmi);
673
0c14c7f9
PZ		 674 /* See the big comment in g4x_set_infoframes() */
675 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
676
6897b4b5 677 if (!enable) {
0c14c7f9
PZ		 678 if (!(val & VIDEO_DIP_ENABLE))
679 return;
0be6f0c8
VS		 680 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
681 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
682 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
0c14c7f9 683 I915_WRITE(reg, val);
9d9740f0 684 POSTING_READ(reg);
0c14c7f9
PZ		 685 return;
686 }
687
72b78c9d 688 if (port != (val & VIDEO_DIP_PORT_MASK)) {
0be6f0c8
VS		 689 WARN(val & VIDEO_DIP_ENABLE,
690 "DIP already enabled on port %c\n",
691 (val & VIDEO_DIP_PORT_MASK) >> 29);
72b78c9d
PZ		 692 val &= ~VIDEO_DIP_PORT_MASK;
693 val |= port;
694 }
695
822974ae 696 val |= VIDEO_DIP_ENABLE;
0be6f0c8
VS		 697 val &= ~(VIDEO_DIP_ENABLE_AVI |
698 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
699 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
822974ae 700
6d67415f
VS		 701 if (intel_hdmi_set_gcp_infoframe(encoder))
702 val |= VIDEO_DIP_ENABLE_GCP;
703
f278d972 704 I915_WRITE(reg, val);
9d9740f0 705 POSTING_READ(reg);
f278d972 706
687f4d06
PZ		 707 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
708 intel_hdmi_set_spd_infoframe(encoder);
c8bb75af 709 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
687f4d06
PZ		 710}
711
712static void cpt_set_infoframes(struct drm_encoder *encoder,
6897b4b5 713 bool enable,
7c5f93b0 714 const struct drm_display_mode *adjusted_mode)
687f4d06 715{
0c14c7f9
PZ		 716 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
717 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
718 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
f0f59a00 719 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
0c14c7f9
PZ		 720 u32 val = I915_READ(reg);
721
afba0188
DV		 722 assert_hdmi_port_disabled(intel_hdmi);
723
0c14c7f9
PZ		 724 /* See the big comment in g4x_set_infoframes() */
725 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
726
6897b4b5 727 if (!enable) {
0c14c7f9
PZ		 728 if (!(val & VIDEO_DIP_ENABLE))
729 return;
0be6f0c8
VS		 730 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
731 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
732 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
0c14c7f9 733 I915_WRITE(reg, val);
9d9740f0 734 POSTING_READ(reg);
0c14c7f9
PZ		 735 return;
736 }
737
822974ae
PZ		 738 /* Set both together, unset both together: see the spec. */
739 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
0dd87d20 740 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
0be6f0c8 741 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
822974ae 742
6d67415f
VS		 743 if (intel_hdmi_set_gcp_infoframe(encoder))
744 val |= VIDEO_DIP_ENABLE_GCP;
745
822974ae 746 I915_WRITE(reg, val);
9d9740f0 747 POSTING_READ(reg);
822974ae 748
687f4d06
PZ		 749 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
750 intel_hdmi_set_spd_infoframe(encoder);
c8bb75af 751 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
687f4d06
PZ		 752}
753
754static void vlv_set_infoframes(struct drm_encoder *encoder,
6897b4b5 755 bool enable,
7c5f93b0 756 const struct drm_display_mode *adjusted_mode)
687f4d06 757{
0c14c7f9 758 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
6a2b8021 759 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
0c14c7f9
PZ		 760 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
761 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
f0f59a00 762 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
0c14c7f9 763 u32 val = I915_READ(reg);
6a2b8021 764 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
0c14c7f9 765
afba0188
DV		 766 assert_hdmi_port_disabled(intel_hdmi);
767
0c14c7f9
PZ		 768 /* See the big comment in g4x_set_infoframes() */
769 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
770
6897b4b5 771 if (!enable) {
0c14c7f9
PZ		 772 if (!(val & VIDEO_DIP_ENABLE))
773 return;
0be6f0c8
VS		 774 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
775 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
776 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
0c14c7f9 777 I915_WRITE(reg, val);
9d9740f0 778 POSTING_READ(reg);
0c14c7f9
PZ		 779 return;
780 }
781
6a2b8021 782 if (port != (val & VIDEO_DIP_PORT_MASK)) {
0be6f0c8
VS		 783 WARN(val & VIDEO_DIP_ENABLE,
784 "DIP already enabled on port %c\n",
785 (val & VIDEO_DIP_PORT_MASK) >> 29);
6a2b8021
JB		 786 val &= ~VIDEO_DIP_PORT_MASK;
787 val |= port;
788 }
789
822974ae 790 val |= VIDEO_DIP_ENABLE;
0be6f0c8
VS		 791 val &= ~(VIDEO_DIP_ENABLE_AVI |
792 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
793 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
822974ae 794
6d67415f
VS		 795 if (intel_hdmi_set_gcp_infoframe(encoder))
796 val |= VIDEO_DIP_ENABLE_GCP;
797
822974ae 798 I915_WRITE(reg, val);
9d9740f0 799 POSTING_READ(reg);
822974ae 800
687f4d06
PZ		 801 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
802 intel_hdmi_set_spd_infoframe(encoder);
c8bb75af 803 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
687f4d06
PZ		 804}
805
806static void hsw_set_infoframes(struct drm_encoder *encoder,
6897b4b5 807 bool enable,
7c5f93b0 808 const struct drm_display_mode *adjusted_mode)
687f4d06 809{
0c14c7f9
PZ		 810 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
811 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
812 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
f0f59a00 813 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
0dd87d20 814 u32 val = I915_READ(reg);
0c14c7f9 815
afba0188
DV		 816 assert_hdmi_port_disabled(intel_hdmi);
817
0be6f0c8
VS		 818 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
819 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
820 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
821
6897b4b5 822 if (!enable) {
0be6f0c8 823 I915_WRITE(reg, val);
9d9740f0 824 POSTING_READ(reg);
0c14c7f9
PZ		 825 return;
826 }
827
6d67415f
VS		 828 if (intel_hdmi_set_gcp_infoframe(encoder))
829 val |= VIDEO_DIP_ENABLE_GCP_HSW;
830
0dd87d20 831 I915_WRITE(reg, val);
9d9740f0 832 POSTING_READ(reg);
0dd87d20 833
687f4d06
PZ		 834 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
835 intel_hdmi_set_spd_infoframe(encoder);
c8bb75af 836 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
687f4d06
PZ		 837}
838
0c2fb7c6
VS		 839void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
840{
841 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
842 struct i2c_adapter *adapter =
843 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
844
845 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
846 return;
847
848 DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
849 enable ? "Enabling" : "Disabling");
850
851 drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
852 adapter, enable);
853}
854
4cde8a21 855static void intel_hdmi_prepare(struct intel_encoder *encoder)
7d57382e 856{
c59423a3 857 struct drm_device *dev = encoder->base.dev;
7d57382e 858 struct drm_i915_private *dev_priv = dev->dev_private;
c59423a3
DV		 859 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
860 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
7c5f93b0 861 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
b242b7f7 862 u32 hdmi_val;
7d57382e 863
0c2fb7c6
VS		 864 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
865
b242b7f7 866 hdmi_val = SDVO_ENCODING_HDMI;
0f2a2a75
VS		 867 if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
868 hdmi_val |= HDMI_COLOR_RANGE_16_235;
b599c0bc 869 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
b242b7f7 870 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
b599c0bc 871 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
b242b7f7 872 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
7d57382e 873
6e3c9717 874 if (crtc->config->pipe_bpp > 24)
4f3a8bc7 875 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
020f6704 876 else
4f3a8bc7 877 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
020f6704 878
6e3c9717 879 if (crtc->config->has_hdmi_sink)
dc0fa718 880 hdmi_val |= HDMI_MODE_SELECT_HDMI;
2e3d6006 881
75770564 882 if (HAS_PCH_CPT(dev))
c59423a3 883 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
44f37d1f
CML		 884 else if (IS_CHERRYVIEW(dev))
885 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
dc0fa718 886 else
c59423a3 887 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
7d57382e 888
b242b7f7
PZ		 889 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
890 POSTING_READ(intel_hdmi->hdmi_reg);
7d57382e
EA		 891}
892
85234cdc
DV		 893static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
894 enum pipe *pipe)
7d57382e 895{
85234cdc 896 struct drm_device *dev = encoder->base.dev;
7d57382e 897 struct drm_i915_private *dev_priv = dev->dev_private;
85234cdc 898 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
6d129bea 899 enum intel_display_power_domain power_domain;
85234cdc 900 u32 tmp;
5b092174 901 bool ret;
85234cdc 902
6d129bea 903 power_domain = intel_display_port_power_domain(encoder);
5b092174 904 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
6d129bea
ID		 905 return false;
906
5b092174
ID		 907 ret = false;
908
b242b7f7 909 tmp = I915_READ(intel_hdmi->hdmi_reg);
85234cdc
DV		 910
911 if (!(tmp & SDVO_ENABLE))
5b092174 912 goto out;
85234cdc
DV		 913
914 if (HAS_PCH_CPT(dev))
915 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 916 else if (IS_CHERRYVIEW(dev))
917 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
85234cdc
DV		 918 else
919 *pipe = PORT_TO_PIPE(tmp);
920
5b092174
ID		 921 ret = true;
922
923out:
924 intel_display_power_put(dev_priv, power_domain);
925
926 return ret;
85234cdc
DV		 927}
928
045ac3b5 929static void intel_hdmi_get_config(struct intel_encoder *encoder,
5cec258b 930 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 931{
932 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
8c875fca
VS		 933 struct drm_device *dev = encoder->base.dev;
934 struct drm_i915_private *dev_priv = dev->dev_private;
045ac3b5 935 u32 tmp, flags = 0;
18442d08 936 int dotclock;
045ac3b5
JB		 937
938 tmp = I915_READ(intel_hdmi->hdmi_reg);
939
940 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
941 flags |= DRM_MODE_FLAG_PHSYNC;
942 else
943 flags |= DRM_MODE_FLAG_NHSYNC;
944
945 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
946 flags |= DRM_MODE_FLAG_PVSYNC;
947 else
948 flags |= DRM_MODE_FLAG_NVSYNC;
949
6897b4b5
DV		 950 if (tmp & HDMI_MODE_SELECT_HDMI)
951 pipe_config->has_hdmi_sink = true;
952
cda0aaaf 953 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
e43823ec
JB		 954 pipe_config->has_infoframe = true;
955
c84db770 956 if (tmp & SDVO_AUDIO_ENABLE)
9ed109a7
DV		 957 pipe_config->has_audio = true;
958
8c875fca
VS		 959 if (!HAS_PCH_SPLIT(dev) &&
960 tmp & HDMI_COLOR_RANGE_16_235)
961 pipe_config->limited_color_range = true;
962
2d112de7 963 pipe_config->base.adjusted_mode.flags |= flags;
18442d08
VS		 964
965 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
966 dotclock = pipe_config->port_clock * 2 / 3;
967 else
968 dotclock = pipe_config->port_clock;
969
be69a133
VS		 970 if (pipe_config->pixel_multiplier)
971 dotclock /= pipe_config->pixel_multiplier;
972
2d112de7 973 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
2bae0304
ACO		 974
975 pipe_config->lane_count = 4;
045ac3b5
JB		 976}
977
d1b1589c
VS		 978static void intel_enable_hdmi_audio(struct intel_encoder *encoder)
979{
980 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
981
982 WARN_ON(!crtc->config->has_hdmi_sink);
983 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
984 pipe_name(crtc->pipe));
985 intel_audio_codec_enable(encoder);
986}
987
bf868c7d 988static void g4x_enable_hdmi(struct intel_encoder *encoder)
7d57382e 989{
5ab432ef 990 struct drm_device *dev = encoder->base.dev;
7d57382e 991 struct drm_i915_private *dev_priv = dev->dev_private;
bf868c7d 992 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
5ab432ef 993 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
7d57382e
EA		 994 u32 temp;
995
b242b7f7 996 temp = I915_READ(intel_hdmi->hdmi_reg);
d8a2d0e0 997
bf868c7d
VS		 998 temp |= SDVO_ENABLE;
999 if (crtc->config->has_audio)
1000 temp |= SDVO_AUDIO_ENABLE;
7a87c289 1001
bf868c7d
VS		 1002 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1003 POSTING_READ(intel_hdmi->hdmi_reg);
1004
1005 if (crtc->config->has_audio)
1006 intel_enable_hdmi_audio(encoder);
1007}
1008
1009static void ibx_enable_hdmi(struct intel_encoder *encoder)
1010{
1011 struct drm_device *dev = encoder->base.dev;
1012 struct drm_i915_private *dev_priv = dev->dev_private;
1013 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1014 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1015 u32 temp;
1016
1017 temp = I915_READ(intel_hdmi->hdmi_reg);
d8a2d0e0 1018
bf868c7d
VS		 1019 temp |= SDVO_ENABLE;
1020 if (crtc->config->has_audio)
1021 temp |= SDVO_AUDIO_ENABLE;
5ab432ef 1022
bf868c7d
VS		 1023 /*
1024 * HW workaround, need to write this twice for issue
1025 * that may result in first write getting masked.
1026 */
1027 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1028 POSTING_READ(intel_hdmi->hdmi_reg);
b242b7f7
PZ		 1029 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1030 POSTING_READ(intel_hdmi->hdmi_reg);
5ab432ef 1031
bf868c7d
VS		 1032 /*
1033 * HW workaround, need to toggle enable bit off and on
1034 * for 12bpc with pixel repeat.
1035 *
1036 * FIXME: BSpec says this should be done at the end of
1037 * of the modeset sequence, so not sure if this isn't too soon.
5ab432ef 1038 */
bf868c7d
VS		 1039 if (crtc->config->pipe_bpp > 24 &&
1040 crtc->config->pixel_multiplier > 1) {
1041 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1042 POSTING_READ(intel_hdmi->hdmi_reg);
1043
1044 /*
1045 * HW workaround, need to write this twice for issue
1046 * that may result in first write getting masked.
1047 */
1048 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1049 POSTING_READ(intel_hdmi->hdmi_reg);
b242b7f7
PZ		 1050 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1051 POSTING_READ(intel_hdmi->hdmi_reg);
7d57382e 1052 }
c1dec79a 1053
bf868c7d 1054 if (crtc->config->has_audio)
d1b1589c
VS		 1055 intel_enable_hdmi_audio(encoder);
1056}
1057
1058static void cpt_enable_hdmi(struct intel_encoder *encoder)
1059{
1060 struct drm_device *dev = encoder->base.dev;
1061 struct drm_i915_private *dev_priv = dev->dev_private;
1062 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1063 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1064 enum pipe pipe = crtc->pipe;
1065 u32 temp;
1066
1067 temp = I915_READ(intel_hdmi->hdmi_reg);
1068
1069 temp |= SDVO_ENABLE;
1070 if (crtc->config->has_audio)
1071 temp |= SDVO_AUDIO_ENABLE;
1072
1073 /*
1074 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1075 *
1076 * The procedure for 12bpc is as follows:
1077 * 1. disable HDMI clock gating
1078 * 2. enable HDMI with 8bpc
1079 * 3. enable HDMI with 12bpc
1080 * 4. enable HDMI clock gating
1081 */
1082
1083 if (crtc->config->pipe_bpp > 24) {
1084 I915_WRITE(TRANS_CHICKEN1(pipe),
1085 I915_READ(TRANS_CHICKEN1(pipe)) |
1086 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1087
1088 temp &= ~SDVO_COLOR_FORMAT_MASK;
1089 temp |= SDVO_COLOR_FORMAT_8bpc;
c1dec79a 1090 }
d1b1589c
VS		 1091
1092 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1093 POSTING_READ(intel_hdmi->hdmi_reg);
1094
1095 if (crtc->config->pipe_bpp > 24) {
1096 temp &= ~SDVO_COLOR_FORMAT_MASK;
1097 temp |= HDMI_COLOR_FORMAT_12bpc;
1098
1099 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1100 POSTING_READ(intel_hdmi->hdmi_reg);
1101
1102 I915_WRITE(TRANS_CHICKEN1(pipe),
1103 I915_READ(TRANS_CHICKEN1(pipe)) &
1104 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1105 }
1106
1107 if (crtc->config->has_audio)
1108 intel_enable_hdmi_audio(encoder);
b76cf76b 1109}
89b667f8 1110
b76cf76b
JN		 1111static void vlv_enable_hdmi(struct intel_encoder *encoder)
1112{
5ab432ef
DV		 1113}
1114
1115static void intel_disable_hdmi(struct intel_encoder *encoder)
1116{
1117 struct drm_device *dev = encoder->base.dev;
1118 struct drm_i915_private *dev_priv = dev->dev_private;
1119 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
495a5bb8 1120 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
5ab432ef 1121 u32 temp;
5ab432ef 1122
b242b7f7 1123 temp = I915_READ(intel_hdmi->hdmi_reg);
5ab432ef 1124
1612c8bd 1125 temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
b242b7f7
PZ		 1126 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1127 POSTING_READ(intel_hdmi->hdmi_reg);
1612c8bd
VS		 1128
1129 /*
1130 * HW workaround for IBX, we need to move the port
1131 * to transcoder A after disabling it to allow the
1132 * matching DP port to be enabled on transcoder A.
1133 */
1134 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) {
0c241d5b
VS		 1135 /*
1136 * We get CPU/PCH FIFO underruns on the other pipe when
1137 * doing the workaround. Sweep them under the rug.
1138 */
1139 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1140 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1141
1612c8bd
VS		 1142 temp &= ~SDVO_PIPE_B_SELECT;
1143 temp |= SDVO_ENABLE;
1144 /*
1145 * HW workaround, need to write this twice for issue
1146 * that may result in first write getting masked.
1147 */
1148 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1149 POSTING_READ(intel_hdmi->hdmi_reg);
1150 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1151 POSTING_READ(intel_hdmi->hdmi_reg);
1152
1153 temp &= ~SDVO_ENABLE;
1154 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1155 POSTING_READ(intel_hdmi->hdmi_reg);
0c241d5b
VS		 1156
1157 intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
1158 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1159 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1612c8bd 1160 }
6d67415f 1161
0be6f0c8 1162 intel_hdmi->set_infoframes(&encoder->base, false, NULL);
0c2fb7c6
VS		 1163
1164 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
7d57382e
EA		 1165}
1166
a4790cec
VS		 1167static void g4x_disable_hdmi(struct intel_encoder *encoder)
1168{
1169 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1170
1171 if (crtc->config->has_audio)
1172 intel_audio_codec_disable(encoder);
1173
1174 intel_disable_hdmi(encoder);
1175}
1176
1177static void pch_disable_hdmi(struct intel_encoder *encoder)
1178{
1179 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1180
1181 if (crtc->config->has_audio)
1182 intel_audio_codec_disable(encoder);
1183}
1184
1185static void pch_post_disable_hdmi(struct intel_encoder *encoder)
1186{
1187 intel_disable_hdmi(encoder);
1188}
1189
c578d152 1190static int intel_hdmi_source_max_tmds_clock(struct drm_i915_private *dev_priv)
7d148ef5 1191{
c578d152 1192 if (IS_G4X(dev_priv))
7d148ef5 1193 return 165000;
c578d152 1194 else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)
7d148ef5
DV		 1195 return 300000;
1196 else
1197 return 225000;
1198}
1199
c578d152
VS		 1200static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1201 bool respect_downstream_limits)
1202{
1203 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1204 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(to_i915(dev));
1205
1206 if (respect_downstream_limits) {
1207 if (hdmi->dp_dual_mode.max_tmds_clock)
1208 max_tmds_clock = min(max_tmds_clock,
1209 hdmi->dp_dual_mode.max_tmds_clock);
1210 if (!hdmi->has_hdmi_sink)
1211 max_tmds_clock = min(max_tmds_clock, 165000);
1212 }
1213
1214 return max_tmds_clock;
1215}
1216
e64e739e
VS		 1217static enum drm_mode_status
1218hdmi_port_clock_valid(struct intel_hdmi *hdmi,
c578d152 1219 int clock, bool respect_downstream_limits)
e64e739e
VS		 1220{
1221 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1222
1223 if (clock < 25000)
1224 return MODE_CLOCK_LOW;
c578d152 1225 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits))
e64e739e
VS		 1226 return MODE_CLOCK_HIGH;
1227
5e6ccc0b
VS		 1228 /* BXT DPLL can't generate 223-240 MHz */
1229 if (IS_BROXTON(dev) && clock > 223333 && clock < 240000)
1230 return MODE_CLOCK_RANGE;
1231
1232 /* CHV DPLL can't generate 216-240 MHz */
1233 if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000)
e64e739e
VS		 1234 return MODE_CLOCK_RANGE;
1235
1236 return MODE_OK;
1237}
1238
c19de8eb
DL		 1239static enum drm_mode_status
1240intel_hdmi_mode_valid(struct drm_connector *connector,
1241 struct drm_display_mode *mode)
7d57382e 1242{
e64e739e
VS		 1243 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1244 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1245 enum drm_mode_status status;
1246 int clock;
587bf496 1247 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
e64e739e
VS		 1248
1249 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1250 return MODE_NO_DBLESCAN;
697c4078 1251
e64e739e 1252 clock = mode->clock;
587bf496
MK		 1253
1254 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1255 clock *= 2;
1256
1257 if (clock > max_dotclk)
1258 return MODE_CLOCK_HIGH;
1259
697c4078
CT		 1260 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1261 clock *= 2;
1262
e64e739e
VS		 1263 /* check if we can do 8bpc */
1264 status = hdmi_port_clock_valid(hdmi, clock, true);
7d57382e 1265
e64e739e
VS		 1266 /* if we can't do 8bpc we may still be able to do 12bpc */
1267 if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK)
1268 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true);
7d57382e 1269
e64e739e 1270 return status;
7d57382e
EA		 1271}
1272
77f06c86 1273static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
71800632 1274{
77f06c86
ACO		 1275 struct drm_device *dev = crtc_state->base.crtc->dev;
1276 struct drm_atomic_state *state;
71800632 1277 struct intel_encoder *encoder;
da3ced29 1278 struct drm_connector *connector;
77f06c86 1279 struct drm_connector_state *connector_state;
71800632 1280 int count = 0, count_hdmi = 0;
77f06c86 1281 int i;
71800632 1282
f227ae9e 1283 if (HAS_GMCH_DISPLAY(dev))
71800632
VS		 1284 return false;
1285
77f06c86
ACO		 1286 state = crtc_state->base.state;
1287
da3ced29 1288 for_each_connector_in_state(state, connector, connector_state, i) {
77f06c86
ACO		 1289 if (connector_state->crtc != crtc_state->base.crtc)
1290 continue;
1291
1292 encoder = to_intel_encoder(connector_state->best_encoder);
1293
71800632
VS		 1294 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
1295 count++;
1296 }
1297
1298 /*
1299 * HDMI 12bpc affects the clocks, so it's only possible
1300 * when not cloning with other encoder types.
1301 */
1302 return count_hdmi > 0 && count_hdmi == count;
1303}
1304
5bfe2ac0 1305bool intel_hdmi_compute_config(struct intel_encoder *encoder,
5cec258b 1306 struct intel_crtc_state *pipe_config)
7d57382e 1307{
5bfe2ac0
DV		 1308 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1309 struct drm_device *dev = encoder->base.dev;
2d112de7 1310 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
e64e739e
VS		 1311 int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1312 int clock_12bpc = clock_8bpc * 3 / 2;
e29c22c0 1313 int desired_bpp;
3685a8f3 1314
6897b4b5
DV		 1315 pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
1316
e43823ec
JB		 1317 if (pipe_config->has_hdmi_sink)
1318 pipe_config->has_infoframe = true;
1319
55bc60db
VS		 1320 if (intel_hdmi->color_range_auto) {
1321 /* See CEA-861-E - 5.1 Default Encoding Parameters */
0f2a2a75
VS		 1322 pipe_config->limited_color_range =
1323 pipe_config->has_hdmi_sink &&
1324 drm_match_cea_mode(adjusted_mode) > 1;
1325 } else {
1326 pipe_config->limited_color_range =
1327 intel_hdmi->limited_color_range;
55bc60db
VS		 1328 }
1329
697c4078
CT		 1330 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1331 pipe_config->pixel_multiplier = 2;
e64e739e 1332 clock_8bpc *= 2;
3320e37f 1333 clock_12bpc *= 2;
697c4078
CT		 1334 }
1335
5bfe2ac0
DV		 1336 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
1337 pipe_config->has_pch_encoder = true;
1338
9ed109a7
DV		 1339 if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
1340 pipe_config->has_audio = true;
1341
4e53c2e0
DV		 1342 /*
1343 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1344 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
325b9d04
DV		 1345 * outputs. We also need to check that the higher clock still fits
1346 * within limits.
4e53c2e0 1347 */
6897b4b5 1348 if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
c578d152 1349 hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true) == MODE_OK &&
7a0baa62 1350 hdmi_12bpc_possible(pipe_config)) {
e29c22c0
DV		 1351 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1352 desired_bpp = 12*3;
325b9d04
DV		 1353
1354 /* Need to adjust the port link by 1.5x for 12bpc. */
ff9a6750 1355 pipe_config->port_clock = clock_12bpc;
4e53c2e0 1356 } else {
e29c22c0
DV		 1357 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1358 desired_bpp = 8*3;
e64e739e
VS		 1359
1360 pipe_config->port_clock = clock_8bpc;
e29c22c0
DV		 1361 }
1362
1363 if (!pipe_config->bw_constrained) {
1364 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
1365 pipe_config->pipe_bpp = desired_bpp;
4e53c2e0
DV		 1366 }
1367
e64e739e
VS		 1368 if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1369 false) != MODE_OK) {
1370 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
325b9d04
DV		 1371 return false;
1372 }
1373
28b468a0
VS		 1374 /* Set user selected PAR to incoming mode's member */
1375 adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
1376
2bae0304
ACO		 1377 pipe_config->lane_count = 4;
1378
7d57382e
EA		 1379 return true;
1380}
1381
953ece69
CW		 1382static void
1383intel_hdmi_unset_edid(struct drm_connector *connector)
9dff6af8 1384{
df0e9248 1385 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
9dff6af8 1386
953ece69
CW		 1387 intel_hdmi->has_hdmi_sink = false;
1388 intel_hdmi->has_audio = false;
1389 intel_hdmi->rgb_quant_range_selectable = false;
1390
c578d152
VS		 1391 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
1392 intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
1393
953ece69
CW		 1394 kfree(to_intel_connector(connector)->detect_edid);
1395 to_intel_connector(connector)->detect_edid = NULL;
1396}
1397
c578d152 1398static void
55d7f30e 1399intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
c578d152
VS		 1400{
1401 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1402 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
55d7f30e 1403 enum port port = hdmi_to_dig_port(hdmi)->port;
c578d152
VS		 1404 struct i2c_adapter *adapter =
1405 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1406 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
1407
55d7f30e
VS		 1408 /*
1409 * Type 1 DVI adaptors are not required to implement any
1410 * registers, so we can't always detect their presence.
1411 * Ideally we should be able to check the state of the
1412 * CONFIG1 pin, but no such luck on our hardware.
1413 *
1414 * The only method left to us is to check the VBT to see
1415 * if the port is a dual mode capable DP port. But let's
1416 * only do that when we sucesfully read the EDID, to avoid
1417 * confusing log messages about DP dual mode adaptors when
1418 * there's nothing connected to the port.
1419 */
1420 if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
1421 if (has_edid &&
1422 intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
1423 DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
1424 type = DRM_DP_DUAL_MODE_TYPE1_DVI;
1425 } else {
1426 type = DRM_DP_DUAL_MODE_NONE;
1427 }
1428 }
1429
1430 if (type == DRM_DP_DUAL_MODE_NONE)
c578d152
VS		 1431 return;
1432
1433 hdmi->dp_dual_mode.type = type;
1434 hdmi->dp_dual_mode.max_tmds_clock =
1435 drm_dp_dual_mode_max_tmds_clock(type, adapter);
1436
1437 DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
1438 drm_dp_get_dual_mode_type_name(type),
1439 hdmi->dp_dual_mode.max_tmds_clock);
1440}
1441
953ece69 1442static bool
237ed86c 1443intel_hdmi_set_edid(struct drm_connector *connector, bool force)
953ece69
CW		 1444{
1445 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1446 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
237ed86c 1447 struct edid *edid = NULL;
953ece69 1448 bool connected = false;
164c8598 1449
69172f21
ID		 1450 if (force) {
1451 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
671dedd2 1452
237ed86c
SJ		 1453 edid = drm_get_edid(connector,
1454 intel_gmbus_get_adapter(dev_priv,
1455 intel_hdmi->ddc_bus));
2ded9e27 1456
55d7f30e 1457 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
c578d152 1458
69172f21
ID		 1459 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1460 }
30ad48b7 1461
953ece69
CW		 1462 to_intel_connector(connector)->detect_edid = edid;
1463 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1464 intel_hdmi->rgb_quant_range_selectable =
1465 drm_rgb_quant_range_selectable(edid);
1466
1467 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
b1d7e4b4
WF		 1468 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1469 intel_hdmi->has_audio =
953ece69
CW		 1470 intel_hdmi->force_audio == HDMI_AUDIO_ON;
1471
1472 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
1473 intel_hdmi->has_hdmi_sink =
1474 drm_detect_hdmi_monitor(edid);
1475
1476 connected = true;
55b7d6e8
CW		 1477 }
1478
953ece69
CW		 1479 return connected;
1480}
1481
8166fcea
DV		 1482static enum drm_connector_status
1483intel_hdmi_detect(struct drm_connector *connector, bool force)
953ece69 1484{
8166fcea
DV		 1485 enum drm_connector_status status;
1486 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1487 struct drm_i915_private *dev_priv = to_i915(connector->dev);
237ed86c 1488 bool live_status = false;
61fb3980 1489 unsigned int try;
953ece69 1490
8166fcea
DV		 1491 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1492 connector->base.id, connector->name);
1493
29bb94bb
ID		 1494 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1495
f8d03ea0 1496 for (try = 0; !live_status && try < 9; try++) {
61fb3980
GW		 1497 if (try)
1498 msleep(10);
237ed86c
SJ		 1499 live_status = intel_digital_port_connected(dev_priv,
1500 hdmi_to_dig_port(intel_hdmi));
237ed86c
SJ		 1501 }
1502
4f4a8185
SS		 1503 if (!live_status) {
1504 DRM_DEBUG_KMS("HDMI live status down\n");
1505 /*
1506 * Live status register is not reliable on all intel platforms.
1507 * So consider live_status only for certain platforms, for
1508 * others, read EDID to determine presence of sink.
1509 */
1510 if (INTEL_INFO(dev_priv)->gen < 7 || IS_IVYBRIDGE(dev_priv))
1511 live_status = true;
1512 }
237ed86c 1513
8166fcea 1514 intel_hdmi_unset_edid(connector);
0b5e88dc 1515
8166fcea 1516 if (intel_hdmi_set_edid(connector, live_status)) {
953ece69
CW		 1517 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1518
1519 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1520 status = connector_status_connected;
8166fcea 1521 } else
953ece69 1522 status = connector_status_disconnected;
671dedd2 1523
29bb94bb
ID		 1524 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1525
2ded9e27 1526 return status;
7d57382e
EA		 1527}
1528
953ece69
CW		 1529static void
1530intel_hdmi_force(struct drm_connector *connector)
7d57382e 1531{
953ece69 1532 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
7d57382e 1533
953ece69
CW		 1534 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1535 connector->base.id, connector->name);
7d57382e 1536
953ece69 1537 intel_hdmi_unset_edid(connector);
671dedd2 1538
953ece69
CW		 1539 if (connector->status != connector_status_connected)
1540 return;
671dedd2 1541
237ed86c 1542 intel_hdmi_set_edid(connector, true);
953ece69
CW		 1543 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1544}
671dedd2 1545
953ece69
CW		 1546static int intel_hdmi_get_modes(struct drm_connector *connector)
1547{
1548 struct edid *edid;
1549
1550 edid = to_intel_connector(connector)->detect_edid;
1551 if (edid == NULL)
1552 return 0;
671dedd2 1553
953ece69 1554 return intel_connector_update_modes(connector, edid);
7d57382e
EA		 1555}
1556
1aad7ac0
CW		 1557static bool
1558intel_hdmi_detect_audio(struct drm_connector *connector)
1559{
1aad7ac0 1560 bool has_audio = false;
953ece69 1561 struct edid *edid;
1aad7ac0 1562
953ece69
CW		 1563 edid = to_intel_connector(connector)->detect_edid;
1564 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
1565 has_audio = drm_detect_monitor_audio(edid);
671dedd2 1566
1aad7ac0
CW		 1567 return has_audio;
1568}
1569
55b7d6e8
CW		 1570static int
1571intel_hdmi_set_property(struct drm_connector *connector,
ed517fbb
PZ		 1572 struct drm_property *property,
1573 uint64_t val)
55b7d6e8
CW		 1574{
1575 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
da63a9f2
PZ		 1576 struct intel_digital_port *intel_dig_port =
1577 hdmi_to_dig_port(intel_hdmi);
e953fd7b 1578 struct drm_i915_private *dev_priv = connector->dev->dev_private;
55b7d6e8
CW		 1579 int ret;
1580
662595df 1581 ret = drm_object_property_set_value(&connector->base, property, val);
55b7d6e8
CW		 1582 if (ret)
1583 return ret;
1584
3f43c48d 1585 if (property == dev_priv->force_audio_property) {
b1d7e4b4 1586 enum hdmi_force_audio i = val;
1aad7ac0
CW		 1587 bool has_audio;
1588
1589 if (i == intel_hdmi->force_audio)
55b7d6e8
CW		 1590 return 0;
1591
1aad7ac0 1592 intel_hdmi->force_audio = i;
55b7d6e8 1593
b1d7e4b4 1594 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 1595 has_audio = intel_hdmi_detect_audio(connector);
1596 else
b1d7e4b4 1597 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0 1598
b1d7e4b4
WF		 1599 if (i == HDMI_AUDIO_OFF_DVI)
1600 intel_hdmi->has_hdmi_sink = 0;
55b7d6e8 1601
1aad7ac0 1602 intel_hdmi->has_audio = has_audio;
55b7d6e8
CW		 1603 goto done;
1604 }
1605
e953fd7b 1606 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80 1607 bool old_auto = intel_hdmi->color_range_auto;
0f2a2a75 1608 bool old_range = intel_hdmi->limited_color_range;
ae4edb80 1609
55bc60db
VS		 1610 switch (val) {
1611 case INTEL_BROADCAST_RGB_AUTO:
1612 intel_hdmi->color_range_auto = true;
1613 break;
1614 case INTEL_BROADCAST_RGB_FULL:
1615 intel_hdmi->color_range_auto = false;
0f2a2a75 1616 intel_hdmi->limited_color_range = false;
55bc60db
VS		 1617 break;
1618 case INTEL_BROADCAST_RGB_LIMITED:
1619 intel_hdmi->color_range_auto = false;
0f2a2a75 1620 intel_hdmi->limited_color_range = true;
55bc60db
VS		 1621 break;
1622 default:
1623 return -EINVAL;
1624 }
ae4edb80
DV		 1625
1626 if (old_auto == intel_hdmi->color_range_auto &&
0f2a2a75 1627 old_range == intel_hdmi->limited_color_range)
ae4edb80
DV		 1628 return 0;
1629
e953fd7b
CW		 1630 goto done;
1631 }
1632
94a11ddc
VK		 1633 if (property == connector->dev->mode_config.aspect_ratio_property) {
1634 switch (val) {
1635 case DRM_MODE_PICTURE_ASPECT_NONE:
1636 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1637 break;
1638 case DRM_MODE_PICTURE_ASPECT_4_3:
1639 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
1640 break;
1641 case DRM_MODE_PICTURE_ASPECT_16_9:
1642 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
1643 break;
1644 default:
1645 return -EINVAL;
1646 }
1647 goto done;
1648 }
1649
55b7d6e8
CW		 1650 return -EINVAL;
1651
1652done:
c0c36b94
CW		 1653 if (intel_dig_port->base.base.crtc)
1654 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
55b7d6e8
CW		 1655
1656 return 0;
1657}
1658
13732ba7
JB		 1659static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1660{
1661 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1662 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
7c5f93b0 1663 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
13732ba7 1664
4cde8a21
DV		 1665 intel_hdmi_prepare(encoder);
1666
6897b4b5 1667 intel_hdmi->set_infoframes(&encoder->base,
6e3c9717 1668 intel_crtc->config->has_hdmi_sink,
6897b4b5 1669 adjusted_mode);
13732ba7
JB		 1670}
1671
9514ac6e 1672static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
89b667f8
JB		 1673{
1674 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
13732ba7 1675 struct intel_hdmi *intel_hdmi = &dport->hdmi;
89b667f8
JB		 1676 struct drm_device *dev = encoder->base.dev;
1677 struct drm_i915_private *dev_priv = dev->dev_private;
1678 struct intel_crtc *intel_crtc =
1679 to_intel_crtc(encoder->base.crtc);
7c5f93b0 1680 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
e4607fcf 1681 enum dpio_channel port = vlv_dport_to_channel(dport);
89b667f8
JB		 1682 int pipe = intel_crtc->pipe;
1683 u32 val;
1684
89b667f8 1685 /* Enable clock channels for this port */
a580516d 1686 mutex_lock(&dev_priv->sb_lock);
ab3c759a 1687 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
89b667f8
JB		 1688 val = 0;
1689 if (pipe)
1690 val |= (1<<21);
1691 else
1692 val &= ~(1<<21);
1693 val |= 0x001000c4;
ab3c759a 1694 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
89b667f8
JB		 1695
1696 /* HDMI 1.0V-2dB */
ab3c759a
CML		 1697 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1698 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1699 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1700 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1701 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1702 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1703 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1704 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
89b667f8
JB		 1705
1706 /* Program lane clock */
ab3c759a
CML		 1707 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1708 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
a580516d 1709 mutex_unlock(&dev_priv->sb_lock);
b76cf76b 1710
6897b4b5 1711 intel_hdmi->set_infoframes(&encoder->base,
6e3c9717 1712 intel_crtc->config->has_hdmi_sink,
6897b4b5 1713 adjusted_mode);
13732ba7 1714
bf868c7d 1715 g4x_enable_hdmi(encoder);
b76cf76b 1716
9b6de0a1 1717 vlv_wait_port_ready(dev_priv, dport, 0x0);
89b667f8
JB		 1718}
1719
9514ac6e 1720static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 1721{
1722 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1723 struct drm_device *dev = encoder->base.dev;
1724 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 1725 struct intel_crtc *intel_crtc =
1726 to_intel_crtc(encoder->base.crtc);
e4607fcf 1727 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 1728 int pipe = intel_crtc->pipe;
89b667f8 1729
4cde8a21
DV		 1730 intel_hdmi_prepare(encoder);
1731
89b667f8 1732 /* Program Tx lane resets to default */
a580516d 1733 mutex_lock(&dev_priv->sb_lock);
ab3c759a 1734 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 1735 DPIO_PCS_TX_LANE2_RESET |
1736 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 1737 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 1738 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1739 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1740 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1741 DPIO_PCS_CLK_SOFT_RESET);
1742
1743 /* Fix up inter-pair skew failure */
ab3c759a
CML		 1744 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1745 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1746 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1747
1748 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1749 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
a580516d 1750 mutex_unlock(&dev_priv->sb_lock);
89b667f8
JB		 1751}
1752
a8f327fb
VS		 1753static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
1754 bool reset)
1755{
1756 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1757 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1758 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1759 enum pipe pipe = crtc->pipe;
1760 uint32_t val;
1761
1762 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1763 if (reset)
1764 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1765 else
1766 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
1767 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1768
1769 if (crtc->config->lane_count > 2) {
1770 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1771 if (reset)
1772 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1773 else
1774 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
1775 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1776 }
1777
1778 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1779 val |= CHV_PCS_REQ_SOFTRESET_EN;
1780 if (reset)
1781 val &= ~DPIO_PCS_CLK_SOFT_RESET;
1782 else
1783 val |= DPIO_PCS_CLK_SOFT_RESET;
1784 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1785
1786 if (crtc->config->lane_count > 2) {
1787 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1788 val |= CHV_PCS_REQ_SOFTRESET_EN;
1789 if (reset)
1790 val &= ~DPIO_PCS_CLK_SOFT_RESET;
1791 else
1792 val |= DPIO_PCS_CLK_SOFT_RESET;
1793 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1794 }
1795}
1796
9197c88b
VS		 1797static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1798{
1799 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1800 struct drm_device *dev = encoder->base.dev;
1801 struct drm_i915_private *dev_priv = dev->dev_private;
1802 struct intel_crtc *intel_crtc =
1803 to_intel_crtc(encoder->base.crtc);
1804 enum dpio_channel ch = vlv_dport_to_channel(dport);
1805 enum pipe pipe = intel_crtc->pipe;
1806 u32 val;
1807
625695f8
VS		 1808 intel_hdmi_prepare(encoder);
1809
b0b33846
VS		 1810 /*
1811 * Must trick the second common lane into life.
1812 * Otherwise we can't even access the PLL.
1813 */
1814 if (ch == DPIO_CH0 && pipe == PIPE_B)
1815 dport->release_cl2_override =
1816 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
1817
e0fce78f
VS		 1818 chv_phy_powergate_lanes(encoder, true, 0x0);
1819
a580516d 1820 mutex_lock(&dev_priv->sb_lock);
9197c88b 1821
a8f327fb
VS		 1822 /* Assert data lane reset */
1823 chv_data_lane_soft_reset(encoder, true);
1824
b9e5ac3c
VS		 1825 /* program left/right clock distribution */
1826 if (pipe != PIPE_B) {
1827 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1828 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1829 if (ch == DPIO_CH0)
1830 val |= CHV_BUFLEFTENA1_FORCE;
1831 if (ch == DPIO_CH1)
1832 val |= CHV_BUFRIGHTENA1_FORCE;
1833 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1834 } else {
1835 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1836 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1837 if (ch == DPIO_CH0)
1838 val |= CHV_BUFLEFTENA2_FORCE;
1839 if (ch == DPIO_CH1)
1840 val |= CHV_BUFRIGHTENA2_FORCE;
1841 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1842 }
1843
9197c88b
VS		 1844 /* program clock channel usage */
1845 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
1846 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1847 if (pipe != PIPE_B)
1848 val &= ~CHV_PCS_USEDCLKCHANNEL;
1849 else
1850 val |= CHV_PCS_USEDCLKCHANNEL;
1851 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
1852
1853 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
1854 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1855 if (pipe != PIPE_B)
1856 val &= ~CHV_PCS_USEDCLKCHANNEL;
1857 else
1858 val |= CHV_PCS_USEDCLKCHANNEL;
1859 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
1860
1861 /*
1862 * This a a bit weird since generally CL
1863 * matches the pipe, but here we need to
1864 * pick the CL based on the port.
1865 */
1866 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
1867 if (pipe != PIPE_B)
1868 val &= ~CHV_CMN_USEDCLKCHANNEL;
1869 else
1870 val |= CHV_CMN_USEDCLKCHANNEL;
1871 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
1872
a580516d 1873 mutex_unlock(&dev_priv->sb_lock);
9197c88b
VS		 1874}
1875
d6db995f
VS		 1876static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)
1877{
1878 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1879 enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
1880 u32 val;
1881
1882 mutex_lock(&dev_priv->sb_lock);
1883
1884 /* disable left/right clock distribution */
1885 if (pipe != PIPE_B) {
1886 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1887 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1888 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1889 } else {
1890 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1891 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1892 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1893 }
1894
1895 mutex_unlock(&dev_priv->sb_lock);
e0fce78f 1896
b0b33846
VS		 1897 /*
1898 * Leave the power down bit cleared for at least one
1899 * lane so that chv_powergate_phy_ch() will power
1900 * on something when the channel is otherwise unused.
1901 * When the port is off and the override is removed
1902 * the lanes power down anyway, so otherwise it doesn't
1903 * really matter what the state of power down bits is
1904 * after this.
1905 */
e0fce78f 1906 chv_phy_powergate_lanes(encoder, false, 0x0);
d6db995f
VS		 1907}
1908
9514ac6e 1909static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
89b667f8
JB		 1910{
1911 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1912 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
5e69f97f
CML		 1913 struct intel_crtc *intel_crtc =
1914 to_intel_crtc(encoder->base.crtc);
e4607fcf 1915 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 1916 int pipe = intel_crtc->pipe;
89b667f8
JB		 1917
1918 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
a580516d 1919 mutex_lock(&dev_priv->sb_lock);
ab3c759a
CML		 1920 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1921 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
a580516d 1922 mutex_unlock(&dev_priv->sb_lock);
89b667f8
JB		 1923}
1924
580d3811
VS		 1925static void chv_hdmi_post_disable(struct intel_encoder *encoder)
1926{
580d3811
VS		 1927 struct drm_device *dev = encoder->base.dev;
1928 struct drm_i915_private *dev_priv = dev->dev_private;
580d3811 1929
a580516d 1930 mutex_lock(&dev_priv->sb_lock);
580d3811 1931
a8f327fb
VS		 1932 /* Assert data lane reset */
1933 chv_data_lane_soft_reset(encoder, true);
580d3811 1934
a580516d 1935 mutex_unlock(&dev_priv->sb_lock);
580d3811
VS		 1936}
1937
e4a1d846
CML		 1938static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1939{
1940 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
b4eb1564 1941 struct intel_hdmi *intel_hdmi = &dport->hdmi;
e4a1d846
CML		 1942 struct drm_device *dev = encoder->base.dev;
1943 struct drm_i915_private *dev_priv = dev->dev_private;
1944 struct intel_crtc *intel_crtc =
1945 to_intel_crtc(encoder->base.crtc);
7c5f93b0 1946 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
e4a1d846
CML		 1947 enum dpio_channel ch = vlv_dport_to_channel(dport);
1948 int pipe = intel_crtc->pipe;
2e523e98 1949 int data, i, stagger;
e4a1d846
CML		 1950 u32 val;
1951
a580516d 1952 mutex_lock(&dev_priv->sb_lock);
949c1d43 1953
570e2a74
VS		 1954 /* allow hardware to manage TX FIFO reset source */
1955 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1956 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1957 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1958
1959 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1960 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1961 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1962
949c1d43 1963 /* Program Tx latency optimal setting */
e4a1d846 1964 for (i = 0; i < 4; i++) {
e4a1d846
CML		 1965 /* Set the upar bit */
1966 data = (i == 1) ? 0x0 : 0x1;
1967 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
1968 data << DPIO_UPAR_SHIFT);
1969 }
1970
1971 /* Data lane stagger programming */
2e523e98
VS		 1972 if (intel_crtc->config->port_clock > 270000)
1973 stagger = 0x18;
1974 else if (intel_crtc->config->port_clock > 135000)
1975 stagger = 0xd;
1976 else if (intel_crtc->config->port_clock > 67500)
1977 stagger = 0x7;
1978 else if (intel_crtc->config->port_clock > 33750)
1979 stagger = 0x4;
1980 else
1981 stagger = 0x2;
1982
1983 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1984 val |= DPIO_TX2_STAGGER_MASK(0x1f);
1985 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1986
1987 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1988 val |= DPIO_TX2_STAGGER_MASK(0x1f);
1989 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1990
1991 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
1992 DPIO_LANESTAGGER_STRAP(stagger) |
1993 DPIO_LANESTAGGER_STRAP_OVRD |
1994 DPIO_TX1_STAGGER_MASK(0x1f) |
1995 DPIO_TX1_STAGGER_MULT(6) |
1996 DPIO_TX2_STAGGER_MULT(0));
1997
1998 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
1999 DPIO_LANESTAGGER_STRAP(stagger) |
2000 DPIO_LANESTAGGER_STRAP_OVRD |
2001 DPIO_TX1_STAGGER_MASK(0x1f) |
2002 DPIO_TX1_STAGGER_MULT(7) |
2003 DPIO_TX2_STAGGER_MULT(5));
e4a1d846 2004
a8f327fb
VS		 2005 /* Deassert data lane reset */
2006 chv_data_lane_soft_reset(encoder, false);
2007
e4a1d846 2008 /* Clear calc init */
1966e59e
VS		 2009 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2010 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 2011 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
2012 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e
VS		 2013 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2014
2015 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2016 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 2017 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
2018 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e 2019 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846 2020
a02ef3c7
VS		 2021 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
2022 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
2023 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
2024 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
2025
2026 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
2027 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
2028 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
2029 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
2030
e4a1d846
CML		 2031 /* FIXME: Program the support xxx V-dB */
2032 /* Use 800mV-0dB */
f72df8db
VS		 2033 for (i = 0; i < 4; i++) {
2034 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2035 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2036 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
2037 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2038 }
e4a1d846 2039
f72df8db
VS		 2040 for (i = 0; i < 4; i++) {
2041 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
67fa24b4 2042
1fb44505
VS		 2043 val &= ~DPIO_SWING_MARGIN000_MASK;
2044 val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
67fa24b4
VS		 2045
2046 /*
2047 * Supposedly this value shouldn't matter when unique transition
2048 * scale is disabled, but in fact it does matter. Let's just
2049 * always program the same value and hope it's OK.
2050 */
2051 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2052 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
2053
f72df8db
VS		 2054 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2055 }
e4a1d846 2056
67fa24b4
VS		 2057 /*
2058 * The document said it needs to set bit 27 for ch0 and bit 26
2059 * for ch1. Might be a typo in the doc.
2060 * For now, for this unique transition scale selection, set bit
2061 * 27 for ch0 and ch1.
2062 */
f72df8db
VS		 2063 for (i = 0; i < 4; i++) {
2064 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2065 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2066 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2067 }
e4a1d846 2068
e4a1d846 2069 /* Start swing calculation */
1966e59e
VS		 2070 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2071 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2072 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2073
2074 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2075 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2076 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846 2077
a580516d 2078 mutex_unlock(&dev_priv->sb_lock);
e4a1d846 2079
b4eb1564 2080 intel_hdmi->set_infoframes(&encoder->base,
6e3c9717 2081 intel_crtc->config->has_hdmi_sink,
b4eb1564
CT		 2082 adjusted_mode);
2083
bf868c7d 2084 g4x_enable_hdmi(encoder);
e4a1d846 2085
9b6de0a1 2086 vlv_wait_port_ready(dev_priv, dport, 0x0);
b0b33846
VS		 2087
2088 /* Second common lane will stay alive on its own now */
2089 if (dport->release_cl2_override) {
2090 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
2091 dport->release_cl2_override = false;
2092 }
e4a1d846
CML		 2093}
2094
7d57382e
EA		 2095static void intel_hdmi_destroy(struct drm_connector *connector)
2096{
10e972d3 2097 kfree(to_intel_connector(connector)->detect_edid);
7d57382e 2098 drm_connector_cleanup(connector);
674e2d08 2099 kfree(connector);
7d57382e
EA		 2100}
2101
7d57382e 2102static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
4d688a2a 2103 .dpms = drm_atomic_helper_connector_dpms,
7d57382e 2104 .detect = intel_hdmi_detect,
953ece69 2105 .force = intel_hdmi_force,
7d57382e 2106 .fill_modes = drm_helper_probe_single_connector_modes,
55b7d6e8 2107 .set_property = intel_hdmi_set_property,
2545e4a6 2108 .atomic_get_property = intel_connector_atomic_get_property,
7d57382e 2109 .destroy = intel_hdmi_destroy,
c6f95f27 2110 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
98969725 2111 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
7d57382e
EA		 2112};
2113
2114static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2115 .get_modes = intel_hdmi_get_modes,
2116 .mode_valid = intel_hdmi_mode_valid,
df0e9248 2117 .best_encoder = intel_best_encoder,
7d57382e
EA		 2118};
2119
7d57382e 2120static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
ea5b213a 2121 .destroy = intel_encoder_destroy,
7d57382e
EA		 2122};
2123
55b7d6e8
CW		 2124static void
2125intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2126{
3f43c48d 2127 intel_attach_force_audio_property(connector);
e953fd7b 2128 intel_attach_broadcast_rgb_property(connector);
55bc60db 2129 intel_hdmi->color_range_auto = true;
94a11ddc
VK		 2130 intel_attach_aspect_ratio_property(connector);
2131 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
55b7d6e8
CW		 2132}
2133
00c09d70
PZ		 2134void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2135 struct intel_connector *intel_connector)
7d57382e 2136{
b9cb234c
PZ		 2137 struct drm_connector *connector = &intel_connector->base;
2138 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2139 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2140 struct drm_device *dev = intel_encoder->base.dev;
7d57382e 2141 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2142 enum port port = intel_dig_port->port;
11c1b657 2143 uint8_t alternate_ddc_pin;
373a3cf7 2144
a5aac5ab
VS		 2145 DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
2146 port_name(port));
2147
ccb1a831
VS		 2148 if (WARN(intel_dig_port->max_lanes < 4,
2149 "Not enough lanes (%d) for HDMI on port %c\n",
2150 intel_dig_port->max_lanes, port_name(port)))
2151 return;
2152
7d57382e 2153 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
8d91104a 2154 DRM_MODE_CONNECTOR_HDMIA);
7d57382e
EA		 2155 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2156
c3febcc4 2157 connector->interlace_allowed = 1;
7d57382e 2158 connector->doublescan_allowed = 0;
573e74ad 2159 connector->stereo_allowed = 1;
66a9278e 2160
08d644ad
DV		 2161 switch (port) {
2162 case PORT_B:
4c272834
JN		 2163 if (IS_BROXTON(dev_priv))
2164 intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT;
2165 else
2166 intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
cf1d5883
SJ		 2167 /*
2168 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
2169 * interrupts to check the external panel connection.
2170 */
e87a005d 2171 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
cf1d5883
SJ		 2172 intel_encoder->hpd_pin = HPD_PORT_A;
2173 else
2174 intel_encoder->hpd_pin = HPD_PORT_B;
08d644ad
DV		 2175 break;
2176 case PORT_C:
4c272834
JN		 2177 if (IS_BROXTON(dev_priv))
2178 intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT;
2179 else
2180 intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
1d843f9d 2181 intel_encoder->hpd_pin = HPD_PORT_C;
08d644ad
DV		 2182 break;
2183 case PORT_D:
4c272834
JN		 2184 if (WARN_ON(IS_BROXTON(dev_priv)))
2185 intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED;
2186 else if (IS_CHERRYVIEW(dev_priv))
988c7015 2187 intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV;
c0c35329 2188 else
988c7015 2189 intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
1d843f9d 2190 intel_encoder->hpd_pin = HPD_PORT_D;
08d644ad 2191 break;
11c1b657
XZ		 2192 case PORT_E:
2193 /* On SKL PORT E doesn't have seperate GMBUS pin
2194 * We rely on VBT to set a proper alternate GMBUS pin. */
2195 alternate_ddc_pin =
2196 dev_priv->vbt.ddi_port_info[PORT_E].alternate_ddc_pin;
2197 switch (alternate_ddc_pin) {
2198 case DDC_PIN_B:
2199 intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
2200 break;
2201 case DDC_PIN_C:
2202 intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
2203 break;
2204 case DDC_PIN_D:
2205 intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
2206 break;
2207 default:
2208 MISSING_CASE(alternate_ddc_pin);
2209 }
2210 intel_encoder->hpd_pin = HPD_PORT_E;
2211 break;
08d644ad 2212 case PORT_A:
1d843f9d 2213 intel_encoder->hpd_pin = HPD_PORT_A;
08d644ad
DV		 2214 /* Internal port only for eDP. */
2215 default:
6e4c1677 2216 BUG();
f8aed700 2217 }
7d57382e 2218
666a4537 2219 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
90b107c8 2220 intel_hdmi->write_infoframe = vlv_write_infoframe;
687f4d06 2221 intel_hdmi->set_infoframes = vlv_set_infoframes;
e43823ec 2222 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
b98856a8 2223 } else if (IS_G4X(dev)) {
7637bfdb
JB		 2224 intel_hdmi->write_infoframe = g4x_write_infoframe;
2225 intel_hdmi->set_infoframes = g4x_set_infoframes;
e43823ec 2226 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
22b8bf17 2227 } else if (HAS_DDI(dev)) {
8c5f5f7c 2228 intel_hdmi->write_infoframe = hsw_write_infoframe;
687f4d06 2229 intel_hdmi->set_infoframes = hsw_set_infoframes;
e43823ec 2230 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
fdf1250a
PZ		 2231 } else if (HAS_PCH_IBX(dev)) {
2232 intel_hdmi->write_infoframe = ibx_write_infoframe;
687f4d06 2233 intel_hdmi->set_infoframes = ibx_set_infoframes;
e43823ec 2234 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
fdf1250a
PZ		 2235 } else {
2236 intel_hdmi->write_infoframe = cpt_write_infoframe;
687f4d06 2237 intel_hdmi->set_infoframes = cpt_set_infoframes;
e43823ec 2238 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
64a8fc01 2239 }
45187ace 2240
affa9354 2241 if (HAS_DDI(dev))
bcbc889b
PZ		 2242 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2243 else
2244 intel_connector->get_hw_state = intel_connector_get_hw_state;
4932e2c3 2245 intel_connector->unregister = intel_connector_unregister;
b9cb234c
PZ		 2246
2247 intel_hdmi_add_properties(intel_hdmi, connector);
2248
2249 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 2250 drm_connector_register(connector);
d8b4c43a 2251 intel_hdmi->attached_connector = intel_connector;
b9cb234c
PZ		 2252
2253 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2254 * 0xd. Failure to do so will result in spurious interrupts being
2255 * generated on the port when a cable is not attached.
2256 */
2257 if (IS_G4X(dev) && !IS_GM45(dev)) {
2258 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2259 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2260 }
2261}
2262
f0f59a00
VS		 2263void intel_hdmi_init(struct drm_device *dev,
2264 i915_reg_t hdmi_reg, enum port port)
b9cb234c
PZ		 2265{
2266 struct intel_digital_port *intel_dig_port;
2267 struct intel_encoder *intel_encoder;
b9cb234c
PZ		 2268 struct intel_connector *intel_connector;
2269
b14c5679 2270 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
b9cb234c
PZ		 2271 if (!intel_dig_port)
2272 return;
2273
08d9bc92 2274 intel_connector = intel_connector_alloc();
b9cb234c
PZ		 2275 if (!intel_connector) {
2276 kfree(intel_dig_port);
2277 return;
2278 }
2279
2280 intel_encoder = &intel_dig_port->base;
b9cb234c
PZ		 2281
2282 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
13a3d91f 2283 DRM_MODE_ENCODER_TMDS, NULL);
00c09d70 2284
5bfe2ac0 2285 intel_encoder->compute_config = intel_hdmi_compute_config;
a4790cec
VS		 2286 if (HAS_PCH_SPLIT(dev)) {
2287 intel_encoder->disable = pch_disable_hdmi;
2288 intel_encoder->post_disable = pch_post_disable_hdmi;
2289 } else {
2290 intel_encoder->disable = g4x_disable_hdmi;
2291 }
00c09d70 2292 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
045ac3b5 2293 intel_encoder->get_config = intel_hdmi_get_config;
e4a1d846 2294 if (IS_CHERRYVIEW(dev)) {
9197c88b 2295 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
e4a1d846
CML		 2296 intel_encoder->pre_enable = chv_hdmi_pre_enable;
2297 intel_encoder->enable = vlv_enable_hdmi;
580d3811 2298 intel_encoder->post_disable = chv_hdmi_post_disable;
d6db995f 2299 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
e4a1d846 2300 } else if (IS_VALLEYVIEW(dev)) {
9514ac6e
CML		 2301 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2302 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
b76cf76b 2303 intel_encoder->enable = vlv_enable_hdmi;
9514ac6e 2304 intel_encoder->post_disable = vlv_hdmi_post_disable;
b76cf76b 2305 } else {
13732ba7 2306 intel_encoder->pre_enable = intel_hdmi_pre_enable;
d1b1589c
VS		 2307 if (HAS_PCH_CPT(dev))
2308 intel_encoder->enable = cpt_enable_hdmi;
bf868c7d
VS		 2309 else if (HAS_PCH_IBX(dev))
2310 intel_encoder->enable = ibx_enable_hdmi;
d1b1589c 2311 else
bf868c7d 2312 intel_encoder->enable = g4x_enable_hdmi;
89b667f8 2313 }
5ab432ef 2314
b9cb234c 2315 intel_encoder->type = INTEL_OUTPUT_HDMI;
882ec384
VS		 2316 if (IS_CHERRYVIEW(dev)) {
2317 if (port == PORT_D)
2318 intel_encoder->crtc_mask = 1 << 2;
2319 else
2320 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2321 } else {
2322 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2323 }
301ea74a 2324 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
c6f1495d
VS		 2325 /*
2326 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2327 * to work on real hardware. And since g4x can send infoframes to
2328 * only one port anyway, nothing is lost by allowing it.
2329 */
2330 if (IS_G4X(dev))
2331 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
7d57382e 2332
174edf1f 2333 intel_dig_port->port = port;
b242b7f7 2334 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
f0f59a00 2335 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
ccb1a831 2336 intel_dig_port->max_lanes = 4;
55b7d6e8 2337
b9cb234c 2338 intel_hdmi_init_connector(intel_dig_port, intel_connector);
7d57382e 2339}
Linux 6.x block layer and io_uring tree(s)