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33a732f4 AD |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Vinit Azad <vinit.azad@intel.com> | |
25 | * Ben Widawsky <ben@bwidawsk.net> | |
26 | * Dave Gordon <david.s.gordon@intel.com> | |
27 | * Alex Dai <yu.dai@intel.com> | |
28 | */ | |
29 | #include <linux/firmware.h> | |
30 | #include "i915_drv.h" | |
31 | #include "intel_guc.h" | |
32 | ||
33 | /** | |
34 | * DOC: GuC | |
35 | * | |
36 | * intel_guc: | |
37 | * Top level structure of guc. It handles firmware loading and manages client | |
38 | * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy | |
39 | * ExecList submission. | |
40 | * | |
41 | * Firmware versioning: | |
42 | * The firmware build process will generate a version header file with major and | |
43 | * minor version defined. The versions are built into CSS header of firmware. | |
44 | * i915 kernel driver set the minimal firmware version required per platform. | |
45 | * The firmware installation package will install (symbolic link) proper version | |
46 | * of firmware. | |
47 | * | |
48 | * GuC address space: | |
49 | * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP), | |
50 | * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is | |
51 | * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects | |
52 | * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM. | |
53 | * | |
54 | * Firmware log: | |
55 | * Firmware log is enabled by setting i915.guc_log_level to non-negative level. | |
56 | * Log data is printed out via reading debugfs i915_guc_log_dump. Reading from | |
57 | * i915_guc_load_status will print out firmware loading status and scratch | |
58 | * registers value. | |
59 | * | |
60 | */ | |
61 | ||
aa557ab0 | 62 | #define I915_SKL_GUC_UCODE "i915/skl_guc_ver4.bin" |
33a732f4 AD |
63 | MODULE_FIRMWARE(I915_SKL_GUC_UCODE); |
64 | ||
65 | /* User-friendly representation of an enum */ | |
66 | const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status) | |
67 | { | |
68 | switch (status) { | |
69 | case GUC_FIRMWARE_FAIL: | |
70 | return "FAIL"; | |
71 | case GUC_FIRMWARE_NONE: | |
72 | return "NONE"; | |
73 | case GUC_FIRMWARE_PENDING: | |
74 | return "PENDING"; | |
75 | case GUC_FIRMWARE_SUCCESS: | |
76 | return "SUCCESS"; | |
77 | default: | |
78 | return "UNKNOWN!"; | |
79 | } | |
80 | }; | |
81 | ||
4df001d3 DG |
82 | static void direct_interrupts_to_host(struct drm_i915_private *dev_priv) |
83 | { | |
84 | struct intel_engine_cs *ring; | |
85 | int i, irqs; | |
86 | ||
87 | /* tell all command streamers NOT to forward interrupts and vblank to GuC */ | |
88 | irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER); | |
89 | irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING); | |
90 | for_each_ring(ring, dev_priv, i) | |
91 | I915_WRITE(RING_MODE_GEN7(ring), irqs); | |
92 | ||
4df001d3 DG |
93 | /* route all GT interrupts to the host */ |
94 | I915_WRITE(GUC_BCS_RCS_IER, 0); | |
95 | I915_WRITE(GUC_VCS2_VCS1_IER, 0); | |
96 | I915_WRITE(GUC_WD_VECS_IER, 0); | |
97 | } | |
98 | ||
99 | static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv) | |
100 | { | |
101 | struct intel_engine_cs *ring; | |
102 | int i, irqs; | |
103 | ||
104 | /* tell all command streamers to forward interrupts and vblank to GuC */ | |
105 | irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_ALWAYS); | |
106 | irqs |= _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING); | |
107 | for_each_ring(ring, dev_priv, i) | |
108 | I915_WRITE(RING_MODE_GEN7(ring), irqs); | |
109 | ||
4df001d3 DG |
110 | /* route USER_INTERRUPT to Host, all others are sent to GuC. */ |
111 | irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | | |
112 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
113 | /* These three registers have the same bit definitions */ | |
114 | I915_WRITE(GUC_BCS_RCS_IER, ~irqs); | |
115 | I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs); | |
116 | I915_WRITE(GUC_WD_VECS_IER, ~irqs); | |
117 | } | |
118 | ||
33a732f4 AD |
119 | static u32 get_gttype(struct drm_i915_private *dev_priv) |
120 | { | |
121 | /* XXX: GT type based on PCI device ID? field seems unused by fw */ | |
122 | return 0; | |
123 | } | |
124 | ||
125 | static u32 get_core_family(struct drm_i915_private *dev_priv) | |
126 | { | |
127 | switch (INTEL_INFO(dev_priv)->gen) { | |
128 | case 9: | |
129 | return GFXCORE_FAMILY_GEN9; | |
130 | ||
131 | default: | |
132 | DRM_ERROR("GUC: unsupported core family\n"); | |
133 | return GFXCORE_FAMILY_UNKNOWN; | |
134 | } | |
135 | } | |
136 | ||
137 | static void set_guc_init_params(struct drm_i915_private *dev_priv) | |
138 | { | |
139 | struct intel_guc *guc = &dev_priv->guc; | |
140 | u32 params[GUC_CTL_MAX_DWORDS]; | |
141 | int i; | |
142 | ||
143 | memset(¶ms, 0, sizeof(params)); | |
144 | ||
145 | params[GUC_CTL_DEVICE_INFO] |= | |
146 | (get_gttype(dev_priv) << GUC_CTL_GTTYPE_SHIFT) | | |
147 | (get_core_family(dev_priv) << GUC_CTL_COREFAMILY_SHIFT); | |
148 | ||
149 | /* | |
150 | * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one | |
151 | * second. This ARAR is calculated by: | |
152 | * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10 | |
153 | */ | |
154 | params[GUC_CTL_ARAT_HIGH] = 0; | |
155 | params[GUC_CTL_ARAT_LOW] = 100000000; | |
156 | ||
157 | params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER; | |
158 | ||
159 | params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER | | |
160 | GUC_CTL_VCS2_ENABLED; | |
161 | ||
162 | if (i915.guc_log_level >= 0) { | |
163 | params[GUC_CTL_LOG_PARAMS] = guc->log_flags; | |
164 | params[GUC_CTL_DEBUG] = | |
165 | i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT; | |
166 | } | |
167 | ||
bac427f8 AD |
168 | /* If GuC submission is enabled, set up additional parameters here */ |
169 | if (i915.enable_guc_submission) { | |
170 | u32 pgs = i915_gem_obj_ggtt_offset(dev_priv->guc.ctx_pool_obj); | |
171 | u32 ctx_in_16 = GUC_MAX_GPU_CONTEXTS / 16; | |
172 | ||
173 | pgs >>= PAGE_SHIFT; | |
174 | params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) | | |
175 | (ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT); | |
176 | ||
177 | params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS; | |
178 | ||
179 | /* Unmask this bit to enable the GuC's internal scheduler */ | |
180 | params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER; | |
181 | } | |
182 | ||
33a732f4 AD |
183 | I915_WRITE(SOFT_SCRATCH(0), 0); |
184 | ||
185 | for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) | |
186 | I915_WRITE(SOFT_SCRATCH(1 + i), params[i]); | |
187 | } | |
188 | ||
189 | /* | |
190 | * Read the GuC status register (GUC_STATUS) and store it in the | |
191 | * specified location; then return a boolean indicating whether | |
192 | * the value matches either of two values representing completion | |
193 | * of the GuC boot process. | |
194 | * | |
195 | * This is used for polling the GuC status in a wait_for_atomic() | |
196 | * loop below. | |
197 | */ | |
198 | static inline bool guc_ucode_response(struct drm_i915_private *dev_priv, | |
199 | u32 *status) | |
200 | { | |
201 | u32 val = I915_READ(GUC_STATUS); | |
0d44d3fa | 202 | u32 uk_val = val & GS_UKERNEL_MASK; |
33a732f4 | 203 | *status = val; |
0d44d3fa AD |
204 | return (uk_val == GS_UKERNEL_READY || |
205 | ((val & GS_MIA_CORE_STATE) && uk_val == GS_UKERNEL_LAPIC_DONE)); | |
33a732f4 AD |
206 | } |
207 | ||
208 | /* | |
209 | * Transfer the firmware image to RAM for execution by the microcontroller. | |
210 | * | |
211 | * GuC Firmware layout: | |
212 | * +-------------------------------+ ---- | |
213 | * | CSS header | 128B | |
214 | * | contains major/minor version | | |
215 | * +-------------------------------+ ---- | |
216 | * | uCode | | |
217 | * +-------------------------------+ ---- | |
218 | * | RSA signature | 256B | |
219 | * +-------------------------------+ ---- | |
33a732f4 AD |
220 | * |
221 | * Architecturally, the DMA engine is bidirectional, and can potentially even | |
222 | * transfer between GTT locations. This functionality is left out of the API | |
223 | * for now as there is no need for it. | |
224 | * | |
225 | * Note that GuC needs the CSS header plus uKernel code to be copied by the | |
226 | * DMA engine in one operation, whereas the RSA signature is loaded via MMIO. | |
227 | */ | |
228 | ||
229 | #define UOS_CSS_HEADER_OFFSET 0 | |
230 | #define UOS_VER_MINOR_OFFSET 0x44 | |
231 | #define UOS_VER_MAJOR_OFFSET 0x46 | |
232 | #define UOS_CSS_HEADER_SIZE 0x80 | |
233 | #define UOS_RSA_SIG_SIZE 0x100 | |
33a732f4 AD |
234 | |
235 | static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv) | |
236 | { | |
237 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; | |
238 | struct drm_i915_gem_object *fw_obj = guc_fw->guc_fw_obj; | |
239 | unsigned long offset; | |
240 | struct sg_table *sg = fw_obj->pages; | |
241 | u32 status, ucode_size, rsa[UOS_RSA_SIG_SIZE / sizeof(u32)]; | |
242 | int i, ret = 0; | |
243 | ||
244 | /* uCode size, also is where RSA signature starts */ | |
aa557ab0 | 245 | offset = ucode_size = guc_fw->guc_fw_size - UOS_RSA_SIG_SIZE; |
33a732f4 AD |
246 | I915_WRITE(DMA_COPY_SIZE, ucode_size); |
247 | ||
248 | /* Copy RSA signature from the fw image to HW for verification */ | |
249 | sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, UOS_RSA_SIG_SIZE, offset); | |
250 | for (i = 0; i < UOS_RSA_SIG_SIZE / sizeof(u32); i++) | |
ab9cc558 | 251 | I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]); |
33a732f4 AD |
252 | |
253 | /* Set the source address for the new blob */ | |
254 | offset = i915_gem_obj_ggtt_offset(fw_obj); | |
255 | I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset)); | |
256 | I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF); | |
257 | ||
258 | /* | |
259 | * Set the DMA destination. Current uCode expects the code to be | |
260 | * loaded at 8k; locations below this are used for the stack. | |
261 | */ | |
262 | I915_WRITE(DMA_ADDR_1_LOW, 0x2000); | |
263 | I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM); | |
264 | ||
265 | /* Finally start the DMA */ | |
266 | I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA)); | |
267 | ||
268 | /* | |
269 | * Spin-wait for the DMA to complete & the GuC to start up. | |
270 | * NB: Docs recommend not using the interrupt for completion. | |
271 | * Measurements indicate this should take no more than 20ms, so a | |
272 | * timeout here indicates that the GuC has failed and is unusable. | |
273 | * (Higher levels of the driver will attempt to fall back to | |
274 | * execlist mode if this happens.) | |
275 | */ | |
276 | ret = wait_for_atomic(guc_ucode_response(dev_priv, &status), 100); | |
277 | ||
278 | DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n", | |
279 | I915_READ(DMA_CTRL), status); | |
280 | ||
281 | if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) { | |
282 | DRM_ERROR("GuC firmware signature verification failed\n"); | |
283 | ret = -ENOEXEC; | |
284 | } | |
285 | ||
286 | DRM_DEBUG_DRIVER("returning %d\n", ret); | |
287 | ||
288 | return ret; | |
289 | } | |
290 | ||
291 | /* | |
292 | * Load the GuC firmware blob into the MinuteIA. | |
293 | */ | |
294 | static int guc_ucode_xfer(struct drm_i915_private *dev_priv) | |
295 | { | |
296 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; | |
297 | struct drm_device *dev = dev_priv->dev; | |
298 | int ret; | |
299 | ||
300 | ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false); | |
301 | if (ret) { | |
302 | DRM_DEBUG_DRIVER("set-domain failed %d\n", ret); | |
303 | return ret; | |
304 | } | |
305 | ||
306 | ret = i915_gem_obj_ggtt_pin(guc_fw->guc_fw_obj, 0, 0); | |
307 | if (ret) { | |
308 | DRM_DEBUG_DRIVER("pin failed %d\n", ret); | |
309 | return ret; | |
310 | } | |
311 | ||
312 | /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ | |
313 | I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); | |
314 | ||
315 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
316 | ||
317 | /* init WOPCM */ | |
318 | I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE); | |
319 | I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE); | |
320 | ||
321 | /* Enable MIA caching. GuC clock gating is disabled. */ | |
322 | I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE); | |
323 | ||
b970b486 NH |
324 | /* WaDisableMinuteIaClockGating:skl,bxt */ |
325 | if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) || | |
326 | (IS_BROXTON(dev) && INTEL_REVID(dev) == BXT_REVID_A0)) { | |
327 | I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) & | |
328 | ~GUC_ENABLE_MIA_CLOCK_GATING)); | |
329 | } | |
330 | ||
33a732f4 AD |
331 | /* WaC6DisallowByGfxPause*/ |
332 | I915_WRITE(GEN6_GFXPAUSE, 0x30FFF); | |
333 | ||
334 | if (IS_BROXTON(dev)) | |
335 | I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE); | |
336 | else | |
337 | I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE); | |
338 | ||
339 | if (IS_GEN9(dev)) { | |
340 | /* DOP Clock Gating Enable for GuC clocks */ | |
341 | I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE | | |
342 | I915_READ(GEN7_MISCCPCTL))); | |
343 | ||
344 | /* allows for 5us before GT can go to RC6 */ | |
345 | I915_WRITE(GUC_ARAT_C6DIS, 0x1FF); | |
346 | } | |
347 | ||
348 | set_guc_init_params(dev_priv); | |
349 | ||
350 | ret = guc_ucode_xfer_dma(dev_priv); | |
351 | ||
352 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
353 | ||
354 | /* | |
355 | * We keep the object pages for reuse during resume. But we can unpin it | |
356 | * now that DMA has completed, so it doesn't continue to take up space. | |
357 | */ | |
358 | i915_gem_object_ggtt_unpin(guc_fw->guc_fw_obj); | |
359 | ||
360 | return ret; | |
361 | } | |
362 | ||
363 | /** | |
364 | * intel_guc_ucode_load() - load GuC uCode into the device | |
365 | * @dev: drm device | |
366 | * | |
367 | * Called from gem_init_hw() during driver loading and also after a GPU reset. | |
368 | * | |
369 | * The firmware image should have already been fetched into memory by the | |
370 | * earlier call to intel_guc_ucode_init(), so here we need only check that | |
371 | * is succeeded, and then transfer the image to the h/w. | |
372 | * | |
373 | * Return: non-zero code on error | |
374 | */ | |
375 | int intel_guc_ucode_load(struct drm_device *dev) | |
376 | { | |
377 | struct drm_i915_private *dev_priv = dev->dev_private; | |
378 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; | |
379 | int err = 0; | |
380 | ||
381 | DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n", | |
382 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status), | |
383 | intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); | |
384 | ||
4df001d3 | 385 | direct_interrupts_to_host(dev_priv); |
44a28b1d | 386 | |
33a732f4 AD |
387 | if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_NONE) |
388 | return 0; | |
389 | ||
390 | if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_SUCCESS && | |
391 | guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL) | |
392 | return -ENOEXEC; | |
393 | ||
394 | guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING; | |
395 | ||
396 | DRM_DEBUG_DRIVER("GuC fw fetch status %s\n", | |
397 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status)); | |
398 | ||
399 | switch (guc_fw->guc_fw_fetch_status) { | |
400 | case GUC_FIRMWARE_FAIL: | |
401 | /* something went wrong :( */ | |
402 | err = -EIO; | |
403 | goto fail; | |
404 | ||
405 | case GUC_FIRMWARE_NONE: | |
406 | case GUC_FIRMWARE_PENDING: | |
407 | default: | |
408 | /* "can't happen" */ | |
409 | WARN_ONCE(1, "GuC fw %s invalid guc_fw_fetch_status %s [%d]\n", | |
410 | guc_fw->guc_fw_path, | |
411 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status), | |
412 | guc_fw->guc_fw_fetch_status); | |
413 | err = -ENXIO; | |
414 | goto fail; | |
415 | ||
416 | case GUC_FIRMWARE_SUCCESS: | |
417 | break; | |
418 | } | |
419 | ||
bac427f8 AD |
420 | err = i915_guc_submission_init(dev); |
421 | if (err) | |
422 | goto fail; | |
423 | ||
33a732f4 AD |
424 | err = guc_ucode_xfer(dev_priv); |
425 | if (err) | |
426 | goto fail; | |
427 | ||
428 | guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS; | |
429 | ||
430 | DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n", | |
431 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status), | |
432 | intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); | |
433 | ||
44a28b1d | 434 | if (i915.enable_guc_submission) { |
a1c41994 AD |
435 | /* The execbuf_client will be recreated. Release it first. */ |
436 | i915_guc_submission_disable(dev); | |
437 | ||
44a28b1d DG |
438 | err = i915_guc_submission_enable(dev); |
439 | if (err) | |
440 | goto fail; | |
4df001d3 | 441 | direct_interrupts_to_guc(dev_priv); |
44a28b1d DG |
442 | } |
443 | ||
33a732f4 AD |
444 | return 0; |
445 | ||
446 | fail: | |
447 | if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING) | |
448 | guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL; | |
449 | ||
4df001d3 | 450 | direct_interrupts_to_host(dev_priv); |
44a28b1d DG |
451 | i915_guc_submission_disable(dev); |
452 | ||
33a732f4 AD |
453 | return err; |
454 | } | |
455 | ||
456 | static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw) | |
457 | { | |
458 | struct drm_i915_gem_object *obj; | |
459 | const struct firmware *fw; | |
460 | const u8 *css_header; | |
aa557ab0 AD |
461 | const size_t minsize = UOS_CSS_HEADER_SIZE + UOS_RSA_SIG_SIZE; |
462 | const size_t maxsize = GUC_WOPCM_SIZE_VALUE + UOS_RSA_SIG_SIZE | |
33a732f4 AD |
463 | - 0x8000; /* 32k reserved (8K stack + 24k context) */ |
464 | int err; | |
465 | ||
466 | DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n", | |
467 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status)); | |
468 | ||
469 | err = request_firmware(&fw, guc_fw->guc_fw_path, &dev->pdev->dev); | |
470 | if (err) | |
471 | goto fail; | |
472 | if (!fw) | |
473 | goto fail; | |
474 | ||
475 | DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n", | |
476 | guc_fw->guc_fw_path, fw); | |
477 | DRM_DEBUG_DRIVER("firmware file size %zu (minimum %zu, maximum %zu)\n", | |
478 | fw->size, minsize, maxsize); | |
479 | ||
480 | /* Check the size of the blob befoe examining buffer contents */ | |
481 | if (fw->size < minsize || fw->size > maxsize) | |
482 | goto fail; | |
483 | ||
484 | /* | |
485 | * The GuC firmware image has the version number embedded at a well-known | |
486 | * offset within the firmware blob; note that major / minor version are | |
487 | * TWO bytes each (i.e. u16), although all pointers and offsets are defined | |
488 | * in terms of bytes (u8). | |
489 | */ | |
490 | css_header = fw->data + UOS_CSS_HEADER_OFFSET; | |
491 | guc_fw->guc_fw_major_found = *(u16 *)(css_header + UOS_VER_MAJOR_OFFSET); | |
492 | guc_fw->guc_fw_minor_found = *(u16 *)(css_header + UOS_VER_MINOR_OFFSET); | |
493 | ||
494 | if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted || | |
495 | guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) { | |
496 | DRM_ERROR("GuC firmware version %d.%d, required %d.%d\n", | |
497 | guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found, | |
498 | guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted); | |
499 | err = -ENOEXEC; | |
500 | goto fail; | |
501 | } | |
502 | ||
503 | DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n", | |
504 | guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found, | |
505 | guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted); | |
506 | ||
bf248ca1 | 507 | mutex_lock(&dev->struct_mutex); |
33a732f4 | 508 | obj = i915_gem_object_create_from_data(dev, fw->data, fw->size); |
bf248ca1 | 509 | mutex_unlock(&dev->struct_mutex); |
33a732f4 AD |
510 | if (IS_ERR_OR_NULL(obj)) { |
511 | err = obj ? PTR_ERR(obj) : -ENOMEM; | |
512 | goto fail; | |
513 | } | |
514 | ||
515 | guc_fw->guc_fw_obj = obj; | |
516 | guc_fw->guc_fw_size = fw->size; | |
517 | ||
518 | DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n", | |
519 | guc_fw->guc_fw_obj); | |
520 | ||
521 | release_firmware(fw); | |
522 | guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS; | |
523 | return; | |
524 | ||
525 | fail: | |
526 | DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n", | |
527 | err, fw, guc_fw->guc_fw_obj); | |
528 | DRM_ERROR("Failed to fetch GuC firmware from %s (error %d)\n", | |
529 | guc_fw->guc_fw_path, err); | |
530 | ||
531 | obj = guc_fw->guc_fw_obj; | |
532 | if (obj) | |
533 | drm_gem_object_unreference(&obj->base); | |
534 | guc_fw->guc_fw_obj = NULL; | |
535 | ||
536 | release_firmware(fw); /* OK even if fw is NULL */ | |
537 | guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL; | |
538 | } | |
539 | ||
540 | /** | |
541 | * intel_guc_ucode_init() - define parameters and fetch firmware | |
542 | * @dev: drm device | |
543 | * | |
544 | * Called early during driver load, but after GEM is initialised. | |
33a732f4 AD |
545 | * |
546 | * The firmware will be transferred to the GuC's memory later, | |
547 | * when intel_guc_ucode_load() is called. | |
548 | */ | |
549 | void intel_guc_ucode_init(struct drm_device *dev) | |
550 | { | |
551 | struct drm_i915_private *dev_priv = dev->dev_private; | |
552 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; | |
553 | const char *fw_path; | |
554 | ||
555 | if (!HAS_GUC_SCHED(dev)) | |
556 | i915.enable_guc_submission = false; | |
557 | ||
558 | if (!HAS_GUC_UCODE(dev)) { | |
559 | fw_path = NULL; | |
560 | } else if (IS_SKYLAKE(dev)) { | |
561 | fw_path = I915_SKL_GUC_UCODE; | |
aa557ab0 AD |
562 | guc_fw->guc_fw_major_wanted = 4; |
563 | guc_fw->guc_fw_minor_wanted = 3; | |
33a732f4 AD |
564 | } else { |
565 | i915.enable_guc_submission = false; | |
566 | fw_path = ""; /* unknown device */ | |
567 | } | |
568 | ||
569 | guc_fw->guc_dev = dev; | |
570 | guc_fw->guc_fw_path = fw_path; | |
571 | guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE; | |
572 | guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE; | |
573 | ||
574 | if (fw_path == NULL) | |
575 | return; | |
576 | ||
577 | if (*fw_path == '\0') { | |
578 | DRM_ERROR("No GuC firmware known for this platform\n"); | |
579 | guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL; | |
580 | return; | |
581 | } | |
582 | ||
583 | guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING; | |
584 | DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path); | |
585 | guc_fw_fetch(dev, guc_fw); | |
586 | /* status must now be FAIL or SUCCESS */ | |
587 | } | |
588 | ||
589 | /** | |
590 | * intel_guc_ucode_fini() - clean up all allocated resources | |
591 | * @dev: drm device | |
592 | */ | |
593 | void intel_guc_ucode_fini(struct drm_device *dev) | |
594 | { | |
595 | struct drm_i915_private *dev_priv = dev->dev_private; | |
596 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; | |
597 | ||
4df001d3 | 598 | direct_interrupts_to_host(dev_priv); |
bac427f8 AD |
599 | i915_guc_submission_fini(dev); |
600 | ||
bf248ca1 | 601 | mutex_lock(&dev->struct_mutex); |
33a732f4 AD |
602 | if (guc_fw->guc_fw_obj) |
603 | drm_gem_object_unreference(&guc_fw->guc_fw_obj->base); | |
604 | guc_fw->guc_fw_obj = NULL; | |
bf248ca1 | 605 | mutex_unlock(&dev->struct_mutex); |
33a732f4 AD |
606 | |
607 | guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE; | |
608 | } |