[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_guc.h

/*
 * Copyright © 2014-2017 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 */

#ifndef _INTEL_GUC_H_
#define _INTEL_GUC_H_

#include "intel_uncore.h"
#include "intel_guc_fw.h"
#include "intel_guc_fwif.h"
#include "intel_guc_ct.h"
#include "intel_guc_log.h"
#include "intel_guc_reg.h"
#include "intel_uc_fw.h"
#include "i915_utils.h"
#include "i915_vma.h"

struct guc_preempt_work {
	struct work_struct work;
	struct intel_engine_cs *engine;
};

/*
 * Top level structure of GuC. It handles firmware loading and manages client
 * pool and doorbells. intel_guc owns a intel_guc_client to replace the legacy
 * ExecList submission.
 */
struct intel_guc {
	struct intel_uc_fw fw;
	struct intel_guc_log log;
	struct intel_guc_ct ct;

	/* Log snapshot if GuC errors during load */
	struct drm_i915_gem_object *load_err_log;

	/* intel_guc_recv interrupt related state */
	spinlock_t irq_lock;
	bool interrupts_enabled;
	unsigned int msg_enabled_mask;

	struct i915_vma *ads_vma;
	struct i915_vma *stage_desc_pool;
	void *stage_desc_pool_vaddr;
	struct ida stage_ids;
	struct i915_vma *shared_data;
	void *shared_data_vaddr;

	struct intel_guc_client *execbuf_client;
	struct intel_guc_client *preempt_client;

	struct guc_preempt_work preempt_work[I915_NUM_ENGINES];
	struct workqueue_struct *preempt_wq;

	DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS);
	/* Cyclic counter mod pagesize	*/
	u32 db_cacheline;

	/* GuC's FW specific registers used in MMIO send */
	struct {
		u32 base;
		unsigned int count;
		enum forcewake_domains fw_domains;
	} send_regs;

	/* To serialize the intel_guc_send actions */
	struct mutex send_mutex;

	/* GuC's FW specific send function */
	int (*send)(struct intel_guc *guc, const u32 *data, u32 len,
		    u32 *response_buf, u32 response_buf_size);

	/* GuC's FW specific event handler function */
	void (*handler)(struct intel_guc *guc);

	/* GuC's FW specific notify function */
	void (*notify)(struct intel_guc *guc);
};

static inline bool intel_guc_is_alive(struct intel_guc *guc)
{
	return intel_uc_fw_is_loaded(&guc->fw);
}

static
inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
{
	return guc->send(guc, action, len, NULL, 0);
}

static inline int
intel_guc_send_and_receive(struct intel_guc *guc, const u32 *action, u32 len,
			   u32 *response_buf, u32 response_buf_size)
{
	return guc->send(guc, action, len, response_buf, response_buf_size);
}

static inline void intel_guc_notify(struct intel_guc *guc)
{
	guc->notify(guc);
}

static inline void intel_guc_to_host_event_handler(struct intel_guc *guc)
{
	guc->handler(guc);
}

/* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */
#define GUC_GGTT_TOP	0xFEE00000

/**
 * intel_guc_ggtt_offset() - Get and validate the GGTT offset of @vma
 * @guc: intel_guc structure.
 * @vma: i915 graphics virtual memory area.
 *
 * GuC does not allow any gfx GGTT address that falls into range
 * [0, ggtt.pin_bias), which is reserved for Boot ROM, SRAM and WOPCM.
 * Currently, in order to exclude [0, ggtt.pin_bias) address space from
 * GGTT, all gfx objects used by GuC are allocated with intel_guc_allocate_vma()
 * and pinned with PIN_OFFSET_BIAS along with the value of ggtt.pin_bias.
 *
 * Return: GGTT offset of the @vma.
 */
static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,
					struct i915_vma *vma)
{
	u32 offset = i915_ggtt_offset(vma);

	GEM_BUG_ON(offset < i915_ggtt_pin_bias(vma));
	GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));

	return offset;
}

void intel_guc_init_early(struct intel_guc *guc);
void intel_guc_init_send_regs(struct intel_guc *guc);
void intel_guc_init_params(struct intel_guc *guc);
int intel_guc_init_misc(struct intel_guc *guc);
int intel_guc_init(struct intel_guc *guc);
void intel_guc_fini(struct intel_guc *guc);
void intel_guc_fini_misc(struct intel_guc *guc);
int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len,
		       u32 *response_buf, u32 response_buf_size);
int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
			u32 *response_buf, u32 response_buf_size);
void intel_guc_to_host_event_handler(struct intel_guc *guc);
void intel_guc_to_host_event_handler_nop(struct intel_guc *guc);
void intel_guc_to_host_event_handler_mmio(struct intel_guc *guc);
int intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
				       const u32 *payload, u32 len);
int intel_guc_sample_forcewake(struct intel_guc *guc);
int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
int intel_guc_suspend(struct intel_guc *guc);
int intel_guc_resume(struct intel_guc *guc);
struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
u32 intel_guc_reserved_gtt_size(struct intel_guc *guc);

static inline int intel_guc_sanitize(struct intel_guc *guc)
{
	intel_uc_fw_sanitize(&guc->fw);
	return 0;
}

static inline void intel_guc_enable_msg(struct intel_guc *guc, u32 mask)
{
	spin_lock_irq(&guc->irq_lock);
	guc->msg_enabled_mask |= mask;
	spin_unlock_irq(&guc->irq_lock);
}

static inline void intel_guc_disable_msg(struct intel_guc *guc, u32 mask)
{
	spin_lock_irq(&guc->irq_lock);
	guc->msg_enabled_mask &= ~mask;
	spin_unlock_irq(&guc->irq_lock);
}

int intel_guc_reset_engine(struct intel_guc *guc,
			   struct intel_engine_cs *engine);

#endif
Commit	Line	Data
9bf384c5 MW	1	/*
	2	* Copyright © 2014-2017 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	*/
	24
	25	#ifndef _INTEL_GUC_H_
	26	#define _INTEL_GUC_H_
	27
	28	#include "intel_uncore.h"
e8668bbc	29	#include "intel_guc_fw.h"
9bf384c5 MW	30	#include "intel_guc_fwif.h"
	31	#include "intel_guc_ct.h"
	32	#include "intel_guc_log.h"
3e8f5b08	33	#include "intel_guc_reg.h"
9bf384c5	34	#include "intel_uc_fw.h"
39e2f501	35	#include "i915_utils.h"
9bf384c5 MW	36	#include "i915_vma.h"
9bf384c5 MW	37
c41937fd MW	38	struct guc_preempt_work {
	39	struct work_struct work;
	40	struct intel_engine_cs *engine;
	41	};
	42
d9e2e014 MW	43	/*
d9e2e014 MW	44	* Top level structure of GuC. It handles firmware loading and manages client
5afc8b49	45	* pool and doorbells. intel_guc owns a intel_guc_client to replace the legacy
d9e2e014 MW	46	* ExecList submission.
d9e2e014 MW	47	*/
9bf384c5 MW	48	struct intel_guc {
	49	struct intel_uc_fw fw;
	50	struct intel_guc_log log;
	51	struct intel_guc_ct ct;
	52
	53	/* Log snapshot if GuC errors during load */
	54	struct drm_i915_gem_object *load_err_log;
	55
	56	/* intel_guc_recv interrupt related state */
eacd8391	57	spinlock_t irq_lock;
9bf384c5	58	bool interrupts_enabled;
eacd8391	59	unsigned int msg_enabled_mask;
9bf384c5 MW	60
	61	struct i915_vma *ads_vma;
	62	struct i915_vma *stage_desc_pool;
	63	void *stage_desc_pool_vaddr;
	64	struct ida stage_ids;
b8e5eb96 MW	65	struct i915_vma *shared_data;
b8e5eb96 MW	66	void *shared_data_vaddr;
9bf384c5	67
5afc8b49 SAK	68	struct intel_guc_client *execbuf_client;
5afc8b49 SAK	69	struct intel_guc_client *preempt_client;
9bf384c5	70
c41937fd MW	71	struct guc_preempt_work preempt_work[I915_NUM_ENGINES];
	72	struct workqueue_struct *preempt_wq;
	73
9bf384c5	74	DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS);
faf65486 JL	75	/* Cyclic counter mod pagesize */
faf65486 JL	76	u32 db_cacheline;
9bf384c5 MW	77
	78	/* GuC's FW specific registers used in MMIO send */
	79	struct {
	80	u32 base;
	81	unsigned int count;
	82	enum forcewake_domains fw_domains;
	83	} send_regs;
	84
	85	/* To serialize the intel_guc_send actions */
	86	struct mutex send_mutex;
	87
	88	/* GuC's FW specific send function */
e09af3a6 MW	89	int (send)(struct intel_guc guc, const u32 *data, u32 len,
e09af3a6 MW	90	u32 *response_buf, u32 response_buf_size);
9bf384c5	91
769bfbf9 MW	92	/* GuC's FW specific event handler function */
	93	void (handler)(struct intel_guc guc);
	94
9bf384c5 MW	95	/* GuC's FW specific notify function */
	96	void (notify)(struct intel_guc guc);
	97	};
	98
48b426a9 DCS	99	static inline bool intel_guc_is_alive(struct intel_guc *guc)
	100	{
	101	return intel_uc_fw_is_loaded(&guc->fw);
	102	}
	103
9bf384c5 MW	104	static
	105	inline int intel_guc_send(struct intel_guc guc, const u32 action, u32 len)
	106	{
e09af3a6 MW	107	return guc->send(guc, action, len, NULL, 0);
	108	}
	109
	110	static inline int
	111	intel_guc_send_and_receive(struct intel_guc guc, const u32 action, u32 len,
	112	u32 *response_buf, u32 response_buf_size)
	113	{
	114	return guc->send(guc, action, len, response_buf, response_buf_size);
9bf384c5 MW	115	}
	116
	117	static inline void intel_guc_notify(struct intel_guc *guc)
	118	{
	119	guc->notify(guc);
	120	}
	121
769bfbf9 MW	122	static inline void intel_guc_to_host_event_handler(struct intel_guc *guc)
	123	{
	124	guc->handler(guc);
	125	}
	126
3c009e3c JL	127	/* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */
	128	#define GUC_GGTT_TOP 0xFEE00000
	129
	130	/**
	131	* intel_guc_ggtt_offset() - Get and validate the GGTT offset of @vma
	132	* @guc: intel_guc structure.
	133	* @vma: i915 graphics virtual memory area.
	134	*
6b0478fb	135	* GuC does not allow any gfx GGTT address that falls into range
dd18cedf JB	136	* [0, ggtt.pin_bias), which is reserved for Boot ROM, SRAM and WOPCM.
dd18cedf JB	137	* Currently, in order to exclude [0, ggtt.pin_bias) address space from
6b0478fb	138	* GGTT, all gfx objects used by GuC are allocated with intel_guc_allocate_vma()
dd18cedf	139	* and pinned with PIN_OFFSET_BIAS along with the value of ggtt.pin_bias.
3c009e3c	140	*
6b0478fb	141	* Return: GGTT offset of the @vma.
d9e2e014	142	*/
3c009e3c JL	143	static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,
3c009e3c JL	144	struct i915_vma *vma)
9bf384c5 MW	145	{
	146	u32 offset = i915_ggtt_offset(vma);
	147
dd18cedf	148	GEM_BUG_ON(offset < i915_ggtt_pin_bias(vma));
9bf384c5 MW	149	GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
	150
	151	return offset;
	152	}
	153
	154	void intel_guc_init_early(struct intel_guc *guc);
	155	void intel_guc_init_send_regs(struct intel_guc *guc);
5d53be45	156	void intel_guc_init_params(struct intel_guc *guc);
c39d2e7e	157	int intel_guc_init_misc(struct intel_guc *guc);
1bbbca0d MW	158	int intel_guc_init(struct intel_guc *guc);
1bbbca0d MW	159	void intel_guc_fini(struct intel_guc *guc);
c39d2e7e	160	void intel_guc_fini_misc(struct intel_guc *guc);
e09af3a6 MW	161	int intel_guc_send_nop(struct intel_guc guc, const u32 action, u32 len,
	162	u32 *response_buf, u32 response_buf_size);
	163	int intel_guc_send_mmio(struct intel_guc guc, const u32 action, u32 len,
	164	u32 *response_buf, u32 response_buf_size);
93bf8096	165	void intel_guc_to_host_event_handler(struct intel_guc *guc);
769bfbf9 MW	166	void intel_guc_to_host_event_handler_nop(struct intel_guc *guc);
769bfbf9 MW	167	void intel_guc_to_host_event_handler_mmio(struct intel_guc *guc);
47c3b5e9 MW	168	int intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
47c3b5e9 MW	169	const u32 *payload, u32 len);
9bf384c5 MW	170	int intel_guc_sample_forcewake(struct intel_guc *guc);
9bf384c5 MW	171	int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
7cfca4af MW	172	int intel_guc_suspend(struct intel_guc *guc);
7cfca4af MW	173	int intel_guc_resume(struct intel_guc *guc);
9bf384c5	174	struct i915_vma intel_guc_allocate_vma(struct intel_guc guc, u32 size);
dd18cedf	175	u32 intel_guc_reserved_gtt_size(struct intel_guc *guc);
9bf384c5	176
c37d5728 MW	177	static inline int intel_guc_sanitize(struct intel_guc *guc)
	178	{
	179	intel_uc_fw_sanitize(&guc->fw);
	180	return 0;
	181	}
	182
bc598425 MW	183	static inline void intel_guc_enable_msg(struct intel_guc *guc, u32 mask)
	184	{
	185	spin_lock_irq(&guc->irq_lock);
	186	guc->msg_enabled_mask \|= mask;
	187	spin_unlock_irq(&guc->irq_lock);
	188	}
	189
	190	static inline void intel_guc_disable_msg(struct intel_guc *guc, u32 mask)
	191	{
	192	spin_lock_irq(&guc->irq_lock);
	193	guc->msg_enabled_mask &= ~mask;
	194	spin_unlock_irq(&guc->irq_lock);
	195	}
	196
9f58892e CW	197	int intel_guc_reset_engine(struct intel_guc *guc,
	198	struct intel_engine_cs *engine);
	199
9bf384c5	200	#endif