[linux-block.git] / drivers / gpu / drm / i915 / intel_fifo_underrun.c

/*
 * Copyright © 2014 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Daniel Vetter <daniel.vetter@ffwll.ch>
 *
 */

#include "i915_drv.h"
#include "intel_drv.h"

/**
 * DOC: fifo underrun handling
 *
 * The i915 driver checks for display fifo underruns using the interrupt signals
 * provided by the hardware. This is enabled by default and fairly useful to
 * debug display issues, especially watermark settings.
 *
 * If an underrun is detected this is logged into dmesg. To avoid flooding logs
 * and occupying the cpu underrun interrupts are disabled after the first
 * occurrence until the next modeset on a given pipe.
 *
 * Note that underrun detection on gmch platforms is a bit more ugly since there
 * is no interrupt (despite that the signalling bit is in the PIPESTAT pipe
 * interrupt register). Also on some other platforms underrun interrupts are
 * shared, which means that if we detect an underrun we need to disable underrun
 * reporting on all pipes.
 *
 * The code also supports underrun detection on the PCH transcoder.
 */

static bool ivb_can_enable_err_int(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct intel_crtc *crtc;
	enum pipe pipe;

	lockdep_assert_held(&dev_priv->irq_lock);

	for_each_pipe(dev_priv, pipe) {
		crtc = intel_get_crtc_for_pipe(dev_priv, pipe);

		if (crtc->cpu_fifo_underrun_disabled)
			return false;
	}

	return true;
}

static bool cpt_can_enable_serr_int(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = to_i915(dev);
	enum pipe pipe;
	struct intel_crtc *crtc;

	lockdep_assert_held(&dev_priv->irq_lock);

	for_each_pipe(dev_priv, pipe) {
		crtc = intel_get_crtc_for_pipe(dev_priv, pipe);

		if (crtc->pch_fifo_underrun_disabled)
			return false;
	}

	return true;
}

static void i9xx_check_fifo_underruns(struct intel_crtc *crtc)
{
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
	i915_reg_t reg = PIPESTAT(crtc->pipe);
	u32 pipestat = I915_READ(reg) & 0xffff0000;

	lockdep_assert_held(&dev_priv->irq_lock);

	if ((pipestat & PIPE_FIFO_UNDERRUN_STATUS) == 0)
		return;

	I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
	POSTING_READ(reg);

	trace_intel_cpu_fifo_underrun(dev_priv, crtc->pipe);
	DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe));
}

static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
					     enum pipe pipe,
					     bool enable, bool old)
{
	struct drm_i915_private *dev_priv = to_i915(dev);
	i915_reg_t reg = PIPESTAT(pipe);
	u32 pipestat = I915_READ(reg) & 0xffff0000;

	lockdep_assert_held(&dev_priv->irq_lock);

	if (enable) {
		I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
		POSTING_READ(reg);
	} else {
		if (old && pipestat & PIPE_FIFO_UNDERRUN_STATUS)
			DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
	}
}

static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
						 enum pipe pipe, bool enable)
{
	struct drm_i915_private *dev_priv = to_i915(dev);
	uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
					  DE_PIPEB_FIFO_UNDERRUN;

	if (enable)
		ilk_enable_display_irq(dev_priv, bit);
	else
		ilk_disable_display_irq(dev_priv, bit);
}

static void ivybridge_check_fifo_underruns(struct intel_crtc *crtc)
{
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
	enum pipe pipe = crtc->pipe;
	uint32_t err_int = I915_READ(GEN7_ERR_INT);

	lockdep_assert_held(&dev_priv->irq_lock);

	if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0)
		return;

	I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
	POSTING_READ(GEN7_ERR_INT);

	trace_intel_cpu_fifo_underrun(dev_priv, pipe);
	DRM_ERROR("fifo underrun on pipe %c\n", pipe_name(pipe));
}

static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
						  enum pipe pipe,
						  bool enable, bool old)
{
	struct drm_i915_private *dev_priv = to_i915(dev);
	if (enable) {
		I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));

		if (!ivb_can_enable_err_int(dev))
			return;

		ilk_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
	} else {
		ilk_disable_display_irq(dev_priv, DE_ERR_INT_IVB);

		if (old &&
		    I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {
			DRM_ERROR("uncleared fifo underrun on pipe %c\n",
				  pipe_name(pipe));
		}
	}
}

static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
						  enum pipe pipe, bool enable)
{
	struct drm_i915_private *dev_priv = to_i915(dev);

	if (enable)
		bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);
	else
		bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);
}

static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
					    enum transcoder pch_transcoder,
					    bool enable)
{
	struct drm_i915_private *dev_priv = to_i915(dev);
	uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
		       SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;

	if (enable)
		ibx_enable_display_interrupt(dev_priv, bit);
	else
		ibx_disable_display_interrupt(dev_priv, bit);
}

static void cpt_check_pch_fifo_underruns(struct intel_crtc *crtc)
{
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
	enum transcoder pch_transcoder = (enum transcoder) crtc->pipe;
	uint32_t serr_int = I915_READ(SERR_INT);

	lockdep_assert_held(&dev_priv->irq_lock);

	if ((serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) == 0)
		return;

	I915_WRITE(SERR_INT, SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
	POSTING_READ(SERR_INT);

	trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder);
	DRM_ERROR("pch fifo underrun on pch transcoder %s\n",
		  transcoder_name(pch_transcoder));
}

static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
					    enum transcoder pch_transcoder,
					    bool enable, bool old)
{
	struct drm_i915_private *dev_priv = to_i915(dev);

	if (enable) {
		I915_WRITE(SERR_INT,
			   SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));

		if (!cpt_can_enable_serr_int(dev))
			return;

		ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
	} else {
		ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);

		if (old && I915_READ(SERR_INT) &
		    SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) {
			DRM_ERROR("uncleared pch fifo underrun on pch transcoder %s\n",
				  transcoder_name(pch_transcoder));
		}
	}
}

static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
						    enum pipe pipe, bool enable)
{
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
	bool old;

	lockdep_assert_held(&dev_priv->irq_lock);

	old = !crtc->cpu_fifo_underrun_disabled;
	crtc->cpu_fifo_underrun_disabled = !enable;

	if (HAS_GMCH_DISPLAY(dev_priv))
		i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
	else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
		ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
	else if (IS_GEN7(dev_priv))
		ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);
	else if (IS_GEN8(dev_priv) || IS_GEN9(dev_priv))
		broadwell_set_fifo_underrun_reporting(dev, pipe, enable);

	return old;
}

/**
 * intel_set_cpu_fifo_underrun_reporting - set cpu fifo underrrun reporting state
 * @dev_priv: i915 device instance
 * @pipe: (CPU) pipe to set state for
 * @enable: whether underruns should be reported or not
 *
 * This function sets the fifo underrun state for @pipe. It is used in the
 * modeset code to avoid false positives since on many platforms underruns are
 * expected when disabling or enabling the pipe.
 *
 * Notice that on some platforms disabling underrun reports for one pipe
 * disables for all due to shared interrupts. Actual reporting is still per-pipe
 * though.
 *
 * Returns the previous state of underrun reporting.
 */
bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
					   enum pipe pipe, bool enable)
{
	unsigned long flags;
	bool ret;

	spin_lock_irqsave(&dev_priv->irq_lock, flags);
	ret = __intel_set_cpu_fifo_underrun_reporting(&dev_priv->drm, pipe,
						      enable);
	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);

	return ret;
}

/**
 * intel_set_pch_fifo_underrun_reporting - set PCH fifo underrun reporting state
 * @dev_priv: i915 device instance
 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
 * @enable: whether underruns should be reported or not
 *
 * This function makes us disable or enable PCH fifo underruns for a specific
 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
 * underrun reporting for one transcoder may also disable all the other PCH
 * error interruts for the other transcoders, due to the fact that there's just
 * one interrupt mask/enable bit for all the transcoders.
 *
 * Returns the previous state of underrun reporting.
 */
bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
					   enum transcoder pch_transcoder,
					   bool enable)
{
	struct intel_crtc *crtc =
		intel_get_crtc_for_pipe(dev_priv, (enum pipe) pch_transcoder);
	unsigned long flags;
	bool old;

	/*
	 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
	 * has only one pch transcoder A that all pipes can use. To avoid racy
	 * pch transcoder -> pipe lookups from interrupt code simply store the
	 * underrun statistics in crtc A. Since we never expose this anywhere
	 * nor use it outside of the fifo underrun code here using the "wrong"
	 * crtc on LPT won't cause issues.
	 */

	spin_lock_irqsave(&dev_priv->irq_lock, flags);

	old = !crtc->pch_fifo_underrun_disabled;
	crtc->pch_fifo_underrun_disabled = !enable;

	if (HAS_PCH_IBX(dev_priv))
		ibx_set_fifo_underrun_reporting(&dev_priv->drm,
						pch_transcoder,
						enable);
	else
		cpt_set_fifo_underrun_reporting(&dev_priv->drm,
						pch_transcoder,
						enable, old);

	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
	return old;
}

/**
 * intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt
 * @dev_priv: i915 device instance
 * @pipe: (CPU) pipe to set state for
 *
 * This handles a CPU fifo underrun interrupt, generating an underrun warning
 * into dmesg if underrun reporting is enabled and then disables the underrun
 * interrupt to avoid an irq storm.
 */
void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
					 enum pipe pipe)
{
	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);

	/* We may be called too early in init, thanks BIOS! */
	if (crtc == NULL)
		return;

	/* GMCH can't disable fifo underruns, filter them. */
	if (HAS_GMCH_DISPLAY(dev_priv) &&
	    crtc->cpu_fifo_underrun_disabled)
		return;

	if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) {
		trace_intel_cpu_fifo_underrun(dev_priv, pipe);
		DRM_ERROR("CPU pipe %c FIFO underrun\n",
			  pipe_name(pipe));
	}

	intel_fbc_handle_fifo_underrun_irq(dev_priv);
}

/**
 * intel_pch_fifo_underrun_irq_handler - handle PCH fifo underrun interrupt
 * @dev_priv: i915 device instance
 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
 *
 * This handles a PCH fifo underrun interrupt, generating an underrun warning
 * into dmesg if underrun reporting is enabled and then disables the underrun
 * interrupt to avoid an irq storm.
 */
void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
					 enum transcoder pch_transcoder)
{
	if (intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder,
						  false)) {
		trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder);
		DRM_ERROR("PCH transcoder %s FIFO underrun\n",
			  transcoder_name(pch_transcoder));
	}
}

/**
 * intel_check_cpu_fifo_underruns - check for CPU fifo underruns immediately
 * @dev_priv: i915 device instance
 *
 * Check for CPU fifo underruns immediately. Useful on IVB/HSW where the shared
 * error interrupt may have been disabled, and so CPU fifo underruns won't
 * necessarily raise an interrupt, and on GMCH platforms where underruns never
 * raise an interrupt.
 */
void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv)
{
	struct intel_crtc *crtc;

	spin_lock_irq(&dev_priv->irq_lock);

	for_each_intel_crtc(&dev_priv->drm, crtc) {
		if (crtc->cpu_fifo_underrun_disabled)
			continue;

		if (HAS_GMCH_DISPLAY(dev_priv))
			i9xx_check_fifo_underruns(crtc);
		else if (IS_GEN7(dev_priv))
			ivybridge_check_fifo_underruns(crtc);
	}

	spin_unlock_irq(&dev_priv->irq_lock);
}

/**
 * intel_check_pch_fifo_underruns - check for PCH fifo underruns immediately
 * @dev_priv: i915 device instance
 *
 * Check for PCH fifo underruns immediately. Useful on CPT/PPT where the shared
 * error interrupt may have been disabled, and so PCH fifo underruns won't
 * necessarily raise an interrupt.
 */
void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv)
{
	struct intel_crtc *crtc;

	spin_lock_irq(&dev_priv->irq_lock);

	for_each_intel_crtc(&dev_priv->drm, crtc) {
		if (crtc->pch_fifo_underrun_disabled)
			continue;

		if (HAS_PCH_CPT(dev_priv))
			cpt_check_pch_fifo_underruns(crtc);
	}

	spin_unlock_irq(&dev_priv->irq_lock);
}
Commit	Line	Data
47339cd9 DV	1	/*
	2	* Copyright © 2014 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* Daniel Vetter <daniel.vetter@ffwll.ch>
	25	*
	26	*/
	27
	28	#include "i915_drv.h"
	29	#include "intel_drv.h"
	30
ef07388e DV	31	/**
	32	* DOC: fifo underrun handling
	33	*
	34	* The i915 driver checks for display fifo underruns using the interrupt signals
	35	* provided by the hardware. This is enabled by default and fairly useful to
	36	* debug display issues, especially watermark settings.
	37	*
	38	* If an underrun is detected this is logged into dmesg. To avoid flooding logs
	39	* and occupying the cpu underrun interrupts are disabled after the first
	40	* occurrence until the next modeset on a given pipe.
	41	*
	42	* Note that underrun detection on gmch platforms is a bit more ugly since there
	43	* is no interrupt (despite that the signalling bit is in the PIPESTAT pipe
	44	* interrupt register). Also on some other platforms underrun interrupts are
	45	* shared, which means that if we detect an underrun we need to disable underrun
	46	* reporting on all pipes.
	47	*
	48	* The code also supports underrun detection on the PCH transcoder.
	49	*/
	50
47339cd9 DV	51	static bool ivb_can_enable_err_int(struct drm_device *dev)
47339cd9 DV	52	{
fac5e23e	53	struct drm_i915_private *dev_priv = to_i915(dev);
47339cd9 DV	54	struct intel_crtc *crtc;
	55	enum pipe pipe;
	56
67520415	57	lockdep_assert_held(&dev_priv->irq_lock);
47339cd9 DV	58
47339cd9 DV	59	for_each_pipe(dev_priv, pipe) {
98187836	60	crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
47339cd9 DV	61
	62	if (crtc->cpu_fifo_underrun_disabled)
	63	return false;
	64	}
	65
	66	return true;
	67	}
	68
	69	static bool cpt_can_enable_serr_int(struct drm_device *dev)
	70	{
fac5e23e	71	struct drm_i915_private *dev_priv = to_i915(dev);
47339cd9 DV	72	enum pipe pipe;
	73	struct intel_crtc *crtc;
	74
67520415	75	lockdep_assert_held(&dev_priv->irq_lock);
47339cd9 DV	76
47339cd9 DV	77	for_each_pipe(dev_priv, pipe) {
98187836	78	crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
47339cd9 DV	79
	80	if (crtc->pch_fifo_underrun_disabled)
	81	return false;
	82	}
	83
	84	return true;
	85	}
	86
aca7b684	87	static void i9xx_check_fifo_underruns(struct intel_crtc *crtc)
47339cd9	88	{
aca7b684	89	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
f0f59a00	90	i915_reg_t reg = PIPESTAT(crtc->pipe);
aca7b684	91	u32 pipestat = I915_READ(reg) & 0xffff0000;
47339cd9	92
67520415	93	lockdep_assert_held(&dev_priv->irq_lock);
47339cd9	94
aca7b684 VS	95	if ((pipestat & PIPE_FIFO_UNDERRUN_STATUS) == 0)
aca7b684 VS	96	return;
47339cd9	97
aca7b684 VS	98	I915_WRITE(reg, pipestat \| PIPE_FIFO_UNDERRUN_STATUS);
aca7b684 VS	99	POSTING_READ(reg);
47339cd9	100
53a7915c	101	trace_intel_cpu_fifo_underrun(dev_priv, crtc->pipe);
aca7b684	102	DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe));
47339cd9 DV	103	}
	104
	105	static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
	106	enum pipe pipe,
	107	bool enable, bool old)
	108	{
fac5e23e	109	struct drm_i915_private *dev_priv = to_i915(dev);
f0f59a00	110	i915_reg_t reg = PIPESTAT(pipe);
47339cd9 DV	111	u32 pipestat = I915_READ(reg) & 0xffff0000;
47339cd9 DV	112
67520415	113	lockdep_assert_held(&dev_priv->irq_lock);
47339cd9 DV	114
	115	if (enable) {
	116	I915_WRITE(reg, pipestat \| PIPE_FIFO_UNDERRUN_STATUS);
	117	POSTING_READ(reg);
	118	} else {
	119	if (old && pipestat & PIPE_FIFO_UNDERRUN_STATUS)
	120	DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
	121	}
	122	}
	123
	124	static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
	125	enum pipe pipe, bool enable)
	126	{
fac5e23e	127	struct drm_i915_private *dev_priv = to_i915(dev);
47339cd9 DV	128	uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
	129	DE_PIPEB_FIFO_UNDERRUN;
	130
	131	if (enable)
fbdedaea	132	ilk_enable_display_irq(dev_priv, bit);
47339cd9	133	else
fbdedaea	134	ilk_disable_display_irq(dev_priv, bit);
47339cd9 DV	135	}
47339cd9 DV	136
aca7b684 VS	137	static void ivybridge_check_fifo_underruns(struct intel_crtc *crtc)
	138	{
	139	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
	140	enum pipe pipe = crtc->pipe;
	141	uint32_t err_int = I915_READ(GEN7_ERR_INT);
	142
67520415	143	lockdep_assert_held(&dev_priv->irq_lock);
aca7b684 VS	144
	145	if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0)
	146	return;
	147
	148	I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
	149	POSTING_READ(GEN7_ERR_INT);
	150
53a7915c	151	trace_intel_cpu_fifo_underrun(dev_priv, pipe);
aca7b684 VS	152	DRM_ERROR("fifo underrun on pipe %c\n", pipe_name(pipe));
	153	}
	154
47339cd9 DV	155	static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
	156	enum pipe pipe,
	157	bool enable, bool old)
	158	{
fac5e23e	159	struct drm_i915_private *dev_priv = to_i915(dev);
47339cd9 DV	160	if (enable) {
	161	I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
	162
	163	if (!ivb_can_enable_err_int(dev))
	164	return;
	165
fbdedaea	166	ilk_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
47339cd9	167	} else {
fbdedaea	168	ilk_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
47339cd9 DV	169
	170	if (old &&
	171	I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {
	172	DRM_ERROR("uncleared fifo underrun on pipe %c\n",
	173	pipe_name(pipe));
	174	}
	175	}
	176	}
	177
	178	static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
	179	enum pipe pipe, bool enable)
	180	{
fac5e23e	181	struct drm_i915_private *dev_priv = to_i915(dev);
47339cd9	182
47339cd9	183	if (enable)
013d3752	184	bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);
47339cd9	185	else
013d3752	186	bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);
47339cd9 DV	187	}
	188
	189	static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
	190	enum transcoder pch_transcoder,
	191	bool enable)
	192	{
fac5e23e	193	struct drm_i915_private *dev_priv = to_i915(dev);
47339cd9 DV	194	uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
	195	SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
	196
	197	if (enable)
	198	ibx_enable_display_interrupt(dev_priv, bit);
	199	else
	200	ibx_disable_display_interrupt(dev_priv, bit);
	201	}
	202
aca7b684 VS	203	static void cpt_check_pch_fifo_underruns(struct intel_crtc *crtc)
	204	{
	205	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
	206	enum transcoder pch_transcoder = (enum transcoder) crtc->pipe;
	207	uint32_t serr_int = I915_READ(SERR_INT);
	208
67520415	209	lockdep_assert_held(&dev_priv->irq_lock);
aca7b684 VS	210
	211	if ((serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) == 0)
	212	return;
	213
	214	I915_WRITE(SERR_INT, SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
	215	POSTING_READ(SERR_INT);
	216
53a7915c	217	trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder);
da205630	218	DRM_ERROR("pch fifo underrun on pch transcoder %s\n",
aca7b684 VS	219	transcoder_name(pch_transcoder));
	220	}
	221
47339cd9 DV	222	static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
	223	enum transcoder pch_transcoder,
	224	bool enable, bool old)
	225	{
fac5e23e	226	struct drm_i915_private *dev_priv = to_i915(dev);
47339cd9 DV	227
	228	if (enable) {
	229	I915_WRITE(SERR_INT,
	230	SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
	231
	232	if (!cpt_can_enable_serr_int(dev))
	233	return;
	234
	235	ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
	236	} else {
	237	ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
	238
	239	if (old && I915_READ(SERR_INT) &
	240	SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) {
da205630	241	DRM_ERROR("uncleared pch fifo underrun on pch transcoder %s\n",
47339cd9 DV	242	transcoder_name(pch_transcoder));
	243	}
	244	}
	245	}
	246
47339cd9 DV	247	static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
	248	enum pipe pipe, bool enable)
	249	{
fac5e23e	250	struct drm_i915_private *dev_priv = to_i915(dev);
98187836	251	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
47339cd9 DV	252	bool old;
47339cd9 DV	253
67520415	254	lockdep_assert_held(&dev_priv->irq_lock);
47339cd9	255
e2af48c6 VS	256	old = !crtc->cpu_fifo_underrun_disabled;
e2af48c6 VS	257	crtc->cpu_fifo_underrun_disabled = !enable;
47339cd9	258
49cff963	259	if (HAS_GMCH_DISPLAY(dev_priv))
47339cd9	260	i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
5db94019	261	else if (IS_GEN5(dev_priv) \|\| IS_GEN6(dev_priv))
47339cd9	262	ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
5db94019	263	else if (IS_GEN7(dev_priv))
47339cd9	264	ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);
5db94019	265	else if (IS_GEN8(dev_priv) \|\| IS_GEN9(dev_priv))
47339cd9 DV	266	broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
	267
	268	return old;
	269	}
	270
ef07388e DV	271	/**
	272	* intel_set_cpu_fifo_underrun_reporting - set cpu fifo underrrun reporting state
	273	* @dev_priv: i915 device instance
	274	* @pipe: (CPU) pipe to set state for
	275	* @enable: whether underruns should be reported or not
	276	*
	277	* This function sets the fifo underrun state for @pipe. It is used in the
	278	* modeset code to avoid false positives since on many platforms underruns are
	279	* expected when disabling or enabling the pipe.
	280	*
	281	* Notice that on some platforms disabling underrun reports for one pipe
	282	* disables for all due to shared interrupts. Actual reporting is still per-pipe
	283	* though.
	284	*
	285	* Returns the previous state of underrun reporting.
	286	*/
a72e4c9f	287	bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
47339cd9 DV	288	enum pipe pipe, bool enable)
47339cd9 DV	289	{
47339cd9 DV	290	unsigned long flags;
	291	bool ret;
	292
	293	spin_lock_irqsave(&dev_priv->irq_lock, flags);
91c8a326	294	ret = __intel_set_cpu_fifo_underrun_reporting(&dev_priv->drm, pipe,
a72e4c9f	295	enable);
47339cd9 DV	296	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
	297
	298	return ret;
	299	}
	300
47339cd9	301	/**
ef07388e DV	302	* intel_set_pch_fifo_underrun_reporting - set PCH fifo underrun reporting state
ef07388e DV	303	* @dev_priv: i915 device instance
47339cd9	304	* @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
ef07388e	305	* @enable: whether underruns should be reported or not
47339cd9 DV	306	*
	307	* This function makes us disable or enable PCH fifo underruns for a specific
	308	* PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
	309	* underrun reporting for one transcoder may also disable all the other PCH
	310	* error interruts for the other transcoders, due to the fact that there's just
	311	* one interrupt mask/enable bit for all the transcoders.
	312	*
	313	* Returns the previous state of underrun reporting.
	314	*/
a72e4c9f	315	bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
47339cd9 DV	316	enum transcoder pch_transcoder,
	317	bool enable)
	318	{
98187836 VS	319	struct intel_crtc *crtc =
98187836 VS	320	intel_get_crtc_for_pipe(dev_priv, (enum pipe) pch_transcoder);
47339cd9 DV	321	unsigned long flags;
	322	bool old;
	323
	324	/*
	325	* NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
	326	* has only one pch transcoder A that all pipes can use. To avoid racy
	327	* pch transcoder -> pipe lookups from interrupt code simply store the
	328	* underrun statistics in crtc A. Since we never expose this anywhere
	329	* nor use it outside of the fifo underrun code here using the "wrong"
	330	* crtc on LPT won't cause issues.
	331	*/
	332
	333	spin_lock_irqsave(&dev_priv->irq_lock, flags);
	334
e2af48c6 VS	335	old = !crtc->pch_fifo_underrun_disabled;
e2af48c6 VS	336	crtc->pch_fifo_underrun_disabled = !enable;
47339cd9	337
2d1fe073	338	if (HAS_PCH_IBX(dev_priv))
91c8a326 CW	339	ibx_set_fifo_underrun_reporting(&dev_priv->drm,
91c8a326 CW	340	pch_transcoder,
a72e4c9f	341	enable);
47339cd9	342	else
91c8a326 CW	343	cpt_set_fifo_underrun_reporting(&dev_priv->drm,
91c8a326 CW	344	pch_transcoder,
a72e4c9f	345	enable, old);
47339cd9 DV	346
	347	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
	348	return old;
	349	}
1f7247c0	350
ef07388e	351	/**
cea3bf81	352	* intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt
ef07388e DV	353	* @dev_priv: i915 device instance
	354	* @pipe: (CPU) pipe to set state for
	355	*
	356	* This handles a CPU fifo underrun interrupt, generating an underrun warning
	357	* into dmesg if underrun reporting is enabled and then disables the underrun
	358	* interrupt to avoid an irq storm.
	359	*/
1f7247c0 DV	360	void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
	361	enum pipe pipe)
	362	{
98187836	363	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
54fc7c1c CW	364
	365	/* We may be called too early in init, thanks BIOS! */
	366	if (crtc == NULL)
	367	return;
	368
0f239f4c	369	/* GMCH can't disable fifo underruns, filter them. */
2d1fe073	370	if (HAS_GMCH_DISPLAY(dev_priv) &&
e2af48c6	371	crtc->cpu_fifo_underrun_disabled)
0f239f4c DV	372	return;
0f239f4c DV	373
53a7915c VS	374	if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) {
53a7915c VS	375	trace_intel_cpu_fifo_underrun(dev_priv, pipe);
1f7247c0 DV	376	DRM_ERROR("CPU pipe %c FIFO underrun\n",
1f7247c0 DV	377	pipe_name(pipe));
53a7915c	378	}
61a585d6 PZ	379
61a585d6 PZ	380	intel_fbc_handle_fifo_underrun_irq(dev_priv);
1f7247c0 DV	381	}
1f7247c0 DV	382
ef07388e DV	383	/**
	384	* intel_pch_fifo_underrun_irq_handler - handle PCH fifo underrun interrupt
	385	* @dev_priv: i915 device instance
	386	* @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
	387	*
	388	* This handles a PCH fifo underrun interrupt, generating an underrun warning
	389	* into dmesg if underrun reporting is enabled and then disables the underrun
	390	* interrupt to avoid an irq storm.
	391	*/
1f7247c0 DV	392	void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
	393	enum transcoder pch_transcoder)
	394	{
	395	if (intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder,
53a7915c VS	396	false)) {
53a7915c VS	397	trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder);
da205630	398	DRM_ERROR("PCH transcoder %s FIFO underrun\n",
1f7247c0	399	transcoder_name(pch_transcoder));
53a7915c	400	}
1f7247c0	401	}
aca7b684 VS	402
	403	/**
	404	* intel_check_cpu_fifo_underruns - check for CPU fifo underruns immediately
	405	* @dev_priv: i915 device instance
	406	*
	407	* Check for CPU fifo underruns immediately. Useful on IVB/HSW where the shared
	408	* error interrupt may have been disabled, and so CPU fifo underruns won't
	409	* necessarily raise an interrupt, and on GMCH platforms where underruns never
	410	* raise an interrupt.
	411	*/
	412	void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv)
	413	{
	414	struct intel_crtc *crtc;
	415
	416	spin_lock_irq(&dev_priv->irq_lock);
	417
91c8a326	418	for_each_intel_crtc(&dev_priv->drm, crtc) {
aca7b684 VS	419	if (crtc->cpu_fifo_underrun_disabled)
	420	continue;
	421
	422	if (HAS_GMCH_DISPLAY(dev_priv))
	423	i9xx_check_fifo_underruns(crtc);
	424	else if (IS_GEN7(dev_priv))
	425	ivybridge_check_fifo_underruns(crtc);
	426	}
	427
	428	spin_unlock_irq(&dev_priv->irq_lock);
	429	}
	430
	431	/**
	432	* intel_check_pch_fifo_underruns - check for PCH fifo underruns immediately
	433	* @dev_priv: i915 device instance
	434	*
	435	* Check for PCH fifo underruns immediately. Useful on CPT/PPT where the shared
	436	* error interrupt may have been disabled, and so PCH fifo underruns won't
	437	* necessarily raise an interrupt.
	438	*/
	439	void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv)
	440	{
	441	struct intel_crtc *crtc;
	442
	443	spin_lock_irq(&dev_priv->irq_lock);
	444
91c8a326	445	for_each_intel_crtc(&dev_priv->drm, crtc) {
aca7b684 VS	446	if (crtc->pch_fifo_underrun_disabled)
	447	continue;
	448
	449	if (HAS_PCH_CPT(dev_priv))
	450	cpt_check_pch_fifo_underruns(crtc);
	451	}
	452
	453	spin_unlock_irq(&dev_priv->irq_lock);
	454	}