[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_fifo_underrun.c

/*
 * Copyright © 2014 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Daniel Vetter <daniel.vetter@ffwll.ch>
 *
 */

#include "i915_drv.h"
#include "intel_drv.h"

/**
 * DOC: fifo underrun handling
 *
 * The i915 driver checks for display fifo underruns using the interrupt signals
 * provided by the hardware. This is enabled by default and fairly useful to
 * debug display issues, especially watermark settings.
 *
 * If an underrun is detected this is logged into dmesg. To avoid flooding logs
 * and occupying the cpu underrun interrupts are disabled after the first
 * occurrence until the next modeset on a given pipe.
 *
 * Note that underrun detection on gmch platforms is a bit more ugly since there
 * is no interrupt (despite that the signalling bit is in the PIPESTAT pipe
 * interrupt register). Also on some other platforms underrun interrupts are
 * shared, which means that if we detect an underrun we need to disable underrun
 * reporting on all pipes.
 *
 * The code also supports underrun detection on the PCH transcoder.
 */

static bool ivb_can_enable_err_int(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct intel_crtc *crtc;
	enum pipe pipe;

	lockdep_assert_held(&dev_priv->irq_lock);

	for_each_pipe(dev_priv, pipe) {
		crtc = intel_get_crtc_for_pipe(dev_priv, pipe);

		if (crtc->cpu_fifo_underrun_disabled)
			return false;
	}

	return true;
}

static bool cpt_can_enable_serr_int(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = to_i915(dev);
	enum pipe pipe;
	struct intel_crtc *crtc;

	lockdep_assert_held(&dev_priv->irq_lock);

	for_each_pipe(dev_priv, pipe) {
		crtc = intel_get_crtc_for_pipe(dev_priv, pipe);

		if (crtc->pch_fifo_underrun_disabled)
			return false;
	}

	return true;
}

static void i9xx_check_fifo_underruns(struct intel_crtc *crtc)
{
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
	i915_reg_t reg = PIPESTAT(crtc->pipe);
	u32 enable_mask;

	lockdep_assert_held(&dev_priv->irq_lock);

	if ((I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0)
		return;

	enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe);
	I915_WRITE(reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
	POSTING_READ(reg);

	trace_intel_cpu_fifo_underrun(dev_priv, crtc->pipe);
	DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe));
}

static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
					     enum pipe pipe,
					     bool enable, bool old)
{
	struct drm_i915_private *dev_priv = to_i915(dev);
	i915_reg_t reg = PIPESTAT(pipe);

	lockdep_assert_held(&dev_priv->irq_lock);

	if (enable) {
		u32 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);

		I915_WRITE(reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
		POSTING_READ(reg);
	} else {
		if (old && I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS)
			DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
	}
}

static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
						 enum pipe pipe, bool enable)
{
	struct drm_i915_private *dev_priv = to_i915(dev);
	uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
					  DE_PIPEB_FIFO_UNDERRUN;

	if (enable)
		ilk_enable_display_irq(dev_priv, bit);
	else
		ilk_disable_display_irq(dev_priv, bit);
}

static void ivybridge_check_fifo_underruns(struct intel_crtc *crtc)
{
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
	enum pipe pipe = crtc->pipe;
	uint32_t err_int = I915_READ(GEN7_ERR_INT);

	lockdep_assert_held(&dev_priv->irq_lock);

	if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0)
		return;

	I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
	POSTING_READ(GEN7_ERR_INT);

	trace_intel_cpu_fifo_underrun(dev_priv, pipe);
	DRM_ERROR("fifo underrun on pipe %c\n", pipe_name(pipe));
}

static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
						  enum pipe pipe,
						  bool enable, bool old)
{
	struct drm_i915_private *dev_priv = to_i915(dev);
	if (enable) {
		I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));

		if (!ivb_can_enable_err_int(dev))
			return;

		ilk_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
	} else {
		ilk_disable_display_irq(dev_priv, DE_ERR_INT_IVB);

		if (old &&
		    I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {
			DRM_ERROR("uncleared fifo underrun on pipe %c\n",
				  pipe_name(pipe));
		}
	}
}

static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
						  enum pipe pipe, bool enable)
{
	struct drm_i915_private *dev_priv = to_i915(dev);

	if (enable)
		bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);
	else
		bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);
}

static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
					    enum pipe pch_transcoder,
					    bool enable)
{
	struct drm_i915_private *dev_priv = to_i915(dev);
	uint32_t bit = (pch_transcoder == PIPE_A) ?
		       SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;

	if (enable)
		ibx_enable_display_interrupt(dev_priv, bit);
	else
		ibx_disable_display_interrupt(dev_priv, bit);
}

static void cpt_check_pch_fifo_underruns(struct intel_crtc *crtc)
{
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
	enum pipe pch_transcoder = crtc->pipe;
	uint32_t serr_int = I915_READ(SERR_INT);

	lockdep_assert_held(&dev_priv->irq_lock);

	if ((serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) == 0)
		return;

	I915_WRITE(SERR_INT, SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
	POSTING_READ(SERR_INT);

	trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder);
	DRM_ERROR("pch fifo underrun on pch transcoder %c\n",
		  pipe_name(pch_transcoder));
}

static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
					    enum pipe pch_transcoder,
					    bool enable, bool old)
{
	struct drm_i915_private *dev_priv = to_i915(dev);

	if (enable) {
		I915_WRITE(SERR_INT,
			   SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));

		if (!cpt_can_enable_serr_int(dev))
			return;

		ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
	} else {
		ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);

		if (old && I915_READ(SERR_INT) &
		    SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) {
			DRM_ERROR("uncleared pch fifo underrun on pch transcoder %c\n",
				  pipe_name(pch_transcoder));
		}
	}
}

static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
						    enum pipe pipe, bool enable)
{
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
	bool old;

	lockdep_assert_held(&dev_priv->irq_lock);

	old = !crtc->cpu_fifo_underrun_disabled;
	crtc->cpu_fifo_underrun_disabled = !enable;

	if (HAS_GMCH_DISPLAY(dev_priv))
		i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
	else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
		ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
	else if (IS_GEN7(dev_priv))
		ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);
	else if (INTEL_GEN(dev_priv) >= 8)
		broadwell_set_fifo_underrun_reporting(dev, pipe, enable);

	return old;
}

/**
 * intel_set_cpu_fifo_underrun_reporting - set cpu fifo underrrun reporting state
 * @dev_priv: i915 device instance
 * @pipe: (CPU) pipe to set state for
 * @enable: whether underruns should be reported or not
 *
 * This function sets the fifo underrun state for @pipe. It is used in the
 * modeset code to avoid false positives since on many platforms underruns are
 * expected when disabling or enabling the pipe.
 *
 * Notice that on some platforms disabling underrun reports for one pipe
 * disables for all due to shared interrupts. Actual reporting is still per-pipe
 * though.
 *
 * Returns the previous state of underrun reporting.
 */
bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
					   enum pipe pipe, bool enable)
{
	unsigned long flags;
	bool ret;

	spin_lock_irqsave(&dev_priv->irq_lock, flags);
	ret = __intel_set_cpu_fifo_underrun_reporting(&dev_priv->drm, pipe,
						      enable);
	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);

	return ret;
}

/**
 * intel_set_pch_fifo_underrun_reporting - set PCH fifo underrun reporting state
 * @dev_priv: i915 device instance
 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
 * @enable: whether underruns should be reported or not
 *
 * This function makes us disable or enable PCH fifo underruns for a specific
 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
 * underrun reporting for one transcoder may also disable all the other PCH
 * error interruts for the other transcoders, due to the fact that there's just
 * one interrupt mask/enable bit for all the transcoders.
 *
 * Returns the previous state of underrun reporting.
 */
bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
					   enum pipe pch_transcoder,
					   bool enable)
{
	struct intel_crtc *crtc =
		intel_get_crtc_for_pipe(dev_priv, pch_transcoder);
	unsigned long flags;
	bool old;

	/*
	 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
	 * has only one pch transcoder A that all pipes can use. To avoid racy
	 * pch transcoder -> pipe lookups from interrupt code simply store the
	 * underrun statistics in crtc A. Since we never expose this anywhere
	 * nor use it outside of the fifo underrun code here using the "wrong"
	 * crtc on LPT won't cause issues.
	 */

	spin_lock_irqsave(&dev_priv->irq_lock, flags);

	old = !crtc->pch_fifo_underrun_disabled;
	crtc->pch_fifo_underrun_disabled = !enable;

	if (HAS_PCH_IBX(dev_priv))
		ibx_set_fifo_underrun_reporting(&dev_priv->drm,
						pch_transcoder,
						enable);
	else
		cpt_set_fifo_underrun_reporting(&dev_priv->drm,
						pch_transcoder,
						enable, old);

	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
	return old;
}

/**
 * intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt
 * @dev_priv: i915 device instance
 * @pipe: (CPU) pipe to set state for
 *
 * This handles a CPU fifo underrun interrupt, generating an underrun warning
 * into dmesg if underrun reporting is enabled and then disables the underrun
 * interrupt to avoid an irq storm.
 */
void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
					 enum pipe pipe)
{
	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);

	/* We may be called too early in init, thanks BIOS! */
	if (crtc == NULL)
		return;

	/* GMCH can't disable fifo underruns, filter them. */
	if (HAS_GMCH_DISPLAY(dev_priv) &&
	    crtc->cpu_fifo_underrun_disabled)
		return;

	if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) {
		trace_intel_cpu_fifo_underrun(dev_priv, pipe);
		DRM_ERROR("CPU pipe %c FIFO underrun\n",
			  pipe_name(pipe));
	}

	intel_fbc_handle_fifo_underrun_irq(dev_priv);
}

/**
 * intel_pch_fifo_underrun_irq_handler - handle PCH fifo underrun interrupt
 * @dev_priv: i915 device instance
 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
 *
 * This handles a PCH fifo underrun interrupt, generating an underrun warning
 * into dmesg if underrun reporting is enabled and then disables the underrun
 * interrupt to avoid an irq storm.
 */
void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
					 enum pipe pch_transcoder)
{
	if (intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder,
						  false)) {
		trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder);
		DRM_ERROR("PCH transcoder %c FIFO underrun\n",
			  pipe_name(pch_transcoder));
	}
}

/**
 * intel_check_cpu_fifo_underruns - check for CPU fifo underruns immediately
 * @dev_priv: i915 device instance
 *
 * Check for CPU fifo underruns immediately. Useful on IVB/HSW where the shared
 * error interrupt may have been disabled, and so CPU fifo underruns won't
 * necessarily raise an interrupt, and on GMCH platforms where underruns never
 * raise an interrupt.
 */
void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv)
{
	struct intel_crtc *crtc;

	spin_lock_irq(&dev_priv->irq_lock);

	for_each_intel_crtc(&dev_priv->drm, crtc) {
		if (crtc->cpu_fifo_underrun_disabled)
			continue;

		if (HAS_GMCH_DISPLAY(dev_priv))
			i9xx_check_fifo_underruns(crtc);
		else if (IS_GEN7(dev_priv))
			ivybridge_check_fifo_underruns(crtc);
	}

	spin_unlock_irq(&dev_priv->irq_lock);
}

/**
 * intel_check_pch_fifo_underruns - check for PCH fifo underruns immediately
 * @dev_priv: i915 device instance
 *
 * Check for PCH fifo underruns immediately. Useful on CPT/PPT where the shared
 * error interrupt may have been disabled, and so PCH fifo underruns won't
 * necessarily raise an interrupt.
 */
void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv)
{
	struct intel_crtc *crtc;

	spin_lock_irq(&dev_priv->irq_lock);

	for_each_intel_crtc(&dev_priv->drm, crtc) {
		if (crtc->pch_fifo_underrun_disabled)
			continue;

		if (HAS_PCH_CPT(dev_priv))
			cpt_check_pch_fifo_underruns(crtc);
	}

	spin_unlock_irq(&dev_priv->irq_lock);
}
Commit	Line	Data
47339cd9 DV	1	/*
	2	* Copyright © 2014 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* Daniel Vetter <daniel.vetter@ffwll.ch>
	25	*
	26	*/
	27
	28	#include "i915_drv.h"
	29	#include "intel_drv.h"
	30
ef07388e DV	31	/**
	32	* DOC: fifo underrun handling
	33	*
	34	* The i915 driver checks for display fifo underruns using the interrupt signals
	35	* provided by the hardware. This is enabled by default and fairly useful to
	36	* debug display issues, especially watermark settings.
	37	*
	38	* If an underrun is detected this is logged into dmesg. To avoid flooding logs
	39	* and occupying the cpu underrun interrupts are disabled after the first
	40	* occurrence until the next modeset on a given pipe.
	41	*
	42	* Note that underrun detection on gmch platforms is a bit more ugly since there
	43	* is no interrupt (despite that the signalling bit is in the PIPESTAT pipe
	44	* interrupt register). Also on some other platforms underrun interrupts are
	45	* shared, which means that if we detect an underrun we need to disable underrun
	46	* reporting on all pipes.
	47	*
	48	* The code also supports underrun detection on the PCH transcoder.
	49	*/
	50
47339cd9 DV	51	static bool ivb_can_enable_err_int(struct drm_device *dev)
47339cd9 DV	52	{
fac5e23e	53	struct drm_i915_private *dev_priv = to_i915(dev);
47339cd9 DV	54	struct intel_crtc *crtc;
	55	enum pipe pipe;
	56
67520415	57	lockdep_assert_held(&dev_priv->irq_lock);
47339cd9 DV	58
47339cd9 DV	59	for_each_pipe(dev_priv, pipe) {
98187836	60	crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
47339cd9 DV	61
	62	if (crtc->cpu_fifo_underrun_disabled)
	63	return false;
	64	}
	65
	66	return true;
	67	}
	68
	69	static bool cpt_can_enable_serr_int(struct drm_device *dev)
	70	{
fac5e23e	71	struct drm_i915_private *dev_priv = to_i915(dev);
47339cd9 DV	72	enum pipe pipe;
	73	struct intel_crtc *crtc;
	74
67520415	75	lockdep_assert_held(&dev_priv->irq_lock);
47339cd9 DV	76
47339cd9 DV	77	for_each_pipe(dev_priv, pipe) {
98187836	78	crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
47339cd9 DV	79
	80	if (crtc->pch_fifo_underrun_disabled)
	81	return false;
	82	}
	83
	84	return true;
	85	}
	86
aca7b684	87	static void i9xx_check_fifo_underruns(struct intel_crtc *crtc)
47339cd9	88	{
aca7b684	89	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
f0f59a00	90	i915_reg_t reg = PIPESTAT(crtc->pipe);
6b12ca56	91	u32 enable_mask;
47339cd9	92
67520415	93	lockdep_assert_held(&dev_priv->irq_lock);
47339cd9	94
6b12ca56	95	if ((I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0)
aca7b684	96	return;
47339cd9	97
6b12ca56 VS	98	enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe);
6b12ca56 VS	99	I915_WRITE(reg, enable_mask \| PIPE_FIFO_UNDERRUN_STATUS);
aca7b684	100	POSTING_READ(reg);
47339cd9	101
53a7915c	102	trace_intel_cpu_fifo_underrun(dev_priv, crtc->pipe);
aca7b684	103	DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe));
47339cd9 DV	104	}
	105
	106	static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
	107	enum pipe pipe,
	108	bool enable, bool old)
	109	{
fac5e23e	110	struct drm_i915_private *dev_priv = to_i915(dev);
f0f59a00	111	i915_reg_t reg = PIPESTAT(pipe);
47339cd9	112
67520415	113	lockdep_assert_held(&dev_priv->irq_lock);
47339cd9 DV	114
47339cd9 DV	115	if (enable) {
6b12ca56 VS	116	u32 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
	117
	118	I915_WRITE(reg, enable_mask \| PIPE_FIFO_UNDERRUN_STATUS);
47339cd9 DV	119	POSTING_READ(reg);
47339cd9 DV	120	} else {
6b12ca56	121	if (old && I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS)
47339cd9 DV	122	DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
	123	}
	124	}
	125
	126	static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
	127	enum pipe pipe, bool enable)
	128	{
fac5e23e	129	struct drm_i915_private *dev_priv = to_i915(dev);
47339cd9 DV	130	uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
	131	DE_PIPEB_FIFO_UNDERRUN;
	132
	133	if (enable)
fbdedaea	134	ilk_enable_display_irq(dev_priv, bit);
47339cd9	135	else
fbdedaea	136	ilk_disable_display_irq(dev_priv, bit);
47339cd9 DV	137	}
47339cd9 DV	138
aca7b684 VS	139	static void ivybridge_check_fifo_underruns(struct intel_crtc *crtc)
	140	{
	141	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
	142	enum pipe pipe = crtc->pipe;
	143	uint32_t err_int = I915_READ(GEN7_ERR_INT);
	144
67520415	145	lockdep_assert_held(&dev_priv->irq_lock);
aca7b684 VS	146
	147	if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0)
	148	return;
	149
	150	I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
	151	POSTING_READ(GEN7_ERR_INT);
	152
53a7915c	153	trace_intel_cpu_fifo_underrun(dev_priv, pipe);
aca7b684 VS	154	DRM_ERROR("fifo underrun on pipe %c\n", pipe_name(pipe));
	155	}
	156
47339cd9 DV	157	static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
	158	enum pipe pipe,
	159	bool enable, bool old)
	160	{
fac5e23e	161	struct drm_i915_private *dev_priv = to_i915(dev);
47339cd9 DV	162	if (enable) {
	163	I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
	164
	165	if (!ivb_can_enable_err_int(dev))
	166	return;
	167
fbdedaea	168	ilk_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
47339cd9	169	} else {
fbdedaea	170	ilk_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
47339cd9 DV	171
	172	if (old &&
	173	I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {
	174	DRM_ERROR("uncleared fifo underrun on pipe %c\n",
	175	pipe_name(pipe));
	176	}
	177	}
	178	}
	179
	180	static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
	181	enum pipe pipe, bool enable)
	182	{
fac5e23e	183	struct drm_i915_private *dev_priv = to_i915(dev);
47339cd9	184
47339cd9	185	if (enable)
013d3752	186	bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);
47339cd9	187	else
013d3752	188	bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);
47339cd9 DV	189	}
	190
	191	static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
41c32e5d	192	enum pipe pch_transcoder,
47339cd9 DV	193	bool enable)
47339cd9 DV	194	{
fac5e23e	195	struct drm_i915_private *dev_priv = to_i915(dev);
41c32e5d	196	uint32_t bit = (pch_transcoder == PIPE_A) ?
47339cd9 DV	197	SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
	198
	199	if (enable)
	200	ibx_enable_display_interrupt(dev_priv, bit);
	201	else
	202	ibx_disable_display_interrupt(dev_priv, bit);
	203	}
	204
aca7b684 VS	205	static void cpt_check_pch_fifo_underruns(struct intel_crtc *crtc)
	206	{
	207	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
41c32e5d	208	enum pipe pch_transcoder = crtc->pipe;
aca7b684 VS	209	uint32_t serr_int = I915_READ(SERR_INT);
aca7b684 VS	210
67520415	211	lockdep_assert_held(&dev_priv->irq_lock);
aca7b684 VS	212
	213	if ((serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) == 0)
	214	return;
	215
	216	I915_WRITE(SERR_INT, SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
	217	POSTING_READ(SERR_INT);
	218
53a7915c	219	trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder);
41c32e5d VS	220	DRM_ERROR("pch fifo underrun on pch transcoder %c\n",
41c32e5d VS	221	pipe_name(pch_transcoder));
aca7b684 VS	222	}
aca7b684 VS	223
47339cd9	224	static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
41c32e5d	225	enum pipe pch_transcoder,
47339cd9 DV	226	bool enable, bool old)
47339cd9 DV	227	{
fac5e23e	228	struct drm_i915_private *dev_priv = to_i915(dev);
47339cd9 DV	229
	230	if (enable) {
	231	I915_WRITE(SERR_INT,
	232	SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
	233
	234	if (!cpt_can_enable_serr_int(dev))
	235	return;
	236
	237	ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
	238	} else {
	239	ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
	240
	241	if (old && I915_READ(SERR_INT) &
	242	SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) {
41c32e5d VS	243	DRM_ERROR("uncleared pch fifo underrun on pch transcoder %c\n",
41c32e5d VS	244	pipe_name(pch_transcoder));
47339cd9 DV	245	}
	246	}
	247	}
	248
47339cd9 DV	249	static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
	250	enum pipe pipe, bool enable)
	251	{
fac5e23e	252	struct drm_i915_private *dev_priv = to_i915(dev);
98187836	253	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
47339cd9 DV	254	bool old;
47339cd9 DV	255
67520415	256	lockdep_assert_held(&dev_priv->irq_lock);
47339cd9	257
e2af48c6 VS	258	old = !crtc->cpu_fifo_underrun_disabled;
e2af48c6 VS	259	crtc->cpu_fifo_underrun_disabled = !enable;
47339cd9	260
49cff963	261	if (HAS_GMCH_DISPLAY(dev_priv))
47339cd9	262	i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
5db94019	263	else if (IS_GEN5(dev_priv) \|\| IS_GEN6(dev_priv))
47339cd9	264	ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
5db94019	265	else if (IS_GEN7(dev_priv))
47339cd9	266	ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);
4efa16ca	267	else if (INTEL_GEN(dev_priv) >= 8)
47339cd9 DV	268	broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
	269
	270	return old;
	271	}
	272
ef07388e DV	273	/**
	274	* intel_set_cpu_fifo_underrun_reporting - set cpu fifo underrrun reporting state
	275	* @dev_priv: i915 device instance
	276	* @pipe: (CPU) pipe to set state for
	277	* @enable: whether underruns should be reported or not
	278	*
	279	* This function sets the fifo underrun state for @pipe. It is used in the
	280	* modeset code to avoid false positives since on many platforms underruns are
	281	* expected when disabling or enabling the pipe.
	282	*
	283	* Notice that on some platforms disabling underrun reports for one pipe
	284	* disables for all due to shared interrupts. Actual reporting is still per-pipe
	285	* though.
	286	*
	287	* Returns the previous state of underrun reporting.
	288	*/
a72e4c9f	289	bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
47339cd9 DV	290	enum pipe pipe, bool enable)
47339cd9 DV	291	{
47339cd9 DV	292	unsigned long flags;
	293	bool ret;
	294
	295	spin_lock_irqsave(&dev_priv->irq_lock, flags);
91c8a326	296	ret = __intel_set_cpu_fifo_underrun_reporting(&dev_priv->drm, pipe,
a72e4c9f	297	enable);
47339cd9 DV	298	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
	299
	300	return ret;
	301	}
	302
47339cd9	303	/**
ef07388e DV	304	* intel_set_pch_fifo_underrun_reporting - set PCH fifo underrun reporting state
ef07388e DV	305	* @dev_priv: i915 device instance
47339cd9	306	* @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
ef07388e	307	* @enable: whether underruns should be reported or not
47339cd9 DV	308	*
	309	* This function makes us disable or enable PCH fifo underruns for a specific
	310	* PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
	311	* underrun reporting for one transcoder may also disable all the other PCH
	312	* error interruts for the other transcoders, due to the fact that there's just
	313	* one interrupt mask/enable bit for all the transcoders.
	314	*
	315	* Returns the previous state of underrun reporting.
	316	*/
a72e4c9f	317	bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
a2196033	318	enum pipe pch_transcoder,
47339cd9 DV	319	bool enable)
47339cd9 DV	320	{
98187836	321	struct intel_crtc *crtc =
a2196033	322	intel_get_crtc_for_pipe(dev_priv, pch_transcoder);
47339cd9 DV	323	unsigned long flags;
	324	bool old;
	325
	326	/*
	327	* NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
	328	* has only one pch transcoder A that all pipes can use. To avoid racy
	329	* pch transcoder -> pipe lookups from interrupt code simply store the
	330	* underrun statistics in crtc A. Since we never expose this anywhere
	331	* nor use it outside of the fifo underrun code here using the "wrong"
	332	* crtc on LPT won't cause issues.
	333	*/
	334
	335	spin_lock_irqsave(&dev_priv->irq_lock, flags);
	336
e2af48c6 VS	337	old = !crtc->pch_fifo_underrun_disabled;
e2af48c6 VS	338	crtc->pch_fifo_underrun_disabled = !enable;
47339cd9	339
2d1fe073	340	if (HAS_PCH_IBX(dev_priv))
91c8a326 CW	341	ibx_set_fifo_underrun_reporting(&dev_priv->drm,
91c8a326 CW	342	pch_transcoder,
a72e4c9f	343	enable);
47339cd9	344	else
91c8a326 CW	345	cpt_set_fifo_underrun_reporting(&dev_priv->drm,
91c8a326 CW	346	pch_transcoder,
a72e4c9f	347	enable, old);
47339cd9 DV	348
	349	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
	350	return old;
	351	}
1f7247c0	352
ef07388e	353	/**
cea3bf81	354	* intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt
ef07388e DV	355	* @dev_priv: i915 device instance
	356	* @pipe: (CPU) pipe to set state for
	357	*
	358	* This handles a CPU fifo underrun interrupt, generating an underrun warning
	359	* into dmesg if underrun reporting is enabled and then disables the underrun
	360	* interrupt to avoid an irq storm.
	361	*/
1f7247c0 DV	362	void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
	363	enum pipe pipe)
	364	{
98187836	365	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
54fc7c1c CW	366
	367	/* We may be called too early in init, thanks BIOS! */
	368	if (crtc == NULL)
	369	return;
	370
0f239f4c	371	/* GMCH can't disable fifo underruns, filter them. */
2d1fe073	372	if (HAS_GMCH_DISPLAY(dev_priv) &&
e2af48c6	373	crtc->cpu_fifo_underrun_disabled)
0f239f4c DV	374	return;
0f239f4c DV	375
53a7915c VS	376	if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) {
53a7915c VS	377	trace_intel_cpu_fifo_underrun(dev_priv, pipe);
1f7247c0 DV	378	DRM_ERROR("CPU pipe %c FIFO underrun\n",
1f7247c0 DV	379	pipe_name(pipe));
53a7915c	380	}
61a585d6 PZ	381
61a585d6 PZ	382	intel_fbc_handle_fifo_underrun_irq(dev_priv);
1f7247c0 DV	383	}
1f7247c0 DV	384
ef07388e DV	385	/**
	386	* intel_pch_fifo_underrun_irq_handler - handle PCH fifo underrun interrupt
	387	* @dev_priv: i915 device instance
	388	* @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
	389	*
	390	* This handles a PCH fifo underrun interrupt, generating an underrun warning
	391	* into dmesg if underrun reporting is enabled and then disables the underrun
	392	* interrupt to avoid an irq storm.
	393	*/
1f7247c0	394	void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
a2196033	395	enum pipe pch_transcoder)
1f7247c0 DV	396	{
1f7247c0 DV	397	if (intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder,
53a7915c VS	398	false)) {
53a7915c VS	399	trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder);
41c32e5d VS	400	DRM_ERROR("PCH transcoder %c FIFO underrun\n",
41c32e5d VS	401	pipe_name(pch_transcoder));
53a7915c	402	}
1f7247c0	403	}
aca7b684 VS	404
	405	/**
	406	* intel_check_cpu_fifo_underruns - check for CPU fifo underruns immediately
	407	* @dev_priv: i915 device instance
	408	*
	409	* Check for CPU fifo underruns immediately. Useful on IVB/HSW where the shared
	410	* error interrupt may have been disabled, and so CPU fifo underruns won't
	411	* necessarily raise an interrupt, and on GMCH platforms where underruns never
	412	* raise an interrupt.
	413	*/
	414	void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv)
	415	{
	416	struct intel_crtc *crtc;
	417
	418	spin_lock_irq(&dev_priv->irq_lock);
	419
91c8a326	420	for_each_intel_crtc(&dev_priv->drm, crtc) {
aca7b684 VS	421	if (crtc->cpu_fifo_underrun_disabled)
	422	continue;
	423
	424	if (HAS_GMCH_DISPLAY(dev_priv))
	425	i9xx_check_fifo_underruns(crtc);
	426	else if (IS_GEN7(dev_priv))
	427	ivybridge_check_fifo_underruns(crtc);
	428	}
	429
	430	spin_unlock_irq(&dev_priv->irq_lock);
	431	}
	432
	433	/**
	434	* intel_check_pch_fifo_underruns - check for PCH fifo underruns immediately
	435	* @dev_priv: i915 device instance
	436	*
	437	* Check for PCH fifo underruns immediately. Useful on CPT/PPT where the shared
	438	* error interrupt may have been disabled, and so PCH fifo underruns won't
	439	* necessarily raise an interrupt.
	440	*/
	441	void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv)
	442	{
	443	struct intel_crtc *crtc;
	444
	445	spin_lock_irq(&dev_priv->irq_lock);
	446
91c8a326	447	for_each_intel_crtc(&dev_priv->drm, crtc) {
aca7b684 VS	448	if (crtc->pch_fifo_underrun_disabled)
	449	continue;
	450
	451	if (HAS_PCH_CPT(dev_priv))
	452	cpt_check_pch_fifo_underruns(crtc);
	453	}
	454
	455	spin_unlock_irq(&dev_priv->irq_lock);
	456	}