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7ff0ebcc RV |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
94b83957 RV |
24 | /** |
25 | * DOC: Frame Buffer Compression (FBC) | |
26 | * | |
27 | * FBC tries to save memory bandwidth (and so power consumption) by | |
28 | * compressing the amount of memory used by the display. It is total | |
29 | * transparent to user space and completely handled in the kernel. | |
7ff0ebcc RV |
30 | * |
31 | * The benefits of FBC are mostly visible with solid backgrounds and | |
94b83957 RV |
32 | * variation-less patterns. It comes from keeping the memory footprint small |
33 | * and having fewer memory pages opened and accessed for refreshing the display. | |
7ff0ebcc | 34 | * |
94b83957 RV |
35 | * i915 is responsible to reserve stolen memory for FBC and configure its |
36 | * offset on proper registers. The hardware takes care of all | |
37 | * compress/decompress. However there are many known cases where we have to | |
38 | * forcibly disable it to allow proper screen updates. | |
7ff0ebcc RV |
39 | */ |
40 | ||
94b83957 RV |
41 | #include "intel_drv.h" |
42 | #include "i915_drv.h" | |
43 | ||
7ff0ebcc RV |
44 | static void i8xx_fbc_disable(struct drm_device *dev) |
45 | { | |
46 | struct drm_i915_private *dev_priv = dev->dev_private; | |
47 | u32 fbc_ctl; | |
48 | ||
49 | dev_priv->fbc.enabled = false; | |
50 | ||
51 | /* Disable compression */ | |
52 | fbc_ctl = I915_READ(FBC_CONTROL); | |
53 | if ((fbc_ctl & FBC_CTL_EN) == 0) | |
54 | return; | |
55 | ||
56 | fbc_ctl &= ~FBC_CTL_EN; | |
57 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
58 | ||
59 | /* Wait for compressing bit to clear */ | |
60 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { | |
61 | DRM_DEBUG_KMS("FBC idle timed out\n"); | |
62 | return; | |
63 | } | |
64 | ||
65 | DRM_DEBUG_KMS("disabled FBC\n"); | |
66 | } | |
67 | ||
68 | static void i8xx_fbc_enable(struct drm_crtc *crtc) | |
69 | { | |
70 | struct drm_device *dev = crtc->dev; | |
71 | struct drm_i915_private *dev_priv = dev->dev_private; | |
72 | struct drm_framebuffer *fb = crtc->primary->fb; | |
73 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
74 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
75 | int cfb_pitch; | |
76 | int i; | |
77 | u32 fbc_ctl; | |
78 | ||
79 | dev_priv->fbc.enabled = true; | |
80 | ||
60ee5cd2 JN |
81 | /* Note: fbc.threshold == 1 for i8xx */ |
82 | cfb_pitch = dev_priv->fbc.uncompressed_size / FBC_LL_SIZE; | |
7ff0ebcc RV |
83 | if (fb->pitches[0] < cfb_pitch) |
84 | cfb_pitch = fb->pitches[0]; | |
85 | ||
86 | /* FBC_CTL wants 32B or 64B units */ | |
87 | if (IS_GEN2(dev)) | |
88 | cfb_pitch = (cfb_pitch / 32) - 1; | |
89 | else | |
90 | cfb_pitch = (cfb_pitch / 64) - 1; | |
91 | ||
92 | /* Clear old tags */ | |
93 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) | |
94 | I915_WRITE(FBC_TAG + (i * 4), 0); | |
95 | ||
96 | if (IS_GEN4(dev)) { | |
97 | u32 fbc_ctl2; | |
98 | ||
99 | /* Set it up... */ | |
100 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; | |
101 | fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane); | |
102 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); | |
103 | I915_WRITE(FBC_FENCE_OFF, crtc->y); | |
104 | } | |
105 | ||
106 | /* enable it... */ | |
107 | fbc_ctl = I915_READ(FBC_CONTROL); | |
108 | fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT; | |
109 | fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC; | |
110 | if (IS_I945GM(dev)) | |
111 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ | |
112 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; | |
113 | fbc_ctl |= obj->fence_reg; | |
114 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
115 | ||
116 | DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n", | |
117 | cfb_pitch, crtc->y, plane_name(intel_crtc->plane)); | |
118 | } | |
119 | ||
120 | static bool i8xx_fbc_enabled(struct drm_device *dev) | |
121 | { | |
122 | struct drm_i915_private *dev_priv = dev->dev_private; | |
123 | ||
124 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; | |
125 | } | |
126 | ||
127 | static void g4x_fbc_enable(struct drm_crtc *crtc) | |
128 | { | |
129 | struct drm_device *dev = crtc->dev; | |
130 | struct drm_i915_private *dev_priv = dev->dev_private; | |
131 | struct drm_framebuffer *fb = crtc->primary->fb; | |
132 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
133 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
134 | u32 dpfc_ctl; | |
135 | ||
136 | dev_priv->fbc.enabled = true; | |
137 | ||
138 | dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN; | |
139 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) | |
140 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
141 | else | |
142 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
143 | dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; | |
144 | ||
145 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); | |
146 | ||
147 | /* enable it... */ | |
148 | I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
149 | ||
150 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); | |
151 | } | |
152 | ||
153 | static void g4x_fbc_disable(struct drm_device *dev) | |
154 | { | |
155 | struct drm_i915_private *dev_priv = dev->dev_private; | |
156 | u32 dpfc_ctl; | |
157 | ||
158 | dev_priv->fbc.enabled = false; | |
159 | ||
160 | /* Disable compression */ | |
161 | dpfc_ctl = I915_READ(DPFC_CONTROL); | |
162 | if (dpfc_ctl & DPFC_CTL_EN) { | |
163 | dpfc_ctl &= ~DPFC_CTL_EN; | |
164 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); | |
165 | ||
166 | DRM_DEBUG_KMS("disabled FBC\n"); | |
167 | } | |
168 | } | |
169 | ||
170 | static bool g4x_fbc_enabled(struct drm_device *dev) | |
171 | { | |
172 | struct drm_i915_private *dev_priv = dev->dev_private; | |
173 | ||
174 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; | |
175 | } | |
176 | ||
dbef0f15 | 177 | static void intel_fbc_nuke(struct drm_i915_private *dev_priv) |
7ff0ebcc | 178 | { |
dbef0f15 PZ |
179 | I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE); |
180 | POSTING_READ(MSG_FBC_REND_STATE); | |
7ff0ebcc RV |
181 | } |
182 | ||
183 | static void ilk_fbc_enable(struct drm_crtc *crtc) | |
184 | { | |
185 | struct drm_device *dev = crtc->dev; | |
186 | struct drm_i915_private *dev_priv = dev->dev_private; | |
187 | struct drm_framebuffer *fb = crtc->primary->fb; | |
188 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
189 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
190 | u32 dpfc_ctl; | |
ce65e47b | 191 | int threshold = dev_priv->fbc.threshold; |
7ff0ebcc RV |
192 | |
193 | dev_priv->fbc.enabled = true; | |
194 | ||
195 | dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane); | |
196 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) | |
ce65e47b | 197 | threshold++; |
7ff0ebcc | 198 | |
ce65e47b | 199 | switch (threshold) { |
7ff0ebcc RV |
200 | case 4: |
201 | case 3: | |
202 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; | |
203 | break; | |
204 | case 2: | |
205 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
206 | break; | |
207 | case 1: | |
208 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
209 | break; | |
210 | } | |
211 | dpfc_ctl |= DPFC_CTL_FENCE_EN; | |
212 | if (IS_GEN5(dev)) | |
213 | dpfc_ctl |= obj->fence_reg; | |
214 | ||
215 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); | |
216 | I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID); | |
217 | /* enable it... */ | |
218 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
219 | ||
220 | if (IS_GEN6(dev)) { | |
221 | I915_WRITE(SNB_DPFC_CTL_SA, | |
222 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); | |
223 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); | |
7ff0ebcc RV |
224 | } |
225 | ||
dbef0f15 PZ |
226 | intel_fbc_nuke(dev_priv); |
227 | ||
7ff0ebcc RV |
228 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); |
229 | } | |
230 | ||
231 | static void ilk_fbc_disable(struct drm_device *dev) | |
232 | { | |
233 | struct drm_i915_private *dev_priv = dev->dev_private; | |
234 | u32 dpfc_ctl; | |
235 | ||
236 | dev_priv->fbc.enabled = false; | |
237 | ||
238 | /* Disable compression */ | |
239 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
240 | if (dpfc_ctl & DPFC_CTL_EN) { | |
241 | dpfc_ctl &= ~DPFC_CTL_EN; | |
242 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); | |
243 | ||
244 | DRM_DEBUG_KMS("disabled FBC\n"); | |
245 | } | |
246 | } | |
247 | ||
248 | static bool ilk_fbc_enabled(struct drm_device *dev) | |
249 | { | |
250 | struct drm_i915_private *dev_priv = dev->dev_private; | |
251 | ||
252 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; | |
253 | } | |
254 | ||
255 | static void gen7_fbc_enable(struct drm_crtc *crtc) | |
256 | { | |
257 | struct drm_device *dev = crtc->dev; | |
258 | struct drm_i915_private *dev_priv = dev->dev_private; | |
259 | struct drm_framebuffer *fb = crtc->primary->fb; | |
260 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
261 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
262 | u32 dpfc_ctl; | |
ce65e47b | 263 | int threshold = dev_priv->fbc.threshold; |
7ff0ebcc RV |
264 | |
265 | dev_priv->fbc.enabled = true; | |
266 | ||
d8514d63 PZ |
267 | dpfc_ctl = 0; |
268 | if (IS_IVYBRIDGE(dev)) | |
269 | dpfc_ctl |= IVB_DPFC_CTL_PLANE(intel_crtc->plane); | |
270 | ||
7ff0ebcc | 271 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
ce65e47b | 272 | threshold++; |
7ff0ebcc | 273 | |
ce65e47b | 274 | switch (threshold) { |
7ff0ebcc RV |
275 | case 4: |
276 | case 3: | |
277 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; | |
278 | break; | |
279 | case 2: | |
280 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
281 | break; | |
282 | case 1: | |
283 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
284 | break; | |
285 | } | |
286 | ||
287 | dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; | |
288 | ||
289 | if (dev_priv->fbc.false_color) | |
290 | dpfc_ctl |= FBC_CTL_FALSE_COLOR; | |
291 | ||
292 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
293 | ||
294 | if (IS_IVYBRIDGE(dev)) { | |
295 | /* WaFbcAsynchFlipDisableFbcQueue:ivb */ | |
296 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
297 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
298 | ILK_FBCQ_DIS); | |
299 | } else { | |
300 | /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ | |
301 | I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe), | |
302 | I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) | | |
303 | HSW_FBCQ_DIS); | |
304 | } | |
305 | ||
306 | I915_WRITE(SNB_DPFC_CTL_SA, | |
307 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); | |
308 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); | |
309 | ||
dbef0f15 | 310 | intel_fbc_nuke(dev_priv); |
7ff0ebcc RV |
311 | |
312 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); | |
313 | } | |
314 | ||
94b83957 RV |
315 | /** |
316 | * intel_fbc_enabled - Is FBC enabled? | |
317 | * @dev: the drm_device | |
318 | * | |
319 | * This function is used to verify the current state of FBC. | |
320 | * FIXME: This should be tracked in the plane config eventually | |
321 | * instead of queried at runtime for most callers. | |
322 | */ | |
7ff0ebcc RV |
323 | bool intel_fbc_enabled(struct drm_device *dev) |
324 | { | |
325 | struct drm_i915_private *dev_priv = dev->dev_private; | |
326 | ||
327 | return dev_priv->fbc.enabled; | |
328 | } | |
329 | ||
7ff0ebcc RV |
330 | static void intel_fbc_work_fn(struct work_struct *__work) |
331 | { | |
332 | struct intel_fbc_work *work = | |
333 | container_of(to_delayed_work(__work), | |
334 | struct intel_fbc_work, work); | |
335 | struct drm_device *dev = work->crtc->dev; | |
336 | struct drm_i915_private *dev_priv = dev->dev_private; | |
337 | ||
338 | mutex_lock(&dev->struct_mutex); | |
339 | if (work == dev_priv->fbc.fbc_work) { | |
340 | /* Double check that we haven't switched fb without cancelling | |
341 | * the prior work. | |
342 | */ | |
343 | if (work->crtc->primary->fb == work->fb) { | |
344 | dev_priv->display.enable_fbc(work->crtc); | |
345 | ||
e35fef21 | 346 | dev_priv->fbc.crtc = to_intel_crtc(work->crtc); |
7ff0ebcc RV |
347 | dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id; |
348 | dev_priv->fbc.y = work->crtc->y; | |
349 | } | |
350 | ||
351 | dev_priv->fbc.fbc_work = NULL; | |
352 | } | |
353 | mutex_unlock(&dev->struct_mutex); | |
354 | ||
355 | kfree(work); | |
356 | } | |
357 | ||
358 | static void intel_fbc_cancel_work(struct drm_i915_private *dev_priv) | |
359 | { | |
360 | if (dev_priv->fbc.fbc_work == NULL) | |
361 | return; | |
362 | ||
363 | DRM_DEBUG_KMS("cancelling pending FBC enable\n"); | |
364 | ||
365 | /* Synchronisation is provided by struct_mutex and checking of | |
366 | * dev_priv->fbc.fbc_work, so we can perform the cancellation | |
367 | * entirely asynchronously. | |
368 | */ | |
369 | if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work)) | |
370 | /* tasklet was killed before being run, clean up */ | |
371 | kfree(dev_priv->fbc.fbc_work); | |
372 | ||
373 | /* Mark the work as no longer wanted so that if it does | |
374 | * wake-up (because the work was already running and waiting | |
375 | * for our mutex), it will discover that is no longer | |
376 | * necessary to run. | |
377 | */ | |
378 | dev_priv->fbc.fbc_work = NULL; | |
379 | } | |
380 | ||
381 | static void intel_fbc_enable(struct drm_crtc *crtc) | |
382 | { | |
383 | struct intel_fbc_work *work; | |
384 | struct drm_device *dev = crtc->dev; | |
385 | struct drm_i915_private *dev_priv = dev->dev_private; | |
386 | ||
387 | if (!dev_priv->display.enable_fbc) | |
388 | return; | |
389 | ||
390 | intel_fbc_cancel_work(dev_priv); | |
391 | ||
392 | work = kzalloc(sizeof(*work), GFP_KERNEL); | |
393 | if (work == NULL) { | |
394 | DRM_ERROR("Failed to allocate FBC work structure\n"); | |
395 | dev_priv->display.enable_fbc(crtc); | |
396 | return; | |
397 | } | |
398 | ||
399 | work->crtc = crtc; | |
400 | work->fb = crtc->primary->fb; | |
401 | INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); | |
402 | ||
403 | dev_priv->fbc.fbc_work = work; | |
404 | ||
405 | /* Delay the actual enabling to let pageflipping cease and the | |
406 | * display to settle before starting the compression. Note that | |
407 | * this delay also serves a second purpose: it allows for a | |
408 | * vblank to pass after disabling the FBC before we attempt | |
409 | * to modify the control registers. | |
410 | * | |
411 | * A more complicated solution would involve tracking vblanks | |
412 | * following the termination of the page-flipping sequence | |
413 | * and indeed performing the enable as a co-routine and not | |
414 | * waiting synchronously upon the vblank. | |
415 | * | |
416 | * WaFbcWaitForVBlankBeforeEnable:ilk,snb | |
417 | */ | |
418 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); | |
419 | } | |
420 | ||
94b83957 RV |
421 | /** |
422 | * intel_fbc_disable - disable FBC | |
423 | * @dev: the drm_device | |
424 | * | |
425 | * This function disables FBC. | |
426 | */ | |
7ff0ebcc RV |
427 | void intel_fbc_disable(struct drm_device *dev) |
428 | { | |
429 | struct drm_i915_private *dev_priv = dev->dev_private; | |
430 | ||
431 | intel_fbc_cancel_work(dev_priv); | |
432 | ||
433 | if (!dev_priv->display.disable_fbc) | |
434 | return; | |
435 | ||
436 | dev_priv->display.disable_fbc(dev); | |
e35fef21 | 437 | dev_priv->fbc.crtc = NULL; |
7ff0ebcc RV |
438 | } |
439 | ||
2e8144a5 PZ |
440 | const char *intel_no_fbc_reason_str(enum no_fbc_reason reason) |
441 | { | |
442 | switch (reason) { | |
443 | case FBC_OK: | |
444 | return "FBC enabled but currently disabled in hardware"; | |
445 | case FBC_UNSUPPORTED: | |
446 | return "unsupported by this chipset"; | |
447 | case FBC_NO_OUTPUT: | |
448 | return "no output"; | |
449 | case FBC_STOLEN_TOO_SMALL: | |
450 | return "not enough stolen memory"; | |
451 | case FBC_UNSUPPORTED_MODE: | |
452 | return "mode incompatible with compression"; | |
453 | case FBC_MODE_TOO_LARGE: | |
454 | return "mode too large for compression"; | |
455 | case FBC_BAD_PLANE: | |
456 | return "FBC unsupported on plane"; | |
457 | case FBC_NOT_TILED: | |
458 | return "framebuffer not tiled or fenced"; | |
459 | case FBC_MULTIPLE_PIPES: | |
460 | return "more than one pipe active"; | |
461 | case FBC_MODULE_PARAM: | |
462 | return "disabled per module param"; | |
463 | case FBC_CHIP_DEFAULT: | |
464 | return "disabled per chip default"; | |
465 | case FBC_ROTATION: | |
466 | return "rotation unsupported"; | |
467 | default: | |
468 | MISSING_CASE(reason); | |
469 | return "unknown reason"; | |
470 | } | |
471 | } | |
472 | ||
473 | static void set_no_fbc_reason(struct drm_i915_private *dev_priv, | |
7ff0ebcc RV |
474 | enum no_fbc_reason reason) |
475 | { | |
476 | if (dev_priv->fbc.no_fbc_reason == reason) | |
2e8144a5 | 477 | return; |
7ff0ebcc RV |
478 | |
479 | dev_priv->fbc.no_fbc_reason = reason; | |
2e8144a5 | 480 | DRM_DEBUG_KMS("Disabling FBC: %s\n", intel_no_fbc_reason_str(reason)); |
7ff0ebcc RV |
481 | } |
482 | ||
95106753 PZ |
483 | static struct drm_crtc *intel_fbc_find_crtc(struct drm_i915_private *dev_priv) |
484 | { | |
95106753 | 485 | struct drm_crtc *crtc = NULL, *tmp_crtc; |
68b92147 | 486 | enum pipe pipe; |
e489e38e | 487 | bool pipe_a_only = false, one_pipe_only = false; |
68b92147 PZ |
488 | |
489 | if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) | |
490 | pipe_a_only = true; | |
e489e38e PZ |
491 | else if (INTEL_INFO(dev_priv)->gen <= 4) |
492 | one_pipe_only = true; | |
68b92147 PZ |
493 | |
494 | for_each_pipe(dev_priv, pipe) { | |
495 | tmp_crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
95106753 | 496 | |
95106753 | 497 | if (intel_crtc_active(tmp_crtc) && |
b70709a6 | 498 | to_intel_plane_state(tmp_crtc->primary->state)->visible) { |
e489e38e | 499 | if (one_pipe_only && crtc) { |
2e8144a5 | 500 | set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES); |
95106753 PZ |
501 | return NULL; |
502 | } | |
503 | crtc = tmp_crtc; | |
504 | } | |
68b92147 PZ |
505 | |
506 | if (pipe_a_only) | |
507 | break; | |
95106753 PZ |
508 | } |
509 | ||
510 | if (!crtc || crtc->primary->fb == NULL) { | |
2e8144a5 | 511 | set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT); |
95106753 PZ |
512 | return NULL; |
513 | } | |
514 | ||
515 | return crtc; | |
516 | } | |
517 | ||
fc786728 PZ |
518 | static int find_compression_threshold(struct drm_device *dev, |
519 | struct drm_mm_node *node, | |
520 | int size, | |
521 | int fb_cpp) | |
522 | { | |
523 | struct drm_i915_private *dev_priv = dev->dev_private; | |
524 | int compression_threshold = 1; | |
525 | int ret; | |
526 | ||
527 | /* HACK: This code depends on what we will do in *_enable_fbc. If that | |
528 | * code changes, this code needs to change as well. | |
529 | * | |
530 | * The enable_fbc code will attempt to use one of our 2 compression | |
531 | * thresholds, therefore, in that case, we only have 1 resort. | |
532 | */ | |
533 | ||
534 | /* Try to over-allocate to reduce reallocations and fragmentation. */ | |
535 | ret = i915_gem_stolen_insert_node(dev_priv, node, size <<= 1, 4096); | |
536 | if (ret == 0) | |
537 | return compression_threshold; | |
538 | ||
539 | again: | |
540 | /* HW's ability to limit the CFB is 1:4 */ | |
541 | if (compression_threshold > 4 || | |
542 | (fb_cpp == 2 && compression_threshold == 2)) | |
543 | return 0; | |
544 | ||
545 | ret = i915_gem_stolen_insert_node(dev_priv, node, size >>= 1, 4096); | |
546 | if (ret && INTEL_INFO(dev)->gen <= 4) { | |
547 | return 0; | |
548 | } else if (ret) { | |
549 | compression_threshold <<= 1; | |
550 | goto again; | |
551 | } else { | |
552 | return compression_threshold; | |
553 | } | |
554 | } | |
555 | ||
556 | static int intel_fbc_alloc_cfb(struct drm_device *dev, int size, int fb_cpp) | |
557 | { | |
558 | struct drm_i915_private *dev_priv = dev->dev_private; | |
559 | struct drm_mm_node *uninitialized_var(compressed_llb); | |
560 | int ret; | |
561 | ||
562 | ret = find_compression_threshold(dev, &dev_priv->fbc.compressed_fb, | |
563 | size, fb_cpp); | |
564 | if (!ret) | |
565 | goto err_llb; | |
566 | else if (ret > 1) { | |
567 | DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n"); | |
568 | ||
569 | } | |
570 | ||
571 | dev_priv->fbc.threshold = ret; | |
572 | ||
573 | if (INTEL_INFO(dev_priv)->gen >= 5) | |
574 | I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start); | |
575 | else if (IS_GM45(dev)) { | |
576 | I915_WRITE(DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start); | |
577 | } else { | |
578 | compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL); | |
579 | if (!compressed_llb) | |
580 | goto err_fb; | |
581 | ||
582 | ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb, | |
583 | 4096, 4096); | |
584 | if (ret) | |
585 | goto err_fb; | |
586 | ||
587 | dev_priv->fbc.compressed_llb = compressed_llb; | |
588 | ||
589 | I915_WRITE(FBC_CFB_BASE, | |
590 | dev_priv->mm.stolen_base + dev_priv->fbc.compressed_fb.start); | |
591 | I915_WRITE(FBC_LL_BASE, | |
592 | dev_priv->mm.stolen_base + compressed_llb->start); | |
593 | } | |
594 | ||
595 | dev_priv->fbc.uncompressed_size = size; | |
596 | ||
597 | DRM_DEBUG_KMS("reserved %d bytes of contiguous stolen space for FBC\n", | |
598 | size); | |
599 | ||
600 | return 0; | |
601 | ||
602 | err_fb: | |
603 | kfree(compressed_llb); | |
604 | i915_gem_stolen_remove_node(dev_priv, &dev_priv->fbc.compressed_fb); | |
605 | err_llb: | |
606 | pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size); | |
607 | return -ENOSPC; | |
608 | } | |
609 | ||
610 | void intel_fbc_cleanup_cfb(struct drm_device *dev) | |
611 | { | |
612 | struct drm_i915_private *dev_priv = dev->dev_private; | |
613 | ||
614 | if (dev_priv->fbc.uncompressed_size == 0) | |
615 | return; | |
616 | ||
617 | i915_gem_stolen_remove_node(dev_priv, &dev_priv->fbc.compressed_fb); | |
618 | ||
619 | if (dev_priv->fbc.compressed_llb) { | |
620 | i915_gem_stolen_remove_node(dev_priv, | |
621 | dev_priv->fbc.compressed_llb); | |
622 | kfree(dev_priv->fbc.compressed_llb); | |
623 | } | |
624 | ||
625 | dev_priv->fbc.uncompressed_size = 0; | |
626 | } | |
627 | ||
628 | static int intel_fbc_setup_cfb(struct drm_device *dev, int size, int fb_cpp) | |
629 | { | |
630 | struct drm_i915_private *dev_priv = dev->dev_private; | |
631 | ||
632 | if (size <= dev_priv->fbc.uncompressed_size) | |
633 | return 0; | |
634 | ||
635 | /* Release any current block */ | |
636 | intel_fbc_cleanup_cfb(dev); | |
637 | ||
638 | return intel_fbc_alloc_cfb(dev, size, fb_cpp); | |
639 | } | |
640 | ||
7ff0ebcc RV |
641 | /** |
642 | * intel_fbc_update - enable/disable FBC as needed | |
643 | * @dev: the drm_device | |
644 | * | |
645 | * Set up the framebuffer compression hardware at mode set time. We | |
646 | * enable it if possible: | |
647 | * - plane A only (on pre-965) | |
648 | * - no pixel mulitply/line duplication | |
649 | * - no alpha buffer discard | |
650 | * - no dual wide | |
651 | * - framebuffer <= max_hdisplay in width, max_vdisplay in height | |
652 | * | |
653 | * We can't assume that any compression will take place (worst case), | |
654 | * so the compressed buffer has to be the same size as the uncompressed | |
655 | * one. It also must reside (along with the line length buffer) in | |
656 | * stolen memory. | |
657 | * | |
658 | * We need to enable/disable FBC on a global basis. | |
659 | */ | |
660 | void intel_fbc_update(struct drm_device *dev) | |
661 | { | |
662 | struct drm_i915_private *dev_priv = dev->dev_private; | |
95106753 | 663 | struct drm_crtc *crtc = NULL; |
7ff0ebcc RV |
664 | struct intel_crtc *intel_crtc; |
665 | struct drm_framebuffer *fb; | |
666 | struct drm_i915_gem_object *obj; | |
667 | const struct drm_display_mode *adjusted_mode; | |
668 | unsigned int max_width, max_height; | |
669 | ||
104618b3 | 670 | if (!HAS_FBC(dev)) |
7ff0ebcc | 671 | return; |
7ff0ebcc | 672 | |
bd49234b YZ |
673 | /* disable framebuffer compression in vGPU */ |
674 | if (intel_vgpu_active(dev)) | |
675 | i915.enable_fbc = 0; | |
676 | ||
7cc65746 | 677 | if (i915.enable_fbc < 0) { |
2e8144a5 | 678 | set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT); |
7cc65746 PZ |
679 | goto out_disable; |
680 | } | |
681 | ||
ab585dea | 682 | if (!i915.enable_fbc) { |
2e8144a5 | 683 | set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM); |
7cc65746 | 684 | goto out_disable; |
7ff0ebcc RV |
685 | } |
686 | ||
687 | /* | |
688 | * If FBC is already on, we just have to verify that we can | |
689 | * keep it that way... | |
690 | * Need to disable if: | |
691 | * - more than one pipe is active | |
692 | * - changing FBC params (stride, fence, mode) | |
693 | * - new fb is too large to fit in compressed buffer | |
694 | * - going to an unsupported config (interlace, pixel multiply, etc.) | |
695 | */ | |
95106753 PZ |
696 | crtc = intel_fbc_find_crtc(dev_priv); |
697 | if (!crtc) | |
7ff0ebcc | 698 | goto out_disable; |
7ff0ebcc RV |
699 | |
700 | intel_crtc = to_intel_crtc(crtc); | |
701 | fb = crtc->primary->fb; | |
702 | obj = intel_fb_obj(fb); | |
6e3c9717 | 703 | adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
7ff0ebcc | 704 | |
7ff0ebcc RV |
705 | if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) || |
706 | (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) { | |
2e8144a5 | 707 | set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE); |
7ff0ebcc RV |
708 | goto out_disable; |
709 | } | |
710 | ||
711 | if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) { | |
712 | max_width = 4096; | |
713 | max_height = 4096; | |
714 | } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { | |
715 | max_width = 4096; | |
716 | max_height = 2048; | |
717 | } else { | |
718 | max_width = 2048; | |
719 | max_height = 1536; | |
720 | } | |
6e3c9717 ACO |
721 | if (intel_crtc->config->pipe_src_w > max_width || |
722 | intel_crtc->config->pipe_src_h > max_height) { | |
2e8144a5 | 723 | set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE); |
7ff0ebcc RV |
724 | goto out_disable; |
725 | } | |
726 | if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) && | |
727 | intel_crtc->plane != PLANE_A) { | |
2e8144a5 | 728 | set_no_fbc_reason(dev_priv, FBC_BAD_PLANE); |
7ff0ebcc RV |
729 | goto out_disable; |
730 | } | |
731 | ||
732 | /* The use of a CPU fence is mandatory in order to detect writes | |
733 | * by the CPU to the scanout and trigger updates to the FBC. | |
734 | */ | |
735 | if (obj->tiling_mode != I915_TILING_X || | |
736 | obj->fence_reg == I915_FENCE_REG_NONE) { | |
2e8144a5 | 737 | set_no_fbc_reason(dev_priv, FBC_NOT_TILED); |
7ff0ebcc RV |
738 | goto out_disable; |
739 | } | |
740 | if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && | |
8e7d688b | 741 | crtc->primary->state->rotation != BIT(DRM_ROTATE_0)) { |
2e8144a5 | 742 | set_no_fbc_reason(dev_priv, FBC_ROTATION); |
7ff0ebcc RV |
743 | goto out_disable; |
744 | } | |
745 | ||
746 | /* If the kernel debugger is active, always disable compression */ | |
747 | if (in_dbg_master()) | |
748 | goto out_disable; | |
749 | ||
fc786728 PZ |
750 | if (intel_fbc_setup_cfb(dev, obj->base.size, |
751 | drm_format_plane_cpp(fb->pixel_format, 0))) { | |
2e8144a5 | 752 | set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL); |
7ff0ebcc RV |
753 | goto out_disable; |
754 | } | |
755 | ||
756 | /* If the scanout has not changed, don't modify the FBC settings. | |
757 | * Note that we make the fundamental assumption that the fb->obj | |
758 | * cannot be unpinned (and have its GTT offset and fence revoked) | |
759 | * without first being decoupled from the scanout and FBC disabled. | |
760 | */ | |
e35fef21 | 761 | if (dev_priv->fbc.crtc == intel_crtc && |
7ff0ebcc RV |
762 | dev_priv->fbc.fb_id == fb->base.id && |
763 | dev_priv->fbc.y == crtc->y) | |
764 | return; | |
765 | ||
766 | if (intel_fbc_enabled(dev)) { | |
767 | /* We update FBC along two paths, after changing fb/crtc | |
768 | * configuration (modeswitching) and after page-flipping | |
769 | * finishes. For the latter, we know that not only did | |
770 | * we disable the FBC at the start of the page-flip | |
771 | * sequence, but also more than one vblank has passed. | |
772 | * | |
773 | * For the former case of modeswitching, it is possible | |
774 | * to switch between two FBC valid configurations | |
775 | * instantaneously so we do need to disable the FBC | |
776 | * before we can modify its control registers. We also | |
777 | * have to wait for the next vblank for that to take | |
778 | * effect. However, since we delay enabling FBC we can | |
779 | * assume that a vblank has passed since disabling and | |
780 | * that we can safely alter the registers in the deferred | |
781 | * callback. | |
782 | * | |
783 | * In the scenario that we go from a valid to invalid | |
784 | * and then back to valid FBC configuration we have | |
785 | * no strict enforcement that a vblank occurred since | |
786 | * disabling the FBC. However, along all current pipe | |
787 | * disabling paths we do need to wait for a vblank at | |
788 | * some point. And we wait before enabling FBC anyway. | |
789 | */ | |
790 | DRM_DEBUG_KMS("disabling active FBC for update\n"); | |
791 | intel_fbc_disable(dev); | |
792 | } | |
793 | ||
794 | intel_fbc_enable(crtc); | |
795 | dev_priv->fbc.no_fbc_reason = FBC_OK; | |
796 | return; | |
797 | ||
798 | out_disable: | |
799 | /* Multiple disables should be harmless */ | |
800 | if (intel_fbc_enabled(dev)) { | |
801 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); | |
802 | intel_fbc_disable(dev); | |
803 | } | |
fc786728 | 804 | intel_fbc_cleanup_cfb(dev); |
7ff0ebcc RV |
805 | } |
806 | ||
dbef0f15 PZ |
807 | void intel_fbc_invalidate(struct drm_i915_private *dev_priv, |
808 | unsigned int frontbuffer_bits, | |
809 | enum fb_op_origin origin) | |
810 | { | |
811 | struct drm_device *dev = dev_priv->dev; | |
812 | unsigned int fbc_bits; | |
813 | ||
814 | if (origin == ORIGIN_GTT) | |
815 | return; | |
816 | ||
817 | if (dev_priv->fbc.enabled) | |
818 | fbc_bits = INTEL_FRONTBUFFER_PRIMARY(dev_priv->fbc.crtc->pipe); | |
819 | else if (dev_priv->fbc.fbc_work) | |
820 | fbc_bits = INTEL_FRONTBUFFER_PRIMARY( | |
821 | to_intel_crtc(dev_priv->fbc.fbc_work->crtc)->pipe); | |
822 | else | |
823 | fbc_bits = dev_priv->fbc.possible_framebuffer_bits; | |
824 | ||
825 | dev_priv->fbc.busy_bits |= (fbc_bits & frontbuffer_bits); | |
826 | ||
827 | if (dev_priv->fbc.busy_bits) | |
828 | intel_fbc_disable(dev); | |
829 | } | |
830 | ||
831 | void intel_fbc_flush(struct drm_i915_private *dev_priv, | |
832 | unsigned int frontbuffer_bits) | |
833 | { | |
834 | struct drm_device *dev = dev_priv->dev; | |
835 | ||
836 | if (!dev_priv->fbc.busy_bits) | |
837 | return; | |
838 | ||
839 | dev_priv->fbc.busy_bits &= ~frontbuffer_bits; | |
840 | ||
841 | if (!dev_priv->fbc.busy_bits) | |
842 | intel_fbc_update(dev); | |
843 | } | |
844 | ||
94b83957 RV |
845 | /** |
846 | * intel_fbc_init - Initialize FBC | |
847 | * @dev_priv: the i915 device | |
848 | * | |
849 | * This function might be called during PM init process. | |
850 | */ | |
7ff0ebcc RV |
851 | void intel_fbc_init(struct drm_i915_private *dev_priv) |
852 | { | |
dbef0f15 PZ |
853 | enum pipe pipe; |
854 | ||
7ff0ebcc RV |
855 | if (!HAS_FBC(dev_priv)) { |
856 | dev_priv->fbc.enabled = false; | |
104618b3 | 857 | dev_priv->fbc.no_fbc_reason = FBC_UNSUPPORTED; |
7ff0ebcc RV |
858 | return; |
859 | } | |
860 | ||
dbef0f15 PZ |
861 | for_each_pipe(dev_priv, pipe) { |
862 | dev_priv->fbc.possible_framebuffer_bits |= | |
863 | INTEL_FRONTBUFFER_PRIMARY(pipe); | |
864 | ||
865 | if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) | |
866 | break; | |
867 | } | |
868 | ||
7ff0ebcc RV |
869 | if (INTEL_INFO(dev_priv)->gen >= 7) { |
870 | dev_priv->display.fbc_enabled = ilk_fbc_enabled; | |
871 | dev_priv->display.enable_fbc = gen7_fbc_enable; | |
872 | dev_priv->display.disable_fbc = ilk_fbc_disable; | |
873 | } else if (INTEL_INFO(dev_priv)->gen >= 5) { | |
874 | dev_priv->display.fbc_enabled = ilk_fbc_enabled; | |
875 | dev_priv->display.enable_fbc = ilk_fbc_enable; | |
876 | dev_priv->display.disable_fbc = ilk_fbc_disable; | |
877 | } else if (IS_GM45(dev_priv)) { | |
878 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; | |
879 | dev_priv->display.enable_fbc = g4x_fbc_enable; | |
880 | dev_priv->display.disable_fbc = g4x_fbc_disable; | |
881 | } else { | |
882 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; | |
883 | dev_priv->display.enable_fbc = i8xx_fbc_enable; | |
884 | dev_priv->display.disable_fbc = i8xx_fbc_disable; | |
885 | ||
886 | /* This value was pulled out of someone's hat */ | |
887 | I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT); | |
888 | } | |
889 | ||
890 | dev_priv->fbc.enabled = dev_priv->display.fbc_enabled(dev_priv->dev); | |
891 | } |