Commit | Line | Data |
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7ff0ebcc RV |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
94b83957 RV |
24 | /** |
25 | * DOC: Frame Buffer Compression (FBC) | |
26 | * | |
27 | * FBC tries to save memory bandwidth (and so power consumption) by | |
28 | * compressing the amount of memory used by the display. It is total | |
29 | * transparent to user space and completely handled in the kernel. | |
7ff0ebcc RV |
30 | * |
31 | * The benefits of FBC are mostly visible with solid backgrounds and | |
94b83957 RV |
32 | * variation-less patterns. It comes from keeping the memory footprint small |
33 | * and having fewer memory pages opened and accessed for refreshing the display. | |
7ff0ebcc | 34 | * |
94b83957 RV |
35 | * i915 is responsible to reserve stolen memory for FBC and configure its |
36 | * offset on proper registers. The hardware takes care of all | |
37 | * compress/decompress. However there are many known cases where we have to | |
38 | * forcibly disable it to allow proper screen updates. | |
7ff0ebcc RV |
39 | */ |
40 | ||
94b83957 RV |
41 | #include "intel_drv.h" |
42 | #include "i915_drv.h" | |
43 | ||
9f218336 PZ |
44 | static inline bool fbc_supported(struct drm_i915_private *dev_priv) |
45 | { | |
8c40074c | 46 | return HAS_FBC(dev_priv); |
9f218336 PZ |
47 | } |
48 | ||
57105022 PZ |
49 | static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv) |
50 | { | |
5697d60f | 51 | return IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8; |
57105022 PZ |
52 | } |
53 | ||
e6cd6dc1 PZ |
54 | static inline bool fbc_on_plane_a_only(struct drm_i915_private *dev_priv) |
55 | { | |
5697d60f | 56 | return INTEL_GEN(dev_priv) < 4; |
e6cd6dc1 PZ |
57 | } |
58 | ||
010cf73d PZ |
59 | static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv) |
60 | { | |
5697d60f | 61 | return INTEL_GEN(dev_priv) <= 3; |
010cf73d PZ |
62 | } |
63 | ||
2db3366b PZ |
64 | /* |
65 | * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the | |
66 | * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's | |
67 | * origin so the x and y offsets can actually fit the registers. As a | |
68 | * consequence, the fence doesn't really start exactly at the display plane | |
69 | * address we program because it starts at the real start of the buffer, so we | |
70 | * have to take this into consideration here. | |
71 | */ | |
72 | static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc) | |
73 | { | |
74 | return crtc->base.y - crtc->adjusted_y; | |
75 | } | |
76 | ||
c5ecd469 PZ |
77 | /* |
78 | * For SKL+, the plane source size used by the hardware is based on the value we | |
79 | * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value | |
80 | * we wrote to PIPESRC. | |
81 | */ | |
aaf78d27 | 82 | static void intel_fbc_get_plane_source_size(struct intel_fbc_state_cache *cache, |
c5ecd469 PZ |
83 | int *width, int *height) |
84 | { | |
c5ecd469 | 85 | if (width) |
73714c05 | 86 | *width = cache->plane.src_w; |
c5ecd469 | 87 | if (height) |
73714c05 | 88 | *height = cache->plane.src_h; |
c5ecd469 PZ |
89 | } |
90 | ||
aaf78d27 PZ |
91 | static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv, |
92 | struct intel_fbc_state_cache *cache) | |
c5ecd469 | 93 | { |
c5ecd469 PZ |
94 | int lines; |
95 | ||
aaf78d27 | 96 | intel_fbc_get_plane_source_size(cache, NULL, &lines); |
79f2624b | 97 | if (INTEL_GEN(dev_priv) == 7) |
c5ecd469 | 98 | lines = min(lines, 2048); |
79f2624b PZ |
99 | else if (INTEL_GEN(dev_priv) >= 8) |
100 | lines = min(lines, 2560); | |
c5ecd469 PZ |
101 | |
102 | /* Hardware needs the full buffer stride, not just the active area. */ | |
aaf78d27 | 103 | return lines * cache->fb.stride; |
c5ecd469 PZ |
104 | } |
105 | ||
0e631adc | 106 | static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv) |
7ff0ebcc | 107 | { |
7ff0ebcc RV |
108 | u32 fbc_ctl; |
109 | ||
7ff0ebcc RV |
110 | /* Disable compression */ |
111 | fbc_ctl = I915_READ(FBC_CONTROL); | |
112 | if ((fbc_ctl & FBC_CTL_EN) == 0) | |
113 | return; | |
114 | ||
115 | fbc_ctl &= ~FBC_CTL_EN; | |
116 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
117 | ||
118 | /* Wait for compressing bit to clear */ | |
8d90dfd5 CW |
119 | if (intel_wait_for_register(dev_priv, |
120 | FBC_STATUS, FBC_STAT_COMPRESSING, 0, | |
121 | 10)) { | |
7ff0ebcc RV |
122 | DRM_DEBUG_KMS("FBC idle timed out\n"); |
123 | return; | |
124 | } | |
7ff0ebcc RV |
125 | } |
126 | ||
b183b3f1 | 127 | static void i8xx_fbc_activate(struct drm_i915_private *dev_priv) |
7ff0ebcc | 128 | { |
b183b3f1 | 129 | struct intel_fbc_reg_params *params = &dev_priv->fbc.params; |
7ff0ebcc RV |
130 | int cfb_pitch; |
131 | int i; | |
132 | u32 fbc_ctl; | |
133 | ||
60ee5cd2 | 134 | /* Note: fbc.threshold == 1 for i8xx */ |
b183b3f1 PZ |
135 | cfb_pitch = params->cfb_size / FBC_LL_SIZE; |
136 | if (params->fb.stride < cfb_pitch) | |
137 | cfb_pitch = params->fb.stride; | |
7ff0ebcc RV |
138 | |
139 | /* FBC_CTL wants 32B or 64B units */ | |
7733b49b | 140 | if (IS_GEN2(dev_priv)) |
7ff0ebcc RV |
141 | cfb_pitch = (cfb_pitch / 32) - 1; |
142 | else | |
143 | cfb_pitch = (cfb_pitch / 64) - 1; | |
144 | ||
145 | /* Clear old tags */ | |
146 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) | |
4d110c71 | 147 | I915_WRITE(FBC_TAG(i), 0); |
7ff0ebcc | 148 | |
7733b49b | 149 | if (IS_GEN4(dev_priv)) { |
7ff0ebcc RV |
150 | u32 fbc_ctl2; |
151 | ||
152 | /* Set it up... */ | |
153 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; | |
b183b3f1 | 154 | fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.plane); |
7ff0ebcc | 155 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
b183b3f1 | 156 | I915_WRITE(FBC_FENCE_OFF, params->crtc.fence_y_offset); |
7ff0ebcc RV |
157 | } |
158 | ||
159 | /* enable it... */ | |
160 | fbc_ctl = I915_READ(FBC_CONTROL); | |
161 | fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT; | |
162 | fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC; | |
7733b49b | 163 | if (IS_I945GM(dev_priv)) |
7ff0ebcc RV |
164 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
165 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; | |
be1e3415 | 166 | fbc_ctl |= params->vma->fence->id; |
7ff0ebcc | 167 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
7ff0ebcc RV |
168 | } |
169 | ||
0e631adc | 170 | static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv) |
7ff0ebcc | 171 | { |
7ff0ebcc RV |
172 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; |
173 | } | |
174 | ||
b183b3f1 | 175 | static void g4x_fbc_activate(struct drm_i915_private *dev_priv) |
7ff0ebcc | 176 | { |
b183b3f1 | 177 | struct intel_fbc_reg_params *params = &dev_priv->fbc.params; |
7ff0ebcc RV |
178 | u32 dpfc_ctl; |
179 | ||
b183b3f1 | 180 | dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane) | DPFC_SR_EN; |
801c8fe8 | 181 | if (params->fb.format->cpp[0] == 2) |
7ff0ebcc RV |
182 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; |
183 | else | |
184 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
7ff0ebcc | 185 | |
be1e3415 CW |
186 | if (params->vma->fence) { |
187 | dpfc_ctl |= DPFC_CTL_FENCE_EN | params->vma->fence->id; | |
12ecf4b9 CW |
188 | I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset); |
189 | } else { | |
190 | I915_WRITE(DPFC_FENCE_YOFF, 0); | |
191 | } | |
7ff0ebcc RV |
192 | |
193 | /* enable it... */ | |
194 | I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
7ff0ebcc RV |
195 | } |
196 | ||
0e631adc | 197 | static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv) |
7ff0ebcc | 198 | { |
7ff0ebcc RV |
199 | u32 dpfc_ctl; |
200 | ||
7ff0ebcc RV |
201 | /* Disable compression */ |
202 | dpfc_ctl = I915_READ(DPFC_CONTROL); | |
203 | if (dpfc_ctl & DPFC_CTL_EN) { | |
204 | dpfc_ctl &= ~DPFC_CTL_EN; | |
205 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); | |
7ff0ebcc RV |
206 | } |
207 | } | |
208 | ||
0e631adc | 209 | static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv) |
7ff0ebcc | 210 | { |
7ff0ebcc RV |
211 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; |
212 | } | |
213 | ||
d5ce4164 PZ |
214 | /* This function forces a CFB recompression through the nuke operation. */ |
215 | static void intel_fbc_recompress(struct drm_i915_private *dev_priv) | |
7ff0ebcc | 216 | { |
dbef0f15 PZ |
217 | I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE); |
218 | POSTING_READ(MSG_FBC_REND_STATE); | |
7ff0ebcc RV |
219 | } |
220 | ||
b183b3f1 | 221 | static void ilk_fbc_activate(struct drm_i915_private *dev_priv) |
7ff0ebcc | 222 | { |
b183b3f1 | 223 | struct intel_fbc_reg_params *params = &dev_priv->fbc.params; |
7ff0ebcc | 224 | u32 dpfc_ctl; |
ce65e47b | 225 | int threshold = dev_priv->fbc.threshold; |
7ff0ebcc | 226 | |
b183b3f1 | 227 | dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane); |
801c8fe8 | 228 | if (params->fb.format->cpp[0] == 2) |
ce65e47b | 229 | threshold++; |
7ff0ebcc | 230 | |
ce65e47b | 231 | switch (threshold) { |
7ff0ebcc RV |
232 | case 4: |
233 | case 3: | |
234 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; | |
235 | break; | |
236 | case 2: | |
237 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
238 | break; | |
239 | case 1: | |
240 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
241 | break; | |
242 | } | |
12ecf4b9 | 243 | |
be1e3415 | 244 | if (params->vma->fence) { |
12ecf4b9 CW |
245 | dpfc_ctl |= DPFC_CTL_FENCE_EN; |
246 | if (IS_GEN5(dev_priv)) | |
be1e3415 | 247 | dpfc_ctl |= params->vma->fence->id; |
12ecf4b9 CW |
248 | if (IS_GEN6(dev_priv)) { |
249 | I915_WRITE(SNB_DPFC_CTL_SA, | |
be1e3415 CW |
250 | SNB_CPU_FENCE_ENABLE | |
251 | params->vma->fence->id); | |
12ecf4b9 CW |
252 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, |
253 | params->crtc.fence_y_offset); | |
254 | } | |
255 | } else { | |
256 | if (IS_GEN6(dev_priv)) { | |
257 | I915_WRITE(SNB_DPFC_CTL_SA, 0); | |
258 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0); | |
259 | } | |
260 | } | |
7ff0ebcc | 261 | |
b183b3f1 | 262 | I915_WRITE(ILK_DPFC_FENCE_YOFF, params->crtc.fence_y_offset); |
be1e3415 CW |
263 | I915_WRITE(ILK_FBC_RT_BASE, |
264 | i915_ggtt_offset(params->vma) | ILK_FBC_RT_VALID); | |
7ff0ebcc RV |
265 | /* enable it... */ |
266 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
267 | ||
d5ce4164 | 268 | intel_fbc_recompress(dev_priv); |
7ff0ebcc RV |
269 | } |
270 | ||
0e631adc | 271 | static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv) |
7ff0ebcc | 272 | { |
7ff0ebcc RV |
273 | u32 dpfc_ctl; |
274 | ||
7ff0ebcc RV |
275 | /* Disable compression */ |
276 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
277 | if (dpfc_ctl & DPFC_CTL_EN) { | |
278 | dpfc_ctl &= ~DPFC_CTL_EN; | |
279 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); | |
7ff0ebcc RV |
280 | } |
281 | } | |
282 | ||
0e631adc | 283 | static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv) |
7ff0ebcc | 284 | { |
7ff0ebcc RV |
285 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; |
286 | } | |
287 | ||
b183b3f1 | 288 | static void gen7_fbc_activate(struct drm_i915_private *dev_priv) |
7ff0ebcc | 289 | { |
b183b3f1 | 290 | struct intel_fbc_reg_params *params = &dev_priv->fbc.params; |
7ff0ebcc | 291 | u32 dpfc_ctl; |
ce65e47b | 292 | int threshold = dev_priv->fbc.threshold; |
7ff0ebcc | 293 | |
5654a162 PP |
294 | /* Display WA #0529: skl, kbl, bxt. */ |
295 | if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) { | |
296 | u32 val = I915_READ(CHICKEN_MISC_4); | |
297 | ||
298 | val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK); | |
299 | ||
300 | if (i915_gem_object_get_tiling(params->vma->obj) != | |
301 | I915_TILING_X) | |
302 | val |= FBC_STRIDE_OVERRIDE | params->gen9_wa_cfb_stride; | |
303 | ||
304 | I915_WRITE(CHICKEN_MISC_4, val); | |
305 | } | |
306 | ||
d8514d63 | 307 | dpfc_ctl = 0; |
7733b49b | 308 | if (IS_IVYBRIDGE(dev_priv)) |
b183b3f1 | 309 | dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane); |
d8514d63 | 310 | |
801c8fe8 | 311 | if (params->fb.format->cpp[0] == 2) |
ce65e47b | 312 | threshold++; |
7ff0ebcc | 313 | |
ce65e47b | 314 | switch (threshold) { |
7ff0ebcc RV |
315 | case 4: |
316 | case 3: | |
317 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; | |
318 | break; | |
319 | case 2: | |
320 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
321 | break; | |
322 | case 1: | |
323 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
324 | break; | |
325 | } | |
326 | ||
be1e3415 | 327 | if (params->vma->fence) { |
12ecf4b9 CW |
328 | dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; |
329 | I915_WRITE(SNB_DPFC_CTL_SA, | |
be1e3415 CW |
330 | SNB_CPU_FENCE_ENABLE | |
331 | params->vma->fence->id); | |
12ecf4b9 CW |
332 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset); |
333 | } else { | |
334 | I915_WRITE(SNB_DPFC_CTL_SA,0); | |
335 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0); | |
336 | } | |
7ff0ebcc RV |
337 | |
338 | if (dev_priv->fbc.false_color) | |
339 | dpfc_ctl |= FBC_CTL_FALSE_COLOR; | |
340 | ||
7733b49b | 341 | if (IS_IVYBRIDGE(dev_priv)) { |
7ff0ebcc RV |
342 | /* WaFbcAsynchFlipDisableFbcQueue:ivb */ |
343 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
344 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
345 | ILK_FBCQ_DIS); | |
40f4022e | 346 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
7ff0ebcc | 347 | /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ |
b183b3f1 PZ |
348 | I915_WRITE(CHICKEN_PIPESL_1(params->crtc.pipe), |
349 | I915_READ(CHICKEN_PIPESL_1(params->crtc.pipe)) | | |
7ff0ebcc RV |
350 | HSW_FBCQ_DIS); |
351 | } | |
352 | ||
57012be9 PZ |
353 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
354 | ||
d5ce4164 | 355 | intel_fbc_recompress(dev_priv); |
7ff0ebcc RV |
356 | } |
357 | ||
8c40074c PZ |
358 | static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv) |
359 | { | |
5697d60f | 360 | if (INTEL_GEN(dev_priv) >= 5) |
8c40074c PZ |
361 | return ilk_fbc_is_active(dev_priv); |
362 | else if (IS_GM45(dev_priv)) | |
363 | return g4x_fbc_is_active(dev_priv); | |
364 | else | |
365 | return i8xx_fbc_is_active(dev_priv); | |
366 | } | |
367 | ||
368 | static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv) | |
369 | { | |
5375ce9f PZ |
370 | struct intel_fbc *fbc = &dev_priv->fbc; |
371 | ||
372 | fbc->active = true; | |
373 | ||
5697d60f | 374 | if (INTEL_GEN(dev_priv) >= 7) |
8c40074c | 375 | gen7_fbc_activate(dev_priv); |
5697d60f | 376 | else if (INTEL_GEN(dev_priv) >= 5) |
8c40074c PZ |
377 | ilk_fbc_activate(dev_priv); |
378 | else if (IS_GM45(dev_priv)) | |
379 | g4x_fbc_activate(dev_priv); | |
380 | else | |
381 | i8xx_fbc_activate(dev_priv); | |
382 | } | |
383 | ||
384 | static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv) | |
385 | { | |
5375ce9f PZ |
386 | struct intel_fbc *fbc = &dev_priv->fbc; |
387 | ||
388 | fbc->active = false; | |
389 | ||
5697d60f | 390 | if (INTEL_GEN(dev_priv) >= 5) |
8c40074c PZ |
391 | ilk_fbc_deactivate(dev_priv); |
392 | else if (IS_GM45(dev_priv)) | |
393 | g4x_fbc_deactivate(dev_priv); | |
394 | else | |
395 | i8xx_fbc_deactivate(dev_priv); | |
396 | } | |
397 | ||
94b83957 | 398 | /** |
0e631adc | 399 | * intel_fbc_is_active - Is FBC active? |
7733b49b | 400 | * @dev_priv: i915 device instance |
94b83957 RV |
401 | * |
402 | * This function is used to verify the current state of FBC. | |
2e7a5701 | 403 | * |
94b83957 | 404 | * FIXME: This should be tracked in the plane config eventually |
2e7a5701 | 405 | * instead of queried at runtime for most callers. |
94b83957 | 406 | */ |
0e631adc | 407 | bool intel_fbc_is_active(struct drm_i915_private *dev_priv) |
7ff0ebcc | 408 | { |
0e631adc | 409 | return dev_priv->fbc.active; |
7ff0ebcc RV |
410 | } |
411 | ||
7ff0ebcc RV |
412 | static void intel_fbc_work_fn(struct work_struct *__work) |
413 | { | |
128d7356 PZ |
414 | struct drm_i915_private *dev_priv = |
415 | container_of(__work, struct drm_i915_private, fbc.work.work); | |
ab34a7e8 PZ |
416 | struct intel_fbc *fbc = &dev_priv->fbc; |
417 | struct intel_fbc_work *work = &fbc->work; | |
418 | struct intel_crtc *crtc = fbc->crtc; | |
91c8a326 | 419 | struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[crtc->pipe]; |
ca18d51d PZ |
420 | |
421 | if (drm_crtc_vblank_get(&crtc->base)) { | |
908b6e6e | 422 | /* CRTC is now off, leave FBC deactivated */ |
ab34a7e8 | 423 | mutex_lock(&fbc->lock); |
ca18d51d | 424 | work->scheduled = false; |
ab34a7e8 | 425 | mutex_unlock(&fbc->lock); |
ca18d51d PZ |
426 | return; |
427 | } | |
128d7356 PZ |
428 | |
429 | retry: | |
430 | /* Delay the actual enabling to let pageflipping cease and the | |
431 | * display to settle before starting the compression. Note that | |
432 | * this delay also serves a second purpose: it allows for a | |
433 | * vblank to pass after disabling the FBC before we attempt | |
434 | * to modify the control registers. | |
435 | * | |
128d7356 | 436 | * WaFbcWaitForVBlankBeforeEnable:ilk,snb |
ca18d51d PZ |
437 | * |
438 | * It is also worth mentioning that since work->scheduled_vblank can be | |
439 | * updated multiple times by the other threads, hitting the timeout is | |
440 | * not an error condition. We'll just end up hitting the "goto retry" | |
441 | * case below. | |
128d7356 | 442 | */ |
ca18d51d PZ |
443 | wait_event_timeout(vblank->queue, |
444 | drm_crtc_vblank_count(&crtc->base) != work->scheduled_vblank, | |
445 | msecs_to_jiffies(50)); | |
7ff0ebcc | 446 | |
ab34a7e8 | 447 | mutex_lock(&fbc->lock); |
7ff0ebcc | 448 | |
128d7356 PZ |
449 | /* Were we cancelled? */ |
450 | if (!work->scheduled) | |
451 | goto out; | |
452 | ||
453 | /* Were we delayed again while this function was sleeping? */ | |
ca18d51d | 454 | if (drm_crtc_vblank_count(&crtc->base) == work->scheduled_vblank) { |
ab34a7e8 | 455 | mutex_unlock(&fbc->lock); |
128d7356 | 456 | goto retry; |
7ff0ebcc | 457 | } |
7ff0ebcc | 458 | |
8c40074c | 459 | intel_fbc_hw_activate(dev_priv); |
128d7356 PZ |
460 | |
461 | work->scheduled = false; | |
462 | ||
463 | out: | |
ab34a7e8 | 464 | mutex_unlock(&fbc->lock); |
ca18d51d | 465 | drm_crtc_vblank_put(&crtc->base); |
7ff0ebcc RV |
466 | } |
467 | ||
0e631adc | 468 | static void intel_fbc_schedule_activation(struct intel_crtc *crtc) |
7ff0ebcc | 469 | { |
fac5e23e | 470 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
ab34a7e8 PZ |
471 | struct intel_fbc *fbc = &dev_priv->fbc; |
472 | struct intel_fbc_work *work = &fbc->work; | |
7ff0ebcc | 473 | |
ab34a7e8 | 474 | WARN_ON(!mutex_is_locked(&fbc->lock)); |
2ae9e365 DV |
475 | if (WARN_ON(!fbc->enabled)) |
476 | return; | |
25ad93fd | 477 | |
ca18d51d PZ |
478 | if (drm_crtc_vblank_get(&crtc->base)) { |
479 | DRM_ERROR("vblank not available for FBC on pipe %c\n", | |
480 | pipe_name(crtc->pipe)); | |
481 | return; | |
482 | } | |
483 | ||
e35be23f PZ |
484 | /* It is useless to call intel_fbc_cancel_work() or cancel_work() in |
485 | * this function since we're not releasing fbc.lock, so it won't have an | |
486 | * opportunity to grab it to discover that it was cancelled. So we just | |
487 | * update the expected jiffy count. */ | |
128d7356 | 488 | work->scheduled = true; |
ca18d51d PZ |
489 | work->scheduled_vblank = drm_crtc_vblank_count(&crtc->base); |
490 | drm_crtc_vblank_put(&crtc->base); | |
7ff0ebcc | 491 | |
128d7356 | 492 | schedule_work(&work->work); |
7ff0ebcc RV |
493 | } |
494 | ||
60eb2cc7 | 495 | static void intel_fbc_deactivate(struct drm_i915_private *dev_priv) |
25ad93fd | 496 | { |
ab34a7e8 PZ |
497 | struct intel_fbc *fbc = &dev_priv->fbc; |
498 | ||
499 | WARN_ON(!mutex_is_locked(&fbc->lock)); | |
25ad93fd | 500 | |
e35be23f PZ |
501 | /* Calling cancel_work() here won't help due to the fact that the work |
502 | * function grabs fbc->lock. Just set scheduled to false so the work | |
503 | * function can know it was cancelled. */ | |
504 | fbc->work.scheduled = false; | |
25ad93fd | 505 | |
ab34a7e8 | 506 | if (fbc->active) |
8c40074c | 507 | intel_fbc_hw_deactivate(dev_priv); |
754d1133 PZ |
508 | } |
509 | ||
faf68d92 ML |
510 | static bool multiple_pipes_ok(struct intel_crtc *crtc, |
511 | struct intel_plane_state *plane_state) | |
232fd934 | 512 | { |
faf68d92 | 513 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
010cf73d PZ |
514 | struct intel_fbc *fbc = &dev_priv->fbc; |
515 | enum pipe pipe = crtc->pipe; | |
232fd934 | 516 | |
010cf73d PZ |
517 | /* Don't even bother tracking anything we don't need. */ |
518 | if (!no_fbc_on_multiple_pipes(dev_priv)) | |
232fd934 PZ |
519 | return true; |
520 | ||
936e71e3 | 521 | if (plane_state->base.visible) |
010cf73d PZ |
522 | fbc->visible_pipes_mask |= (1 << pipe); |
523 | else | |
524 | fbc->visible_pipes_mask &= ~(1 << pipe); | |
232fd934 | 525 | |
010cf73d | 526 | return (fbc->visible_pipes_mask & ~(1 << pipe)) != 0; |
232fd934 PZ |
527 | } |
528 | ||
7733b49b | 529 | static int find_compression_threshold(struct drm_i915_private *dev_priv, |
fc786728 PZ |
530 | struct drm_mm_node *node, |
531 | int size, | |
532 | int fb_cpp) | |
533 | { | |
72e96d64 | 534 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
fc786728 PZ |
535 | int compression_threshold = 1; |
536 | int ret; | |
a9da512b PZ |
537 | u64 end; |
538 | ||
539 | /* The FBC hardware for BDW/SKL doesn't have access to the stolen | |
540 | * reserved range size, so it always assumes the maximum (8mb) is used. | |
541 | * If we enable FBC using a CFB on that memory range we'll get FIFO | |
542 | * underruns, even if that range is not reserved by the BIOS. */ | |
b976dc53 | 543 | if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv)) |
72e96d64 | 544 | end = ggtt->stolen_size - 8 * 1024 * 1024; |
a9da512b | 545 | else |
3c6b29b2 | 546 | end = U64_MAX; |
fc786728 PZ |
547 | |
548 | /* HACK: This code depends on what we will do in *_enable_fbc. If that | |
549 | * code changes, this code needs to change as well. | |
550 | * | |
551 | * The enable_fbc code will attempt to use one of our 2 compression | |
552 | * thresholds, therefore, in that case, we only have 1 resort. | |
553 | */ | |
554 | ||
555 | /* Try to over-allocate to reduce reallocations and fragmentation. */ | |
a9da512b PZ |
556 | ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1, |
557 | 4096, 0, end); | |
fc786728 PZ |
558 | if (ret == 0) |
559 | return compression_threshold; | |
560 | ||
561 | again: | |
562 | /* HW's ability to limit the CFB is 1:4 */ | |
563 | if (compression_threshold > 4 || | |
564 | (fb_cpp == 2 && compression_threshold == 2)) | |
565 | return 0; | |
566 | ||
a9da512b PZ |
567 | ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1, |
568 | 4096, 0, end); | |
5697d60f | 569 | if (ret && INTEL_GEN(dev_priv) <= 4) { |
fc786728 PZ |
570 | return 0; |
571 | } else if (ret) { | |
572 | compression_threshold <<= 1; | |
573 | goto again; | |
574 | } else { | |
575 | return compression_threshold; | |
576 | } | |
577 | } | |
578 | ||
c5ecd469 | 579 | static int intel_fbc_alloc_cfb(struct intel_crtc *crtc) |
fc786728 | 580 | { |
fac5e23e | 581 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
ab34a7e8 | 582 | struct intel_fbc *fbc = &dev_priv->fbc; |
fc786728 | 583 | struct drm_mm_node *uninitialized_var(compressed_llb); |
c5ecd469 PZ |
584 | int size, fb_cpp, ret; |
585 | ||
ab34a7e8 | 586 | WARN_ON(drm_mm_node_allocated(&fbc->compressed_fb)); |
c5ecd469 | 587 | |
aaf78d27 | 588 | size = intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache); |
801c8fe8 | 589 | fb_cpp = fbc->state_cache.fb.format->cpp[0]; |
fc786728 | 590 | |
ab34a7e8 | 591 | ret = find_compression_threshold(dev_priv, &fbc->compressed_fb, |
fc786728 PZ |
592 | size, fb_cpp); |
593 | if (!ret) | |
594 | goto err_llb; | |
595 | else if (ret > 1) { | |
596 | DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n"); | |
597 | ||
598 | } | |
599 | ||
ab34a7e8 | 600 | fbc->threshold = ret; |
fc786728 | 601 | |
5697d60f | 602 | if (INTEL_GEN(dev_priv) >= 5) |
ab34a7e8 | 603 | I915_WRITE(ILK_DPFC_CB_BASE, fbc->compressed_fb.start); |
7733b49b | 604 | else if (IS_GM45(dev_priv)) { |
ab34a7e8 | 605 | I915_WRITE(DPFC_CB_BASE, fbc->compressed_fb.start); |
fc786728 PZ |
606 | } else { |
607 | compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL); | |
608 | if (!compressed_llb) | |
609 | goto err_fb; | |
610 | ||
611 | ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb, | |
612 | 4096, 4096); | |
613 | if (ret) | |
614 | goto err_fb; | |
615 | ||
ab34a7e8 | 616 | fbc->compressed_llb = compressed_llb; |
fc786728 PZ |
617 | |
618 | I915_WRITE(FBC_CFB_BASE, | |
ab34a7e8 | 619 | dev_priv->mm.stolen_base + fbc->compressed_fb.start); |
fc786728 PZ |
620 | I915_WRITE(FBC_LL_BASE, |
621 | dev_priv->mm.stolen_base + compressed_llb->start); | |
622 | } | |
623 | ||
b8bf5d7f | 624 | DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n", |
ab34a7e8 | 625 | fbc->compressed_fb.size, fbc->threshold); |
fc786728 PZ |
626 | |
627 | return 0; | |
628 | ||
629 | err_fb: | |
630 | kfree(compressed_llb); | |
ab34a7e8 | 631 | i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb); |
fc786728 | 632 | err_llb: |
8d0e9bcb CW |
633 | if (drm_mm_initialized(&dev_priv->mm.stolen)) |
634 | pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size); | |
fc786728 PZ |
635 | return -ENOSPC; |
636 | } | |
637 | ||
7733b49b | 638 | static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) |
fc786728 | 639 | { |
ab34a7e8 PZ |
640 | struct intel_fbc *fbc = &dev_priv->fbc; |
641 | ||
642 | if (drm_mm_node_allocated(&fbc->compressed_fb)) | |
643 | i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb); | |
644 | ||
645 | if (fbc->compressed_llb) { | |
646 | i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb); | |
647 | kfree(fbc->compressed_llb); | |
fc786728 | 648 | } |
fc786728 PZ |
649 | } |
650 | ||
7733b49b | 651 | void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) |
25ad93fd | 652 | { |
ab34a7e8 PZ |
653 | struct intel_fbc *fbc = &dev_priv->fbc; |
654 | ||
9f218336 | 655 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
656 | return; |
657 | ||
ab34a7e8 | 658 | mutex_lock(&fbc->lock); |
7733b49b | 659 | __intel_fbc_cleanup_cfb(dev_priv); |
ab34a7e8 | 660 | mutex_unlock(&fbc->lock); |
25ad93fd PZ |
661 | } |
662 | ||
adf70c65 PZ |
663 | static bool stride_is_valid(struct drm_i915_private *dev_priv, |
664 | unsigned int stride) | |
665 | { | |
666 | /* These should have been caught earlier. */ | |
667 | WARN_ON(stride < 512); | |
668 | WARN_ON((stride & (64 - 1)) != 0); | |
669 | ||
670 | /* Below are the additional FBC restrictions. */ | |
671 | ||
672 | if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv)) | |
673 | return stride == 4096 || stride == 8192; | |
674 | ||
675 | if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048) | |
676 | return false; | |
677 | ||
678 | if (stride > 16384) | |
679 | return false; | |
680 | ||
681 | return true; | |
682 | } | |
683 | ||
aaf78d27 PZ |
684 | static bool pixel_format_is_valid(struct drm_i915_private *dev_priv, |
685 | uint32_t pixel_format) | |
b9e831dc | 686 | { |
aaf78d27 | 687 | switch (pixel_format) { |
b9e831dc PZ |
688 | case DRM_FORMAT_XRGB8888: |
689 | case DRM_FORMAT_XBGR8888: | |
690 | return true; | |
691 | case DRM_FORMAT_XRGB1555: | |
692 | case DRM_FORMAT_RGB565: | |
693 | /* 16bpp not supported on gen2 */ | |
aaf78d27 | 694 | if (IS_GEN2(dev_priv)) |
b9e831dc PZ |
695 | return false; |
696 | /* WaFbcOnly1to1Ratio:ctg */ | |
697 | if (IS_G4X(dev_priv)) | |
698 | return false; | |
699 | return true; | |
700 | default: | |
701 | return false; | |
702 | } | |
703 | } | |
704 | ||
856312ae PZ |
705 | /* |
706 | * For some reason, the hardware tracking starts looking at whatever we | |
707 | * programmed as the display plane base address register. It does not look at | |
708 | * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y} | |
709 | * variables instead of just looking at the pipe/plane size. | |
710 | */ | |
711 | static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc) | |
3c5f174e | 712 | { |
fac5e23e | 713 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
aaf78d27 | 714 | struct intel_fbc *fbc = &dev_priv->fbc; |
856312ae | 715 | unsigned int effective_w, effective_h, max_w, max_h; |
3c5f174e | 716 | |
5697d60f | 717 | if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) { |
3c5f174e PZ |
718 | max_w = 4096; |
719 | max_h = 4096; | |
5697d60f | 720 | } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { |
3c5f174e PZ |
721 | max_w = 4096; |
722 | max_h = 2048; | |
723 | } else { | |
724 | max_w = 2048; | |
725 | max_h = 1536; | |
726 | } | |
727 | ||
aaf78d27 PZ |
728 | intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w, |
729 | &effective_h); | |
856312ae PZ |
730 | effective_w += crtc->adjusted_x; |
731 | effective_h += crtc->adjusted_y; | |
732 | ||
733 | return effective_w <= max_w && effective_h <= max_h; | |
3c5f174e PZ |
734 | } |
735 | ||
faf68d92 ML |
736 | static void intel_fbc_update_state_cache(struct intel_crtc *crtc, |
737 | struct intel_crtc_state *crtc_state, | |
738 | struct intel_plane_state *plane_state) | |
7ff0ebcc | 739 | { |
fac5e23e | 740 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
ab34a7e8 | 741 | struct intel_fbc *fbc = &dev_priv->fbc; |
aaf78d27 | 742 | struct intel_fbc_state_cache *cache = &fbc->state_cache; |
aaf78d27 | 743 | struct drm_framebuffer *fb = plane_state->base.fb; |
be1e3415 CW |
744 | |
745 | cache->vma = NULL; | |
7ff0ebcc | 746 | |
aaf78d27 PZ |
747 | cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags; |
748 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
a7d1b3f4 | 749 | cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate; |
aaf78d27 PZ |
750 | |
751 | cache->plane.rotation = plane_state->base.rotation; | |
73714c05 VS |
752 | /* |
753 | * Src coordinates are already rotated by 270 degrees for | |
754 | * the 90/270 degree plane rotation cases (to match the | |
755 | * GTT mapping), hence no need to account for rotation here. | |
756 | */ | |
936e71e3 VS |
757 | cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16; |
758 | cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16; | |
759 | cache->plane.visible = plane_state->base.visible; | |
aaf78d27 PZ |
760 | |
761 | if (!cache->plane.visible) | |
762 | return; | |
7ff0ebcc | 763 | |
801c8fe8 | 764 | cache->fb.format = fb->format; |
aaf78d27 | 765 | cache->fb.stride = fb->pitches[0]; |
be1e3415 CW |
766 | |
767 | cache->vma = plane_state->vma; | |
aaf78d27 PZ |
768 | } |
769 | ||
770 | static bool intel_fbc_can_activate(struct intel_crtc *crtc) | |
771 | { | |
fac5e23e | 772 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
aaf78d27 PZ |
773 | struct intel_fbc *fbc = &dev_priv->fbc; |
774 | struct intel_fbc_state_cache *cache = &fbc->state_cache; | |
775 | ||
61a585d6 PZ |
776 | /* We don't need to use a state cache here since this information is |
777 | * global for all CRTC. | |
778 | */ | |
779 | if (fbc->underrun_detected) { | |
780 | fbc->no_fbc_reason = "underrun detected"; | |
781 | return false; | |
782 | } | |
783 | ||
be1e3415 | 784 | if (!cache->vma) { |
913a3a6a | 785 | fbc->no_fbc_reason = "primary plane not visible"; |
615b40d7 PZ |
786 | return false; |
787 | } | |
7ff0ebcc | 788 | |
aaf78d27 PZ |
789 | if ((cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) || |
790 | (cache->crtc.mode_flags & DRM_MODE_FLAG_DBLSCAN)) { | |
913a3a6a | 791 | fbc->no_fbc_reason = "incompatible mode"; |
615b40d7 | 792 | return false; |
7ff0ebcc RV |
793 | } |
794 | ||
45b32a29 | 795 | if (!intel_fbc_hw_tracking_covers_screen(crtc)) { |
913a3a6a | 796 | fbc->no_fbc_reason = "mode too large for compression"; |
615b40d7 | 797 | return false; |
7ff0ebcc | 798 | } |
3c5f174e | 799 | |
7ff0ebcc RV |
800 | /* The use of a CPU fence is mandatory in order to detect writes |
801 | * by the CPU to the scanout and trigger updates to the FBC. | |
2efb813d CW |
802 | * |
803 | * Note that is possible for a tiled surface to be unmappable (and | |
804 | * so have no fence associated with it) due to aperture constaints | |
805 | * at the time of pinning. | |
7ff0ebcc | 806 | */ |
be1e3415 | 807 | if (!cache->vma->fence) { |
c82dd884 CW |
808 | fbc->no_fbc_reason = "framebuffer not tiled or fenced"; |
809 | return false; | |
7ff0ebcc | 810 | } |
5697d60f | 811 | if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) && |
c2c446ad | 812 | cache->plane.rotation != DRM_MODE_ROTATE_0) { |
913a3a6a | 813 | fbc->no_fbc_reason = "rotation unsupported"; |
615b40d7 | 814 | return false; |
7ff0ebcc RV |
815 | } |
816 | ||
aaf78d27 | 817 | if (!stride_is_valid(dev_priv, cache->fb.stride)) { |
913a3a6a | 818 | fbc->no_fbc_reason = "framebuffer stride not supported"; |
615b40d7 | 819 | return false; |
adf70c65 PZ |
820 | } |
821 | ||
801c8fe8 | 822 | if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) { |
913a3a6a | 823 | fbc->no_fbc_reason = "pixel format is invalid"; |
615b40d7 | 824 | return false; |
b9e831dc PZ |
825 | } |
826 | ||
7b24c9a6 PZ |
827 | /* WaFbcExceedCdClockThreshold:hsw,bdw */ |
828 | if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) && | |
49cd97a3 | 829 | cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) { |
913a3a6a | 830 | fbc->no_fbc_reason = "pixel rate is too big"; |
615b40d7 | 831 | return false; |
7b24c9a6 PZ |
832 | } |
833 | ||
c5ecd469 PZ |
834 | /* It is possible for the required CFB size change without a |
835 | * crtc->disable + crtc->enable since it is possible to change the | |
836 | * stride without triggering a full modeset. Since we try to | |
837 | * over-allocate the CFB, there's a chance we may keep FBC enabled even | |
838 | * if this happens, but if we exceed the current CFB size we'll have to | |
839 | * disable FBC. Notice that it would be possible to disable FBC, wait | |
840 | * for a frame, free the stolen node, then try to reenable FBC in case | |
841 | * we didn't get any invalidate/deactivate calls, but this would require | |
842 | * a lot of tracking just for a specific case. If we conclude it's an | |
843 | * important case, we can implement it later. */ | |
aaf78d27 | 844 | if (intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) > |
ab34a7e8 | 845 | fbc->compressed_fb.size * fbc->threshold) { |
913a3a6a | 846 | fbc->no_fbc_reason = "CFB requirements changed"; |
615b40d7 PZ |
847 | return false; |
848 | } | |
849 | ||
850 | return true; | |
851 | } | |
852 | ||
ee2be309 | 853 | static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv) |
44a8a257 | 854 | { |
913a3a6a | 855 | struct intel_fbc *fbc = &dev_priv->fbc; |
44a8a257 | 856 | |
c033666a | 857 | if (intel_vgpu_active(dev_priv)) { |
913a3a6a | 858 | fbc->no_fbc_reason = "VGPU is active"; |
44a8a257 PZ |
859 | return false; |
860 | } | |
861 | ||
44a8a257 | 862 | if (!i915.enable_fbc) { |
80788a0f | 863 | fbc->no_fbc_reason = "disabled per module param or by default"; |
44a8a257 PZ |
864 | return false; |
865 | } | |
866 | ||
61a585d6 PZ |
867 | if (fbc->underrun_detected) { |
868 | fbc->no_fbc_reason = "underrun detected"; | |
869 | return false; | |
870 | } | |
871 | ||
ee2be309 PZ |
872 | return true; |
873 | } | |
874 | ||
b183b3f1 PZ |
875 | static void intel_fbc_get_reg_params(struct intel_crtc *crtc, |
876 | struct intel_fbc_reg_params *params) | |
877 | { | |
fac5e23e | 878 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
aaf78d27 PZ |
879 | struct intel_fbc *fbc = &dev_priv->fbc; |
880 | struct intel_fbc_state_cache *cache = &fbc->state_cache; | |
b183b3f1 PZ |
881 | |
882 | /* Since all our fields are integer types, use memset here so the | |
883 | * comparison function can rely on memcmp because the padding will be | |
884 | * zero. */ | |
885 | memset(params, 0, sizeof(*params)); | |
886 | ||
be1e3415 CW |
887 | params->vma = cache->vma; |
888 | ||
b183b3f1 PZ |
889 | params->crtc.pipe = crtc->pipe; |
890 | params->crtc.plane = crtc->plane; | |
891 | params->crtc.fence_y_offset = get_crtc_fence_y_offset(crtc); | |
892 | ||
801c8fe8 | 893 | params->fb.format = cache->fb.format; |
aaf78d27 | 894 | params->fb.stride = cache->fb.stride; |
b183b3f1 | 895 | |
aaf78d27 | 896 | params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache); |
5654a162 PP |
897 | |
898 | if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) | |
899 | params->gen9_wa_cfb_stride = DIV_ROUND_UP(cache->plane.src_w, | |
900 | 32 * fbc->threshold) * 8; | |
b183b3f1 PZ |
901 | } |
902 | ||
903 | static bool intel_fbc_reg_params_equal(struct intel_fbc_reg_params *params1, | |
904 | struct intel_fbc_reg_params *params2) | |
905 | { | |
906 | /* We can use this since intel_fbc_get_reg_params() does a memset. */ | |
907 | return memcmp(params1, params2, sizeof(*params1)) == 0; | |
908 | } | |
909 | ||
faf68d92 ML |
910 | void intel_fbc_pre_update(struct intel_crtc *crtc, |
911 | struct intel_crtc_state *crtc_state, | |
912 | struct intel_plane_state *plane_state) | |
615b40d7 | 913 | { |
fac5e23e | 914 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
ab34a7e8 | 915 | struct intel_fbc *fbc = &dev_priv->fbc; |
615b40d7 | 916 | |
1eb52238 PZ |
917 | if (!fbc_supported(dev_priv)) |
918 | return; | |
919 | ||
920 | mutex_lock(&fbc->lock); | |
615b40d7 | 921 | |
faf68d92 | 922 | if (!multiple_pipes_ok(crtc, plane_state)) { |
913a3a6a | 923 | fbc->no_fbc_reason = "more than one pipe active"; |
212890cf | 924 | goto deactivate; |
7ff0ebcc RV |
925 | } |
926 | ||
ab34a7e8 | 927 | if (!fbc->enabled || fbc->crtc != crtc) |
1eb52238 | 928 | goto unlock; |
615b40d7 | 929 | |
faf68d92 | 930 | intel_fbc_update_state_cache(crtc, crtc_state, plane_state); |
aaf78d27 | 931 | |
212890cf | 932 | deactivate: |
60eb2cc7 | 933 | intel_fbc_deactivate(dev_priv); |
1eb52238 PZ |
934 | unlock: |
935 | mutex_unlock(&fbc->lock); | |
212890cf PZ |
936 | } |
937 | ||
1eb52238 | 938 | static void __intel_fbc_post_update(struct intel_crtc *crtc) |
212890cf | 939 | { |
fac5e23e | 940 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
212890cf PZ |
941 | struct intel_fbc *fbc = &dev_priv->fbc; |
942 | struct intel_fbc_reg_params old_params; | |
943 | ||
944 | WARN_ON(!mutex_is_locked(&fbc->lock)); | |
945 | ||
946 | if (!fbc->enabled || fbc->crtc != crtc) | |
947 | return; | |
948 | ||
949 | if (!intel_fbc_can_activate(crtc)) { | |
950 | WARN_ON(fbc->active); | |
951 | return; | |
952 | } | |
615b40d7 | 953 | |
ab34a7e8 PZ |
954 | old_params = fbc->params; |
955 | intel_fbc_get_reg_params(crtc, &fbc->params); | |
b183b3f1 | 956 | |
7ff0ebcc RV |
957 | /* If the scanout has not changed, don't modify the FBC settings. |
958 | * Note that we make the fundamental assumption that the fb->obj | |
959 | * cannot be unpinned (and have its GTT offset and fence revoked) | |
960 | * without first being decoupled from the scanout and FBC disabled. | |
961 | */ | |
ab34a7e8 PZ |
962 | if (fbc->active && |
963 | intel_fbc_reg_params_equal(&old_params, &fbc->params)) | |
7ff0ebcc RV |
964 | return; |
965 | ||
60eb2cc7 | 966 | intel_fbc_deactivate(dev_priv); |
0e631adc | 967 | intel_fbc_schedule_activation(crtc); |
212890cf | 968 | fbc->no_fbc_reason = "FBC enabled (active or scheduled)"; |
25ad93fd PZ |
969 | } |
970 | ||
1eb52238 | 971 | void intel_fbc_post_update(struct intel_crtc *crtc) |
25ad93fd | 972 | { |
fac5e23e | 973 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
ab34a7e8 | 974 | struct intel_fbc *fbc = &dev_priv->fbc; |
754d1133 | 975 | |
9f218336 | 976 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
977 | return; |
978 | ||
ab34a7e8 | 979 | mutex_lock(&fbc->lock); |
1eb52238 | 980 | __intel_fbc_post_update(crtc); |
ab34a7e8 | 981 | mutex_unlock(&fbc->lock); |
7ff0ebcc RV |
982 | } |
983 | ||
261fe99a PZ |
984 | static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc) |
985 | { | |
986 | if (fbc->enabled) | |
987 | return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit; | |
988 | else | |
989 | return fbc->possible_framebuffer_bits; | |
990 | } | |
991 | ||
dbef0f15 PZ |
992 | void intel_fbc_invalidate(struct drm_i915_private *dev_priv, |
993 | unsigned int frontbuffer_bits, | |
994 | enum fb_op_origin origin) | |
995 | { | |
ab34a7e8 | 996 | struct intel_fbc *fbc = &dev_priv->fbc; |
dbef0f15 | 997 | |
9f218336 | 998 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
999 | return; |
1000 | ||
0dd81544 | 1001 | if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP) |
dbef0f15 PZ |
1002 | return; |
1003 | ||
ab34a7e8 | 1004 | mutex_lock(&fbc->lock); |
25ad93fd | 1005 | |
261fe99a | 1006 | fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits; |
dbef0f15 | 1007 | |
5bc40472 | 1008 | if (fbc->enabled && fbc->busy_bits) |
60eb2cc7 | 1009 | intel_fbc_deactivate(dev_priv); |
25ad93fd | 1010 | |
ab34a7e8 | 1011 | mutex_unlock(&fbc->lock); |
dbef0f15 PZ |
1012 | } |
1013 | ||
1014 | void intel_fbc_flush(struct drm_i915_private *dev_priv, | |
6f4551fe | 1015 | unsigned int frontbuffer_bits, enum fb_op_origin origin) |
dbef0f15 | 1016 | { |
ab34a7e8 PZ |
1017 | struct intel_fbc *fbc = &dev_priv->fbc; |
1018 | ||
9f218336 | 1019 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
1020 | return; |
1021 | ||
ab34a7e8 | 1022 | mutex_lock(&fbc->lock); |
dbef0f15 | 1023 | |
ab34a7e8 | 1024 | fbc->busy_bits &= ~frontbuffer_bits; |
dbef0f15 | 1025 | |
ab28a547 PZ |
1026 | if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP) |
1027 | goto out; | |
1028 | ||
261fe99a PZ |
1029 | if (!fbc->busy_bits && fbc->enabled && |
1030 | (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) { | |
0dd81544 | 1031 | if (fbc->active) |
ee7d6cfa | 1032 | intel_fbc_recompress(dev_priv); |
0dd81544 | 1033 | else |
1eb52238 | 1034 | __intel_fbc_post_update(fbc->crtc); |
6f4551fe | 1035 | } |
25ad93fd | 1036 | |
ab28a547 | 1037 | out: |
ab34a7e8 | 1038 | mutex_unlock(&fbc->lock); |
dbef0f15 PZ |
1039 | } |
1040 | ||
f51be2e0 PZ |
1041 | /** |
1042 | * intel_fbc_choose_crtc - select a CRTC to enable FBC on | |
1043 | * @dev_priv: i915 device instance | |
1044 | * @state: the atomic state structure | |
1045 | * | |
1046 | * This function looks at the proposed state for CRTCs and planes, then chooses | |
1047 | * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to | |
1048 | * true. | |
1049 | * | |
1050 | * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe | |
1051 | * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc. | |
1052 | */ | |
1053 | void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, | |
1054 | struct drm_atomic_state *state) | |
1055 | { | |
1056 | struct intel_fbc *fbc = &dev_priv->fbc; | |
f51be2e0 PZ |
1057 | struct drm_plane *plane; |
1058 | struct drm_plane_state *plane_state; | |
4f8f2251 | 1059 | bool crtc_chosen = false; |
ba67fab0 | 1060 | int i; |
f51be2e0 PZ |
1061 | |
1062 | mutex_lock(&fbc->lock); | |
1063 | ||
4f8f2251 PZ |
1064 | /* Does this atomic commit involve the CRTC currently tied to FBC? */ |
1065 | if (fbc->crtc && | |
1066 | !drm_atomic_get_existing_crtc_state(state, &fbc->crtc->base)) | |
f51be2e0 PZ |
1067 | goto out; |
1068 | ||
ee2be309 PZ |
1069 | if (!intel_fbc_can_enable(dev_priv)) |
1070 | goto out; | |
1071 | ||
f51be2e0 PZ |
1072 | /* Simply choose the first CRTC that is compatible and has a visible |
1073 | * plane. We could go for fancier schemes such as checking the plane | |
1074 | * size, but this would just affect the few platforms that don't tie FBC | |
1075 | * to pipe or plane A. */ | |
e96b206f | 1076 | for_each_new_plane_in_state(state, plane, plane_state, i) { |
f51be2e0 PZ |
1077 | struct intel_plane_state *intel_plane_state = |
1078 | to_intel_plane_state(plane_state); | |
ba67fab0 | 1079 | struct intel_crtc_state *intel_crtc_state; |
f7e9b004 | 1080 | struct intel_crtc *crtc = to_intel_crtc(plane_state->crtc); |
f51be2e0 | 1081 | |
936e71e3 | 1082 | if (!intel_plane_state->base.visible) |
f51be2e0 PZ |
1083 | continue; |
1084 | ||
f7e9b004 PZ |
1085 | if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A) |
1086 | continue; | |
1087 | ||
1088 | if (fbc_on_plane_a_only(dev_priv) && crtc->plane != PLANE_A) | |
03e39104 PZ |
1089 | continue; |
1090 | ||
ba67fab0 | 1091 | intel_crtc_state = to_intel_crtc_state( |
f7e9b004 | 1092 | drm_atomic_get_existing_crtc_state(state, &crtc->base)); |
f51be2e0 | 1093 | |
ba67fab0 | 1094 | intel_crtc_state->enable_fbc = true; |
f7e9b004 | 1095 | crtc_chosen = true; |
ba67fab0 | 1096 | break; |
f51be2e0 PZ |
1097 | } |
1098 | ||
f7e9b004 PZ |
1099 | if (!crtc_chosen) |
1100 | fbc->no_fbc_reason = "no suitable CRTC for FBC"; | |
1101 | ||
f51be2e0 PZ |
1102 | out: |
1103 | mutex_unlock(&fbc->lock); | |
1104 | } | |
1105 | ||
d029bcad PZ |
1106 | /** |
1107 | * intel_fbc_enable: tries to enable FBC on the CRTC | |
1108 | * @crtc: the CRTC | |
62f90b38 DV |
1109 | * @crtc_state: corresponding &drm_crtc_state for @crtc |
1110 | * @plane_state: corresponding &drm_plane_state for the primary plane of @crtc | |
d029bcad | 1111 | * |
f51be2e0 | 1112 | * This function checks if the given CRTC was chosen for FBC, then enables it if |
49227c4a PZ |
1113 | * possible. Notice that it doesn't activate FBC. It is valid to call |
1114 | * intel_fbc_enable multiple times for the same pipe without an | |
1115 | * intel_fbc_disable in the middle, as long as it is deactivated. | |
d029bcad | 1116 | */ |
faf68d92 ML |
1117 | void intel_fbc_enable(struct intel_crtc *crtc, |
1118 | struct intel_crtc_state *crtc_state, | |
1119 | struct intel_plane_state *plane_state) | |
d029bcad | 1120 | { |
fac5e23e | 1121 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
ab34a7e8 | 1122 | struct intel_fbc *fbc = &dev_priv->fbc; |
d029bcad PZ |
1123 | |
1124 | if (!fbc_supported(dev_priv)) | |
1125 | return; | |
1126 | ||
ab34a7e8 | 1127 | mutex_lock(&fbc->lock); |
d029bcad | 1128 | |
ab34a7e8 | 1129 | if (fbc->enabled) { |
49227c4a PZ |
1130 | WARN_ON(fbc->crtc == NULL); |
1131 | if (fbc->crtc == crtc) { | |
faf68d92 | 1132 | WARN_ON(!crtc_state->enable_fbc); |
49227c4a PZ |
1133 | WARN_ON(fbc->active); |
1134 | } | |
d029bcad PZ |
1135 | goto out; |
1136 | } | |
1137 | ||
faf68d92 | 1138 | if (!crtc_state->enable_fbc) |
f51be2e0 PZ |
1139 | goto out; |
1140 | ||
ab34a7e8 PZ |
1141 | WARN_ON(fbc->active); |
1142 | WARN_ON(fbc->crtc != NULL); | |
d029bcad | 1143 | |
faf68d92 | 1144 | intel_fbc_update_state_cache(crtc, crtc_state, plane_state); |
c5ecd469 | 1145 | if (intel_fbc_alloc_cfb(crtc)) { |
913a3a6a | 1146 | fbc->no_fbc_reason = "not enough stolen memory"; |
c5ecd469 PZ |
1147 | goto out; |
1148 | } | |
1149 | ||
d029bcad | 1150 | DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc->pipe)); |
ab34a7e8 | 1151 | fbc->no_fbc_reason = "FBC enabled but not active yet\n"; |
d029bcad | 1152 | |
ab34a7e8 PZ |
1153 | fbc->enabled = true; |
1154 | fbc->crtc = crtc; | |
d029bcad | 1155 | out: |
ab34a7e8 | 1156 | mutex_unlock(&fbc->lock); |
d029bcad PZ |
1157 | } |
1158 | ||
1159 | /** | |
1160 | * __intel_fbc_disable - disable FBC | |
1161 | * @dev_priv: i915 device instance | |
1162 | * | |
1163 | * This is the low level function that actually disables FBC. Callers should | |
1164 | * grab the FBC lock. | |
1165 | */ | |
1166 | static void __intel_fbc_disable(struct drm_i915_private *dev_priv) | |
1167 | { | |
ab34a7e8 PZ |
1168 | struct intel_fbc *fbc = &dev_priv->fbc; |
1169 | struct intel_crtc *crtc = fbc->crtc; | |
d029bcad | 1170 | |
ab34a7e8 PZ |
1171 | WARN_ON(!mutex_is_locked(&fbc->lock)); |
1172 | WARN_ON(!fbc->enabled); | |
1173 | WARN_ON(fbc->active); | |
58f9c0bc | 1174 | WARN_ON(crtc->active); |
d029bcad PZ |
1175 | |
1176 | DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc->pipe)); | |
1177 | ||
c5ecd469 PZ |
1178 | __intel_fbc_cleanup_cfb(dev_priv); |
1179 | ||
ab34a7e8 PZ |
1180 | fbc->enabled = false; |
1181 | fbc->crtc = NULL; | |
d029bcad PZ |
1182 | } |
1183 | ||
1184 | /** | |
c937ab3e | 1185 | * intel_fbc_disable - disable FBC if it's associated with crtc |
d029bcad PZ |
1186 | * @crtc: the CRTC |
1187 | * | |
1188 | * This function disables FBC if it's associated with the provided CRTC. | |
1189 | */ | |
c937ab3e | 1190 | void intel_fbc_disable(struct intel_crtc *crtc) |
d029bcad | 1191 | { |
fac5e23e | 1192 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
ab34a7e8 | 1193 | struct intel_fbc *fbc = &dev_priv->fbc; |
d029bcad PZ |
1194 | |
1195 | if (!fbc_supported(dev_priv)) | |
1196 | return; | |
1197 | ||
ab34a7e8 | 1198 | mutex_lock(&fbc->lock); |
4da45616 | 1199 | if (fbc->crtc == crtc) |
d029bcad | 1200 | __intel_fbc_disable(dev_priv); |
ab34a7e8 | 1201 | mutex_unlock(&fbc->lock); |
65c7600f PZ |
1202 | |
1203 | cancel_work_sync(&fbc->work.work); | |
d029bcad PZ |
1204 | } |
1205 | ||
1206 | /** | |
c937ab3e | 1207 | * intel_fbc_global_disable - globally disable FBC |
d029bcad PZ |
1208 | * @dev_priv: i915 device instance |
1209 | * | |
1210 | * This function disables FBC regardless of which CRTC is associated with it. | |
1211 | */ | |
c937ab3e | 1212 | void intel_fbc_global_disable(struct drm_i915_private *dev_priv) |
d029bcad | 1213 | { |
ab34a7e8 PZ |
1214 | struct intel_fbc *fbc = &dev_priv->fbc; |
1215 | ||
d029bcad PZ |
1216 | if (!fbc_supported(dev_priv)) |
1217 | return; | |
1218 | ||
ab34a7e8 PZ |
1219 | mutex_lock(&fbc->lock); |
1220 | if (fbc->enabled) | |
d029bcad | 1221 | __intel_fbc_disable(dev_priv); |
ab34a7e8 | 1222 | mutex_unlock(&fbc->lock); |
65c7600f PZ |
1223 | |
1224 | cancel_work_sync(&fbc->work.work); | |
d029bcad PZ |
1225 | } |
1226 | ||
61a585d6 PZ |
1227 | static void intel_fbc_underrun_work_fn(struct work_struct *work) |
1228 | { | |
1229 | struct drm_i915_private *dev_priv = | |
1230 | container_of(work, struct drm_i915_private, fbc.underrun_work); | |
1231 | struct intel_fbc *fbc = &dev_priv->fbc; | |
1232 | ||
1233 | mutex_lock(&fbc->lock); | |
1234 | ||
1235 | /* Maybe we were scheduled twice. */ | |
2ae9e365 | 1236 | if (fbc->underrun_detected || !fbc->enabled) |
61a585d6 PZ |
1237 | goto out; |
1238 | ||
1239 | DRM_DEBUG_KMS("Disabling FBC due to FIFO underrun.\n"); | |
1240 | fbc->underrun_detected = true; | |
1241 | ||
1242 | intel_fbc_deactivate(dev_priv); | |
1243 | out: | |
1244 | mutex_unlock(&fbc->lock); | |
1245 | } | |
1246 | ||
1247 | /** | |
1248 | * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun | |
1249 | * @dev_priv: i915 device instance | |
1250 | * | |
1251 | * Without FBC, most underruns are harmless and don't really cause too many | |
1252 | * problems, except for an annoying message on dmesg. With FBC, underruns can | |
1253 | * become black screens or even worse, especially when paired with bad | |
1254 | * watermarks. So in order for us to be on the safe side, completely disable FBC | |
1255 | * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe | |
1256 | * already suggests that watermarks may be bad, so try to be as safe as | |
1257 | * possible. | |
1258 | * | |
1259 | * This function is called from the IRQ handler. | |
1260 | */ | |
1261 | void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv) | |
1262 | { | |
1263 | struct intel_fbc *fbc = &dev_priv->fbc; | |
1264 | ||
1265 | if (!fbc_supported(dev_priv)) | |
1266 | return; | |
1267 | ||
1268 | /* There's no guarantee that underrun_detected won't be set to true | |
1269 | * right after this check and before the work is scheduled, but that's | |
1270 | * not a problem since we'll check it again under the work function | |
1271 | * while FBC is locked. This check here is just to prevent us from | |
1272 | * unnecessarily scheduling the work, and it relies on the fact that we | |
1273 | * never switch underrun_detect back to false after it's true. */ | |
1274 | if (READ_ONCE(fbc->underrun_detected)) | |
1275 | return; | |
1276 | ||
1277 | schedule_work(&fbc->underrun_work); | |
1278 | } | |
1279 | ||
010cf73d PZ |
1280 | /** |
1281 | * intel_fbc_init_pipe_state - initialize FBC's CRTC visibility tracking | |
1282 | * @dev_priv: i915 device instance | |
1283 | * | |
1284 | * The FBC code needs to track CRTC visibility since the older platforms can't | |
1285 | * have FBC enabled while multiple pipes are used. This function does the | |
1286 | * initial setup at driver load to make sure FBC is matching the real hardware. | |
1287 | */ | |
1288 | void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv) | |
1289 | { | |
1290 | struct intel_crtc *crtc; | |
1291 | ||
1292 | /* Don't even bother tracking anything if we don't need. */ | |
1293 | if (!no_fbc_on_multiple_pipes(dev_priv)) | |
1294 | return; | |
1295 | ||
91c8a326 | 1296 | for_each_intel_crtc(&dev_priv->drm, crtc) |
525b9311 | 1297 | if (intel_crtc_active(crtc) && |
1d4258db | 1298 | crtc->base.primary->state->visible) |
010cf73d PZ |
1299 | dev_priv->fbc.visible_pipes_mask |= (1 << crtc->pipe); |
1300 | } | |
1301 | ||
80788a0f PZ |
1302 | /* |
1303 | * The DDX driver changes its behavior depending on the value it reads from | |
1304 | * i915.enable_fbc, so sanitize it by translating the default value into either | |
1305 | * 0 or 1 in order to allow it to know what's going on. | |
1306 | * | |
1307 | * Notice that this is done at driver initialization and we still allow user | |
1308 | * space to change the value during runtime without sanitizing it again. IGT | |
1309 | * relies on being able to change i915.enable_fbc at runtime. | |
1310 | */ | |
1311 | static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv) | |
1312 | { | |
1313 | if (i915.enable_fbc >= 0) | |
1314 | return !!i915.enable_fbc; | |
1315 | ||
36dbc4d7 CW |
1316 | if (!HAS_FBC(dev_priv)) |
1317 | return 0; | |
1318 | ||
fd7d6c5c | 1319 | if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) |
80788a0f PZ |
1320 | return 1; |
1321 | ||
1322 | return 0; | |
1323 | } | |
1324 | ||
36dbc4d7 CW |
1325 | static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv) |
1326 | { | |
36dbc4d7 | 1327 | /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */ |
80debff8 | 1328 | if (intel_vtd_active() && |
36dbc4d7 CW |
1329 | (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) { |
1330 | DRM_INFO("Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n"); | |
1331 | return true; | |
1332 | } | |
36dbc4d7 CW |
1333 | |
1334 | return false; | |
1335 | } | |
1336 | ||
94b83957 RV |
1337 | /** |
1338 | * intel_fbc_init - Initialize FBC | |
1339 | * @dev_priv: the i915 device | |
1340 | * | |
1341 | * This function might be called during PM init process. | |
1342 | */ | |
7ff0ebcc RV |
1343 | void intel_fbc_init(struct drm_i915_private *dev_priv) |
1344 | { | |
ab34a7e8 | 1345 | struct intel_fbc *fbc = &dev_priv->fbc; |
dbef0f15 PZ |
1346 | enum pipe pipe; |
1347 | ||
ab34a7e8 | 1348 | INIT_WORK(&fbc->work.work, intel_fbc_work_fn); |
61a585d6 | 1349 | INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn); |
ab34a7e8 PZ |
1350 | mutex_init(&fbc->lock); |
1351 | fbc->enabled = false; | |
1352 | fbc->active = false; | |
1353 | fbc->work.scheduled = false; | |
25ad93fd | 1354 | |
36dbc4d7 CW |
1355 | if (need_fbc_vtd_wa(dev_priv)) |
1356 | mkwrite_device_info(dev_priv)->has_fbc = false; | |
1357 | ||
80788a0f PZ |
1358 | i915.enable_fbc = intel_sanitize_fbc_option(dev_priv); |
1359 | DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n", i915.enable_fbc); | |
1360 | ||
7ff0ebcc | 1361 | if (!HAS_FBC(dev_priv)) { |
ab34a7e8 | 1362 | fbc->no_fbc_reason = "unsupported by this chipset"; |
7ff0ebcc RV |
1363 | return; |
1364 | } | |
1365 | ||
dbef0f15 | 1366 | for_each_pipe(dev_priv, pipe) { |
ab34a7e8 | 1367 | fbc->possible_framebuffer_bits |= |
dbef0f15 PZ |
1368 | INTEL_FRONTBUFFER_PRIMARY(pipe); |
1369 | ||
57105022 | 1370 | if (fbc_on_pipe_a_only(dev_priv)) |
dbef0f15 PZ |
1371 | break; |
1372 | } | |
1373 | ||
8c40074c | 1374 | /* This value was pulled out of someone's hat */ |
5697d60f | 1375 | if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv)) |
7ff0ebcc | 1376 | I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT); |
7ff0ebcc | 1377 | |
b07ea0fa | 1378 | /* We still don't have any sort of hardware state readout for FBC, so |
0e631adc PZ |
1379 | * deactivate it in case the BIOS activated it to make sure software |
1380 | * matches the hardware state. */ | |
8c40074c PZ |
1381 | if (intel_fbc_hw_is_active(dev_priv)) |
1382 | intel_fbc_hw_deactivate(dev_priv); | |
7ff0ebcc | 1383 | } |