Commit | Line | Data |
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7ff0ebcc RV |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
94b83957 RV |
24 | /** |
25 | * DOC: Frame Buffer Compression (FBC) | |
26 | * | |
27 | * FBC tries to save memory bandwidth (and so power consumption) by | |
28 | * compressing the amount of memory used by the display. It is total | |
29 | * transparent to user space and completely handled in the kernel. | |
7ff0ebcc RV |
30 | * |
31 | * The benefits of FBC are mostly visible with solid backgrounds and | |
94b83957 RV |
32 | * variation-less patterns. It comes from keeping the memory footprint small |
33 | * and having fewer memory pages opened and accessed for refreshing the display. | |
7ff0ebcc | 34 | * |
94b83957 RV |
35 | * i915 is responsible to reserve stolen memory for FBC and configure its |
36 | * offset on proper registers. The hardware takes care of all | |
37 | * compress/decompress. However there are many known cases where we have to | |
38 | * forcibly disable it to allow proper screen updates. | |
7ff0ebcc RV |
39 | */ |
40 | ||
94b83957 RV |
41 | #include "intel_drv.h" |
42 | #include "i915_drv.h" | |
43 | ||
9f218336 PZ |
44 | static inline bool fbc_supported(struct drm_i915_private *dev_priv) |
45 | { | |
46 | return dev_priv->fbc.enable_fbc != NULL; | |
47 | } | |
48 | ||
57105022 PZ |
49 | static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv) |
50 | { | |
51 | return IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8; | |
52 | } | |
53 | ||
2db3366b PZ |
54 | /* |
55 | * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the | |
56 | * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's | |
57 | * origin so the x and y offsets can actually fit the registers. As a | |
58 | * consequence, the fence doesn't really start exactly at the display plane | |
59 | * address we program because it starts at the real start of the buffer, so we | |
60 | * have to take this into consideration here. | |
61 | */ | |
62 | static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc) | |
63 | { | |
64 | return crtc->base.y - crtc->adjusted_y; | |
65 | } | |
66 | ||
7733b49b | 67 | static void i8xx_fbc_disable(struct drm_i915_private *dev_priv) |
7ff0ebcc | 68 | { |
7ff0ebcc RV |
69 | u32 fbc_ctl; |
70 | ||
71 | dev_priv->fbc.enabled = false; | |
72 | ||
73 | /* Disable compression */ | |
74 | fbc_ctl = I915_READ(FBC_CONTROL); | |
75 | if ((fbc_ctl & FBC_CTL_EN) == 0) | |
76 | return; | |
77 | ||
78 | fbc_ctl &= ~FBC_CTL_EN; | |
79 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
80 | ||
81 | /* Wait for compressing bit to clear */ | |
82 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { | |
83 | DRM_DEBUG_KMS("FBC idle timed out\n"); | |
84 | return; | |
85 | } | |
86 | ||
87 | DRM_DEBUG_KMS("disabled FBC\n"); | |
88 | } | |
89 | ||
220285f2 | 90 | static void i8xx_fbc_enable(struct intel_crtc *crtc) |
7ff0ebcc | 91 | { |
220285f2 PZ |
92 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
93 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
7ff0ebcc | 94 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
7ff0ebcc RV |
95 | int cfb_pitch; |
96 | int i; | |
97 | u32 fbc_ctl; | |
98 | ||
99 | dev_priv->fbc.enabled = true; | |
100 | ||
60ee5cd2 JN |
101 | /* Note: fbc.threshold == 1 for i8xx */ |
102 | cfb_pitch = dev_priv->fbc.uncompressed_size / FBC_LL_SIZE; | |
7ff0ebcc RV |
103 | if (fb->pitches[0] < cfb_pitch) |
104 | cfb_pitch = fb->pitches[0]; | |
105 | ||
106 | /* FBC_CTL wants 32B or 64B units */ | |
7733b49b | 107 | if (IS_GEN2(dev_priv)) |
7ff0ebcc RV |
108 | cfb_pitch = (cfb_pitch / 32) - 1; |
109 | else | |
110 | cfb_pitch = (cfb_pitch / 64) - 1; | |
111 | ||
112 | /* Clear old tags */ | |
113 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) | |
4d110c71 | 114 | I915_WRITE(FBC_TAG(i), 0); |
7ff0ebcc | 115 | |
7733b49b | 116 | if (IS_GEN4(dev_priv)) { |
7ff0ebcc RV |
117 | u32 fbc_ctl2; |
118 | ||
119 | /* Set it up... */ | |
120 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; | |
220285f2 | 121 | fbc_ctl2 |= FBC_CTL_PLANE(crtc->plane); |
7ff0ebcc | 122 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
2db3366b | 123 | I915_WRITE(FBC_FENCE_OFF, get_crtc_fence_y_offset(crtc)); |
7ff0ebcc RV |
124 | } |
125 | ||
126 | /* enable it... */ | |
127 | fbc_ctl = I915_READ(FBC_CONTROL); | |
128 | fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT; | |
129 | fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC; | |
7733b49b | 130 | if (IS_I945GM(dev_priv)) |
7ff0ebcc RV |
131 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
132 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; | |
133 | fbc_ctl |= obj->fence_reg; | |
134 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
135 | ||
136 | DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n", | |
220285f2 | 137 | cfb_pitch, crtc->base.y, plane_name(crtc->plane)); |
7ff0ebcc RV |
138 | } |
139 | ||
7733b49b | 140 | static bool i8xx_fbc_enabled(struct drm_i915_private *dev_priv) |
7ff0ebcc | 141 | { |
7ff0ebcc RV |
142 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; |
143 | } | |
144 | ||
220285f2 | 145 | static void g4x_fbc_enable(struct intel_crtc *crtc) |
7ff0ebcc | 146 | { |
220285f2 PZ |
147 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
148 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
7ff0ebcc | 149 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
7ff0ebcc RV |
150 | u32 dpfc_ctl; |
151 | ||
152 | dev_priv->fbc.enabled = true; | |
153 | ||
220285f2 | 154 | dpfc_ctl = DPFC_CTL_PLANE(crtc->plane) | DPFC_SR_EN; |
7ff0ebcc RV |
155 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
156 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
157 | else | |
158 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
159 | dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; | |
160 | ||
2db3366b | 161 | I915_WRITE(DPFC_FENCE_YOFF, get_crtc_fence_y_offset(crtc)); |
7ff0ebcc RV |
162 | |
163 | /* enable it... */ | |
164 | I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
165 | ||
220285f2 | 166 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane)); |
7ff0ebcc RV |
167 | } |
168 | ||
7733b49b | 169 | static void g4x_fbc_disable(struct drm_i915_private *dev_priv) |
7ff0ebcc | 170 | { |
7ff0ebcc RV |
171 | u32 dpfc_ctl; |
172 | ||
173 | dev_priv->fbc.enabled = false; | |
174 | ||
175 | /* Disable compression */ | |
176 | dpfc_ctl = I915_READ(DPFC_CONTROL); | |
177 | if (dpfc_ctl & DPFC_CTL_EN) { | |
178 | dpfc_ctl &= ~DPFC_CTL_EN; | |
179 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); | |
180 | ||
181 | DRM_DEBUG_KMS("disabled FBC\n"); | |
182 | } | |
183 | } | |
184 | ||
7733b49b | 185 | static bool g4x_fbc_enabled(struct drm_i915_private *dev_priv) |
7ff0ebcc | 186 | { |
7ff0ebcc RV |
187 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; |
188 | } | |
189 | ||
d5ce4164 PZ |
190 | /* This function forces a CFB recompression through the nuke operation. */ |
191 | static void intel_fbc_recompress(struct drm_i915_private *dev_priv) | |
7ff0ebcc | 192 | { |
dbef0f15 PZ |
193 | I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE); |
194 | POSTING_READ(MSG_FBC_REND_STATE); | |
7ff0ebcc RV |
195 | } |
196 | ||
220285f2 | 197 | static void ilk_fbc_enable(struct intel_crtc *crtc) |
7ff0ebcc | 198 | { |
220285f2 PZ |
199 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
200 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
7ff0ebcc | 201 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
7ff0ebcc | 202 | u32 dpfc_ctl; |
ce65e47b | 203 | int threshold = dev_priv->fbc.threshold; |
2db3366b | 204 | unsigned int y_offset; |
7ff0ebcc RV |
205 | |
206 | dev_priv->fbc.enabled = true; | |
207 | ||
220285f2 | 208 | dpfc_ctl = DPFC_CTL_PLANE(crtc->plane); |
7ff0ebcc | 209 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
ce65e47b | 210 | threshold++; |
7ff0ebcc | 211 | |
ce65e47b | 212 | switch (threshold) { |
7ff0ebcc RV |
213 | case 4: |
214 | case 3: | |
215 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; | |
216 | break; | |
217 | case 2: | |
218 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
219 | break; | |
220 | case 1: | |
221 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
222 | break; | |
223 | } | |
224 | dpfc_ctl |= DPFC_CTL_FENCE_EN; | |
7733b49b | 225 | if (IS_GEN5(dev_priv)) |
7ff0ebcc RV |
226 | dpfc_ctl |= obj->fence_reg; |
227 | ||
2db3366b PZ |
228 | y_offset = get_crtc_fence_y_offset(crtc); |
229 | I915_WRITE(ILK_DPFC_FENCE_YOFF, y_offset); | |
7ff0ebcc RV |
230 | I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID); |
231 | /* enable it... */ | |
232 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
233 | ||
7733b49b | 234 | if (IS_GEN6(dev_priv)) { |
7ff0ebcc RV |
235 | I915_WRITE(SNB_DPFC_CTL_SA, |
236 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); | |
2db3366b | 237 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, y_offset); |
7ff0ebcc RV |
238 | } |
239 | ||
d5ce4164 | 240 | intel_fbc_recompress(dev_priv); |
dbef0f15 | 241 | |
220285f2 | 242 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane)); |
7ff0ebcc RV |
243 | } |
244 | ||
7733b49b | 245 | static void ilk_fbc_disable(struct drm_i915_private *dev_priv) |
7ff0ebcc | 246 | { |
7ff0ebcc RV |
247 | u32 dpfc_ctl; |
248 | ||
249 | dev_priv->fbc.enabled = false; | |
250 | ||
251 | /* Disable compression */ | |
252 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
253 | if (dpfc_ctl & DPFC_CTL_EN) { | |
254 | dpfc_ctl &= ~DPFC_CTL_EN; | |
255 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); | |
256 | ||
257 | DRM_DEBUG_KMS("disabled FBC\n"); | |
258 | } | |
259 | } | |
260 | ||
7733b49b | 261 | static bool ilk_fbc_enabled(struct drm_i915_private *dev_priv) |
7ff0ebcc | 262 | { |
7ff0ebcc RV |
263 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; |
264 | } | |
265 | ||
220285f2 | 266 | static void gen7_fbc_enable(struct intel_crtc *crtc) |
7ff0ebcc | 267 | { |
220285f2 PZ |
268 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
269 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
7ff0ebcc | 270 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
7ff0ebcc | 271 | u32 dpfc_ctl; |
ce65e47b | 272 | int threshold = dev_priv->fbc.threshold; |
7ff0ebcc RV |
273 | |
274 | dev_priv->fbc.enabled = true; | |
275 | ||
d8514d63 | 276 | dpfc_ctl = 0; |
7733b49b | 277 | if (IS_IVYBRIDGE(dev_priv)) |
220285f2 | 278 | dpfc_ctl |= IVB_DPFC_CTL_PLANE(crtc->plane); |
d8514d63 | 279 | |
7ff0ebcc | 280 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
ce65e47b | 281 | threshold++; |
7ff0ebcc | 282 | |
ce65e47b | 283 | switch (threshold) { |
7ff0ebcc RV |
284 | case 4: |
285 | case 3: | |
286 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; | |
287 | break; | |
288 | case 2: | |
289 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
290 | break; | |
291 | case 1: | |
292 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
293 | break; | |
294 | } | |
295 | ||
296 | dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; | |
297 | ||
298 | if (dev_priv->fbc.false_color) | |
299 | dpfc_ctl |= FBC_CTL_FALSE_COLOR; | |
300 | ||
7733b49b | 301 | if (IS_IVYBRIDGE(dev_priv)) { |
7ff0ebcc RV |
302 | /* WaFbcAsynchFlipDisableFbcQueue:ivb */ |
303 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
304 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
305 | ILK_FBCQ_DIS); | |
40f4022e | 306 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
7ff0ebcc | 307 | /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ |
220285f2 PZ |
308 | I915_WRITE(CHICKEN_PIPESL_1(crtc->pipe), |
309 | I915_READ(CHICKEN_PIPESL_1(crtc->pipe)) | | |
7ff0ebcc RV |
310 | HSW_FBCQ_DIS); |
311 | } | |
312 | ||
57012be9 PZ |
313 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
314 | ||
7ff0ebcc RV |
315 | I915_WRITE(SNB_DPFC_CTL_SA, |
316 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); | |
2db3366b | 317 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, get_crtc_fence_y_offset(crtc)); |
7ff0ebcc | 318 | |
d5ce4164 | 319 | intel_fbc_recompress(dev_priv); |
7ff0ebcc | 320 | |
220285f2 | 321 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane)); |
7ff0ebcc RV |
322 | } |
323 | ||
94b83957 RV |
324 | /** |
325 | * intel_fbc_enabled - Is FBC enabled? | |
7733b49b | 326 | * @dev_priv: i915 device instance |
94b83957 RV |
327 | * |
328 | * This function is used to verify the current state of FBC. | |
329 | * FIXME: This should be tracked in the plane config eventually | |
330 | * instead of queried at runtime for most callers. | |
331 | */ | |
7733b49b | 332 | bool intel_fbc_enabled(struct drm_i915_private *dev_priv) |
7ff0ebcc | 333 | { |
7ff0ebcc RV |
334 | return dev_priv->fbc.enabled; |
335 | } | |
336 | ||
e8cb8d69 PZ |
337 | static void intel_fbc_enable(struct intel_crtc *crtc, |
338 | const struct drm_framebuffer *fb) | |
339 | { | |
340 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
341 | ||
342 | dev_priv->fbc.enable_fbc(crtc); | |
343 | ||
344 | dev_priv->fbc.crtc = crtc; | |
345 | dev_priv->fbc.fb_id = fb->base.id; | |
346 | dev_priv->fbc.y = crtc->base.y; | |
347 | } | |
348 | ||
7ff0ebcc RV |
349 | static void intel_fbc_work_fn(struct work_struct *__work) |
350 | { | |
351 | struct intel_fbc_work *work = | |
352 | container_of(to_delayed_work(__work), | |
353 | struct intel_fbc_work, work); | |
220285f2 PZ |
354 | struct drm_i915_private *dev_priv = work->crtc->base.dev->dev_private; |
355 | struct drm_framebuffer *crtc_fb = work->crtc->base.primary->fb; | |
7ff0ebcc | 356 | |
25ad93fd | 357 | mutex_lock(&dev_priv->fbc.lock); |
7ff0ebcc RV |
358 | if (work == dev_priv->fbc.fbc_work) { |
359 | /* Double check that we haven't switched fb without cancelling | |
360 | * the prior work. | |
361 | */ | |
e8cb8d69 PZ |
362 | if (crtc_fb == work->fb) |
363 | intel_fbc_enable(work->crtc, work->fb); | |
7ff0ebcc RV |
364 | |
365 | dev_priv->fbc.fbc_work = NULL; | |
366 | } | |
25ad93fd | 367 | mutex_unlock(&dev_priv->fbc.lock); |
7ff0ebcc RV |
368 | |
369 | kfree(work); | |
370 | } | |
371 | ||
372 | static void intel_fbc_cancel_work(struct drm_i915_private *dev_priv) | |
373 | { | |
25ad93fd PZ |
374 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
375 | ||
7ff0ebcc RV |
376 | if (dev_priv->fbc.fbc_work == NULL) |
377 | return; | |
378 | ||
379 | DRM_DEBUG_KMS("cancelling pending FBC enable\n"); | |
380 | ||
381 | /* Synchronisation is provided by struct_mutex and checking of | |
382 | * dev_priv->fbc.fbc_work, so we can perform the cancellation | |
383 | * entirely asynchronously. | |
384 | */ | |
385 | if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work)) | |
386 | /* tasklet was killed before being run, clean up */ | |
387 | kfree(dev_priv->fbc.fbc_work); | |
388 | ||
389 | /* Mark the work as no longer wanted so that if it does | |
390 | * wake-up (because the work was already running and waiting | |
391 | * for our mutex), it will discover that is no longer | |
392 | * necessary to run. | |
393 | */ | |
394 | dev_priv->fbc.fbc_work = NULL; | |
395 | } | |
396 | ||
e8cb8d69 | 397 | static void intel_fbc_schedule_enable(struct intel_crtc *crtc) |
7ff0ebcc RV |
398 | { |
399 | struct intel_fbc_work *work; | |
220285f2 | 400 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
7ff0ebcc | 401 | |
25ad93fd PZ |
402 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
403 | ||
7ff0ebcc RV |
404 | intel_fbc_cancel_work(dev_priv); |
405 | ||
406 | work = kzalloc(sizeof(*work), GFP_KERNEL); | |
407 | if (work == NULL) { | |
408 | DRM_ERROR("Failed to allocate FBC work structure\n"); | |
e8cb8d69 | 409 | intel_fbc_enable(crtc, crtc->base.primary->fb); |
7ff0ebcc RV |
410 | return; |
411 | } | |
412 | ||
413 | work->crtc = crtc; | |
220285f2 | 414 | work->fb = crtc->base.primary->fb; |
7ff0ebcc RV |
415 | INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); |
416 | ||
417 | dev_priv->fbc.fbc_work = work; | |
418 | ||
419 | /* Delay the actual enabling to let pageflipping cease and the | |
420 | * display to settle before starting the compression. Note that | |
421 | * this delay also serves a second purpose: it allows for a | |
422 | * vblank to pass after disabling the FBC before we attempt | |
423 | * to modify the control registers. | |
424 | * | |
425 | * A more complicated solution would involve tracking vblanks | |
426 | * following the termination of the page-flipping sequence | |
427 | * and indeed performing the enable as a co-routine and not | |
428 | * waiting synchronously upon the vblank. | |
429 | * | |
430 | * WaFbcWaitForVBlankBeforeEnable:ilk,snb | |
431 | */ | |
432 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); | |
433 | } | |
434 | ||
7733b49b | 435 | static void __intel_fbc_disable(struct drm_i915_private *dev_priv) |
25ad93fd | 436 | { |
25ad93fd PZ |
437 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
438 | ||
439 | intel_fbc_cancel_work(dev_priv); | |
440 | ||
7733b49b | 441 | dev_priv->fbc.disable_fbc(dev_priv); |
25ad93fd PZ |
442 | dev_priv->fbc.crtc = NULL; |
443 | } | |
444 | ||
94b83957 RV |
445 | /** |
446 | * intel_fbc_disable - disable FBC | |
7733b49b | 447 | * @dev_priv: i915 device instance |
94b83957 RV |
448 | * |
449 | * This function disables FBC. | |
450 | */ | |
7733b49b | 451 | void intel_fbc_disable(struct drm_i915_private *dev_priv) |
7ff0ebcc | 452 | { |
9f218336 | 453 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
454 | return; |
455 | ||
25ad93fd | 456 | mutex_lock(&dev_priv->fbc.lock); |
7733b49b | 457 | __intel_fbc_disable(dev_priv); |
25ad93fd PZ |
458 | mutex_unlock(&dev_priv->fbc.lock); |
459 | } | |
7ff0ebcc | 460 | |
25ad93fd PZ |
461 | /* |
462 | * intel_fbc_disable_crtc - disable FBC if it's associated with crtc | |
463 | * @crtc: the CRTC | |
464 | * | |
465 | * This function disables FBC if it's associated with the provided CRTC. | |
466 | */ | |
467 | void intel_fbc_disable_crtc(struct intel_crtc *crtc) | |
468 | { | |
7733b49b | 469 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
7ff0ebcc | 470 | |
9f218336 | 471 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
472 | return; |
473 | ||
25ad93fd PZ |
474 | mutex_lock(&dev_priv->fbc.lock); |
475 | if (dev_priv->fbc.crtc == crtc) | |
7733b49b | 476 | __intel_fbc_disable(dev_priv); |
25ad93fd | 477 | mutex_unlock(&dev_priv->fbc.lock); |
7ff0ebcc RV |
478 | } |
479 | ||
2e8144a5 | 480 | static void set_no_fbc_reason(struct drm_i915_private *dev_priv, |
bf6189c6 | 481 | const char *reason) |
7ff0ebcc RV |
482 | { |
483 | if (dev_priv->fbc.no_fbc_reason == reason) | |
2e8144a5 | 484 | return; |
7ff0ebcc RV |
485 | |
486 | dev_priv->fbc.no_fbc_reason = reason; | |
bf6189c6 | 487 | DRM_DEBUG_KMS("Disabling FBC: %s\n", reason); |
7ff0ebcc RV |
488 | } |
489 | ||
30c58d58 PZ |
490 | static bool crtc_is_valid(struct intel_crtc *crtc) |
491 | { | |
492 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
493 | ||
494 | if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A) | |
495 | return false; | |
496 | ||
497 | if (!intel_crtc_active(&crtc->base)) | |
498 | return false; | |
499 | ||
500 | if (!to_intel_plane_state(crtc->base.primary->state)->visible) | |
501 | return false; | |
502 | ||
503 | return true; | |
504 | } | |
505 | ||
95106753 PZ |
506 | static struct drm_crtc *intel_fbc_find_crtc(struct drm_i915_private *dev_priv) |
507 | { | |
95106753 | 508 | struct drm_crtc *crtc = NULL, *tmp_crtc; |
68b92147 | 509 | enum pipe pipe; |
68b92147 PZ |
510 | |
511 | for_each_pipe(dev_priv, pipe) { | |
512 | tmp_crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
95106753 | 513 | |
30c58d58 | 514 | if (crtc_is_valid(to_intel_crtc(tmp_crtc))) |
95106753 | 515 | crtc = tmp_crtc; |
95106753 PZ |
516 | } |
517 | ||
a4dedd5a | 518 | if (!crtc) |
95106753 | 519 | return NULL; |
95106753 PZ |
520 | |
521 | return crtc; | |
522 | } | |
523 | ||
232fd934 PZ |
524 | static bool multiple_pipes_ok(struct drm_i915_private *dev_priv) |
525 | { | |
526 | enum pipe pipe; | |
527 | int n_pipes = 0; | |
528 | struct drm_crtc *crtc; | |
529 | ||
530 | if (INTEL_INFO(dev_priv)->gen > 4) | |
531 | return true; | |
532 | ||
533 | for_each_pipe(dev_priv, pipe) { | |
534 | crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
535 | ||
536 | if (intel_crtc_active(crtc) && | |
537 | to_intel_plane_state(crtc->primary->state)->visible) | |
538 | n_pipes++; | |
539 | } | |
540 | ||
541 | return (n_pipes < 2); | |
542 | } | |
543 | ||
7733b49b | 544 | static int find_compression_threshold(struct drm_i915_private *dev_priv, |
fc786728 PZ |
545 | struct drm_mm_node *node, |
546 | int size, | |
547 | int fb_cpp) | |
548 | { | |
fc786728 PZ |
549 | int compression_threshold = 1; |
550 | int ret; | |
a9da512b PZ |
551 | u64 end; |
552 | ||
553 | /* The FBC hardware for BDW/SKL doesn't have access to the stolen | |
554 | * reserved range size, so it always assumes the maximum (8mb) is used. | |
555 | * If we enable FBC using a CFB on that memory range we'll get FIFO | |
556 | * underruns, even if that range is not reserved by the BIOS. */ | |
ef11bdb3 RV |
557 | if (IS_BROADWELL(dev_priv) || |
558 | IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) | |
a9da512b PZ |
559 | end = dev_priv->gtt.stolen_size - 8 * 1024 * 1024; |
560 | else | |
561 | end = dev_priv->gtt.stolen_usable_size; | |
fc786728 PZ |
562 | |
563 | /* HACK: This code depends on what we will do in *_enable_fbc. If that | |
564 | * code changes, this code needs to change as well. | |
565 | * | |
566 | * The enable_fbc code will attempt to use one of our 2 compression | |
567 | * thresholds, therefore, in that case, we only have 1 resort. | |
568 | */ | |
569 | ||
570 | /* Try to over-allocate to reduce reallocations and fragmentation. */ | |
a9da512b PZ |
571 | ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1, |
572 | 4096, 0, end); | |
fc786728 PZ |
573 | if (ret == 0) |
574 | return compression_threshold; | |
575 | ||
576 | again: | |
577 | /* HW's ability to limit the CFB is 1:4 */ | |
578 | if (compression_threshold > 4 || | |
579 | (fb_cpp == 2 && compression_threshold == 2)) | |
580 | return 0; | |
581 | ||
a9da512b PZ |
582 | ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1, |
583 | 4096, 0, end); | |
7733b49b | 584 | if (ret && INTEL_INFO(dev_priv)->gen <= 4) { |
fc786728 PZ |
585 | return 0; |
586 | } else if (ret) { | |
587 | compression_threshold <<= 1; | |
588 | goto again; | |
589 | } else { | |
590 | return compression_threshold; | |
591 | } | |
592 | } | |
593 | ||
7733b49b PZ |
594 | static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv, int size, |
595 | int fb_cpp) | |
fc786728 | 596 | { |
fc786728 PZ |
597 | struct drm_mm_node *uninitialized_var(compressed_llb); |
598 | int ret; | |
599 | ||
7733b49b | 600 | ret = find_compression_threshold(dev_priv, &dev_priv->fbc.compressed_fb, |
fc786728 PZ |
601 | size, fb_cpp); |
602 | if (!ret) | |
603 | goto err_llb; | |
604 | else if (ret > 1) { | |
605 | DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n"); | |
606 | ||
607 | } | |
608 | ||
609 | dev_priv->fbc.threshold = ret; | |
610 | ||
611 | if (INTEL_INFO(dev_priv)->gen >= 5) | |
612 | I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start); | |
7733b49b | 613 | else if (IS_GM45(dev_priv)) { |
fc786728 PZ |
614 | I915_WRITE(DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start); |
615 | } else { | |
616 | compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL); | |
617 | if (!compressed_llb) | |
618 | goto err_fb; | |
619 | ||
620 | ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb, | |
621 | 4096, 4096); | |
622 | if (ret) | |
623 | goto err_fb; | |
624 | ||
625 | dev_priv->fbc.compressed_llb = compressed_llb; | |
626 | ||
627 | I915_WRITE(FBC_CFB_BASE, | |
628 | dev_priv->mm.stolen_base + dev_priv->fbc.compressed_fb.start); | |
629 | I915_WRITE(FBC_LL_BASE, | |
630 | dev_priv->mm.stolen_base + compressed_llb->start); | |
631 | } | |
632 | ||
633 | dev_priv->fbc.uncompressed_size = size; | |
634 | ||
b8bf5d7f PZ |
635 | DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n", |
636 | dev_priv->fbc.compressed_fb.size, | |
637 | dev_priv->fbc.threshold); | |
fc786728 PZ |
638 | |
639 | return 0; | |
640 | ||
641 | err_fb: | |
642 | kfree(compressed_llb); | |
643 | i915_gem_stolen_remove_node(dev_priv, &dev_priv->fbc.compressed_fb); | |
644 | err_llb: | |
645 | pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size); | |
646 | return -ENOSPC; | |
647 | } | |
648 | ||
7733b49b | 649 | static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) |
fc786728 | 650 | { |
fc786728 PZ |
651 | if (dev_priv->fbc.uncompressed_size == 0) |
652 | return; | |
653 | ||
654 | i915_gem_stolen_remove_node(dev_priv, &dev_priv->fbc.compressed_fb); | |
655 | ||
656 | if (dev_priv->fbc.compressed_llb) { | |
657 | i915_gem_stolen_remove_node(dev_priv, | |
658 | dev_priv->fbc.compressed_llb); | |
659 | kfree(dev_priv->fbc.compressed_llb); | |
660 | } | |
661 | ||
662 | dev_priv->fbc.uncompressed_size = 0; | |
663 | } | |
664 | ||
7733b49b | 665 | void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) |
25ad93fd | 666 | { |
9f218336 | 667 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
668 | return; |
669 | ||
25ad93fd | 670 | mutex_lock(&dev_priv->fbc.lock); |
7733b49b | 671 | __intel_fbc_cleanup_cfb(dev_priv); |
25ad93fd PZ |
672 | mutex_unlock(&dev_priv->fbc.lock); |
673 | } | |
674 | ||
c4ffd409 PZ |
675 | /* |
676 | * For SKL+, the plane source size used by the hardware is based on the value we | |
677 | * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value | |
678 | * we wrote to PIPESRC. | |
679 | */ | |
680 | static void intel_fbc_get_plane_source_size(struct intel_crtc *crtc, | |
681 | int *width, int *height) | |
fc786728 | 682 | { |
c4ffd409 PZ |
683 | struct intel_plane_state *plane_state = |
684 | to_intel_plane_state(crtc->base.primary->state); | |
685 | int w, h; | |
686 | ||
687 | if (intel_rotation_90_or_270(plane_state->base.rotation)) { | |
688 | w = drm_rect_height(&plane_state->src) >> 16; | |
689 | h = drm_rect_width(&plane_state->src) >> 16; | |
690 | } else { | |
691 | w = drm_rect_width(&plane_state->src) >> 16; | |
692 | h = drm_rect_height(&plane_state->src) >> 16; | |
693 | } | |
694 | ||
695 | if (width) | |
696 | *width = w; | |
697 | if (height) | |
698 | *height = h; | |
699 | } | |
700 | ||
701 | static int intel_fbc_calculate_cfb_size(struct intel_crtc *crtc) | |
702 | { | |
703 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
704 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
705 | int lines; | |
706 | ||
707 | intel_fbc_get_plane_source_size(crtc, NULL, &lines); | |
708 | if (INTEL_INFO(dev_priv)->gen >= 7) | |
709 | lines = min(lines, 2048); | |
710 | ||
711 | return lines * fb->pitches[0]; | |
712 | } | |
713 | ||
714 | static int intel_fbc_setup_cfb(struct intel_crtc *crtc) | |
715 | { | |
716 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
717 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
718 | int size, cpp; | |
719 | ||
720 | size = intel_fbc_calculate_cfb_size(crtc); | |
721 | cpp = drm_format_plane_cpp(fb->pixel_format, 0); | |
722 | ||
fc786728 PZ |
723 | if (size <= dev_priv->fbc.uncompressed_size) |
724 | return 0; | |
725 | ||
726 | /* Release any current block */ | |
7733b49b | 727 | __intel_fbc_cleanup_cfb(dev_priv); |
fc786728 | 728 | |
c4ffd409 | 729 | return intel_fbc_alloc_cfb(dev_priv, size, cpp); |
fc786728 PZ |
730 | } |
731 | ||
adf70c65 PZ |
732 | static bool stride_is_valid(struct drm_i915_private *dev_priv, |
733 | unsigned int stride) | |
734 | { | |
735 | /* These should have been caught earlier. */ | |
736 | WARN_ON(stride < 512); | |
737 | WARN_ON((stride & (64 - 1)) != 0); | |
738 | ||
739 | /* Below are the additional FBC restrictions. */ | |
740 | ||
741 | if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv)) | |
742 | return stride == 4096 || stride == 8192; | |
743 | ||
744 | if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048) | |
745 | return false; | |
746 | ||
747 | if (stride > 16384) | |
748 | return false; | |
749 | ||
750 | return true; | |
751 | } | |
752 | ||
b9e831dc PZ |
753 | static bool pixel_format_is_valid(struct drm_framebuffer *fb) |
754 | { | |
755 | struct drm_device *dev = fb->dev; | |
756 | struct drm_i915_private *dev_priv = dev->dev_private; | |
757 | ||
758 | switch (fb->pixel_format) { | |
759 | case DRM_FORMAT_XRGB8888: | |
760 | case DRM_FORMAT_XBGR8888: | |
761 | return true; | |
762 | case DRM_FORMAT_XRGB1555: | |
763 | case DRM_FORMAT_RGB565: | |
764 | /* 16bpp not supported on gen2 */ | |
765 | if (IS_GEN2(dev)) | |
766 | return false; | |
767 | /* WaFbcOnly1to1Ratio:ctg */ | |
768 | if (IS_G4X(dev_priv)) | |
769 | return false; | |
770 | return true; | |
771 | default: | |
772 | return false; | |
773 | } | |
774 | } | |
775 | ||
856312ae PZ |
776 | /* |
777 | * For some reason, the hardware tracking starts looking at whatever we | |
778 | * programmed as the display plane base address register. It does not look at | |
779 | * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y} | |
780 | * variables instead of just looking at the pipe/plane size. | |
781 | */ | |
782 | static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc) | |
3c5f174e PZ |
783 | { |
784 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
856312ae | 785 | unsigned int effective_w, effective_h, max_w, max_h; |
3c5f174e PZ |
786 | |
787 | if (INTEL_INFO(dev_priv)->gen >= 8 || IS_HASWELL(dev_priv)) { | |
788 | max_w = 4096; | |
789 | max_h = 4096; | |
790 | } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { | |
791 | max_w = 4096; | |
792 | max_h = 2048; | |
793 | } else { | |
794 | max_w = 2048; | |
795 | max_h = 1536; | |
796 | } | |
797 | ||
856312ae PZ |
798 | intel_fbc_get_plane_source_size(crtc, &effective_w, &effective_h); |
799 | effective_w += crtc->adjusted_x; | |
800 | effective_h += crtc->adjusted_y; | |
801 | ||
802 | return effective_w <= max_w && effective_h <= max_h; | |
3c5f174e PZ |
803 | } |
804 | ||
7ff0ebcc | 805 | /** |
25ad93fd | 806 | * __intel_fbc_update - enable/disable FBC as needed, unlocked |
7733b49b | 807 | * @dev_priv: i915 device instance |
7ff0ebcc RV |
808 | * |
809 | * Set up the framebuffer compression hardware at mode set time. We | |
810 | * enable it if possible: | |
811 | * - plane A only (on pre-965) | |
812 | * - no pixel mulitply/line duplication | |
813 | * - no alpha buffer discard | |
814 | * - no dual wide | |
815 | * - framebuffer <= max_hdisplay in width, max_vdisplay in height | |
816 | * | |
817 | * We can't assume that any compression will take place (worst case), | |
818 | * so the compressed buffer has to be the same size as the uncompressed | |
819 | * one. It also must reside (along with the line length buffer) in | |
820 | * stolen memory. | |
821 | * | |
822 | * We need to enable/disable FBC on a global basis. | |
823 | */ | |
7733b49b | 824 | static void __intel_fbc_update(struct drm_i915_private *dev_priv) |
7ff0ebcc | 825 | { |
95106753 | 826 | struct drm_crtc *crtc = NULL; |
7ff0ebcc RV |
827 | struct intel_crtc *intel_crtc; |
828 | struct drm_framebuffer *fb; | |
829 | struct drm_i915_gem_object *obj; | |
830 | const struct drm_display_mode *adjusted_mode; | |
7ff0ebcc | 831 | |
25ad93fd PZ |
832 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
833 | ||
bd49234b | 834 | /* disable framebuffer compression in vGPU */ |
7733b49b | 835 | if (intel_vgpu_active(dev_priv->dev)) |
bd49234b YZ |
836 | i915.enable_fbc = 0; |
837 | ||
7cc65746 | 838 | if (i915.enable_fbc < 0) { |
bf6189c6 | 839 | set_no_fbc_reason(dev_priv, "disabled per chip default"); |
7cc65746 PZ |
840 | goto out_disable; |
841 | } | |
842 | ||
ab585dea | 843 | if (!i915.enable_fbc) { |
bf6189c6 | 844 | set_no_fbc_reason(dev_priv, "disabled per module param"); |
7cc65746 | 845 | goto out_disable; |
7ff0ebcc RV |
846 | } |
847 | ||
848 | /* | |
849 | * If FBC is already on, we just have to verify that we can | |
850 | * keep it that way... | |
851 | * Need to disable if: | |
852 | * - more than one pipe is active | |
853 | * - changing FBC params (stride, fence, mode) | |
854 | * - new fb is too large to fit in compressed buffer | |
855 | * - going to an unsupported config (interlace, pixel multiply, etc.) | |
856 | */ | |
95106753 | 857 | crtc = intel_fbc_find_crtc(dev_priv); |
8df5dd57 | 858 | if (!crtc) { |
bf6189c6 | 859 | set_no_fbc_reason(dev_priv, "no output"); |
7ff0ebcc | 860 | goto out_disable; |
8df5dd57 | 861 | } |
7ff0ebcc | 862 | |
232fd934 | 863 | if (!multiple_pipes_ok(dev_priv)) { |
bf6189c6 | 864 | set_no_fbc_reason(dev_priv, "more than one pipe active"); |
232fd934 PZ |
865 | goto out_disable; |
866 | } | |
867 | ||
7ff0ebcc RV |
868 | intel_crtc = to_intel_crtc(crtc); |
869 | fb = crtc->primary->fb; | |
870 | obj = intel_fb_obj(fb); | |
6e3c9717 | 871 | adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
7ff0ebcc | 872 | |
7ff0ebcc RV |
873 | if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) || |
874 | (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) { | |
bf6189c6 | 875 | set_no_fbc_reason(dev_priv, "incompatible mode"); |
7ff0ebcc RV |
876 | goto out_disable; |
877 | } | |
878 | ||
856312ae | 879 | if (!intel_fbc_hw_tracking_covers_screen(intel_crtc)) { |
bf6189c6 | 880 | set_no_fbc_reason(dev_priv, "mode too large for compression"); |
7ff0ebcc RV |
881 | goto out_disable; |
882 | } | |
3c5f174e | 883 | |
7733b49b | 884 | if ((INTEL_INFO(dev_priv)->gen < 4 || HAS_DDI(dev_priv)) && |
7ff0ebcc | 885 | intel_crtc->plane != PLANE_A) { |
bf6189c6 | 886 | set_no_fbc_reason(dev_priv, "FBC unsupported on plane"); |
7ff0ebcc RV |
887 | goto out_disable; |
888 | } | |
889 | ||
890 | /* The use of a CPU fence is mandatory in order to detect writes | |
891 | * by the CPU to the scanout and trigger updates to the FBC. | |
892 | */ | |
893 | if (obj->tiling_mode != I915_TILING_X || | |
894 | obj->fence_reg == I915_FENCE_REG_NONE) { | |
bf6189c6 | 895 | set_no_fbc_reason(dev_priv, "framebuffer not tiled or fenced"); |
7ff0ebcc RV |
896 | goto out_disable; |
897 | } | |
7733b49b | 898 | if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) && |
8e7d688b | 899 | crtc->primary->state->rotation != BIT(DRM_ROTATE_0)) { |
bf6189c6 | 900 | set_no_fbc_reason(dev_priv, "rotation unsupported"); |
7ff0ebcc RV |
901 | goto out_disable; |
902 | } | |
903 | ||
adf70c65 | 904 | if (!stride_is_valid(dev_priv, fb->pitches[0])) { |
bf6189c6 | 905 | set_no_fbc_reason(dev_priv, "framebuffer stride not supported"); |
adf70c65 PZ |
906 | goto out_disable; |
907 | } | |
908 | ||
b9e831dc | 909 | if (!pixel_format_is_valid(fb)) { |
bf6189c6 | 910 | set_no_fbc_reason(dev_priv, "pixel format is invalid"); |
b9e831dc PZ |
911 | goto out_disable; |
912 | } | |
913 | ||
7ff0ebcc | 914 | /* If the kernel debugger is active, always disable compression */ |
89351085 | 915 | if (in_dbg_master()) { |
bf6189c6 | 916 | set_no_fbc_reason(dev_priv, "Kernel debugger is active"); |
7ff0ebcc | 917 | goto out_disable; |
89351085 | 918 | } |
7ff0ebcc | 919 | |
7b24c9a6 PZ |
920 | /* WaFbcExceedCdClockThreshold:hsw,bdw */ |
921 | if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) && | |
922 | ilk_pipe_pixel_rate(intel_crtc->config) >= | |
923 | dev_priv->cdclk_freq * 95 / 100) { | |
bf6189c6 | 924 | set_no_fbc_reason(dev_priv, "pixel rate is too big"); |
7b24c9a6 PZ |
925 | goto out_disable; |
926 | } | |
927 | ||
c4ffd409 | 928 | if (intel_fbc_setup_cfb(intel_crtc)) { |
bf6189c6 | 929 | set_no_fbc_reason(dev_priv, "not enough stolen memory"); |
7ff0ebcc RV |
930 | goto out_disable; |
931 | } | |
932 | ||
933 | /* If the scanout has not changed, don't modify the FBC settings. | |
934 | * Note that we make the fundamental assumption that the fb->obj | |
935 | * cannot be unpinned (and have its GTT offset and fence revoked) | |
936 | * without first being decoupled from the scanout and FBC disabled. | |
937 | */ | |
e35fef21 | 938 | if (dev_priv->fbc.crtc == intel_crtc && |
7ff0ebcc RV |
939 | dev_priv->fbc.fb_id == fb->base.id && |
940 | dev_priv->fbc.y == crtc->y) | |
941 | return; | |
942 | ||
7733b49b | 943 | if (intel_fbc_enabled(dev_priv)) { |
7ff0ebcc RV |
944 | /* We update FBC along two paths, after changing fb/crtc |
945 | * configuration (modeswitching) and after page-flipping | |
946 | * finishes. For the latter, we know that not only did | |
947 | * we disable the FBC at the start of the page-flip | |
948 | * sequence, but also more than one vblank has passed. | |
949 | * | |
950 | * For the former case of modeswitching, it is possible | |
951 | * to switch between two FBC valid configurations | |
952 | * instantaneously so we do need to disable the FBC | |
953 | * before we can modify its control registers. We also | |
954 | * have to wait for the next vblank for that to take | |
955 | * effect. However, since we delay enabling FBC we can | |
956 | * assume that a vblank has passed since disabling and | |
957 | * that we can safely alter the registers in the deferred | |
958 | * callback. | |
959 | * | |
960 | * In the scenario that we go from a valid to invalid | |
961 | * and then back to valid FBC configuration we have | |
962 | * no strict enforcement that a vblank occurred since | |
963 | * disabling the FBC. However, along all current pipe | |
964 | * disabling paths we do need to wait for a vblank at | |
965 | * some point. And we wait before enabling FBC anyway. | |
966 | */ | |
967 | DRM_DEBUG_KMS("disabling active FBC for update\n"); | |
7733b49b | 968 | __intel_fbc_disable(dev_priv); |
7ff0ebcc RV |
969 | } |
970 | ||
e8cb8d69 | 971 | intel_fbc_schedule_enable(intel_crtc); |
793af070 | 972 | dev_priv->fbc.no_fbc_reason = "FBC enabled (not necessarily active)"; |
7ff0ebcc RV |
973 | return; |
974 | ||
975 | out_disable: | |
976 | /* Multiple disables should be harmless */ | |
7733b49b | 977 | if (intel_fbc_enabled(dev_priv)) { |
7ff0ebcc | 978 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); |
7733b49b | 979 | __intel_fbc_disable(dev_priv); |
7ff0ebcc | 980 | } |
7733b49b | 981 | __intel_fbc_cleanup_cfb(dev_priv); |
25ad93fd PZ |
982 | } |
983 | ||
984 | /* | |
985 | * intel_fbc_update - enable/disable FBC as needed | |
7733b49b | 986 | * @dev_priv: i915 device instance |
25ad93fd PZ |
987 | * |
988 | * This function reevaluates the overall state and enables or disables FBC. | |
989 | */ | |
7733b49b | 990 | void intel_fbc_update(struct drm_i915_private *dev_priv) |
25ad93fd | 991 | { |
9f218336 | 992 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
993 | return; |
994 | ||
25ad93fd | 995 | mutex_lock(&dev_priv->fbc.lock); |
7733b49b | 996 | __intel_fbc_update(dev_priv); |
25ad93fd | 997 | mutex_unlock(&dev_priv->fbc.lock); |
7ff0ebcc RV |
998 | } |
999 | ||
dbef0f15 PZ |
1000 | void intel_fbc_invalidate(struct drm_i915_private *dev_priv, |
1001 | unsigned int frontbuffer_bits, | |
1002 | enum fb_op_origin origin) | |
1003 | { | |
dbef0f15 PZ |
1004 | unsigned int fbc_bits; |
1005 | ||
9f218336 | 1006 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
1007 | return; |
1008 | ||
dbef0f15 PZ |
1009 | if (origin == ORIGIN_GTT) |
1010 | return; | |
1011 | ||
25ad93fd PZ |
1012 | mutex_lock(&dev_priv->fbc.lock); |
1013 | ||
dbef0f15 PZ |
1014 | if (dev_priv->fbc.enabled) |
1015 | fbc_bits = INTEL_FRONTBUFFER_PRIMARY(dev_priv->fbc.crtc->pipe); | |
1016 | else if (dev_priv->fbc.fbc_work) | |
1017 | fbc_bits = INTEL_FRONTBUFFER_PRIMARY( | |
220285f2 | 1018 | dev_priv->fbc.fbc_work->crtc->pipe); |
dbef0f15 PZ |
1019 | else |
1020 | fbc_bits = dev_priv->fbc.possible_framebuffer_bits; | |
1021 | ||
1022 | dev_priv->fbc.busy_bits |= (fbc_bits & frontbuffer_bits); | |
1023 | ||
1024 | if (dev_priv->fbc.busy_bits) | |
7733b49b | 1025 | __intel_fbc_disable(dev_priv); |
25ad93fd PZ |
1026 | |
1027 | mutex_unlock(&dev_priv->fbc.lock); | |
dbef0f15 PZ |
1028 | } |
1029 | ||
1030 | void intel_fbc_flush(struct drm_i915_private *dev_priv, | |
6f4551fe | 1031 | unsigned int frontbuffer_bits, enum fb_op_origin origin) |
dbef0f15 | 1032 | { |
9f218336 | 1033 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
1034 | return; |
1035 | ||
6f4551fe PZ |
1036 | if (origin == ORIGIN_GTT) |
1037 | return; | |
25ad93fd | 1038 | |
6f4551fe | 1039 | mutex_lock(&dev_priv->fbc.lock); |
dbef0f15 PZ |
1040 | |
1041 | dev_priv->fbc.busy_bits &= ~frontbuffer_bits; | |
1042 | ||
6f4551fe PZ |
1043 | if (!dev_priv->fbc.busy_bits) { |
1044 | __intel_fbc_disable(dev_priv); | |
7733b49b | 1045 | __intel_fbc_update(dev_priv); |
6f4551fe | 1046 | } |
25ad93fd | 1047 | |
25ad93fd | 1048 | mutex_unlock(&dev_priv->fbc.lock); |
dbef0f15 PZ |
1049 | } |
1050 | ||
94b83957 RV |
1051 | /** |
1052 | * intel_fbc_init - Initialize FBC | |
1053 | * @dev_priv: the i915 device | |
1054 | * | |
1055 | * This function might be called during PM init process. | |
1056 | */ | |
7ff0ebcc RV |
1057 | void intel_fbc_init(struct drm_i915_private *dev_priv) |
1058 | { | |
dbef0f15 PZ |
1059 | enum pipe pipe; |
1060 | ||
25ad93fd PZ |
1061 | mutex_init(&dev_priv->fbc.lock); |
1062 | ||
7ff0ebcc RV |
1063 | if (!HAS_FBC(dev_priv)) { |
1064 | dev_priv->fbc.enabled = false; | |
bf6189c6 | 1065 | dev_priv->fbc.no_fbc_reason = "unsupported by this chipset"; |
7ff0ebcc RV |
1066 | return; |
1067 | } | |
1068 | ||
dbef0f15 PZ |
1069 | for_each_pipe(dev_priv, pipe) { |
1070 | dev_priv->fbc.possible_framebuffer_bits |= | |
1071 | INTEL_FRONTBUFFER_PRIMARY(pipe); | |
1072 | ||
57105022 | 1073 | if (fbc_on_pipe_a_only(dev_priv)) |
dbef0f15 PZ |
1074 | break; |
1075 | } | |
1076 | ||
7ff0ebcc | 1077 | if (INTEL_INFO(dev_priv)->gen >= 7) { |
ff2a3117 PZ |
1078 | dev_priv->fbc.fbc_enabled = ilk_fbc_enabled; |
1079 | dev_priv->fbc.enable_fbc = gen7_fbc_enable; | |
1080 | dev_priv->fbc.disable_fbc = ilk_fbc_disable; | |
7ff0ebcc | 1081 | } else if (INTEL_INFO(dev_priv)->gen >= 5) { |
ff2a3117 PZ |
1082 | dev_priv->fbc.fbc_enabled = ilk_fbc_enabled; |
1083 | dev_priv->fbc.enable_fbc = ilk_fbc_enable; | |
1084 | dev_priv->fbc.disable_fbc = ilk_fbc_disable; | |
7ff0ebcc | 1085 | } else if (IS_GM45(dev_priv)) { |
ff2a3117 PZ |
1086 | dev_priv->fbc.fbc_enabled = g4x_fbc_enabled; |
1087 | dev_priv->fbc.enable_fbc = g4x_fbc_enable; | |
1088 | dev_priv->fbc.disable_fbc = g4x_fbc_disable; | |
7ff0ebcc | 1089 | } else { |
ff2a3117 PZ |
1090 | dev_priv->fbc.fbc_enabled = i8xx_fbc_enabled; |
1091 | dev_priv->fbc.enable_fbc = i8xx_fbc_enable; | |
1092 | dev_priv->fbc.disable_fbc = i8xx_fbc_disable; | |
7ff0ebcc RV |
1093 | |
1094 | /* This value was pulled out of someone's hat */ | |
1095 | I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT); | |
1096 | } | |
1097 | ||
7733b49b | 1098 | dev_priv->fbc.enabled = dev_priv->fbc.fbc_enabled(dev_priv); |
7ff0ebcc | 1099 | } |