Commit | Line | Data |
---|---|---|
7ff0ebcc RV |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
94b83957 RV |
24 | /** |
25 | * DOC: Frame Buffer Compression (FBC) | |
26 | * | |
27 | * FBC tries to save memory bandwidth (and so power consumption) by | |
28 | * compressing the amount of memory used by the display. It is total | |
29 | * transparent to user space and completely handled in the kernel. | |
7ff0ebcc RV |
30 | * |
31 | * The benefits of FBC are mostly visible with solid backgrounds and | |
94b83957 RV |
32 | * variation-less patterns. It comes from keeping the memory footprint small |
33 | * and having fewer memory pages opened and accessed for refreshing the display. | |
7ff0ebcc | 34 | * |
94b83957 RV |
35 | * i915 is responsible to reserve stolen memory for FBC and configure its |
36 | * offset on proper registers. The hardware takes care of all | |
37 | * compress/decompress. However there are many known cases where we have to | |
38 | * forcibly disable it to allow proper screen updates. | |
7ff0ebcc RV |
39 | */ |
40 | ||
94b83957 RV |
41 | #include "intel_drv.h" |
42 | #include "i915_drv.h" | |
43 | ||
9f218336 PZ |
44 | static inline bool fbc_supported(struct drm_i915_private *dev_priv) |
45 | { | |
0e631adc | 46 | return dev_priv->fbc.activate != NULL; |
9f218336 PZ |
47 | } |
48 | ||
57105022 PZ |
49 | static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv) |
50 | { | |
51 | return IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8; | |
52 | } | |
53 | ||
e6cd6dc1 PZ |
54 | static inline bool fbc_on_plane_a_only(struct drm_i915_private *dev_priv) |
55 | { | |
56 | return INTEL_INFO(dev_priv)->gen < 4; | |
57 | } | |
58 | ||
2db3366b PZ |
59 | /* |
60 | * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the | |
61 | * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's | |
62 | * origin so the x and y offsets can actually fit the registers. As a | |
63 | * consequence, the fence doesn't really start exactly at the display plane | |
64 | * address we program because it starts at the real start of the buffer, so we | |
65 | * have to take this into consideration here. | |
66 | */ | |
67 | static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc) | |
68 | { | |
69 | return crtc->base.y - crtc->adjusted_y; | |
70 | } | |
71 | ||
c5ecd469 PZ |
72 | /* |
73 | * For SKL+, the plane source size used by the hardware is based on the value we | |
74 | * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value | |
75 | * we wrote to PIPESRC. | |
76 | */ | |
aaf78d27 | 77 | static void intel_fbc_get_plane_source_size(struct intel_fbc_state_cache *cache, |
c5ecd469 PZ |
78 | int *width, int *height) |
79 | { | |
c5ecd469 PZ |
80 | int w, h; |
81 | ||
aaf78d27 PZ |
82 | if (intel_rotation_90_or_270(cache->plane.rotation)) { |
83 | w = cache->plane.src_h; | |
84 | h = cache->plane.src_w; | |
c5ecd469 | 85 | } else { |
aaf78d27 PZ |
86 | w = cache->plane.src_w; |
87 | h = cache->plane.src_h; | |
c5ecd469 PZ |
88 | } |
89 | ||
90 | if (width) | |
91 | *width = w; | |
92 | if (height) | |
93 | *height = h; | |
94 | } | |
95 | ||
aaf78d27 PZ |
96 | static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv, |
97 | struct intel_fbc_state_cache *cache) | |
c5ecd469 | 98 | { |
c5ecd469 PZ |
99 | int lines; |
100 | ||
aaf78d27 | 101 | intel_fbc_get_plane_source_size(cache, NULL, &lines); |
c5ecd469 PZ |
102 | if (INTEL_INFO(dev_priv)->gen >= 7) |
103 | lines = min(lines, 2048); | |
104 | ||
105 | /* Hardware needs the full buffer stride, not just the active area. */ | |
aaf78d27 | 106 | return lines * cache->fb.stride; |
c5ecd469 PZ |
107 | } |
108 | ||
0e631adc | 109 | static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv) |
7ff0ebcc | 110 | { |
7ff0ebcc RV |
111 | u32 fbc_ctl; |
112 | ||
0e631adc | 113 | dev_priv->fbc.active = false; |
7ff0ebcc RV |
114 | |
115 | /* Disable compression */ | |
116 | fbc_ctl = I915_READ(FBC_CONTROL); | |
117 | if ((fbc_ctl & FBC_CTL_EN) == 0) | |
118 | return; | |
119 | ||
120 | fbc_ctl &= ~FBC_CTL_EN; | |
121 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
122 | ||
123 | /* Wait for compressing bit to clear */ | |
124 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { | |
125 | DRM_DEBUG_KMS("FBC idle timed out\n"); | |
126 | return; | |
127 | } | |
7ff0ebcc RV |
128 | } |
129 | ||
b183b3f1 | 130 | static void i8xx_fbc_activate(struct drm_i915_private *dev_priv) |
7ff0ebcc | 131 | { |
b183b3f1 | 132 | struct intel_fbc_reg_params *params = &dev_priv->fbc.params; |
7ff0ebcc RV |
133 | int cfb_pitch; |
134 | int i; | |
135 | u32 fbc_ctl; | |
136 | ||
0e631adc | 137 | dev_priv->fbc.active = true; |
7ff0ebcc | 138 | |
60ee5cd2 | 139 | /* Note: fbc.threshold == 1 for i8xx */ |
b183b3f1 PZ |
140 | cfb_pitch = params->cfb_size / FBC_LL_SIZE; |
141 | if (params->fb.stride < cfb_pitch) | |
142 | cfb_pitch = params->fb.stride; | |
7ff0ebcc RV |
143 | |
144 | /* FBC_CTL wants 32B or 64B units */ | |
7733b49b | 145 | if (IS_GEN2(dev_priv)) |
7ff0ebcc RV |
146 | cfb_pitch = (cfb_pitch / 32) - 1; |
147 | else | |
148 | cfb_pitch = (cfb_pitch / 64) - 1; | |
149 | ||
150 | /* Clear old tags */ | |
151 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) | |
4d110c71 | 152 | I915_WRITE(FBC_TAG(i), 0); |
7ff0ebcc | 153 | |
7733b49b | 154 | if (IS_GEN4(dev_priv)) { |
7ff0ebcc RV |
155 | u32 fbc_ctl2; |
156 | ||
157 | /* Set it up... */ | |
158 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; | |
b183b3f1 | 159 | fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.plane); |
7ff0ebcc | 160 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
b183b3f1 | 161 | I915_WRITE(FBC_FENCE_OFF, params->crtc.fence_y_offset); |
7ff0ebcc RV |
162 | } |
163 | ||
164 | /* enable it... */ | |
165 | fbc_ctl = I915_READ(FBC_CONTROL); | |
166 | fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT; | |
167 | fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC; | |
7733b49b | 168 | if (IS_I945GM(dev_priv)) |
7ff0ebcc RV |
169 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
170 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; | |
b183b3f1 | 171 | fbc_ctl |= params->fb.fence_reg; |
7ff0ebcc | 172 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
7ff0ebcc RV |
173 | } |
174 | ||
0e631adc | 175 | static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv) |
7ff0ebcc | 176 | { |
7ff0ebcc RV |
177 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; |
178 | } | |
179 | ||
b183b3f1 | 180 | static void g4x_fbc_activate(struct drm_i915_private *dev_priv) |
7ff0ebcc | 181 | { |
b183b3f1 | 182 | struct intel_fbc_reg_params *params = &dev_priv->fbc.params; |
7ff0ebcc RV |
183 | u32 dpfc_ctl; |
184 | ||
0e631adc | 185 | dev_priv->fbc.active = true; |
7ff0ebcc | 186 | |
b183b3f1 PZ |
187 | dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane) | DPFC_SR_EN; |
188 | if (drm_format_plane_cpp(params->fb.pixel_format, 0) == 2) | |
7ff0ebcc RV |
189 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; |
190 | else | |
191 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
b183b3f1 | 192 | dpfc_ctl |= DPFC_CTL_FENCE_EN | params->fb.fence_reg; |
7ff0ebcc | 193 | |
b183b3f1 | 194 | I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset); |
7ff0ebcc RV |
195 | |
196 | /* enable it... */ | |
197 | I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
7ff0ebcc RV |
198 | } |
199 | ||
0e631adc | 200 | static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv) |
7ff0ebcc | 201 | { |
7ff0ebcc RV |
202 | u32 dpfc_ctl; |
203 | ||
0e631adc | 204 | dev_priv->fbc.active = false; |
7ff0ebcc RV |
205 | |
206 | /* Disable compression */ | |
207 | dpfc_ctl = I915_READ(DPFC_CONTROL); | |
208 | if (dpfc_ctl & DPFC_CTL_EN) { | |
209 | dpfc_ctl &= ~DPFC_CTL_EN; | |
210 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); | |
7ff0ebcc RV |
211 | } |
212 | } | |
213 | ||
0e631adc | 214 | static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv) |
7ff0ebcc | 215 | { |
7ff0ebcc RV |
216 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; |
217 | } | |
218 | ||
d5ce4164 PZ |
219 | /* This function forces a CFB recompression through the nuke operation. */ |
220 | static void intel_fbc_recompress(struct drm_i915_private *dev_priv) | |
7ff0ebcc | 221 | { |
dbef0f15 PZ |
222 | I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE); |
223 | POSTING_READ(MSG_FBC_REND_STATE); | |
7ff0ebcc RV |
224 | } |
225 | ||
b183b3f1 | 226 | static void ilk_fbc_activate(struct drm_i915_private *dev_priv) |
7ff0ebcc | 227 | { |
b183b3f1 | 228 | struct intel_fbc_reg_params *params = &dev_priv->fbc.params; |
7ff0ebcc | 229 | u32 dpfc_ctl; |
ce65e47b | 230 | int threshold = dev_priv->fbc.threshold; |
7ff0ebcc | 231 | |
0e631adc | 232 | dev_priv->fbc.active = true; |
7ff0ebcc | 233 | |
b183b3f1 PZ |
234 | dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane); |
235 | if (drm_format_plane_cpp(params->fb.pixel_format, 0) == 2) | |
ce65e47b | 236 | threshold++; |
7ff0ebcc | 237 | |
ce65e47b | 238 | switch (threshold) { |
7ff0ebcc RV |
239 | case 4: |
240 | case 3: | |
241 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; | |
242 | break; | |
243 | case 2: | |
244 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
245 | break; | |
246 | case 1: | |
247 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
248 | break; | |
249 | } | |
250 | dpfc_ctl |= DPFC_CTL_FENCE_EN; | |
7733b49b | 251 | if (IS_GEN5(dev_priv)) |
b183b3f1 | 252 | dpfc_ctl |= params->fb.fence_reg; |
7ff0ebcc | 253 | |
b183b3f1 PZ |
254 | I915_WRITE(ILK_DPFC_FENCE_YOFF, params->crtc.fence_y_offset); |
255 | I915_WRITE(ILK_FBC_RT_BASE, params->fb.ggtt_offset | ILK_FBC_RT_VALID); | |
7ff0ebcc RV |
256 | /* enable it... */ |
257 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
258 | ||
7733b49b | 259 | if (IS_GEN6(dev_priv)) { |
7ff0ebcc | 260 | I915_WRITE(SNB_DPFC_CTL_SA, |
b183b3f1 PZ |
261 | SNB_CPU_FENCE_ENABLE | params->fb.fence_reg); |
262 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset); | |
7ff0ebcc RV |
263 | } |
264 | ||
d5ce4164 | 265 | intel_fbc_recompress(dev_priv); |
7ff0ebcc RV |
266 | } |
267 | ||
0e631adc | 268 | static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv) |
7ff0ebcc | 269 | { |
7ff0ebcc RV |
270 | u32 dpfc_ctl; |
271 | ||
0e631adc | 272 | dev_priv->fbc.active = false; |
7ff0ebcc RV |
273 | |
274 | /* Disable compression */ | |
275 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
276 | if (dpfc_ctl & DPFC_CTL_EN) { | |
277 | dpfc_ctl &= ~DPFC_CTL_EN; | |
278 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); | |
7ff0ebcc RV |
279 | } |
280 | } | |
281 | ||
0e631adc | 282 | static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv) |
7ff0ebcc | 283 | { |
7ff0ebcc RV |
284 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; |
285 | } | |
286 | ||
b183b3f1 | 287 | static void gen7_fbc_activate(struct drm_i915_private *dev_priv) |
7ff0ebcc | 288 | { |
b183b3f1 | 289 | struct intel_fbc_reg_params *params = &dev_priv->fbc.params; |
7ff0ebcc | 290 | u32 dpfc_ctl; |
ce65e47b | 291 | int threshold = dev_priv->fbc.threshold; |
7ff0ebcc | 292 | |
0e631adc | 293 | dev_priv->fbc.active = true; |
7ff0ebcc | 294 | |
d8514d63 | 295 | dpfc_ctl = 0; |
7733b49b | 296 | if (IS_IVYBRIDGE(dev_priv)) |
b183b3f1 | 297 | dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane); |
d8514d63 | 298 | |
b183b3f1 | 299 | if (drm_format_plane_cpp(params->fb.pixel_format, 0) == 2) |
ce65e47b | 300 | threshold++; |
7ff0ebcc | 301 | |
ce65e47b | 302 | switch (threshold) { |
7ff0ebcc RV |
303 | case 4: |
304 | case 3: | |
305 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; | |
306 | break; | |
307 | case 2: | |
308 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
309 | break; | |
310 | case 1: | |
311 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
312 | break; | |
313 | } | |
314 | ||
315 | dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; | |
316 | ||
317 | if (dev_priv->fbc.false_color) | |
318 | dpfc_ctl |= FBC_CTL_FALSE_COLOR; | |
319 | ||
7733b49b | 320 | if (IS_IVYBRIDGE(dev_priv)) { |
7ff0ebcc RV |
321 | /* WaFbcAsynchFlipDisableFbcQueue:ivb */ |
322 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
323 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
324 | ILK_FBCQ_DIS); | |
40f4022e | 325 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
7ff0ebcc | 326 | /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ |
b183b3f1 PZ |
327 | I915_WRITE(CHICKEN_PIPESL_1(params->crtc.pipe), |
328 | I915_READ(CHICKEN_PIPESL_1(params->crtc.pipe)) | | |
7ff0ebcc RV |
329 | HSW_FBCQ_DIS); |
330 | } | |
331 | ||
57012be9 PZ |
332 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
333 | ||
7ff0ebcc | 334 | I915_WRITE(SNB_DPFC_CTL_SA, |
b183b3f1 PZ |
335 | SNB_CPU_FENCE_ENABLE | params->fb.fence_reg); |
336 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset); | |
7ff0ebcc | 337 | |
d5ce4164 | 338 | intel_fbc_recompress(dev_priv); |
7ff0ebcc RV |
339 | } |
340 | ||
94b83957 | 341 | /** |
0e631adc | 342 | * intel_fbc_is_active - Is FBC active? |
7733b49b | 343 | * @dev_priv: i915 device instance |
94b83957 RV |
344 | * |
345 | * This function is used to verify the current state of FBC. | |
346 | * FIXME: This should be tracked in the plane config eventually | |
347 | * instead of queried at runtime for most callers. | |
348 | */ | |
0e631adc | 349 | bool intel_fbc_is_active(struct drm_i915_private *dev_priv) |
7ff0ebcc | 350 | { |
0e631adc | 351 | return dev_priv->fbc.active; |
7ff0ebcc RV |
352 | } |
353 | ||
7ff0ebcc RV |
354 | static void intel_fbc_work_fn(struct work_struct *__work) |
355 | { | |
128d7356 PZ |
356 | struct drm_i915_private *dev_priv = |
357 | container_of(__work, struct drm_i915_private, fbc.work.work); | |
ab34a7e8 PZ |
358 | struct intel_fbc *fbc = &dev_priv->fbc; |
359 | struct intel_fbc_work *work = &fbc->work; | |
360 | struct intel_crtc *crtc = fbc->crtc; | |
ca18d51d PZ |
361 | struct drm_vblank_crtc *vblank = &dev_priv->dev->vblank[crtc->pipe]; |
362 | ||
363 | if (drm_crtc_vblank_get(&crtc->base)) { | |
364 | DRM_ERROR("vblank not available for FBC on pipe %c\n", | |
365 | pipe_name(crtc->pipe)); | |
366 | ||
ab34a7e8 | 367 | mutex_lock(&fbc->lock); |
ca18d51d | 368 | work->scheduled = false; |
ab34a7e8 | 369 | mutex_unlock(&fbc->lock); |
ca18d51d PZ |
370 | return; |
371 | } | |
128d7356 PZ |
372 | |
373 | retry: | |
374 | /* Delay the actual enabling to let pageflipping cease and the | |
375 | * display to settle before starting the compression. Note that | |
376 | * this delay also serves a second purpose: it allows for a | |
377 | * vblank to pass after disabling the FBC before we attempt | |
378 | * to modify the control registers. | |
379 | * | |
128d7356 | 380 | * WaFbcWaitForVBlankBeforeEnable:ilk,snb |
ca18d51d PZ |
381 | * |
382 | * It is also worth mentioning that since work->scheduled_vblank can be | |
383 | * updated multiple times by the other threads, hitting the timeout is | |
384 | * not an error condition. We'll just end up hitting the "goto retry" | |
385 | * case below. | |
128d7356 | 386 | */ |
ca18d51d PZ |
387 | wait_event_timeout(vblank->queue, |
388 | drm_crtc_vblank_count(&crtc->base) != work->scheduled_vblank, | |
389 | msecs_to_jiffies(50)); | |
7ff0ebcc | 390 | |
ab34a7e8 | 391 | mutex_lock(&fbc->lock); |
7ff0ebcc | 392 | |
128d7356 PZ |
393 | /* Were we cancelled? */ |
394 | if (!work->scheduled) | |
395 | goto out; | |
396 | ||
397 | /* Were we delayed again while this function was sleeping? */ | |
ca18d51d | 398 | if (drm_crtc_vblank_count(&crtc->base) == work->scheduled_vblank) { |
ab34a7e8 | 399 | mutex_unlock(&fbc->lock); |
128d7356 | 400 | goto retry; |
7ff0ebcc | 401 | } |
7ff0ebcc | 402 | |
128d7356 | 403 | if (crtc->base.primary->fb == work->fb) |
ab34a7e8 | 404 | fbc->activate(dev_priv); |
128d7356 PZ |
405 | |
406 | work->scheduled = false; | |
407 | ||
408 | out: | |
ab34a7e8 | 409 | mutex_unlock(&fbc->lock); |
ca18d51d | 410 | drm_crtc_vblank_put(&crtc->base); |
7ff0ebcc RV |
411 | } |
412 | ||
413 | static void intel_fbc_cancel_work(struct drm_i915_private *dev_priv) | |
414 | { | |
ab34a7e8 PZ |
415 | struct intel_fbc *fbc = &dev_priv->fbc; |
416 | ||
417 | WARN_ON(!mutex_is_locked(&fbc->lock)); | |
418 | fbc->work.scheduled = false; | |
7ff0ebcc RV |
419 | } |
420 | ||
0e631adc | 421 | static void intel_fbc_schedule_activation(struct intel_crtc *crtc) |
7ff0ebcc | 422 | { |
220285f2 | 423 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
ab34a7e8 PZ |
424 | struct intel_fbc *fbc = &dev_priv->fbc; |
425 | struct intel_fbc_work *work = &fbc->work; | |
7ff0ebcc | 426 | |
ab34a7e8 | 427 | WARN_ON(!mutex_is_locked(&fbc->lock)); |
25ad93fd | 428 | |
ca18d51d PZ |
429 | if (drm_crtc_vblank_get(&crtc->base)) { |
430 | DRM_ERROR("vblank not available for FBC on pipe %c\n", | |
431 | pipe_name(crtc->pipe)); | |
432 | return; | |
433 | } | |
434 | ||
128d7356 PZ |
435 | /* It is useless to call intel_fbc_cancel_work() in this function since |
436 | * we're not releasing fbc.lock, so it won't have an opportunity to grab | |
437 | * it to discover that it was cancelled. So we just update the expected | |
438 | * jiffy count. */ | |
220285f2 | 439 | work->fb = crtc->base.primary->fb; |
128d7356 | 440 | work->scheduled = true; |
ca18d51d PZ |
441 | work->scheduled_vblank = drm_crtc_vblank_count(&crtc->base); |
442 | drm_crtc_vblank_put(&crtc->base); | |
7ff0ebcc | 443 | |
128d7356 | 444 | schedule_work(&work->work); |
7ff0ebcc RV |
445 | } |
446 | ||
d029bcad | 447 | static void __intel_fbc_deactivate(struct drm_i915_private *dev_priv) |
25ad93fd | 448 | { |
ab34a7e8 PZ |
449 | struct intel_fbc *fbc = &dev_priv->fbc; |
450 | ||
451 | WARN_ON(!mutex_is_locked(&fbc->lock)); | |
25ad93fd PZ |
452 | |
453 | intel_fbc_cancel_work(dev_priv); | |
454 | ||
ab34a7e8 PZ |
455 | if (fbc->active) |
456 | fbc->deactivate(dev_priv); | |
754d1133 PZ |
457 | } |
458 | ||
25ad93fd | 459 | /* |
d029bcad | 460 | * intel_fbc_deactivate - deactivate FBC if it's associated with crtc |
25ad93fd PZ |
461 | * @crtc: the CRTC |
462 | * | |
d029bcad | 463 | * This function deactivates FBC if it's associated with the provided CRTC. |
25ad93fd | 464 | */ |
d029bcad | 465 | void intel_fbc_deactivate(struct intel_crtc *crtc) |
25ad93fd | 466 | { |
7733b49b | 467 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
ab34a7e8 | 468 | struct intel_fbc *fbc = &dev_priv->fbc; |
7ff0ebcc | 469 | |
9f218336 | 470 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
471 | return; |
472 | ||
ab34a7e8 PZ |
473 | mutex_lock(&fbc->lock); |
474 | if (fbc->crtc == crtc) | |
d029bcad | 475 | __intel_fbc_deactivate(dev_priv); |
ab34a7e8 | 476 | mutex_unlock(&fbc->lock); |
7ff0ebcc RV |
477 | } |
478 | ||
2e8144a5 | 479 | static void set_no_fbc_reason(struct drm_i915_private *dev_priv, |
bf6189c6 | 480 | const char *reason) |
7ff0ebcc | 481 | { |
ab34a7e8 PZ |
482 | struct intel_fbc *fbc = &dev_priv->fbc; |
483 | ||
484 | if (fbc->no_fbc_reason == reason) | |
2e8144a5 | 485 | return; |
7ff0ebcc | 486 | |
ab34a7e8 | 487 | fbc->no_fbc_reason = reason; |
bf6189c6 | 488 | DRM_DEBUG_KMS("Disabling FBC: %s\n", reason); |
7ff0ebcc RV |
489 | } |
490 | ||
d029bcad | 491 | static bool crtc_can_fbc(struct intel_crtc *crtc) |
30c58d58 PZ |
492 | { |
493 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
494 | ||
495 | if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A) | |
496 | return false; | |
497 | ||
e6cd6dc1 PZ |
498 | if (fbc_on_plane_a_only(dev_priv) && crtc->plane != PLANE_A) |
499 | return false; | |
500 | ||
d029bcad PZ |
501 | return true; |
502 | } | |
503 | ||
232fd934 PZ |
504 | static bool multiple_pipes_ok(struct drm_i915_private *dev_priv) |
505 | { | |
506 | enum pipe pipe; | |
507 | int n_pipes = 0; | |
508 | struct drm_crtc *crtc; | |
509 | ||
510 | if (INTEL_INFO(dev_priv)->gen > 4) | |
511 | return true; | |
512 | ||
513 | for_each_pipe(dev_priv, pipe) { | |
514 | crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
515 | ||
516 | if (intel_crtc_active(crtc) && | |
517 | to_intel_plane_state(crtc->primary->state)->visible) | |
518 | n_pipes++; | |
519 | } | |
520 | ||
521 | return (n_pipes < 2); | |
522 | } | |
523 | ||
7733b49b | 524 | static int find_compression_threshold(struct drm_i915_private *dev_priv, |
fc786728 PZ |
525 | struct drm_mm_node *node, |
526 | int size, | |
527 | int fb_cpp) | |
528 | { | |
fc786728 PZ |
529 | int compression_threshold = 1; |
530 | int ret; | |
a9da512b PZ |
531 | u64 end; |
532 | ||
533 | /* The FBC hardware for BDW/SKL doesn't have access to the stolen | |
534 | * reserved range size, so it always assumes the maximum (8mb) is used. | |
535 | * If we enable FBC using a CFB on that memory range we'll get FIFO | |
536 | * underruns, even if that range is not reserved by the BIOS. */ | |
ef11bdb3 RV |
537 | if (IS_BROADWELL(dev_priv) || |
538 | IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) | |
a9da512b PZ |
539 | end = dev_priv->gtt.stolen_size - 8 * 1024 * 1024; |
540 | else | |
541 | end = dev_priv->gtt.stolen_usable_size; | |
fc786728 PZ |
542 | |
543 | /* HACK: This code depends on what we will do in *_enable_fbc. If that | |
544 | * code changes, this code needs to change as well. | |
545 | * | |
546 | * The enable_fbc code will attempt to use one of our 2 compression | |
547 | * thresholds, therefore, in that case, we only have 1 resort. | |
548 | */ | |
549 | ||
550 | /* Try to over-allocate to reduce reallocations and fragmentation. */ | |
a9da512b PZ |
551 | ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1, |
552 | 4096, 0, end); | |
fc786728 PZ |
553 | if (ret == 0) |
554 | return compression_threshold; | |
555 | ||
556 | again: | |
557 | /* HW's ability to limit the CFB is 1:4 */ | |
558 | if (compression_threshold > 4 || | |
559 | (fb_cpp == 2 && compression_threshold == 2)) | |
560 | return 0; | |
561 | ||
a9da512b PZ |
562 | ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1, |
563 | 4096, 0, end); | |
7733b49b | 564 | if (ret && INTEL_INFO(dev_priv)->gen <= 4) { |
fc786728 PZ |
565 | return 0; |
566 | } else if (ret) { | |
567 | compression_threshold <<= 1; | |
568 | goto again; | |
569 | } else { | |
570 | return compression_threshold; | |
571 | } | |
572 | } | |
573 | ||
c5ecd469 | 574 | static int intel_fbc_alloc_cfb(struct intel_crtc *crtc) |
fc786728 | 575 | { |
c5ecd469 | 576 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
ab34a7e8 | 577 | struct intel_fbc *fbc = &dev_priv->fbc; |
fc786728 | 578 | struct drm_mm_node *uninitialized_var(compressed_llb); |
c5ecd469 PZ |
579 | int size, fb_cpp, ret; |
580 | ||
ab34a7e8 | 581 | WARN_ON(drm_mm_node_allocated(&fbc->compressed_fb)); |
c5ecd469 | 582 | |
aaf78d27 PZ |
583 | size = intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache); |
584 | fb_cpp = drm_format_plane_cpp(fbc->state_cache.fb.pixel_format, 0); | |
fc786728 | 585 | |
ab34a7e8 | 586 | ret = find_compression_threshold(dev_priv, &fbc->compressed_fb, |
fc786728 PZ |
587 | size, fb_cpp); |
588 | if (!ret) | |
589 | goto err_llb; | |
590 | else if (ret > 1) { | |
591 | DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n"); | |
592 | ||
593 | } | |
594 | ||
ab34a7e8 | 595 | fbc->threshold = ret; |
fc786728 PZ |
596 | |
597 | if (INTEL_INFO(dev_priv)->gen >= 5) | |
ab34a7e8 | 598 | I915_WRITE(ILK_DPFC_CB_BASE, fbc->compressed_fb.start); |
7733b49b | 599 | else if (IS_GM45(dev_priv)) { |
ab34a7e8 | 600 | I915_WRITE(DPFC_CB_BASE, fbc->compressed_fb.start); |
fc786728 PZ |
601 | } else { |
602 | compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL); | |
603 | if (!compressed_llb) | |
604 | goto err_fb; | |
605 | ||
606 | ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb, | |
607 | 4096, 4096); | |
608 | if (ret) | |
609 | goto err_fb; | |
610 | ||
ab34a7e8 | 611 | fbc->compressed_llb = compressed_llb; |
fc786728 PZ |
612 | |
613 | I915_WRITE(FBC_CFB_BASE, | |
ab34a7e8 | 614 | dev_priv->mm.stolen_base + fbc->compressed_fb.start); |
fc786728 PZ |
615 | I915_WRITE(FBC_LL_BASE, |
616 | dev_priv->mm.stolen_base + compressed_llb->start); | |
617 | } | |
618 | ||
b8bf5d7f | 619 | DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n", |
ab34a7e8 | 620 | fbc->compressed_fb.size, fbc->threshold); |
fc786728 PZ |
621 | |
622 | return 0; | |
623 | ||
624 | err_fb: | |
625 | kfree(compressed_llb); | |
ab34a7e8 | 626 | i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb); |
fc786728 PZ |
627 | err_llb: |
628 | pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size); | |
629 | return -ENOSPC; | |
630 | } | |
631 | ||
7733b49b | 632 | static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) |
fc786728 | 633 | { |
ab34a7e8 PZ |
634 | struct intel_fbc *fbc = &dev_priv->fbc; |
635 | ||
636 | if (drm_mm_node_allocated(&fbc->compressed_fb)) | |
637 | i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb); | |
638 | ||
639 | if (fbc->compressed_llb) { | |
640 | i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb); | |
641 | kfree(fbc->compressed_llb); | |
fc786728 | 642 | } |
fc786728 PZ |
643 | } |
644 | ||
7733b49b | 645 | void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) |
25ad93fd | 646 | { |
ab34a7e8 PZ |
647 | struct intel_fbc *fbc = &dev_priv->fbc; |
648 | ||
9f218336 | 649 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
650 | return; |
651 | ||
ab34a7e8 | 652 | mutex_lock(&fbc->lock); |
7733b49b | 653 | __intel_fbc_cleanup_cfb(dev_priv); |
ab34a7e8 | 654 | mutex_unlock(&fbc->lock); |
25ad93fd PZ |
655 | } |
656 | ||
adf70c65 PZ |
657 | static bool stride_is_valid(struct drm_i915_private *dev_priv, |
658 | unsigned int stride) | |
659 | { | |
660 | /* These should have been caught earlier. */ | |
661 | WARN_ON(stride < 512); | |
662 | WARN_ON((stride & (64 - 1)) != 0); | |
663 | ||
664 | /* Below are the additional FBC restrictions. */ | |
665 | ||
666 | if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv)) | |
667 | return stride == 4096 || stride == 8192; | |
668 | ||
669 | if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048) | |
670 | return false; | |
671 | ||
672 | if (stride > 16384) | |
673 | return false; | |
674 | ||
675 | return true; | |
676 | } | |
677 | ||
aaf78d27 PZ |
678 | static bool pixel_format_is_valid(struct drm_i915_private *dev_priv, |
679 | uint32_t pixel_format) | |
b9e831dc | 680 | { |
aaf78d27 | 681 | switch (pixel_format) { |
b9e831dc PZ |
682 | case DRM_FORMAT_XRGB8888: |
683 | case DRM_FORMAT_XBGR8888: | |
684 | return true; | |
685 | case DRM_FORMAT_XRGB1555: | |
686 | case DRM_FORMAT_RGB565: | |
687 | /* 16bpp not supported on gen2 */ | |
aaf78d27 | 688 | if (IS_GEN2(dev_priv)) |
b9e831dc PZ |
689 | return false; |
690 | /* WaFbcOnly1to1Ratio:ctg */ | |
691 | if (IS_G4X(dev_priv)) | |
692 | return false; | |
693 | return true; | |
694 | default: | |
695 | return false; | |
696 | } | |
697 | } | |
698 | ||
856312ae PZ |
699 | /* |
700 | * For some reason, the hardware tracking starts looking at whatever we | |
701 | * programmed as the display plane base address register. It does not look at | |
702 | * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y} | |
703 | * variables instead of just looking at the pipe/plane size. | |
704 | */ | |
705 | static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc) | |
3c5f174e PZ |
706 | { |
707 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
aaf78d27 | 708 | struct intel_fbc *fbc = &dev_priv->fbc; |
856312ae | 709 | unsigned int effective_w, effective_h, max_w, max_h; |
3c5f174e PZ |
710 | |
711 | if (INTEL_INFO(dev_priv)->gen >= 8 || IS_HASWELL(dev_priv)) { | |
712 | max_w = 4096; | |
713 | max_h = 4096; | |
714 | } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { | |
715 | max_w = 4096; | |
716 | max_h = 2048; | |
717 | } else { | |
718 | max_w = 2048; | |
719 | max_h = 1536; | |
720 | } | |
721 | ||
aaf78d27 PZ |
722 | intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w, |
723 | &effective_h); | |
856312ae PZ |
724 | effective_w += crtc->adjusted_x; |
725 | effective_h += crtc->adjusted_y; | |
726 | ||
727 | return effective_w <= max_w && effective_h <= max_h; | |
3c5f174e PZ |
728 | } |
729 | ||
aaf78d27 | 730 | static void intel_fbc_update_state_cache(struct intel_crtc *crtc) |
7ff0ebcc | 731 | { |
754d1133 | 732 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
ab34a7e8 | 733 | struct intel_fbc *fbc = &dev_priv->fbc; |
aaf78d27 PZ |
734 | struct intel_fbc_state_cache *cache = &fbc->state_cache; |
735 | struct intel_crtc_state *crtc_state = crtc->config; | |
736 | struct intel_plane_state *plane_state = | |
737 | to_intel_plane_state(crtc->base.primary->state); | |
738 | struct drm_framebuffer *fb = plane_state->base.fb; | |
7ff0ebcc | 739 | struct drm_i915_gem_object *obj; |
7ff0ebcc | 740 | |
aaf78d27 PZ |
741 | cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags; |
742 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
743 | cache->crtc.hsw_bdw_pixel_rate = | |
744 | ilk_pipe_pixel_rate(crtc_state); | |
745 | ||
746 | cache->plane.rotation = plane_state->base.rotation; | |
747 | cache->plane.src_w = drm_rect_width(&plane_state->src) >> 16; | |
748 | cache->plane.src_h = drm_rect_height(&plane_state->src) >> 16; | |
749 | cache->plane.visible = plane_state->visible; | |
750 | ||
751 | if (!cache->plane.visible) | |
752 | return; | |
7ff0ebcc | 753 | |
7ff0ebcc | 754 | obj = intel_fb_obj(fb); |
615b40d7 | 755 | |
aaf78d27 PZ |
756 | /* FIXME: We lack the proper locking here, so only run this on the |
757 | * platforms that need. */ | |
758 | if (dev_priv->fbc.activate == ilk_fbc_activate) | |
759 | cache->fb.ilk_ggtt_offset = i915_gem_obj_ggtt_offset(obj); | |
760 | cache->fb.id = fb->base.id; | |
761 | cache->fb.pixel_format = fb->pixel_format; | |
762 | cache->fb.stride = fb->pitches[0]; | |
763 | cache->fb.fence_reg = obj->fence_reg; | |
764 | cache->fb.tiling_mode = obj->tiling_mode; | |
765 | } | |
766 | ||
767 | static bool intel_fbc_can_activate(struct intel_crtc *crtc) | |
768 | { | |
769 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
770 | struct intel_fbc *fbc = &dev_priv->fbc; | |
771 | struct intel_fbc_state_cache *cache = &fbc->state_cache; | |
772 | ||
773 | if (!cache->plane.visible) { | |
615b40d7 PZ |
774 | set_no_fbc_reason(dev_priv, "primary plane not visible"); |
775 | return false; | |
776 | } | |
7ff0ebcc | 777 | |
aaf78d27 PZ |
778 | if ((cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) || |
779 | (cache->crtc.mode_flags & DRM_MODE_FLAG_DBLSCAN)) { | |
bf6189c6 | 780 | set_no_fbc_reason(dev_priv, "incompatible mode"); |
615b40d7 | 781 | return false; |
7ff0ebcc RV |
782 | } |
783 | ||
45b32a29 | 784 | if (!intel_fbc_hw_tracking_covers_screen(crtc)) { |
bf6189c6 | 785 | set_no_fbc_reason(dev_priv, "mode too large for compression"); |
615b40d7 | 786 | return false; |
7ff0ebcc | 787 | } |
3c5f174e | 788 | |
7ff0ebcc RV |
789 | /* The use of a CPU fence is mandatory in order to detect writes |
790 | * by the CPU to the scanout and trigger updates to the FBC. | |
791 | */ | |
aaf78d27 PZ |
792 | if (cache->fb.tiling_mode != I915_TILING_X || |
793 | cache->fb.fence_reg == I915_FENCE_REG_NONE) { | |
bf6189c6 | 794 | set_no_fbc_reason(dev_priv, "framebuffer not tiled or fenced"); |
615b40d7 | 795 | return false; |
7ff0ebcc | 796 | } |
7733b49b | 797 | if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) && |
aaf78d27 | 798 | cache->plane.rotation != BIT(DRM_ROTATE_0)) { |
bf6189c6 | 799 | set_no_fbc_reason(dev_priv, "rotation unsupported"); |
615b40d7 | 800 | return false; |
7ff0ebcc RV |
801 | } |
802 | ||
aaf78d27 | 803 | if (!stride_is_valid(dev_priv, cache->fb.stride)) { |
bf6189c6 | 804 | set_no_fbc_reason(dev_priv, "framebuffer stride not supported"); |
615b40d7 | 805 | return false; |
adf70c65 PZ |
806 | } |
807 | ||
aaf78d27 | 808 | if (!pixel_format_is_valid(dev_priv, cache->fb.pixel_format)) { |
bf6189c6 | 809 | set_no_fbc_reason(dev_priv, "pixel format is invalid"); |
615b40d7 | 810 | return false; |
b9e831dc PZ |
811 | } |
812 | ||
7b24c9a6 PZ |
813 | /* WaFbcExceedCdClockThreshold:hsw,bdw */ |
814 | if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) && | |
aaf78d27 | 815 | cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk_freq * 95 / 100) { |
bf6189c6 | 816 | set_no_fbc_reason(dev_priv, "pixel rate is too big"); |
615b40d7 | 817 | return false; |
7b24c9a6 PZ |
818 | } |
819 | ||
c5ecd469 PZ |
820 | /* It is possible for the required CFB size change without a |
821 | * crtc->disable + crtc->enable since it is possible to change the | |
822 | * stride without triggering a full modeset. Since we try to | |
823 | * over-allocate the CFB, there's a chance we may keep FBC enabled even | |
824 | * if this happens, but if we exceed the current CFB size we'll have to | |
825 | * disable FBC. Notice that it would be possible to disable FBC, wait | |
826 | * for a frame, free the stolen node, then try to reenable FBC in case | |
827 | * we didn't get any invalidate/deactivate calls, but this would require | |
828 | * a lot of tracking just for a specific case. If we conclude it's an | |
829 | * important case, we can implement it later. */ | |
aaf78d27 | 830 | if (intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) > |
ab34a7e8 | 831 | fbc->compressed_fb.size * fbc->threshold) { |
c5ecd469 | 832 | set_no_fbc_reason(dev_priv, "CFB requirements changed"); |
615b40d7 PZ |
833 | return false; |
834 | } | |
835 | ||
836 | return true; | |
837 | } | |
838 | ||
44a8a257 PZ |
839 | static bool intel_fbc_can_enable(struct intel_crtc *crtc) |
840 | { | |
841 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
842 | ||
843 | if (intel_vgpu_active(dev_priv->dev)) { | |
844 | set_no_fbc_reason(dev_priv, "VGPU is active"); | |
845 | return false; | |
846 | } | |
847 | ||
848 | if (i915.enable_fbc < 0) { | |
849 | set_no_fbc_reason(dev_priv, "disabled per chip default"); | |
850 | return false; | |
851 | } | |
852 | ||
853 | if (!i915.enable_fbc) { | |
854 | set_no_fbc_reason(dev_priv, "disabled per module param"); | |
855 | return false; | |
856 | } | |
857 | ||
858 | if (!crtc_can_fbc(crtc)) { | |
859 | set_no_fbc_reason(dev_priv, "no enabled pipes can have FBC"); | |
860 | return false; | |
861 | } | |
862 | ||
863 | return true; | |
864 | } | |
865 | ||
b183b3f1 PZ |
866 | static void intel_fbc_get_reg_params(struct intel_crtc *crtc, |
867 | struct intel_fbc_reg_params *params) | |
868 | { | |
869 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
aaf78d27 PZ |
870 | struct intel_fbc *fbc = &dev_priv->fbc; |
871 | struct intel_fbc_state_cache *cache = &fbc->state_cache; | |
b183b3f1 PZ |
872 | |
873 | /* Since all our fields are integer types, use memset here so the | |
874 | * comparison function can rely on memcmp because the padding will be | |
875 | * zero. */ | |
876 | memset(params, 0, sizeof(*params)); | |
877 | ||
878 | params->crtc.pipe = crtc->pipe; | |
879 | params->crtc.plane = crtc->plane; | |
880 | params->crtc.fence_y_offset = get_crtc_fence_y_offset(crtc); | |
881 | ||
aaf78d27 PZ |
882 | params->fb.id = cache->fb.id; |
883 | params->fb.pixel_format = cache->fb.pixel_format; | |
884 | params->fb.stride = cache->fb.stride; | |
885 | params->fb.fence_reg = cache->fb.fence_reg; | |
b183b3f1 | 886 | |
aaf78d27 | 887 | params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache); |
b183b3f1 | 888 | |
aaf78d27 | 889 | params->fb.ggtt_offset = cache->fb.ilk_ggtt_offset; |
b183b3f1 PZ |
890 | } |
891 | ||
892 | static bool intel_fbc_reg_params_equal(struct intel_fbc_reg_params *params1, | |
893 | struct intel_fbc_reg_params *params2) | |
894 | { | |
895 | /* We can use this since intel_fbc_get_reg_params() does a memset. */ | |
896 | return memcmp(params1, params2, sizeof(*params1)) == 0; | |
897 | } | |
898 | ||
212890cf | 899 | static void intel_fbc_pre_update(struct intel_crtc *crtc) |
615b40d7 PZ |
900 | { |
901 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
ab34a7e8 | 902 | struct intel_fbc *fbc = &dev_priv->fbc; |
615b40d7 | 903 | |
ab34a7e8 | 904 | WARN_ON(!mutex_is_locked(&fbc->lock)); |
615b40d7 PZ |
905 | |
906 | if (!multiple_pipes_ok(dev_priv)) { | |
907 | set_no_fbc_reason(dev_priv, "more than one pipe active"); | |
212890cf | 908 | goto deactivate; |
7ff0ebcc RV |
909 | } |
910 | ||
ab34a7e8 | 911 | if (!fbc->enabled || fbc->crtc != crtc) |
615b40d7 PZ |
912 | return; |
913 | ||
aaf78d27 PZ |
914 | intel_fbc_update_state_cache(crtc); |
915 | ||
212890cf PZ |
916 | deactivate: |
917 | __intel_fbc_deactivate(dev_priv); | |
918 | } | |
919 | ||
920 | static void intel_fbc_post_update(struct intel_crtc *crtc) | |
921 | { | |
922 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
923 | struct intel_fbc *fbc = &dev_priv->fbc; | |
924 | struct intel_fbc_reg_params old_params; | |
925 | ||
926 | WARN_ON(!mutex_is_locked(&fbc->lock)); | |
927 | ||
928 | if (!fbc->enabled || fbc->crtc != crtc) | |
929 | return; | |
930 | ||
931 | if (!intel_fbc_can_activate(crtc)) { | |
932 | WARN_ON(fbc->active); | |
933 | return; | |
934 | } | |
615b40d7 | 935 | |
ab34a7e8 PZ |
936 | old_params = fbc->params; |
937 | intel_fbc_get_reg_params(crtc, &fbc->params); | |
b183b3f1 | 938 | |
7ff0ebcc RV |
939 | /* If the scanout has not changed, don't modify the FBC settings. |
940 | * Note that we make the fundamental assumption that the fb->obj | |
941 | * cannot be unpinned (and have its GTT offset and fence revoked) | |
942 | * without first being decoupled from the scanout and FBC disabled. | |
943 | */ | |
ab34a7e8 PZ |
944 | if (fbc->active && |
945 | intel_fbc_reg_params_equal(&old_params, &fbc->params)) | |
7ff0ebcc RV |
946 | return; |
947 | ||
212890cf | 948 | __intel_fbc_deactivate(dev_priv); |
0e631adc | 949 | intel_fbc_schedule_activation(crtc); |
212890cf | 950 | fbc->no_fbc_reason = "FBC enabled (active or scheduled)"; |
25ad93fd PZ |
951 | } |
952 | ||
953 | /* | |
d029bcad | 954 | * intel_fbc_update - activate/deactivate FBC as needed |
754d1133 | 955 | * @crtc: the CRTC that triggered the update |
25ad93fd | 956 | * |
d029bcad | 957 | * This function reevaluates the overall state and activates or deactivates FBC. |
25ad93fd | 958 | */ |
754d1133 | 959 | void intel_fbc_update(struct intel_crtc *crtc) |
25ad93fd | 960 | { |
754d1133 | 961 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
ab34a7e8 | 962 | struct intel_fbc *fbc = &dev_priv->fbc; |
754d1133 | 963 | |
9f218336 | 964 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
965 | return; |
966 | ||
ab34a7e8 | 967 | mutex_lock(&fbc->lock); |
212890cf PZ |
968 | intel_fbc_pre_update(crtc); |
969 | intel_fbc_post_update(crtc); | |
ab34a7e8 | 970 | mutex_unlock(&fbc->lock); |
7ff0ebcc RV |
971 | } |
972 | ||
261fe99a PZ |
973 | static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc) |
974 | { | |
975 | if (fbc->enabled) | |
976 | return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit; | |
977 | else | |
978 | return fbc->possible_framebuffer_bits; | |
979 | } | |
980 | ||
dbef0f15 PZ |
981 | void intel_fbc_invalidate(struct drm_i915_private *dev_priv, |
982 | unsigned int frontbuffer_bits, | |
983 | enum fb_op_origin origin) | |
984 | { | |
ab34a7e8 | 985 | struct intel_fbc *fbc = &dev_priv->fbc; |
dbef0f15 | 986 | |
9f218336 | 987 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
988 | return; |
989 | ||
0dd81544 | 990 | if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP) |
dbef0f15 PZ |
991 | return; |
992 | ||
ab34a7e8 | 993 | mutex_lock(&fbc->lock); |
25ad93fd | 994 | |
261fe99a | 995 | fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits; |
dbef0f15 | 996 | |
ab34a7e8 | 997 | if (fbc->busy_bits) |
d029bcad | 998 | __intel_fbc_deactivate(dev_priv); |
25ad93fd | 999 | |
ab34a7e8 | 1000 | mutex_unlock(&fbc->lock); |
dbef0f15 PZ |
1001 | } |
1002 | ||
1003 | void intel_fbc_flush(struct drm_i915_private *dev_priv, | |
6f4551fe | 1004 | unsigned int frontbuffer_bits, enum fb_op_origin origin) |
dbef0f15 | 1005 | { |
ab34a7e8 PZ |
1006 | struct intel_fbc *fbc = &dev_priv->fbc; |
1007 | ||
9f218336 | 1008 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
1009 | return; |
1010 | ||
0dd81544 | 1011 | if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP) |
6f4551fe | 1012 | return; |
25ad93fd | 1013 | |
ab34a7e8 | 1014 | mutex_lock(&fbc->lock); |
dbef0f15 | 1015 | |
ab34a7e8 | 1016 | fbc->busy_bits &= ~frontbuffer_bits; |
dbef0f15 | 1017 | |
261fe99a PZ |
1018 | if (!fbc->busy_bits && fbc->enabled && |
1019 | (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) { | |
0dd81544 | 1020 | if (fbc->active) |
ee7d6cfa | 1021 | intel_fbc_recompress(dev_priv); |
0dd81544 | 1022 | else |
212890cf | 1023 | intel_fbc_post_update(fbc->crtc); |
6f4551fe | 1024 | } |
25ad93fd | 1025 | |
ab34a7e8 | 1026 | mutex_unlock(&fbc->lock); |
dbef0f15 PZ |
1027 | } |
1028 | ||
d029bcad PZ |
1029 | /** |
1030 | * intel_fbc_enable: tries to enable FBC on the CRTC | |
1031 | * @crtc: the CRTC | |
1032 | * | |
1033 | * This function checks if it's possible to enable FBC on the following CRTC, | |
1034 | * then enables it. Notice that it doesn't activate FBC. | |
1035 | */ | |
1036 | void intel_fbc_enable(struct intel_crtc *crtc) | |
1037 | { | |
1038 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
ab34a7e8 | 1039 | struct intel_fbc *fbc = &dev_priv->fbc; |
d029bcad PZ |
1040 | |
1041 | if (!fbc_supported(dev_priv)) | |
1042 | return; | |
1043 | ||
ab34a7e8 | 1044 | mutex_lock(&fbc->lock); |
d029bcad | 1045 | |
ab34a7e8 PZ |
1046 | if (fbc->enabled) { |
1047 | WARN_ON(fbc->crtc == crtc); | |
d029bcad PZ |
1048 | goto out; |
1049 | } | |
1050 | ||
ab34a7e8 PZ |
1051 | WARN_ON(fbc->active); |
1052 | WARN_ON(fbc->crtc != NULL); | |
d029bcad | 1053 | |
44a8a257 | 1054 | if (!intel_fbc_can_enable(crtc)) |
d029bcad | 1055 | goto out; |
d029bcad | 1056 | |
aaf78d27 | 1057 | intel_fbc_update_state_cache(crtc); |
c5ecd469 PZ |
1058 | if (intel_fbc_alloc_cfb(crtc)) { |
1059 | set_no_fbc_reason(dev_priv, "not enough stolen memory"); | |
1060 | goto out; | |
1061 | } | |
1062 | ||
d029bcad | 1063 | DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc->pipe)); |
ab34a7e8 | 1064 | fbc->no_fbc_reason = "FBC enabled but not active yet\n"; |
d029bcad | 1065 | |
ab34a7e8 PZ |
1066 | fbc->enabled = true; |
1067 | fbc->crtc = crtc; | |
d029bcad | 1068 | out: |
ab34a7e8 | 1069 | mutex_unlock(&fbc->lock); |
d029bcad PZ |
1070 | } |
1071 | ||
1072 | /** | |
1073 | * __intel_fbc_disable - disable FBC | |
1074 | * @dev_priv: i915 device instance | |
1075 | * | |
1076 | * This is the low level function that actually disables FBC. Callers should | |
1077 | * grab the FBC lock. | |
1078 | */ | |
1079 | static void __intel_fbc_disable(struct drm_i915_private *dev_priv) | |
1080 | { | |
ab34a7e8 PZ |
1081 | struct intel_fbc *fbc = &dev_priv->fbc; |
1082 | struct intel_crtc *crtc = fbc->crtc; | |
d029bcad | 1083 | |
ab34a7e8 PZ |
1084 | WARN_ON(!mutex_is_locked(&fbc->lock)); |
1085 | WARN_ON(!fbc->enabled); | |
1086 | WARN_ON(fbc->active); | |
d029bcad PZ |
1087 | assert_pipe_disabled(dev_priv, crtc->pipe); |
1088 | ||
1089 | DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc->pipe)); | |
1090 | ||
c5ecd469 PZ |
1091 | __intel_fbc_cleanup_cfb(dev_priv); |
1092 | ||
ab34a7e8 PZ |
1093 | fbc->enabled = false; |
1094 | fbc->crtc = NULL; | |
d029bcad PZ |
1095 | } |
1096 | ||
1097 | /** | |
1098 | * intel_fbc_disable_crtc - disable FBC if it's associated with crtc | |
1099 | * @crtc: the CRTC | |
1100 | * | |
1101 | * This function disables FBC if it's associated with the provided CRTC. | |
1102 | */ | |
1103 | void intel_fbc_disable_crtc(struct intel_crtc *crtc) | |
1104 | { | |
1105 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
ab34a7e8 | 1106 | struct intel_fbc *fbc = &dev_priv->fbc; |
d029bcad PZ |
1107 | |
1108 | if (!fbc_supported(dev_priv)) | |
1109 | return; | |
1110 | ||
ab34a7e8 PZ |
1111 | mutex_lock(&fbc->lock); |
1112 | if (fbc->crtc == crtc) { | |
1113 | WARN_ON(!fbc->enabled); | |
1114 | WARN_ON(fbc->active); | |
d029bcad PZ |
1115 | __intel_fbc_disable(dev_priv); |
1116 | } | |
ab34a7e8 | 1117 | mutex_unlock(&fbc->lock); |
d029bcad PZ |
1118 | } |
1119 | ||
1120 | /** | |
1121 | * intel_fbc_disable - globally disable FBC | |
1122 | * @dev_priv: i915 device instance | |
1123 | * | |
1124 | * This function disables FBC regardless of which CRTC is associated with it. | |
1125 | */ | |
1126 | void intel_fbc_disable(struct drm_i915_private *dev_priv) | |
1127 | { | |
ab34a7e8 PZ |
1128 | struct intel_fbc *fbc = &dev_priv->fbc; |
1129 | ||
d029bcad PZ |
1130 | if (!fbc_supported(dev_priv)) |
1131 | return; | |
1132 | ||
ab34a7e8 PZ |
1133 | mutex_lock(&fbc->lock); |
1134 | if (fbc->enabled) | |
d029bcad | 1135 | __intel_fbc_disable(dev_priv); |
ab34a7e8 | 1136 | mutex_unlock(&fbc->lock); |
d029bcad PZ |
1137 | } |
1138 | ||
94b83957 RV |
1139 | /** |
1140 | * intel_fbc_init - Initialize FBC | |
1141 | * @dev_priv: the i915 device | |
1142 | * | |
1143 | * This function might be called during PM init process. | |
1144 | */ | |
7ff0ebcc RV |
1145 | void intel_fbc_init(struct drm_i915_private *dev_priv) |
1146 | { | |
ab34a7e8 | 1147 | struct intel_fbc *fbc = &dev_priv->fbc; |
dbef0f15 PZ |
1148 | enum pipe pipe; |
1149 | ||
ab34a7e8 PZ |
1150 | INIT_WORK(&fbc->work.work, intel_fbc_work_fn); |
1151 | mutex_init(&fbc->lock); | |
1152 | fbc->enabled = false; | |
1153 | fbc->active = false; | |
1154 | fbc->work.scheduled = false; | |
25ad93fd | 1155 | |
7ff0ebcc | 1156 | if (!HAS_FBC(dev_priv)) { |
ab34a7e8 | 1157 | fbc->no_fbc_reason = "unsupported by this chipset"; |
7ff0ebcc RV |
1158 | return; |
1159 | } | |
1160 | ||
dbef0f15 | 1161 | for_each_pipe(dev_priv, pipe) { |
ab34a7e8 | 1162 | fbc->possible_framebuffer_bits |= |
dbef0f15 PZ |
1163 | INTEL_FRONTBUFFER_PRIMARY(pipe); |
1164 | ||
57105022 | 1165 | if (fbc_on_pipe_a_only(dev_priv)) |
dbef0f15 PZ |
1166 | break; |
1167 | } | |
1168 | ||
7ff0ebcc | 1169 | if (INTEL_INFO(dev_priv)->gen >= 7) { |
ab34a7e8 PZ |
1170 | fbc->is_active = ilk_fbc_is_active; |
1171 | fbc->activate = gen7_fbc_activate; | |
1172 | fbc->deactivate = ilk_fbc_deactivate; | |
7ff0ebcc | 1173 | } else if (INTEL_INFO(dev_priv)->gen >= 5) { |
ab34a7e8 PZ |
1174 | fbc->is_active = ilk_fbc_is_active; |
1175 | fbc->activate = ilk_fbc_activate; | |
1176 | fbc->deactivate = ilk_fbc_deactivate; | |
7ff0ebcc | 1177 | } else if (IS_GM45(dev_priv)) { |
ab34a7e8 PZ |
1178 | fbc->is_active = g4x_fbc_is_active; |
1179 | fbc->activate = g4x_fbc_activate; | |
1180 | fbc->deactivate = g4x_fbc_deactivate; | |
7ff0ebcc | 1181 | } else { |
ab34a7e8 PZ |
1182 | fbc->is_active = i8xx_fbc_is_active; |
1183 | fbc->activate = i8xx_fbc_activate; | |
1184 | fbc->deactivate = i8xx_fbc_deactivate; | |
7ff0ebcc RV |
1185 | |
1186 | /* This value was pulled out of someone's hat */ | |
1187 | I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT); | |
1188 | } | |
1189 | ||
b07ea0fa | 1190 | /* We still don't have any sort of hardware state readout for FBC, so |
0e631adc PZ |
1191 | * deactivate it in case the BIOS activated it to make sure software |
1192 | * matches the hardware state. */ | |
ab34a7e8 PZ |
1193 | if (fbc->is_active(dev_priv)) |
1194 | fbc->deactivate(dev_priv); | |
7ff0ebcc | 1195 | } |