Commit | Line | Data |
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79e53945 JB |
1 | /* |
2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright (c) 2007-2008 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
23 | * IN THE SOFTWARE. | |
24 | */ | |
25 | #ifndef __INTEL_DRV_H__ | |
26 | #define __INTEL_DRV_H__ | |
27 | ||
28 | #include <linux/i2c.h> | |
8ea30864 | 29 | #include "i915_drm.h" |
80824003 | 30 | #include "i915_drv.h" |
79e53945 | 31 | #include "drm_crtc.h" |
79e53945 | 32 | #include "drm_crtc_helper.h" |
37811fcc | 33 | #include "drm_fb_helper.h" |
913d8d11 | 34 | |
481b6af3 | 35 | #define _wait_for(COND, MS, W) ({ \ |
913d8d11 CW |
36 | unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \ |
37 | int ret__ = 0; \ | |
0206e353 | 38 | while (!(COND)) { \ |
913d8d11 CW |
39 | if (time_after(jiffies, timeout__)) { \ |
40 | ret__ = -ETIMEDOUT; \ | |
41 | break; \ | |
42 | } \ | |
cc1f7194 | 43 | if (W && drm_can_sleep()) msleep(W); \ |
913d8d11 CW |
44 | } \ |
45 | ret__; \ | |
46 | }) | |
47 | ||
57f350b6 JB |
48 | #define wait_for_atomic_us(COND, US) ({ \ |
49 | int i, ret__ = -ETIMEDOUT; \ | |
50 | for (i = 0; i < (US); i++) { \ | |
51 | if ((COND)) { \ | |
52 | ret__ = 0; \ | |
53 | break; \ | |
54 | } \ | |
55 | udelay(1); \ | |
56 | } \ | |
57 | ret__; \ | |
58 | }) | |
59 | ||
481b6af3 CW |
60 | #define wait_for(COND, MS) _wait_for(COND, MS, 1) |
61 | #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) | |
62 | ||
021357ac CW |
63 | #define KHz(x) (1000*x) |
64 | #define MHz(x) KHz(1000*x) | |
65 | ||
79e53945 JB |
66 | /* |
67 | * Display related stuff | |
68 | */ | |
69 | ||
70 | /* store information about an Ixxx DVO */ | |
71 | /* The i830->i865 use multiple DVOs with multiple i2cs */ | |
72 | /* the i915, i945 have a single sDVO i2c bus - which is different */ | |
73 | #define MAX_OUTPUTS 6 | |
74 | /* maximum connectors per crtcs in the mode set */ | |
75 | #define INTELFB_CONN_LIMIT 4 | |
76 | ||
77 | #define INTEL_I2C_BUS_DVO 1 | |
78 | #define INTEL_I2C_BUS_SDVO 2 | |
79 | ||
80 | /* these are outputs from the chip - integrated only | |
81 | external chips are via DVO or SDVO output */ | |
82 | #define INTEL_OUTPUT_UNUSED 0 | |
83 | #define INTEL_OUTPUT_ANALOG 1 | |
84 | #define INTEL_OUTPUT_DVO 2 | |
85 | #define INTEL_OUTPUT_SDVO 3 | |
86 | #define INTEL_OUTPUT_LVDS 4 | |
87 | #define INTEL_OUTPUT_TVOUT 5 | |
7d57382e | 88 | #define INTEL_OUTPUT_HDMI 6 |
a4fc5ed6 | 89 | #define INTEL_OUTPUT_DISPLAYPORT 7 |
32f9d658 | 90 | #define INTEL_OUTPUT_EDP 8 |
79e53945 | 91 | |
f8aed700 ML |
92 | /* Intel Pipe Clone Bit */ |
93 | #define INTEL_HDMIB_CLONE_BIT 1 | |
94 | #define INTEL_HDMIC_CLONE_BIT 2 | |
95 | #define INTEL_HDMID_CLONE_BIT 3 | |
96 | #define INTEL_HDMIE_CLONE_BIT 4 | |
97 | #define INTEL_HDMIF_CLONE_BIT 5 | |
98 | #define INTEL_SDVO_NON_TV_CLONE_BIT 6 | |
99 | #define INTEL_SDVO_TV_CLONE_BIT 7 | |
100 | #define INTEL_SDVO_LVDS_CLONE_BIT 8 | |
101 | #define INTEL_ANALOG_CLONE_BIT 9 | |
102 | #define INTEL_TV_CLONE_BIT 10 | |
103 | #define INTEL_DP_B_CLONE_BIT 11 | |
104 | #define INTEL_DP_C_CLONE_BIT 12 | |
105 | #define INTEL_DP_D_CLONE_BIT 13 | |
106 | #define INTEL_LVDS_CLONE_BIT 14 | |
107 | #define INTEL_DVO_TMDS_CLONE_BIT 15 | |
108 | #define INTEL_DVO_LVDS_CLONE_BIT 16 | |
7c8460db | 109 | #define INTEL_EDP_CLONE_BIT 17 |
f8aed700 | 110 | |
79e53945 JB |
111 | #define INTEL_DVO_CHIP_NONE 0 |
112 | #define INTEL_DVO_CHIP_LVDS 1 | |
113 | #define INTEL_DVO_CHIP_TMDS 2 | |
114 | #define INTEL_DVO_CHIP_TVOUT 4 | |
115 | ||
6c9547ff CW |
116 | /* drm_display_mode->private_flags */ |
117 | #define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0) | |
118 | #define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT) | |
3b5c78a3 | 119 | #define INTEL_MODE_DP_FORCE_6BPC (0x10) |
f9bef081 DV |
120 | /* This flag must be set by the encoder's mode_fixup if it changes the crtc |
121 | * timings in the mode to prevent the crtc fixup from overwriting them. | |
122 | * Currently only lvds needs that. */ | |
123 | #define INTEL_MODE_CRTC_TIMINGS_SET (0x20) | |
6c9547ff CW |
124 | |
125 | static inline void | |
126 | intel_mode_set_pixel_multiplier(struct drm_display_mode *mode, | |
127 | int multiplier) | |
128 | { | |
129 | mode->clock *= multiplier; | |
130 | mode->private_flags |= multiplier; | |
131 | } | |
132 | ||
133 | static inline int | |
134 | intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode) | |
135 | { | |
136 | return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT; | |
137 | } | |
138 | ||
79e53945 JB |
139 | struct intel_framebuffer { |
140 | struct drm_framebuffer base; | |
05394f39 | 141 | struct drm_i915_gem_object *obj; |
79e53945 JB |
142 | }; |
143 | ||
37811fcc CW |
144 | struct intel_fbdev { |
145 | struct drm_fb_helper helper; | |
146 | struct intel_framebuffer ifb; | |
147 | struct list_head fbdev_list; | |
148 | struct drm_display_mode *our_mode; | |
149 | }; | |
79e53945 | 150 | |
21d40d37 | 151 | struct intel_encoder { |
4ef69c7a | 152 | struct drm_encoder base; |
79e53945 | 153 | int type; |
e2f0ba97 | 154 | bool needs_tv_clock; |
21d40d37 | 155 | void (*hot_plug)(struct intel_encoder *); |
f8aed700 ML |
156 | int crtc_mask; |
157 | int clone_mask; | |
79e53945 JB |
158 | }; |
159 | ||
5daa55eb ZW |
160 | struct intel_connector { |
161 | struct drm_connector base; | |
df0e9248 | 162 | struct intel_encoder *encoder; |
5daa55eb ZW |
163 | }; |
164 | ||
79e53945 JB |
165 | struct intel_crtc { |
166 | struct drm_crtc base; | |
80824003 JB |
167 | enum pipe pipe; |
168 | enum plane plane; | |
79e53945 JB |
169 | u8 lut_r[256], lut_g[256], lut_b[256]; |
170 | int dpms_mode; | |
f7abfe8b | 171 | bool active; /* is the crtc on? independent of the dpms mode */ |
652c393a JB |
172 | bool busy; /* is scanout buffer being updated frequently? */ |
173 | struct timer_list idle_timer; | |
174 | bool lowfreq_avail; | |
02e792fb | 175 | struct intel_overlay *overlay; |
6b95a207 | 176 | struct intel_unpin_work *unpin_work; |
77ffb597 | 177 | int fdi_lanes; |
cda4b7d3 | 178 | |
05394f39 | 179 | struct drm_i915_gem_object *cursor_bo; |
cda4b7d3 CW |
180 | uint32_t cursor_addr; |
181 | int16_t cursor_x, cursor_y; | |
182 | int16_t cursor_width, cursor_height; | |
6b383a7f | 183 | bool cursor_visible; |
5a354204 | 184 | unsigned int bpp; |
4b645f14 | 185 | |
ee7b9f93 JB |
186 | /* We can share PLLs across outputs if the timings match */ |
187 | struct intel_pch_pll *pch_pll; | |
79e53945 JB |
188 | }; |
189 | ||
b840d907 JB |
190 | struct intel_plane { |
191 | struct drm_plane base; | |
192 | enum pipe pipe; | |
193 | struct drm_i915_gem_object *obj; | |
175bd420 | 194 | bool primary_disabled; |
b840d907 JB |
195 | int max_downscale; |
196 | u32 lut_r[1024], lut_g[1024], lut_b[1024]; | |
197 | void (*update_plane)(struct drm_plane *plane, | |
198 | struct drm_framebuffer *fb, | |
199 | struct drm_i915_gem_object *obj, | |
200 | int crtc_x, int crtc_y, | |
201 | unsigned int crtc_w, unsigned int crtc_h, | |
202 | uint32_t x, uint32_t y, | |
203 | uint32_t src_w, uint32_t src_h); | |
204 | void (*disable_plane)(struct drm_plane *plane); | |
8ea30864 JB |
205 | int (*update_colorkey)(struct drm_plane *plane, |
206 | struct drm_intel_sprite_colorkey *key); | |
207 | void (*get_colorkey)(struct drm_plane *plane, | |
208 | struct drm_intel_sprite_colorkey *key); | |
b840d907 JB |
209 | }; |
210 | ||
b445e3b0 ED |
211 | struct intel_watermark_params { |
212 | unsigned long fifo_size; | |
213 | unsigned long max_wm; | |
214 | unsigned long default_wm; | |
215 | unsigned long guard_size; | |
216 | unsigned long cacheline_size; | |
217 | }; | |
218 | ||
219 | struct cxsr_latency { | |
220 | int is_desktop; | |
221 | int is_ddr3; | |
222 | unsigned long fsb_freq; | |
223 | unsigned long mem_freq; | |
224 | unsigned long display_sr; | |
225 | unsigned long display_hpll_disable; | |
226 | unsigned long cursor_sr; | |
227 | unsigned long cursor_hpll_disable; | |
228 | }; | |
229 | ||
79e53945 | 230 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
5daa55eb | 231 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
4ef69c7a | 232 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
79e53945 | 233 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
b840d907 | 234 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
79e53945 | 235 | |
45187ace JB |
236 | #define DIP_HEADER_SIZE 5 |
237 | ||
3c17fe4b DH |
238 | #define DIP_TYPE_AVI 0x82 |
239 | #define DIP_VERSION_AVI 0x2 | |
240 | #define DIP_LEN_AVI 13 | |
c846b619 PZ |
241 | #define DIP_AVI_PR_1 0 |
242 | #define DIP_AVI_PR_2 1 | |
3c17fe4b | 243 | |
26005210 | 244 | #define DIP_TYPE_SPD 0x83 |
c0864cb3 JB |
245 | #define DIP_VERSION_SPD 0x1 |
246 | #define DIP_LEN_SPD 25 | |
247 | #define DIP_SPD_UNKNOWN 0 | |
248 | #define DIP_SPD_DSTB 0x1 | |
249 | #define DIP_SPD_DVDP 0x2 | |
250 | #define DIP_SPD_DVHS 0x3 | |
251 | #define DIP_SPD_HDDVR 0x4 | |
252 | #define DIP_SPD_DVC 0x5 | |
253 | #define DIP_SPD_DSC 0x6 | |
254 | #define DIP_SPD_VCD 0x7 | |
255 | #define DIP_SPD_GAME 0x8 | |
256 | #define DIP_SPD_PC 0x9 | |
257 | #define DIP_SPD_BD 0xa | |
258 | #define DIP_SPD_SCD 0xb | |
259 | ||
3c17fe4b DH |
260 | struct dip_infoframe { |
261 | uint8_t type; /* HB0 */ | |
262 | uint8_t ver; /* HB1 */ | |
263 | uint8_t len; /* HB2 - body len, not including checksum */ | |
264 | uint8_t ecc; /* Header ECC */ | |
265 | uint8_t checksum; /* PB0 */ | |
266 | union { | |
267 | struct { | |
268 | /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */ | |
269 | uint8_t Y_A_B_S; | |
270 | /* PB2 - C 7:6, M 5:4, R 3:0 */ | |
271 | uint8_t C_M_R; | |
272 | /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */ | |
273 | uint8_t ITC_EC_Q_SC; | |
274 | /* PB4 - VIC 6:0 */ | |
275 | uint8_t VIC; | |
0aa534df PZ |
276 | /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */ |
277 | uint8_t YQ_CN_PR; | |
3c17fe4b DH |
278 | /* PB6 to PB13 */ |
279 | uint16_t top_bar_end; | |
280 | uint16_t bottom_bar_start; | |
281 | uint16_t left_bar_end; | |
282 | uint16_t right_bar_start; | |
283 | } avi; | |
c0864cb3 JB |
284 | struct { |
285 | uint8_t vn[8]; | |
286 | uint8_t pd[16]; | |
287 | uint8_t sdi; | |
288 | } spd; | |
3c17fe4b DH |
289 | uint8_t payload[27]; |
290 | } __attribute__ ((packed)) body; | |
291 | } __attribute__((packed)); | |
292 | ||
f875c15a CW |
293 | static inline struct drm_crtc * |
294 | intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) | |
295 | { | |
296 | struct drm_i915_private *dev_priv = dev->dev_private; | |
297 | return dev_priv->pipe_to_crtc_mapping[pipe]; | |
298 | } | |
299 | ||
417ae147 CW |
300 | static inline struct drm_crtc * |
301 | intel_get_crtc_for_plane(struct drm_device *dev, int plane) | |
302 | { | |
303 | struct drm_i915_private *dev_priv = dev->dev_private; | |
304 | return dev_priv->plane_to_crtc_mapping[plane]; | |
305 | } | |
306 | ||
4e5359cd SF |
307 | struct intel_unpin_work { |
308 | struct work_struct work; | |
309 | struct drm_device *dev; | |
05394f39 CW |
310 | struct drm_i915_gem_object *old_fb_obj; |
311 | struct drm_i915_gem_object *pending_flip_obj; | |
4e5359cd SF |
312 | struct drm_pending_vblank_event *event; |
313 | int pending; | |
314 | bool enable_stall_check; | |
315 | }; | |
316 | ||
1630fe75 CW |
317 | struct intel_fbc_work { |
318 | struct delayed_work work; | |
319 | struct drm_crtc *crtc; | |
320 | struct drm_framebuffer *fb; | |
321 | int interval; | |
322 | }; | |
323 | ||
335af9a2 | 324 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); |
f899fc64 | 325 | extern bool intel_ddc_probe(struct intel_encoder *intel_encoder, int ddc_bus); |
f0217c42 | 326 | |
3f43c48d | 327 | extern void intel_attach_force_audio_property(struct drm_connector *connector); |
e953fd7b CW |
328 | extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector); |
329 | ||
79e53945 | 330 | extern void intel_crt_init(struct drm_device *dev); |
7d57382e | 331 | extern void intel_hdmi_init(struct drm_device *dev, int sdvox_reg); |
3c17fe4b | 332 | void intel_dip_infoframe_csum(struct dip_infoframe *avi_if); |
eef4eacb DV |
333 | extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, |
334 | bool is_sdvob); | |
79e53945 JB |
335 | extern void intel_dvo_init(struct drm_device *dev); |
336 | extern void intel_tv_init(struct drm_device *dev); | |
05394f39 CW |
337 | extern void intel_mark_busy(struct drm_device *dev, |
338 | struct drm_i915_gem_object *obj); | |
c5d1b51d | 339 | extern bool intel_lvds_init(struct drm_device *dev); |
a4fc5ed6 KP |
340 | extern void intel_dp_init(struct drm_device *dev, int dp_reg); |
341 | void | |
342 | intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, | |
343 | struct drm_display_mode *adjusted_mode); | |
cb0953d7 | 344 | extern bool intel_dpd_is_edp(struct drm_device *dev); |
0206e353 | 345 | extern void intel_edp_link_config(struct intel_encoder *, int *, int *); |
814948ad | 346 | extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder); |
b840d907 | 347 | extern int intel_plane_init(struct drm_device *dev, enum pipe pipe); |
6f1d69b0 ED |
348 | extern void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
349 | enum plane plane); | |
32f9d658 | 350 | |
9104183d CW |
351 | void intel_sanitize_pm(struct drm_device *dev); |
352 | ||
a9573556 | 353 | /* intel_panel.c */ |
1d8e1c75 CW |
354 | extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, |
355 | struct drm_display_mode *adjusted_mode); | |
356 | extern void intel_pch_panel_fitting(struct drm_device *dev, | |
357 | int fitting_mode, | |
358 | struct drm_display_mode *mode, | |
359 | struct drm_display_mode *adjusted_mode); | |
a9573556 CW |
360 | extern u32 intel_panel_get_max_backlight(struct drm_device *dev); |
361 | extern u32 intel_panel_get_backlight(struct drm_device *dev); | |
362 | extern void intel_panel_set_backlight(struct drm_device *dev, u32 level); | |
aaa6fd2a | 363 | extern int intel_panel_setup_backlight(struct drm_device *dev); |
47356eb6 CW |
364 | extern void intel_panel_enable_backlight(struct drm_device *dev); |
365 | extern void intel_panel_disable_backlight(struct drm_device *dev); | |
aaa6fd2a | 366 | extern void intel_panel_destroy_backlight(struct drm_device *dev); |
fe16d949 | 367 | extern enum drm_connector_status intel_panel_detect(struct drm_device *dev); |
1d8e1c75 | 368 | |
79e53945 | 369 | extern void intel_crtc_load_lut(struct drm_crtc *crtc); |
0206e353 AJ |
370 | extern void intel_encoder_prepare(struct drm_encoder *encoder); |
371 | extern void intel_encoder_commit(struct drm_encoder *encoder); | |
ea5b213a | 372 | extern void intel_encoder_destroy(struct drm_encoder *encoder); |
79e53945 | 373 | |
df0e9248 CW |
374 | static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector) |
375 | { | |
376 | return to_intel_connector(connector)->encoder; | |
377 | } | |
378 | ||
379 | extern void intel_connector_attach_encoder(struct intel_connector *connector, | |
380 | struct intel_encoder *encoder); | |
381 | extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector); | |
79e53945 JB |
382 | |
383 | extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
384 | struct drm_crtc *crtc); | |
08d7b3d1 CW |
385 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
386 | struct drm_file *file_priv); | |
9d0498a2 | 387 | extern void intel_wait_for_vblank(struct drm_device *dev, int pipe); |
58e10eb9 | 388 | extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe); |
8261b191 CW |
389 | |
390 | struct intel_load_detect_pipe { | |
d2dff872 | 391 | struct drm_framebuffer *release_fb; |
8261b191 CW |
392 | bool load_detect_temp; |
393 | int dpms_mode; | |
394 | }; | |
7173188d CW |
395 | extern bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, |
396 | struct drm_connector *connector, | |
397 | struct drm_display_mode *mode, | |
8261b191 | 398 | struct intel_load_detect_pipe *old); |
21d40d37 | 399 | extern void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, |
c1c43977 | 400 | struct drm_connector *connector, |
8261b191 | 401 | struct intel_load_detect_pipe *old); |
79e53945 | 402 | |
79e53945 JB |
403 | extern void intelfb_restore(void); |
404 | extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
405 | u16 blue, int regno); | |
b8c00ac5 DA |
406 | extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
407 | u16 *blue, int regno); | |
0cdab21f | 408 | extern void intel_enable_clock_gating(struct drm_device *dev); |
2b4e57bd | 409 | extern void ironlake_disable_rc6(struct drm_device *dev); |
f97108d1 JB |
410 | extern void ironlake_enable_drps(struct drm_device *dev); |
411 | extern void ironlake_disable_drps(struct drm_device *dev); | |
79e53945 | 412 | |
127bd2ac | 413 | extern int intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 414 | struct drm_i915_gem_object *obj, |
919926ae | 415 | struct intel_ring_buffer *pipelined); |
1690e1eb | 416 | extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj); |
127bd2ac | 417 | |
38651674 DA |
418 | extern int intel_framebuffer_init(struct drm_device *dev, |
419 | struct intel_framebuffer *ifb, | |
308e5bcb | 420 | struct drm_mode_fb_cmd2 *mode_cmd, |
05394f39 | 421 | struct drm_i915_gem_object *obj); |
38651674 DA |
422 | extern int intel_fbdev_init(struct drm_device *dev); |
423 | extern void intel_fbdev_fini(struct drm_device *dev); | |
3fa016a0 | 424 | extern void intel_fbdev_set_suspend(struct drm_device *dev, int state); |
6b95a207 KH |
425 | extern void intel_prepare_page_flip(struct drm_device *dev, int plane); |
426 | extern void intel_finish_page_flip(struct drm_device *dev, int pipe); | |
1afe3e9d | 427 | extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane); |
6b95a207 | 428 | |
02e792fb DV |
429 | extern void intel_setup_overlay(struct drm_device *dev); |
430 | extern void intel_cleanup_overlay(struct drm_device *dev); | |
ce453d81 | 431 | extern int intel_overlay_switch_off(struct intel_overlay *overlay); |
02e792fb DV |
432 | extern int intel_overlay_put_image(struct drm_device *dev, void *data, |
433 | struct drm_file *file_priv); | |
434 | extern int intel_overlay_attrs(struct drm_device *dev, void *data, | |
435 | struct drm_file *file_priv); | |
4abe3520 | 436 | |
eb1f8e4f | 437 | extern void intel_fb_output_poll_changed(struct drm_device *dev); |
e8e7a2b8 | 438 | extern void intel_fb_restore_mode(struct drm_device *dev); |
645c62a5 | 439 | |
b840d907 JB |
440 | extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
441 | bool state); | |
442 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) | |
443 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) | |
444 | ||
645c62a5 | 445 | extern void intel_init_clock_gating(struct drm_device *dev); |
e0dac65e WF |
446 | extern void intel_write_eld(struct drm_encoder *encoder, |
447 | struct drm_display_mode *mode); | |
d4270e57 | 448 | extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe); |
45244b87 | 449 | extern void intel_prepare_ddi(struct drm_device *dev); |
c82e4d26 | 450 | extern void hsw_fdi_link_train(struct drm_crtc *crtc); |
d4270e57 | 451 | |
b840d907 | 452 | /* For use by IVB LP watermark workaround in intel_sprite.c */ |
f681fa23 | 453 | extern void intel_update_watermarks(struct drm_device *dev); |
b840d907 JB |
454 | extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, |
455 | uint32_t sprite_width, | |
456 | int pixel_size); | |
1f8eeabf ED |
457 | extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe, |
458 | struct drm_display_mode *mode); | |
8ea30864 JB |
459 | |
460 | extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data, | |
461 | struct drm_file *file_priv); | |
462 | extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data, | |
463 | struct drm_file *file_priv); | |
464 | ||
57f350b6 JB |
465 | extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg); |
466 | ||
85208be0 | 467 | /* Power-related functions, located in intel_pm.c */ |
1fa61106 | 468 | extern void intel_init_pm(struct drm_device *dev); |
85208be0 | 469 | /* FBC */ |
85208be0 ED |
470 | extern bool intel_fbc_enabled(struct drm_device *dev); |
471 | extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval); | |
472 | extern void intel_update_fbc(struct drm_device *dev); | |
eb48eb00 DV |
473 | /* IPS */ |
474 | extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv); | |
475 | extern void intel_gpu_ips_teardown(void); | |
85208be0 | 476 | |
b3daeaef DV |
477 | extern void gen6_enable_rps(struct drm_i915_private *dev_priv); |
478 | extern void gen6_update_ring_freq(struct drm_i915_private *dev_priv); | |
479 | extern void gen6_disable_rps(struct drm_device *dev); | |
480 | extern void intel_init_emon(struct drm_device *dev); | |
481 | ||
79e53945 | 482 | #endif /* __INTEL_DRV_H__ */ |