Commit | Line | Data |
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79e53945 JB |
1 | /* |
2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright (c) 2007-2008 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
23 | * IN THE SOFTWARE. | |
24 | */ | |
25 | #ifndef __INTEL_DRV_H__ | |
26 | #define __INTEL_DRV_H__ | |
27 | ||
28 | #include <linux/i2c.h> | |
760285e7 | 29 | #include <drm/i915_drm.h> |
80824003 | 30 | #include "i915_drv.h" |
760285e7 DH |
31 | #include <drm/drm_crtc.h> |
32 | #include <drm/drm_crtc_helper.h> | |
33 | #include <drm/drm_fb_helper.h> | |
612a9aab | 34 | #include <drm/drm_dp_helper.h> |
913d8d11 | 35 | |
1d5bfac9 DV |
36 | /** |
37 | * _wait_for - magic (register) wait macro | |
38 | * | |
39 | * Does the right thing for modeset paths when run under kdgb or similar atomic | |
40 | * contexts. Note that it's important that we check the condition again after | |
41 | * having timed out, since the timeout could be due to preemption or similar and | |
42 | * we've never had a chance to check the condition before the timeout. | |
43 | */ | |
481b6af3 | 44 | #define _wait_for(COND, MS, W) ({ \ |
1d5bfac9 | 45 | unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ |
913d8d11 | 46 | int ret__ = 0; \ |
0206e353 | 47 | while (!(COND)) { \ |
913d8d11 | 48 | if (time_after(jiffies, timeout__)) { \ |
1d5bfac9 DV |
49 | if (!(COND)) \ |
50 | ret__ = -ETIMEDOUT; \ | |
913d8d11 CW |
51 | break; \ |
52 | } \ | |
0cc2764c BW |
53 | if (W && drm_can_sleep()) { \ |
54 | msleep(W); \ | |
55 | } else { \ | |
56 | cpu_relax(); \ | |
57 | } \ | |
913d8d11 CW |
58 | } \ |
59 | ret__; \ | |
60 | }) | |
61 | ||
481b6af3 CW |
62 | #define wait_for(COND, MS) _wait_for(COND, MS, 1) |
63 | #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) | |
6effa33b DV |
64 | #define wait_for_atomic_us(COND, US) _wait_for((COND), \ |
65 | DIV_ROUND_UP((US), 1000), 0) | |
481b6af3 | 66 | |
021357ac CW |
67 | #define KHz(x) (1000*x) |
68 | #define MHz(x) KHz(1000*x) | |
69 | ||
79e53945 JB |
70 | /* |
71 | * Display related stuff | |
72 | */ | |
73 | ||
74 | /* store information about an Ixxx DVO */ | |
75 | /* The i830->i865 use multiple DVOs with multiple i2cs */ | |
76 | /* the i915, i945 have a single sDVO i2c bus - which is different */ | |
77 | #define MAX_OUTPUTS 6 | |
78 | /* maximum connectors per crtcs in the mode set */ | |
79 | #define INTELFB_CONN_LIMIT 4 | |
80 | ||
81 | #define INTEL_I2C_BUS_DVO 1 | |
82 | #define INTEL_I2C_BUS_SDVO 2 | |
83 | ||
84 | /* these are outputs from the chip - integrated only | |
85 | external chips are via DVO or SDVO output */ | |
86 | #define INTEL_OUTPUT_UNUSED 0 | |
87 | #define INTEL_OUTPUT_ANALOG 1 | |
88 | #define INTEL_OUTPUT_DVO 2 | |
89 | #define INTEL_OUTPUT_SDVO 3 | |
90 | #define INTEL_OUTPUT_LVDS 4 | |
91 | #define INTEL_OUTPUT_TVOUT 5 | |
7d57382e | 92 | #define INTEL_OUTPUT_HDMI 6 |
a4fc5ed6 | 93 | #define INTEL_OUTPUT_DISPLAYPORT 7 |
32f9d658 | 94 | #define INTEL_OUTPUT_EDP 8 |
00c09d70 | 95 | #define INTEL_OUTPUT_UNKNOWN 9 |
79e53945 JB |
96 | |
97 | #define INTEL_DVO_CHIP_NONE 0 | |
98 | #define INTEL_DVO_CHIP_LVDS 1 | |
99 | #define INTEL_DVO_CHIP_TMDS 2 | |
100 | #define INTEL_DVO_CHIP_TVOUT 4 | |
101 | ||
79e53945 JB |
102 | struct intel_framebuffer { |
103 | struct drm_framebuffer base; | |
05394f39 | 104 | struct drm_i915_gem_object *obj; |
79e53945 JB |
105 | }; |
106 | ||
37811fcc CW |
107 | struct intel_fbdev { |
108 | struct drm_fb_helper helper; | |
109 | struct intel_framebuffer ifb; | |
110 | struct list_head fbdev_list; | |
111 | struct drm_display_mode *our_mode; | |
112 | }; | |
79e53945 | 113 | |
21d40d37 | 114 | struct intel_encoder { |
4ef69c7a | 115 | struct drm_encoder base; |
9a935856 DV |
116 | /* |
117 | * The new crtc this encoder will be driven from. Only differs from | |
118 | * base->crtc while a modeset is in progress. | |
119 | */ | |
120 | struct intel_crtc *new_crtc; | |
121 | ||
79e53945 | 122 | int type; |
e2f0ba97 | 123 | bool needs_tv_clock; |
66a9278e DV |
124 | /* |
125 | * Intel hw has only one MUX where encoders could be clone, hence a | |
126 | * simple flag is enough to compute the possible_clones mask. | |
127 | */ | |
128 | bool cloneable; | |
5ab432ef | 129 | bool connectors_active; |
21d40d37 | 130 | void (*hot_plug)(struct intel_encoder *); |
7ae89233 DV |
131 | bool (*compute_config)(struct intel_encoder *, |
132 | struct intel_crtc_config *); | |
dafd226c | 133 | void (*pre_pll_enable)(struct intel_encoder *); |
bf49ec8c | 134 | void (*pre_enable)(struct intel_encoder *); |
ef9c3aee | 135 | void (*enable)(struct intel_encoder *); |
6cc5f341 | 136 | void (*mode_set)(struct intel_encoder *intel_encoder); |
ef9c3aee | 137 | void (*disable)(struct intel_encoder *); |
bf49ec8c | 138 | void (*post_disable)(struct intel_encoder *); |
f0947c37 DV |
139 | /* Read out the current hw state of this connector, returning true if |
140 | * the encoder is active. If the encoder is enabled it also set the pipe | |
141 | * it is connected to in the pipe parameter. */ | |
142 | bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); | |
f8aed700 | 143 | int crtc_mask; |
1d843f9d | 144 | enum hpd_pin hpd_pin; |
79e53945 JB |
145 | }; |
146 | ||
1d508706 | 147 | struct intel_panel { |
dd06f90e | 148 | struct drm_display_mode *fixed_mode; |
4d891523 | 149 | int fitting_mode; |
1d508706 JN |
150 | }; |
151 | ||
5daa55eb ZW |
152 | struct intel_connector { |
153 | struct drm_connector base; | |
9a935856 DV |
154 | /* |
155 | * The fixed encoder this connector is connected to. | |
156 | */ | |
df0e9248 | 157 | struct intel_encoder *encoder; |
9a935856 DV |
158 | |
159 | /* | |
160 | * The new encoder this connector will be driven. Only differs from | |
161 | * encoder while a modeset is in progress. | |
162 | */ | |
163 | struct intel_encoder *new_encoder; | |
164 | ||
f0947c37 DV |
165 | /* Reads out the current hw, returning true if the connector is enabled |
166 | * and active (i.e. dpms ON state). */ | |
167 | bool (*get_hw_state)(struct intel_connector *); | |
1d508706 JN |
168 | |
169 | /* Panel info for eDP and LVDS */ | |
170 | struct intel_panel panel; | |
9cd300e0 JN |
171 | |
172 | /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ | |
173 | struct edid *edid; | |
821450c6 EE |
174 | |
175 | /* since POLL and HPD connectors may use the same HPD line keep the native | |
176 | state of connector->polled in case hotplug storm detection changes it */ | |
177 | u8 polled; | |
5daa55eb ZW |
178 | }; |
179 | ||
b8cecdf5 DV |
180 | struct intel_crtc_config { |
181 | struct drm_display_mode requested_mode; | |
182 | struct drm_display_mode adjusted_mode; | |
7ae89233 DV |
183 | /* This flag must be set by the encoder's compute_config callback if it |
184 | * changes the crtc timings in the mode to prevent the crtc fixup from | |
185 | * overwriting them. Currently only lvds needs that. */ | |
186 | bool timings_set; | |
5bfe2ac0 DV |
187 | /* Whether to set up the PCH/FDI. Note that we never allow sharing |
188 | * between pch encoders and cpu encoders. */ | |
189 | bool has_pch_encoder; | |
50f3b016 | 190 | |
3b117c8f DV |
191 | /* CPU Transcoder for the pipe. Currently this can only differ from the |
192 | * pipe on Haswell (where we have a special eDP transcoder). */ | |
193 | enum transcoder cpu_transcoder; | |
194 | ||
50f3b016 DV |
195 | /* |
196 | * Use reduced/limited/broadcast rbg range, compressing from the full | |
197 | * range fed into the crtcs. | |
198 | */ | |
199 | bool limited_color_range; | |
200 | ||
03afc4a2 DV |
201 | /* DP has a bunch of special case unfortunately, so mark the pipe |
202 | * accordingly. */ | |
203 | bool has_dp_encoder; | |
965e0c48 | 204 | bool dither; |
f47709a9 DV |
205 | |
206 | /* Controls for the clock computation, to override various stages. */ | |
207 | bool clock_set; | |
208 | ||
209 | /* Settings for the intel dpll used on pretty much everything but | |
210 | * haswell. */ | |
211 | struct dpll { | |
212 | unsigned n; | |
213 | unsigned m1, m2; | |
214 | unsigned p1, p2; | |
215 | } dpll; | |
216 | ||
965e0c48 | 217 | int pipe_bpp; |
6cf86a5e | 218 | struct intel_link_m_n dp_m_n; |
df92b1e6 DV |
219 | /** |
220 | * This is currently used by DP and HDMI encoders since those can have a | |
221 | * target pixel clock != the port link clock (which is currently stored | |
222 | * in adjusted_mode->clock). | |
223 | */ | |
224 | int pixel_target_clock; | |
6cc5f341 DV |
225 | /* Used by SDVO (and if we ever fix it, HDMI). */ |
226 | unsigned pixel_multiplier; | |
b8cecdf5 DV |
227 | }; |
228 | ||
79e53945 JB |
229 | struct intel_crtc { |
230 | struct drm_crtc base; | |
80824003 JB |
231 | enum pipe pipe; |
232 | enum plane plane; | |
79e53945 | 233 | u8 lut_r[256], lut_g[256], lut_b[256]; |
08a48469 DV |
234 | /* |
235 | * Whether the crtc and the connected output pipeline is active. Implies | |
236 | * that crtc->enabled is set, i.e. the current mode configuration has | |
237 | * some outputs connected to this crtc. | |
08a48469 DV |
238 | */ |
239 | bool active; | |
7b9f35a6 | 240 | bool eld_vld; |
93314b5b | 241 | bool primary_disabled; /* is the crtc obscured by a plane? */ |
652c393a | 242 | bool lowfreq_avail; |
02e792fb | 243 | struct intel_overlay *overlay; |
6b95a207 | 244 | struct intel_unpin_work *unpin_work; |
77ffb597 | 245 | int fdi_lanes; |
cda4b7d3 | 246 | |
b4a98e57 CW |
247 | atomic_t unpin_work_count; |
248 | ||
e506a0c6 DV |
249 | /* Display surface base address adjustement for pageflips. Note that on |
250 | * gen4+ this only adjusts up to a tile, offsets within a tile are | |
251 | * handled in the hw itself (with the TILEOFF register). */ | |
252 | unsigned long dspaddr_offset; | |
253 | ||
05394f39 | 254 | struct drm_i915_gem_object *cursor_bo; |
cda4b7d3 CW |
255 | uint32_t cursor_addr; |
256 | int16_t cursor_x, cursor_y; | |
257 | int16_t cursor_width, cursor_height; | |
6b383a7f | 258 | bool cursor_visible; |
4b645f14 | 259 | |
b8cecdf5 DV |
260 | struct intel_crtc_config config; |
261 | ||
ee7b9f93 JB |
262 | /* We can share PLLs across outputs if the timings match */ |
263 | struct intel_pch_pll *pch_pll; | |
6441ab5f | 264 | uint32_t ddi_pll_sel; |
10d83730 VS |
265 | |
266 | /* reset counter value when the last flip was submitted */ | |
267 | unsigned int reset_counter; | |
79e53945 JB |
268 | }; |
269 | ||
b840d907 JB |
270 | struct intel_plane { |
271 | struct drm_plane base; | |
7f1f3851 | 272 | int plane; |
b840d907 JB |
273 | enum pipe pipe; |
274 | struct drm_i915_gem_object *obj; | |
2d354c34 | 275 | bool can_scale; |
b840d907 JB |
276 | int max_downscale; |
277 | u32 lut_r[1024], lut_g[1024], lut_b[1024]; | |
5e1bac2f JB |
278 | int crtc_x, crtc_y; |
279 | unsigned int crtc_w, crtc_h; | |
280 | uint32_t src_x, src_y; | |
281 | uint32_t src_w, src_h; | |
b840d907 JB |
282 | void (*update_plane)(struct drm_plane *plane, |
283 | struct drm_framebuffer *fb, | |
284 | struct drm_i915_gem_object *obj, | |
285 | int crtc_x, int crtc_y, | |
286 | unsigned int crtc_w, unsigned int crtc_h, | |
287 | uint32_t x, uint32_t y, | |
288 | uint32_t src_w, uint32_t src_h); | |
289 | void (*disable_plane)(struct drm_plane *plane); | |
8ea30864 JB |
290 | int (*update_colorkey)(struct drm_plane *plane, |
291 | struct drm_intel_sprite_colorkey *key); | |
292 | void (*get_colorkey)(struct drm_plane *plane, | |
293 | struct drm_intel_sprite_colorkey *key); | |
b840d907 JB |
294 | }; |
295 | ||
b445e3b0 ED |
296 | struct intel_watermark_params { |
297 | unsigned long fifo_size; | |
298 | unsigned long max_wm; | |
299 | unsigned long default_wm; | |
300 | unsigned long guard_size; | |
301 | unsigned long cacheline_size; | |
302 | }; | |
303 | ||
304 | struct cxsr_latency { | |
305 | int is_desktop; | |
306 | int is_ddr3; | |
307 | unsigned long fsb_freq; | |
308 | unsigned long mem_freq; | |
309 | unsigned long display_sr; | |
310 | unsigned long display_hpll_disable; | |
311 | unsigned long cursor_sr; | |
312 | unsigned long cursor_hpll_disable; | |
313 | }; | |
314 | ||
79e53945 | 315 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
5daa55eb | 316 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
4ef69c7a | 317 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
79e53945 | 318 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
b840d907 | 319 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
79e53945 | 320 | |
45187ace JB |
321 | #define DIP_HEADER_SIZE 5 |
322 | ||
3c17fe4b DH |
323 | #define DIP_TYPE_AVI 0x82 |
324 | #define DIP_VERSION_AVI 0x2 | |
325 | #define DIP_LEN_AVI 13 | |
c846b619 PZ |
326 | #define DIP_AVI_PR_1 0 |
327 | #define DIP_AVI_PR_2 1 | |
abedc077 VS |
328 | #define DIP_AVI_RGB_QUANT_RANGE_DEFAULT (0 << 2) |
329 | #define DIP_AVI_RGB_QUANT_RANGE_LIMITED (1 << 2) | |
330 | #define DIP_AVI_RGB_QUANT_RANGE_FULL (2 << 2) | |
3c17fe4b | 331 | |
26005210 | 332 | #define DIP_TYPE_SPD 0x83 |
c0864cb3 JB |
333 | #define DIP_VERSION_SPD 0x1 |
334 | #define DIP_LEN_SPD 25 | |
335 | #define DIP_SPD_UNKNOWN 0 | |
336 | #define DIP_SPD_DSTB 0x1 | |
337 | #define DIP_SPD_DVDP 0x2 | |
338 | #define DIP_SPD_DVHS 0x3 | |
339 | #define DIP_SPD_HDDVR 0x4 | |
340 | #define DIP_SPD_DVC 0x5 | |
341 | #define DIP_SPD_DSC 0x6 | |
342 | #define DIP_SPD_VCD 0x7 | |
343 | #define DIP_SPD_GAME 0x8 | |
344 | #define DIP_SPD_PC 0x9 | |
345 | #define DIP_SPD_BD 0xa | |
346 | #define DIP_SPD_SCD 0xb | |
347 | ||
3c17fe4b DH |
348 | struct dip_infoframe { |
349 | uint8_t type; /* HB0 */ | |
350 | uint8_t ver; /* HB1 */ | |
351 | uint8_t len; /* HB2 - body len, not including checksum */ | |
352 | uint8_t ecc; /* Header ECC */ | |
353 | uint8_t checksum; /* PB0 */ | |
354 | union { | |
355 | struct { | |
356 | /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */ | |
357 | uint8_t Y_A_B_S; | |
358 | /* PB2 - C 7:6, M 5:4, R 3:0 */ | |
359 | uint8_t C_M_R; | |
360 | /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */ | |
361 | uint8_t ITC_EC_Q_SC; | |
362 | /* PB4 - VIC 6:0 */ | |
363 | uint8_t VIC; | |
0aa534df PZ |
364 | /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */ |
365 | uint8_t YQ_CN_PR; | |
3c17fe4b DH |
366 | /* PB6 to PB13 */ |
367 | uint16_t top_bar_end; | |
368 | uint16_t bottom_bar_start; | |
369 | uint16_t left_bar_end; | |
370 | uint16_t right_bar_start; | |
81014b9d | 371 | } __attribute__ ((packed)) avi; |
c0864cb3 JB |
372 | struct { |
373 | uint8_t vn[8]; | |
374 | uint8_t pd[16]; | |
375 | uint8_t sdi; | |
81014b9d | 376 | } __attribute__ ((packed)) spd; |
3c17fe4b DH |
377 | uint8_t payload[27]; |
378 | } __attribute__ ((packed)) body; | |
379 | } __attribute__((packed)); | |
380 | ||
f5bbfca3 | 381 | struct intel_hdmi { |
b242b7f7 | 382 | u32 hdmi_reg; |
f5bbfca3 | 383 | int ddc_bus; |
f5bbfca3 | 384 | uint32_t color_range; |
55bc60db | 385 | bool color_range_auto; |
f5bbfca3 ED |
386 | bool has_hdmi_sink; |
387 | bool has_audio; | |
388 | enum hdmi_force_audio force_audio; | |
abedc077 | 389 | bool rgb_quant_range_selectable; |
f5bbfca3 ED |
390 | void (*write_infoframe)(struct drm_encoder *encoder, |
391 | struct dip_infoframe *frame); | |
687f4d06 PZ |
392 | void (*set_infoframes)(struct drm_encoder *encoder, |
393 | struct drm_display_mode *adjusted_mode); | |
f5bbfca3 ED |
394 | }; |
395 | ||
b091cd92 | 396 | #define DP_MAX_DOWNSTREAM_PORTS 0x10 |
54d63ca6 SK |
397 | #define DP_LINK_CONFIGURATION_SIZE 9 |
398 | ||
399 | struct intel_dp { | |
54d63ca6 | 400 | uint32_t output_reg; |
9ed35ab1 | 401 | uint32_t aux_ch_ctl_reg; |
54d63ca6 SK |
402 | uint32_t DP; |
403 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; | |
404 | bool has_audio; | |
405 | enum hdmi_force_audio force_audio; | |
406 | uint32_t color_range; | |
55bc60db | 407 | bool color_range_auto; |
54d63ca6 SK |
408 | uint8_t link_bw; |
409 | uint8_t lane_count; | |
410 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; | |
b091cd92 | 411 | uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; |
54d63ca6 SK |
412 | struct i2c_adapter adapter; |
413 | struct i2c_algo_dp_aux_data algo; | |
414 | bool is_pch_edp; | |
415 | uint8_t train_set[4]; | |
416 | int panel_power_up_delay; | |
417 | int panel_power_down_delay; | |
418 | int panel_power_cycle_delay; | |
419 | int backlight_on_delay; | |
420 | int backlight_off_delay; | |
54d63ca6 SK |
421 | struct delayed_work panel_vdd_work; |
422 | bool want_panel_vdd; | |
dd06f90e | 423 | struct intel_connector *attached_connector; |
54d63ca6 SK |
424 | }; |
425 | ||
da63a9f2 PZ |
426 | struct intel_digital_port { |
427 | struct intel_encoder base; | |
174edf1f | 428 | enum port port; |
876a8cdf | 429 | u32 port_reversal; |
da63a9f2 PZ |
430 | struct intel_dp dp; |
431 | struct intel_hdmi hdmi; | |
432 | }; | |
433 | ||
89b667f8 JB |
434 | static inline int |
435 | vlv_dport_to_channel(struct intel_digital_port *dport) | |
436 | { | |
437 | switch (dport->port) { | |
438 | case PORT_B: | |
439 | return 0; | |
440 | case PORT_C: | |
441 | return 1; | |
442 | default: | |
443 | BUG(); | |
444 | } | |
445 | } | |
446 | ||
f875c15a CW |
447 | static inline struct drm_crtc * |
448 | intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) | |
449 | { | |
450 | struct drm_i915_private *dev_priv = dev->dev_private; | |
451 | return dev_priv->pipe_to_crtc_mapping[pipe]; | |
452 | } | |
453 | ||
417ae147 CW |
454 | static inline struct drm_crtc * |
455 | intel_get_crtc_for_plane(struct drm_device *dev, int plane) | |
456 | { | |
457 | struct drm_i915_private *dev_priv = dev->dev_private; | |
458 | return dev_priv->plane_to_crtc_mapping[plane]; | |
459 | } | |
460 | ||
4e5359cd SF |
461 | struct intel_unpin_work { |
462 | struct work_struct work; | |
b4a98e57 | 463 | struct drm_crtc *crtc; |
05394f39 CW |
464 | struct drm_i915_gem_object *old_fb_obj; |
465 | struct drm_i915_gem_object *pending_flip_obj; | |
4e5359cd | 466 | struct drm_pending_vblank_event *event; |
e7d841ca CW |
467 | atomic_t pending; |
468 | #define INTEL_FLIP_INACTIVE 0 | |
469 | #define INTEL_FLIP_PENDING 1 | |
470 | #define INTEL_FLIP_COMPLETE 2 | |
4e5359cd SF |
471 | bool enable_stall_check; |
472 | }; | |
473 | ||
1630fe75 CW |
474 | struct intel_fbc_work { |
475 | struct delayed_work work; | |
476 | struct drm_crtc *crtc; | |
477 | struct drm_framebuffer *fb; | |
478 | int interval; | |
479 | }; | |
480 | ||
d2acd215 DV |
481 | int intel_pch_rawclk(struct drm_device *dev); |
482 | ||
4eab8136 JN |
483 | int intel_connector_update_modes(struct drm_connector *connector, |
484 | struct edid *edid); | |
335af9a2 | 485 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); |
f0217c42 | 486 | |
3f43c48d | 487 | extern void intel_attach_force_audio_property(struct drm_connector *connector); |
e953fd7b CW |
488 | extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector); |
489 | ||
79e53945 | 490 | extern void intel_crt_init(struct drm_device *dev); |
08d644ad | 491 | extern void intel_hdmi_init(struct drm_device *dev, |
b242b7f7 | 492 | int hdmi_reg, enum port port); |
00c09d70 PZ |
493 | extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
494 | struct intel_connector *intel_connector); | |
f5bbfca3 | 495 | extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); |
5bfe2ac0 DV |
496 | extern bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
497 | struct intel_crtc_config *pipe_config); | |
f5bbfca3 | 498 | extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if); |
eef4eacb DV |
499 | extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, |
500 | bool is_sdvob); | |
79e53945 JB |
501 | extern void intel_dvo_init(struct drm_device *dev); |
502 | extern void intel_tv_init(struct drm_device *dev); | |
f047e395 | 503 | extern void intel_mark_busy(struct drm_device *dev); |
f047e395 | 504 | extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj); |
725a5b54 | 505 | extern void intel_mark_idle(struct drm_device *dev); |
c5d1b51d | 506 | extern bool intel_lvds_init(struct drm_device *dev); |
1974cad0 | 507 | extern bool intel_is_dual_link_lvds(struct drm_device *dev); |
ab9d7c30 PZ |
508 | extern void intel_dp_init(struct drm_device *dev, int output_reg, |
509 | enum port port); | |
00c09d70 PZ |
510 | extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
511 | struct intel_connector *intel_connector); | |
247d89f6 | 512 | extern void intel_dp_init_link_config(struct intel_dp *intel_dp); |
c19b0669 PZ |
513 | extern void intel_dp_start_link_train(struct intel_dp *intel_dp); |
514 | extern void intel_dp_complete_link_train(struct intel_dp *intel_dp); | |
515 | extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); | |
00c09d70 PZ |
516 | extern void intel_dp_encoder_destroy(struct drm_encoder *encoder); |
517 | extern void intel_dp_check_link_status(struct intel_dp *intel_dp); | |
5bfe2ac0 DV |
518 | extern bool intel_dp_compute_config(struct intel_encoder *encoder, |
519 | struct intel_crtc_config *pipe_config); | |
cb0953d7 | 520 | extern bool intel_dpd_is_edp(struct drm_device *dev); |
d6c50ff8 PZ |
521 | extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp); |
522 | extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp); | |
82a4d9c0 PZ |
523 | extern void ironlake_edp_panel_on(struct intel_dp *intel_dp); |
524 | extern void ironlake_edp_panel_off(struct intel_dp *intel_dp); | |
525 | extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); | |
526 | extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); | |
814948ad | 527 | extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder); |
7f1f3851 | 528 | extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); |
6f1d69b0 ED |
529 | extern void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
530 | enum plane plane); | |
32f9d658 | 531 | |
a9573556 | 532 | /* intel_panel.c */ |
dd06f90e JN |
533 | extern int intel_panel_init(struct intel_panel *panel, |
534 | struct drm_display_mode *fixed_mode); | |
1d508706 JN |
535 | extern void intel_panel_fini(struct intel_panel *panel); |
536 | ||
1d8e1c75 CW |
537 | extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, |
538 | struct drm_display_mode *adjusted_mode); | |
539 | extern void intel_pch_panel_fitting(struct drm_device *dev, | |
540 | int fitting_mode, | |
cb1793ce | 541 | const struct drm_display_mode *mode, |
1d8e1c75 | 542 | struct drm_display_mode *adjusted_mode); |
a9573556 | 543 | extern u32 intel_panel_get_max_backlight(struct drm_device *dev); |
a9573556 | 544 | extern void intel_panel_set_backlight(struct drm_device *dev, u32 level); |
0657b6b1 | 545 | extern int intel_panel_setup_backlight(struct drm_connector *connector); |
24ded204 DV |
546 | extern void intel_panel_enable_backlight(struct drm_device *dev, |
547 | enum pipe pipe); | |
47356eb6 | 548 | extern void intel_panel_disable_backlight(struct drm_device *dev); |
aaa6fd2a | 549 | extern void intel_panel_destroy_backlight(struct drm_device *dev); |
fe16d949 | 550 | extern enum drm_connector_status intel_panel_detect(struct drm_device *dev); |
1d8e1c75 | 551 | |
d9e55608 | 552 | struct intel_set_config { |
1aa4b628 DV |
553 | struct drm_encoder **save_connector_encoders; |
554 | struct drm_crtc **save_encoder_crtcs; | |
5e2b584e DV |
555 | |
556 | bool fb_changed; | |
557 | bool mode_changed; | |
d9e55608 DV |
558 | }; |
559 | ||
c0c36b94 CW |
560 | extern int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
561 | int x, int y, struct drm_framebuffer *old_fb); | |
a261b246 | 562 | extern void intel_modeset_disable(struct drm_device *dev); |
c0c36b94 | 563 | extern void intel_crtc_restore_mode(struct drm_crtc *crtc); |
79e53945 | 564 | extern void intel_crtc_load_lut(struct drm_crtc *crtc); |
b2cabb0e | 565 | extern void intel_crtc_update_dpms(struct drm_crtc *crtc); |
ea5b213a | 566 | extern void intel_encoder_destroy(struct drm_encoder *encoder); |
5ab432ef | 567 | extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode); |
6ed0f796 | 568 | extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder); |
5ab432ef | 569 | extern void intel_connector_dpms(struct drm_connector *, int mode); |
f0947c37 | 570 | extern bool intel_connector_get_hw_state(struct intel_connector *connector); |
b980514c | 571 | extern void intel_modeset_check_state(struct drm_device *dev); |
5e1bac2f | 572 | extern void intel_plane_restore(struct drm_plane *plane); |
b980514c | 573 | |
79e53945 | 574 | |
df0e9248 CW |
575 | static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector) |
576 | { | |
577 | return to_intel_connector(connector)->encoder; | |
578 | } | |
579 | ||
7739c33b PZ |
580 | static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
581 | { | |
da63a9f2 PZ |
582 | struct intel_digital_port *intel_dig_port = |
583 | container_of(encoder, struct intel_digital_port, base.base); | |
584 | return &intel_dig_port->dp; | |
585 | } | |
586 | ||
587 | static inline struct intel_digital_port * | |
588 | enc_to_dig_port(struct drm_encoder *encoder) | |
589 | { | |
590 | return container_of(encoder, struct intel_digital_port, base.base); | |
591 | } | |
592 | ||
593 | static inline struct intel_digital_port * | |
594 | dp_to_dig_port(struct intel_dp *intel_dp) | |
595 | { | |
596 | return container_of(intel_dp, struct intel_digital_port, dp); | |
597 | } | |
598 | ||
599 | static inline struct intel_digital_port * | |
600 | hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) | |
601 | { | |
602 | return container_of(intel_hdmi, struct intel_digital_port, hdmi); | |
7739c33b PZ |
603 | } |
604 | ||
b0ea7d37 DL |
605 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
606 | struct intel_digital_port *port); | |
607 | ||
df0e9248 CW |
608 | extern void intel_connector_attach_encoder(struct intel_connector *connector, |
609 | struct intel_encoder *encoder); | |
610 | extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector); | |
79e53945 JB |
611 | |
612 | extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
613 | struct drm_crtc *crtc); | |
08d7b3d1 CW |
614 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
615 | struct drm_file *file_priv); | |
a5c961d1 PZ |
616 | extern enum transcoder |
617 | intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, | |
618 | enum pipe pipe); | |
9d0498a2 | 619 | extern void intel_wait_for_vblank(struct drm_device *dev, int pipe); |
58e10eb9 | 620 | extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe); |
d4b1931c | 621 | extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); |
89b667f8 | 622 | extern void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port); |
8261b191 CW |
623 | |
624 | struct intel_load_detect_pipe { | |
d2dff872 | 625 | struct drm_framebuffer *release_fb; |
8261b191 CW |
626 | bool load_detect_temp; |
627 | int dpms_mode; | |
628 | }; | |
d2434ab7 | 629 | extern bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 630 | struct drm_display_mode *mode, |
8261b191 | 631 | struct intel_load_detect_pipe *old); |
d2434ab7 | 632 | extern void intel_release_load_detect_pipe(struct drm_connector *connector, |
8261b191 | 633 | struct intel_load_detect_pipe *old); |
79e53945 | 634 | |
79e53945 JB |
635 | extern void intelfb_restore(void); |
636 | extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
637 | u16 blue, int regno); | |
b8c00ac5 DA |
638 | extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
639 | u16 *blue, int regno); | |
0cdab21f | 640 | extern void intel_enable_clock_gating(struct drm_device *dev); |
79e53945 | 641 | |
127bd2ac | 642 | extern int intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 643 | struct drm_i915_gem_object *obj, |
919926ae | 644 | struct intel_ring_buffer *pipelined); |
1690e1eb | 645 | extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj); |
127bd2ac | 646 | |
38651674 DA |
647 | extern int intel_framebuffer_init(struct drm_device *dev, |
648 | struct intel_framebuffer *ifb, | |
308e5bcb | 649 | struct drm_mode_fb_cmd2 *mode_cmd, |
05394f39 | 650 | struct drm_i915_gem_object *obj); |
38651674 | 651 | extern int intel_fbdev_init(struct drm_device *dev); |
20afbda2 | 652 | extern void intel_fbdev_initial_config(struct drm_device *dev); |
38651674 | 653 | extern void intel_fbdev_fini(struct drm_device *dev); |
3fa016a0 | 654 | extern void intel_fbdev_set_suspend(struct drm_device *dev, int state); |
6b95a207 KH |
655 | extern void intel_prepare_page_flip(struct drm_device *dev, int plane); |
656 | extern void intel_finish_page_flip(struct drm_device *dev, int pipe); | |
1afe3e9d | 657 | extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane); |
6b95a207 | 658 | |
02e792fb DV |
659 | extern void intel_setup_overlay(struct drm_device *dev); |
660 | extern void intel_cleanup_overlay(struct drm_device *dev); | |
ce453d81 | 661 | extern int intel_overlay_switch_off(struct intel_overlay *overlay); |
02e792fb DV |
662 | extern int intel_overlay_put_image(struct drm_device *dev, void *data, |
663 | struct drm_file *file_priv); | |
664 | extern int intel_overlay_attrs(struct drm_device *dev, void *data, | |
665 | struct drm_file *file_priv); | |
4abe3520 | 666 | |
eb1f8e4f | 667 | extern void intel_fb_output_poll_changed(struct drm_device *dev); |
e8e7a2b8 | 668 | extern void intel_fb_restore_mode(struct drm_device *dev); |
645c62a5 | 669 | |
b840d907 JB |
670 | extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
671 | bool state); | |
672 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) | |
673 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) | |
674 | ||
645c62a5 | 675 | extern void intel_init_clock_gating(struct drm_device *dev); |
e0dac65e WF |
676 | extern void intel_write_eld(struct drm_encoder *encoder, |
677 | struct drm_display_mode *mode); | |
d4270e57 | 678 | extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe); |
6cf86a5e DV |
679 | extern void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
680 | struct intel_link_m_n *m_n); | |
681 | extern void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, | |
682 | struct intel_link_m_n *m_n); | |
45244b87 | 683 | extern void intel_prepare_ddi(struct drm_device *dev); |
c82e4d26 | 684 | extern void hsw_fdi_link_train(struct drm_crtc *crtc); |
0e72a5b5 | 685 | extern void intel_ddi_init(struct drm_device *dev, enum port port); |
d4270e57 | 686 | |
b840d907 | 687 | /* For use by IVB LP watermark workaround in intel_sprite.c */ |
f681fa23 | 688 | extern void intel_update_watermarks(struct drm_device *dev); |
b840d907 JB |
689 | extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, |
690 | uint32_t sprite_width, | |
691 | int pixel_size); | |
1f8eeabf ED |
692 | extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe, |
693 | struct drm_display_mode *mode); | |
8ea30864 | 694 | |
bc752862 CW |
695 | extern unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
696 | unsigned int tiling_mode, | |
697 | unsigned int bpp, | |
698 | unsigned int pitch); | |
5a35e99e | 699 | |
8ea30864 JB |
700 | extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
701 | struct drm_file *file_priv); | |
702 | extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data, | |
703 | struct drm_file *file_priv); | |
704 | ||
57f350b6 | 705 | extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg); |
e2fa6fba P |
706 | extern void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, |
707 | u32 val); | |
57f350b6 | 708 | |
85208be0 | 709 | /* Power-related functions, located in intel_pm.c */ |
1fa61106 | 710 | extern void intel_init_pm(struct drm_device *dev); |
85208be0 | 711 | /* FBC */ |
85208be0 ED |
712 | extern bool intel_fbc_enabled(struct drm_device *dev); |
713 | extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval); | |
714 | extern void intel_update_fbc(struct drm_device *dev); | |
eb48eb00 DV |
715 | /* IPS */ |
716 | extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv); | |
717 | extern void intel_gpu_ips_teardown(void); | |
85208be0 | 718 | |
15d199ea | 719 | extern bool intel_using_power_well(struct drm_device *dev); |
fa42e23c | 720 | extern void intel_init_power_well(struct drm_device *dev); |
cb10799c | 721 | extern void intel_set_power_well(struct drm_device *dev, bool enable); |
8090c6b9 DV |
722 | extern void intel_enable_gt_powersave(struct drm_device *dev); |
723 | extern void intel_disable_gt_powersave(struct drm_device *dev); | |
6590190d | 724 | extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv); |
930ebb46 | 725 | extern void ironlake_teardown_rc6(struct drm_device *dev); |
b3daeaef | 726 | |
85234cdc DV |
727 | extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
728 | enum pipe *pipe); | |
b8fc2f6a | 729 | extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv); |
79f689aa | 730 | extern void intel_ddi_pll_init(struct drm_device *dev); |
8228c251 | 731 | extern void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc); |
ad80a810 PZ |
732 | extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
733 | enum transcoder cpu_transcoder); | |
fc914639 PZ |
734 | extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); |
735 | extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); | |
6441ab5f PZ |
736 | extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev); |
737 | extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock); | |
6441ab5f | 738 | extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc); |
dae84799 | 739 | extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); |
c19b0669 | 740 | extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder); |
1ad960f2 PZ |
741 | extern bool |
742 | intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); | |
743 | extern void intel_ddi_fdi_disable(struct drm_crtc *crtc); | |
72662e10 | 744 | |
96a02917 VS |
745 | extern void intel_display_handle_reset(struct drm_device *dev); |
746 | ||
79e53945 | 747 | #endif /* __INTEL_DRV_H__ */ |