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79e53945 JB |
1 | /* |
2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright (c) 2007-2008 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
23 | * IN THE SOFTWARE. | |
24 | */ | |
25 | #ifndef __INTEL_DRV_H__ | |
26 | #define __INTEL_DRV_H__ | |
27 | ||
28 | #include <linux/i2c.h> | |
80824003 | 29 | #include "i915_drv.h" |
79e53945 | 30 | #include "drm_crtc.h" |
79e53945 | 31 | #include "drm_crtc_helper.h" |
37811fcc | 32 | #include "drm_fb_helper.h" |
913d8d11 | 33 | |
481b6af3 | 34 | #define _wait_for(COND, MS, W) ({ \ |
913d8d11 CW |
35 | unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \ |
36 | int ret__ = 0; \ | |
37 | while (! (COND)) { \ | |
38 | if (time_after(jiffies, timeout__)) { \ | |
39 | ret__ = -ETIMEDOUT; \ | |
40 | break; \ | |
41 | } \ | |
82d7c9e7 | 42 | if (W && !in_dbg_master()) msleep(W); \ |
913d8d11 CW |
43 | } \ |
44 | ret__; \ | |
45 | }) | |
46 | ||
481b6af3 CW |
47 | #define wait_for(COND, MS) _wait_for(COND, MS, 1) |
48 | #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) | |
49 | ||
ec5da01e CW |
50 | #define MSLEEP(x) do { \ |
51 | if (in_dbg_master()) \ | |
52 | mdelay(x); \ | |
53 | else \ | |
54 | msleep(x); \ | |
55 | } while(0) | |
56 | ||
021357ac CW |
57 | #define KHz(x) (1000*x) |
58 | #define MHz(x) KHz(1000*x) | |
59 | ||
79e53945 JB |
60 | /* |
61 | * Display related stuff | |
62 | */ | |
63 | ||
64 | /* store information about an Ixxx DVO */ | |
65 | /* The i830->i865 use multiple DVOs with multiple i2cs */ | |
66 | /* the i915, i945 have a single sDVO i2c bus - which is different */ | |
67 | #define MAX_OUTPUTS 6 | |
68 | /* maximum connectors per crtcs in the mode set */ | |
69 | #define INTELFB_CONN_LIMIT 4 | |
70 | ||
71 | #define INTEL_I2C_BUS_DVO 1 | |
72 | #define INTEL_I2C_BUS_SDVO 2 | |
73 | ||
74 | /* these are outputs from the chip - integrated only | |
75 | external chips are via DVO or SDVO output */ | |
76 | #define INTEL_OUTPUT_UNUSED 0 | |
77 | #define INTEL_OUTPUT_ANALOG 1 | |
78 | #define INTEL_OUTPUT_DVO 2 | |
79 | #define INTEL_OUTPUT_SDVO 3 | |
80 | #define INTEL_OUTPUT_LVDS 4 | |
81 | #define INTEL_OUTPUT_TVOUT 5 | |
7d57382e | 82 | #define INTEL_OUTPUT_HDMI 6 |
a4fc5ed6 | 83 | #define INTEL_OUTPUT_DISPLAYPORT 7 |
32f9d658 | 84 | #define INTEL_OUTPUT_EDP 8 |
79e53945 | 85 | |
f8aed700 ML |
86 | /* Intel Pipe Clone Bit */ |
87 | #define INTEL_HDMIB_CLONE_BIT 1 | |
88 | #define INTEL_HDMIC_CLONE_BIT 2 | |
89 | #define INTEL_HDMID_CLONE_BIT 3 | |
90 | #define INTEL_HDMIE_CLONE_BIT 4 | |
91 | #define INTEL_HDMIF_CLONE_BIT 5 | |
92 | #define INTEL_SDVO_NON_TV_CLONE_BIT 6 | |
93 | #define INTEL_SDVO_TV_CLONE_BIT 7 | |
94 | #define INTEL_SDVO_LVDS_CLONE_BIT 8 | |
95 | #define INTEL_ANALOG_CLONE_BIT 9 | |
96 | #define INTEL_TV_CLONE_BIT 10 | |
97 | #define INTEL_DP_B_CLONE_BIT 11 | |
98 | #define INTEL_DP_C_CLONE_BIT 12 | |
99 | #define INTEL_DP_D_CLONE_BIT 13 | |
100 | #define INTEL_LVDS_CLONE_BIT 14 | |
101 | #define INTEL_DVO_TMDS_CLONE_BIT 15 | |
102 | #define INTEL_DVO_LVDS_CLONE_BIT 16 | |
7c8460db | 103 | #define INTEL_EDP_CLONE_BIT 17 |
f8aed700 | 104 | |
79e53945 JB |
105 | #define INTEL_DVO_CHIP_NONE 0 |
106 | #define INTEL_DVO_CHIP_LVDS 1 | |
107 | #define INTEL_DVO_CHIP_TMDS 2 | |
108 | #define INTEL_DVO_CHIP_TVOUT 4 | |
109 | ||
6c9547ff CW |
110 | /* drm_display_mode->private_flags */ |
111 | #define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0) | |
112 | #define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT) | |
113 | ||
114 | static inline void | |
115 | intel_mode_set_pixel_multiplier(struct drm_display_mode *mode, | |
116 | int multiplier) | |
117 | { | |
118 | mode->clock *= multiplier; | |
119 | mode->private_flags |= multiplier; | |
120 | } | |
121 | ||
122 | static inline int | |
123 | intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode) | |
124 | { | |
125 | return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT; | |
126 | } | |
127 | ||
79e53945 JB |
128 | struct intel_framebuffer { |
129 | struct drm_framebuffer base; | |
130 | struct drm_gem_object *obj; | |
131 | }; | |
132 | ||
37811fcc CW |
133 | struct intel_fbdev { |
134 | struct drm_fb_helper helper; | |
135 | struct intel_framebuffer ifb; | |
136 | struct list_head fbdev_list; | |
137 | struct drm_display_mode *our_mode; | |
138 | }; | |
79e53945 | 139 | |
21d40d37 | 140 | struct intel_encoder { |
4ef69c7a | 141 | struct drm_encoder base; |
79e53945 | 142 | int type; |
79e53945 | 143 | bool load_detect_temp; |
e2f0ba97 | 144 | bool needs_tv_clock; |
21d40d37 | 145 | void (*hot_plug)(struct intel_encoder *); |
f8aed700 ML |
146 | int crtc_mask; |
147 | int clone_mask; | |
79e53945 JB |
148 | }; |
149 | ||
5daa55eb ZW |
150 | struct intel_connector { |
151 | struct drm_connector base; | |
df0e9248 | 152 | struct intel_encoder *encoder; |
5daa55eb ZW |
153 | }; |
154 | ||
79e53945 JB |
155 | struct intel_crtc { |
156 | struct drm_crtc base; | |
80824003 JB |
157 | enum pipe pipe; |
158 | enum plane plane; | |
79e53945 JB |
159 | u8 lut_r[256], lut_g[256], lut_b[256]; |
160 | int dpms_mode; | |
f7abfe8b | 161 | bool active; /* is the crtc on? independent of the dpms mode */ |
652c393a JB |
162 | bool busy; /* is scanout buffer being updated frequently? */ |
163 | struct timer_list idle_timer; | |
164 | bool lowfreq_avail; | |
02e792fb | 165 | struct intel_overlay *overlay; |
6b95a207 | 166 | struct intel_unpin_work *unpin_work; |
77ffb597 | 167 | int fdi_lanes; |
cda4b7d3 CW |
168 | |
169 | struct drm_gem_object *cursor_bo; | |
170 | uint32_t cursor_addr; | |
171 | int16_t cursor_x, cursor_y; | |
172 | int16_t cursor_width, cursor_height; | |
6b383a7f | 173 | bool cursor_visible; |
79e53945 JB |
174 | }; |
175 | ||
176 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) | |
5daa55eb | 177 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
4ef69c7a | 178 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
79e53945 JB |
179 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
180 | ||
f875c15a CW |
181 | static inline struct drm_crtc * |
182 | intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) | |
183 | { | |
184 | struct drm_i915_private *dev_priv = dev->dev_private; | |
185 | return dev_priv->pipe_to_crtc_mapping[pipe]; | |
186 | } | |
187 | ||
4e5359cd SF |
188 | struct intel_unpin_work { |
189 | struct work_struct work; | |
190 | struct drm_device *dev; | |
191 | struct drm_gem_object *old_fb_obj; | |
192 | struct drm_gem_object *pending_flip_obj; | |
193 | struct drm_pending_vblank_event *event; | |
194 | int pending; | |
195 | bool enable_stall_check; | |
196 | }; | |
197 | ||
335af9a2 | 198 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); |
f899fc64 | 199 | extern bool intel_ddc_probe(struct intel_encoder *intel_encoder, int ddc_bus); |
f0217c42 | 200 | |
79e53945 | 201 | extern void intel_crt_init(struct drm_device *dev); |
7d57382e EA |
202 | extern void intel_hdmi_init(struct drm_device *dev, int sdvox_reg); |
203 | extern bool intel_sdvo_init(struct drm_device *dev, int output_device); | |
79e53945 JB |
204 | extern void intel_dvo_init(struct drm_device *dev); |
205 | extern void intel_tv_init(struct drm_device *dev); | |
652c393a | 206 | extern void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj); |
79e53945 | 207 | extern void intel_lvds_init(struct drm_device *dev); |
a4fc5ed6 KP |
208 | extern void intel_dp_init(struct drm_device *dev, int dp_reg); |
209 | void | |
210 | intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, | |
211 | struct drm_display_mode *adjusted_mode); | |
36e83a18 | 212 | extern bool intel_pch_has_edp(struct drm_crtc *crtc); |
cb0953d7 | 213 | extern bool intel_dpd_is_edp(struct drm_device *dev); |
21d40d37 | 214 | extern void intel_edp_link_config (struct intel_encoder *, int *, int *); |
32f9d658 | 215 | |
a9573556 | 216 | /* intel_panel.c */ |
1d8e1c75 CW |
217 | extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, |
218 | struct drm_display_mode *adjusted_mode); | |
219 | extern void intel_pch_panel_fitting(struct drm_device *dev, | |
220 | int fitting_mode, | |
221 | struct drm_display_mode *mode, | |
222 | struct drm_display_mode *adjusted_mode); | |
a9573556 CW |
223 | extern u32 intel_panel_get_max_backlight(struct drm_device *dev); |
224 | extern u32 intel_panel_get_backlight(struct drm_device *dev); | |
225 | extern void intel_panel_set_backlight(struct drm_device *dev, u32 level); | |
1d8e1c75 | 226 | |
79e53945 JB |
227 | extern void intel_crtc_load_lut(struct drm_crtc *crtc); |
228 | extern void intel_encoder_prepare (struct drm_encoder *encoder); | |
229 | extern void intel_encoder_commit (struct drm_encoder *encoder); | |
ea5b213a | 230 | extern void intel_encoder_destroy(struct drm_encoder *encoder); |
79e53945 | 231 | |
df0e9248 CW |
232 | static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector) |
233 | { | |
234 | return to_intel_connector(connector)->encoder; | |
235 | } | |
236 | ||
237 | extern void intel_connector_attach_encoder(struct intel_connector *connector, | |
238 | struct intel_encoder *encoder); | |
239 | extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector); | |
79e53945 JB |
240 | |
241 | extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
242 | struct drm_crtc *crtc); | |
08d7b3d1 CW |
243 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
244 | struct drm_file *file_priv); | |
9d0498a2 JB |
245 | extern void intel_wait_for_vblank_off(struct drm_device *dev, int pipe); |
246 | extern void intel_wait_for_vblank(struct drm_device *dev, int pipe); | |
21d40d37 | 247 | extern struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, |
c1c43977 | 248 | struct drm_connector *connector, |
79e53945 JB |
249 | struct drm_display_mode *mode, |
250 | int *dpms_mode); | |
21d40d37 | 251 | extern void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, |
c1c43977 | 252 | struct drm_connector *connector, |
79e53945 JB |
253 | int dpms_mode); |
254 | ||
255 | extern struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB); | |
256 | extern int intel_sdvo_supports_hotplug(struct drm_connector *connector); | |
257 | extern void intel_sdvo_set_hotplug(struct drm_connector *connector, int enable); | |
79e53945 JB |
258 | extern void intelfb_restore(void); |
259 | extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
260 | u16 blue, int regno); | |
b8c00ac5 DA |
261 | extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
262 | u16 *blue, int regno); | |
7e8b60fa | 263 | extern void intel_init_clock_gating(struct drm_device *dev); |
f97108d1 JB |
264 | extern void ironlake_enable_drps(struct drm_device *dev); |
265 | extern void ironlake_disable_drps(struct drm_device *dev); | |
79e53945 | 266 | |
127bd2ac | 267 | extern int intel_pin_and_fence_fb_obj(struct drm_device *dev, |
48b956c5 CW |
268 | struct drm_gem_object *obj, |
269 | bool pipelined); | |
127bd2ac | 270 | |
38651674 DA |
271 | extern int intel_framebuffer_init(struct drm_device *dev, |
272 | struct intel_framebuffer *ifb, | |
273 | struct drm_mode_fb_cmd *mode_cmd, | |
274 | struct drm_gem_object *obj); | |
275 | extern int intel_fbdev_init(struct drm_device *dev); | |
276 | extern void intel_fbdev_fini(struct drm_device *dev); | |
28d52043 | 277 | |
6b95a207 KH |
278 | extern void intel_prepare_page_flip(struct drm_device *dev, int plane); |
279 | extern void intel_finish_page_flip(struct drm_device *dev, int pipe); | |
1afe3e9d | 280 | extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane); |
6b95a207 | 281 | |
02e792fb DV |
282 | extern void intel_setup_overlay(struct drm_device *dev); |
283 | extern void intel_cleanup_overlay(struct drm_device *dev); | |
5dcdbcb0 CW |
284 | extern int intel_overlay_switch_off(struct intel_overlay *overlay, |
285 | bool interruptible); | |
02e792fb DV |
286 | extern int intel_overlay_put_image(struct drm_device *dev, void *data, |
287 | struct drm_file *file_priv); | |
288 | extern int intel_overlay_attrs(struct drm_device *dev, void *data, | |
289 | struct drm_file *file_priv); | |
4abe3520 | 290 | |
eb1f8e4f | 291 | extern void intel_fb_output_poll_changed(struct drm_device *dev); |
79e53945 | 292 | #endif /* __INTEL_DRV_H__ */ |