Commit | Line | Data |
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79e53945 JB |
1 | /* |
2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright (c) 2007-2008 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
23 | * IN THE SOFTWARE. | |
24 | */ | |
25 | #ifndef __INTEL_DRV_H__ | |
26 | #define __INTEL_DRV_H__ | |
27 | ||
28 | #include <linux/i2c.h> | |
8ea30864 | 29 | #include "i915_drm.h" |
80824003 | 30 | #include "i915_drv.h" |
79e53945 | 31 | #include "drm_crtc.h" |
79e53945 | 32 | #include "drm_crtc_helper.h" |
37811fcc | 33 | #include "drm_fb_helper.h" |
54d63ca6 | 34 | #include "drm_dp_helper.h" |
913d8d11 | 35 | |
481b6af3 | 36 | #define _wait_for(COND, MS, W) ({ \ |
913d8d11 CW |
37 | unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \ |
38 | int ret__ = 0; \ | |
0206e353 | 39 | while (!(COND)) { \ |
913d8d11 CW |
40 | if (time_after(jiffies, timeout__)) { \ |
41 | ret__ = -ETIMEDOUT; \ | |
42 | break; \ | |
43 | } \ | |
cc1f7194 | 44 | if (W && drm_can_sleep()) msleep(W); \ |
913d8d11 CW |
45 | } \ |
46 | ret__; \ | |
47 | }) | |
48 | ||
57f350b6 | 49 | #define wait_for_atomic_us(COND, US) ({ \ |
bcf9dcc1 CW |
50 | unsigned long timeout__ = jiffies + usecs_to_jiffies(US); \ |
51 | int ret__ = 0; \ | |
52 | while (!(COND)) { \ | |
53 | if (time_after(jiffies, timeout__)) { \ | |
54 | ret__ = -ETIMEDOUT; \ | |
55 | break; \ | |
56 | } \ | |
57 | cpu_relax(); \ | |
58 | } \ | |
59 | ret__; \ | |
57f350b6 JB |
60 | }) |
61 | ||
481b6af3 CW |
62 | #define wait_for(COND, MS) _wait_for(COND, MS, 1) |
63 | #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) | |
64 | ||
021357ac CW |
65 | #define KHz(x) (1000*x) |
66 | #define MHz(x) KHz(1000*x) | |
67 | ||
79e53945 JB |
68 | /* |
69 | * Display related stuff | |
70 | */ | |
71 | ||
72 | /* store information about an Ixxx DVO */ | |
73 | /* The i830->i865 use multiple DVOs with multiple i2cs */ | |
74 | /* the i915, i945 have a single sDVO i2c bus - which is different */ | |
75 | #define MAX_OUTPUTS 6 | |
76 | /* maximum connectors per crtcs in the mode set */ | |
77 | #define INTELFB_CONN_LIMIT 4 | |
78 | ||
79 | #define INTEL_I2C_BUS_DVO 1 | |
80 | #define INTEL_I2C_BUS_SDVO 2 | |
81 | ||
82 | /* these are outputs from the chip - integrated only | |
83 | external chips are via DVO or SDVO output */ | |
84 | #define INTEL_OUTPUT_UNUSED 0 | |
85 | #define INTEL_OUTPUT_ANALOG 1 | |
86 | #define INTEL_OUTPUT_DVO 2 | |
87 | #define INTEL_OUTPUT_SDVO 3 | |
88 | #define INTEL_OUTPUT_LVDS 4 | |
89 | #define INTEL_OUTPUT_TVOUT 5 | |
7d57382e | 90 | #define INTEL_OUTPUT_HDMI 6 |
a4fc5ed6 | 91 | #define INTEL_OUTPUT_DISPLAYPORT 7 |
32f9d658 | 92 | #define INTEL_OUTPUT_EDP 8 |
79e53945 JB |
93 | |
94 | #define INTEL_DVO_CHIP_NONE 0 | |
95 | #define INTEL_DVO_CHIP_LVDS 1 | |
96 | #define INTEL_DVO_CHIP_TMDS 2 | |
97 | #define INTEL_DVO_CHIP_TVOUT 4 | |
98 | ||
6c9547ff CW |
99 | /* drm_display_mode->private_flags */ |
100 | #define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0) | |
101 | #define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT) | |
3b5c78a3 | 102 | #define INTEL_MODE_DP_FORCE_6BPC (0x10) |
f9bef081 DV |
103 | /* This flag must be set by the encoder's mode_fixup if it changes the crtc |
104 | * timings in the mode to prevent the crtc fixup from overwriting them. | |
105 | * Currently only lvds needs that. */ | |
106 | #define INTEL_MODE_CRTC_TIMINGS_SET (0x20) | |
6c9547ff CW |
107 | |
108 | static inline void | |
109 | intel_mode_set_pixel_multiplier(struct drm_display_mode *mode, | |
110 | int multiplier) | |
111 | { | |
112 | mode->clock *= multiplier; | |
113 | mode->private_flags |= multiplier; | |
114 | } | |
115 | ||
116 | static inline int | |
117 | intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode) | |
118 | { | |
119 | return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT; | |
120 | } | |
121 | ||
79e53945 JB |
122 | struct intel_framebuffer { |
123 | struct drm_framebuffer base; | |
05394f39 | 124 | struct drm_i915_gem_object *obj; |
79e53945 JB |
125 | }; |
126 | ||
37811fcc CW |
127 | struct intel_fbdev { |
128 | struct drm_fb_helper helper; | |
129 | struct intel_framebuffer ifb; | |
130 | struct list_head fbdev_list; | |
131 | struct drm_display_mode *our_mode; | |
132 | }; | |
79e53945 | 133 | |
21d40d37 | 134 | struct intel_encoder { |
4ef69c7a | 135 | struct drm_encoder base; |
79e53945 | 136 | int type; |
e2f0ba97 | 137 | bool needs_tv_clock; |
66a9278e DV |
138 | /* |
139 | * Intel hw has only one MUX where encoders could be clone, hence a | |
140 | * simple flag is enough to compute the possible_clones mask. | |
141 | */ | |
142 | bool cloneable; | |
5ab432ef | 143 | bool connectors_active; |
21d40d37 | 144 | void (*hot_plug)(struct intel_encoder *); |
ef9c3aee DV |
145 | void (*enable)(struct intel_encoder *); |
146 | void (*disable)(struct intel_encoder *); | |
f8aed700 | 147 | int crtc_mask; |
79e53945 JB |
148 | }; |
149 | ||
5daa55eb ZW |
150 | struct intel_connector { |
151 | struct drm_connector base; | |
df0e9248 | 152 | struct intel_encoder *encoder; |
5daa55eb ZW |
153 | }; |
154 | ||
79e53945 JB |
155 | struct intel_crtc { |
156 | struct drm_crtc base; | |
80824003 JB |
157 | enum pipe pipe; |
158 | enum plane plane; | |
79e53945 JB |
159 | u8 lut_r[256], lut_g[256], lut_b[256]; |
160 | int dpms_mode; | |
f7abfe8b | 161 | bool active; /* is the crtc on? independent of the dpms mode */ |
93314b5b | 162 | bool primary_disabled; /* is the crtc obscured by a plane? */ |
652c393a | 163 | bool lowfreq_avail; |
02e792fb | 164 | struct intel_overlay *overlay; |
6b95a207 | 165 | struct intel_unpin_work *unpin_work; |
77ffb597 | 166 | int fdi_lanes; |
cda4b7d3 | 167 | |
e506a0c6 DV |
168 | /* Display surface base address adjustement for pageflips. Note that on |
169 | * gen4+ this only adjusts up to a tile, offsets within a tile are | |
170 | * handled in the hw itself (with the TILEOFF register). */ | |
171 | unsigned long dspaddr_offset; | |
172 | ||
05394f39 | 173 | struct drm_i915_gem_object *cursor_bo; |
cda4b7d3 CW |
174 | uint32_t cursor_addr; |
175 | int16_t cursor_x, cursor_y; | |
176 | int16_t cursor_width, cursor_height; | |
6b383a7f | 177 | bool cursor_visible; |
5a354204 | 178 | unsigned int bpp; |
4b645f14 | 179 | |
ee7b9f93 JB |
180 | /* We can share PLLs across outputs if the timings match */ |
181 | struct intel_pch_pll *pch_pll; | |
79e53945 JB |
182 | }; |
183 | ||
b840d907 JB |
184 | struct intel_plane { |
185 | struct drm_plane base; | |
186 | enum pipe pipe; | |
187 | struct drm_i915_gem_object *obj; | |
188 | int max_downscale; | |
189 | u32 lut_r[1024], lut_g[1024], lut_b[1024]; | |
190 | void (*update_plane)(struct drm_plane *plane, | |
191 | struct drm_framebuffer *fb, | |
192 | struct drm_i915_gem_object *obj, | |
193 | int crtc_x, int crtc_y, | |
194 | unsigned int crtc_w, unsigned int crtc_h, | |
195 | uint32_t x, uint32_t y, | |
196 | uint32_t src_w, uint32_t src_h); | |
197 | void (*disable_plane)(struct drm_plane *plane); | |
8ea30864 JB |
198 | int (*update_colorkey)(struct drm_plane *plane, |
199 | struct drm_intel_sprite_colorkey *key); | |
200 | void (*get_colorkey)(struct drm_plane *plane, | |
201 | struct drm_intel_sprite_colorkey *key); | |
b840d907 JB |
202 | }; |
203 | ||
b445e3b0 ED |
204 | struct intel_watermark_params { |
205 | unsigned long fifo_size; | |
206 | unsigned long max_wm; | |
207 | unsigned long default_wm; | |
208 | unsigned long guard_size; | |
209 | unsigned long cacheline_size; | |
210 | }; | |
211 | ||
212 | struct cxsr_latency { | |
213 | int is_desktop; | |
214 | int is_ddr3; | |
215 | unsigned long fsb_freq; | |
216 | unsigned long mem_freq; | |
217 | unsigned long display_sr; | |
218 | unsigned long display_hpll_disable; | |
219 | unsigned long cursor_sr; | |
220 | unsigned long cursor_hpll_disable; | |
221 | }; | |
222 | ||
79e53945 | 223 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
5daa55eb | 224 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
4ef69c7a | 225 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
79e53945 | 226 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
b840d907 | 227 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
79e53945 | 228 | |
45187ace JB |
229 | #define DIP_HEADER_SIZE 5 |
230 | ||
3c17fe4b DH |
231 | #define DIP_TYPE_AVI 0x82 |
232 | #define DIP_VERSION_AVI 0x2 | |
233 | #define DIP_LEN_AVI 13 | |
c846b619 PZ |
234 | #define DIP_AVI_PR_1 0 |
235 | #define DIP_AVI_PR_2 1 | |
3c17fe4b | 236 | |
26005210 | 237 | #define DIP_TYPE_SPD 0x83 |
c0864cb3 JB |
238 | #define DIP_VERSION_SPD 0x1 |
239 | #define DIP_LEN_SPD 25 | |
240 | #define DIP_SPD_UNKNOWN 0 | |
241 | #define DIP_SPD_DSTB 0x1 | |
242 | #define DIP_SPD_DVDP 0x2 | |
243 | #define DIP_SPD_DVHS 0x3 | |
244 | #define DIP_SPD_HDDVR 0x4 | |
245 | #define DIP_SPD_DVC 0x5 | |
246 | #define DIP_SPD_DSC 0x6 | |
247 | #define DIP_SPD_VCD 0x7 | |
248 | #define DIP_SPD_GAME 0x8 | |
249 | #define DIP_SPD_PC 0x9 | |
250 | #define DIP_SPD_BD 0xa | |
251 | #define DIP_SPD_SCD 0xb | |
252 | ||
3c17fe4b DH |
253 | struct dip_infoframe { |
254 | uint8_t type; /* HB0 */ | |
255 | uint8_t ver; /* HB1 */ | |
256 | uint8_t len; /* HB2 - body len, not including checksum */ | |
257 | uint8_t ecc; /* Header ECC */ | |
258 | uint8_t checksum; /* PB0 */ | |
259 | union { | |
260 | struct { | |
261 | /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */ | |
262 | uint8_t Y_A_B_S; | |
263 | /* PB2 - C 7:6, M 5:4, R 3:0 */ | |
264 | uint8_t C_M_R; | |
265 | /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */ | |
266 | uint8_t ITC_EC_Q_SC; | |
267 | /* PB4 - VIC 6:0 */ | |
268 | uint8_t VIC; | |
0aa534df PZ |
269 | /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */ |
270 | uint8_t YQ_CN_PR; | |
3c17fe4b DH |
271 | /* PB6 to PB13 */ |
272 | uint16_t top_bar_end; | |
273 | uint16_t bottom_bar_start; | |
274 | uint16_t left_bar_end; | |
275 | uint16_t right_bar_start; | |
81014b9d | 276 | } __attribute__ ((packed)) avi; |
c0864cb3 JB |
277 | struct { |
278 | uint8_t vn[8]; | |
279 | uint8_t pd[16]; | |
280 | uint8_t sdi; | |
81014b9d | 281 | } __attribute__ ((packed)) spd; |
3c17fe4b DH |
282 | uint8_t payload[27]; |
283 | } __attribute__ ((packed)) body; | |
284 | } __attribute__((packed)); | |
285 | ||
f5bbfca3 ED |
286 | struct intel_hdmi { |
287 | struct intel_encoder base; | |
288 | u32 sdvox_reg; | |
289 | int ddc_bus; | |
290 | int ddi_port; | |
291 | uint32_t color_range; | |
292 | bool has_hdmi_sink; | |
293 | bool has_audio; | |
294 | enum hdmi_force_audio force_audio; | |
295 | void (*write_infoframe)(struct drm_encoder *encoder, | |
296 | struct dip_infoframe *frame); | |
687f4d06 PZ |
297 | void (*set_infoframes)(struct drm_encoder *encoder, |
298 | struct drm_display_mode *adjusted_mode); | |
f5bbfca3 ED |
299 | }; |
300 | ||
54d63ca6 SK |
301 | #define DP_RECEIVER_CAP_SIZE 0xf |
302 | #define DP_LINK_CONFIGURATION_SIZE 9 | |
303 | ||
304 | struct intel_dp { | |
305 | struct intel_encoder base; | |
306 | uint32_t output_reg; | |
307 | uint32_t DP; | |
308 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; | |
309 | bool has_audio; | |
310 | enum hdmi_force_audio force_audio; | |
ab9d7c30 | 311 | enum port port; |
54d63ca6 SK |
312 | uint32_t color_range; |
313 | int dpms_mode; | |
314 | uint8_t link_bw; | |
315 | uint8_t lane_count; | |
316 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; | |
317 | struct i2c_adapter adapter; | |
318 | struct i2c_algo_dp_aux_data algo; | |
319 | bool is_pch_edp; | |
320 | uint8_t train_set[4]; | |
321 | int panel_power_up_delay; | |
322 | int panel_power_down_delay; | |
323 | int panel_power_cycle_delay; | |
324 | int backlight_on_delay; | |
325 | int backlight_off_delay; | |
326 | struct drm_display_mode *panel_fixed_mode; /* for eDP */ | |
327 | struct delayed_work panel_vdd_work; | |
328 | bool want_panel_vdd; | |
329 | struct edid *edid; /* cached EDID for eDP */ | |
330 | int edid_mode_count; | |
331 | }; | |
332 | ||
f875c15a CW |
333 | static inline struct drm_crtc * |
334 | intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) | |
335 | { | |
336 | struct drm_i915_private *dev_priv = dev->dev_private; | |
337 | return dev_priv->pipe_to_crtc_mapping[pipe]; | |
338 | } | |
339 | ||
417ae147 CW |
340 | static inline struct drm_crtc * |
341 | intel_get_crtc_for_plane(struct drm_device *dev, int plane) | |
342 | { | |
343 | struct drm_i915_private *dev_priv = dev->dev_private; | |
344 | return dev_priv->plane_to_crtc_mapping[plane]; | |
345 | } | |
346 | ||
4e5359cd SF |
347 | struct intel_unpin_work { |
348 | struct work_struct work; | |
349 | struct drm_device *dev; | |
05394f39 CW |
350 | struct drm_i915_gem_object *old_fb_obj; |
351 | struct drm_i915_gem_object *pending_flip_obj; | |
4e5359cd SF |
352 | struct drm_pending_vblank_event *event; |
353 | int pending; | |
354 | bool enable_stall_check; | |
355 | }; | |
356 | ||
1630fe75 CW |
357 | struct intel_fbc_work { |
358 | struct delayed_work work; | |
359 | struct drm_crtc *crtc; | |
360 | struct drm_framebuffer *fb; | |
361 | int interval; | |
362 | }; | |
363 | ||
335af9a2 | 364 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); |
f0217c42 | 365 | |
3f43c48d | 366 | extern void intel_attach_force_audio_property(struct drm_connector *connector); |
e953fd7b CW |
367 | extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector); |
368 | ||
79e53945 | 369 | extern void intel_crt_init(struct drm_device *dev); |
08d644ad DV |
370 | extern void intel_hdmi_init(struct drm_device *dev, |
371 | int sdvox_reg, enum port port); | |
f5bbfca3 | 372 | extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); |
f5bbfca3 | 373 | extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if); |
eef4eacb DV |
374 | extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, |
375 | bool is_sdvob); | |
79e53945 JB |
376 | extern void intel_dvo_init(struct drm_device *dev); |
377 | extern void intel_tv_init(struct drm_device *dev); | |
f047e395 CW |
378 | extern void intel_mark_busy(struct drm_device *dev); |
379 | extern void intel_mark_idle(struct drm_device *dev); | |
380 | extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj); | |
381 | extern void intel_mark_fb_idle(struct drm_i915_gem_object *obj); | |
c5d1b51d | 382 | extern bool intel_lvds_init(struct drm_device *dev); |
ab9d7c30 PZ |
383 | extern void intel_dp_init(struct drm_device *dev, int output_reg, |
384 | enum port port); | |
a4fc5ed6 KP |
385 | void |
386 | intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, | |
387 | struct drm_display_mode *adjusted_mode); | |
cb0953d7 | 388 | extern bool intel_dpd_is_edp(struct drm_device *dev); |
0206e353 | 389 | extern void intel_edp_link_config(struct intel_encoder *, int *, int *); |
94bf2ced DV |
390 | extern int intel_edp_target_clock(struct intel_encoder *, |
391 | struct drm_display_mode *mode); | |
814948ad | 392 | extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder); |
b840d907 | 393 | extern int intel_plane_init(struct drm_device *dev, enum pipe pipe); |
6f1d69b0 ED |
394 | extern void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
395 | enum plane plane); | |
32f9d658 | 396 | |
a9573556 | 397 | /* intel_panel.c */ |
1d8e1c75 CW |
398 | extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, |
399 | struct drm_display_mode *adjusted_mode); | |
400 | extern void intel_pch_panel_fitting(struct drm_device *dev, | |
401 | int fitting_mode, | |
cb1793ce | 402 | const struct drm_display_mode *mode, |
1d8e1c75 | 403 | struct drm_display_mode *adjusted_mode); |
a9573556 | 404 | extern u32 intel_panel_get_max_backlight(struct drm_device *dev); |
a9573556 | 405 | extern void intel_panel_set_backlight(struct drm_device *dev, u32 level); |
aaa6fd2a | 406 | extern int intel_panel_setup_backlight(struct drm_device *dev); |
24ded204 DV |
407 | extern void intel_panel_enable_backlight(struct drm_device *dev, |
408 | enum pipe pipe); | |
47356eb6 | 409 | extern void intel_panel_disable_backlight(struct drm_device *dev); |
aaa6fd2a | 410 | extern void intel_panel_destroy_backlight(struct drm_device *dev); |
fe16d949 | 411 | extern enum drm_connector_status intel_panel_detect(struct drm_device *dev); |
1d8e1c75 | 412 | |
79e53945 | 413 | extern void intel_crtc_load_lut(struct drm_crtc *crtc); |
0206e353 AJ |
414 | extern void intel_encoder_prepare(struct drm_encoder *encoder); |
415 | extern void intel_encoder_commit(struct drm_encoder *encoder); | |
5ab432ef DV |
416 | extern void intel_encoder_noop(struct drm_encoder *encoder); |
417 | extern void intel_encoder_disable(struct drm_encoder *encoder); | |
ea5b213a | 418 | extern void intel_encoder_destroy(struct drm_encoder *encoder); |
5ab432ef DV |
419 | extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode); |
420 | extern void intel_connector_dpms(struct drm_connector *, int mode); | |
79e53945 | 421 | |
df0e9248 CW |
422 | static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector) |
423 | { | |
424 | return to_intel_connector(connector)->encoder; | |
425 | } | |
426 | ||
427 | extern void intel_connector_attach_encoder(struct intel_connector *connector, | |
428 | struct intel_encoder *encoder); | |
429 | extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector); | |
79e53945 JB |
430 | |
431 | extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
432 | struct drm_crtc *crtc); | |
08d7b3d1 CW |
433 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
434 | struct drm_file *file_priv); | |
9d0498a2 | 435 | extern void intel_wait_for_vblank(struct drm_device *dev, int pipe); |
58e10eb9 | 436 | extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe); |
8261b191 CW |
437 | |
438 | struct intel_load_detect_pipe { | |
d2dff872 | 439 | struct drm_framebuffer *release_fb; |
8261b191 CW |
440 | bool load_detect_temp; |
441 | int dpms_mode; | |
442 | }; | |
d2434ab7 | 443 | extern bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 444 | struct drm_display_mode *mode, |
8261b191 | 445 | struct intel_load_detect_pipe *old); |
d2434ab7 | 446 | extern void intel_release_load_detect_pipe(struct drm_connector *connector, |
8261b191 | 447 | struct intel_load_detect_pipe *old); |
79e53945 | 448 | |
79e53945 JB |
449 | extern void intelfb_restore(void); |
450 | extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
451 | u16 blue, int regno); | |
b8c00ac5 DA |
452 | extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
453 | u16 *blue, int regno); | |
0cdab21f | 454 | extern void intel_enable_clock_gating(struct drm_device *dev); |
79e53945 | 455 | |
127bd2ac | 456 | extern int intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 457 | struct drm_i915_gem_object *obj, |
919926ae | 458 | struct intel_ring_buffer *pipelined); |
1690e1eb | 459 | extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj); |
127bd2ac | 460 | |
38651674 DA |
461 | extern int intel_framebuffer_init(struct drm_device *dev, |
462 | struct intel_framebuffer *ifb, | |
308e5bcb | 463 | struct drm_mode_fb_cmd2 *mode_cmd, |
05394f39 | 464 | struct drm_i915_gem_object *obj); |
38651674 DA |
465 | extern int intel_fbdev_init(struct drm_device *dev); |
466 | extern void intel_fbdev_fini(struct drm_device *dev); | |
3fa016a0 | 467 | extern void intel_fbdev_set_suspend(struct drm_device *dev, int state); |
6b95a207 KH |
468 | extern void intel_prepare_page_flip(struct drm_device *dev, int plane); |
469 | extern void intel_finish_page_flip(struct drm_device *dev, int pipe); | |
1afe3e9d | 470 | extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane); |
6b95a207 | 471 | |
02e792fb DV |
472 | extern void intel_setup_overlay(struct drm_device *dev); |
473 | extern void intel_cleanup_overlay(struct drm_device *dev); | |
ce453d81 | 474 | extern int intel_overlay_switch_off(struct intel_overlay *overlay); |
02e792fb DV |
475 | extern int intel_overlay_put_image(struct drm_device *dev, void *data, |
476 | struct drm_file *file_priv); | |
477 | extern int intel_overlay_attrs(struct drm_device *dev, void *data, | |
478 | struct drm_file *file_priv); | |
4abe3520 | 479 | |
eb1f8e4f | 480 | extern void intel_fb_output_poll_changed(struct drm_device *dev); |
e8e7a2b8 | 481 | extern void intel_fb_restore_mode(struct drm_device *dev); |
645c62a5 | 482 | |
b840d907 JB |
483 | extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
484 | bool state); | |
485 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) | |
486 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) | |
487 | ||
645c62a5 | 488 | extern void intel_init_clock_gating(struct drm_device *dev); |
e0dac65e WF |
489 | extern void intel_write_eld(struct drm_encoder *encoder, |
490 | struct drm_display_mode *mode); | |
d4270e57 | 491 | extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe); |
45244b87 | 492 | extern void intel_prepare_ddi(struct drm_device *dev); |
c82e4d26 | 493 | extern void hsw_fdi_link_train(struct drm_crtc *crtc); |
0e72a5b5 | 494 | extern void intel_ddi_init(struct drm_device *dev, enum port port); |
d4270e57 | 495 | |
b840d907 | 496 | /* For use by IVB LP watermark workaround in intel_sprite.c */ |
f681fa23 | 497 | extern void intel_update_watermarks(struct drm_device *dev); |
b840d907 JB |
498 | extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, |
499 | uint32_t sprite_width, | |
500 | int pixel_size); | |
1f8eeabf ED |
501 | extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe, |
502 | struct drm_display_mode *mode); | |
8ea30864 JB |
503 | |
504 | extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data, | |
505 | struct drm_file *file_priv); | |
506 | extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data, | |
507 | struct drm_file *file_priv); | |
508 | ||
57f350b6 JB |
509 | extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg); |
510 | ||
85208be0 | 511 | /* Power-related functions, located in intel_pm.c */ |
1fa61106 | 512 | extern void intel_init_pm(struct drm_device *dev); |
85208be0 | 513 | /* FBC */ |
85208be0 ED |
514 | extern bool intel_fbc_enabled(struct drm_device *dev); |
515 | extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval); | |
516 | extern void intel_update_fbc(struct drm_device *dev); | |
eb48eb00 DV |
517 | /* IPS */ |
518 | extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv); | |
519 | extern void intel_gpu_ips_teardown(void); | |
85208be0 | 520 | |
0232e927 | 521 | extern void intel_init_power_wells(struct drm_device *dev); |
8090c6b9 DV |
522 | extern void intel_enable_gt_powersave(struct drm_device *dev); |
523 | extern void intel_disable_gt_powersave(struct drm_device *dev); | |
6590190d | 524 | extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv); |
930ebb46 | 525 | extern void ironlake_teardown_rc6(struct drm_device *dev); |
b3daeaef | 526 | |
5ab432ef DV |
527 | extern void intel_enable_ddi(struct intel_encoder *encoder); |
528 | extern void intel_disable_ddi(struct intel_encoder *encoder); | |
72662e10 ED |
529 | extern void intel_ddi_mode_set(struct drm_encoder *encoder, |
530 | struct drm_display_mode *mode, | |
531 | struct drm_display_mode *adjusted_mode); | |
532 | ||
79e53945 | 533 | #endif /* __INTEL_DRV_H__ */ |